WO2024070312A1 - 半導体装置および半導体モジュール - Google Patents

半導体装置および半導体モジュール Download PDF

Info

Publication number
WO2024070312A1
WO2024070312A1 PCT/JP2023/029800 JP2023029800W WO2024070312A1 WO 2024070312 A1 WO2024070312 A1 WO 2024070312A1 JP 2023029800 W JP2023029800 W JP 2023029800W WO 2024070312 A1 WO2024070312 A1 WO 2024070312A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring layer
layer
wiring
semiconductor
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/029800
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
耕作 足立
和真 西尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2024549864A priority Critical patent/JPWO2024070312A1/ja
Publication of WO2024070312A1 publication Critical patent/WO2024070312A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Definitions

  • This disclosure relates to semiconductor devices and semiconductor modules.
  • One example of a semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor resistor layer formed on the insulating layer (see, for example, Patent Document 1).
  • a semiconductor device that solves the above problem includes a substrate, an element insulating layer provided on the substrate, and a wiring layer provided on the element insulating layer, the wiring layer including a first wiring layer and a second wiring layer provided at a position different from the first wiring layer in the thickness direction of the element insulating layer and electrically connected to the first wiring layer, the first wiring layer including a first overlapping portion that overlaps with the second wiring layer when viewed from the thickness direction of the element insulating layer, and a first protruding portion that protrudes from the second wiring layer when viewed from the thickness direction of the element insulating layer.
  • the semiconductor module that solves the above problem includes the above semiconductor device, a support member that supports the semiconductor device, and a sealing resin that seals the semiconductor device and the support member.
  • the above semiconductor device and semiconductor module can improve the dielectric strength.
  • FIG. 1 is a schematic plan view of a semiconductor module according to a first embodiment.
  • FIG. 2 is a schematic plan view of a first chip and a second chip in the semiconductor module of FIG.
  • FIG. 3 is a schematic plan view of a semiconductor resistor layer in the first chip.
  • FIG. 4 is a plan view showing a part of the semiconductor resistor layer on the terminal side of the first chip and the planar structure of the periphery thereof.
  • FIG. 5 is a plan view showing a part of the semiconductor resistor layer on the opposite side to the terminals in the first chip and the planar structure of the periphery thereof.
  • FIG. 6 is a plan view showing another part of the semiconductor resistor layer on the terminal side of the first chip and the planar structure of the periphery thereof.
  • FIG. 7 is a plan view showing a planar structure of still another part of the semiconductor resistor layer on the terminal side of the first chip and its surrounding area.
  • FIG. 8 is a schematic cross-sectional view of a part of the semiconductor resistor layer and its periphery in the first chip.
  • FIG. 9 is a schematic cross-sectional view of the first chip taken along line F9-F9 in FIG.
  • FIG. 10 is a schematic cross-sectional view of the first chip taken along line F10-F10 in FIG. 11A to 11C are schematic cross-sectional views showing an example of a manufacturing process for the first chip of the first embodiment.
  • FIG. 12 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG.
  • FIG. 13 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 14 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 15 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 16 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 17 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 18 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 19 is a schematic cross-sectional view showing an example of a simulation result of the electric field intensity of the first chip of the first embodiment.
  • FIG. 20 is a schematic cross-sectional view showing an example of a simulation result of the electric field intensity of the first comparative example.
  • FIG. 20 is a schematic cross-sectional view showing an example of a simulation result of the electric field intensity of the first comparative example.
  • FIG. 21 is a schematic cross-sectional view showing an example of a simulation result of the electric field intensity of the second comparative example.
  • FIG. 22 is a graph showing the relationship between the first protrusion length of the first wiring layer and the electric field intensity.
  • FIG. 23 is a schematic cross-sectional view showing the positional relationship between the first wiring layer, the second wiring layer, and the semiconductor resistor layer in the first chip of the second embodiment.
  • FIG. 24 is a plan view showing a planar structure of a part of the semiconductor resistance layer on the terminal side of the first chip of the third embodiment and its periphery.
  • FIG. 25 is a plan view showing another part of the semiconductor resistance layer on the terminal side of the first chip of the third embodiment and the planar structure of the periphery thereof.
  • FIG. 26 is a plan view showing a planar structure of still another part of the semiconductor resistance layer on the terminal side of the first chip of the third embodiment and its periphery.
  • FIG. 27 is a schematic cross-sectional view of the first chip taken along line F27-F27 in FIG.
  • FIG. 28 is a schematic cross-sectional view showing an example of a simulation result of the electric field intensity of the first chip of the third embodiment.
  • FIG. 29 is a graph showing the relationship between the first protrusion length of the first wiring layer and the electric field intensity.
  • FIG. 30 is a schematic cross-sectional view of the first wiring layer and its periphery in the first chip of the fourth embodiment.
  • FIG. 31 is a circuit diagram illustrating a schematic circuit configuration of a semiconductor module according to the fifth embodiment.
  • FIG. 32 is a schematic cross-sectional view of a semiconductor module according to the fifth embodiment.
  • FIG. 33 is a schematic cross-sectional view of a first chip in a semiconductor module according to the fifth embodiment.
  • FIG. 34 is an enlarged cross-sectional view of the second coil and its periphery in FIG. 33.
  • FIG. 35 is a schematic cross-sectional view of a first chip of the modified example.
  • FIG. 1 shows a schematic diagram of the overall layout of the semiconductor module 10.
  • Figure 2 shows a schematic diagram of the electrical configuration and electrical connection structure of each of a first chip 14 and a second chip 15 of the semiconductor module 10, which will be described later. Note that in Figure 1, components inside a sealing resin 16, which will be described later, are shown by solid lines in order to facilitate understanding of the drawing. In Figure 2, components inside the first chip 14 and the second chip 15 are shown by solid lines in order to facilitate understanding of the drawing.
  • planar view refers to viewing the semiconductor module 10 in the Z direction of the mutually orthogonal XYZ axes shown in FIG. 4. Unless otherwise specified, “planar view” refers to viewing the semiconductor module 10 from above along the Z axis.
  • the semiconductor module 10 comprises a frame 11, a die pad 12, a plurality of leads 13A-13G (seven in the first embodiment), a first chip 14 mounted on the frame 11, a second chip 15 mounted on the die pad 12, wires W1-W11, and a sealing resin 16 that seals them.
  • the first chip 14 corresponds to the "semiconductor device" and the frame 11 corresponds to the "support member.”
  • the sealing resin 16 is formed, for example, in the shape of a rectangular flat plate with its thickness direction in the Z direction.
  • the sealing resin 16 has first to fourth sealing side surfaces 16A to 16D.
  • the sealing resin 16 is formed in a rectangular shape with the X direction being the longitudinal direction in a plan view and the Y direction being the lateral direction.
  • the first sealing side surface 16A and the second sealing side surface 16B form both end faces of the sealing resin 16 in the X direction
  • the third sealing side surface 16C and the fourth sealing side surface 16D form both end faces of the sealing resin 16 in the Y direction.
  • the shape of the sealing resin 16 in a plan view can be changed as desired.
  • the frame 11, die pad 12, and leads 13A to 13G are arranged at a distance from each other in the X direction.
  • the X direction is the arrangement direction of the frame 11, die pad 12, and leads 13A to 13G.
  • the arrangement direction of the frame 11, die pad 12, and leads 13A to 13G coincides with the longitudinal direction of the sealing resin 16. Therefore, it can be said that the frame 11, die pad 12, and leads 13A to 13G are arranged at a distance from each other in the longitudinal direction of the sealing resin 16.
  • the frame 11 is arranged near the first sealing side surface 16A with respect to the die pad 12.
  • the leads 13B to 13G are arranged near the second sealing side surface 16B with respect to the die pad 12.
  • Each of the frame 11, die pad 12, and leads 13A to 13G is formed of a metal material such as copper (Cu) or aluminum (Al).
  • the frame 11, the die pad 12, and the leads 13A to 13G are each formed from a thin metal plate.
  • the frame 11 is adapted to mount the first chip 14 and to be electrically connected to the first chip 14
  • the die pad 12 is adapted to mount the second chip 15
  • the leads 13B to 13G are adapted to be electrically connected to the second chip 15.
  • the frame 11 and the leads 13A to 13G are not limited to being thin metal plates, but may be any conductive layer.
  • the die pad 12 is not limited to being made of a conductive material such as a thin metal plate, but may be a plate material formed from an insulating material. In other words, the die pad 12 is only required to be a support member that supports the second chip 15.
  • the frame 11 includes a die pad portion 11 A and a lead portion 11 B.
  • the die pad portion 11 A and the lead portion 11 B are integrally formed.
  • the die pad portion 11A is a portion on which the first chip 14 is mounted, and supports the first chip 14.
  • the die pad portion 11A is disposed closer to the second sealing side surface 16B than the first sealing side surface 16A and spaced apart from it.
  • the die pad portion 11A is formed in a rectangular flat plate shape with the thickness direction being the Z direction.
  • the shape of the die pad portion 11A in a plan view is a rectangle with the Y direction being the longitudinal direction and the X direction being the lateral direction.
  • the die pad portion 11A is formed so that the arrangement direction of the frame 11, the die pad 12, and the leads 13A to 13G is the lateral direction. It can also be said that the die pad portion 11A is formed so that the longitudinal direction of the sealing resin 16 is the lateral direction.
  • the first chip 14 is mounted on the die pad portion 11A. More specifically, the first chip 14 is joined to the die pad portion 11A by a conductive bonding material such as solder paste, silver (Ag) paste, etc. It can also be said that the first chip 14 is die bonded to the die pad portion 11A. In this way, it can also be said that the first chip 14 is mounted on the frame 11.
  • a conductive bonding material such as solder paste, silver (Ag) paste, etc. It can also be said that the first chip 14 is die bonded to the die pad portion 11A. In this way, it can also be said that the first chip 14 is mounted on the frame 11.
  • the lead portion 11B is connected to a corner portion consisting of the end portion of the die pad portion 11A in the Y direction that is closer to the third sealing side surface 16C and the end portion of the die pad portion 11A in the X direction that is closer to the first sealing side surface 16A.
  • the lead portion 11B extends from the die pad portion 11A in the X direction toward the first sealing side surface 16A.
  • the configuration of the frame 11 can be changed as desired.
  • the die pad portion 11A and the lead portion 11B may be provided separately.
  • the die pad portion 11A and the lead portion 11B may be arranged at a distance from each other.
  • the die pad portion 11A is not limited to being a thin metal plate (conductive layer) and may be formed from an insulating material.
  • the die pad portion 11A may be any supporting member that supports the first chip 14.
  • the die pad 12 is the portion on which the second chip 15 is mounted, and supports the second chip 15.
  • the shape of the die pad 12 in a plan view is rectangular, with the Y direction being the long side and the X direction being the short side. Therefore, the long side of the die pad 12 coincides with the long side of the die pad portion 11A of the frame 11, and the short side of the die pad 12 coincides with the short side of the die pad portion 11A.
  • the die pad 12 is formed so that the arrangement direction of the frame 11, die pad 12, and leads 13A to 13G is the short side.
  • the second chip 15 is mounted on the die pad 12. More specifically, the second chip 15 is joined to the die pad 12 by a conductive bonding material such as solder paste, silver (Ag) paste, etc. It can also be said that the second chip 15 is die-bonded to the die pad 12.
  • a conductive bonding material such as solder paste, silver (Ag) paste, etc. It can also be said that the second chip 15 is die-bonded to the die pad 12.
  • Lead 13A and leads 13B to 13G are distributed and arranged at both ends of sealing resin 16 in the X direction. More specifically, lead 13A is arranged at the end closer to the first sealing side surface 16A of both ends of sealing resin 16 in the X direction. Each of leads 13B to 13G is arranged at the end closer to the second sealing side surface 16B of both ends of sealing resin 16 in the X direction. In the first embodiment, lead 13A is arranged at a position overlapping with the end closer to the fourth sealing side surface 16D of both ends of die pad portion 11A in the Y direction when viewed from the X direction. Lead 13A is arranged close to the first sealing side surface 16A relative to die pad portion 11A and separated from die pad portion 11A.
  • Each of the leads 13B to 13G are aligned in the X direction and spaced apart in the Y direction.
  • the leads 13B to 13G are arranged in the following order from the fourth sealing side 16D to the third sealing side 16C: lead 13B, lead 13C, lead 13D, lead 13E, lead 13F, and lead 13G.
  • the distance between lead 13A and lead portion 11B in the Y direction is greater than the distance between adjacent leads in the Y direction among the leads 13B to 13G.
  • the first chip 14 mounted on the die pad portion 11A is formed in the shape of a rectangular plate.
  • the shape of the first chip 14 is rectangular with the Y direction as the long side and the X direction as the short side.
  • the long side of the first chip 14 coincides with the long side of the die pad portion 11A
  • the short side of the first chip 14 coincides with the short side of the die pad portion 11A.
  • the first chip 14 is formed so that the arrangement direction of the frame 11, die pad 12, and leads 13A to 13G is the short side.
  • the first chip 14 includes a plurality of terminals P1 to P5.
  • the terminals P1 to P5 are formed so as to be exposed from the chip surface of the first chip 14.
  • the terminals P1 and P2 are provided on the end of the chip surface in the X direction that is closer to the first sealing side surface 16A.
  • the terminal P1 is provided on the chip surface near the lead 13A.
  • the terminal P2 is provided on the chip surface near the lead portion 11B.
  • the terminals P3 to P5 are provided on the end of the chip surface in the X direction that is closer to the second chip 15.
  • the terminals P3 to P5 are arranged at a distance from each other in the Y direction.
  • the second chip 15 mounted on the die pad 12 is formed in the shape of a rectangular plate.
  • the shape of the second chip 15 is rectangular with the Y direction as the long side and the X direction as the short side.
  • the long side of the second chip 15 coincides with the long side of the die pad 12
  • the short side of the second chip 15 coincides with the short side of the die pad 12.
  • the second chip 15 is formed so that the arrangement direction of the frame 11, die pad 12, and leads 13A to 13G is the short side.
  • the second chip 15 includes a plurality of terminals Q1 to Q9.
  • the plurality of terminals Q1 to Q9 are formed so as to be exposed from the chip surface of the second chip 15.
  • the terminals Q1 to Q3 are provided at the end of the chip surface in the X direction that is closer to the first chip 14.
  • the terminals Q1 to Q3 are arranged at a distance from each other in the Y direction.
  • the terminals Q4 to Q9 are provided at the end of the chip surface in the X direction that is closer to the second sealing side surface 16B.
  • the terminals Q4 to Q9 are arranged at a distance from each other in the Y direction.
  • Terminal P1 of the first chip 14 is electrically connected to lead 13A by wire W1.
  • Terminal P2 is electrically connected to lead portion 11B by wire W2.
  • High voltage generating unit VT is electrically connected to lead 13A and lead portion 11B.
  • High voltage generating unit VT is, for example, a DC power source.
  • the positive electrode of high voltage generating unit VT is electrically connected to lead 13A, and the negative electrode of high voltage generating unit VT is electrically connected to lead portion 11B.
  • Terminals P3 to P5 of the first chip 14 and terminals Q1 to Q3 of the second chip 15 are individually electrically connected by wires W3 to W5.
  • Terminals Q4 to Q9 are individually electrically connected to leads 13B to 13G by wires W6 to W11.
  • terminals P1 to P5 constitute high-voltage side terminals
  • terminals P3 to P5 constitute low-voltage side terminals.
  • the terminals electrically connected to the lead 13A and the lead portion 11B constitute the high-voltage side terminals
  • the terminals electrically connected to the second chip 15 constitute the low-voltage side terminals.
  • the die pad portion 11A of the frame 11 electrically connected to the high voltage generating unit VT constitutes the high voltage side die pad
  • the die pad 12 constitutes the low voltage side die pad. Therefore, the dielectric strength voltage between the terminals P3 to P5 and the substrate 30 (described later) of the first chip 14 is higher than the dielectric strength voltage between the terminals P1, P2 and the substrate 30. In one example, the dielectric strength voltage between the terminals P3 to P5 and the substrate 30 is approximately 3850V DC, and the dielectric strength voltage between the terminals P1, P2 and the substrate 30 is approximately 1400V DC.
  • the first chip 14 includes first to fourth resistor circuits 14A to 14D for stepping down the high voltage of the high voltage generating unit VT (see FIG. 1).
  • the first resistor circuit 14A has a resistance value RA
  • the second resistor circuit 14B has a resistance value RB
  • the third resistor circuit 14C has a resistance value RC
  • the fourth resistor circuit 14D has a resistance value RD.
  • the resistance value RB is smaller than the resistance value RA.
  • the ratio (RB/RA) of the resistance value RB to the resistance value RA is set in advance.
  • the resistance value RC is smaller than the resistance value RD.
  • the ratio (RC/RD) of the resistance value RC to the resistance value RD is set in advance.
  • the ratio (RB/RA) and the ratio (RC/RD) are set to the same predetermined value (for example, 1/999).
  • the first to fourth resistor circuits 14A to 14D are connected in series. Each of the first to fourth resistor circuits 14A to 14D has a first end and a second end. The first end of the first resistor circuit 14A is electrically connected to the terminal P1, and the second end of the first resistor circuit 14A is electrically connected to the first end of the second resistor circuit 14B. The connection point between the first resistor circuit 14A and the second resistor circuit 14B is electrically connected to the terminal P3. The second end of the second resistor circuit 14B is electrically connected to the first end of the third resistor circuit 14C. The connection point between the second resistor circuit 14B and the third resistor circuit 14C is electrically connected to the terminal P4.
  • the second end of the third resistor circuit 14C is electrically connected to the first end of the fourth resistor circuit 14D.
  • the connection point between the third resistor circuit 14C and the fourth resistor circuit 14D is electrically connected to the terminal P5.
  • the second end of the fourth resistor circuit 14D is electrically connected to the terminal P2.
  • the second chip 15 includes a voltage detection circuit 15A.
  • the voltage detection circuit 15A includes an operational amplifier.
  • the voltage detection circuit 15A is electrically connected to terminals Q1 to Q3.
  • the terminal Q1 is electrically connected to the terminal P3 of the first chip 14 by a wire W3
  • the terminal Q2 is electrically connected to the terminal P4 of the first chip 14 by a wire W4
  • the terminal Q3 is electrically connected to the terminal P5 of the first chip 14 by a wire W5. Therefore, the voltage detection circuit 15A detects the voltage between the connection point between the first resistor circuit 14A and the second resistor circuit 14B, the connection point between the second resistor circuit 14B and the third resistor circuit 14C, and the connection point between the third resistor circuit 14C and the fourth resistor circuit 14D.
  • the terminals Q4 to Q9 (leads 13B to 13G (see FIG. 1)) are used to supply a power supply voltage to the operational amplifier in the second chip 15 and to output the output signal of the voltage detection circuit 15
  • FIG. 3 shows a schematic planar structure of the first chip 14 including the first to fourth resistor circuits 14A to 14D (see FIG. 2) of the first chip 14. As shown in FIG. 2,
  • the first chip 14 includes a plurality of unit semiconductor resistance layers (hereinafter, "semiconductor resistance layers 20").
  • Each semiconductor resistance layer 20 extends along the X direction. In other words, each semiconductor resistance layer 20 extends in the short direction of the first chip 14.
  • the plurality of semiconductor resistance layers 20 are arranged spaced apart from one another in the Y direction while being aligned with one another in the X direction. In other words, the plurality of semiconductor resistance layers 20 are arranged spaced apart from one another in the longitudinal direction of the first chip 14.
  • the semiconductor resistance layers 20 correspond to "element configuration layers".
  • semiconductor resistance layer 20 arranged at the first end in the Y direction among the multiple semiconductor resistance layers 20 is referred to as “semiconductor resistance layer 20E1", and the semiconductor resistance layer 20 arranged at the second end opposite the first end in the Y direction among the multiple semiconductor resistance layers 20 is referred to as “semiconductor resistance layer 20E2".
  • a terminal P1 is electrically connected to the semiconductor resistance layer 20 adjacent to the semiconductor resistance layer 20E1 among the multiple semiconductor resistance layers 20. This semiconductor resistance layer 20 and terminal P1 are electrically connected by a wiring 21.
  • a terminal P2 is electrically connected to the semiconductor resistance layer 20 adjacent to the semiconductor resistance layer 20E2 among the multiple semiconductor resistance layers 20. This semiconductor resistance layer 20 and terminal P2 are electrically connected by a wiring 22.
  • each semiconductor resistance layer 20 includes a first resistance end RE1 and a second resistance end RE2.
  • the first resistance end RE1 is the end on the side where terminals P1, P2 are located, of both ends of each semiconductor resistance layer 20 in the X direction.
  • the second resistance end RE2 is the end on the opposite side to the side where terminals P1, P2 are located, of both ends of each semiconductor resistance layer 20 in the X direction.
  • the multiple semiconductor resistance layers 20 are used as components of the first to fourth resistance circuits 14A to 14D (see FIG. 2 for both).
  • the multiple semiconductor resistance layers 20 can be divided into multiple resistance regions in the Y direction, the first to fourth resistance regions R1 to R4.
  • the first resistance region R1 is a region including the semiconductor resistance layer 20E1 that constitutes the first end in the Y direction of the multiple semiconductor resistance layers 20, and the fourth resistance region R4 is a region including the semiconductor resistance layer 20E2 that constitutes the second end in the Y direction of the multiple semiconductor resistance layers 20.
  • the portion of the multiple semiconductor resistance layers 20 that is disposed between the first resistance region R1 and the fourth resistance region R4 in the Y direction is divided into the second resistance region R2 and the third resistance region R3.
  • the second resistance region R2 is a region adjacent to the first resistance region R1, and the third resistance region R3 is a region adjacent to the fourth resistance region R4. Therefore, the first to fourth resistance regions R1 to R4 are arranged in the order of resistance regions R1, R2, R3, and R4 from the first end to the second end of the multiple semiconductor resistance layers 20.
  • the first resistance region R1 is a region that constitutes the first resistance circuit 14A
  • the second resistance region R2 is a region that constitutes the second resistance circuit 14B
  • the third resistance region R3 is a region that constitutes the third resistance circuit 14C
  • the fourth resistance region R4 is a region that constitutes the fourth resistance circuit 14D.
  • the number of semiconductor resistance layers 20 in each of the first to fourth resistance regions R1 to R4 is set individually. In the first embodiment, the number of semiconductor resistance layers 20 in the first resistance region R1 and the fourth resistance region R4 is the same, and the number of semiconductor resistance layers 20 in the second resistance region R2 and the third resistance region R3 is the same. The number of each of the first resistance region R1 and the fourth resistance region R4 is greater than the number of each of the second resistance region R2 and the third resistance region R3.
  • the number of semiconductor resistance layers 20 in the first to fourth resistance regions R1 to R4 is not limited to that in the first embodiment, and can be changed as desired.
  • the multiple semiconductor resistance layers 20 are electrically connected alternately at the first resistance end RE1 and the second resistance end RE2, so that all of the multiple semiconductor resistance layers 20 except for the semiconductor resistance layers 20E1 and 20E2 are connected in series.
  • Each of the semiconductor resistance layers 20E1 and 20E2 of the multiple semiconductor resistance layers 20 is in an electrically floating state.
  • the six semiconductor resistance layers 20 from the first end semiconductor resistance layer 20E1 in the first resistance region R1 are electrically connected to each other at both the first resistance end RE1 and the second resistance end RE2.
  • the seventh semiconductor resistance layer 20 and the eighth semiconductor resistance layer 20 from the semiconductor resistance layer 20E1 are electrically connected at the first resistance end RE1, but are not electrically connected at the second resistance end RE2.
  • the sixth semiconductor resistance layer 20 and the seventh semiconductor resistance layer 20 from the semiconductor resistance layer 20E1 are electrically connected at the second resistance end RE2. Thereafter, such electrical connections of the semiconductor resistance layers 20 are repeated.
  • the six semiconductor resistance layers 20 from the semiconductor resistance layer 20E2 at the second end of the fourth resistance region R4 are electrically connected to each other at both the first resistance end RE1 and the second resistance end RE2.
  • the electrical connection mode of the multiple semiconductor resistance layers 20 in the fourth resistance region R4 is similar to that of the first resistance region R1, so a detailed description thereof will be omitted.
  • the terminal P3 is electrically connected to the first resistor end RE1 of the semiconductor resistor layer 20 at the end of the second resistor region R2 closer to the first resistor region R1.
  • the terminal P3 and the semiconductor resistor layer 20 are electrically connected by a wiring 23.
  • the terminal P4 is electrically connected to the first resistance end RE1 of the semiconductor resistance layer 20 at the end of the second resistance region R2 closer to the third resistance region R3, and to the first resistance end RE1 of the semiconductor resistance layer 20 at the end of the third resistance region R3 closer to the second resistance region R2.
  • the terminal P4 and the two semiconductor resistance layers 20 are electrically connected by wiring 24.
  • the terminal P5 is electrically connected to the first resistor end RE1 of the semiconductor resistor layer 20 at the end of the third resistor region R3 closer to the fourth resistor region R4.
  • the terminal P5 and the semiconductor resistor layer 20 are electrically connected by a wiring 25.
  • FIG. 4 shows an example of a planar structure in which the terminal P1 and its periphery are enlarged
  • FIG. 5 shows an example of a planar structure in which the second resistor end RE2 of the semiconductor resistor layer 20 in the first resistor region R1 and its periphery are enlarged
  • FIG. 6 shows an example of a planar structure in which the terminal P2 and its periphery are enlarged
  • FIG. 7 shows an example of a planar structure in which the terminals P3 to P5 and their periphery are enlarged. Note that FIG.
  • FIG. 3 is a simplified diagram of the planar structure of the first chip 14 for convenience, and may differ from the planar structure of the first chip 14 in FIGS. 4 to 7. Also, the double-dashed line frames in FIGS. 4, 6, and 7 indicate openings 43X in the passivation film 43, which will be described later.
  • the first chip 14 includes a wiring layer 70.
  • the wiring layer 70 is a conductive layer including the wirings 21 to 25 shown in Figure 3.
  • the wiring layer 70 includes a wiring layer for electrically connecting the semiconductor resistance layer 20 to the terminals P1 to P5 (see Figure 3).
  • the wiring layer 70 is made of one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W, as appropriate.
  • the wiring layer 70 is made of a material including Al.
  • the wiring layer 70 includes a first wiring layer 71 and a second wiring layer 72 electrically connected to the first wiring layer 71.
  • the wiring layer 70 also includes a plurality of vias 80 and a plurality of vias 81.
  • the second wiring layer 72 is electrically connected to the semiconductor resistance layer 20 by the vias 80.
  • the first wiring layer 71 is electrically connected to the second wiring layer 72 by the vias 81.
  • a plurality of first wiring layers 71 are provided, and a plurality of second wiring layers 72 are provided. The positional relationship in the Z direction between the semiconductor resistance layer 20, the first wiring layer 71, the second wiring layer 72, the vias 80, and the vias 81 will be described later.
  • the second wiring layer 72 constitutes part of a conductive path that electrically connects the semiconductor resistance layer 20 and the first wiring layer 71.
  • the multiple second wiring layers 72 include a second wiring layer 72A connected to the first resistance end RE1 of the semiconductor resistance layer 20, and a second wiring layer 72B connected to the second resistance end RE2 of the semiconductor resistance layer 20.
  • a plurality of second wiring layers 72A are provided, and a plurality of second wiring layers 72B are provided.
  • the plurality of second wiring layers 72A are arranged at the same positions in the X direction and spaced apart from each other in the Y direction.
  • the plurality of second wiring layers 72B are arranged at the same positions in the X direction and spaced apart from each other in the Y direction.
  • the second wiring layers 72A and the second wiring layers 72B are arranged with a partial shift in the Y direction.
  • Each second wiring layer 72A is disposed at a position overlapping the first resistor end RE1 of the semiconductor resistor layer 20 in a planar view. Each second wiring layer 72A extends from the position overlapping the first resistor end RE1 of the semiconductor resistor layer 20 in a planar view toward the opposite side to the second resistor end RE2 in the X direction.
  • the multiple second wiring layers 72A include end wiring layers 72EA (see Figures 4 and 6) arranged at both ends in the Y direction.
  • the end wiring layers 72EA are formed to overlap the semiconductor resistance layers 20E1 (20E2) and the six semiconductor resistance layers 20 in a plan view.
  • the shape of the end wiring layers 72EA in a plan view is rectangular with the X direction as the width direction (short side direction) and the Y direction as the length direction. In one example, the length in the Y direction of the end wiring layers 72EA is less than twice the width (length in the X direction) of the end wiring layers 72EA.
  • each second wiring layer 72A (hereinafter, "second wiring layer 72PA") except for the two end wiring layers 72EA is formed so as to overlap with both of the two semiconductor resistance layers 20 adjacent in the Y direction in a plan view. Therefore, the length in the Y direction of the end wiring layer 72EA is greater than the width (length in the Y direction) of each second wiring layer 72PA.
  • each second wiring layer 72PA constitutes part of a conductive path that electrically connects two semiconductor resistance layers 20 adjacent in the Y direction. It can also be said that the second wiring layer 72PA electrically connects two semiconductor resistance layers 20 adjacent in the Y direction. It can also be said that the second wiring layer 72PA is a wiring layer for electrically connecting two semiconductor resistance layers 20 adjacent in the Y direction.
  • Each second wiring layer 72PA is formed in a flat plate shape with the thickness direction being in the Z direction.
  • the thickness of the second wiring layer 72PA is thinner than the width of the second wiring layer 72PA (the length in the direction perpendicular to the extension direction of the second wiring layer 72PA in a plan view).
  • the shape of the second wiring layer 72PA in plan view is different from the shape of the end wiring layer 72EA, and is rectangular with the X direction being the longitudinal direction and the Y direction being the width direction (short side direction).
  • the length in the X direction of the second wiring layer 72PA is more than twice the width (length in the Y direction) of the second wiring layer 72PA.
  • the length in the X direction of the second wiring layer 72PA is four times or less the width of the second wiring layer 72PA.
  • the length in the X direction of the second wiring layer 72PA is about three times the width of the second wiring layer 72PA.
  • the semiconductor resistance layer 20 and the second wiring layer 72PA are connected by a plurality of vias 80.
  • the semiconductor resistance layer 20 and the end wiring layer 72EA are connected by a plurality of vias 80.
  • Each via 80 extends in the Z direction, which is the thickness direction of the element insulation layer 40.
  • the vias 80 are made of one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W, as appropriate. In the first embodiment, the vias 80 are made of a material containing W.
  • Each second wiring layer 72B is disposed at a position overlapping the second resistor end RE2 of the semiconductor resistor layer 20 in a planar view. Each second wiring layer 72B extends from the position overlapping the second resistor end RE2 of the semiconductor resistor layer 20 in a planar view toward the opposite side to the first resistor end RE1 in the X direction.
  • the second wiring layer 72B includes end wiring layers 72EB (see FIG. 5) arranged at both ends in the Y direction.
  • the end wiring layers 72EB are formed to overlap the seven semiconductor resistance layers 20, i.e., the semiconductor resistance layer 20E1 (20E2) and the six semiconductor resistance layers 20, in a plan view.
  • the shape of the end wiring layer 72EB in a plan view is rectangular, with the X direction being the width direction (short side direction) and the Y direction being the length direction.
  • the length in the Y direction of the end wiring layer 72EB is equal to or less than twice the width (length in the X direction) of the end wiring layer 72EB.
  • Each second wiring layer 72B (hereinafter, "second wiring layer 72PB") except for the two end wiring layers 72EB is formed so as to overlap with both of the two semiconductor resistance layers 20 adjacent in the Y direction in a plan view. Therefore, the length in the Y direction of the end wiring layer 72EB is greater than the width (length in the Y direction) of each second wiring layer 72PB.
  • the second wiring layer 72PB forms part of a conductive path that electrically connects two semiconductor resistance layers 20 adjacent in the Y direction. It can also be said that the second wiring layer 72PB electrically connects two semiconductor resistance layers 20 adjacent in the Y direction. It can also be said that the second wiring layer 72PB is a wiring layer for electrically connecting two semiconductor resistance layers 20 adjacent in the Y direction.
  • the second wiring layer 72PB is configured so that the position, size, and relationship between width and thickness in the Z direction are the same as those of the second wiring layer 72PA.
  • the end wiring layer 72EB is configured so that the position, size, and relationship between width and thickness in the Z direction are the same as those of the end wiring layer 72EA.
  • Each of the second wiring layer 72PB and the end wiring layer 72EB is electrically connected to the semiconductor resistance layer 20 by a plurality of vias 80, similar to the second wiring layer 72PA and the end wiring layer 72EA.
  • the position, size, and relationship between width and thickness in the Z direction of the second wiring layer 72PB can be changed arbitrarily.
  • the second wiring layer 72PB may be disposed at a different position in the Z direction from the second wiring layer 72PA.
  • the position, size, and relationship between width and thickness in the Z direction of the end wiring layer 72EB can be changed arbitrarily.
  • the end wiring layer 72EB may be disposed at a different position in the Z direction from the end wiring layer 72EA.
  • the first wiring layer 71 includes first wiring layers 71A to 71E electrically connected to the terminals P1 to P5.
  • the first wiring layers 71A to 71E are disposed at the same positions as one another in the Z direction. As shown in FIG. 4, the first wiring layer 71A constitutes a part of the conductive path electrically connecting the semiconductor resistance layer 20 and the terminal P1, that is, a part of the wiring 21.
  • the first wiring layer 71A can also be said to be a wiring layer for electrically connecting the semiconductor resistance layer 20 and the terminal P1.
  • the first wiring layer 71A is electrically connected to the terminal P1.
  • the first wiring layer 71A is electrically connected to the semiconductor resistance layer 20 through the second wiring layer 72A and the via 80.
  • the terminal P1 is formed integrally with the first wiring layer 71A. In other words, a part of the first wiring layer 71A constitutes the terminal P1.
  • the first wiring layer 71A includes a resistor cover portion 71AA extending along the X direction, a terminal configuration portion 71AB, and a wiring cover portion 71AC.
  • the resistor cover portion 71AA, the terminal configuration portion 71AB, and the wiring cover portion 71AC are integrally formed.
  • the resistor cover portion 71AA in plan view, covers the semiconductor resistance layer 20E1 that is the first end of the multiple semiconductor resistance layers 20. In one example, the resistor cover portion 71AA covers the entire upper surface of the semiconductor resistance layer 20E1. The length in the X direction of the resistor cover portion 71AA is longer than the length in the X direction of the semiconductor resistance layer 20E1. Therefore, the resistor cover portion 71AA has a portion that protrudes in the X direction from both ends in the X direction of the semiconductor resistance layer 20E1. The width (length in the Y direction) of the resistor cover portion 71AA is greater than the width (length in the Y direction) of the semiconductor resistance layer 20. Thus, in plan view, the resistor cover portion 71AA covers each side that constitutes the semiconductor resistance layer 20.
  • the terminal component 71AB is connected to the end of the resistor cover part 71AA in the X direction that is closer to the terminal P1.
  • the terminal component 71AB is formed in an L shape.
  • the terminal component 71AB includes a first portion extending from the resistor cover part 71AA in the X direction, and a second portion extending from the first portion in the Y direction.
  • the width of the first portion is greater than the width of the resistor cover part 71AA (size in the Y direction).
  • the first portion of the terminal component 71AB is provided at a position spaced apart from the semiconductor resistance layer 20 in the X direction in a plan view. On the other hand, the first portion of the terminal component 71AB is provided at a position overlapping with the end wiring layer 72EA in a plan view.
  • the second portion of the terminal component 71AB is provided at a position spaced apart from the semiconductor resistance layer 20 in the X direction.
  • the width (length in the X direction) of the second portion of the terminal component 71AB is greater than the width of the resistor cover portion 71AA.
  • a terminal P1 is configured at a position of the terminal component 71AB spaced apart from the resistor cover portion 71AA in the Y direction.
  • the terminal P1 is formed in the second portion of the terminal component 71AB.
  • the terminal component 71AB configures the terminal P1
  • the terminal component 71AB configures an "electrode pad.”
  • the terminal configuration portion 71AB overlaps a part of the second wiring layer 72PA adjacent to the end wiring layer 72EA in the Y direction in a plan view.
  • the terminal configuration portion 71AB and the end wiring layer 72EA are connected by a plurality of vias 81. This electrically connects the first wiring layer 71A and the end wiring layer 72EA.
  • Each via 81 extends in the Z direction.
  • the vias 81 are made of one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W, as appropriate.
  • the vias 81 are made of a material containing W.
  • the vias 81 are made of the same material as the vias 80. Note that the vias 81 may be made of a material different from that of the vias 80.
  • the wiring cover portion 71AC is provided at a position spaced apart from the semiconductor resistance layer 20 in the X direction.
  • the wiring cover portion 71AC extends along the Y direction.
  • the length of the wiring cover portion 71AC in the Y direction is shorter than the length of the terminal configuration portion 71AB (see FIG. 4) in the Y direction.
  • the width (length in the X direction) of the wiring cover portion 71AC is greater than the width of the resistance cover portion 71AA.
  • the width of the wiring cover portion 71AC is smaller than the width of the terminal configuration portion 71AB.
  • the wiring cover portion 71AC is disposed at a position overlapping with the end wiring layer 72EB in a plan view.
  • the wiring cover portion 71AC is formed so as to cover the entire end wiring layer 72EB in the X direction.
  • the length in the Y direction of the wiring cover portion 71AC is longer than the length in the Y direction of the end wiring layer 72EB.
  • the wiring cover portion 71AC is formed so as to overlap with a portion in the Y direction of the second wiring layer 72PB adjacent to the end wiring layer 72EB.
  • the wiring cover portion 71AC and the end wiring layer 72EB are connected by a plurality of vias 81. This electrically connects the first wiring layer 71A and the end wiring layer 72EB.
  • the number of vias 81 can be changed as desired.
  • the first wiring layer 71B constitutes part of the conductive path electrically connecting the semiconductor resistance layer 20 and the terminal P2, i.e., part of the wiring 22.
  • the first wiring layer 71B can also be said to be a wiring layer for electrically connecting the semiconductor resistance layer 20 and the terminal P2.
  • the first wiring layer 71B is electrically connected to the terminal P2.
  • the first wiring layer 71B is electrically connected to the semiconductor resistance layer 20 through the second wiring layer 72A and the via 80.
  • the terminal P2 is formed integrally with the first wiring layer 71B. In other words, a part of the first wiring layer 71B constitutes the terminal P2.
  • the shape of the first wiring layer 71B in a plan view is symmetrical to the first wiring layer 71A in the Y direction. Therefore, like the first wiring layer 71A, the first wiring layer 71B includes a resistor cover portion 71BA, a terminal configuration portion 71BB, and a wiring cover portion (not shown). In one example, the resistor cover portion 71BA, the terminal configuration portion 71BB, and the wiring cover portion are integrally formed.
  • the terminal configuration portion 71BB is disposed at a position overlapping the end wiring layer 72EA in a plan view.
  • the end wiring layer 72EA shown in FIG. 6 is formed so as to overlap both the semiconductor resistance layer 20E2 constituting the second end and the six semiconductor resistance layers 20 in a plan view.
  • the end wiring layer 72EA and the terminal configuration portion 71BB are connected by a plurality of vias 81. This electrically connects the end wiring layer 72EA and the first wiring layer 71B.
  • the end wiring layer 72EA and the six semiconductor resistance layers 20 adjacent to the semiconductor resistance layer 20E2 in the Y direction are connected by a plurality of vias 80. As a result, the six semiconductor resistance layers 20 and the end wiring layer 72EA are electrically connected to each other.
  • the first wiring layer 71C is disposed in a plan view at a distance from the semiconductor resistance layer 20 in the X direction.
  • the first wiring layer 71C constitutes part of the conductive path electrically connecting the semiconductor resistance layer 20 and the terminal P3, i.e., part of the wiring 23.
  • the first wiring layer 71C can also be said to be a wiring layer for electrically connecting the semiconductor resistance layer 20 and the terminal P3.
  • the first wiring layer 71C is electrically connected to the terminal P3.
  • the first wiring layer 71C is electrically connected to the semiconductor resistance layer 20 via the second wiring layer 72PA and the via 80.
  • the terminal P3 is formed integrally with the first wiring layer 71C. In other words, a part of the first wiring layer 71C constitutes the terminal P3.
  • the first wiring layer 71C is formed in an L-shape in a plan view. More specifically, the first wiring layer 71C includes a first portion 71CA extending in the X-direction and a second portion 71CB extending in the Y-direction from the first portion 71CA toward the terminal P4. The terminal P3 is formed in the second portion 71CB.
  • the first portion 71CA is formed so as to overlap with the second wiring layer 72PA in a plan view.
  • the first portion 71CA and the second wiring layer 72PA are connected by a plurality of vias 81. This electrically connects the first wiring layer 71C and the second wiring layer 72PA.
  • the width (size in the Y direction) of the first portion 71CA is larger than the width (size in the Y direction) of the second wiring layer 72PA. Therefore, in a plan view, the first portion 71CA protrudes on both sides in the Y direction from the second wiring layer 72PA.
  • the first portion 71CA is formed so as to overlap with a part of the second wiring layer 72PA adjacent in the Y direction to the second wiring layer 72PA corresponding to the first portion 71CA.
  • the first portion 71CA extends toward the opposite side of the semiconductor resistance layer 20 from the second wiring layer 72PA.
  • the second wiring layer 72PA corresponding to the first portion 71CA and the two semiconductor resistance layers 20 corresponding to this second wiring layer 72PA are connected by a plurality of vias 80. This electrically connects the second wiring layer 72PA and the semiconductor resistance layers 20.
  • the first wiring layer 71D is disposed at a distance from the semiconductor resistance layer 20 in the X direction in a plan view.
  • the first wiring layer 71D constitutes part of the conductive path electrically connecting the semiconductor resistance layer 20 and the terminal P4, i.e., part of the wiring 24.
  • the first wiring layer 71D can also be said to be a wiring layer for electrically connecting the semiconductor resistance layer 20 and the terminal P4.
  • the first wiring layer 71D is electrically connected to the terminal P4.
  • the first wiring layer 71D is electrically connected to the semiconductor resistance layer 20 via the second wiring layer 72A and the via 80.
  • the terminal P4 is formed integrally with the first wiring layer 71D. In other words, a part of the first wiring layer 71D constitutes the terminal P4.
  • the first wiring layer 71D is formed in a T-shape in a plan view. More specifically, the first wiring layer 71D includes a first portion 71DA extending in the X-direction and a second portion 71DB extending in the Y-direction from both ends of the first portion 71DA in the X-direction.
  • the terminal P4 is configured in the second portion 71DB.
  • the first portion 71DA is formed so as to overlap with the second wiring layer 72PA in a plan view.
  • the first portion 71DA and the second wiring layer 72PA are connected by a plurality of vias 81. This electrically connects the first wiring layer 71D and the second wiring layer 72PA.
  • the width (size in the Y direction) of the first portion 71DA is greater than the width (size in the Y direction) of the second wiring layer 72PA. Therefore, in a plan view, the first portion 71DA protrudes on both sides in the Y direction from the second wiring layer 72PA.
  • the first portion 71DA extends further toward the opposite side to the semiconductor resistance layer 20 than the second wiring layer 72PA.
  • the second wiring layer 72PA corresponding to the first portion 71DA and the two semiconductor resistance layers 20 corresponding to this second wiring layer 72PA are connected by a plurality of vias 80. This electrically connects the second wiring layer 72PA and the semiconductor resistance layers 20.
  • the first wiring layer 71E is disposed apart from the semiconductor resistance layer 20 in the X direction in a plan view.
  • the first wiring layer 71E constitutes part of the conductive path electrically connecting the semiconductor resistance layer 20 and the terminal P5, i.e., part of the wiring 25.
  • the first wiring layer 71E can also be said to be a wiring layer for electrically connecting the semiconductor resistance layer 20 and the terminal P5.
  • the first wiring layer 71E is electrically connected to the terminal P5.
  • the first wiring layer 71E is electrically connected to the semiconductor resistance layer 20 via the second wiring layer 72PA and the via 80.
  • the terminal P5 is formed integrally with the first wiring layer 71E. In other words, a part of the first wiring layer 71E constitutes the terminal P5.
  • the first wiring layer 71E is formed in an L-shape in a plan view. More specifically, the first wiring layer 71E includes a first portion 71EA extending in the X-direction and a second portion 71EB extending in the Y-direction from the first portion 71EA toward the terminal P4. The terminal P5 is formed in the second portion 71EB.
  • the arrangement and connection of the first wiring layer 71E to the second wiring layer 72A are similar to those of the first wiring layer 71C, and therefore will not be described in detail.
  • the first wiring layer 71 includes a first wiring layer 71F that is provided separately from the first wiring layers 71A to 71E.
  • a plurality of first wiring layers 71F are provided.
  • the plurality of first wiring layers 71F are disposed at positions between the first wiring layers 71A to 71E in the Y direction.
  • the plurality of first wiring layers 71F are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction.
  • the shape of the first wiring layer 71F in plan view is a rectangle with the width direction (short side direction) being the X direction and the length direction being the Y direction.
  • the width (length in the X direction) of the first wiring layer 71F is larger than the width (length in the X direction) of the second wiring layer 72PA.
  • the first wiring layer 71F is provided so as to overlap with a plurality of second wiring layers 72PA in the Y direction.
  • the first wiring layer 71F extends toward the opposite side of the semiconductor resistance layer 20 with respect to the second wiring layer 72PA in the X direction. In one example, as shown in FIG.
  • the first wiring layer 71F adjacent to the terminal configuration portion 71AB overlaps with a part of the second wiring layer 72PA adjacent to the end wiring layer 72EA in the Y direction.
  • the first wiring layer 71F is provided so as to overlap with three second wiring layers 72PA adjacent to each other in the Y direction.
  • the first wiring layer 71F and one of the multiple second wiring layers 72PA corresponding to the first wiring layer 71F are connected by multiple vias 81. This electrically connects the first wiring layer 71F and one of the multiple second wiring layers 72PA corresponding to the first wiring layer 71F.
  • the first wiring layer 71 includes a first wiring layer 71G provided near the second resistor end RE2 of the semiconductor resistance layer 20 in a plan view.
  • the first wiring layer 71G extends along the Y direction. That is, the shape of the first wiring layer 71G in a plan view is a rectangle with the X direction being the width direction (short side direction) and the Y direction being the length direction.
  • the width of the first wiring layer 71G is the same as the width of the first wiring layer 71F
  • the length of the first wiring layer 71G in the Y direction is the same as the length of the first wiring layer 71F in the Y direction.
  • the first wiring layer 71G extends toward the opposite side to the semiconductor resistance layer 20 in the X direction with respect to the second wiring layer 72B.
  • a plurality of first wiring layers 71G are provided.
  • the plurality of first wiring layers 71G are arranged at the same positions in the X direction and spaced apart from each other in the Y direction.
  • the first wiring layer 71G and one of the multiple second wiring layers 72PB corresponding to the first wiring layer 71G are connected by multiple vias 81. This electrically connects the first wiring layer 71G and one of the multiple second wiring layers 72PB corresponding to the first wiring layer 71G.
  • FIG. 8 shows a schematic cross-sectional structure of the first chip 14.
  • Figure 8 shows a cross-sectional structure obtained by cutting a region including four semiconductor resistance layers 20 adjacent in the Y direction in the first resistance region R1 in the YZ plane.
  • Figure 9 shows an example of a cross-sectional structure obtained by cutting the first chip 14 along line F9-F9 in Figure 3.
  • Figure 10 shows an example of a cross-sectional structure obtained by cutting the first chip 14 along line F10-F10 in Figure 3.
  • one or two vias 80 are provided for each semiconductor resistance layer 20, but in reality, as shown in Figures 4 to 7, many vias 80 are provided for one semiconductor resistance layer 20.
  • one via 81 is provided for each second wiring layer 72A (72B), but in reality, as shown in Figures 4 to 7, many vias 81 are provided for one second wiring layer 72A (72B).
  • the number of vias 80 and vias 81 can be changed arbitrarily.
  • first wiring layer 71 when describing matters common to the first wiring layers 71A to 71G, or when describing matters where it is not necessary to distinguish between the first wiring layers 71A to 71G, it may simply be referred to as the "first wiring layer 71.”
  • second wiring layer 72 when describing matters common to the second wiring layers 72A, 72B, or when describing matters where it is not necessary to distinguish between the second wiring layers 72A, 72B, it may simply be referred to as the "second wiring layer 72.”
  • the first chip 14 includes a substrate 30 and an element insulating layer 40 provided on the substrate 30 .
  • the substrate 30 is formed of, for example, a semiconductor substrate.
  • the substrate 30 is a semiconductor substrate formed of a material containing Si.
  • the substrate 30 may be a wide band gap semiconductor or a compound semiconductor.
  • the substrate 30 may be an insulating substrate formed of a material containing glass or a material containing ceramics such as alumina, instead of a semiconductor substrate.
  • the wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or more.
  • the wide bandgap semiconductor may be SiC (silicon carbide).
  • the compound semiconductor may be a III-V compound semiconductor.
  • the compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).
  • the element insulating layer 40 has an element front surface 41 and an element back surface 42 that face opposite each other in the Z direction.
  • the element back surface 42 is in contact with the substrate 30.
  • the element front surface 41 is the surface opposite the substrate 30 in the Z direction.
  • the Z direction corresponds to the "thickness direction of the element insulating layer.” Therefore, a planar view means "viewed from the thickness direction of the element insulating layer.”
  • a passivation film 43 is provided on the element insulating layer 40 . 8, the passivation film 43 is formed on the element surface 41 of the element insulating layer 40.
  • the passivation film 43 is a surface protection film for the first chip 14, and is formed of, for example, a material containing SiN.
  • the material constituting the passivation film 43 can be changed arbitrarily, and may be formed of, for example, a material containing SiO 2.
  • the passivation film 43 may also have a laminated structure of multiple films, and may be, for example, a laminated structure of a film formed of a material containing SiN and a film formed of a material containing SiO 2 .
  • the element insulating layer 40 includes a substrate-side insulating layer 50 provided on the substrate 30 , and a front-side insulating layer 60 laminated on the substrate-side insulating layer 50 .
  • the substrate-side insulating layer 50 is, for example, an insulating layer for improving the dielectric strength voltage of the first chip 14.
  • the substrate-side insulating layer 50 is an insulating layer including the element back surface 42 of the element insulating layer 40. In other words, the substrate-side insulating layer 50 is in contact with the substrate 30.
  • the substrate-side insulating layer 50 has a plurality of etching stopper films 51 and an interlayer insulating film 52 formed on the plurality of etching stopper films 51.
  • the plurality of etching stopper films 51 and the plurality of interlayer insulating films 52 are stacked alternately one by one in the Z direction.
  • the etching stopper film 51 is formed of a material including SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), etc. In the first embodiment, the etching stopper film 51 is formed of a material including SiN.
  • the interlayer insulating film 52 is an oxide film formed of a material containing SiO 2 (silicon oxide).
  • the thickness of the interlayer insulating film 52 is thicker than the thickness of the etching stopper film 51.
  • the etching stopper film 51 has a thickness of 50 nm or more and less than 1000 nm.
  • the interlayer insulating film 52 has a thickness of 500 nm or more and 5000 nm or less. In the first embodiment, the etching stopper film 51 has a thickness of about 300 nm, and the interlayer insulating film 52 has a thickness of about 2000 nm.
  • the ratio of the thickness of the etching stopper film 51 to the thickness of the interlayer insulating film 52 in the drawings is different from the actual ratio of the thickness of the etching stopper film 51 to the thickness of the interlayer insulating film 52.
  • the element insulating layer 40 is provided with a plurality of semiconductor resistance layers 20.
  • the plurality of semiconductor resistance layers 20 are provided on the substrate-side insulating layer 50.
  • the plurality of semiconductor resistance layers 20 are covered by the surface-side insulating layer 60.
  • the first chip 14 further includes the semiconductor resistance layer 20 provided on the substrate-side insulating layer 50, and the surface-side insulating layer 60 that covers the semiconductor resistance layer 20.
  • the multiple semiconductor resistance layers 20 provided on the substrate-side insulating layer 50 are arranged at the same position relative to one another in the Z direction.
  • Each semiconductor resistance layer 20 is arranged closer to the element surface 41 than the substrate-side insulating layer 50 and spaced apart from the substrate-side insulating layer 50.
  • a portion of the surface-side insulating layer 60 is interposed between each semiconductor resistance layer 20 and the substrate-side insulating layer 50 in the Z direction. For this reason, each semiconductor resistance layer 20 can be said to be embedded in the surface-side insulating layer 60.
  • the semiconductor resistance layer 20 is formed in a flat plate shape with the thickness direction being the Z direction.
  • the thickness of the semiconductor resistance layer 20 is thinner than the width (length in the X direction) of the semiconductor resistance layer 20.
  • the thickness of the semiconductor resistance layer 20 is, for example, 1 nm or more and 100 nm or less. In the first embodiment, the thickness of the semiconductor resistance layer 20 is about 2.5 nm.
  • the semiconductor resistance layer 20 is formed of a material containing, for example, CrSi (chromium silicon). Therefore, it can be said that the semiconductor resistance layer 20 has a thickness thinner than the interlayer insulating film 52.
  • the semiconductor resistance layer 20 may have a thickness thinner than the etching stopper film 51.
  • the wiring layer 70 is provided in the element insulating layer 40. More specifically, each first wiring layer 71 and each second wiring layer 72 is provided in the element insulating layer 40. In one example, each first wiring layer 71 and each second wiring layer 72 is provided in the front insulating layer 60.
  • the second wiring layer 72 is provided at a different position from the first wiring layer 71 in the Z direction.
  • the second wiring layer 72 is provided on the substrate-side insulating layer 50.
  • the second wiring layer 72 is in contact with the substrate-side insulating layer 50.
  • the second wiring layer 72A is in contact with the uppermost interlayer insulating film 52 of the substrate-side insulating layer 50.
  • the first wiring layer 71 is disposed at a distance from the substrate-side insulating layer 50 in the Z direction. In other words, the first wiring layer 71 is disposed closer to the element surface 41 of the element insulating layer 40 than the second wiring layer 72.
  • the second wiring layer 72 is provided at a different position in the Z direction from each semiconductor resistance layer 20.
  • each semiconductor resistance layer 20 is provided at a different position in the Z direction from the second wiring layer 72.
  • the second wiring layer 72 is disposed closer to the substrate 30 (see FIG. 4) than each semiconductor resistance layer 20 in the Z direction. Therefore, each semiconductor resistance layer 20 is disposed at a distance in the Z direction from the substrate-side insulating layer 50.
  • the second wiring layer 72 is disposed at a distance in the Z direction from each semiconductor resistance layer 20.
  • a part of the front-side insulating layer 60 is interposed between the second wiring layer 72A and each semiconductor resistance layer 20 in the Z direction.
  • the first wiring layer 71 is disposed on the opposite side of the semiconductor resistance layer 20 from the substrate 30 in the Z direction.
  • the first wiring layer 71 is disposed closer to the element surface 41 of the element insulating layer 40 than the semiconductor resistance layer 20 in the Z direction.
  • the first wiring layer 71 is disposed on the opposite side of the semiconductor resistance layer 20 from the second wiring layer 72 in the Z direction.
  • the second wiring layer 72 is disposed on the opposite side of the semiconductor resistance layer 20 from the first wiring layer 71. It can also be said that the second wiring layer 72 is disposed closer to the substrate 30 than the semiconductor resistance layer 20 in the Z direction.
  • the first distance D1 between the first wiring layer 71 and the semiconductor resistance layer 20 in the Z direction is smaller than the second distance D2 between the second wiring layer 72 and the semiconductor resistance layer 20 in the Z direction.
  • the first distance D1 is equal to or less than half the second distance D2. In this way, it can be said that the first wiring layer 71 is disposed closer to the semiconductor resistance layer 20 in the Z direction than the second wiring layer 72.
  • a part of the front-side insulating layer 60 is interposed between the first wiring layer 71 and the semiconductor resistance layer 20 in the Z direction.
  • a part of the front-side insulating layer 60 is interposed between the first wiring layer 71 and the second wiring layer 72 in the Z direction.
  • the thickness of the second wiring layer 72 is thicker than the thickness of the semiconductor resistance layer 20. On the other hand, the thickness of the second wiring layer 72 is thinner than the thickness of the interlayer insulating film 52.
  • the thicknesses of the multiple second wiring layers 72 are the same as each other. Therefore, the thickness of the second wiring layer 72A and the thickness of the second wiring layer 72B are the same as each other.
  • the first wiring layer 71 is formed in a flat plate shape with the thickness direction being the Z direction.
  • the thicknesses of the multiple first wiring layers 71 are the same as each other.
  • the thickness of the first wiring layer 71 is thinner than the width of the first wiring layer 71 (the length in a direction perpendicular to the direction in which the first wiring layer 71 extends in a plan view).
  • the thickness of the first wiring layer 71 is thicker than the thickness of the semiconductor resistance layer 20.
  • the thickness of the first wiring layer 71 is thicker than the thickness of the interlayer insulating film 52.
  • the first wiring layer 71 has a thickness thicker than the first distance D1.
  • the first wiring layer 71 has a thickness that is twice or more the first distance D1.
  • the first wiring layer 71 may have a thickness thicker than the second distance D2.
  • the first wiring layer 71 has a thickness greater than that of the second wiring layer 72. In one example, the thickness of the first wiring layer 71 is at least twice the thickness of the second wiring layer 72. In one example, the thickness of the first wiring layer 71 is at least three times the thickness of the second wiring layer 72. In one example, the thickness of the first wiring layer 71 is at least four times the thickness of the second wiring layer 72.
  • the thickness of the first wiring layer 71 can be changed as desired. In one example, the thickness of the first wiring layer 71 may be equal to or less than the first distance D1. In another example, the thickness of the first wiring layer 71 may be equal to or less than the thickness of the second wiring layer 72.
  • terminal P1 is provided on element insulating layer 40.
  • terminals P2 to P5 are also provided on element insulating layer 40.
  • terminals P1 to P5 are provided on front-side insulating layer 60.
  • Terminals P1 to P5 are made of one or more of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au (gold), Ag (silver), Cu (copper), Al (aluminum), Ni (nickel), Pd (palladium), and W (tungsten).
  • terminals P1 to P5 are made of a material containing Al.
  • Terminal P1 is covered by both the front-side insulating layer 60 and the passivation film 43. Meanwhile, the front-side insulating layer 60 and the passivation film 43 have openings 43X, 60X that expose terminal P1. The front-side insulating layer 60 and the passivation film 43 have openings 43X, 60X that expose terminals P2 to P5 (see Figures 6 and 7). For this reason, terminals P1 to P5 shown in Figures 4, 6, and 7 include exposed surfaces for connecting wires W1 to W5 (see Figure 1). In this way, terminals P1 to P5 form electrode pads.
  • the configuration of the first wiring layer 71, particularly the first wiring layers 71A, 71F, and 71G, and the configuration of the second wiring layer 72 will be described with reference to FIGS.
  • the end wiring layer 72EA of the second wiring layer 72A includes a second overlapping portion 75EA that overlaps with the semiconductor resistance layer 20 in a planar view, and a second protruding portion 76EA that protrudes from the semiconductor resistance layer 20 in a planar view.
  • the second overlapping portion 75EA is formed to overlap the semiconductor resistance layer 20E1 and each of the six semiconductor resistance layers 20 adjacent in the Y direction.
  • the second overlapping portion 75EA overlaps the semiconductor resistance layer 20E1 and the first resistance end portion RE1 of each of the six semiconductor resistance layers 20 adjacent in the Y direction.
  • the second overlapping portion 75EA constitutes the end portion closer to the semiconductor resistance layer 20 of both ends of the end wiring layer 72EA in the X direction.
  • the vias 80 are provided at positions that overlap both the second overlapping portion 75EA and the first resistor ends RE1 of six semiconductor resistor layers 20 adjacent in the Y direction in a plan view.
  • the vias 80 contact both the second overlapping portion 75EA and the first resistor ends RE1.
  • the second protruding portion 76EA extends in the X direction from the second overlapping portion 75EA away from the semiconductor resistance layer 20 in a plan view.
  • the second protruding portion 76EA is formed to overlap the terminal configuration portion 71AB of the first wiring layer 71A in a plan view.
  • the terminal component 71AB of the first wiring layer 71A includes a first overlapping portion 73BA that overlaps with the end wiring layer 72EA in a planar view, and a first protruding portion 74BA that protrudes from the end wiring layer 72EA in a planar view.
  • the first overlapping portion 73BA overlaps with the end wiring layer 72EA of the second wiring layer 72A in a planar view. More specifically, the first overlapping portion 73BA overlaps with the first end of the end wiring layer 72EA in the X direction that is closer to the terminal P1 in a planar view. The first overlapping portion 73BA overlaps with the entire first end of the end wiring layer 72EA in the Y direction in a planar view. For this reason, it can be said that the first overlapping portion 73BA covers the entire first end of the end wiring layer 72EA in the Y direction.
  • the first protruding portion 74BA extends in a direction away from the semiconductor resistance layer 20 from the first overlapping portion 73BA in a plan view.
  • the vias 81 are provided at positions overlapping both the first end of the end wiring layer 72EA and the first overlapping portion 73BA in a plan view. The vias 81 are in contact with both the first end of the end wiring layer 72EA and the first overlapping portion 73BA.
  • the end wiring layer 72EB of the second wiring layer 72B includes a second overlapping portion 75EB that overlaps with the semiconductor resistance layer 20 in a planar view, and a second protruding portion 76EB that protrudes from the semiconductor resistance layer 20 in a planar view.
  • the second overlapping portion 75EB is formed so as to overlap both of two semiconductor resistance layers 20 adjacent in the Y direction.
  • the second overlapping portion 75EB overlaps with the second resistance end portions RE2 of seven semiconductor resistance layers 20 adjacent in the Y direction.
  • the second overlapping portion 75EB constitutes the end portion closer to the semiconductor resistance layer 20 of both ends of the second wiring layer 72B in the X direction.
  • the second protruding portion 76EB extends along the X direction so as to move away from the second overlapping portion 75EB toward the semiconductor resistance layer 20 in a plan view.
  • the wiring cover portion 71AC of the first wiring layer 71A includes a first overlapping portion 73CA that overlaps with the end wiring layer 72EA in a planar view, and a first protruding portion 74CA that protrudes from the end wiring layer 72EB in a planar view.
  • the first overlapping portion 73CA overlaps with the end wiring layer 72EB of the second wiring layer 72B in a planar view. More specifically, the first overlapping portion 73CA overlaps with the first end of the end wiring layer 72EB in the X direction that is farther from the semiconductor resistance layer 20 in a planar view. The first overlapping portion 73CA overlaps with the entire first end of the end wiring layer 72EB in the Y direction in a planar view. For this reason, it can be said that the first overlapping portion 73CA covers the entire first end of the end wiring layer 72EB in the Y direction.
  • the first protruding portion 74CA extends from the first overlapping portion 73CA in a direction away from the semiconductor resistance layer 20 in a plan view.
  • the protruding length of the first protruding portion 74CA is longer than the first distance D1.
  • the protruding length of the first protruding portion 74CA is 1 ⁇ m or more and 10 ⁇ m or less.
  • the protruding length of the first protruding portion 74CA is shorter than the protruding length of the first protruding portion 74BA.
  • the protrusion length of the first protrusion portion 74CA can be defined as the distance in the X direction between the end face of the end wiring layer 72EB, which is farther from the semiconductor resistance layer 20, and the end face of the wiring cover portion 71AC, which is farther from the semiconductor resistance layer 20, in a plan view.
  • the protrusion length of the first protrusion portion 74CA can be changed arbitrarily.
  • the protrusion length of the first protrusion portion 74CA may be longer than 10 ⁇ m.
  • the protrusion length of the first protrusion portion 74CA may be less than or equal to the first distance D1.
  • the vias 81 are provided at positions that overlap both the first end of the end wiring layer 72EB and the first overlapping portion 73CA of the first wiring layer 71A in a plan view.
  • the vias 81 contact both the first end of the end wiring layer 72EB and the first overlapping portion 73CA.
  • the first wiring layer 71F includes a first overlapping portion 73F that overlaps with the second wiring layer 72PA in a planar view, and a first protruding portion 74F that protrudes from the second wiring layer 72PA in a planar view.
  • the second wiring layer 72A corresponding to the first wiring layer 71F includes a second overlapping portion 75A that overlaps with the semiconductor resistance layer 20 in a planar view, and a second protruding portion 76A that protrudes from the semiconductor resistance layer 20 in a planar view.
  • the first overlapping portion 73F overlaps with the first end of the second wiring layer 72PA that is closer to the terminal P1 in a plan view. As shown in FIG. 4, the first overlapping portion 73F overlaps with the entire Y direction of the first end of the second wiring layer 72PA at the center in the Y direction of the three second wiring layers 72PA adjacent in the Y direction. The first overlapping portion 73F overlaps with a part of the first end of the second wiring layer 72PA at both ends in the Y direction of the three second wiring layers 72PA adjacent in the Y direction.
  • the first protruding portion 74F extends from the first overlapping portion 73F in a direction away from the second wiring layer 72PA in a plan view.
  • the protruding length of the first protruding portion 74F is longer than the first distance D1 (see FIG. 9).
  • the protruding length of the first protruding portion 74F is 1 ⁇ m or more and 10 ⁇ m or less.
  • the protruding length of the first protruding portion 74F is shorter than the protruding length of the first protruding portion 74BA (see FIG. 9).
  • the protrusion length of the first protrusion portion 74F can be defined as the distance in the X direction between the end face of the second wiring layer 72PA that is closer to the terminal P1 and the end face of the first wiring layer 71F that is farther from the semiconductor resistance layer 20 in the X direction, in a plan view.
  • the protrusion length of the first protrusion portion 74F can be changed arbitrarily.
  • the protrusion length of the first protrusion portion 74F may be longer than 10 ⁇ m.
  • the protrusion length of the first protrusion portion 74F may be equal to or shorter than the first distance D1.
  • the vias 81 are provided at positions that overlap both the second wiring layer 72PA and the first overlapping portion 73F of the first wiring layer 71F in a plan view.
  • the vias 81 are in contact with both the second wiring layer 72PA and the first overlapping portion 73F.
  • the first wiring layer 71G includes a first overlapping portion 73G that overlaps with the second wiring layer 72PB in a plan view, and a first protruding portion 74G that protrudes from the second wiring layer 72B in a plan view.
  • the second wiring layer 72PB corresponding to the first wiring layer 71G includes a second overlapping portion 75B that overlaps with the semiconductor resistance layer 20 in a plan view, and a second protruding portion 76B that protrudes from the semiconductor resistance layer 20 in a plan view.
  • the configuration of the first wiring layer 71G and the connection structure with the multiple vias 80 are similar to those of the first wiring layer 71F, so detailed descriptions thereof will be omitted.
  • the first wiring layer 71B like the first wiring layer 71A, includes a first overlapping portion 73B that overlaps with the end wiring layer 72EA in a planar view, and a first protruding portion 74B that protrudes from the end wiring layer 72EA in a planar view.
  • the end wiring layer 72EA like the end wiring layer 72EA corresponding to the first wiring layer 71A, includes a second overlapping portion 75EA that overlaps with the semiconductor resistance layer 20 in a planar view, and a second protruding portion 76EA that protrudes from the semiconductor resistance layer 20 in a planar view.
  • the arrangement and connection structure of the first overlapping portion 73B, the first protruding portion 74B, the second overlapping portion 75EA, and the second protruding portion 76EA are similar to those of the first wiring layer 71A, so detailed description thereof will be omitted.
  • the first wiring layer 71C includes a first overlapping portion 73C that overlaps with the second wiring layer 72PA in a planar view, and a first protruding portion 74C that protrudes from the second wiring layer 72PA in a planar view.
  • the second wiring layer 72PA corresponding to the first wiring layer 71C includes a second overlapping portion 75A that overlaps with the semiconductor resistance layer 20 in a planar view, and a second protruding portion 76A that protrudes from the semiconductor resistance layer 20 in a planar view.
  • the arrangement and connection structure of the first overlapping portion 73C, the first protruding portion 74C, the second overlapping portion 75A, and the second protruding portion 76A are similar to those of the first wiring layer 71A, so detailed description thereof will be omitted.
  • the first wiring layer 71D includes a first overlapping portion 73D that overlaps with the second wiring layer 72PA in a planar view, and a first protruding portion 74D that protrudes from the second wiring layer 72PA in a planar view.
  • the second wiring layer 72PA corresponding to the first wiring layer 71D includes a second overlapping portion 75A that overlaps with the semiconductor resistance layer 20 in a planar view, and a second protruding portion 76A that protrudes from the semiconductor resistance layer 20 in a planar view.
  • the arrangement and connection structure of the first overlapping portion 73D, the first protruding portion 74D, the second overlapping portion 75A, and the second protruding portion 76A are similar to those of the first wiring layer 71A, so detailed description thereof will be omitted.
  • the arrangement and connection structure of the first overlapping portion 73E, the first protruding portion 74E, the second overlapping portion 75A, and the second protruding portion 76A are similar to those of the first wiring layer 71A, so detailed description thereof will be omitted.
  • the manufacturing method of the first chip 14 mainly includes the steps of preparing a substrate 830, forming a substrate-side insulating layer 850 on the substrate 830, forming a second wiring layer 72, forming a first surface-side insulating layer 861, forming a via 80, forming a semiconductor resistance layer 20, forming a second surface-side insulating layer 862, forming a via 81, forming the first wiring layer 71 and terminals P1 to P5, forming a third surface-side insulating layer 863, forming a passivation film 843, and singulating.
  • substrate 830 for example a Si substrate, is prepared.
  • substrate 830 is a component that constitutes substrate 30, for example a semiconductor wafer.
  • substrate 830 is configured to include multiple substrates 30.
  • a process of forming a substrate-side insulating layer 850 on the substrate 30 is carried out.
  • the substrate-side insulating layer 850 is formed on the substrate 30, for example, by CVD (chemical vapor deposition). More specifically, an etching stopper film 851 and an interlayer insulating film 852 are formed so as to be alternately stacked, for example, by CVD.
  • the substrate-side insulating layer 850 is an insulating layer that constitutes the substrate-side insulating layer 50.
  • the process of forming the second wiring layer 72 is performed after the process of forming the substrate-side insulating layer 850.
  • a metal film (not shown) which is the material film of the second wiring layer 72 is first formed on the substrate-side insulating layer 850 by, for example, a sputtering method.
  • the metal film is, for example, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W selected as appropriate.
  • the metal film is then patterned by, for example, lithography and etching to form the second wiring layer 72.
  • the first surface-side insulating layer 861 is formed on the substrate-side insulating layer 850 by, for example, CVD so as to cover the second wiring layer 72.
  • the first surface-side insulating layer 861 is an insulating layer that constitutes a part of the surface-side insulating layer 60.
  • the first surface-side insulating layer 861 is formed of a material containing, for example, SiO2 .
  • a via opening is formed, for example, by etching.
  • the via opening penetrates the first surface-side insulating layer 861 in the Z direction and exposes the second wiring layer 72.
  • a metal material is filled into the via opening, for example, by a sputtering method.
  • the metal material is, for example, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W, as appropriate. In this way, the via 80 is formed.
  • a resistance material film which is a material film of the semiconductor resistance layer 20 is formed on the first surface side insulating layer 861.
  • the resistance material film is formed over the entire first surface side insulating layer 861.
  • the resistance material film is then patterned by, for example, lithography and etching to form the semiconductor resistance layer 20.
  • the upper end of the via 80 is connected to the semiconductor resistance layer 20.
  • the second surface-side insulating layer 862 is formed on the first surface-side insulating layer 861 by, for example, CVD so as to cover the semiconductor resistance layer 20.
  • the second surface-side insulating layer 862 is an insulating layer that constitutes a part of the surface-side insulating layer 60.
  • the second surface-side insulating layer 862 is formed of a material containing, for example, SiO 2. Note that in FIG. 15, the interface between the first surface-side insulating layer 861 and the second surface-side insulating layer 862 is shown to facilitate understanding of the drawing.
  • a via opening is formed, for example, by etching.
  • the via opening penetrates both the first surface side insulating layer 861 and the second surface side insulating layer 862 in the Z direction and exposes the second wiring layer 72.
  • a metal material is filled into the via opening, for example, by a sputtering method.
  • the metal material is, for example, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W, as appropriate. In this way, the via 81 is formed.
  • a metal film (not shown) which is the material film of the first wiring layer 71 and the terminals P1 to P5 is first formed on the second surface-side insulating layer 862 by, for example, a sputtering method.
  • the metal film is, for example, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W, as appropriate.
  • the first wiring layer 71 and the terminals P1 to P5 are formed by patterning the metal film by, for example, lithography and etching. In this way, since the terminals P1 to P5 are included in the first wiring layer 71, the first wiring layer 71 and the terminals P1 to P5 are formed in the same process.
  • the third surface-side insulating layer 863 is formed on the second surface-side insulating layer 862 by, for example, CVD so as to cover the first wiring layer 71 and the terminals P1 to P5.
  • the third surface-side insulating layer 863 is an insulating layer that constitutes a part of the surface-side insulating layer 60.
  • the third surface-side insulating layer 863 is formed of a material that contains, for example, SiO2 . Note that in Fig. 17, the interface between the second surface-side insulating layer 862 and the third surface-side insulating layer 863 is shown to facilitate understanding of the drawing.
  • the surface-side insulating layer 860 that constitutes the surface-side insulating layer 60 is formed.
  • a portion of the third surface-side insulating layer 863 that covers the terminals P1 to P5 is removed, for example by etching. That is, a portion of the terminals P1 to P5 is exposed from the third surface-side insulating layer 863. It can also be said that an opening 860X that exposes the terminals P1 to P5 is formed in the surface-side insulating layer 860. In FIG. 17, the opening 860X that exposes the terminal P1 is shown. The opening 860X corresponds to the opening 60X.
  • a passivation material film which is a material film of the passivation film 843, is first formed, for example, on the third surface side insulating layer 863 and the terminals P1 to P5. Then, a part of the passivation material film covering the terminals P1 to P5 is removed, for example, by etching. In other words, a part of the terminals P1 to P5 is exposed from the passivation material film. It can also be said that an opening 843X that exposes the terminals P1 to P5 is formed in the passivation film 843. In this way, the passivation film 843 is formed.
  • the passivation film 843 is a film that constitutes the passivation film 43, and is formed of a material containing SiN, for example. Note that the opening 843X that exposes the terminal P1 is shown in FIG. 18. The opening 843X corresponds to the opening 43X.
  • the passivation film 843, the first to third surface-side insulating layers 861 to 863, the substrate-side insulating layer 850, and the substrate 830 are cut along the cutting lines CL in FIG. 18 using, for example, a dicing blade. This forms the passivation film 43, the surface-side insulating layer 60, the element insulating layer 40, and the substrate 30.
  • the first chip 14 is manufactured.
  • FIGS. Fig. 19 shows the results of a simulation of electric field strength modeled on the first wiring layer 71, the second wiring layer 72, the vias 80 and 81, and the semiconductor resistance layer 20 of the first embodiment.
  • Fig. 20 shows the results of a simulation of electric field strength modeled on the structure of the first comparative example.
  • Fig. 21 shows the results of a simulation of electric field strength modeled on the structure of the second comparative example. Note that the intensity of the electric field strength is indicated by the shade of the dots in Figs. 19 to 21. In other words, the darker the dots in Figs. 19 to 21, the higher the electric field strength.
  • the first comparative example shown in FIG. 20 is a configuration in which the first wiring layer 71 and the via 81 are omitted from the first embodiment.
  • electric field concentration occurs at each corner portion of the first end C1 and the second end C2 of the second wiring layer 72 in the X direction.
  • electric field concentration occurs significantly at the corner portion of the first end C1 of the second wiring layer 72.
  • the first end C1 of the second wiring layer 72 is the end opposite the semiconductor resistance layer 20 in the X direction, among both ends of the second wiring layer 72 in the X direction.
  • the second end C2 of the second wiring layer 72 is the end in the direction in which the semiconductor resistance layer 20 extends, among both ends of the second wiring layer 72 in the X direction.
  • the cause of this electric field concentration at the first end C1 is thought to be that the equipotential lines shown by solid lines wrap around from the first end C1 of the second wiring layer 72 to above the semiconductor resistance layer 20, causing the equipotential lines to bend sharply at the corner portion of the first end C1, narrowing the spacing between the equipotential lines.
  • the semiconductor resistance layer 20 includes a protruding portion 20P that protrudes in the X direction beyond the second wiring layer 72, as in the second comparative example.
  • the semiconductor resistance layer 20 includes a protruding portion that protrudes from the second wiring layer 72 to the side opposite the second end C2 in the X direction.
  • the protruding portion 20P makes the equipotential lines at the first end C1 of the second wiring layer 72 curve more gently, thereby mitigating the electric field concentration at the first end C1.
  • the equipotential lines bend around the tip of the protrusion 20P.
  • the equipotential lines bend sharply at the tip of the protrusion 20P, narrowing the spacing between the equipotential lines, i.e., causing electric field concentration.
  • the first wiring layer 71 is provided so as to protrude from the second wiring layer 72 in the X direction in a plan view.
  • the thickness of the first wiring layer 71 is greater than the thicknesses of the semiconductor resistance layer 20 and the second wiring layer 72.
  • the first wiring layer 71 makes the equipotential lines at the first end C1 of the second wiring layer 72 curve more gently, so that electric field concentration at the first end C1 is alleviated.
  • the equipotential lines curve more gently. This makes it possible to suppress the occurrence of electric field concentration in the first wiring layer 71.
  • FIG. 22 is a graph showing the relationship between the first protrusion length and the electric field strength.
  • the first protrusion length is the length by which the first wiring layer 71 protrudes from the second wiring layer 72 in the X-direction in a plan view.
  • FIG. 22 shows the electric field strength when the first protrusion length is changed from 1 ⁇ m to 10 ⁇ m.
  • “none" is the first comparative example, a configuration in which the first wiring layer 71 is omitted.
  • the dashed line graph in FIG. 22 shows the electric field strength in the second wiring layer 72, and the solid line graph shows the electric field strength in the first wiring layer 71.
  • the first comparative example does not include the first wiring layer 71, so the electric field strength in the first wiring layer 71 is "0."
  • the electric field strength in the second wiring layer 72 is large in the first comparative example.
  • the electric field strength in the second wiring layer 72 is smaller than that in the first comparative example. And, as shown in the dashed line graph in FIG. 22, the electric field strength in the second wiring layer 72 decreases as the first protrusion length increases.
  • the electric field strength in the first wiring layer 71 increases as the first protrusion length increases in the range of 1 ⁇ m to 4 ⁇ m, but the electric field strength in the first wiring layer 71 is smaller than the electric field strength in the second wiring layer 72 of the first comparative example. Also, the electric field strength in the first wiring layer 71 decreases as the first protrusion length increases in the range of 4 ⁇ m to 10 ⁇ m. Thus, it can be seen that the electric field strength in the second wiring layer 72 is smaller than that in the first comparative example when the first protrusion length is in the range of 1 ⁇ m or more and 10 ⁇ m or less.
  • the wiring layer 70 includes a first wiring layer 71F and a second wiring layer 72PA provided at a position different from the first wiring layer 71F in the Z direction and electrically connected to the first wiring layer 71F.
  • the first wiring layer 71F includes a first overlapping portion 73F that overlaps with the second wiring layer 72PA in a plan view, and a first protruding portion 74F that protrudes from the second wiring layer 72PA in a plan view.
  • the first protruding portion 74F reduces the abrupt bending of the equipotential lines in the second wiring layer 72PA, which is caused by the equipotential lines wrapping around the second wiring layer 72PA. This reduces electric field concentration in the second wiring layer 72PA. Similarly, the electric field concentration in the second wiring layer 72PA (end wiring layer 72EA) can be reduced for the first wiring layers 71A-71E, 71G.
  • the first wiring layer 71 is thicker than the second wiring layer 72 . According to this configuration, the equipotential lines are less likely to deviate via the second wiring layer 72 and the first wiring layer 71, and thus abrupt bending of the equipotential lines is mitigated. Therefore, it is possible to mitigate both the electric field concentration in the second wiring layer 72 and the electric field concentration in the first wiring layer 71.
  • the first wiring layer 71 is disposed on the opposite side of the semiconductor resistance layer 20 from the substrate 30 in the Z direction.
  • the second wiring layer 72 is disposed closer to the substrate 30 than the semiconductor resistance layer 20 in the Z direction.
  • the first distance D1 between the first wiring layer 71 and the semiconductor resistance layer 20 in the Z direction is smaller than the second distance D2 between the second wiring layer 72 and the semiconductor resistance layer 20 in the Z direction.
  • the equipotential lines below the second wiring layer 72 wrap around the first wiring layer 71 via the first protruding portion of the first wiring layer 71. This reduces the sharp bending of the equipotential lines, thereby reducing the electric field concentration in the second wiring layer 72.
  • the protruding length of the first protruding portion 74F of the first wiring layer 71F is longer than the first distance D1.
  • This configuration can reduce electric field concentration in the second wiring layer 72, as compared with the configuration not including the first wiring layer 71 such as the first comparative example. Note that a similar effect can be obtained by making the first protruding length of the first protruding portion 74G of the first wiring layer 71G longer than the first distance D1.
  • the protruding length of the first protruding portion 74F of the first wiring layer 71F is not less than 1 ⁇ m and not more than 10 ⁇ m.
  • This configuration can reduce electric field concentration in the second wiring layer 72, as compared with a configuration not including the first wiring layer 71 such as the first comparative example. Note that a similar effect can be obtained by setting the first protrusion length of the first protrusion portion 74G of the first wiring layer 71G to be 1 ⁇ m or more and 10 ⁇ m or less.
  • the first wiring layer 71 has a thickness greater than the first distance D1. According to this configuration, since equipotential lines are less likely to wrap around the first wiring layer 71, electric field concentration in the second wiring layer 72 can be alleviated.
  • the first wiring layer 71 is disposed in the same position in the Z direction as the terminals P1 to P5 that constitute the electrode pads. According to this configuration, the first wiring layer 71 and the terminals P1 to P5 can be formed in the same process, thereby simplifying the manufacturing process of the first chip 14. Therefore, the first chip 14 can be manufactured easily.
  • a semiconductor module 10 according to a second embodiment will be described with reference to Fig. 23.
  • the semiconductor module 10 according to the second embodiment differs from the semiconductor module 10 according to the first embodiment mainly in the positional relationship between the semiconductor resistance layer 20 and the second wiring layer 72.
  • differences from the first embodiment will be described in detail, and components common to the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.
  • the first wiring layer 71 is disposed on the opposite side of the semiconductor resistance layer 20 from the substrate 30 (see FIG. 4) in the Z direction, as in the first embodiment.
  • the second wiring layer 72 is disposed between the first wiring layer 71 and the semiconductor resistance layer 20 in the Z direction.
  • the second wiring layer 72 is disposed on the opposite side of the semiconductor resistance layer 20 from the substrate 30 in the Z direction. It can also be said that the semiconductor resistance layer 20 is disposed closer to the substrate 30 than the second wiring layer 72 in the Z direction.
  • the semiconductor resistance layer 20 is provided on the substrate-side insulating layer 50. More specifically, the semiconductor resistance layer 20 is provided on the uppermost interlayer insulating film 52 of the substrate-side insulating layer 50. The semiconductor resistance layer 20 is in contact with the substrate-side insulating layer 50. The semiconductor resistance layer 20 is in contact with the uppermost interlayer insulating film 52 of the substrate-side insulating layer 50.
  • the second wiring layer 72 is disposed closer to the element surface 41 of the element insulating layer 40 than the substrate-side insulating layer 50. Therefore, a part of the surface-side insulating layer 60 is interposed between the second wiring layer 72 and the substrate-side insulating layer 50 in the Z direction. Furthermore, the second wiring layer 72 is disposed away from the semiconductor resistance layer 20 in the Z direction. Therefore, a part of the surface-side insulating layer 60 is interposed between the second wiring layer 72 and the semiconductor resistance layer 20 in the Z direction. Furthermore, the second wiring layer 72 is disposed away from the first wiring layer 71 in the Z direction. Therefore, a part of the surface-side insulating layer 60 is interposed between the second wiring layer 72 and the first wiring layer 71 in the Z direction.
  • the end wiring layer 72EA of the second wiring layer 72A includes the second overlapping portion 75EA and the second protruding portion 76EA, as in the first embodiment.
  • the terminal configuration portion 71AB of the first wiring layer 71A includes the first overlapping portion 73BA and the first protruding portion 74BA, as in the first embodiment.
  • the end wiring layer 72EB of the second wiring layer 72B includes the second overlapping portion 75EB and the second protruding portion 76EB, as in the first embodiment.
  • the wiring cover portion 71AC of the first wiring layer 71A includes the first overlapping portion 73CA and the first protruding portion 74CA, as in the first embodiment.
  • the configurations of the second wiring layers 72PA, 72PB and the first wiring layers 71B to 71G are also the same as in the first embodiment. Therefore, the second embodiment can achieve the same effects as the first embodiment.
  • a semiconductor module 10 of the third embodiment will be described with reference to Figures 24 to 29.
  • the semiconductor module 10 of the third embodiment differs from the semiconductor module 10 of the first embodiment mainly in the shape of the second wiring layer 72A.
  • differences from the first embodiment will be described in detail, and components common to the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.
  • the second wiring layer 72A includes connection wiring layers 72AA to 72AE for electrically connecting to the terminals P1 to P5.
  • the connection wiring layer 72AA is a wiring layer for electrically connecting to the terminal P1, and is provided at a position overlapping the first wiring layer 71A in a planar view.
  • the connection wiring layer 72AA is formed to have a shape similar to that of the first wiring layer 71A in a planar view.
  • the width of the connection wiring layer 72AA is narrower than the width of the first wiring layer 71A.
  • the width of the connection wiring layer 72AA is the size in a direction perpendicular to the direction in which the connection wiring layer 72AA extends in a planar view.
  • connection wiring layer 72AA includes a first end 72A1 and a second end 72A2 as both ends in the direction in which the connection wiring layer 72AA extends in a plan view.
  • the first end 72A1 is the end of the connection wiring layer 72AA that is closer to the semiconductor resistance layer 20, and the second end 72A2 is the end that is farther from the semiconductor resistance layer 20.
  • the first end 72A1 of the connection wiring layer 72AA is electrically connected to six semiconductor resistance layers 20 adjacent in the Y direction by a plurality of vias 80.
  • the first end 72A1 of the connection wiring layer 72AA is provided at a position overlapping the first resistance end RE1 of the six semiconductor resistance layers 20 adjacent in the Y direction.
  • the connection wiring layer 72AA includes a first portion extending in the X direction from the first end 72A1 and a second portion extending in the Y direction from the first portion.
  • the width (size in the Y direction) of the first portion is smaller than the size in the Y direction of the first end 72A1 of the connection wiring layer 72AA.
  • the first portion is provided at a position overlapping with the end of the resistor cover portion 71AA of the first wiring layer 71A closer to the terminal configuration portion 71AB in a plan view.
  • the width of the first portion is smaller than the width of the resistor cover portion 71AA.
  • the second portion is provided at a position overlapping with the terminal configuration portion 71AB in a plan view.
  • the width of the second portion (size in the X direction) is smaller than the width of the terminal component 71AB.
  • connection wiring layer 72AA is provided at a position overlapping with the terminal P1 in a plan view. In other words, the second end is included in the second portion of the connection wiring layer 72AA.
  • the connection wiring layer 72AA is electrically connected to the terminal P1 at the second end 72A2 by a plurality of vias 81.
  • connection wiring layer 72AB is a wiring layer for electrically connecting to the terminal P2, and is provided at a position overlapping the first wiring layer 71B in a planar view.
  • the connection wiring layer 72AB is formed to have the same shape as the first wiring layer 71B in a planar view.
  • the width of the connection wiring layer 72AB is narrower than the width of the first wiring layer 71B.
  • the width of the connection wiring layer 72AB is the size in the direction perpendicular to the direction in which the connection wiring layer 72AB extends in a planar view.
  • the connection wiring layer 72AB includes a first end 72B1 and a second end 72B2.
  • the first end 72B1 of the connection wiring layer 72AB is electrically connected to six semiconductor resistance layers 20 adjacent in the Y direction by a plurality of vias 80.
  • the first end 72B1 of the connection wiring layer 72AB is provided at a position overlapping the first resistance end RE1 of the six semiconductor resistance layers 20 adjacent in the Y direction.
  • the connection wiring layer 72AB has a symmetrical shape in the Y direction to the connection wiring layer 72AA. For this reason, a detailed description of the configuration of the connection wiring layer 72AB will be omitted.
  • the second end 72B2 of the connection wiring layer 72AB is provided at a position overlapping with the terminal P2 in a plan view.
  • the connection wiring layer 72AB is electrically connected to the terminal P2 at the second end 72B2 by a plurality of vias 81.
  • the connection wiring layer 72AC is a wiring layer for electrically connecting to the terminal P3, and is provided at a position overlapping the first wiring layer 71C in a planar view.
  • the connection wiring layer 72AC is formed to have a shape similar to that of the first wiring layer 71C in a planar view.
  • the width of the connection wiring layer 72AC is narrower than the width of the first wiring layer 71C.
  • the width of the connection wiring layer 72AC is the size in a direction perpendicular to the direction in which the connection wiring layer 72AC extends in a planar view.
  • connection wiring layer 72AC includes a first end 72C1 and a second end 72C2 as both ends in the direction in which the connection wiring layer 72AC extends in a plan view.
  • the first end 72C1 is the end of the connection wiring layer 72AC that is closer to the semiconductor resistance layer 20, and the second end 72C2 is the end that is farther from the semiconductor resistance layer 20.
  • the first end 72C1 of the connection wiring layer 72AC is electrically connected to two semiconductor resistance layers 20 adjacent in the Y direction by a plurality of vias 80.
  • the first end 72C1 of the connection wiring layer 72AC is provided at a position overlapping the first resistance end RE1 of the two semiconductor resistance layers 20 adjacent in the Y direction.
  • the connection wiring layer 72AC includes a first portion extending in the X direction from the first end 72C1, and a second portion extending in the Y direction from the first portion.
  • the connection wiring layer 72AC has a constant width.
  • connection wiring layer 72AC The second end 72C2 of the connection wiring layer 72AC is provided at a position overlapping with the terminal P3 in a plan view. In other words, the second portion is included in the second portion of the connection wiring layer 72AC.
  • the connection wiring layer 72AC is electrically connected to the terminal P3 at the second end 72C2 by a plurality of vias 81.
  • the connection wiring layer 72AD is a wiring layer for electrically connecting to the terminal P4, and is provided at a position overlapping the first wiring layer 71D in a planar view.
  • the connection wiring layer 72AD is formed to have a shape similar to that of the first wiring layer 71D in a planar view.
  • the width of the connection wiring layer 72AD is narrower than the width of the first wiring layer 71D.
  • the width of the connection wiring layer 72AD is the size in a direction perpendicular to the direction in which the connection wiring layer 72AD extends in a planar view.
  • connection wiring layer 72AD includes a first end 72D1 and a second end 72D2 as both ends in the direction in which the connection wiring layer 72AD extends in a plan view.
  • the first end 72D1 is the end of the connection wiring layer 72AD that is closer to the semiconductor resistance layer 20, and the second end 72D2 is the end that is farther from the semiconductor resistance layer 20.
  • the first end 72D1 of the connection wiring layer 72AD is electrically connected to two semiconductor resistance layers 20 adjacent in the Y direction by a plurality of vias 80.
  • the first end 72D1 of the connection wiring layer 72AD is provided at a position overlapping the first resistance end RE1 of the two semiconductor resistance layers 20 adjacent in the Y direction.
  • the connection wiring layer 72AC has a constant width.
  • connection wiring layer 72AD The second end 72D2 of the connection wiring layer 72AD is provided at a position overlapping with the terminal P4 in a plan view. In other words, the second end 72D2 is included in the second and third parts of the connection wiring layer 72AD.
  • the connection wiring layer 72AD is electrically connected to the terminal P4 at the second end 72D2 by a plurality of vias 81.
  • the connection wiring layer 72AE is a wiring layer for electrically connecting to the terminal P5, and is provided at a position overlapping the first wiring layer 71E in a planar view.
  • the connection wiring layer 72AE is formed to have the same shape as the first wiring layer 71E in a planar view.
  • the width of the connection wiring layer 72AE is narrower than the width of the first wiring layer 71E.
  • the width of the connection wiring layer 72AE is the size in the direction perpendicular to the direction in which the connection wiring layer 72AE extends in a planar view.
  • the connection wiring layer 72AE includes a first end 72E1 and a second end 72E2.
  • the first end 72E1 of the connection wiring layer 72AE is electrically connected to two semiconductor resistance layers 20 adjacent in the Y direction by a plurality of vias 80.
  • the first end 72E1 of the connection wiring layer 72AE is provided at a position overlapping the first resistance end RE1 of the two semiconductor resistance layers 20 adjacent in the Y direction.
  • the connection wiring layer 72AE has a symmetrical shape in the Y direction to the connection wiring layer 72AC. For this reason, a detailed description of the configuration of the connection wiring layer 72AE is omitted.
  • the second end 72E2 of the connection wiring layer 72AE is provided at a position overlapping the terminal P5 in a plan view.
  • the connection wiring layer 72AE is electrically connected to the terminal P5 at the second end 72E2 by a plurality of vias 81.
  • Fig. 27 shows a cross-sectional structure of the wiring 21 and its periphery in the first chip 14 cut in the YZ plane.
  • Fig. 27 shows the connection structure between the connection wiring layer 72AA and the first wiring layer 71A. Note that the connection structure between the connection wiring layers 72AB to 72AE and the first wiring layers 71B to 71E is similar to the connection structure between the connection wiring layer 72AA and the first wiring layer 71A, so a description thereof will be omitted.
  • the first wiring layer 71A includes a first overlapping portion 73AA that overlaps with the connection wiring layer 72AA of the second wiring layer 72A in a planar view, and a first protruding portion 74AA that protrudes from the connection wiring layer 72AA in a planar view.
  • the first overlapping portion 73AA is formed so as to overlap the entire width of the connection wiring layer 72AA. Therefore, in a plan view, it can be said that the first wiring layer 71A covers the entire connection wiring layer 72AA.
  • the first protruding portion 74AA is formed so as to protrude from both sides of the connection wiring layer 72AA in the width direction.
  • the protruding length of the portion of the first protruding portion 74AA that protrudes from one side of the connection wiring layer 72AA in the width direction is 1 ⁇ m or more and 10 ⁇ m or less.
  • a first protrusion length of a portion of the first protrusion portion 74AA that protrudes from a first direction in the width direction of the connection wiring layer 72AA and a second protrusion length of a portion that protrudes from a second direction opposite to the first direction in the width direction of the connection wiring layer 72AA are equal to each other.
  • the first protrusion length and the second protrusion length can be set separately. Therefore, the first protrusion length and the second protrusion length may be different from each other. Also, at least one of the first protrusion length and the second protrusion length may be longer than 10 ⁇ m.
  • Fig. 28 shows a simulation result of the electric field strength modeled on the connection wiring layer 72AA, the first wiring layer 71A, and the via 81.
  • Fig. 29 is a graph showing the relationship between the first protrusion length of the first protrusion portion 74AA of the first wiring layer 71A and the electric field strength.
  • "None (typ.)" in Fig. 29 shows the electric field strength of the connection wiring layer 72AA in the first comparative example (see Fig. 20) that does not include the first wiring layer 71.
  • the first protruding portion 74AA of the first wiring layer 71A gently bends the equipotential lines at the corners that form the ends of the connection wiring layer 72AA that are closer to the first protruding portion 74AA of both ends in the X direction. This reduces the electric field concentration at the corners of the connection wiring layer 72AA.
  • the electric field strength in the connection wiring layer 72AA is smaller than that in the first comparative example. It can also be seen that the electric field strength in the connection wiring layer 72AA decreases as the first protrusion length increases.
  • the first protrusion length is the length of the portion of the first protrusion portion 74AA that protrudes from one side of the width direction of the connection wiring layer 72AA.
  • the first overlapping portion 73AA of the first wiring layer 71A is formed so as to overlap the entire width of the connection wiring layer 72AA.
  • the first protruding portion 74AA is formed so as to protrude from both sides of the connection wiring layer 72AA in the width direction.
  • the first protruding portion 74AA can mitigate the sudden bending of the equipotential lines at the corner portion formed by both side surfaces and the bottom surface of the connection wiring layer 72AA in the width direction. Therefore, electric field concentration in the connection wiring layer 72AA can be mitigated.
  • the protruding length (first protruding length) of the portion of the first protruding portion 74AA protruding from one side in the width direction of the connection wiring layer 72AA is not less than 1 ⁇ m and not more than 10 ⁇ m. This configuration can reduce electric field concentration in the connection wiring layer 72AA.
  • a semiconductor module 10 according to a fourth embodiment will be described with reference to Fig. 30.
  • the semiconductor module 10 according to the fourth embodiment differs from the semiconductor module 10 according to the first embodiment mainly in that a third wiring layer 90 is added.
  • a third wiring layer 90 is added.
  • the first chip 14 further includes a third wiring layer 90 electrically connected to the first wiring layer 71.
  • the third wiring layer 90 is embedded in the front insulating layer 60.
  • the third wiring layer 90 is disposed at a position different from the first wiring layer 71 and the second wiring layer 72 in the Z direction.
  • the third wiring layer 90 is disposed on the opposite side of the semiconductor resistance layer 20 with respect to the first wiring layer 71 in the Z direction.
  • the third wiring layer 90 is made of one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W as appropriate.
  • the third wiring layer 90 is made of a material containing Al. That is, in the fourth embodiment, the third wiring layer 90 is made of the same material as the first wiring layer 71.
  • the third wiring layer 90 has a thickness greater than that of the second wiring layer 72.
  • the third wiring layer 90 has a thickness greater than the first distance D1.
  • the thickness of the third wiring layer 90 is the same as that of the first wiring layer 71.
  • the thickness of the third wiring layer 90 can be changed as desired.
  • the third wiring layer 90 may have a thickness greater than that of the second wiring layer 72 and less than that of the first wiring layer 71.
  • the third wiring layer 90 may have a thickness greater than that of the first wiring layer 71.
  • the third wiring layer 90 may also have a thickness equal to or less than the first distance D1.
  • the third wiring layer 90 is electrically connected to the first wiring layer 71 by a plurality of vias 82.
  • the plurality of vias 82 extend in the Z direction.
  • the plurality of vias 82 are in contact with both the third wiring layer 90 and the first wiring layer 71.
  • the third wiring layer 90 includes a third overlapping portion 91 that overlaps with the first wiring layer 71 in a plan view, and a third protruding portion 92 that protrudes from the first wiring layer 71 in a plan view.
  • the third overlapping portion 91 is formed so as to cover at least the outer periphery of the first wiring layer 71 in a plan view.
  • the third overlapping portion 91 may be formed in a frame shape that covers the outer periphery of the first wiring layer 71 but does not cover an inner portion of the first wiring layer 71 in a plan view.
  • the third overlapping portion 91 may be formed so as to cover the entire first wiring layer 71 in a plan view.
  • the third protrusion 92 is formed so as to protrude from at least one side of the width direction of the first wiring layer 71 in a plan view.
  • the third protrusion 92 is formed so as to protrude from only one side of the width direction of the first wiring layer 71.
  • the protrusion length of the portion of the third protrusion 92 protruding from one side of the width direction of the first wiring layer 71 is, for example, 1 ⁇ m or more and 10 ⁇ m or less.
  • the third protrusion 92 may be formed so as to protrude from both sides of the width direction of the first wiring layer 71.
  • the first protrusion length of the portion of the first protrusion 92 protruding from the first direction in the width direction of the first wiring layer 71 and the second protrusion length of the portion protruding from the second direction opposite to the first direction in the width direction of the first wiring layer 71 are equal to each other.
  • the first protrusion length and the second protrusion length can be set individually. Therefore, the first protrusion length and the second protrusion length may be different from each other. Furthermore, at least one of the first protrusion length and the second protrusion length may be longer than 10 ⁇ m.
  • the third wiring layer 90 constitutes the terminals P1 to P5. That is, in the fourth embodiment, the first wiring layer 71 does not constitute the terminals P1 to P5.
  • the third wiring layer 90 covering the first wiring layer 71A is formed so as to cover the resistor cover portion 71AA, the terminal configuration portion 71AB, and the wiring cover portion 71AC of the first wiring layer 71A.
  • the configuration of the third wiring layer 90 covering the first wiring layer 71A is not limited to this.
  • the third wiring layer 90 covering the first wiring layer 71A may be configured to cover at least one of the resistor cover portion 71AA, the terminal configuration portion 71AB, and the wiring cover portion 71AC.
  • the configuration of the third wiring layer 90 covering the first wiring layer 71B may be the same as the configuration of the third wiring layer 90 covering the first wiring layer 71A.
  • the shape of the first wiring layer 71 in plan view is not limited to the shape of the first wiring layer 71 in the first embodiment and can be changed as desired.
  • the first wiring layer 71A only needs to include a first overlapping portion that overlaps with the second wiring layer 72A in plan view and a first protruding portion that protrudes from the second wiring layer 72A in plan view, so the resistor cover portion 71AA may be omitted.
  • the first wiring layer 71B can also be changed in a similar manner.
  • the third wiring layer 90 may have a resistor cover portion that covers the semiconductor resistor layer 20 in plan view.
  • the first chip 14 further includes a third wiring layer 90 electrically connected to the first wiring layer 71F.
  • the third wiring layer 90 includes a third overlapping portion 91 that overlaps with the first wiring layer 71F in a planar view, and a third protruding portion 92 that protrudes from the first wiring layer 71F in a planar view.
  • the equipotential lines are less likely to wrap around the first wiring layer 71F, and therefore the sharp bending of the equipotential lines at the end of the first wiring layer 71F opposite the semiconductor resistance layer 20 can be mitigated. Therefore, the electric field concentration at the end of the first wiring layer 71F can be mitigated.
  • the equipotential lines must wrap around the first wiring layer 71F, the second wiring layer 72A, and the third wiring layer 90, the electric field strength in each of the first wiring layer 71F, the second wiring layer 72A, and the third wiring layer 90 is reduced.
  • the third wiring layer 90 has a thickness greater than that of the second wiring layer 72A. According to this configuration, the equipotential lines are less likely to detour through the first wiring layer 71F, the second wiring layer 72A, and the third wiring layer 90, and thus sharp bending of the equipotential lines is mitigated. Therefore, it is possible to mitigate both electric field concentration in each of the first wiring layer 71F, the second wiring layer 72A, and the third wiring layer 90.
  • the third wiring layer 90 has a thickness greater than the first distance D1. According to this configuration, since equipotential lines are less likely to wrap around the third wiring layer 90, electric field concentration in both the first wiring layer 71F and the second wiring layer 72A can be alleviated.
  • the third protrusion length of the third wiring layer 90 is longer than the first distance D1.
  • This configuration can reduce electric field concentration in both the first wiring layer 71F and the second wiring layer 72A, compared to the first comparative example that does not include the first wiring layer 71.
  • the same effect can be obtained by making the first protruding length of the first protruding portion 74G of the first wiring layer 71G longer than the first distance D1.
  • the third protrusion length of the third wiring layer 90 is not less than 1 ⁇ m and not more than 10 ⁇ m.
  • This configuration can reduce electric field concentration in the first wiring layer 71F and the second wiring layer 72A, compared to the first comparative example that does not include the first wiring layer 71.
  • the same effect can be obtained by setting the first protrusion length of the first protrusion portion 74G of the first wiring layer 71G to be 1 ⁇ m or more and 10 ⁇ m or less.
  • the semiconductor module 100 of the fifth embodiment is a signal transmission device that transmits a pulse signal while electrically isolating a primary terminal 101 and a secondary terminal 102.
  • An example of such a signal transmission device is a digital isolator.
  • One example of a digital isolator is a DC/DC converter.
  • the semiconductor module 100 includes a signal transmission circuit 100A having a primary circuit 103 electrically connected to the primary terminal 101, a secondary circuit 104 electrically connected to the secondary terminal 102, and a transformer 105 that electrically insulates the primary circuit 103 from the secondary circuit 104.
  • the primary circuit 103 is configured to operate when a first voltage V1 is applied.
  • the primary circuit 103 is electrically connected to, for example, an external control device (not shown) via the primary terminal 101.
  • the secondary circuit 104 is a circuit configured to operate when a second voltage V2 different from the first voltage V1 is applied.
  • the second voltage V2 is, for example, higher than the first voltage V1.
  • the first voltage V1 and the second voltage V2 are DC voltages.
  • the secondary circuit 104 is electrically connected, for example, to a drive circuit that is to be controlled by the control device via the secondary terminals 102.
  • An example of a drive circuit is a switching circuit.
  • the signal transmission circuit 100A when a control signal from the control device is input to the primary circuit 103 via the primary terminal 101, the signal is transmitted from the primary circuit 103 to the secondary circuit 104 via the transformer 105. The signal transmitted to the secondary circuit 104 is then output from the secondary circuit 104 to the drive circuit via the secondary terminal 102.
  • the primary circuit 103 and the secondary circuit 104 are electrically insulated by the transformer 105. More specifically, the transformer 105 restricts the transmission of DC voltage between the primary circuit 103 and the secondary circuit 104, while allowing the transmission of pulse signals.
  • the state in which the primary circuit 103 and the secondary circuit 104 are insulated means that the transmission of DC voltage between the primary circuit 103 and the secondary circuit 104 is blocked, while the transmission of a pulse signal from the primary circuit 103 to the secondary circuit 104 is permitted.
  • the dielectric strength voltage of the semiconductor module 100 is, for example, 2500 Vrms or more and 7500 Vrms or less. In one example, the dielectric strength voltage of the semiconductor module 100 is approximately 5700 Vrms. However, the specific value of the dielectric strength voltage of the semiconductor module 100 is not limited to this and can be changed as desired. In one example, the ground of the primary circuit 103 and the ground of the secondary circuit 104 are provided independently.
  • the semiconductor module 100 includes two transformers 105 corresponding to the transmission of two types of signals from the primary circuit 103 to the secondary circuit 104. More specifically, the semiconductor module 100 includes a transformer 105 used to transmit a first signal from the primary circuit 103 to the secondary circuit 104, and a transformer 105 used to transmit a second signal from the primary circuit 103 to the secondary circuit 104.
  • the first signal is a signal including rising edge information of an external signal input to the semiconductor module 100
  • the second signal is a signal including falling edge information of the external signal.
  • a pulse signal is generated by the first signal and the second signal.
  • transformer 105 used to transmit the first signal will be referred to as the "first transformer 105A,” and the transformer 105 used to transmit the second signal will be referred to as the “second transformer 105B.”
  • the first transformer 105A is configured to transmit a first signal from the primary circuit 103 to the secondary circuit 104 while electrically insulating the primary circuit 103 from the secondary circuit 104.
  • the second transformer 105B is configured to transmit a second signal from the primary circuit 103 to the secondary circuit 104 while electrically insulating the primary circuit 103 from the secondary circuit 104.
  • the dielectric strength voltage of the first transformer 105A and the second transformer 105B is, for example, 2500 Vrms or more and 7500 Vrms or less. However, the specific values of the dielectric strength voltages of the first transformer 105A and the second transformer 105B are not limited to these values and can be changed arbitrarily.
  • the first transformer 105A has a low-voltage coil 106A and a high-voltage coil 107A that is electrically insulated from the low-voltage coil 106A and can be magnetically coupled.
  • a first coil end of the low-voltage coil 106A is electrically connected to the primary circuit 103, while a second coil end of the low-voltage coil 106A is electrically connected to the ground of the primary circuit 103.
  • a first coil end of the high-voltage coil 107A is electrically connected to the secondary circuit 104, while a second coil end of the high-voltage coil 107A is electrically connected to the ground of the secondary circuit 104.
  • the second transformer 105B has a low-voltage coil 106B and a high-voltage coil 107B that is electrically insulated from the low-voltage coil 106B and can be magnetically coupled. As shown in FIG. 31, the electrical connection between the low-voltage coil 106B and the high-voltage coil 107B is the same as that of the first transformer 105A, so a detailed description thereof will be omitted.
  • low-voltage coils 106A and 106B correspond to the "first coil”
  • high-voltage coils 107A and 107B correspond to the "second coil”
  • low-voltage coils 106A and 106B and high-voltage coils 107A and 107B correspond to the "element configuration layer.”
  • the semiconductor module 100 has multiple semiconductor chips packaged in one package.
  • the package format of the semiconductor module 100 is a small outline (SO) type.
  • SO small outline
  • SOP small outline package
  • the package format of the semiconductor module 100 can be changed as desired.
  • the semiconductor module 100 includes a first chip 110, a second chip 120, and a transformer chip 130 as semiconductor chips.
  • the semiconductor module 100 also includes a primary side die pad 140 on which the first chip 110 is mounted, a secondary side die pad 150 on which the second chip 120 is mounted, and a sealing resin 160 that seals the first chip 110, the second chip 120, the transformer chip 130, the primary side die pad 140, and the secondary side die pad 150.
  • the transformer chip 130 corresponds to the "semiconductor device”.
  • the secondary side die pad 150 corresponds to the "support member”.
  • the sealing resin 160 is made of an electrically insulating material.
  • One example of such a material is black epoxy resin.
  • the sealing resin 160 is formed in a rectangular plate shape with the thickness direction being in the Z direction.
  • both the primary side die pad 140 and the secondary side die pad 150 are arranged at a distance from each other in the X direction. Both the primary side die pad 140 and the secondary side die pad 150 are formed in a flat plate shape. In one example, both the primary side die pad 140 and the secondary side die pad 150 are conductive layers formed from a conductive material.
  • the conductive material is a material containing Cu and Al. Note that the material constituting both the primary side die pad 140 and the secondary side die pad 150 is not limited to a conductive material and may be an insulating material. One example of the insulating material may be ceramics such as alumina.
  • the transformer chip 130 is mounted on the secondary die pad 150. Therefore, it can be said that the transformer chip 130 is supported by the secondary die pad 150. Both the transformer chip 130 and the second chip 120 are mounted on the secondary die pad 150. The transformer chip 130 and the second chip 120 are arranged spaced apart from each other in the X direction. The transformer chip 130 is disposed between the first chip 110 and the second chip 120 in the X direction.
  • the first chip 110 is a chip that includes the primary circuit 103.
  • the first chip 110 has a plurality of first electrode pads 111 and a plurality of second electrode pads 112 that are exposed from the top surface of the chip.
  • the first chip 110 is joined to the primary die pad 140 by a conductive bonding material such as solder paste or silver paste.
  • the primary die pad 140 constitutes the first ground. Therefore, the primary circuit 103 is electrically connected to the first ground.
  • the second chip 120 is a chip that includes the secondary circuit 104.
  • the second chip 120 has a plurality of first electrode pads 121 and a plurality of second electrode pads 122 that are exposed from the top surface of the chip.
  • the second chip 120 is joined to the secondary die pad 150 by a conductive bonding material.
  • the secondary die pad 150 constitutes the second ground. Therefore, the secondary circuit 104 is electrically connected to the second ground.
  • the transformer chip 130 is a chip including both the first transformer 105A and the second transformer 105B (see FIG. 31). Therefore, the transformer chip 130 is a chip dedicated to the first transformer 105A and the second transformer 105B, separate from the first chip 110 and the second chip 120.
  • the transformer chip 130 has a plurality of first electrode pads 131 and a plurality of second electrode pads 132 that are provided so as to be exposed from the upper surface of the chip.
  • the plurality of first electrode pads 131 are electrode pads electrically connected to the low voltage coil 106A (106B), and the plurality of second electrode pads 132 are electrode pads electrically connected to the high voltage coil 107A (107B).
  • the transformer chip 130 is bonded to the secondary die pad 150, for example, by a conductive bonding material.
  • the transformer chip 130 may be bonded to the secondary die pad 150, for example, by an insulating bonding material such as epoxy resin.
  • the first electrode pads 111 of the first chip 110 are individually connected to a number of primary leads (not shown) by a number of wires WA1.
  • the primary leads are components that constitute the primary terminals 101 in FIG. 31. This electrically connects the primary circuit 103 and the primary terminals 101.
  • the primary leads have terminal portions that protrude from the sealing resin 160 toward the outside.
  • the second electrode pads 112 of the first chip 110 are individually connected to the first electrode pads 131 of the transformer chip 130 by wires WA2. This electrically connects the primary circuit 103 and the low-voltage coil 106A (106B).
  • the second electrode pads 132 of the transformer chip 130 are individually connected to the first electrode pads 121 of the second chip 120 by wires WA3. This electrically connects the secondary circuit 104 and the high-voltage coil 107A (107B).
  • the second electrode pads 122 of the second chip 120 are individually connected to a number of secondary leads (not shown) by a number of wires WA4.
  • the secondary leads are components that constitute the secondary terminals 102 in FIG. 31. This electrically connects the secondary circuit 104 and the secondary terminals 102.
  • the secondary leads have terminal portions that protrude from the sealing resin 160 toward the outside.
  • Each of the wires WA1 to WA4 is a bonding wire formed by a wire bonding device.
  • Each of the wires WA1 to WA4 is made of a conductor such as Au (gold), Al, or Cu.
  • FIG. 33 shows a cross-sectional structure of the transformer chip 130 and the secondary die pad 150 cut in the XZ plane.
  • the multiple first electrode pads 131 are referred to as “first electrode pads 131A” and “first electrode pads 131B”
  • the multiple second electrode pads 132 are referred to as “second electrode pads 132A” and “second electrode pads 132B.”
  • the transformer chip 130 includes a substrate 30 and an element insulating layer 40, similar to the first chip 14 of the first embodiment.
  • the transformer chip 130 also includes a first coil 133 that constitutes the low-voltage coil 106A (106B) and a second coil 134 that constitutes the high-voltage coil 107A (107B).
  • Both the first coil 133 and the second coil 134 are embedded in the element insulating layer 40. In one example, both the first coil 133 and the second coil 134 are embedded in the substrate-side insulating layer 50.
  • the second coil 134 is disposed opposite the first coil 133 in the Z direction. A part of the element insulating layer 40 (substrate-side insulating layer 50) is interposed between the first coil 133 and the second coil 134.
  • the second coil 134 is disposed closer to the element surface 41 of the element insulating layer 40 than the first coil 133.
  • the position of the second coil 134 in the Z direction can be changed as desired.
  • the second coil 134 may be disposed on the substrate-side insulating layer 50.
  • the material constituting the first coil 133 and the second coil 134 is appropriately selected from one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W.
  • each of the first coil 133 and the second coil 134 is formed from a material containing Cu.
  • the first coil 133 is electrically connected to the first electrode pad 131A via the low-voltage side connection wiring 135.
  • the first coil 133 is also electrically connected to the first electrode pad 131B via the low-voltage side connection wiring 136.
  • the second coil 134 is electrically connected to the second electrode pad 132A via the high-voltage side connection wiring 137.
  • the second coil 134 is electrically connected to the second electrode pad 132B via the high-voltage side connection wiring 138.
  • the low-voltage side connection wirings 135 and 136 are formed, for example, by a combination of a wiring layer and a via.
  • the first electrode pads 131A and 131B and the second electrode pads 132A and 132B are covered by the passivation film 43 with a portion of them exposed.
  • FIG. 34 is an enlarged view of the high voltage side connection wiring 137 and its surroundings.
  • the high voltage side connection wiring 137 includes a first wiring layer 137A, a second wiring layer 137B, a first via 137C, and a second via 137D.
  • the first wiring layer 137A, the second wiring layer 137B, the first via 137C, and the second via 137D are provided in the front side insulating layer 60.
  • the first wiring layer 137A, the second wiring layer 137B, the first via 137C, and the second via 137D are each appropriately selected from one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W.
  • the first wiring layer 137A and the second wiring layer 137B are each formed of a material containing Al.
  • the first via 137C and the second via 137D are each formed of a material containing W.
  • the first wiring layer 137A is disposed on the opposite side of the substrate 30 from the second coil 134 in the Z direction.
  • the second wiring layer 137B is disposed between the second coil 134 and the first wiring layer 137A in the Z direction. It can also be said that the second wiring layer 137B is disposed on the opposite side of the substrate 30 from the second coil 134 in the Z direction.
  • the second wiring layer 137B includes a second overlapping portion 137BA that overlaps with the second coil 134 in a planar view, and a second protruding portion 137BB that protrudes from the second coil 134 in a planar view.
  • the second overlapping portion 137BA includes an annular portion formed in a ring shape so as to cover the outermost conductor of the second coil 134 in a planar view.
  • the second overlapping portion 137BA is not limited to being annular in a planar view, and may be formed in a circular shape so as to cover the entire second coil 134 in a planar view, for example.
  • the shape of the second coil 134 in a planar view is rectangular, the second overlapping portion 137BA may be formed in a rectangular shape so as to cover the entire second coil 134 in a planar view.
  • the second protruding portion 137BB includes an annular portion formed in a ring shape so as to extend from the second overlapping portion 137BA toward the outside of the second coil 134.
  • the first vias 137C are conductive members that electrically connect the second coil 134 and the second wiring layer 137B, and for example, a plurality of first vias 137C are provided. Each of the first vias 137C extends in the Z direction. The plurality of first vias 137C contact both the second coil 134 and the second overlapping portion 137BA of the second wiring layer 137B in a plan view.
  • the first wiring layer 137A includes a first overlapping portion 137AA that overlaps with the second wiring layer 137B in a planar view, and a first protruding portion 137AB that protrudes from the second wiring layer 137B in a planar view.
  • the first overlapping portion 137AA includes an annular portion formed in a ring shape so as to cover the outer periphery of the second wiring layer 137B in a planar view.
  • the first overlapping portion 137AA is not limited to being annular in a planar view, and may be formed in a circular shape so as to cover the entire second wiring layer 137B in a planar view, for example.
  • the shape of the second wiring layer 137B in a planar view is rectangular, the first overlapping portion 137AA may be formed in a rectangular shape so as to cover the entire second wiring layer 137B in a planar view.
  • the first protruding portion 137AB includes a ring-shaped portion that is formed in a ring shape so as to extend outward from the first overlapping portion 137AA toward the outside of the second wiring layer 137B.
  • the second vias 137D are conductive members that electrically connect the second wiring layer 137B and the first wiring layer 137A, and are provided in multiple numbers, for example. Each of the second vias 137D extends in the Z direction. In a plan view, the multiple second vias 137D are in contact with both the second protruding portion 137BB of the second wiring layer 137B and the first overlapping portion 137AA of the first wiring layer 137A.
  • the high-voltage side connection wiring 138 includes a first wiring layer 138A, a second wiring layer 138B, a first via 138C, and a second via 138D.
  • the configuration of the high-voltage side connection wiring 138 is similar to the configuration of the high-voltage side connection wiring 137, and therefore a detailed description thereof will be omitted. Note that according to the fifth embodiment, the same effects as those of the first embodiment can be obtained.
  • the position of the first wiring layer 71 in the Z direction can be changed arbitrarily.
  • the first wiring layer 71 may be disposed so that its underside is at the same position as the underside of the semiconductor resistance layer 20.
  • the underside of the first wiring layer 71 is the surface of the first wiring layer 71 in the Z direction that faces the substrate 30.
  • the underside of the semiconductor resistance layer 20 is the surface of the semiconductor resistance layer 20 in the Z direction that faces the substrate 30.
  • the first protruding portion 74AA of the first wiring layer 71A may protrude from only one side of the width direction of the connection wiring layer 72AA, rather than from both sides. Note that the first protruding portions of the first wiring layers 71B to 71E may also be modified in the same manner as the first wiring layer 71A.
  • terminals P1 to P5 may be provided separately from the first wiring layer 71.
  • the first wiring layer 71 is electrically connected to the terminals P1 to P5.
  • the terminals P1 to P5 may be arranged on the opposite side of the first wiring layer 71 to the semiconductor resistance layer 20.
  • the terminals P1 to P5 may also be arranged in the same position as the first wiring layer 71 in the Z direction.
  • terminals P1 to P5 may be provided separately from the third wiring layer 90.
  • the third wiring layer 90 is electrically connected to the terminals P1 to P5.
  • the terminals P1 to P5 may be arranged on the opposite side of the third wiring layer 90 to the first wiring layer 71.
  • the terminals P1 to P5 may also be arranged in the same position as the third wiring layer 90 in the Z direction.
  • the number of semiconductor resistance layers 20 can be changed as desired.
  • the number of semiconductor resistance layers 20 may be one.
  • the semiconductor resistance layer 20 may be formed, for example, in a bellows shape in a plan view.
  • the second wiring layer 72 may be provided at both ends in the direction in which the semiconductor resistance layer 20 extends and at the locations where the terminals P3 to P5 are connected.
  • the number of semiconductor resistance layers 20 to which the second wiring layers 72PA, 72PB are connected can be changed as desired.
  • the second wiring layers 72PA, 72PB may be configured to connect three or more semiconductor resistance layers 20.
  • the positional relationship between the first wiring layers 137A, 138A and the second wiring layers 137B, 138B of the high-voltage side connection wiring 137, 138 and the second coil 134 can be changed as desired.
  • the second wiring layers 137B, 138B may be disposed closer to the substrate 30 than the second coil 134.
  • the second coil 134 is disposed spaced apart in the Z direction from the substrate-side insulating layer 50.
  • the relative positions of the first coil 133 and the second coil 134 in the transformer chip 130 can be changed as desired.
  • the first coil 133 may be positioned closer to the element surface 41 of the element insulating layer 40 than the second coil 134.
  • the position of the transformer chip 130 can be changed arbitrarily.
  • the transformer chip 130 may be disposed on the primary side die pad 140.
  • the transformer chip 130 may also be mounted on an intermediate die pad (not shown) separate from the primary side die pad 140 and the secondary side die pad 150.
  • the intermediate die pad is disposed, for example, between the primary side die pad 140 and the secondary side die pad 150 in the X direction.
  • the intermediate die pad is sealed with the sealing resin 160.
  • the primary side die pad 140 corresponds to the "support member”.
  • the transformer chip 130 is disposed on the intermediate die pad, the intermediate die pad corresponds to the "support member".
  • the direction of signal transmission in the semiconductor module 100 can be changed arbitrarily.
  • the semiconductor module 100 may be configured so that a signal is transmitted from the secondary circuit 104 to the primary circuit 103 via the transformer 105. More specifically, when a signal (e.g., a feedback signal) from a drive circuit electrically connected to the secondary circuit 104 via the secondary terminal 102 is input to the secondary terminal 102, the signal is transmitted from the secondary circuit 104 to the primary circuit 103 via the transformer 105. Then, the signal of the primary circuit 103 is output to a control device electrically connected to the primary circuit 103 via the primary terminal 101.
  • the semiconductor module 100 may also be configured so that a signal is transmitted in both directions between the primary circuit 103 and the secondary circuit 104.
  • the semiconductor module 100 may include a primary circuit 103 and a secondary circuit 104 configured to transmit and receive signals to and from the primary circuit 103 via a transformer 105.
  • the configuration of the semiconductor module 100 can be changed as desired.
  • the semiconductor module 100 includes a transformer chip 130, a die pad on which the transformer chip 130 is mounted, and a sealing resin 160 that seals the transformer chip 130 and the die pad.
  • the first chip 110 and the second chip 120, the primary side die pad 140, and the secondary side die pad 150 may be omitted from the semiconductor module 100.
  • the semiconductor module 100 may include a capacitor 200A instead of the transformer 105.
  • a first electrode of the capacitor 200A is electrically connected to the primary circuit 103, and a second electrode of the capacitor 200A is electrically connected to the secondary circuit 104.
  • the semiconductor module 100 may include, for example, a capacitor chip 200 shown in FIG. 35 instead of the transformer chip 130.
  • the capacitor chip 200 corresponds to a "semiconductor device".
  • the capacitor chip 200 like the transformer chip 130, includes a substrate 30, an element insulating layer 40 provided on the substrate 30, and a first electrode plate 201 and a second electrode plate 202 embedded in the element insulating layer 40.
  • the first electrode plate 201 constitutes the first electrode of the capacitor 200A
  • the second electrode plate 202 constitutes the second electrode of the capacitor 200A.
  • the capacitor chip 200 further includes a first electrode pad 203 electrically connected to the first electrode plate 201 and a second electrode pad 204 electrically connected to the second electrode plate 202. Both the first electrode pad 203 and the second electrode pad 204 are formed on the front-side insulating layer 60, like the transformer chip 130, and are covered by a passivation film 43.
  • the first electrode plate 201 and the second electrode plate 202 of the capacitor 200A correspond to the "element configuration layer".
  • the first electrode plate 201 of the capacitor 200A is embedded in the substrate-side insulating layer 50, and the second electrode plate 202 is provided on the substrate-side insulating layer 50.
  • the second electrode plate 202 is covered by the surface-side insulating layer 60.
  • the first electrode plate 201 and the second electrode plate 202 are arranged to face each other in the Z direction, for example.
  • Both the first electrode plate 201 and the second electrode plate 202 are formed in a flat plate shape with the Z direction as the thickness direction. Note that both the first electrode plate 201 and the second electrode plate 202 of the capacitor 200A may be embedded in the substrate-side insulating layer 50.
  • the capacitor chip 200 further includes a low-voltage side connection wiring 205 and a high-voltage side connection wiring 206.
  • the low-voltage side connection wiring 205 is a wiring that connects the first electrode plate 201 and the first electrode pad 203.
  • the high-voltage side connection wiring 206 is a wiring that connects the second electrode plate 202 and the second electrode pad 204.
  • the high voltage side connection wiring 206 includes a first wiring layer 211 , a second wiring layer 212 , a first via 213 , and a second via 214 .
  • the second wiring layer 212 is disposed at a position different from the second electrode plate 202 in the Z direction. In one example, the second wiring layer 212 is disposed on the opposite side of the substrate 30 with respect to the second electrode plate 202 in the Z direction. The second wiring layer 212 is disposed spaced apart from the second electrode plate 202 in the Z direction. For this reason, a part of the front-side insulating layer 60 is interposed between the second wiring layer 212 and the second electrode plate 202 in the Z direction.
  • the second wiring layer 212 is electrically connected to the second electrode plate 202 by the first via 213.
  • the second wiring layer 212 includes a second overlapping portion 212A that overlaps with the second electrode plate 202 in a planar view, and a second protruding portion 212B that protrudes from the second electrode plate 202 in a planar view.
  • the second protruding portion 212B extends from the second overlapping portion 212A toward the first wiring layer 211.
  • the first wiring layer 211 is disposed at a different position in the Z direction from the second electrode plate 202.
  • the first wiring layer 211 is also disposed at a different position in the Z direction from the second wiring layer 212.
  • the first wiring layer 211 is disposed on the opposite side of the substrate 30 from the second wiring layer 212 in the Z direction.
  • the second wiring layer 212 is disposed between the first wiring layer 211 and the second electrode plate 202 in the Z direction. For this reason, a part of the front-side insulating layer 60 is interposed between the first wiring layer 211 and the second wiring layer 212 in the Z direction.
  • the first wiring layer 211 is electrically connected to the second wiring layer 212 by the second via 214.
  • the first wiring layer 211 includes a first overlapping portion 211A that overlaps with the second wiring layer 212 in a planar view, and a first protruding portion 211B that protrudes from the second wiring layer 212 in a planar view.
  • the first protruding portion 211B extends from the first overlapping portion 211A toward the opposite side to the second electrode plate 202 in the Y direction.
  • on as used in this disclosure includes the meanings of “on” and “above” unless the context clearly indicates otherwise.
  • the expression “A is formed on B” is intended to mean that, although in each of the above embodiments, A may be in contact with B and directly disposed on B, as a modified example, A may be disposed above B without contacting B.
  • the term “on” does not exclude a structure in which another member is formed between A and B.
  • the Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to be perfectly aligned with the vertical direction.
  • the various structures according to this disclosure are not limited to the "up” and “down” of the z direction described in this specification being “up” and “down” in the vertical direction.
  • the X direction may be the vertical direction
  • the Y direction may be the vertical direction.
  • the first wiring layer (71F) is A first overlapping portion (73F) overlapping the second wiring layer (72PA) when viewed from a thickness direction (Z direction) of the element insulating layer (40); a first protruding portion (74F) protruding from the second wiring layer (72PA) when viewed in a thickness direction (Z direction) of the element insulating layer (40).
  • the semiconductor device further includes one or more element configuration layers (20) provided on the element insulating layer (40) and electrically connected to the wiring layer (70),
  • the element configuration layer (20) is provided at a position different from the second wiring layer (72PA) in a thickness direction (Z direction) of the element insulating layer (40),
  • the second wiring layer (72PA) is A second overlapping portion (75A) that overlaps with the element configuration layer (20) when viewed from the thickness direction (Z direction) of the element insulating layer (40);
  • the semiconductor device according to Appendix A1 further comprising: a second protruding portion (76A) protruding from the element configuration layer (20) when viewed in a thickness direction (Z direction) of the element insulating layer (40).
  • Appendix A3 The semiconductor device according to Appendix A2, wherein the second wiring layer (72) is configured to connect a plurality of the element configuration layers (20).
  • Appendix A5 The semiconductor device according to any one of Appendixes A1 to A3, wherein a protruding length of the first protruding portion (74F) is 1 ⁇ m or more and 10 ⁇ m or less.
  • the first wiring layer (71F/71) is disposed on the opposite side of the element configuration layer (20) to the substrate (30) in the thickness direction (Z direction) of the element insulating layer (40);
  • Appendix A7 The semiconductor device described in Appendix A6, wherein a first distance (D1) between the first wiring layer (71) and the element configuration layer (20) in a thickness direction (Z direction) of the element insulating layer (40) is smaller than a second distance (D2) between the second wiring layer (72) and the element configuration layer (20) in the thickness direction (Z direction) of the element insulating layer (40).
  • Appendix A8 The semiconductor device according to Appendix A7, wherein a protruding length of the first protruding portion (74F) is longer than the first distance (D1).
  • the first wiring layer (71A) is disposed on the opposite side of the element configuration layer (20) to the substrate (30) in the thickness direction (Z direction) of the element insulating layer (40);
  • Appendix A12 The semiconductor device according to Appendix A11, wherein the first wiring layer (71A) is disposed at the same position as the electrode pad (P1) in a thickness direction (Z direction) of the element insulating layer (40).
  • the first overlapping portion (73AA) is formed so as to overlap the second wiring layer (72AA) over the entire width direction thereof,
  • Appendix A14 The semiconductor device according to Appendix A11, wherein a protruding length of a portion of the first protruding portion (74AA) protruding from one side in a width direction of the second wiring layer (72AA) is 1 ⁇ m or more and 10 ⁇ m or less.
  • the element constituent layer is A first coil (106A, 106B), The semiconductor device according to claim 2 or 3, further comprising: a second coil (107A, 107B) disposed opposite the first coil (106A, 106B).
  • a semiconductor device (10) according to any one of appendices A1 to A16; A support member (150) for supporting the semiconductor device (10); and a sealing resin (160) that seals the semiconductor device (10) and the support member (150).
  • the third wiring layer (90) is a third overlapping portion (91) overlapping the first wiring layer (71F) when viewed from a thickness direction (Z direction) of the element insulating layer (40);
  • the semiconductor device according to any one of Appendix A1 to A17, further comprising: a third protruding portion (92) protruding from the first wiring layer (71F) when viewed from a thickness direction (Z direction) of the element insulating layer (40).
  • Appendix A19 The semiconductor device according to Appendix A18, wherein the third wiring layer (90) has a thickness greater than that of the second wiring layer (72).
  • Appendix A20 The semiconductor device according to Appendix A18 or A19, wherein a protruding length of the third protruding portion (92) is 1 ⁇ m or more and 10 ⁇ m or less.
  • Appendix A21 The semiconductor device according to any one of Appendices A18 to A20, wherein the third wiring layer (90) has a thickness greater than a first distance (D1) between the first wiring layer (71) and the element configuration layer (20) in a thickness direction (Z direction) of the element insulating layer (40).
  • REFERENCE SIGNS LIST 10 semiconductor module 11: frame 11A: die pad portion 11B: lead portion 12: die pad 13A to 13G: leads 14: first chip (semiconductor device) Reference Signs List 14A to 14D...first to fourth resistor circuits 15...second chip 15A...voltage detection circuit 16...sealing resin 16A to 16D...first to fourth sealing side surfaces 20, 20E1, 20E2...semiconductor resistor layer 20P...projection 21 to 25...wiring 30...substrate 40...element insulating layer 41...element front surface 42...element back surface 43...passivation film 43X...opening 50...substrate side insulating layer 51...etching stopper film 52...interlayer insulating film 60...front surface insulating layer 60X...opening 70...wiring layer 71, 71A to 71G...first wiring layer 71AA, 71BA...resistor cover portion 71AB, 71BB...terminal configuration portion 71AC...wiring cover portion

Landscapes

  • Semiconductor Integrated Circuits (AREA)
PCT/JP2023/029800 2022-09-30 2023-08-18 半導体装置および半導体モジュール Ceased WO2024070312A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024549864A JPWO2024070312A1 (https=) 2022-09-30 2023-08-18

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-157864 2022-09-30
JP2022157864 2022-09-30

Publications (1)

Publication Number Publication Date
WO2024070312A1 true WO2024070312A1 (ja) 2024-04-04

Family

ID=90477313

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/029800 Ceased WO2024070312A1 (ja) 2022-09-30 2023-08-18 半導体装置および半導体モジュール

Country Status (2)

Country Link
JP (1) JPWO2024070312A1 (https=)
WO (1) WO2024070312A1 (https=)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165577A (ja) * 2005-12-14 2007-06-28 Nec Electronics Corp 半導体ウエハならびに半導体装置およびその製造方法
US20150069572A1 (en) * 2013-09-12 2015-03-12 Texas Instruments Incorporated Multilayer High Voltage Isolation Barrier in an Integrated Circuit
WO2022065007A1 (ja) * 2020-09-23 2022-03-31 ローム株式会社 半導体装置、半導体モジュール、モータ駆動装置および車両

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165577A (ja) * 2005-12-14 2007-06-28 Nec Electronics Corp 半導体ウエハならびに半導体装置およびその製造方法
US20150069572A1 (en) * 2013-09-12 2015-03-12 Texas Instruments Incorporated Multilayer High Voltage Isolation Barrier in an Integrated Circuit
WO2022065007A1 (ja) * 2020-09-23 2022-03-31 ローム株式会社 半導体装置、半導体モジュール、モータ駆動装置および車両

Also Published As

Publication number Publication date
JPWO2024070312A1 (https=) 2024-04-04

Similar Documents

Publication Publication Date Title
US20220208674A1 (en) Insulating chip
US12396264B2 (en) Isolation transformer
JP7803936B2 (ja) 絶縁トランス
WO2022210551A1 (ja) アイソレータ、絶縁モジュールおよびゲートドライバ
US20240313043A1 (en) Insulation chip and signal transmission device
US20240420884A1 (en) Insulated chip and signal transmitting device
US20250014799A1 (en) Insulating chip and signal transmission device
WO2024070312A1 (ja) 半導体装置および半導体モジュール
US12549180B2 (en) Isolation transformer, isolation module, and gate driver
US20250279355A1 (en) Data and power isolation with double isolation barrier
JP7784383B2 (ja) 半導体装置および半導体モジュール
US20240332259A1 (en) Insulation chip and signal transmission device
US20240282699A1 (en) Semiconductor device
US20240332171A1 (en) Insulation chip and signal transmission device
JP2024080049A (ja) 半導体装置および半導体モジュール
US20240332345A1 (en) Insulating chip and signal propagating device
JP2024176796A (ja) トランスチップおよび信号伝達装置
US20250072012A1 (en) Semiconductor device
US20240331932A1 (en) Insulation chip and signal transmission device
US20240072031A1 (en) Signal transmission device and insulated module
JP2024173373A (ja) 信号伝達装置
US12615787B2 (en) Isolator including electrically floating intermediate electrode portion
JP2025021948A (ja) 絶縁チップおよび半導体装置
JP2024173372A (ja) トランスチップおよび信号伝達装置
US20250070103A1 (en) Semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23871554

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2024549864

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 23871554

Country of ref document: EP

Kind code of ref document: A1