WO2024066241A1 - 基于自平衡差分信号积分放大电路的芯片状态监控电路 - Google Patents

基于自平衡差分信号积分放大电路的芯片状态监控电路 Download PDF

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Publication number
WO2024066241A1
WO2024066241A1 PCT/CN2023/082992 CN2023082992W WO2024066241A1 WO 2024066241 A1 WO2024066241 A1 WO 2024066241A1 CN 2023082992 W CN2023082992 W CN 2023082992W WO 2024066241 A1 WO2024066241 A1 WO 2024066241A1
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sampling
capacitor
self
network
integration
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PCT/CN2023/082992
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English (en)
French (fr)
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曹正州
夏飞歌
单悦尔
闫华
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无锡中微亿芯有限公司
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Priority to US18/347,660 priority Critical patent/US20230353161A1/en
Publication of WO2024066241A1 publication Critical patent/WO2024066241A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices

Definitions

  • the present application relates to the field of chip technology, and in particular to a chip state monitoring circuit based on a self-balanced differential signal integration amplifier circuit.
  • SRAM programmable logic devices are designed based on reconfigurable SRAM storage technology. They can realize different functions for users by completing the configuration of circuit logic and are widely used in various fields and scenarios.
  • SRAM type programmable logic devices often have higher reliability requirements.
  • SRAM type programmable logic devices are prone to various operational failures during operation, and operational reliability is difficult to guarantee.
  • a chip state monitoring circuit based on a self-balanced differential signal integration amplifier circuit characterized in that the chip state monitoring circuit comprises a state sensing circuit, a self-balanced differential signal integration amplifier circuit and an analog-to-digital converter connected in sequence, the analog-to-digital converter is connected to a chip configuration circuit inside the chip, and the state sensing circuit is arranged at a point to be detected inside the chip and senses a differential state signal of the chip;
  • the self-balanced differential signal integration amplifier circuit includes a fully differential operational amplifier, a positive coefficient integration network and a negative coefficient balance network, and both networks are connected between the input end and the output end of the fully differential operational amplifier; the fully differential operational amplifier realizes a signal amplification function for the state signal under the action of the positive coefficient integration network, and reversely adjusts the signal amplification under the action of the negative coefficient balance network, and the reverse adjustment function of the negative coefficient balance network is gradually enhanced until the self-balanced differential signal integration amplifier circuit reaches self-balance, so that the output signal of the self-balanced differential signal integration amplifier circuit is stabilized as the state signal after being amplified K times;
  • the state signal amplified by K times is converted by the analog-to-digital converter and then output to the chip configuration circuit.
  • the present application discloses a chip state monitoring circuit based on a self-balanced differential signal integral amplifier circuit.
  • the chip state monitoring circuit is built into the chip and can monitor the state of the chip and make timely Feedback or response, thereby improving the reliability and service life of the chip.
  • the chip status monitoring circuit uses a new self-balanced differential signal integral amplifier circuit. Through the built-in positive coefficient integral network and negative coefficient balance network, the self-balanced differential signal integral amplifier circuit can interact with each other to amplify to the required multiple and then enter a self-balanced stable state, thereby achieving a fixed multiple amplification, without the need for regular reading, and the control method is simple and flexible.
  • the amplification factor achieved by the self-balanced differential signal integration amplifier circuit in a stable state is related to the capacitance of the sampling capacitor and the balancing capacitor. Therefore, the stable amplification factor can be adjusted by adjusting the ratio of the sampling capacitor and the balancing capacitor.
  • the amplification factor has high adjustment accuracy and the adjustment method is accurate and flexible.
  • the self-balanced differential signal integration amplifier circuit has a simple circuit structure, does not require complex peripheral circuits, does not occupy too much chip area and chip resources, and is suitable for use in chip scenarios.
  • FIG. 1 is a schematic diagram of circuit connections of a chip status monitoring circuit in a chip in one embodiment of the present application.
  • FIG. 2 is a circuit diagram of a self-balanced differential signal integration amplifier circuit in a chip status monitoring circuit in an embodiment of the present application.
  • FIG. 3 is a timing diagram of the control of corresponding switches by various control signals in FIG. 2 .
  • FIG. 4 is a diagram showing the voltage variation of the output signal of the self-balanced differential signal integration amplifier circuit in the present application, and a diagram showing the variation of the amount of charge transferred from the sampling capacitor to the two networks with the sampling period.
  • the present application discloses a chip state monitoring circuit based on a self-balanced differential signal integral amplifier circuit, and the chip can be an FPGA chip or an ASIC chip, for example, an SRAM type FPGA.
  • the chip state monitoring circuit includes a state sensing circuit, a self-balanced differential signal integral amplifier circuit and an analog-to-digital converter connected in sequence, and the analog-to-digital converter is connected to the chip configuration circuit inherent in the chip.
  • the chip state monitoring circuit can be added to the existing chip architecture to monitor the operating state of the chip, thereby ensuring its operating reliability. It should be noted that Figure 1 only schematically shows the connection relationship between the chip state monitoring circuit and the chip configuration circuit when it is set inside the chip, and does not indicate the actual position of the chip state monitoring circuit in the chip and the chip area occupied.
  • the state sensing circuit is set at the point to be detected inside the chip and senses the differential state signal of the chip.
  • the self-balanced differential signal integration amplifier circuit amplifies the sensed state signal.
  • the amplified state signal is converted by the analog-to-digital converter and then output to the chip configuration circuit.
  • the chip configuration circuit can provide feedback or respond in a timely manner after receiving the state signal.
  • the state sensing circuit can be various sensors, and the sensed state signal can be various important operating parameters of the chip.
  • the target chip is an SRAM-type FPGA
  • the state sensing circuit is a temperature sensor.
  • the sensed state signal is a temperature signal.
  • the chip configuration circuit can adjust the main frequency of the chip in time, effectively protecting the SRAM-type FPGA from high temperature, thereby improving the reliability and service life of the chip. In addition to temperature, the same is true for other important operating parameters.
  • the sensed status signal is generally a small AC signal in differential form, so a differential signal integration amplifier circuit is needed to amplify the status signal.
  • Conventional differential signal integration amplifier circuits amplify differential signals through a fixed period, and will continue to integrate until the maximum output swing of the circuit. It is necessary to read the amplified signal regularly, which is difficult to control and the amplification factor is not easy to adjust.
  • conventional differential signal integration amplifier circuits have complex peripheral circuits, which will occupy more chip resources and chip area, and are difficult to apply in scenarios such as chips that require high integration. Therefore, the existing common differential signal integration amplifier circuits cannot be directly used in the chip status monitoring circuit of this application.
  • the present application uses a new self-balanced differential signal integration amplifier circuit, which includes a fully differential operational amplifier, a positive coefficient integration network and a negative coefficient balance network, and both networks are connected between the input and output ends of the fully differential operational amplifier.
  • the fully differential operational amplifier realizes the signal amplification function of the state signal under the action of the positive coefficient integration network, and reversely adjusts the signal amplification under the action of the negative coefficient balance network.
  • the self-balanced differential signal integration amplifier circuit realizes the amplification function of the state signal as a whole, but the reverse adjustment function realized by the negative coefficient balance network will gradually increase until it finally reaches self-balance with the amplification factor, so that the output signal of the self-balanced differential signal integration amplifier circuit finally reaches stability, and the output amplified K times state signal.
  • the self-balanced differential signal integration amplifier circuit also includes a sampling network, the sampling network samples the charge of the state signal, and the sampled charge of the sampling network is transferred to the two networks:
  • part of the charge sampled by the sampling network will be transferred to the positive coefficient integration network to realize the signal amplification function, and the other part of the charge sampled by the sampling network will be transferred to the negative coefficient balance network to realize the reverse regulation function of signal amplification.
  • the overall effect is stronger than the reverse regulation effect, so the output signal of the self-balanced differential signal integration amplifier circuit gradually increases.
  • the charge transferred from the sampling network to the negative coefficient balance network gradually increases, making the reverse regulation function of the negative coefficient balance network gradually enhanced.
  • the self-balancing differential signal integration amplifier circuit After the self-balancing differential signal integration amplifier circuit reaches self-balancing, all the charges sampled by the sampling network are transferred to the negative coefficient balancing network, so that the output signal of the self-balancing differential signal integration amplifier circuit is stabilized as a state signal after being amplified K times.
  • the actual self-balanced differential signal integration amplifier circuit works in cycles, and the output signal gradually increases.
  • the self-balanced differential signal integration amplifier circuit sequentially goes through the sampling stage, the integration stage, and the holding stage, so that the output signal of the self-balanced differential signal integration amplifier circuit increases, and finally reaches stability after several sampling cycles.
  • the working process is as follows:
  • each sampling cycle before the self-balanced differential signal integration amplifier circuit reaches self-balance (1) In the sampling phase, the sampling network samples the charge of the state signal. (2) In the integration phase, the fully differential operational amplifier starts to work, and the sampling network transfers the sampled charge to the positive coefficient integration network and the negative coefficient balance network according to the process described above, so that the output signal of the self-balanced differential signal integration amplifier circuit increases. (3) In the holding phase, the output signal of the fully differential operational amplifier remains unchanged.
  • the charge transferred from the sampling network to the integration network and the balancing network is not fixed.
  • the charge transferred from the sampling network to the negative coefficient balancing network increases with the increase of the output signal of the fully differential operational amplifier, thereby making the reverse regulation function realized by the negative coefficient balancing network gradually increase with the sampling cycle until it finally reaches a balance with the amplification function realized by the positive coefficient integration network, so that after several sampling cycles, the self-balanced differential signal integration amplifier circuit reaches self-balance.
  • the sampling network In each sampling cycle after the self-balanced differential signal integration amplifier circuit reaches self-balance: (1) In the sampling phase, the sampling network also samples the charge of the state signal.
  • the fully differential operational amplifier starts to work, and the sampling network transfers all the sampled charges to the negative coefficient balancing network, so that the output signal of the self-balanced differential signal integration amplifier circuit remains unchanged.
  • the output signal of the fully differential operational amplifier remains unchanged.
  • the sampling network is built based on the sampling capacitor Cs
  • the positive coefficient integration network is built based on the integration capacitor Cfp
  • the negative coefficient balance network is built based on the balance capacitor Cfn .
  • the circuit diagram of the self-balanced differential signal integration amplifier circuit in an embodiment shown in Figure 2.
  • the circuit structure of the self-balanced differential signal integration amplifier circuit is simple and does not require complex peripheral circuits.
  • the self-balanced differential signal integration amplifier circuit also includes a common-mode signal generating circuit.
  • the common-mode signal generating circuit is connected to the common-mode signal terminal Com of the fully differential operational amplifier U1 and provides a voltage value of Vcom .
  • the common-mode signal generating circuit is composed of a resistor R1 and a resistor R2 . Pressure circuit implementation.
  • a first circuit structure is connected between the positive input terminal Ip and the negative output terminal On of the fully differential operational amplifier U1, and a second circuit structure is connected between the negative input terminal In and the positive output terminal Op of the fully differential operational amplifier U1.
  • the circuit structures of the first circuit structure and the second circuit structure are symmetrical and have the same working process.
  • Each circuit structure includes a sampling network, a positive coefficient integration network and a negative coefficient balancing network.
  • the sampling network in the first circuit structure is connected to the positive differential input terminal V inp of the self-balanced differential signal integration amplifier circuit for sampling, and the sampling network in the second circuit structure is connected to the negative differential input terminal V inn of the self-balanced differential signal integration amplifier circuit for sampling.
  • the sampling network in the first circuit structure is connected to the negative differential input terminal V inn of the self-balanced differential signal integration amplifier circuit, and the sampling network in the second circuit structure is connected to the positive differential input terminal V inp of the self-balanced differential signal integration amplifier circuit, so that the changing voltage difference on the sampling capacitor in each sampling network transfers the sampled charge to the two networks in the circuit structure.
  • the upper plate of the sampling capacitor Cs in the sampling network is connected to the positive differential input terminal Vinp of the self-balanced differential signal integration amplifier circuit through the switch S6 , and the upper plate of the sampling capacitor Cs is also connected to the negative differential input terminal Vinn of the self-balanced differential signal integration amplifier circuit through the switch S7 .
  • the lower plate of the sampling capacitor Cs is connected to the lower plate of the balancing capacitor Cfn in the negative coefficient balancing network, and the upper plate of the balancing capacitor Cfn is connected to the negative output terminal On of the full differential operational amplifier through the switch S1 .
  • the upper plate of the balancing capacitor Cfn is also connected to the common mode signal terminal Com of the full differential operational amplifier through the switch S2 .
  • the lower plate of the sampling capacitor Cs is also connected to the lower plate of the integration capacitor Cfp in the positive coefficient integration network through the switch S3 , and the upper plate of the integration capacitor Cfp is connected to the negative output terminal On of the full differential operational amplifier through the switch S4 .
  • the lower plate of the integrating capacitor C fp is also connected to the positive input terminal Ip of the full differential operational amplifier, and the positive input terminal Ip and the negative output terminal On of the full differential operational amplifier are also bridged via a switch S 5 .
  • the second circuit structure is symmetrical to the first circuit structure, and the same reference numerals are used in FIG2 .
  • the upper plate of the sampling capacitor Cs in the sampling network is connected to the negative differential input terminal Vinn through the switch S6 , and the upper plate of the sampling capacitor Cs is also connected to the positive differential input terminal Vinp through the switch S7 .
  • the lower plate of the sampling capacitor Cs is connected to the lower plate of the balancing capacitor Cfn in the negative coefficient balancing network, and the upper plate of the balancing capacitor Cfn is connected to the positive output terminal Op of the full differential operational amplifier through the switch S1 .
  • the upper plate of the balancing capacitor Cfn is also connected to the common mode signal terminal Com of the full differential operational amplifier through the switch S2 .
  • the lower plate of the sampling capacitor Cs is also connected to the positive output terminal Op of the full differential operational amplifier through the switch S1.
  • the switch S3 is connected to the lower plate of the integral capacitor Cfp in the positive coefficient integral network, and the upper plate of the integral capacitor Cfp is connected to the positive output terminal Op of the full differential operational amplifier through the switch S4 .
  • the lower plate of the integral capacitor Cfp is also connected to the negative input terminal In of the full differential operational amplifier, and the positive input terminal Ip and the negative output terminal On of the full differential operational amplifier are also bridged through the switch S5 .
  • switch S1 is controlled by control signal ctrl1
  • switch S2 switch S5 and switch S6 are all controlled by control signal ctrl2
  • switch S3 is controlled by control signal ctrl3
  • switch S4 and switch S7 are controlled by control signal ctrl4.
  • the working process of the self-balanced differential signal integration amplifier circuit is as follows. Since the first circuit structure and the second circuit structure are symmetrical and have the same working process, the working process of the first circuit structure in each sampling period is described as follows:
  • control signal ctrl2 controls the switch S2 , switch S5 and switch S6 to be closed
  • control signal ctrl3 controls the switch S3 to be closed
  • control signal ctrl1 controls the switch S1 to be opened
  • control signal ctrl4 controls the switch S4 and switch S7 to be opened.
  • the switch S5 Since the switch S5 is closed, the positive input terminal Ip and the negative output terminal On, and the negative input terminal In and the positive output terminal Op of the fully differential operational amplifier U1 are short-circuited.
  • the value generated after the short-circuiting is connected to the lower plate of the sampling capacitor Cs through the path of F ⁇ D ⁇ B, and is also connected to the lower plate of the balancing capacitor Cfn .
  • the switch S6 Since the switch S6 is closed and the switch S7 is open, the upper plate of the sampling capacitor Cs in the first circuit structure is connected to the positive differential input terminal V inp , so the charge sampled by the sampling capacitor Cs is Cs is the capacitance of the sampling capacitor Cs .
  • control signal ctrl2 controls the switches S2 , S5 and S6 to be opened
  • control signal ctrl3 controls the switch S3 to be closed
  • control signal ctrl1 controls the switch S1 to be closed
  • control signal ctrl4 controls the switch S6 to be closed.
  • Switch S4 and switch S7 are closed.
  • the fully differential operational amplifier starts to work, and the upper plate of the sampling capacitor Cs in the first circuit structure is switched to connect to the negative differential input terminal Vinn .
  • the charge sampled by the sampling capacitor Cs becomes Vinn is the voltage value of the negative differential input terminal Vinn .
  • the changing voltage difference on the sampling capacitor Cs causes the sampling capacitor Cs to transfer the sampled charge to the balancing capacitor Cfn and the integration capacitor Cfp .
  • the transferred charge is
  • the lower plate of the sampling capacitor Cs , the lower plate of the balancing capacitor Cfn and the lower plate of the integrating capacitor Cfp are connected and connected to the positive input terminal Ip of the full differential operational amplifier.
  • the upper plate of the balancing capacitor Cfn and the upper plate of the integrating capacitor Cfp are connected and connected to the negative output terminal On of the full differential operational amplifier.
  • the charge in the balancing capacitor Cfn becomes Since the charge change in the balancing capacitor Cfn is caused by the charge transferred from the sampling capacitor Cs , the charge transferred from the sampling capacitor Cs to the balancing capacitor Cfn of the negative coefficient balancing network can be determined as
  • the control signal ctrl2 controls the switches S2 , S5 , and S6 to be turned off
  • the control signal ctrl3 controls the switch S3 to be turned off
  • the control signal ctrl1 controls the switch S1 to be turned off
  • the control signal ctrl4 controls the switch S4 and S7 to be turned on.
  • the two ends of the integration capacitor Cfp are respectively connected to the input and output ends of the fully differential operational amplifier.
  • the fully differential operational amplifier keeps the output signal unchanged, and the charge of the integration capacitor Cfp remains unchanged until the next sampling cycle.
  • the self-balanced differential signal integration amplifier circuit After several sampling cycles, when ⁇ Q fn increases to be equal to ⁇ Q s , the self-balanced differential signal integration amplifier circuit reaches self-balance. In each subsequent sampling cycle, the charge ⁇ Q s transferred from the sampling capacitor C s to the two networks is completely transferred to the balancing capacitor C fn , and no longer transferred to the integration capacitor C fp . The output signal of the self-balanced differential signal integration amplifier circuit is stabilized as a state signal amplified K times.
  • the amplification factor K of the state signal achieved by the self-balanced differential signal integration amplifier circuit in the stable state is determined by the capacitance of the sampling capacitor Cs and the capacitance of the balancing capacitor Cfn .
  • Cs M ⁇ Cfn
  • Cs is the capacitance of the sampling capacitor Cs
  • Cfn is the capacitance of the balancing capacitor Cfn
  • M is a positive coefficient.

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Abstract

本申请公开了一种基于自平衡差分信号积分放大电路的芯片状态监控电路，涉及芯片技术领域，该芯片状态监控电路内置在芯片中，可以感应芯片的状态信号并经过放大和模数转换后传输给芯片配置电路，以便芯片配置电路进行状态监控以及时做出反馈或响应，从而提高芯片的可靠性和使用寿命。该芯片状态监控电路中使用了全新的自平衡差分信号积分放大电路，通过内置的正系数积分网络和负系数平衡网络，可以使得该自平衡差分信号积分放大电路放大到所需倍数后即进入自平衡的稳定状态，从而实现固定倍数的放大，无需定时读取，控制方式简单且灵活。

Description

基于自平衡差分信号积分放大电路的芯片状态监控电路 技术领域
本申请涉及芯片技术领域，尤其是一种基于自平衡差分信号积分放大电路的芯片状态监控电路。
背景技术
SRAM型可编程逻辑器件基于可重复配置的SRAM型存储技术设计而成，可以通过完成电路逻辑的配置，从而实现用户不同的功能，被广泛应用在各种领域和各种场景下。
SRAM型可编程逻辑器件的应用领域往往有较高的可靠性要求，但是随着内部逻辑资源用量、运算速度和功耗的增加，SRAM型可编程逻辑器件在工作过程中容易出现各种运行故障，运行可靠性难以保证。
发明内容
本申请人针对上述问题及技术需求，提出了一种基于自平衡差分信号积分放大电路的芯片状态监控电路，本申请的技术方案如下：
一种基于自平衡差分信号积分放大电路的芯片状态监控电路，其特征在于，芯片状态监控电路包括依次连接的状态感应电路、自平衡差分信号积分放大电路和模数转换器，模数转换器连接芯片内部的芯片配置电路，状态感应电路设置在芯片内部的待检测点处并感应得到芯片的差分形式的状态信号；
自平衡差分信号积分放大电路包括全差分运算放大器、正系数积分网络和负系数平衡网络，两个网络均连接在全差分运算放大器的输入端和输出端之间；全差分运算放大器在正系数积分网络的作用下对状态信号实现信号放大功能、在负系数平衡网络的作用下对信号放大进行反向调节，且负系数平衡网络的反向调节功能逐渐增强直至自平衡差分信号积分放大电路达到自平衡，使得自平衡差分信号积分放大电路的输出信号稳定为放大K倍后的状态信号；
放大K倍后的状态信号经过模数转换器的模数转换后输出给芯片配置电路。
本申请的有益技术效果是：
本申请公开了一种基于自平衡差分信号积分放大电路的芯片状态监控电路，该芯片状态监控电路内置在芯片中可以对芯片的状态进行监控以及时做出 的反馈或响应，从而提高芯片的可靠性和使用寿命。该芯片状态监控电路内部使用了全新的自平衡差分信号积分放大电路，通过内置的正系数积分网络和负系数平衡网络，可以互相作用使得该自平衡差分信号积分放大电路可以放大到所需倍数后即进入自平衡的稳定状态，从而实现固定倍数的放大，无需定时读取，控制方式简单且灵活。
该自平衡差分信号积分放大电路稳定状态下实现的放大倍数与采样电容和平衡电容的容值相关，因此通过调节采样电容和平衡电容的比例就可以调节稳定放大倍数，放大倍数的调节精度高且调节方式精确灵活。
自平衡差分信号积分放大电路的电路结构简单、无需复杂的外围电路，不会占用过多芯片面积和芯片资源，适合用于芯片场景。
附图说明
图1是本申请一个实施例中的芯片状态监控电路在芯片中的电路连接示意图。
图2是本申请一个实施例中的芯片状态监控电路中的自平衡差分信号积分放大电路的电路图。
图3是图2中各个控制信号对相应的开关的控制时序图。
图4是本申请中的自平衡差分信号积分放大电路的输出信号的电压变化图，以及采样电容向两个网络中转移的电荷量随着采样周期的变化图。
具体实施方式
下面结合附图对本申请的具体实施方式做进一步说明。
本申请公开了一种基于自平衡差分信号积分放大电路的芯片状态监控电路，该芯片可以是FPGA芯片或者ASIC芯片，比如可以是SRAM型FPGA。芯片状态监控电路包括依次连接的状态感应电路、自平衡差分信号积分放大电路和模数转换器，模数转换器连接芯片内部固有的芯片配置电路。请参考图1所示的芯片内部结构示意图，可以通过在现有的芯片架构中增加该芯片状态监控电路以对芯片的运行状态进行监控，从而保证其运行可靠性。需要说明的是，图1仅示意性地示出了芯片状态监控电路设置在芯片内部时与芯片配置电路的连接关系，而并不表示芯片状态监控电路实际在芯片内设置的位置以及占用的芯片区域。
其中，状态感应电路设置在芯片内部的待检测点处并感应得到芯片的差分形式的状态信号。自平衡差分信号积分放大电路对感应到的状态信号进行放大， 放大后的状态信号经过模数转换器的模数转换后输出给芯片配置电路。芯片配置电路在接收到状态信号后可以及时反馈或者做出响应。状态感应电路可以是各类传感器，感应到的状态信号可以是芯片的各种重要的运行参数。
比如在一个典型应用中，针对的芯片为SRAM型FPGA，状态感应电路为温度传感器，则感应到的状态信号为温度信号，在芯片运行过程中，过多热量积累容易引起热击穿或电击穿，由于SRAM型FPGA在断电后不能保存自身的数据，因此监控SRAM型FPGA运行过程中的温度信号有非常重要的应用价值，继而芯片配置电路可以及时调整芯片的主频工作频率，有效的对SRAM型FPGA进行高温保护，从而提高芯片的可靠性和使用寿命。除了温度之外，对于其他各类重要的运行参数也是如此。
在该芯片状态监控电路中，感应到的状态信号一般为差分形式的交流小信号，所以需要使用差分信号积分放大电路对状态信号进行放大。常规的差分信号积分放大电路通过固定的周期对差分信号进行放大，会一直积分直到电路的最大输出摆幅，需要定时读取放大后的信号，控制难度大、放大倍数不易调节，而且常规的差分信号积分放大电路存在外围电路复杂的问题，会占用较多的芯片资源和芯片面积，很难应用在芯片这种对集成度要求高的场景内，因此本申请的芯片状态监控电路中不能直接使用现有常见的差分信号积分放大电路。
为了适应芯片内部的使用需求，本申请使用了一种全新的自平衡差分信号积分放大电路，该自平衡差分信号积分放大电路包括全差分运算放大器、正系数积分网络和负系数平衡网络，两个网络均连接在全差分运算放大器的输入端和输出端之间。全差分运算放大器在正系数积分网络的作用下对状态信号实现信号放大功能、在负系数平衡网络的作用下对信号放大进行反向调节。该自平衡差分信号积分放大电路整体实现对状态信号的放大功能，但负系数平衡网络实现的反向调节功能会逐渐增强直至最终与放大倍数达到自平衡，使得自平衡差分信号积分放大电路的输出信号最终达到稳定，输出放大K倍后的状态信号。
两个网络的信号放大功能和反向调节功能的变化过程是通过如下方法实现的：该自平衡差分信号积分放大电路还包括采样网络，采样网络采样状态信号的电荷，采样网络采样的电荷会转移到两个网络中：
在自平衡差分信号积分放大电路达到自平衡之前，采样网络采样到的一部分电荷会转移到正系数积分网络中实现信号放大功能，采样网络采样到的另一部分电荷转移到负系数平衡网络实现对信号放大的反向调节功能，信号放大效 果整体强于反向调节效果，因此自平衡差分信号积分放大电路的输出信号逐渐增大。随着全差分运算放大器的输出信号的增大，采样网络转移到负系数平衡网络的电荷逐渐增大、使得负系数平衡网络实现的反向调节功能逐渐增强。
直至自平衡差分信号积分放大电路达到自平衡之后，采样网络采样到的电荷全部转移到负系数平衡网络中，使得自平衡差分信号积分放大电路的输出信号稳定为放大K倍后的状态信号。
实际自平衡差分信号积分放大电路按周期工作、输出信号逐步增大，在每个采样周期内，自平衡差分信号积分放大电路依次经过采样阶段、积分阶段和保持阶段使得自平衡差分信号积分放大电路的输出信号增大，最终在经过若干个采样周期后达到稳定。工作过程如下：
在自平衡差分信号积分放大电路达到自平衡之前的每个采样周期内：(1)在采样阶段，采样网络采样状态信号的电荷。(2)在积分阶段，全差分运算放大器开始工作，采样网络按上述介绍的过程将采样到的电荷转移到正系数积分网络和负系数平衡网络，使得自平衡差分信号积分放大电路的输出信号增大。(3)在保持阶段，全差分运算放大器的输出信号保持不变。
随着采样周期的推进，在不同采样周期的积分阶段内，采样网络向积分网络和平衡网络转移的电荷并不是固定的，采样网络转移到负系数平衡网络中的电荷随着全差分运算放大器的输出信号的增大而增大，由此使得负系数平衡网络实现的反向调节功能随着采样周期逐渐增大，直至最终与正系数积分网络实现的放大功能达到平衡，使得在经过若干个采样周期后，自平衡差分信号积分放大电路达到自平衡。在自平衡差分信号积分放大电路达到自平衡之后的每个采样周期内：(1)在采样阶段，采样网络同样采样状态信号的电荷。(2)在积分阶段，全差分运算放大器开始工作，采样网络将采样到的电荷全部转移到负系数平衡网络，使得自平衡差分信号积分放大电路的输出信号保持不变。(3)在保持阶段，全差分运算放大器的输出信号保持不变。
采样网络基于采样电容Cs搭建，正系数积分网络基于积分电容Cfp搭建、负系数平衡网络基于平衡电容Cfn搭建。请结合图2所示的一个实施例中的自平衡差分信号积分放大电路的电路图，自平衡差分信号积分放大电路的电路结构简单，无需复杂的外围电路。该自平衡差分信号积分放大电路还包括共模信号产生电路，共模信号产生电路连接全差分运算放大器U1的共模信号端Com提供的电压值为Vcom。在一个实施例中，共模信号产生电路由电阻R1和电阻R2构成的分 压电路实现。
全差分运算放大器U1的正输入端Ip和负输出端On之间连接第一电路结构，全差分运算放大器U1的负输入端In和正输出端Op之间连接第二电路结构，第一电路结构与第二电路结构的电路结构对称，工作过程相同，每个电路结构分别包括采样网络、正系数积分网络和负系数平衡网络。
在自平衡差分信号积分放大电路的每个采样周期内，(1)在采样阶段，第一电路结构中的采样网络连接至自平衡差分信号积分放大电路的正差分输入端Vinp进行采样、第二电路结构中的采样网络连接至自平衡差分信号积分放大电路的负差分输入端Vinn进行采样。(2)在积分阶段，切换为由第一电路结构中的采样网络连接至自平衡差分信号积分放大电路的负差分输入端Vinn、第二电路结构中的采样网络连接至自平衡差分信号积分放大电路的正差分输入端Vinp，由此每个采样网络中的采样电容上变化的电压差将采样到的电荷转移到所在的电路结构中的两个网络中。
请结合图2，在第一电路结构中，采样网络中的采样电容Cs的上极板通过开关S6连接自平衡差分信号积分放大电路的正差分输入端Vinp，采样电容Cs的上极板还通过开关S7连接自平衡差分信号积分放大电路的负差分输入端Vinn。采样电容Cs的下极板连接负系数平衡网络中的平衡电容Cfn的下极板，平衡电容Cfn的上极板通过开关S1连接全差分运算放大器的负输出端On。平衡电容Cfn的上极板还通过开关S2连接全差分运算放大器的共模信号端Com。采样电容Cs的下极板还通过开关S3连接正系数积分网络中的积分电容Cfp的下极板，积分电容Cfp的上极板通过开关S4连接全差分运算放大器的负输出端On。积分电容Cfp的下极板还连接全差分运算放大器的正输入端Ip，全差分运算放大器的正输入端Ip和负输出端On之间还通过开关S5跨接。
第二电路结构与第一电路结构对称，图2采用相同的附图标记表示，在第二电路结构中，采样网络中的采样电容Cs的上极板通过开关S6连接负差分输入端Vinn，采样电容Cs的上极板还通过开关S7连接正差分输入端Vinp。采样电容Cs的下极板连接负系数平衡网络中的平衡电容Cfn的下极板，平衡电容Cfn的上极板通过开关S1连接全差分运算放大器的正输出端Op。平衡电容Cfn的上极板还通过开关S2连接全差分运算放大器的共模信号端Com。采样电容Cs的下极板还通过开 关S3连接正系数积分网络中的积分电容Cfp的下极板，积分电容Cfp的上极板通过开关S4连接全差分运算放大器的正输出端Op。积分电容Cfp的下极板还连接全差分运算放大器的负输入端In，全差分运算放大器的正输入端Ip和负输出端On之间还通过开关S5跨接。
两个电路结构中的开关S1受控于控制信号ctrl1，开关S2、开关S5和开关S6均受控于控制信号ctrl2，开关S3受控于控制信号ctrl3，开关S4和开关S7受控于控制信号ctrl4。
基于图2所示的电路图，请参考图3所示的各个控制信号对相应开关的控制时序图2，以及图4所示的电压变化值，该自平衡差分信号积分放大电路工作过程如下，由于第一电路结构和第二电路结构对称且工作过程相同，因此以第一电路结构在每个采样周期内的工作过程介绍如下：
(1)在采样阶段，控制信号ctrl2控制开关S2、开关S5和开关S6闭合，控制信号ctrl3控制开关S3闭合，控制信号ctrl1控制开关S1断开，控制信号ctrl4控制开关S4和开关S7断开。
由于开关S5闭合，因此全差分运算放大器U1的正输入端Ip和负输出端On短接、负输入端In和正输出端Op短接，短接后产生的值通过F→D→B的路径连接到采样电容Cs的下极板，同时连接到平衡电容Cfn的下极板。
由于开关S6闭合、开关S7断开，所以第一电路结构中的采样电容Cs的上极板连接正差分输入端Vinp，因此采样电容Cs采样到的电荷为Cs为采样电容Cs的容值。
平衡电容Cfn的上极板连接共模信号产生电路的输出端，电压值为Vcom，所以平衡电容Cfn中的电荷为VIp是全差分运算放大器的正输入端Ip的电压值，Cfn为平衡电容Cfn的容值。由于正输入端Ip和负输出端On短接，所以Vcom＝VIp＝VOn，因此VIp是全差分运算放大器的正输入端Ip的电压值，VOn是全差分运算放大器的负输出端On的电压值。
由于开关S1和开关S4断开，所以积分电容Cfp中的电荷保持不变，承接上一个采样周期的电荷。
(2)在积分阶段，控制信号ctrl2控制开关S2、开关S5和开关S6断开，控制信号ctrl3控制开关S3闭合，控制信号ctrl1控制开关S1闭合，控制信号ctrl4控制开 关S4和开关S7闭合。
由于开关S5断开，全差分运算放大器开始工作，第一电路结构中的采样电容Cs的上极板切换至连接负差分输入端Vinn。此时采样电容Cs采样到的电荷变为Vinn是负差分输入端Vinn的电压值。从采样阶段切换到积分阶段，采样电容Cs上变化的电压差导致采样电容Cs将采样到的电荷转移到平衡电容Cfn和积分电容Cfp上，转移的电荷为
采样电容Cs的下极板、平衡电容Cfn的下极板和积分电容Cfp的下极板相连并连接全差分运算放大器的正输入端Ip。平衡电容Cfn的上极板和积分电容Cfp的上极板相连并连接全差分运算放大器的负输出端On。
因此此时平衡电容Cfn中的电荷变为由于平衡电容Cfn中的电荷变化是由采样电容Cs转移电荷引起的，所以可以确定采样电容Cs转移到负系数平衡网络的平衡电容Cfn的电荷为
进一步可以确定采样电容Cs转移到正系数积分网络的积分电容Cfp的电荷为ΔQfp＝ΔQs-ΔQfn＝(Vinn-Vinp)*Cs-(VOn-VIp)*Cfn。
(3)在保持阶段，控制信号ctrl2控制开关S2、开关S5和开关S6断开，控制信号ctrl3控制开关S3断开，控制信号ctrl1控制开关S1断开，控制信号ctrl4控制开关S4和开关S7闭合。积分电容Cfp的两端分别连接全差分运算放大器的输入端和输出端，全差分运算放大器保持输出信号不变，积分电容Cfp的电荷保持不变，直至下一个采样周期。
基于上述介绍的工作过程可以确定，当ΔQs和ΔQfn不相等、也即自平衡差分信号积分放大电路达到自平衡之前的每个采样周期内，当切换到积分阶段后，采样电容Cs将电荷转移到两个网络中，转移到两个网络中的电荷量如上所述。且随着采样周期的变化，全差分运算放大器的输出信号VOn和VOp增大，由此使得采样电容Cs在采样阶段转移到平衡电容Cfn的电荷ΔQfn增大、负系数平衡网络实现的反向调节功能增强。
直至在经过若干个采样周期后，ΔQfn增大到与ΔQs相等时，自平衡差分信号积分放大电路达到自平衡，在此后的每个采样周期内，采样电容Cs向两个网络转移的电荷ΔQs全部转移到平衡电容Cfn中，而不再转移到积分电容Cfp中，从 而使得自平衡差分信号积分放大电路的输出信号稳定为放大K倍后的状态信号。如图4所示，差分输入端获取到的状态信号的电压置为Vinp-Vinn＝ΔV，则自平衡差分信号积分放大电路的输出信号随着采样周期逐步增大，直至最终稳定在VOp-VOn＝K×ΔV后，随着采样周期变化，自平衡差分信号积分放大电路的输出信号不再变化，达到稳定输出的效果。
请参考图4所示的采样电容Cs转移到两个网络中的电荷量ΔQs随着采样周期的变化示意图，从图4可以看出，随着采样周期的增多，采样电容Cs转移到积分电容Cfp的电荷ΔQfp逐步增少，采样电容Cs转移到平衡电容Cfn的电荷ΔQfn逐步增多直至达到ΔQs，之后的采样周期内，转移到负系数平衡网络的平衡电容Cfn的电荷ΔQfn均为ΔQs，转移到积分电容Cfp的电荷ΔQfp均为0。
且自平衡差分信号积分放大电路得到稳定状态对状态信号实现的放大倍数K由采样电容Cs的容值和平衡电容Cfn的容值决定。请结合图2，假设Cs＝M×Cfn，Cs是采样电容Cs的容值，Cfn为平衡电容Cfn的容值，M是正系数。可以推导确定Von＝Vcom-M*(Vinp-Vinn)，Vop＝Vcom+M*(Vinp-Vinn)，则可以得到，该自平衡差分信号积分放大电路达到稳定状态时实现的放大倍数因此通过调节采样电容Cs和平衡电容Cfn的比值，即可精确调节放大倍数K。
以上所述的仅是本申请的优选实施方式，本申请不限于以上实施例。可以理解，本领域技术人员在不脱离本申请的精神和构思的前提下直接导出或联想到的其他改进和变化，均应认为包含在本申请的保护范围之内。

Claims (10)

  1. 一种基于自平衡差分信号积分放大电路的芯片状态监控电路，其特征在于，所述芯片状态监控电路包括依次连接的状态感应电路、自平衡差分信号积分放大电路和模数转换器，所述模数转换器连接芯片内部的芯片配置电路，所述状态感应电路设置在芯片内部的待检测点处并感应得到所述芯片的差分形式的状态信号；
    所述自平衡差分信号积分放大电路包括全差分运算放大器、正系数积分网络和负系数平衡网络，两个网络均连接在所述全差分运算放大器的输入端和输出端之间；所述全差分运算放大器在所述正系数积分网络的作用下对所述状态信号实现信号放大功能、在所述负系数平衡网络的作用下对信号放大进行反向调节，且所述负系数平衡网络实现的反向调节功能逐渐增强直至所述自平衡差分信号积分放大电路达到自平衡，使得所述自平衡差分信号积分放大电路的输出信号稳定为放大K倍后的状态信号；
    放大K倍后的状态信号经过所述模数转换器的模数转换后输出给所述芯片配置电路。
  2. 根据权利要求1所述的芯片状态监控电路，其特征在于，所述自平衡差分信号积分放大电路还包括采样网络，所述采样网络采样所述状态信号的电荷；
    在所述自平衡差分信号积分放大电路达到自平衡之前，所述采样网络采样到的一部分电荷转移到所述正系数积分网络实现信号放大功能，所述采样网络采样到的另一部分电荷转移到所述负系数平衡网络实现信号放大的反向调节功能，所述自平衡差分信号积分放大电路的输出信号逐渐增大；且随着所述全差分运算放大器的输出信号的增大，所述采样网络转移到所述负系数平衡网络的电荷逐渐增大、使得所述负系数平衡网络实现的反向调节功能逐渐增强；
    在所述自平衡差分信号积分放大电路达到自平衡之后，所述采样网络采样到的电荷全部转移到所述负系数平衡网络，所述自平衡差分信号积分放大电路的输出信号稳定为放大K倍后的状态信号。
  3. 根据权利要求2所述的芯片状态监控电路，其特征在于，所述正系数积分网络基于积分电容Cfp搭建，所述负系数平衡网络基于平衡电容Cfn搭建，所述采样网络基于采样电容Cs搭建，所述自平衡差分信号积分放大电路稳定状态对所述状态信号实现的放大倍数K由采样电容Cs和平衡电容Cfn的容值决定。
  4. 根据权利要求3所述的芯片状态监控电路，其特征在于，所述自平衡差分信号积分放大电路稳定状态对所述状态信号实现的放大倍数其中，Cs表示采样电容Cs的容值，Cfn表示平衡电容Cfn的容值。
  5. 根据权利要求2所述的芯片状态监控电路，其特征在于，在每个采样周期内，所述自平衡差分信号积分放大电路依次经过采样阶段、积分阶段和保持阶段；
    在所述自平衡差分信号积分放大电路达到自平衡之前的每个采样周期内：在采样阶段，所述采样网络采样所述状态信号的电荷；在积分阶段，所述采样网络采样到的电荷转移到所述正系数积分网络和所述负系数平衡网络，使得所述自平衡差分信号积分放大电路的输出信号增大；在保持阶段，所述全差分运算放大器的输出信号保持不变；
    在经过若干个采样周期、所述自平衡差分信号积分放大电路达到自平衡之后的每个采样周期内：在采样阶段，所述采样网络采样所述状态信号的电荷；在积分阶段，所述采样网络采样到的电荷全部转移到所述负系数平衡网络，使得所述自平衡差分信号积分放大电路的输出信号保持不变；在保持阶段，所述全差分运算放大器的输出信号保持不变。
  6. 根据权利要求5所述的芯片状态监控电路，其特征在于，
    在所述自平衡差分信号积分放大电路达到自平衡之前的各个采样周期的积分阶段，所述全差分运算放大器开始工作，采样电容采样到的电荷转移到所述正系数积分网络中以及转移到所述负系数平衡网络中，且转移到所述负系数平衡网络中的电荷随着所述全差分运算放大器的输出信号的增大而增大，使得所述负系数平衡网络实现的反向调节功能逐渐增强。
  7. 根据权利要求5所述的芯片状态监控电路，其特征在于，所述自平衡差分信号积分放大电路还包括共模信号产生电路，所述共模信号产生电路连接所述全差分运算放大器的共模信号端Com；
    所述全差分运算放大器的正输入端Ip和负输出端On之间连接第一电路结构，所述全差分运算放大器的负输入端In和正输出端Op之间连接第二电路结构，第一电路结构与第二电路结构的电路结构对称；每个电路结构分别包括采样网络、正系数积分网络和负系数平衡网络；
    在所述自平衡差分信号积分放大电路的每个采样周期内，在采样阶段，所 述第一电路结构中的采样网络连接至所述自平衡差分信号积分放大电路的正差分输入端Vinp进行采样、所述第二电路结构中的采样网络连接至所述自平衡差分信号积分放大电路的负差分输入端Vinn进行采样；在积分阶段，切换为所述第一电路结构中的采样网络连接至所述自平衡差分信号积分放大电路的负差分输入端Vinn、所述第二电路结构中的采样网络连接至所述自平衡差分信号积分放大电路的正差分输入端Vinp，两个采样网络中的采样电容上变化的电压差将采样到的电荷转移到所在的电路结构中的正系数积分网络中的积分电容Cfp和负系数平衡网络中的平衡电容Cfn中。
  8. 根据权利要求7所述的芯片状态监控电路，其特征在于，所述第一电路结构包括：
    采样网络中的采样电容Cs的上极板通过开关S6连接所述自平衡差分信号积分放大电路的正差分输入端Vinp，采样电容Cs的上极板还通过开关S7连接所述自平衡差分信号积分放大电路的负差分输入端Vinn，采样电容Cs的下极板连接负系数平衡网络中的平衡电容Cfn的下极板，平衡电容Cfn的上极板通过开关S1连接所述全差分运算放大器的负输出端On；平衡电容Cfn的上极板还通过开关S2连接所述全差分运算放大器的共模信号端Com；采样电容Cs的下极板还通过开关S3连接正系数积分网络中的积分电容Cfp的下极板，积分电容Cfp的上极板通过开关S4连接所述全差分运算放大器的负输出端On；积分电容Cfp的下极板还连接所述全差分运算放大器的正输入端Ip，所述全差分运算放大器的正输入端Ip和负输出端On之间还通过开关S5跨接；
    其中，开关S1受控于控制信号ctrl1，开关S2、开关S5和开关S6均受控于控制信号ctrl2，开关S3受控于控制信号ctrl3，开关S4和开关S7受控于控制信号ctrl4。
  9. 根据权利要求8所述的芯片状态监控电路，其特征在于，所述第一电路结构在每个采样周期内的工作过程如下：
    在采样阶段，控制信号ctrl2控制开关S2、开关S5和开关S6闭合，控制信号ctrl3控制开关S3闭合，控制信号ctrl1控制开关S1断开，控制信号ctrl4控制开关S4和开关S7断开；第一电路结构中的采样电容Cs的上极板连接正差分输入端Vinp，所述全差分运算放大器的正输入端Ip和负输出端On短接，短接后的值连接到采 样电容Cs的下极板和平衡电容Cfn的下极板，平衡电容Cfn的上极板连接所述共模信号产生电路的输出端；积分电容Cfp中的电荷保持不变；
    在积分阶段，控制信号ctrl2控制开关S2、开关S5和开关S6断开，控制信号ctrl3控制开关S3闭合，控制信号ctrl1控制开关S1闭合，控制信号ctrl4控制开关S4和开关S7闭合，所述全差分运算放大器开始工作，第一电路结构中的采样电容Cs的上极板切换至连接负差分输入端Vinn，采样电容Cs的下极板、平衡电容Cfn的下极板和积分电容Cfp的下极板相连并连接所述全差分运算放大器的正输入端Ip；平衡电容Cfn的上极板和积分电容Cfp的上极板相连并连接所述全差分运算放大器的负输出端On；采样电容Cs上变化的电压差将采样到的电荷转移到平衡电容Cfn和积分电容Cfp上；
    在保持阶段，控制信号ctrl2控制开关S2、开关S5和开关S6断开，控制信号ctrl3控制开关S3断开，控制信号ctrl1控制开关S1断开，控制信号ctrl4控制开关S4和开关S7闭合；积分电容Cfp的两端分别连接所述全差分运算放大器的正输入端Ip和负输出端On，所述全差分运算放大器保持输出信号不变。
  10. 根据权利要求9所述的芯片状态监控电路，其特征在于，所述第一电路结构在每个采样周期内的工作过程如下：
    在采样阶段，采样电容Cs采样到的电荷为平衡电容Cfn中的电荷为积分电容Cfp中的电荷保持为上一个采样周期内的电荷量；
    在积分阶段，采样电容Cs采样到的电荷变为平衡电容Cfn中的电荷变为
    从采样阶段切换到积分阶段，采样电容Cs上变化的电压差导致采样电容Cs向两个网络转移的电荷为
    在保持阶段，积分电容Cfp的电荷保持不变，直至下一个采样周期；
    其中，在所述自平衡差分信号积分放大电路达到自平衡之前的每个采样周期内，切换到积分阶段后，采样电容Cs转移到所述负系数平衡网络的平衡电容Cfn的电荷为转移到所述正系数积分网络的积分电容Cfp的电荷为ΔQfp＝ΔQs-ΔQfn＝(Vinn-Vinp)*Cs-(VOn-VIp)*Cfn；
    随着采样周期的变化，所述全差分运算放大器的输出信号VOn和VOp增大，使得采样电容Cs转移到平衡电容Cfn的电荷ΔQfn增大、所述负系数平衡网络实现的反向调节功能逐渐增强；
    在经过若干个采样周期后，当ΔQs和ΔQfn相等时，所述自平衡差分信号积分放大电路达到自平衡，此后在所述自平衡差分信号积分放大电路达到自平衡之后的每个采样周期内，切换到积分阶段后，采样电容Cs向两个网络转移的电荷ΔQs全部转移到平衡电容Cfn中，而不再转移到积分电容Cfp中，所述自平衡差分信号积分放大电路的输出信号稳定为放大K倍后的状态信号；
    其中，Cs为采样电容Cs的容值，Cfn为平衡电容Cfn的容值，Vcom是所述共模信号产生电路输出给所述全差分运算放大器的共模信号端Com的电压值，Vinp是正差分输入端Vinp的电压值，Vinn是负差分输入端Vinn的电压值，VIp是所述全差分运算放大器的正输入端Ip的电压值，VOn是所述全差分运算放大器的负输出端On的电压值。
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