WO2024062980A1 - 積層セラミック電子部品及びその製造方法 - Google Patents

積層セラミック電子部品及びその製造方法 Download PDF

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Publication number
WO2024062980A1
WO2024062980A1 PCT/JP2023/033293 JP2023033293W WO2024062980A1 WO 2024062980 A1 WO2024062980 A1 WO 2024062980A1 JP 2023033293 W JP2023033293 W JP 2023033293W WO 2024062980 A1 WO2024062980 A1 WO 2024062980A1
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WIPO (PCT)
Prior art keywords
side margin
lamination
electronic component
ceramic electronic
cover layer
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PCT/JP2023/033293
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English (en)
French (fr)
Japanese (ja)
Inventor
島崎恭輔
西川潤
齋藤正貴
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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Priority to JP2024548219A priority Critical patent/JPWO2024062980A1/ja
Publication of WO2024062980A1 publication Critical patent/WO2024062980A1/ja
Priority to US19/072,380 priority patent/US20250201477A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/224—Housing; Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

Definitions

  • the present invention relates to a multilayer ceramic electronic component and a manufacturing method thereof.
  • a multilayer ceramic capacitor includes a laminated portion in which internal electrodes and dielectric layers are alternately laminated, and a side margin portion that covers both sides of the laminated portion (see, for example, Patent Documents 1 to 3).
  • the side margin portion is sometimes formed after the formation of the laminated portion in order to improve capacitance without requiring a design margin that takes into account printing accuracy of internal electrodes, lamination accuracy, etc.
  • a method of forming the side margin portion for example, there is a method of pressing the side surface of the laminated portion against the green sheet and separating a portion of the green sheet stuck to the side surface from the other portion as the side margin portion.
  • the side margin portion when the side margin portion is formed as described above, there is a risk that the side margin portion may peel off from the laminated portion due to stress caused by a difference in thermal contraction rate between the side margin portion and the laminated portion during the firing process of a multilayer ceramic capacitor, for example. If the side margin portion peels off, moisture may enter through the gap created by the peeling, and the characteristics of the multilayer ceramic capacitor may deteriorate.
  • the present invention has been made in view of the above problems, and an object thereof is to provide a multilayer ceramic electronic component that can suppress peeling of the side margin portion, and a method for manufacturing the same.
  • the multilayer ceramic electronic component of the present invention includes a plurality of internal electrode layers and a plurality of dielectric layers that are alternately laminated, and a cover provided on the outside in the lamination direction of the plurality of internal electrode layers and the plurality of dielectric layers.
  • a substantially rectangular parallelepiped-shaped laminated portion including a layer; a side margin portion provided on a side facing in a first direction substantially perpendicular to the lamination direction among the six surfaces of the laminated portion; an external electrode provided on an end face facing a second direction substantially orthogonal to the first direction and the lamination direction, and connected to the internal electrode layer;
  • a cross section of the laminated portion along one direction is viewed, in at least one corner of the laminated portion, a first end of the side margin portion in the lamination direction is a portion of the cover layer in the first direction. It is characterized by being in contact with the second end from the stacking direction.
  • the at least one corner may have a curved surface that is convex outward, and the first end may contact the curved surface provided at the second end from the stacking direction.
  • the ratio of the distance between the tip of the first end portion and the side surface in the first direction of the side margin portion to the thickness of the cover layer in the lamination direction is 0.2. It may be more than that.
  • the ratio of the distance between the tip of the first end portion and the side surface in the first direction of the side margin portion to the thickness of the cover layer in the lamination direction is 0.5. It may be more than that.
  • the ratio of the distance between the tip of the first end of the side margin portion in the first direction and the side surface to the thickness of the cover layer in the stacking direction may be 2.8 or less.
  • the ratio of the distance between the tip of the first end portion and the side surface in the first direction of the side margin portion to the thickness of the cover layer in the lamination direction is 1.0. It may be the following.
  • the distance between the tip of the first end and the side surface in the first direction is 2.1 to 240.2 ⁇ m
  • the thickness of the cover layer in the lamination direction is: It may be 11.2 to 85.2 ⁇ m.
  • the distance between the tip of the first end portion and the side surface in the first direction is 5.0 to 200.0 ⁇ m
  • the thickness of the cover layer in the lamination direction is: It may be 10.0 to 90.0 ⁇ m.
  • the distance between the tip of the first end portion and the side surface in the first direction is 10.0 to 90.0 ⁇ m
  • the thickness of the cover layer in the lamination direction is: It may be 20.0 to 55.0 ⁇ m.
  • the method for manufacturing a multilayer ceramic electronic component of the present invention includes a plurality of internal electrode layers and a plurality of dielectric layers that are alternately laminated, and a plurality of internal electrode layers and a plurality of dielectric layers that are provided on the outside in the lamination direction of the plurality of internal electrode layers and the plurality of dielectric layers.
  • polishing a substantially rectangular parallelepiped-shaped laminated portion including a covered cover layer, and forming a side margin portion on a side facing in a first direction substantially perpendicular to the lamination direction among six surfaces of the laminated portion; a step of forming an external electrode connected to the internal electrode layer on an end surface of the six surfaces of the laminated portion facing in a second direction substantially perpendicular to the first direction and the lamination direction; and the step of forming the side margin portion includes forming the side margin portion in at least one corner of the laminated portion when a cross section of the laminated portion along the lamination direction and the first direction is viewed.
  • a first end of the cover layer in the stacking direction is formed so as to be in contact with a second end of the cover layer in the first direction from the stacking direction.
  • the step of polishing the laminated portion forms an outwardly convex curved surface on the at least one corner
  • the step of forming the side margin portion includes It may be formed so as to be in contact with the curved surface provided at the second end from the stacking direction.
  • FIG. 1 is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment.
  • 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line AA in FIG. 1.
  • FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line BB in FIG. 1.
  • FIG. 2 is a cross-sectional view of a comparative multilayer ceramic capacitor taken along line BB in FIG. 1.
  • FIG. It is a flow chart showing an example of a manufacturing process of a multilayer ceramic capacitor. It is a sectional view showing an example of a lamination process. It is a side view of 2 s of laminated parts which shows an example of a polishing process.
  • FIG. 7 is a side view (part 2) showing an example of the side margin forming step when the end face of the laminated portion is viewed from the front.
  • FIG. 7 is a side view (part 3) showing an example of the side margin forming step when the end face of the laminated portion is viewed from the front.
  • FIG. 1 is a perspective view showing an example of a multilayer ceramic capacitor 1 according to an embodiment.
  • FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line AA in FIG.
  • FIG. 3A is a cross-sectional view of the multilayer ceramic capacitor 1 taken along the line BB in FIG.
  • the multilayer ceramic capacitor 1 is an example of a multilayer ceramic electronic component.
  • the multilayer ceramic capacitor 1 includes a multilayer chip 2 having a substantially rectangular parallelepiped shape, and external electrodes 3a and 3b provided on a pair of end faces 2A and 2B facing each other in the longitudinal direction of the multilayer chip 2.
  • FIG. 2, FIG. 3A, and FIG. 3B show an X direction, a Y direction, and a Z direction that are orthogonal to each other.
  • the X direction is the length (L) direction of the multilayer ceramic capacitor 1, and corresponds to the direction in which the pair of end faces of the multilayer chip 2 face each other.
  • the Y direction is the width (W) direction of the multilayer ceramic capacitor 1, and corresponds to the direction in which the pair of side surfaces of the multilayer chip 2 face each other.
  • the Z direction is the height (H) direction of the multilayer ceramic capacitor 1 and coincides with the stacking direction of the multilayer ceramic capacitor 1. Note that the width direction is an example of the first direction, and the length direction is an example of the second direction.
  • the multilayer chip 2 covers a substantially rectangular parallelepiped-shaped multilayer portion 2s having a multilayer structure and a pair of side surfaces 2E and 2F of the multilayer ceramic capacitor 1, which face each other in the width direction. It has a pair of side margin parts 40 and 41.
  • dielectric layers 22 containing a ceramic material functioning as a dielectric and internal electrode layers 23 are alternately laminated, and the dielectric layers 22 and internal electrode layers 23 are sandwiched from both sides in the lamination direction.
  • a pair of cover layers 20 and 21 are stacked on top of each other.
  • the side margin portions 40 and 41 are arranged adjacent to both ends of each internal electrode layer 23 that is drawn out and exposed to the pair of side surfaces 2E and 2F of the laminated portion 2s. Thereby, the cover layers 20 and 21 and the side margin parts 40 and 41 protect the internal electrode layer 23.
  • the internal electrode layer 23 is mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin).
  • the internal electrode layer 23 may contain noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or Sn, and an alloy containing these may be used as the main component of the internal electrode layer 23. It's okay.
  • the dielectric layer 22 has, for example, a ceramic material having a perovskite structure represented by the general formula ABO3 as a main phase.
  • the perovskite structure includes ABO 3- ⁇ that deviates from the stoichiometric composition.
  • the ceramic materials include BaTiO 3 (barium titanate), CaZrO 3 (calcium zirconate), CaTiO 3 (calcium titanate), SrTiO 3 (strontium titanate), MgTiO 3 (magnesium titanate), and perovskite structures. Select and use at least one of Ba 1-x-y Ca x Sry Ti 1-z Zr z O 3 (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ z ⁇ 1) to form.
  • Ba 1-x-y Ca x Sry Ti 1-z Zr z O 3 is barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, and zirconate titanate. Barium calcium, etc.
  • cover layers 20 and 21 mainly contain a ceramic material.
  • the material of the cover layers 20 and 21 is the same as that of the dielectric layer 22 in that the main component is a ceramic material.
  • the cover layers 20 and 21 are provided on the outside of each dielectric layer 22 in the lamination direction, and constitute the upper surface 2C and the lower surface 2D of the lamination section 2s in the lamination direction.
  • the side margin parts 40 and 41 are mainly made of ceramic material.
  • the main components of the side margin parts 40 and 41 are the same as that of the dielectric layer 22 and the ceramic material.
  • the side margin parts 40 and 41 are formed on the side surfaces 2E and 2F after the laminated part 2s is formed.
  • the external electrodes 3a and 3b respectively cover end surfaces 2A and 2B that face each other in the longitudinal direction of the stacked portion 2s.
  • the length direction is an example of a second direction substantially orthogonal to the stacking direction and the width direction, and is the direction in which the internal electrode layer 23 is drawn out.
  • the external electrodes 3a and 3b extend to the upper surface 2C, the lower surface 2D, and the two side surfaces 2E and 2F.
  • the external electrodes 3a and 3b are spaced apart from each other on the top surface 2C, bottom surface 2D, and two side surfaces 2E and 2F.
  • the external electrodes 3a and 3b have a base metal film containing a metal such as Cu, Ni, Al (aluminum), or Zn (zinc), or an alloy of two or more of these (for example, an alloy of Cu and Ni) as a main component. , a glass component for densification of the external electrodes 3a, 3b, and a common material for controlling the sinterability of the external electrodes 3a, 3b.
  • the glass components are oxides such as Ba (barium), Sr (strontium), Ca (calcium), Zn (zinc), Al, Si (silicon), and B (boron).
  • the common material is, for example, a ceramic component whose main component is the same material as the main component of the dielectric layer 22.
  • the external electrodes 3a and 3b may include a plating layer covering the base metal film.
  • the plating layer may have a base metal such as Ni, Cu, or Sn as a main component.
  • a layer of conductive resin such as epoxy resin and urethane resin may be formed between the underlying metal film and the plating layer.
  • each internal electrode layer 23 in the length direction are divided into an end surface 2A where the external electrode 3a of the laminated chip 2 is provided and an end surface 2B where the external electrode 3b is provided. They are alternately pulled out and exposed. Thereby, each internal electrode layer 23 is alternately electrically connected to the external electrodes 3a and 3b in the stacking direction. That is, the external electrodes 3a, 3b of each end surface 2A, 2B are alternately connected to each internal electrode layer 23 along the stacking direction.
  • each end of the side margin parts 40, 41 in the stacking direction is 4e is in contact with each end 20e, 21e in the width direction of the cover layers 20, 21 from the stacking direction. Thereby, each end 20e, 21e of the cover layers 20, 21 is covered by the end 4e of the side margin parts 40, 41.
  • Each end 20e, 21e of the cover layers 20, 21 has a curved shape with rounded corners by polishing.
  • the end portions 4e of the side margin portions 40, 41 in the stacking direction are extended to cover the central region in the width direction so as to ride on this curved region.
  • FIG. 3B is a cross-sectional view of the multilayer ceramic capacitor 1a for comparison along line BB in FIG. 1.
  • the comparative multilayer ceramic capacitor 1a has side margin parts 40a, 41a instead of the side margin parts 40, 41, and has cover layers 20a, 21a instead of the cover layers 20, 21.
  • the end portions 20ae, 21ae of the cover layers 20a, 21a in the width direction of the multilayer chip 2 are not curved but have substantially right angle corners. Therefore, the boundary between the end portions 4ae of the side margin portions 40a, 41a in the lamination direction and the end portions 20ae, 21ae of the cover layers 20a, 21a in the width direction is not a curve but a substantially straight line along the lamination direction. Therefore, the end portions 4ae of the side margin portions 40a, 41a are in contact with the end portions 20ae, 21ae of the cover layers 20a, 21a from the width direction, not from the stacking direction of the stacked chips 2.
  • each end 4e of the side margin parts 40, 41 in the stacking direction is connected to each end 20e, 21e of the cover layers 20, 21 in the width direction. Since the contact area between the side margin parts 40, 41 and the laminated part 2s is increased by the contact between the side margin parts 40, 41 and the laminated part 2s, the adhesion force of the side margin parts 40, 41 to the laminated part 2s is increased. Therefore, peeling of the side margin parts 40, 41 from the laminated part 2s is suppressed.
  • each end 4e of the side margin parts 40, 41 in the stacking direction of the stacked chip 2 is an example of a first end
  • each end 20e, 21e of the cover layers 20, 21 in the width direction of the stacked part 2s is This is an example of the second end.
  • Each corner 2r of the laminate 2s is formed with an outwardly convex curved surface, for example by barrel polishing.
  • the end 4e of the side margin 41 contacts the curved surface of the corner 2r provided at each end 20e, 21e of the cover layers 20, 21 from the lamination direction. For this reason, the end 4e of the side margin 40, 41 is formed to extend toward the center in the width direction along the curved surface of the corner 2r. Therefore, the contact area between the side margin 40, 41 and the laminate 2s is increased compared to when the corner 2r is formed with a flat surface rather than a curved surface, making it possible to increase the adhesion.
  • the thickness of the cover layer 20 in the lamination direction is b ⁇ m
  • the distance between the tip P of the end 4e of the side margin part 41 and the side surfaces 2E, 2F of the lamination part 2s in the width direction. is defined as a ⁇ m
  • the ratio of distance a to thickness b (a/b) is defined as a parameter R indicating the degree of bending.
  • the parameter R can be adjusted depending on the execution conditions (for example, time) of the barrel polishing of the laminated portion 2s, the density of the green sheets of the material of the cover layers 20 and 21, and the like.
  • the parameter R of the multilayer ceramic capacitor 1 of the embodiment is greater than zero.
  • the larger the parameter R is the more the adhesion between the side margin parts 40, 41 and the laminated part 2s increases, making it difficult for them to separate.
  • the larger the parameter R the longer the distance from the outside to the internal electrode layer 23 along the boundary between the side margin parts 40, 41 and the laminated part 2s. Since moisture easily enters the interior along the boundaries between the side margin parts 40, 41 and the laminated part 2s, the greater the parameter R, the longer the intrusion path becomes, and the moisture resistance of the multilayer ceramic capacitor 1 improves.
  • the parameter R is 0.2 or more, a sufficiently large adhesion force is obtained between the laminated portion 2s and the side margin portions 40, 41, so that peeling of the side margin portions 40, 41 can be suppressed more effectively. Furthermore, it is more preferable that the parameter R is 0.5 or more, since the path of moisture penetration becomes sufficiently long. Further, it is preferable that the parameter R is 2.8 or less because it facilitates the formation of the side margin portions 40 and 41. Furthermore, it is more preferable to set the parameter R to 1.0 or less, since the internal electrode layer 23 is less likely to be scraped even if the laminated portion 2s is polished, and loss of capacitance can be suppressed.
  • the distance a between the tip P and the side surfaces 2E and 2F shown in FIG. 3A is 2.1 to 240.2 ⁇ m, and the thickness b of the cover layer is 11.2 to 85.2 ⁇ m.
  • the ranges of distance a and thickness b in this way, a sufficiently wide area is secured for the side margin parts 40 and 41 to exhibit adhesion to the laminated part 2s, thereby suppressing separation of the side margin parts 40 and 41. can.
  • the distance a is set to 5.0 to 200.0 ⁇ m and the thickness b is set to 10.0 to 90.0 ⁇ m, the path for moisture to enter the laminated chip 2 from the outside becomes sufficiently long.
  • the distance a may be set to 10.0 to 90.0 ⁇ m
  • the thickness b may be set to 20.0 to 55.0 ⁇ m.
  • the distance a is preferably 200 ⁇ m or less, more preferably 90 ⁇ m or less. Further, since a sufficiently large adhesion force can be obtained between the laminated portion 2s and the side margin portions 40, 41, the distance a is preferably 5 ⁇ m or more, and more preferably 10 ⁇ m or more.
  • the distance b is preferably 90 ⁇ m or less, more preferably 55 ⁇ m or less. Furthermore, the longer the distance b, the stronger the multilayer ceramic capacitor 1 becomes against external shocks, and the longer the path for moisture to enter. Therefore, the distance b is preferably 10 ⁇ m or more, more preferably 20 ⁇ m or more.
  • FIG. 4 is a flowchart showing an example of the manufacturing process of the multilayer ceramic capacitor 1. This manufacturing process is an example of a method for manufacturing a laminated ceramic electronic component.
  • a green sheet forming step St1 is performed.
  • a dielectric material obtained by adding various additive compounds (sintering aids, etc.) to ceramic powder is mixed with a binder such as polyvinyl butyral (PVB) resin and an organic solvent such as ethanol or toluene. , plasticizer and wet-mix.
  • a dielectric green sheet is coated on a base material by, for example, a die coater method or a doctor blade method, and then dried.
  • the base material is, for example, a PET (polyethylene terephthalate) film.
  • the additive compounds of the ceramic powder include Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd ( oxides of gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium) and Yb (ytterbium)), as well as Co (cobalt), Ni, Li (lithium) , B (boron), Na (sodium), K (potassium), and Si (silicon) or glass.
  • an internal electrode printing step St2 is performed.
  • a plurality of internal electrode patterns corresponding to the internal electrode layer 23 are separated from each other by printing a metal conductive paste for forming internal electrodes containing an organic binder on a dielectric green sheet on a base material by gravure printing. to form a film.
  • Ceramic particles are added to the metal conductive paste as a co-material.
  • the main component of the ceramic particles is not particularly limited, it is preferably the same as the main component ceramic of the dielectric layer 22.
  • FIG. 5 is a cross-sectional view showing an example of the lamination step St3.
  • a laminated sheet 5S is formed by laminating dielectric green sheets 5 on which internal electrode patterns 6, which will become internal electrode layers 23, are printed.
  • Dielectric green sheets 5a and 5b corresponding to the cover layers 20 and 21 are laminated on both end faces of the laminated sheet 5S in the lamination direction, respectively.
  • a crimping step St4 is performed.
  • the plurality of dielectric green sheets 5, 5a, and 5b are bonded together by applying pressure to the laminated sheet 5S.
  • the compression means include, but are not limited to, a hydrostatic press.
  • a cutting step St5 is performed.
  • a plurality of laminated portions 2s are obtained by cutting the laminated sheet 5S in the lamination direction along a predetermined cut line LW using a cutting blade.
  • polishing process Next, a polishing step St6 is performed. This will be explained below with reference to FIG.
  • FIG. 6 is a side view of the laminated portion 2s showing an example of the polishing step St6.
  • FIG. 6 shows an end surface 2A of the laminated portion 2s before firing.
  • the laminated portion 2s is polished by a technique such as barrel polishing.
  • the corner portion 2r of the laminated portion 2s is rounded.
  • the parameter R can be adjusted within the above range by appropriately setting the execution conditions (for example, time) for barrel polishing the laminated portion 2s.
  • the distance a shown in FIG. 3A increases.
  • FIG. 7 to 9 are side views showing an example of the side margin forming step St7 when the end surface 2A of the laminated portion 2s is viewed from the front.
  • the process of forming the side margin part 41 on one side surface 2F is described, but the process of forming the side margin part 40 on the other side surface 2E is also similar.
  • a dielectric green sheet 91 is placed on the surface of a flat elastic body 92. Further, one side surface 2E of the laminated portion 2s is fixed with tape 90, and the laminated portion 2s is arranged above the other side surface 2F so as to face the surface of the dielectric green sheet 91.
  • the tape 90 is moved downward by a pressing device (not shown). As a result, the laminated portion 2s moves toward the dielectric green sheet 91 as indicated by the symbol D.
  • the side surface 2F of the laminated portion 2s is pressed against the surface of the dielectric green sheet 91, as shown in FIG.
  • the pressed portion of the dielectric green sheet 91 is depressed by the pressure from the laminated portion 2s, and the elastic body 92 below it is also depressed.
  • the corresponding portion of the dielectric green sheet 91 is pressed against the side surface 2F of the laminated portion 2s by the restoring force from the elastic body 92.
  • a portion of the dielectric green sheet 91 sticks to the side surface 2F.
  • the dielectric green sheets 91 are stuck along the corners 2r of the stacked portion 2s at both ends of the side surface 2F in the stacking direction. Thereafter, when the pressing force of the laminated portion 2s increases, a shearing force is generated between the portion where the dielectric green sheet 91 is stuck and the other portion, so that both portions are separated from each other.
  • the tape 90 is moved upward by a pressing device (not shown).
  • the laminated portion 2s moves away from the elastic body 92 as indicated by the symbol U.
  • the separated portion of the dielectric green sheet 91 sticks to the side surface 2F of the laminated portion 2s, and is formed as the side margin portion 41.
  • the side margin parts 41 and 40 are formed on the side surfaces 2F and 2E of the laminated part 2s, respectively, and the laminated part 2s before firing is produced.
  • the parameter R of the degree of bending of the corner portion 2r is too large, sufficient shearing force cannot be obtained when pressing the laminated portion 2s, so that the side margin portion 41 may not be formed normally. From this point of view, it is preferable to select the elastic body 92 that deforms more than the size of the corner 2r under a predetermined pressing force.
  • a repolishing step St8 is performed.
  • the laminated portion 2s on which the side margin portions 40 and 41 are formed is polished again by a technique such as barrel polishing. As a result, the corners of the side margin portions 40 and 41 are rounded.
  • an external electrode forming step St9 is performed. This process covers the pair of end faces 2A, 2B of the stacked chip 2 including the side margin parts 40, 41, respectively, and forms the base of the pair of external electrodes 3a, 3b alternately connected to the internal electrode layers 23 along the stacking direction.
  • a process of forming a metal film In this step, a conductive paste containing, for example, metal powder, glass frit, binder, and solvent is applied to each end surface 2A, 2B, upper surface 2C, lower surface 2D, and each side surface 2E, 2F of the laminated chip 2.
  • the base metal film of the external electrodes 3a and 3b is formed by baking. Note that the binder and solvent are evaporated by baking.
  • An example of a method for applying the conductive paste is a dipping method. Further, the base metal film of such external electrodes 3a, 3b may be formed by sputtering method.
  • a firing step St10 is performed.
  • the laminated chip 2 on which the external electrodes 3a and 3b are formed is subjected to binder removal treatment in an N2 atmosphere at 250 to 500°C, and then baked at 1300 to 1400°C for about 1 hour in a reducing atmosphere. , each particle in the laminated chip 2 is sintered. In this manner, the manufacturing process of the multilayer ceramic capacitor 1 is performed.
  • a plurality of layers of metal such as Cu, Ni, and Sn may be coated on the base metal film of each external electrode 3a, 3b by plating.
  • the external electrodes 3a and 3b may be formed by forming a Cu plating layer, a Ni plating layer, and a Sn plating layer on a base metal film mainly composed of Ni. Further, the external electrodes 3a and 3b may be formed by forming a Ni plating layer and a Sn plating layer on a base metal film containing Cu as a main component.
  • the end portions 4e of the side margin portions 40, 41 in the lamination direction extend in the width direction so as to cover the ends of the cover layers 20, 21 in the width direction.
  • this configuration only needs to be formed at at least one corner 2r.
  • the effect of suppressing peeling of the side margin portions 40 and 41 improves.
  • Table 1 shows sample No. 1 of multilayer ceramic capacitor 1a, 1.
  • the distance a from 1 to 9, the thickness b, the parameter R, the presence or absence of manufacturing defects, the number of pieces whose side margin parts 40 and 41 have peeled off, and the number of pieces whose moisture resistance is defective are shown.
  • Sample No. 1 to 9 were manufactured in 1000 pieces each according to the above manufacturing process and evaluated.
  • the distance a and the thickness b are 1000 samples No. It was calculated as the average value of 20 values extracted from 1 to 9.
  • the sizes of samples 1 to 9 are 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height.
  • the rated voltage of 1 to 9 was 10V.
  • Each sample No. The distance a, thickness b, and parameter R of 1 to 9 are different.
  • the distance a, the thickness b, and the parameter R were adjusted in the polishing step St6 described above.
  • Sample No. 2 to 9 are multilayer ceramic capacitors 1 of the embodiment shown in FIG. 3A.
  • Sample No. All corner portions 2r of the laminated portions 2 to 9 were formed with curved surfaces.
  • the ends 20e and 21e of the cover layers 20 and 21 were covered with the ends 4e of the side margin parts 40 and 41 at all corner parts 2r.
  • sample No. 1 is a comparative multilayer ceramic capacitor 1a shown in FIG. 3B. Sample No. No curved surface was formed at each corner of the laminated portion 2s of No. 1. The evaluation results are described below.
  • each sample No. It was confirmed whether the side margin parts 40 and 41 of Nos. 1 to 9 were formed normally. Sample No. with the largest parameter R. Only the side margin portions 40 and 41 of No. 9 were not formed properly, and the manufacturing defect was determined to be "present.” Other sample no. Side margin portions 40a, 41a, 40, and 41 of Nos. 1 to 8 were formed normally. Note that the number of confirmed samples is based on sample No. There were 1000 pieces for each of Nos. 1 to 8.
  • the parameter R is preferably 2.8 or less. Furthermore, it is more preferable to set the parameter R to 1.0 or less because the internal electrode layer 23 is less likely to be scraped in the polishing step St6 and loss of capacitance can be suppressed. In addition, sample No. Sample No. 9 was not evaluated for peeling and moisture resistance because the side margin portions 40 and 41 could not be formed properly.
  • each sample No. After applying a rated voltage of 10 V to 200 samples No. 1 to No. 8 under conditions of a temperature of 45° C. and a humidity of 95% and holding it for a predetermined time, each sample No. The electrical resistance of 1 to 7 was measured. A multilayer ceramic capacitor having an electrical resistance of 10 M ⁇ or more was determined to be “good”, and a multilayer ceramic capacitor having an electrical resistance of less than 10 M ⁇ was determined to be “bad”.
  • sample No. 1 whose parameter R is 0. Regarding No. 1, one out of 200 items was determined to be "defective.” On the other hand, other sample No. For items 2 to 8, all 200 items were judged to be "good.”
  • the smaller the parameter R the smaller the degree of bending of the corner 2r of the laminated portion 2s, and therefore the shorter the distance from the outside to the internal electrode layer 23 along the boundary between the side margin portions 40, 41 and the laminated portion 2s. Therefore, peeling of the side margin portions 40 and 41 causes moisture to enter the interior, which tends to affect the characteristics of the multilayer ceramic capacitor 1.
  • the parameter R is preferably 0.2 or more.
  • the parameter R is set to 0.3 or more because it is possible to obtain greater adhesion between the laminated portion 2s and the side margin portions 40 and 41.
  • the parameter R is 0.5 or more, since the path of moisture penetration becomes sufficiently long.
  • the distance a when the distance a is set to 2.1 to 240.2 ⁇ m and the thickness b of the cover layer is set to 11.2 to 85.2 ⁇ m, it is sufficient to exhibit the adhesion force of the side margin parts 40 and 41 to the laminated part 2s. Since a wide area is ensured, peeling of the side margin parts 40 and 41 can be suppressed. In this case, the moisture intrusion path becomes sufficiently long, so that the moisture resistance is further improved. Furthermore, if the distance a is set to 5.0 to 200.0 ⁇ m and the thickness b is set to 10.0 to 90.0 ⁇ m, the path for moisture to enter the laminated chip 2 from the outside becomes sufficiently long. Preferably, and more preferably, the distance a may be set to 10.0 to 90.0 ⁇ m, and the thickness b may be set to 20.0 to 55.0 ⁇ m.
  • the distance a is preferably 200 ⁇ m or less, more preferably 90 ⁇ m or less. Further, since a sufficiently large adhesion force can be obtained between the laminated portion 2s and the side margin portions 40 and 41, the distance a is preferably 5 ⁇ m or more, and more preferably 10 ⁇ m or more.
  • the distance b is preferably 90 ⁇ m or less, and more preferably 55 ⁇ m or less. Furthermore, the longer the distance b, the stronger the multilayer ceramic capacitor 1 is against external shocks, and the shorter the path for moisture intrusion. For this reason, the distance b is preferably 10 ⁇ m or more, and more preferably 20 ⁇ m or more.

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PCT/JP2023/033293 2022-09-20 2023-09-13 積層セラミック電子部品及びその製造方法 Ceased WO2024062980A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019102578A (ja) * 2017-11-30 2019-06-24 太陽誘電株式会社 積層セラミック電子部品及びその製造方法
JP2019106427A (ja) * 2017-12-11 2019-06-27 太陽誘電株式会社 積層セラミック電子部品及びその製造方法
JP2020004815A (ja) * 2018-06-27 2020-01-09 株式会社村田製作所 チップ型電子部品の製造方法
JP2021114512A (ja) * 2020-01-17 2021-08-05 株式会社村田製作所 積層セラミックコンデンサ
JP2021174821A (ja) * 2020-04-22 2021-11-01 株式会社村田製作所 積層セラミックコンデンサ

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019102578A (ja) * 2017-11-30 2019-06-24 太陽誘電株式会社 積層セラミック電子部品及びその製造方法
JP2019106427A (ja) * 2017-12-11 2019-06-27 太陽誘電株式会社 積層セラミック電子部品及びその製造方法
JP2020004815A (ja) * 2018-06-27 2020-01-09 株式会社村田製作所 チップ型電子部品の製造方法
JP2021114512A (ja) * 2020-01-17 2021-08-05 株式会社村田製作所 積層セラミックコンデンサ
JP2021174821A (ja) * 2020-04-22 2021-11-01 株式会社村田製作所 積層セラミックコンデンサ

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