WO2024060526A1 - 适用于pfm控制芯片的频率控制电路及相关装置 - Google Patents

适用于pfm控制芯片的频率控制电路及相关装置 Download PDF

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Publication number
WO2024060526A1
WO2024060526A1 PCT/CN2023/080678 CN2023080678W WO2024060526A1 WO 2024060526 A1 WO2024060526 A1 WO 2024060526A1 CN 2023080678 W CN2023080678 W CN 2023080678W WO 2024060526 A1 WO2024060526 A1 WO 2024060526A1
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resistor
control circuit
frequency control
frequency
source
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PCT/CN2023/080678
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English (en)
French (fr)
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杜得喜
江力
张涛
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深圳英集芯科技股份有限公司
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Publication of WO2024060526A1 publication Critical patent/WO2024060526A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/06—Frequency or rate modulation, i.e. PFM or PRM
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • This application relates to the field of electronic technology, and specifically to a frequency control circuit and related devices suitable for PFM control chips.
  • PWM pulse width modulation
  • PFM pulse frequency modulation
  • PSM Pulse Skip Modulation
  • the feedback voltage (FB) is detected by using a frequency control circuit to adjust the output frequency.
  • FB feedback voltage
  • the frequency change is most affected by FB, which will introduce the following risks: poor loop stability design, easy instability, audible noise, and valley lock failure for circuits with valley lock. Therefore, how to solve the above defects brought about by the PFM control mode needs to be solved urgently.
  • Embodiments of the present application provide a frequency control circuit and related devices suitable for PFM control chips, which can solve the audible noise problem at the frequency reduction point, the optimization valley locking problem, and the load near the frequency reduction point in the PFM control mode. Corresponding to the loop stability problem, at the same time, it can improve the efficiency of the system at light load.
  • inventions of the present application provide a frequency control circuit suitable for a PFM control chip.
  • the frequency control circuit includes: an operational amplifier circuit, a first current source, a second current source, a first NMOS transistor, and a second NMOS transistor. tube, the first PMOS tube, the second PMOS tube, the comparator and the pulse circuit, where,
  • the positive input terminal of the operational amplifier circuit is used to access the feedback voltage fed back after the system detects the output
  • the negative input terminal of the operational amplifier circuit is used to access the first current source, and is connected to the negative input terminal of the comparator through the first resistor, and is connected to the source of the first NMOS tube through the first resistor and the second resistor;
  • the output terminal of the operational amplifier circuit is connected to the gate of the first NMOS tube;
  • the first current source is connected to an external power supply;
  • the source of the first NMOS transistor is connected to ground through a third resistor; the drain of the first NMOS transistor is connected to the drain and gate of the first PMOS transistor; the drain of the first NMOS transistor is connected to the ground through the second resistor.
  • the current source is grounded;
  • the source and substrate of the first PMOS transistor and the source and substrate of the second PMOS transistor are both connected to the external power supply; the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor. pole; the drain of the second PMOS tube is connected to the positive input terminal of the comparator and grounded through a capacitor, and the drain of the second PMOS tube is connected to the drain of the second NMOS tube; the second NMOS The gate of the tube is connected to the output terminal of the pulse circuit, and the source of the second NMOS tube is connected to ground; the output terminal of the comparator is connected to the input terminal of the pulse circuit, and the output terminal of the pulse circuit is used for output. frequency signal.
  • embodiments of the present application provide a PFM control chip, which includes the frequency control circuit described in the first aspect.
  • embodiments of the present application provide a switching power supply, characterized in that the switching power supply includes a frequency control circuit as described in the first aspect, or a PFM control chip as described in the second aspect.
  • an embodiment of the present application provides a charger, characterized in that the charger includes the frequency control circuit as described in the first aspect, or the PFM control chip as described in the second aspect, or the switching power supply as described in the third aspect.
  • the frequency control circuit and related devices suitable for PFM control chips described in the embodiments of the present application include: an operational amplifier circuit, a first current source, a second current source, a first NMOS transistor, a third Two NMOS tubes, a first PMOS tube, a second PMOS tube, a comparator and a pulse circuit, wherein the positive input terminal of the operational amplifier circuit is used to connect the feedback voltage, and the negative input terminal of the operational amplifier circuit is used to connect the first current source, and is connected to the negative input terminal of the comparator through the first resistor, and is connected to the source of the first NMOS tube through the first resistor and the second resistor; the output terminal of the operational amplifier circuit is connected to the gate of the first NMOS tube; the first The current source is connected to the external power supply; the source of the first NMOS tube is connected to the ground through the third resistor; the drain of the first NMOS tube is connected to the drain and gate of the first PMOS tube; the drain of the first NMOS tube is connected
  • the positive input terminal of the comparator is connected to the positive input terminal of the comparator and the ground through the capacitor, the drain of the second PMOS tube is connected to the drain of the second NMOS tube; the gate of the second NMOS tube is connected to the output terminal of the pulse circuit, and the source of the second NMOS tube Grounded; the output end of the comparator is connected to the input end of the pulse circuit.
  • the output end of the pulse circuit is used to output a frequency signal, which can solve the audible noise problem at the frequency reduction point, optimize the valley locking problem, and correspond to the load near the frequency reduction point. Loop stability issues while improving system efficiency at light loads.
  • Figure 1 is a schematic structural diagram of a frequency control circuit suitable for a PFM control chip provided by an embodiment of the present application;
  • Figure 2 is a schematic diagram illustrating the relationship between FB and FRE provided by an embodiment of the present application.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Explicitly and implicitly understood by those skilled in the art Yes, the embodiments described herein may be combined with other embodiments.
  • Figure 1 is a schematic structural diagram of a frequency control circuit suitable for a PFM control chip provided by an embodiment of the present application.
  • the frequency control circuit includes: an operational amplifier circuit OP, a first current source I1, a second current Source I2, first NMOS transistor MN0, second NMOS transistor MN1, first PMOS transistor MP0, second PMOS transistor MP1, comparator CMP and pulse circuit PULSE, where,
  • the positive input terminal (+) of the operational amplifier circuit OP is used to connect to the feedback voltage FB, and the negative input terminal (-) of the operational amplifier circuit OP is used to connect to the first current source I1, and through the first Resistor R1 is connected to the negative input terminal (-) of the comparator CMP, and is connected to the source of the first NMOS transistor (MN0) through the first resistor R1 and the second resistor R2; the operational amplifier circuit OP
  • the output terminal (-) is connected to the gate of the first NMOS transistor (MN0); the first current source I1 is connected to the external power supply VCC;
  • the source of the first NMOS transistor MN0 is connected to the ground through the third resistor R3; the drain of the first NMOS transistor MN0 is connected to the drain and gate of the first PMOS transistor MP0; the drain of the first NMOS transistor MN0 Grounded through the second current source I2;
  • the source and substrate of the first PMOS transistor MP0 and the source and substrate of the second PMOS transistor MP1 are both connected to the external power supply VCC; the gate of the first PMOS transistor MP0 is connected to the second The gate of the PMOS tube MP1; the drain of the second PMOS tube MP1 is connected to the positive input terminal (+) of the comparator CMP and grounded through the capacitor C1, and the drain of the second PMOS tube MP1 is connected to the first The drains of two NMOS transistors MN1; the gate of the second NMOS transistor MN1 is connected to the output end of the pulse circuit PULSE, the source electrode of the second NMOS transistor MN1 is connected to ground; the output end of the comparator CMP is connected to the The input terminal of the pulse circuit PULSE, and the output terminal of the pulse circuit PULSE are used to output the frequency signal FRE.
  • the operational amplifier circuit OP current sources I1, I2, resistors R1, R2 and R3, NMOS tubes MN0 and MN1, PMOS tubes MP0 and MP1, capacitor C1, comparator CMP and pulse circuit PULSE form a frequency control circuit.
  • the frequency control circuit can be used in a switching power supply control chip to solve the audible noise problem at the frequency reduction point, optimize the valley locking problem, and the loop stability problem corresponding to the load near the frequency reduction point, while improving the efficiency of the system at light load.
  • the frequency control circuit is used to implement the following functions:
  • a first control current related to the feedback voltage FB is generated through the operational amplifier circuit OP, the third resistor R3 and the first NMOS transistor MN0;
  • a second control current is obtained, and the second control current is used to charge the capacitor C1,
  • the second control current is a ramp signal, and K is greater than 1;
  • a fixed voltage is generated through the first current source I1 and the first resistor R1;
  • the difference voltage between the feedback voltage FB and the fixed voltage is used as the threshold of the comparator CMP, and the threshold is used to provide corresponding thresholds for different loads.
  • the operational amplifier circuit OP, R3 and MN0 are used to generate a current related to FB, and then, Reduce the current through MP0 and MP1 by 1/K times and then charge the capacitor C1 to generate a ramp signal, which then passes through I1 and R1 to generate a fixed voltage.
  • the FB voltage minus this voltage is used as the threshold of the comparator.
  • the characteristics of this threshold It changes with the change of FB, which provides different thresholds for different loads.
  • the threshold can be FB minus the fixed voltage value on R1, so it actually controls the fixed voltage value on R1. Different frequency curves can be obtained, and the results are shown in Figure 2. That is, as long as the threshold is controlled well, the required frequency curve can be obtained.
  • the frequency control circuit is also used to implement the following functions:
  • the pulse circuit controls the opening and closing of the second NMOS transistor and the voltage of the capacitor to obtain a frequency related to the feedback voltage.
  • the PULSE circuit is used to control the opening and closing of MN1 to reset the voltage of the capacitor C1. Finally, a frequency related to FB is obtained.
  • the frequency control circuit is also used to implement the following functions:
  • f represents the frequency signal
  • FB represents the feedback voltage
  • I1 represents the current value of the first current source
  • R1 represents the resistance of the first resistor
  • R2 represents the resistance of the second resistor
  • R3 represents the resistance of the third resistor
  • C1 represents the capacitance of the capacitor.
  • the second current source is used to offset the current error introduced by the first current source.
  • I2 is used to offset the current error introduced by I1.
  • the pulse width of the pulse circuit should be as small as possible, which can reduce the error value of the final frequency.
  • the frequency control circuit described in the embodiment of this application is suitable for the PFM control chip.
  • the frequency control circuit includes: an operational amplifier circuit, a first current source, a second current source, a first NMOS transistor, and a second NMOS transistor.
  • a first PMOS tube, a second PMOS tube, a comparator and a pulse circuit wherein the positive input terminal of the operational amplifier circuit is used to connect to the feedback voltage, and the negative input terminal of the operational amplifier circuit is used to connect to the first current source, and The negative input terminal of the comparator is connected through the first resistor, and the source of the first NMOS tube is connected through the first resistor and the second resistor; the output terminal of the operational amplifier circuit is connected to the gate of the first NMOS tube; the first current source is connected External power supply; the source of the first NMOS tube is connected to the ground through the third resistor; the drain of the first NMOS tube is connected to the drain and gate of the first PMOS tube; the drain of the first NMOS tube is connected to the ground through the second current source; The source and substrate of one PMOS tube and the source and substrate of the second PMOS tube are both connected to the external power supply; the gate of the first PMOS tube is connected to the gate of the second PMOS tube; the drain of the second PMOS tube
  • the output end of the pulse circuit is used to output a frequency signal, which can solve the audible noise problem at the frequency reduction point, optimize the valley locking problem, and stabilize the loop corresponding to the load near the frequency reduction point. performance issues while improving the efficiency of the system under light load.
  • a PFM control chip can also be provided, which includes the above frequency control circuit.
  • the PFM control chip can solve the problem of audible noise appearing at the frequency reduction point, optimize the valley locking problem, and solve the problem of load near the frequency reduction point. Corresponds to loop stability issues and improves system efficiency at light load.
  • a switching power supply can also be provided, which includes the above-mentioned frequency control circuit, or the above-mentioned PFM control chip.
  • the frequency control circuit can solve the audible noise problem that occurs at the frequency reduction point, optimize the valley locking problem, and It solves the loop stability problem corresponding to the load near the frequency reduction point and improves the efficiency of the system at light load.
  • a charger may also be provided, which includes the above-mentioned frequency control circuit, or the above-mentioned PFM control chip, or the above-mentioned switching power supply.
  • the frequency control circuit can solve the problem of audible noise occurring at the frequency reduction point. Optimize the valley locking problem and the loop stability problem corresponding to the load near the frequency reduction point, while improving the efficiency of the system at light load.

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  • Power Engineering (AREA)
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Abstract

本申请提供了一种适用于PFM控制芯片的频率控制电路及相关装置，该频率控制电路中运放电路的正输入端接入系统检测输出后反馈的反馈电压、负输入端接入第一电流源，通过第一电阻连接比较器的负输入端，通过第一电阻和第二电阻连接第一NMOS管的源极；运放电路的输出端连接第一NMOS管的栅极；第一NMOS管的漏极连接第一PMOS管的漏极和栅极；第一PMOS管的源极和衬底与第二PMOS管的源极和衬底连接外部电源；第一PMOS管的栅极连接第二PMOS管的栅极；第二PMOS管的漏极连接第二NMOS管的漏极；第二NMOS管的栅极连接脉冲电路；比较器连接脉冲电路的输入端。本申请实施例能够降频点出现的可闻噪声问题。

Description

适用于PFM控制芯片的频率控制电路及相关装置
本申请要求于2022年09月21日提交中国专利局、申请号为202211146921.X、申请名称为“适用于PFM控制芯片的频率控制电路及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，具体涉及一种适用于PFM控制芯片的频率控制电路及相关装置。
背景技术
在目前流行的开关电源控制芯片中，常见的主要控制技术可以分为三种，脉冲宽度调制(PWM，Pulse Width Modulation)、脉冲频率调制(PFM，Pulse Frequency Modulation)和(PSM，Pulse Skip Modulation)。
实际应用中，在PFM控制方式下，通过使用频率控制电路检测反馈电压(FB)，进而调节频率大小的输出。但是，在降频点附近，频率的变化受FB的影响最大，将会引入以下风险：环路稳定性不好设计，容易不稳定，出现可闻噪声，对于有谷底锁定电路，谷底锁定失效，因此，如何解决在PFM控制方式下带来的上述缺陷的问题亟待解决。
发明内容
本申请实施例提供了一种适用于PFM控制芯片的频率控制电路及相关装置，能够解决在PFM控制方式下，降频点出现的可闻噪声问题、优化谷底锁定问题、以及降频点附近负载所对应环路稳定性问题，同时，能够提高系统在轻载时的效率。
第一方面，本申请实施例提供一种适用于PFM控制芯片的频率控制电路，所述频率控制电路包括：运放电路、第一电流源、第二电流源、第一NMOS管、第二NMOS管、第一PMOS管、第二PMOS管、比较器和脉冲电路，其中，
所述运放电路的正输入端用于接入系统检测输出后反馈的反馈电压，所述运放电路的负输入端用于接入所述第一电流源，且通过第一电阻连接所述比较器的负输入端，以及通过所述第一电阻和第二电阻连接所述第一NMOS管的源极；所述运放电路的输出端连接所述第一NMOS管的栅极；所述第一电流源连接外部电源；
所述第一NMOS管的源极通过第三电阻接地；所述第一NMOS管的漏极连接第一PMOS管的漏极和栅极；所述第一NMOS管的漏极通过所述第二电流源接地；
所述第一PMOS管的源极和衬底与所述第二PMOS管的源极和衬底均连接所述外部电源；所述第一PMOS管的栅极连接所述第二PMOS管的栅极；所述第二PMOS管的漏极连接所述比较器的正输入端以及通过电容接地，所述第二PMOS管的漏极连接所述第二NMOS管的漏极；所述第二NMOS管的栅极连接所述脉冲电路的输出端，所述第二NMOS管的源极接地；所述比较器的输出端连接所述脉冲电路的输入端，所述脉冲电路的输出端用于输出频率信号。
第二方面，本申请实施例提供一种PFM控制芯片，所述PFM控制芯片包括如第一方面所述的频率控制电路。
第三方面，本申请实施例提供一种开关电源，其特征在于，所述开关电源包括如第一方面所述的频率控制电路，或者，如第二方面所述的PFM控制芯片。
第四方面，本申请实施例提供一种充电器，其特征在于，所述充电器包括如第一方面所述的频率控制电路，或者，如第二方面所述的PFM控制芯片，或者，如第三方面所述的开关电源。
实施本申请实施例，具备如下有益效果：
可以看出，本申请实施例中所描述的适用于PFM控制芯片的频率控制电路及相关装置，频率控制电路包括：运放电路、第一电流源、第二电流源、第一NMOS管、第二NMOS管、第一PMOS管、第二PMOS管、比较器和脉冲电路，其中，运放电路的正输入端用于接入反馈电压，运放电路的负输入端用于接入第一电流源，且通过第一电阻连接比较器的负输入端，以及通过第一电阻和第二电阻连接第一NMOS管的源极；运放电路的输出端连接第一NMOS管的栅极；第一电流源连接外部电源；第一NMOS管的源极通过第三电阻接地；第一NMOS管的漏极连接第一PMOS管的漏极和栅极；第一NMOS管的漏极通过第二电流源接地；第一PMOS管的源极和衬底与第二PMOS管的源极和衬底均连接外部电源；第一PMOS管的栅极连接第二PMOS管的栅极；第二PMOS管的漏极连接比较器的正输入端以及通过电容接地，第二PMOS管的漏极连接第二NMOS管的漏极；第二NMOS管的栅极连接脉冲电路的输出端，第二NMOS管的源极接地；比较器的输出端连接脉冲电路的输入端，脉冲电路的输出端用于输出频率信号，可以解决降频点出现的可闻噪声问题，优化谷底锁定问题，以及降频点附近负载所对应环路稳定性问题，同时提高系统在轻载时的效率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种适用于PFM控制芯片的频率控制电路的结构示意图；
图2是本申请实施例提供的一种FB与FRE之间关系的演示示意图。
具体实施方式
为了本技术领域人员更好理解本申请的技术方案，下面结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的部分实施例，而并非全部的实施例。基于本申请实施例的描述，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请所保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如，包含了一系列步骤或单元的过程、方法、软件、产品或设备没有限定于已列出的步骤或单元，而是还包括没有列出的步骤或单元，或还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的 是，本文所描述的实施例可以与其它实施例相结合。
下面结合附图对本申请实施例进行介绍，附图中相交导线的交叉处有圆点表示导线相接，交叉处无圆点表示导线不相接。
请参阅图1，图1是本申请实施例提供的一种适用于PFM控制芯片的频率控制电路的结构示意图，所述频率控制电路包括：运放电路OP、第一电流源I1、第二电流源I2、第一NMOS管MN0、第二NMOS管MN1、第一PMOS管MP0、第二PMOS管MP1、比较器CMP和脉冲电路PULSE，其中，
所述运放电路OP的正输入端(+)用于接入反馈电压FB，所述运放电路OP的负输入端(-)用于接入所述第一电流源I1，且通过第一电阻R1连接所述比较器CMP的负输入端(-)，以及通过所述第一电阻R1和第二电阻R2连接所述第一NMOS管(MN0)的源极；所述运放电路OP的输出端(-)连接所述第一NMOS管(MN0)的栅极；所述第一电流源I1连接外部电源VCC；
所述第一NMOS管MN0的源极通过第三电阻R3接地；所述第一NMOS管MN0的漏极连接第一PMOS管MP0的漏极和栅极；所述第一NMOS管MN0的漏极通过所述第二电流源I2接地；
所述第一PMOS管MP0的源极和衬底与所述第二PMOS管MP1的源极和衬底均连接所述外部电源VCC；所述第一PMOS管MP0的栅极连接所述第二PMOS管MP1的栅极；所述第二PMOS管MP1的漏极连接所述比较器CMP的正输入端(+)以及通过电容C1接地，所述第二PMOS管MP1的漏极连接所述第二NMOS管MN1的漏极；所述第二NMOS管MN1的栅极连接所述脉冲电路PULSE的输出端，所述第二NMOS管MN1的源极接地；所述比较器CMP的输出端连接所述脉冲电路PULSE的输入端，所述脉冲电路PULSE的输出端用于输出频率信号FRE。
具体实现中，运放电路OP，电流源I1、I2，电阻R1、R2和R3，NMOS管MN0、MN1，PMOS管MP0、MP1，电容C1、比较器CMP和脉冲电路PULSE构成了频率控制电路。
实际应用中，在降频点如果频率斜率太大，就会常出现频率变化太大，导致输出纹波变大，进而影响FB电压，反馈到芯片，又影响到频率，导致频率忽高忽低，从而出现可闻噪声、严重引起环路稳定性、以及锁谷问题。
本申请实施例中，频率控制电路，其可以用在开关电源控制芯片中。可以解决降频点出现的可闻噪声问题，优化谷底锁定问题，以及降频点附近负载所对应环路稳定性问题，同时提高系统在轻载时的效率。
可选的，所述频率控制电路用于实现如下功能：
通过所述运放电路OP、所述第三电阻R3和所述第一NMOS管MN0产生一个与所述反馈电压FB相关的第一控制电流；
将所述第一控制电流通过所述第一PMOS管MP0、所述第二PMOS管MP1缩小1/K倍后，得到第二控制电流，该第二控制电流用于给所述电容C1充电，所述第二控制电流为一斜坡信号，K为大于1；
通过所述第一电流源I1和所述第一电阻R1产生一固定电压；
将所述反馈电压FB与所述固定电压之间的差值电压作为所述比较器CMP的阈值，该阈值用于给不同的负载提供相应的阈值。
本申请实施例中，利用运放电路OP，R3和MN0产生一个和FB相关的电流，然后，再 将该电流通过MP0、MP1减小1/K倍后给电容C1充电，产生一个斜坡信号，再通过I1，R1产生一个固定电压，FB电压减去该电压作为比较器的阈值，该阈值的特点是随着FB的变化而变化，这就为不同负载提供了不同的阈值，具体的，该阈值具体可以为FB减去R1上的固定电压值，所以实际上是控制R1上的固定电压值，就可以得到不同频率曲线，其结果如图2所示。即只要控制好该阈值，就可以得到需要的频率曲线。
可选的，所述频率控制电路还用于实现如下功能：
通过所述脉冲电路控制所述第二NMOS管的开断以及所述电容的电压，得到与所述反馈电压相关的频率。
然后通过比较器CMP比较这两个值后，再通过PULSE电路控制MN1的开断，复位电容C1的电压。最终得到一个和FB相关的频率。
可选的，所述频率控制电路还用于实现如下功能：
按照如下公式确定所述频率信号：
f＝(FB-I1*R1-I1*R2)/(R3*C1*K*(FB-I1*R1))
其中，f表示所述频率信号，FB表示所述反馈电压，I1表示所述第一电流源的电流值，R1表示所述第一电阻的阻值，R2表示所述第二电阻的阻值，R3表示所述第三电阻的阻值，C1表示所述电容的电容值。
可选的，所述第二电流源用于抵消所述第一电流源引入的电流误差。
其中，I2是用来抵消I1引入电流误差，脉冲电路的脉冲宽度尽量小，可以减小最终得到频率的误差值。
通过以上对以上电路元件取不同的值进行仿真，可以得到图2所示的FB与频率FRE的关系图。
举例说明下，如图2所示，实际仿真实验中，假设A为I1*R1的值，可以得到，通过调节A的值，实现频率曲线曲率的调节，满足不同系统的需求。同时从实际的仿真曲线图中可以发现，在降频点附近，频率变化缓慢，避免可闻噪声产生，优化谷底锁定问题。到轻载时，频率变化加快，提高了轻载的效率。
可以看出，本申请实施例中所描述的适用于PFM控制芯片的频率控制电路，频率控制电路包括：运放电路、第一电流源、第二电流源、第一NMOS管、第二NMOS管、第一PMOS管、第二PMOS管、比较器和脉冲电路，其中，运放电路的正输入端用于接入反馈电压，运放电路的负输入端用于接入第一电流源，且通过第一电阻连接比较器的负输入端，以及通过第一电阻和第二电阻连接第一NMOS管的源极；运放电路的输出端连接第一NMOS管的栅极；第一电流源连接外部电源；第一NMOS管的源极通过第三电阻接地；第一NMOS管的漏极连接第一PMOS管的漏极和栅极；第一NMOS管的漏极通过第二电流源接地；第一PMOS管的源极和衬底与第二PMOS管的源极和衬底均连接外部电源；第一PMOS管的栅极连接第二PMOS管的栅极；第二PMOS管的漏极连接比较器的正输入端以及通过电容接地，第二PMOS管的漏极连接第二NMOS管的漏极；第二NMOS管的栅极连接脉冲电路的输出端，第二NMOS管的源极接地；比较器的输出端连接脉冲电路的输入端，脉冲电路的输出端用于输出频率信号，可以解决降频点出现的可闻噪声问题，优化谷底锁定问题，以及降频点附近负载所对应环路稳定性问题，同时提高系统在轻载时的效率。
本申请实施例中，还可以提供一种PFM控制芯片，其包括上述频率控制电路，通过PFM控制芯片可以解决降频点出现的可闻噪声问题，优化谷底锁定问题，以及降频点附近负载所 对应环路稳定性问题，同时提高系统在轻载时的效率。
本申请实施例中，还可以提供一种开关电源，其包括上述频率控制电路，或者，上述PFM控制芯片，通过频率控制电路可以解决降频点出现的可闻噪声问题，优化谷底锁定问题，以及降频点附近负载所对应环路稳定性问题，同时提高系统在轻载时的效率。
本申请实施例中，还可以提供一种充电器，其包括上述频率控制电路，或者，上述PFM控制芯片，或者，上述开关电源，通过频率控制电路可以解决降频点出现的可闻噪声问题，优化谷底锁定问题，以及降频点附近负载所对应环路稳定性问题，同时提高系统在轻载时的效率。
以上是本申请实施例的实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请实施例原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (9)

  1. 一种适用于PFM控制芯片的频率控制电路，其特征在于，所述频率控制电路包括：运放电路、第一电流源、第二电流源、第一NMOS管、第二NMOS管、第一PMOS管、第二PMOS管、比较器和脉冲电路，其中，
    所述运放电路的正输入端用于接入系统检测输出后反馈的反馈电压，所述运放电路的负输入端用于接入所述第一电流源，且通过第一电阻连接所述比较器的负输入端，以及通过所述第一电阻和第二电阻连接所述第一NMOS管的源极；所述运放电路的输出端连接所述第一NMOS管的栅极；所述第一电流源连接外部电源；
    所述第一NMOS管的源极通过第三电阻接地；所述第一NMOS管的漏极连接第一PMOS管的漏极和栅极；所述第一NMOS管的漏极通过所述第二电流源接地；
    所述第一PMOS管的源极和衬底与所述第二PMOS管的源极和衬底均连接所述外部电源；所述第一PMOS管的栅极连接所述第二PMOS管的栅极；所述第二PMOS管的漏极连接所述比较器的正输入端以及通过电容接地，所述第二PMOS管的漏极连接所述第二NMOS管的漏极；所述第二NMOS管的栅极连接所述脉冲电路的输出端，所述第二NMOS管的源极接地；所述比较器的输出端连接所述脉冲电路的输入端，所述脉冲电路的输出端用于输出频率信号。
  2. 根据权利要求1所述的频率控制电路，其特征在于，所述频率控制电路用于实现如下功能：
    通过所述运放电路、所述第三电阻和所述第一NMOS管产生一个与所述反馈电压相关的第一控制电流；
    将所述第一控制电流通过所述第一PMOS管、所述第二PMOS管缩小1/K倍后，得到第二控制电流，该第二控制电流用于给所述电容充电，所述第二控制电流为一斜坡信号，K为大于1；
    通过所述第一电流源和所述第一电阻产生一固定电压；
    将所述反馈电压与所述固定电压之间的差值电压作为所述比较器的阈值，该阈值用于给不同的负载提供相应的阈值。
  3. 根据权利要求2所述的频率控制电路，其特征在于，所述频率控制电路还用于实现如下功能：
    通过所述脉冲电路控制所述第二NMOS管的开断以及所述电容的电压，得到与所述反馈电压相关的频率。
  4. 根据权利要求2所述的频率控制电路，其特征在于，所述频率控制电路还用于实现如下功能：
    按照如下公式确定所述频率信号：
    f＝(FB-I1*R1-I1*R2)/(R3*C1*K*(FB-I1*R1))
    其中，f表示所述频率信号，FB表示所述反馈电压，I1表示所述第一电流源的电流值，R1表示所述第一电阻的阻值，R2表示所述第二电阻的阻值，R3表示所述第三电阻的阻值，C1表示所述电容的电容值。
  5. 根据权利要求1-4任一项所述的频率控制电路，其特征在于，所述第二电流源用于抵消所述第一电流源引入的电流误差。
  6. 根据权利要求1-4任一项所述的频率控制电路，其特征在于，所述脉冲电路的脉冲宽度小于预设阈值。
  7. 一种PFM控制芯片，其特征在于，所述PFM控制芯片包括如权利要求1-6任一项所述的频率控制电路。
  8. 一种开关电源，其特征在于，所述开关电源包括如权利要求1-6任一项所述的频率控制电路，或者，如权利要求7所述的PFM控制芯片。
  9. 一种充电器，其特征在于，所述充电器包括如权利要求1-6任一项所述的频率控制电路，或者，如权利要求7所述的PFM控制芯片，或者，如权利要求8所述的开关电源。
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