WO2024060355A1 - 像素电路及其驱动方法和显示面板 - Google Patents

像素电路及其驱动方法和显示面板 Download PDF

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Publication number
WO2024060355A1
WO2024060355A1 PCT/CN2022/128102 CN2022128102W WO2024060355A1 WO 2024060355 A1 WO2024060355 A1 WO 2024060355A1 CN 2022128102 W CN2022128102 W CN 2022128102W WO 2024060355 A1 WO2024060355 A1 WO 2024060355A1
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WIPO (PCT)
Prior art keywords
module
node
transistor
compensation
voltage
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PCT/CN2022/128102
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English (en)
French (fr)
Inventor
林兆敏
王峥
唐韬
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昆山国显光电有限公司
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Publication of WO2024060355A1 publication Critical patent/WO2024060355A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present application relates to the field of display technology, and in particular, to a pixel circuit, a driving method thereof, and a display panel.
  • a display panel usually includes multiple pixel circuits.
  • the size of the driving current flowing through the light-emitting module in the pixel circuit determines the luminous brightness of the display panel.
  • Existing display panels have leakage problems, which affects the display effect.
  • the present application provides a pixel circuit and a driving method thereof and a display panel, so as to improve the display effect of the display panel using the pixel circuit.
  • a pixel circuit including: a driving module, a leakage suppression module, an initialization module, a first compensation module, a first storage module, a second storage module and a light-emitting module;
  • the control end of the driving module and the leakage suppression module are connected to the first node, the initialization module and the leakage suppression module are connected to the second node, and the initialization module is used to pass the initialization voltage through the
  • the leakage suppression module transmits to the first node and initializes the control end of the driving module;
  • the driving module and the light-emitting module are connected between the first power line and the second power line, and the driving module is used to During the light-emitting phase, drive the light-emitting module to emit light;
  • the first storage module is connected to the first node and is used to store the voltage of the first node;
  • the second storage module is connected to the second node and is used to store the voltage of the second node;
  • the first compensation module is connected to the second node and is used to perform voltage compensation on the second node in response to the voltage signal of the first node.
  • it also includes a second compensation module and a data writing module;
  • the data writing module is connected between the data line and the first end of the driving module, and the second compensation module is connected between the second end of the driving module and the second node;
  • the first end of the first storage module is connected to the first power line
  • the second end of the first storage module and the control end of the driving module are connected to the first node
  • the leakage suppression module The first end of the leakage suppression module is connected to the first node, the second end of the leakage suppression module and the second end of the initialization module are connected to the second node, and the first end of the initialization module is connected to the Initializing voltage
  • the first end of the second storage module is connected to the first power line
  • the second end of the second storage module is connected to the second node.
  • the first compensation module includes a first compensation subunit and a second compensation subunit; the first end of the first compensation subunit is connected to the first power line, and the first compensation subunit The second end is connected to the second node, and the control end of the first compensation subunit is connected to the first node;
  • the first end of the second compensation subunit is connected to the initialization voltage
  • the second end of the second compensation subunit is connected to the second node
  • the control end of the second compensation subunit is connected to the First node connection
  • the first compensation subunit and the second compensation subunit are not turned on at the same time.
  • the driving module includes a first transistor, the first compensation subunit includes a second transistor, and the second compensation subunit includes a third transistor;
  • the gate electrode of the second transistor and the gate electrode of the first transistor are connected to the first node, the first electrode of the second transistor is connected to the second node, and the second electrode of the second transistor is connected to the first node.
  • the gate electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the gate electrode of the third transistor is connected to the first power line.
  • the two poles are connected to the initializing voltage;
  • the second transistor and the third transistor have different channel types.
  • the first storage module includes a first capacitor
  • the second storage module includes a second capacitor; the first end of the first capacitor is connected to the first power line, and the first end of the first capacitor is connected to the first power line.
  • the second end is connected to the first node, the first end of the second capacitor is connected to the first power line, and the second end of the second capacitor is connected to the second node;
  • the capacitance of the first capacitor is greater than the capacitance of the second capacitor.
  • the leakage suppression module includes a fourth transistor, the initialization module includes a fifth transistor, the second compensation module includes a sixth transistor, the data writing module includes a seventh transistor;
  • the pixel circuit further It includes a first light-emitting control module and a second light-emitting control module, the first light-emitting control module includes an eighth transistor, the second light-emitting control module includes a ninth transistor, and the light-emitting module includes a light-emitting diode;
  • the gate of the fourth transistor is connected to the first scan signal, the first electrode of the fourth transistor is connected to the first node, and the second electrode of the fourth transistor is connected to the second node, so The gate of the fifth transistor is connected to the second scan signal, the first electrode of the fifth transistor is connected to the initialization voltage, the second electrode of the fifth transistor is connected to the second node, and the first electrode of the fifth transistor is connected to the initializing voltage.
  • the gates of the six transistors are connected to the third scan signal, the first pole of the sixth transistor is connected to the second terminal of the driving module, and the second pole of the sixth transistor is connected to the second node, so
  • the gate of the seventh transistor is connected to the third scan signal, the first electrode of the seventh transistor is connected to the data line, and the second electrode of the seventh transistor is connected to the first terminal of the driving module. connect;
  • the gate electrode of the eighth transistor and the gate electrode of the ninth transistor are both connected to the lighting control signal, the first electrode of the eighth transistor is connected to the first power line, and the second electrode of the eighth transistor is connected to the first power supply line.
  • the first terminal of the ninth transistor is connected to the first terminal of the driving module, the first terminal of the ninth transistor is connected to the second terminal of the driving module, and the second terminal of the ninth transistor is connected to the first terminal of the light-emitting diode. Connect, the second pole of the light-emitting diode is connected to the second power line;
  • the fourth transistor, the fifth transistor and the sixth transistor are dual-gate transistors.
  • the first compensation module includes a first compensation subunit and a second compensation subunit;
  • the first end of the first compensation subunit is connected to the second compensation module, the second end of the first compensation subunit is connected to the second node, and the control end of the first compensation subunit is connected to The first node is connected;
  • a first end of the second compensation subunit is connected to the initialization module, a second end of the second compensation subunit is connected to the second node, and a control end of the second compensation subunit is connected to the first node;
  • the first compensation subunit and the second compensation subunit are not turned on at the same time.
  • a driving method of a pixel circuit includes a driving module, a leakage suppression module, an initialization module, a first compensation module, a first storage module, a second storage module and a light emitting module. ;
  • the control end of the driving module and the leakage suppression module are connected to the first node, the initialization module and the leakage suppression module are connected to the second node, the driving module and the light-emitting module are connected to the first power supply between the power line and the second power line, the first storage module is connected to the first node, the second storage module is connected to the second node, and the first compensation module is connected to the second node ;
  • the driving method of the pixel circuit includes:
  • control the initialization module to transmit the initialization voltage to the first node through the leakage suppression module, and initialize the control end of the driving module;
  • the driving module is controlled to drive the light-emitting module to emit light
  • the first compensation module is controlled to be turned on in response to the voltage signal of the first node to perform voltage compensation on the second node.
  • the pixel circuit further includes a second compensation module and a data writing module.
  • the data writing module is connected between the data line and the first end of the driving module.
  • the second compensation module is connected to between the second end of the driving module and the second node;
  • the driving method of the pixel circuit further includes:
  • control the data writing module to transmit the data voltage on the data line to the control end of the driving module through the turned-on second compensation module
  • the first compensation module includes a first compensation sub-unit and a second compensation sub-unit.
  • the first end of the first compensation sub-unit is connected to the first power line.
  • the second end of the first compensation sub-unit Connected to the second node, the control end of the first compensation subunit is connected to the first node;
  • the first end of the second compensation subunit is connected to the initialization voltage, and the second compensation subunit
  • the second end of the unit is connected to the second node, and the control end of the second compensation subunit is connected to the first node;
  • the step of controlling the first compensation module to turn on in response to the voltage signal of the first node and performing voltage compensation on the second node specifically includes:
  • control the first compensation subunit When the voltage of the second node is negatively biased, control the first compensation subunit to be turned on in response to the voltage signal of the first node, and perform positive compensation for the voltage of the second node;
  • the second compensation subunit When the voltage of the second node is forward biased, the second compensation subunit is controlled to be turned on in response to the voltage signal of the first node to perform negative compensation on the voltage of the second node.
  • a display panel including the pixel circuit provided by any embodiment of the present application.
  • the technical solution provided by this embodiment uses a pixel circuit including a driving module, a leakage suppression module, an initialization module, a first compensation module, a first storage module, a second storage module and a light-emitting module; the control end of the driving module and the leakage suppression module Connected to the first node, the initialization module and the leakage suppression module are connected to the second node.
  • the initialization module is used to transmit the initialization voltage to the first node through the leakage suppression module during the initialization phase, and initialize the control end of the driving module; the driving module and the light emitting module
  • the module is connected between the first power line and the second power line, and the driving module is used to drive the light-emitting module to emit light during the light-emitting phase;
  • the first storage module is connected to the first node and is used to store the voltage of the first node;
  • the second storage module The first compensation module is connected to the second node and used to store the voltage of the second node;
  • the first compensation module is connected to the second node and is used to respond to the voltage signal of the first node and perform voltage compensation on the second node.
  • the potential of the first node is stabilized by setting the leakage suppression module and the second storage module; on the other hand, the voltage of the second node is self-compensated by setting the first compensation module to reduce the voltage of the first node.
  • the voltage difference between the first node and the second node further reduces the leakage current, thereby improving the leakage phenomenon of the pixel circuit and improving the display effect.
  • Figure 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 6 is a driving timing waveform diagram of a pixel circuit provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of a leakage flow curve provided by an embodiment of the present application.
  • Figure 9 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 10 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 12 is a flow chart of a driving method for a pixel circuit provided by an embodiment of the present application.
  • Figure 13 is a flow chart of another driving method of a pixel circuit provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the pixel circuit usually includes a driving transistor and an initialization transistor for resetting the gate potential of the driving transistor.
  • the driving transistor and initialization The transistors are all LTPS TFTs. Due to the large leakage current of LTPS TFTs, during the light-emitting stage, the gate potential of the driving transistor will be affected by the leakage current of the initialization transistor, causing the gate potential of the driving transistor to be unstable, thereby affecting the display effect. .
  • Figure 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit includes a driving module 110, a leakage suppression module 120, and an initialization module. 130.
  • the control end of the driving module 110 and the leakage suppression module 120 are connected to the first node N1.
  • the initialization module 130 and the leakage suppression module 120 are connected to the second node N2.
  • the initialization module 130 is used to transmit the initialization voltage Vref through the leakage suppression module during the initialization phase.
  • 120 is output to the first node N1 to initialize the control end of the driving module 110; the driving module 110 and the light-emitting module 170 are connected between the first power line L1 and the second power line L2, and the driving module 110 is used to drive light during the light-emitting phase.
  • Module 170 emits light.
  • the first storage module 150 is connected to the first node N1 and is used to store the voltage of the first node N1; the second storage module 160 is connected to the second node N2 and is used to store the voltage of the second node N2; the first compensation module 140 is connected to the second node N2 and is used to respond to the voltage signal of the first node N1 and perform voltage compensation on the second node N2.
  • the first node N1 and the second node N2 are voltage nodes in the pixel circuit, where the first node N1 is a connection node between the control end of the driving module 110 and the first end of the leakage suppression module 120, and the second node N2 is a leakage The connection node between the second end of the suppression module 120 and the second end of the initialization module 130.
  • the second end of the initialization module 130 is connected to the initialization voltage Vref.
  • the initialization voltage Vref can be provided by the initialization signal line.
  • the first power line L1 is used to transmit the first power voltage VDD
  • the second power line L2 is used to transmit the second power voltage VSS.
  • the driving module 110 drives the light-emitting module 170 to emit light according to the voltage of its control end.
  • the first storage module 150 and the second storage module 160 are used to store the voltage of the first node N1 and the second node N2, respectively, and maintain the voltage of the nodes during the light-emitting stage.
  • the initialization voltage Vref is written into the first node N1, and the potential of the control end of the driving module 110 is reset.
  • the initialization voltage Vref can be a negative polarity voltage.
  • the leakage suppression module 120 is not provided, during the light-emitting phase, the initialization module 130 is turned off, and the first storage module 150 maintains the voltage of the first node N1. However, due to the leakage current in the initialization module 130, the potential of the control terminal of the driving module 110 is lowered. Unstable, and the lower the refresh rate, the longer the holding time of the first memory module 150, the more serious the leakage current of the initialization module 130, and the greater the change in display brightness within one display cycle, causing the display screen to Flashing.
  • leakage is reduced by providing a leakage suppression module 120 and a second storage module 160 between the initialization module 130 and the first node N1.
  • the leakage current will flow to the second node N2, and the potential of the second node N2 will change.
  • the voltage difference between the first node N1 and the second node N2 gradually increases, further increasing the leakage current. Therefore, by providing the second storage module 160 to store and maintain the potential of the second node N2, the voltage of the second node N2 is maintained at a relatively stable level, thereby stabilizing the voltage difference between the first node N1 and the second node N2, and thus improving the leakage phenomenon of the first node N1.
  • the pixel circuit provided in this embodiment also includes a first compensation module 140.
  • the first compensation module 140 can be turned on according to the voltage signal of the first node N1, and then compensate the voltage of the second node N2 to reduce The voltage difference between the first node N1 and the second node N2 ensures that no leakage current flows through the leakage suppression module 120, so that the potential of the first node N1 remains constant, thereby improving the display effect of the display screen.
  • the first compensation module 140 is controlled to be turned on to provide a negative voltage to the second node N2.
  • N2 performs negative compensation, thereby reducing the voltage difference between the first node N1 and the second node N2.
  • the second node N2 is negatively biased, by controlling the first compensation module 140 to be turned on, a positive voltage is provided to the second node N2, and the second node N2 is positively compensated, which can also reduce the first node N1 and the second node N2. voltage difference between them.
  • the technical solution provided by this embodiment uses a pixel circuit including a driving module, a leakage suppression module, an initialization module, a first compensation module, a first storage module, a second storage module and a light-emitting module; the control end of the driving module and the leakage suppression module Connected to the first node, the initialization module and the leakage suppression module are connected to the second node.
  • the initialization module is used to transmit the initialization voltage to the first node through the leakage suppression module during the initialization phase, and initialize the control end of the driving module; the driving module and the light emitting module
  • the module is connected between the first power line and the second power line, and the driving module is used to drive the light-emitting module to emit light during the light-emitting phase;
  • the first storage module is connected to the first node and is used to store the voltage of the first node;
  • the second storage module The first compensation module is connected to the second node and used to store the voltage of the second node;
  • the first compensation module is connected to the second node and is used to respond to the voltage signal of the first node and perform voltage compensation on the second node.
  • the potential of the first node is stabilized by setting the leakage suppression module and the second storage module; on the other hand, the voltage of the second node is self-compensated by setting the first compensation module to reduce the voltage of the first node.
  • the voltage difference between the first node and the second node further reduces the leakage current, thereby improving the leakage phenomenon of the pixel circuit and improving the display effect.
  • FIG 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit also includes a second compensation module 180 and a data writing module.
  • Module 190, the data writing module 190 is connected between the data line Data and the first end of the driving module 110, and the second compensation module 180 is connected between the second end of the driving module 110 and the second node N2.
  • the pixel circuit can realize the threshold compensation function of the driving module 110 .
  • the driving module 110 is in a conductive state.
  • the data voltage Vdata is written to the first voltage Vdata through the data writing module 190, the driving module 110, the second compensation module 180 and the leakage suppression module 120.
  • Node N1 when the potential of the first node N1 causes the driving module 110 to turn off, the first storage module 150 stores the voltage of the first node N1. This voltage includes the data voltage Vdata and the threshold information of the driving module 110, realizing the driving Threshold compensation of module 110.
  • the initialization module 130, the leakage suppression module 120 and the second compensation module 180 are all turned off, and the driving module 110 drives the light-emitting module 170 to emit light.
  • FIG 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the first compensation module 140 includes a first compensation sub-unit 141 and a second compensation sub-unit. Unit 142.
  • the first end of the first compensation subunit 141 is connected to the first power line L1, the second end of the first compensation subunit 141 is connected to the second node N2, and the control end of the first compensation subunit 141 is connected to the first power line L1.
  • Node N1 is connected; the first end of the second compensation subunit 142 is connected to the initialization voltage Vref, the second end of the second compensation subunit 142 is connected to the second node N2, and the control end of the second compensation subunit 142 is connected to the first node N1 connection.
  • the first compensation sub-unit 141 and the second compensation sub-unit 142 are not turned on at the same time.
  • the voltage of the first node N1 (stored on the first storage module 150) has two leakage paths, one is leakage through the second compensation module 180, and the other is leakage through the initialization module 130.
  • the leakage rate is positively related to the voltage difference across the corresponding module.
  • the voltages of the first node N1 and the second node N2 are equal, which is the difference between the data voltage Vdata and the threshold voltage of the driving module 110.
  • the leakage current rates of the two leakage paths are different. , so the potential change of the second node N2 is also different.
  • the second compensation subunit 142 As time goes by, when the potential of the second node N2 is positively biased, the second compensation subunit 142 is controlled to be turned on, and the initialization voltage Vref charges the second node N2 with negative charges until the second node N2 is connected to the first node N1 When the voltage difference between them meets the turn-off condition of the second compensation sub-unit 142, the second compensation sub-unit 142 stops voltage compensation for the second node N1. At this time, the voltage between the first node N1 and the second node N2 The difference is small, so that the leakage current from the second node N2 to the first node N1 through the leakage suppression module 130 can be effectively suppressed, and the stability of the voltage of the first node N1 can be maintained.
  • the first compensation subunit 141 is controlled to be turned on, and the first power supply voltage VDD charges positive charge to the second node N2 until the connection between the second node N2 and the first node N1
  • the first compensation sub-unit 141 stops voltage compensation for the second node N1.
  • the voltage difference between the first node N1 and the second node N2 It is smaller, so that the leakage current from the first node N1 to the second node N2 through the leakage suppression module 130 can be effectively suppressed, and the stability of the voltage of the first node N1 can be maintained.
  • FIG. 4 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application, and shows a specific structure of the pixel circuit shown in FIG. 3.
  • the first storage module 150 includes a first capacitor C1
  • the second storage module 160 includes a second capacitor C2
  • the first end of the first capacitor C1 is connected to the first power line L1
  • the second end of the first capacitor C1 is connected to the first node N1
  • the first end of the second capacitor C2 is connected to the first power line L1
  • the second end of the second capacitor C2 is connected to the first node N1.
  • the second node N2 is connected.
  • the capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2, that is, the voltage holding capacity of the first capacitor C1 is greater than the voltage holding capacity of the second capacitor C2, which facilitates the voltage regulation of the second node N2.
  • the driving module 110 includes a first transistor T1, the first compensation subunit 141 includes a second transistor T2, and the second compensation subunit 142 includes a third transistor T3; the gate of the second transistor T2 is connected to the third transistor T2.
  • the gate of a transistor T1 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the first power supply.
  • the line L1 is connected, the gate of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second node of the third transistor T3 is connected to the line L1. pole is connected to the initialization voltage Vref.
  • the channel types of the second transistor T2 and the third transistor T3 are different.
  • the second transistor T2 is an N-type transistor
  • the third transistor T3 is a P-type transistor.
  • the voltages of the first node N1 and the second node N2 are both Vdata-Vth1, where Vth1 is the threshold voltage of the first transistor T1.
  • the leakage currents of the two leakage paths cause the potential of the second node N2 to be forward biased, and the voltage of the second node N2 is greater than the voltage of the first node N1 and the threshold voltage Vth3 of the third transistor T3.
  • the technical solution provided by this embodiment is to set the N-type second transistor T2 and the P-type third transistor T3, and control the conduction of the second transistor T2 or the third transistor T3 according to the difference between the second node N2 and the first node N1. to self-compensate the voltage of the second node N1, thereby reducing the cross-voltage between the first node N1 and the second node N2, thereby reducing the leakage current between the first capacitor C1 and the second capacitor C2.
  • Figure 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the leakage suppression module 120 includes a fourth transistor T4, and the initialization module 130 includes a fifth transistor T5.
  • the second compensation module 180 includes a sixth transistor T6, and the data writing module 190 includes a seventh transistor T7; the pixel circuit also includes a first emission control module 111 and a second emission control module 112, and the first emission control module 111 includes an eighth transistor.
  • the second light-emitting control module 112 includes a ninth transistor T9, and the light-emitting module 170 includes a light-emitting diode D1; the gate of the fourth transistor T4 is connected to the first scanning signal S1, and the first electrode of the fourth transistor T4 is connected to the first node N1 connection, the second electrode of the fourth transistor T4 is connected to the second node N2, the gate of the fifth transistor T5 is connected to the second scanning signal S2, the first electrode of the fifth transistor T5 is connected to the initialization voltage Vref, and the fifth transistor T5
  • the second electrode of the sixth transistor T6 is connected to the second node N2, the gate electrode of the sixth transistor T6 is connected to the third scanning signal S3, the first electrode of the sixth transistor T6 is connected to the second terminal of the driving module 110, and the gate electrode of the sixth transistor T6 is connected to the second terminal of the driving module 110.
  • the second electrode is connected to the second node N2, the gate electrode of the seventh transistor T7 is connected to the third scanning signal S3, the first electrode of the seventh transistor T7 is connected to the data line Data, and the second electrode of the seventh transistor T7 is connected to the driving module 110
  • the first end of the eighth transistor T8 and the gate of the ninth transistor T9 are both connected to the lighting control signal EM, the first electrode of the eighth transistor T8 is connected to the first power line L1, and the gate of the eighth transistor T8
  • the second pole is connected to the first pole of the driving module 110, the first pole of the ninth transistor T9 is connected to the second pole of the driving module 110, the second pole of the ninth transistor T9 is connected to the first pole of the light emitting diode D1, and emits light.
  • the second pole of the diode D1 is connected to the second power line L2.
  • Figure 6 is a driving timing waveform diagram of a pixel circuit provided in an embodiment of the present application, which can be used for the pixel circuit shown in Figure 5.
  • the working process of the pixel circuit provided in this embodiment includes an initialization stage t1, a data writing stage t2 and a light-emitting stage t3.
  • the first scanning signal S1 is low level
  • the second scanning signal S2 is low level
  • the third scanning signal S3 is high level
  • the light emission control signal EM is high level. Therefore, the fourth transistor T4 and the fifth transistor T5 is turned on, the initialization voltage Vref is written to the gate of the first transistor T1 through the fifth transistor T5 and the fourth transistor T4, and the gate voltage of the first transistor T1 is reset to the initialization voltage Vref.
  • the voltage of the first node N1 is equal to the voltage of the second node N2, and both are the initialization voltage Vref. Therefore, the second transistor T2 and the third transistor T3 are in the off state.
  • the first scanning signal S1 is low level
  • the second scanning signal S2 is high level
  • the third scanning signal S3 is low level
  • the light emission control signal EM is high level. Therefore, the fourth The transistor T4, the sixth transistor T6 and the seventh transistor T7 are turned on, the fifth transistor T5 is turned off, and the data voltage Vdata is written to the first transistor through the seventh transistor T7, the first transistor T1, the sixth transistor T6 and the fourth transistor T4.
  • the gate of the transistor T1 implements data writing and compensation of the first transistor T1. At this time, the voltages of the first node N1 and the second node N2 are both Vdata+Vth1.
  • the first scanning signal S1 is high level
  • the second scanning signal S2 is high level
  • the third scanning signal S3 is high level
  • the light-emitting control signal EM is low level. Therefore, the eighth transistor T8
  • the ninth transistor T9 is turned on, and the first transistor T1 generates a driving current according to its gate voltage to drive the light-emitting diode D1 to emit light.
  • Figure 7 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application. The difference from the pixel circuit shown in Figure 5 is that the pixel circuit shown in Figure 7 does not include the leakage suppression module 120, the first compensation sub-unit 141 and the third Two compensation subunits 142.
  • the pixel circuit shown in Figure 7 does not include the leakage suppression module 120, the first compensation sub-unit 141 and the third Two compensation subunits 142.
  • the data voltage Vdata is written into the gate of the first transistor T1
  • Both the fifth transistor T5 and the sixth transistor T6 are in the off state, and the leakage current of the first capacitor C1 (first node N1) There are two paths, one is leakage through the sixth transistor T6, and the other is leakage through the fifth transistor T5.
  • VDD-VN1 refers to the voltage difference across the sixth transistor T6 during the light-emitting phase
  • VN1-Vref refers to the voltage difference across the fifth transistor T5.
  • Figure 8 is a schematic diagram of a leakage current curve provided by an embodiment of the present application.
  • the solid line represents the leakage current of the first node N1 in the pixel circuit shown in Figure 7, and the dotted line represents the first node N1 in the pixel circuit shown in Figure 5.
  • the leakage current, line AA' represents the time required for the first node N1 in the pixel circuit shown in Figure 7 to reach a balanced voltage
  • BB' represents the time required for the first node N1 in the pixel circuit shown in Figure 5 to reach a balanced voltage.
  • the technical solution provided by this embodiment makes it take longer for the first node N1 to reach the equilibrium voltage, that is, the leakage current rate of the first node N1 is slower, especially During the initial period of leakage flow, the leakage flow at the first node N1 approaches zero.
  • the second pole of the first transistor T1 has a positive voltage, and the initialization voltage Vref is a negative voltage.
  • the voltage difference across the sixth transistor T6 is inconsistent with the voltage difference across the fifth transistor T5. Therefore, the two The leakage current rates of the leakage current paths are also different, which results in that the voltage difference between the first node N1 and the second node N2 cannot be maintained at 0V, and leakage current will still occur.
  • the voltage of the second node N2 is self-compensated by adding the second transistor T2 and the third transistor T3, thereby suppressing the leakage current between the first node N1 and the second node N2.
  • the voltage difference between the first node N1 and the second node N2 is controlled to (VN1-
  • Figure 9 is a structural schematic diagram of another pixel circuit provided in an embodiment of the present application.
  • the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are dual-gate transistors.
  • the dual-gate transistor has a smaller leakage current than the single-gate transistor, which can further reduce the leakage of the first node N1.
  • the first compensation module 140 may also have other connection methods.
  • Figure 10 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application, and shows the specific structure of the pixel circuit shown in Figure 10.
  • the first compensation module 140 includes a first compensation sub-unit 141 and a second compensation sub-unit 142; the first end of the first compensation sub-unit 141 and the second compensation sub-unit 142
  • the module 180 is connected, the second end of the first compensation subunit 141 is connected to the second node N2, the control end of the first compensation subunit 141 is connected to the first node N1; the first end of the second compensation subunit 142 is connected to the initialization module 130 is connected, the second end of the second compensation subunit 142 is connected to the second node N2, and the control end of the second compensation subunit 142 is connected to the first node N1.
  • the first compensation subunit 141 includes a second transistor T2
  • the second compensation subunit 142 includes a third transistor T3 , wherein the second transistor T2 is connected to the middle node of the sixth transistor T6 and the second node. N2, the third transistor T3 is connected between the intermediate node of the fifth transistor T5 and the second node N2.
  • the sixth transistor T6 The voltage of the intermediate node is closer to the first power supply voltage VDD than the voltage of point M1, and the leakage rate of positive charges is greater; the intermediate node of the fifth transistor T5 is closer to the initialization voltage Vref than the voltage of point M2, and the leakage rate of negative charges is greater. big.
  • the leakage current of point M1 is greater than that of point M2, by turning on the third transistor T3, more negative charges can be provided to point M1 in the same time to balance the voltage of the second node N2.
  • embodiments of the present application also provide a driving method for a pixel circuit, which is used to drive the pixel circuit provided by any embodiment of the present application.
  • Figure 12 is a flow chart of a driving method for a pixel circuit provided by an embodiment of the present application. Combining Figures 1 and 12, the driving method for the pixel circuit includes:
  • control initialization module transmits the initialization voltage to the first node through the leakage suppression module, and initializes the control end of the drive module.
  • control the driving module to drive the light-emitting module to emit light
  • control the first compensation module to turn on in response to the voltage signal of the first node to perform voltage compensation on the second node.
  • the technical solution provided by this embodiment uses a pixel circuit including a driving module, a leakage suppression module, an initialization module, a first compensation module, a first storage module, a second storage module and a light-emitting module; the control end of the driving module and the leakage suppression module Connected to the first node, the initialization module and the leakage suppression module are connected to the second node.
  • the initialization module is used to transmit the initialization voltage to the first node through the leakage suppression module during the initialization phase, and initialize the control end of the driving module; the driving module and the light emitting module
  • the module is connected between the first power line and the second power line, and the driving module is used to drive the light-emitting module to emit light during the light-emitting phase;
  • the first storage module is connected to the first node and is used to store the voltage of the first node;
  • the second storage module The first compensation module is connected to the second node and used to store the voltage of the second node;
  • the first compensation module is connected to the second node and is used to respond to the voltage signal of the first node and perform voltage compensation on the second node.
  • the potential of the first node is stabilized by setting the leakage suppression module and the second storage module; on the other hand, the voltage of the second node is self-compensated by setting the first compensation module to reduce the voltage of the first node.
  • the voltage difference between the first node and the second node further reduces the leakage current, thereby improving the leakage phenomenon of the pixel circuit and improving the display effect.
  • FIG. 13 is a flow chart of another driving method for a pixel circuit provided by an embodiment of the present application. Combining FIG. 3 and FIG. 13, the driving method includes:
  • control initialization module transmits the initialization voltage to the first node through the leakage suppression module, and initializes the control end of the drive module.
  • control data writing module transmits the data voltage on the data line to the control end of the driving module through the turned-on second compensation module.
  • the driving module is controlled to drive the light-emitting module to emit light.
  • the first compensation subunit is controlled to be turned on in response to the voltage signal of the first node and perform positive compensation for the voltage of the second node;
  • the second compensation subunit is controlled to be turned on in response to the voltage signal of the first node to perform negative compensation on the voltage of the second node.
  • FIG. 14 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel can be applied to a mobile phone or any electronic product with a display function, including but not limited to the following categories: Televisions, notebook computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, vehicle-mounted monitors, medical equipment, industrial control equipment, touch interactive terminals, etc.
  • the embodiments of this application are not particularly limited.

Abstract

一种像素电路及其驱动方法和显示面板，像素电路包括驱动模块（110）、漏电抑制模块（120）、初始化模块（130）、第一补偿模块（140）、第一存储模块（150）、第二存储模块（160）和发光模块（170）；驱动模块（110）的控制端与漏电抑制模块（120）连接于第一节点（N1），初始化模块（130）与漏电抑制模块（120）连接于第二节点（N2），第一存储模块（150）与第一节点（N1）连接，第二存储模块（160）与第二节点（N2）连接，第一补偿模块（140）与第二节点（N2）连接，用于响应第一节点（N1）的电压信号对第二节点（N2）进行电压补偿。通过设置漏电抑制模块（120）和第二存储模块（160）来稳定第一节点（N1）的电位；此外通过设置第一补偿模块（140）对第二节点（N2）的电压进行自补偿，以减小第一节点（N1）和第二节点（N2）之间的电压差，进一步减小漏电流，提高显示效果。

Description

像素电路及其驱动方法和显示面板
本申请要求于2022年09月22日提交中国专利局、申请号为202211160466.9、申请名称为“像素电路及其驱动方法和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路及其驱动方法和显示面板。
背景技术
随着显示技术的发展，人们对画面显示质量的要求也越来越高。
显示面板中通常包括多个像素电路，像素电路中流经发光模块的驱动电流的大小决定了显示面板的发光亮度。现有的显示面板存在漏电的问题，影响显示效果。
发明内容
本申请提供了一种像素电路及其驱动方法和显示面板，以改善应用该像素电路的显示面板的显示效果。
根据本申请的一方面，提供了一种像素电路，包括：驱动模块、漏电抑制模块、初始化模块、第一补偿模块、第一存储模块、第二存储模块和发光模块；
所述驱动模块的控制端与所述漏电抑制模块连接于第一节点，所述初始化模块与所述漏电抑制模块连接于第二节点，所述初始化模块用于在初始化阶段将初始化电压经所述漏电抑制模块传输至所述第一节点，对所述驱动模块的控制端初始化；所述驱动模块和所述发光模块连接于第一电源线和第二电源线之间，所述驱动模块用于在发光阶段驱动所述发光模块发光；
所述第一存储模块与所述第一节点连接，用于存储所述第一节点的电压；所述第二存储模块与所述第二节点连接，用于存储所述第二节点的电压；
所述第一补偿模块与所述第二节点连接，用于响应所述第一节点的电压信号，对所述第二节点进行电压补偿。
可选地，还包括第二补偿模块和数据写入模块；
所述数据写入模块连接于数据线和所述驱动模块的第一端之间，所述第二补偿模块连接于所述驱动模块的第二端和所述第二节点之间；
所述第一存储模块的第一端与所述第一电源线连接，所述第一存储模块的第二端与所述驱动模块的控制端连接于所述第一节点，所述漏电抑制模块的第一端与所述第一节点连接，所述漏电抑制模块的第二端与所述初始化模块的第二端连接于所述第二节点，所述初始化模块的第一端接入所述初始化电压，所述第二存储模块的第一端与所述第一电源线连接，所述第二存储模块的第二端与所述第二节点连接。
可选地，所述第一补偿模块包括第一补偿子单元和第二补偿子单元；所述第一补偿子单元的第一端与所述第一电源线连接，所述第一补偿子单元的第二端与所述第二节点连接，所述第一补偿子单元的控制端与所述第一节点连接；
所述第二补偿子单元的第一端接入所述初始化电压，所述第二补偿子单元的第二端与所述第二节点连接，所述第二补偿子单元的控制端与所述第一节点连接；
其中，所述第一补偿子单元和所述第二补偿子单元不同时导通。
可选地，所述驱动模块包括第一晶体管，所述第一补偿子单元包括第二晶体管，所述第二补偿子单元包括第三晶体管；
所述第二晶体管的栅极与所述第一晶体管的栅极连接于所述第一节点，所述第二晶体管的第一极与所述第二节点连接，所述第二晶体管的第二极与所述第一电源线连接，所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的第一极与所述第二节点连接，所述第三晶体管的第二极接入所述初始化电压；
所述第二晶体管与所述第三晶体管的沟道类型不同。
可选地，所述第一存储模块包括第一电容，所述第二存储模块包括第二电容；所述第一电容的第一端与所述第一电源线连接，所述第一电容的第二端与所述第一节点连接，所述第二电容的第一端与所述第一电源线连接，所述第二电容的第二端与所述第二节点连接；
所述第一电容的容值大于所述第二电容的容值。
可选地，所述漏电抑制模块包括第四晶体管，所述初始化模块包括第五晶体管，所述第二补偿模块包括第六晶体管，所述数据写入模块包括第七晶体管；所述像素电路还包括第一发光控制模块和第二发光控制模块，所述第一发光控制模块包括第八晶体管，所述第二发光控制模块包括第九晶体管，所述发光模块包括发光二极管；
所述第四晶体管的栅极接入第一扫描信号，所述第四晶体管的第一极与所述第一节点连接，所述第四晶体管的第二极与所述第二节点连接，所述第五晶体管的栅极接入第二扫描信号，所述第五晶体管的第一极接入所述初始化电压，所述第五晶体管的第二极与所述第二节点连接，所述第六晶体管的栅极接入第三扫描信号，所述第六晶体管的第一极与所述驱动模块的第二端连接，所述第六晶体管的第二极与所述第二节点连接，所述第七晶体管的栅极接入所述第三扫描信号，所述第七晶体管的第一极与所述数据线连接，所述第七晶体管的第二极与所述驱动模块的第一端连接；
所述第八晶体管的栅极和所述第九晶体管的栅极均接入发光控制信号，所述第八晶体管的第一极与所述第一电源线连接，所述第八晶体管的第二极与所述驱动模块的第一端连接，所述第九晶体管的第一极与所述驱动模块的第二端连接，所述第九晶体管的第二极与所述发光二极管的第一极连接，所述发光二极管的第二极与所述第二电源线连接；
优选地，所述第四晶体管、所述第五晶体管和所述第六晶体管为双栅晶体管。
可选地，所述第一补偿模块包括第一补偿子单元和第二补偿子单元；
所述第一补偿子单元的第一端与所述第二补偿模块连接，所述第一补偿子单元的第二端与所述 第二节点连接，所述第一补偿子单元的控制端与所述第一节点连接；
所述第二补偿子单元的第一端与所述初始化模块连接，所述第二补偿子单元的第二端与所述第二节点连接，所述第二补偿子单元的控制端与所述第一节点连接；
其中，所述第一补偿子单元和所述第二补偿子单元不同时导通。
根据本申请的另一方面，提供了一种像素电路的驱动方法，所述像素电路包括驱动模块、漏电抑制模块、初始化模块、第一补偿模块、第一存储模块、第二存储模块和发光模块；所述驱动模块的控制端与所述漏电抑制模块连接于第一节点，所述初始化模块与所述漏电抑制模块连接于第二节点，所述驱动模块和所述发光模块连接于第一电源线和第二电源线之间，所述第一存储模块与所述第一节点连接，所述第二存储模块与所述第二节点连接，所述第一补偿模块与所述第二节点连接；
所述像素电路的驱动方法包括：
在初始化阶段，控制所述初始化模块将初始化电压经所述漏电抑制模块传输至所述第一节点，对所述驱动模块的控制端初始化；
在发光阶段，控制所述驱动模块驱动所述发光模块发光，并控制所述第一补偿模块响应所述第一节点的电压信号导通，对所述第二节点进行电压补偿。
可选地，所述像素电路还包括第二补偿模块和数据写入模块，所述数据写入模块连接于数据线和所述驱动模块的第一端之间，所述第二补偿模块连接于所述驱动模块的第二端和所述第二节点之间；
在所述发光阶段之前，所述像素电路的驱动方法还包括：
在数据写入阶段，控制所述数据写入模块将所述数据线上的数据电压经导通的所述第二补偿模块传输至所述驱动模块的控制端；
所述第一补偿模块包括第一补偿子单元和第二补偿子单元，所述第一补偿子单元的第一端与所述第一电源线连接，所述第一补偿子单元的第二端与所述第二节点连接，所述第一补偿子单元的控制端与所述第一节点连接；所述第二补偿子单元的第一端接入所述初始化电压，所述第二补偿子单元的第二端与所述第二节点连接，所述第二补偿子单元的控制端与所述第一节点连接；
所述控制所述第一补偿模块响应所述第一节点的电压信号导通，对所述第二节点进行电压补偿的步骤具体包括：
当所述第二节点的电压负偏时，控制所述第一补偿子单元响应所述第一节点的电压信号导通，对所述第二节点的电压进行正补偿；
当所述第二节点的电压正偏时，控制所述第二补偿子单元响应所述第一节点的电压信号导通，对所述第二节点的电压进行负补偿。
根据本申请的另一方面，提供了一种显示面板，包括本申请任意实施例所提供的像素电路。
本实施例提供的技术方案，采用的像素电路包括驱动模块、漏电抑制模块、初始化模块、第一补偿模块、第一存储模块、第二存储模块和发光模块；驱动模块的控制端与漏电抑制模块连接于第一节点，初始化模块与漏电抑制模块连接于第二节点，初始化模块用于在初始化阶段将初始化电压 经漏电抑制模块传输至第一节点，对驱动模块的控制端初始化；驱动模块和发光模块连接于第一电源线和第二电源线之间，驱动模块用于在发光阶段驱动发光模块发光；第一存储模块与第一节点连接，用于存储第一节点的电压；第二存储模块与第二节点连接，用于存储第二节点的电压；第一补偿模块与第二节点连接，用于响应第一节点的电压信号，对第二节点进行电压补偿。在发光阶段，一方面通过设置漏电抑制模块和第二存储模块来稳定第一节点的电位；另一方面，通过设置第一补偿模块对第二节点的电压进行自补偿，以减小第一节点和第二节点之间的电压差，进一步减小漏电流，从而能够改善像素电路的漏电现象，提高显示效果。
应当理解，本部分所描述的内容并非旨在标识本申请的实施例的关键或重要特征，也不用于限制本申请的范围。本申请的其它特征将通过以下的说明书而变得容易理解。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种像素电路的结构示意图；
图2为本申请实施例提供的另一种像素电路的结构示意图；
图3为本申请实施例提供的另一种像素电路的结构示意图；
图4为本申请实施例提供的另一种像素电路的结构示意图；
图5为本申请实施例提供的另一种像素电路的结构示意图；
图6为本申请实施例提供的一种像素电路的驱动时序波形图；
图7为本申请实施例提供的另一种像素电路的结构示意图；
图8为本申请实施例提供的一种漏流曲线示意图；
图9为本申请实施例提供的另一种像素电路的结构示意图；
图10为本申请实施例提供的另一种像素电路的结构示意图；
图11为本申请实施例提供的另一种像素电路的结构示意图；
图12为本申请实施例提供的一种像素电路的驱动方法的流程图；
图13为本申请实施例提供的另一种像素电路的驱动方法的流程图；
图14为本申请实施例提供的一种显示面板的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
正如背景技术所述，现有的显示面板存在漏电的现象。经申请人研究发现，出现上述问题原因在于，现有显示面板结构的阵列基板多为LTPS TFT基板，像素电路通常包括驱动晶体管和用于对驱动晶体管栅极电位复位的初始化晶体管，驱动晶体管和初始化晶体管均为LTPS TFT，因LTPS TFT的漏流较大，在发光阶段，驱动晶体管的栅极电位会因初始化晶体管的漏流而产生影响，造成驱动晶体管的栅极电位不稳定，从而影响显示效果。现有的解决方案通常采用优化驱动晶体管栅极处的存储电容的保压能力的方式，或者采用漏流更小的LGZO晶体管(LTPO技术)来降低漏电，但是工艺难度大成本高，对解决漏电问题的提升效果有限。
基于上述问题，本申请实施例提供一种像素电路，图1为本申请实施例提供的一种像素电路的结构示意图，参考图1，该像素电路包括驱动模块110、漏电抑制模块120、初始化模块130、第一补偿模块140、第一存储模块150、第二存储模块160和发光模块170。
驱动模块110的控制端与漏电抑制模块120连接于第一节点N1，初始化模块130与漏电抑制模块120连接于第二节点N2，初始化模块130用于在初始化阶段将初始化电压Vref经漏电抑制模块传120输至第一节点N1，对驱动模块110的控制端初始化；驱动模块110和发光模块170连接于第一电源线L1和第二电源线L2之间，驱动模块110用于在发光阶段驱动发光模块170发光。
第一存储模块150与第一节点N1连接，用于存储第一节点N1的电压；第二存储模块160与第二节点N2连接，用于存储第二节点N2的电压；第一补偿模块140与第二节点N2连接，用于响应第一节点N1的电压信号，对第二节点N2进行电压补偿。
具体地，第一节点N1和第二节点N2为像素电路中的电压节点，其中，第一节点N1为驱动模块110控制端与漏电抑制模块120第一端的连接节点，第二节点N2为漏电抑制模块120第二端与初始化模块130第二端的连接节点，初始化模块130的第二端接入初始化电压Vref，该初始化电压Vref可以由初始化信号线提供。
在本实施例中，第一电源线L1用于传输第一电源电压VDD，第二电源线L2用于传输第二电源电压VSS，当第一电源线L1和第二电源线L2之间的放电路径导通时，驱动模块110根据其控制端的电压驱动发光模块170发光。第一存储模块150和第二存储模块160分别用于存储第一节点N1和第二节点N2的电压，并在发光阶段对该节点的电压进行保压。例如，第一存储模块150的一端和第二存储模块160的一端均接入第一电源电压VDD，第一存储模块150的另一端与第一节点N1连接，第二存储模块160的另一端与第二节点N2连接。在初始化模块130和漏电抑制模块120均导通时，初始化电压Vref写入第一节点N1，对驱动模块110控制端的电位进行复位。这里，初始化电压Vref 可以为负极性电压。
若不设置漏电抑制模块120，在发光阶段，初始化模块130关断，第一存储模块150对第一节点N1的电压进行保压，但是由于初始化模块130存在漏流，导致驱动模块110控制端的电位不稳定，并且刷新率越低，第一存储模块150的保压时间就越长，初始化模块130的漏电流就越严重，一个显示周期内，显示亮度的变化程度也就越大，造成显示画面闪烁。
在本实施例中，通过在初始化模块130和第一节点N1之间设置漏电抑制模块120和第二存储模块160来降低漏电。在初始化模块130关断后，漏电流会流至第二节点N2，第二节点N2的电位发生变化。在第二节点N2的电位变化过程中，使得第一节点N1和第二节点N2之间的电压差逐渐增大，进一步加大漏电流。因此通过设置第二存储模块160对第二节点N2的电位进行存储并保压，使得第二节点N2的电压保持在较为稳定的水平，从而稳定第一节点N1和第二节点N2之间的电压差，进而改善第一节点N1的漏电现象。
另一方面，本实施例提供的像素电路还包括第一补偿模块140，第一补偿模块140能够根据第一节点N1的电压信号导通，进而对第二节点N2的电压进行补偿，以减小第一节点N1和第二节点N2之间的电压差，保证漏电抑制模块120不会有漏电流流过，使得第一节点N1的电位保持恒定，从而改善显示画面的显示效果。示例性地，相对于第一节点N1的电压来说，当第二节点N2的电压正偏时，通过控制第一补偿模块140导通，向第二节点N2提供一个负压，对第二节点N2进行负补偿，从而降低第一节点N1和第二节点N2之间的电压差。当第二节点N2负偏时，通过控制第一补偿模块140导通，向第二节点N2提供一个正压，对第二节点N2进行正补偿，同样能够降低第一节点N1和第二节点N2之间的电压差。
本实施例提供的技术方案，采用的像素电路包括驱动模块、漏电抑制模块、初始化模块、第一补偿模块、第一存储模块、第二存储模块和发光模块；驱动模块的控制端与漏电抑制模块连接于第一节点，初始化模块与漏电抑制模块连接于第二节点，初始化模块用于在初始化阶段将初始化电压经漏电抑制模块传输至第一节点，对驱动模块的控制端初始化；驱动模块和发光模块连接于第一电源线和第二电源线之间，驱动模块用于在发光阶段驱动发光模块发光；第一存储模块与第一节点连接，用于存储第一节点的电压；第二存储模块与第二节点连接，用于存储第二节点的电压；第一补偿模块与第二节点连接，用于响应第一节点的电压信号，对第二节点进行电压补偿。在发光阶段，一方面通过设置漏电抑制模块和第二存储模块来稳定第一节点的电位；另一方面，通过设置第一补偿模块对第二节点的电压进行自补偿，以减小第一节点和第二节点之间的电压差，进一步减小漏电流，从而能够改善像素电路的漏电现象，提高显示效果。
图2为本申请实施例提供的另一种像素电路的结构示意图，参考图1和图2，在上述技术方案的基础上，可选地，像素电路还包括第二补偿模块180和数据写入模块190，数据写入模块190连接于数据线Data和驱动模块110的第一端之间，第二补偿模块180连接于驱动模块110的第二端和第二节点N2之间。
其中，该像素电路能够实现驱动模块110的阈值补偿功能。在初始化阶段结束后，驱动模块110 处于导通状态，进入数据写入阶段后，数据电压Vdata通过数据写入模块190、驱动模块110、第二补偿模块180和漏电抑制模块120写入至第一节点N1，当第一节点N1的电位使得驱动模块110关断时，第一存储模块150存储第一节点N1的电压，该电压包含了数据电压Vdata和驱动模块110的阈值信息，实现了对驱动模块110的阈值补偿。
在发光阶段，初始化模块130、漏电抑制模块120和第二补偿模块180均关断，驱动模块110驱动发光模块170发光。
图3为本申请实施例提供的另一种像素电路的结构示意图，参考图2和图3，在上述技术方案的基础上，第一补偿模块140包括第一补偿子单元141和第二补偿子单元142。
具体地，第一补偿子单元141的第一端与第一电源线L1连接，第一补偿子单元141的第二端与第二节点N2连接，第一补偿子单元141的控制端与第一节点N1连接；第二补偿子单元142的第一端接入初始化电压Vref，第二补偿子单元142的第二端与第二节点N2连接，第二补偿子单元142的控制端与第一节点N1连接。其中，第一补偿子单元141和第二补偿子单元142不同时导通。
此时，第一节点N1的电压(存储在第一存储模块150上)的漏电路径有两条，一条是通过第二补偿模块180进行漏电，另一条是通过初始化模块130进行漏电。漏电速率与对应模块两端的电压差正相关。在写完数据后，第一节点N1和第二节点N2的电压相等，均为数据电压Vdata与驱动模块110的阈值电压之差，在漏流过程中，由于两条漏电路径的漏流速率不同，因此第二节点N2的电位变化也不同。随着时间的推移，当第二节点N2的电位正偏时，控制第二补偿子单元142导通，初始化电压Vref向第二节点N2充入负电荷，直到第二节点N2与第一节点N1之间的电压差满足第二补偿子单元142的关断条件时，第二补偿子单元142停止对第二节点N1进行电压补偿，此时，第一节点N1和第二节点N2之间的电压差较小，从而能够有效抑制第二节点N2通过漏电抑制模块130到第一节点N1的漏电流，能够维持第一节点N1电压的稳定性。
同样地，当第二节点N2的电位负偏时，控制第一补偿子单元141导通，第一电源电压VDD向第二节点N2充入正电荷，直到第二节点N2与第一节点N1之间的电压差满足第一补偿子单元141的关断条件时，第一补偿子单元141停止对第二节点N1进行电压补偿，此时，第一节点N1和第二节点N2之间的电压差较小，从而能够有效抑制第一节点N1通过漏电抑制模块130到第二节点N2的漏电流，能够维持第一节点N1电压的稳定性。
示例性地，图4为本申请实施例提供的另一种像素电路的结构示意图，并示出了图3所示像素电路的一种具体结构，参考图4，在上述技术方案的基础上，可选地，所述第一存储模块150包括第一电容C1，所述第二存储模块160包括第二电容C2，所述第一电容C1的第一端与所述第一电源线L1连接，所述第一电容C1的第二端与所述第一节点N1连接，所述第二电容C2的第一端与所述第一电源线L1连接，所述第二电容C2的第二端与所述第二节点N2连接。
其中，第一电容C1的容值大于第二电容C2的容值，即第一电容C1的保压能力大于第二电容C2的保压能力，便于对第二节点N2的电压调节。
驱动模块110包括第一晶体管T1，所述第一补偿子单元141包括第二晶体管T2，所述第二补偿 子单元142包括第三晶体管T3；所述第二晶体管T2的栅极与所述第一晶体管T1的栅极连接于所述第一节点N1，所述第二晶体管T2的第一极与所述第二节点N2连接，所述第二晶体管T2的第二极与所述第一电源线L1连接，所述第三晶体管T3的栅极与所述第一节点N1连接，所述第三晶体管T3的第一极与所述第二节点N2连接，所述第三晶体管T3的第二极接入所述初始化电压Vref。
在本实施例中，第二晶体管T2与第三晶体管T3的沟道类型不同，例如，第二晶体管T2为N型晶体管，第三晶体管T3为P型晶体管。在完成数据写入后，第一节点N1和第二节点N2的电压均为Vdata-Vth1，其中，Vth1为第一晶体管T1的阈值电压。在漏电过程中，随着时间推移，两条漏电路径的漏电流使得第二节点N2的电位正偏，且第二节点N2的电压大于第一节点N1的电压与第三晶体管T3阈值电压Vth3的差值时(即VN2＞VN1+Vth3)，第三晶体管T3导通，且第二晶体管T2关断，因此初始化电压Vref通过第三晶体管T3向第二节点N2充入负电荷(也即向第二电容C2充入负电荷)，直到VN2＝VN1+Vth3时，第三晶体管T3关断，此时可视为第一节点N1与第二节点N2之间的电压达到一个平衡，二者之间的压差较小，有效抑制了第一节点N1与第二节点N2之间的漏流。
若两条漏电路径的漏电流使得第二节点N2的电位负偏，且第二节点N2的电压小于第一节点N1的电压与第二晶体管T2阈值电压Vth2的差值时(即VN2＜VN1-Vth2)，第二晶体管T2导通，且第三晶体管T3关断，因此第一电源电压VDD通过第二晶体管T2向第二节点N2充入正电荷(也即向第二电容C2充入正电荷)，直到VN2＝VN1-Vth2时，第二晶体管T2关断，此时可视为第一节点N1与第二节点N2之间的电压达到一个平衡，二者之间的压差较小，有效抑制了第一节点N1与第二节点N2之间的漏流。
本实施例提供的技术方案通过设置N型第二晶体管T2和P型第三晶体管T3，并根据第二节点N2与第一节点N1之间的差值控制第二晶体管T2或第三晶体管T3导通，以对第二节点N1的电压进行自补偿，从而减小第一节点N1与第二节点N2之间的跨压，进而减小第一电容C1和第二电容C2之间的漏流。
图5为本申请实施例提供的另一种像素电路的结构示意图，在上述各技术方案的基础上，参考图5，漏电抑制模块120包括第四晶体管T4，初始化模块130包括第五晶体管T5，第二补偿模块180包括第六晶体管T6，数据写入模块190包括第七晶体管T7；像素电路还包括第一发光控制模块111和第二发光控制模块112，第一发光控制模块111包括第八晶体管T8，第二发光控制模块112包括第九晶体管T9，发光模块170包括发光二极管D1；第四晶体管T4的栅极接入第一扫描信号S1，第四晶体管T4的第一极与第一节点N1连接，第四晶体管T4的第二极与第二节点N2连接，第五晶体管T5的栅极接入第二扫描信号S2，第五晶体管T5的第一极接入初始化电压Vref，第五晶体管T5的第二极与第二节点N2连接，第六晶体管T6的栅极接入第三扫描信号S3，第六晶体管T6的第一极与驱动模块110的第二端连接，第六晶体管T6的第二极与第二节点N2连接，第七晶体管T7的栅极接入第三扫描信号S3，第七晶体管T7的第一极与数据线Data连接，第七晶体管T7的第二极与驱动模块110的第一端连接；第八晶体管T8的栅极和第九晶体管T9的栅极均接入发光控制信号EM，第八晶体管T8的第一极与第一电源线L1连接，第八晶体管T8的第二极与驱动模块110的第一极连接， 第九晶体管T9的第一极与驱动模块110的第二极连接，第九晶体管T9的第二极与发光二极管D1的第一极连接，发光二极管D1的第二极与第二电源线L2连接。
图6为本申请实施例提供的一种像素电路的驱动时序波形图，可用于图5所示的像素电路，参考图5和图6，以第二晶体管T2为N型晶体管，其他晶体管为P型晶体管为例，本实施例提供的像素电路的工作过程包括初始化阶段t1、数据写入阶段t2和发光阶段t3。
在初始化阶段t1，第一扫描信号S1为低电平，第二扫描信号S2为低电平，第三扫描信号S3为高电平，发光控制信号EM为高电平，因此，第四晶体管T4和第五晶体管T5导通，初始化电压Vref经第五晶体管T5和第四晶体管T4写入至第一晶体管T1的栅极，将第一晶体管T1的栅极电压复位为初始化电压Vref。此时，第一节点N1的电压与第二节点N2的电压相等，均为初始化电压Vref，因此第二晶体管T2和第三晶体管T3处于关断状态。
在数据写入阶段t2，第一扫描信号S1为低电平，第二扫描信号S2为高电平，第三扫描信号S3为低电平，发光控制信号EM为高电平，因此，第四晶体管T4、第六晶体管T6和第七晶体管T7导通，第五晶体管T5关断，数据电压Vdata经第七晶体管T7、第一晶体管T1、第六晶体管T6和第四晶体管T4写入至第一晶体管T1的栅极，实现第一晶体管T1的数据写入及补偿。此时，第一节点N1和第二节点N2的电压均为Vdata+Vth1。
在发光阶段t3，第一扫描信号S1为高电平，第二扫描信号S2为高电平，第三扫描信号S3为高电平，发光控制信号EM为低电平，因此，第八晶体管T8和第九晶体管T9导通，第一晶体管T1根据其栅极电压产生驱动电流，驱动发光二极管D1发光。
在发光阶段t3，减小第一节点N1漏电的具体工作原理如下：
图7为本申请实施例提供的另一种像素电路的结构示意图，与图5所示像素电路的区别在于，图7所示像素电路不包括漏电抑制模块120、第一补偿子单元141和第二补偿子单元142。在图7中，第一晶体管T1的栅极写入数据电压Vdata后，进入发光阶段，第五晶体管T5和第六晶体管T6均处于关断状态，第一电容C1(第一节点N1)的漏电路径存在两条，一条是经第六晶体管T6漏电，另一条是经过第五晶体管T5漏电。当|VDD-VN1|＞|VN1-Vref|时，在第一电容C1的保压过程中，由于漏流，第一节点N1被充入正电荷，第一节点N1的电压正偏，经过一段时间后达到平衡状态|VDD-VN1|＝|VN1-Vref|，此时第一节点N1的电压为平衡电压。这里的VDD-VN1指的是发光阶段时第六晶体管T6两端的电压差，VN1-Vref指的是第五晶体管T5两端的电压差。反之，当|VDD-VN1|＜|VN1-Vref|时，在第一电容C1的保压过程中，由于漏流，第一节点N1被充入负电荷，第一节点N1的电压负偏，经过一段时间后第一节点N1同样达到平衡电压。因此，图7所示像素电路的第一节点N1的漏流速率逐渐减小，且在漏流初始阶段具有最大漏流速率。
在图5中，在漏流初始时刻，第一节点N1和第二节点N2之间的电压差为零，因此第一节点N1的初始漏流速率为零。随着时间推移，第二节点N2因漏流出现电压偏移，但是由于第四晶体管T4的截止作用，第一节点N1与第二节点N2之间的电压差逐渐增大，第一节点N1开始漏流并逐渐增大，当第二节点N2达到平衡电压时，由于第四晶体管T1存在漏流，第一节点N1继续向第二节点C2漏 流，随着第一节点N1与第二节点N2之间的压差逐渐减小，第一节点N1的漏流也逐渐减小，直到第一节点N1与第二节点N2达到平衡状态。
图8为本申请实施例提供的一种漏流曲线示意图，其中实线表示图7所示像素电路中第一节点N1的漏流，点划线表示图5所示像素电路中第一节点N1的漏流，AA’线表示图7所示像素电路中第一节点N1达到平衡电压所需要的时间，BB’表示图5所示像素电路中第一节点N1达到平衡电压所需要的时间。相比与未设置漏电抑制模块120的像素电路来说，本实施例提供的技术方案使得第一节点N1达到平衡电压的时间更长，也即第一节点N1的漏流速率更慢，尤其是在漏流初始的一段时间内，第一节点N1的漏流趋近于零。
进一步地，在漏流过程中，第一晶体管T1的第二极为正压，而初始化电压Vref为负压，第六晶体管T6两端的电压差与第五晶体管T5两端的电压差不一致，因此两条漏流路径的漏流速率也不同，这就导致第一节点N1与第二节点N2之间的电压差不能维持在0V，仍会有漏电流产生。
在本实施例中，通过增设第二晶体管T2和第三晶体管T3对第二节点N2的电压进行自补偿，从而抑制第一节点N1与第二节点N2之间的漏流。
具体地，根据两条漏电路径的漏流速率不同，当漏流使得第二节点N2的电压正偏，且VN2＞VN1+Vth3时，第三晶体管T3导通，且第二晶体管T2关断，因此初始化电压Vref通过第三晶体管T3向第二节点N2充入负电荷，也即向第二电容C2充入负电荷，直到VN2＝VN1+Vth3时，第三晶体管T3关断，此时可视为第一节点N1与第二节点N2之间的电压达到一个平衡，二者之间的压差较小，有效抑制了第一节点N1与第二节点N2之间的漏流。
当漏流使得第二节点N2的电压负偏，且VN2＜VN1-Vth2时，第二晶体管T2导通，且第三晶体管T3关断，因此第一电源电压VDD通过第二晶体管T2向第二节点N2充入正电荷(也即向第二电容C2充入正电荷)，直到VN2＝VN1-Vth2时，第二晶体管T2关断，此时可视为第一节点N1与第二节点N2之间的电压达到一个平衡，二者之间的压差较小，有效抑制了第一节点N1与第二节点N2之间的漏流。
本实施例中，通过第二晶体管T2和第三晶体管T3的自补偿功能，将第一节点N1和第二节点N2之间的电压差控制在(VN1-|Vth2|)～(VN1+|Vth3|)的范围内，从而有效抑制第一节点N1到第二节点N2的漏流，保证第一节点N1电压的稳定性，进而在低频显示下，防止出现闪烁现象。
图9为本申请实施例提供的另一种像素电路的结构示意图，在上述技术方案的基础上，可选地，第四晶体管T4、第五晶体管T5和第六晶体管T6为双栅晶体管，双栅晶体管比单栅晶体管具有更小的漏电流，能够进一步减小第一节点N1的漏电。
可选地，第一补偿模块140还可以有其他的连接方式。图10为本申请实施例提供的另一种像素电路的结构示意图，图11为本申请实施例提供的另一种像素电路的结构示意图，并示出了图10所示像素电路的具体结构，参考图2和图10，在上述各技术方案的基础上，第一补偿模块140包括第一补偿子单元141和第二补偿子单元142；第一补偿子单元141的第一端与第二补偿模块180连接，第一补偿子单元141的第二端与第二节点N2连接，第一补偿子单元141的控制端与第一节点N1连 接；第二补偿子单元142的第一端与初始化模块130连接，第二补偿子单元142的第二端与第二节点N2连接，第二补偿子单元142的控制端与第一节点N1连接。
具体地，参考图11，第一补偿子单元141包括第二晶体管T2，第二补偿子单元142包括第三晶体管T3，其中，第二晶体管T2连接于第六晶体管T6的中间节点与第二节点N2之间，第三晶体管T3连接于第五晶体管T5的中间节点与第二节点N2之间，相比于图5所示的像素电路，图11所示的像素电路中，第六晶体管T6的中间节点的电压比M1点的电压更接近第一电源电压VDD，正电荷漏流速率更大；第五晶体管T5的中间节点比M2点的电压更接近初始化电压Vref，负电荷的漏流速率更大。当M1点的漏流大于M2点时，通过导通第三晶体管T3，在相同时间内能够向M1点提供更多的负电荷来平衡第二节点N2的电压。当M1点的漏流小于M2点时，通过导通第二晶体管T2，在相同时间内能够向M2点提供更多的正电荷来平衡第二节点N2的电压。此外，由于第二晶体管T2和第三晶体管T3没有直接接入第一电源电压VDD或初始化电压Vref，可以有效避免第二晶体管T2和第三晶体管T3的漏流带来的功耗上升。
可选地，本申请实施例还提供了一种像素电路的驱动方法，用于驱动本申请任意实施例所提供的像素电路。图12为本申请实施例提供的一种像素电路的驱动方法的流程图，结合图1和图12，该像素电路的驱动方法包括：
S110、在初始化阶段，控制初始化模块将初始化电压经漏电抑制模块传输至第一节点，对驱动模块的控制端初始化。
S120、在发光阶段，控制驱动模块驱动发光模块发光，并控制第一补偿模块响应第一节点的电压信号导通，对第二节点进行电压补偿。
本实施例提供的技术方案，采用的像素电路包括驱动模块、漏电抑制模块、初始化模块、第一补偿模块、第一存储模块、第二存储模块和发光模块；驱动模块的控制端与漏电抑制模块连接于第一节点，初始化模块与漏电抑制模块连接于第二节点，初始化模块用于在初始化阶段将初始化电压经漏电抑制模块传输至第一节点，对驱动模块的控制端初始化；驱动模块和发光模块连接于第一电源线和第二电源线之间，驱动模块用于在发光阶段驱动发光模块发光；第一存储模块与第一节点连接，用于存储第一节点的电压；第二存储模块与第二节点连接，用于存储第二节点的电压；第一补偿模块与第二节点连接，用于响应第一节点的电压信号，对第二节点进行电压补偿。在发光阶段，一方面通过设置漏电抑制模块和第二存储模块来稳定第一节点的电位；另一方面，通过设置第一补偿模块对第二节点的电压进行自补偿，以减小第一节点和第二节点之间的电压差，进一步减小漏电流，从而能够改善像素电路的漏电现象，提高显示效果。
可选地，图13为本申请实施例提供的另一种像素电路的驱动方法的流程图，结合图3和图13，该驱动方法包括：
S110、在初始化阶段，控制初始化模块将初始化电压经漏电抑制模块传输至第一节点，对驱动模块的控制端初始化。
S210、在数据写入阶段，控制数据写入模块将数据线上的数据电压经导通的第二补偿模块传输 至驱动模块的控制端。
S121、在发光阶段，控制驱动模块驱动发光模块发光，当第二节点的电压负偏时，控制第一补偿子单元响应第一节点的电压信号导通，对第二节点的电压进行正补偿；当第二节点的电压正偏时，控制第二补偿子单元响应第一节点的电压信号导通，对第二节点的电压进行负补偿。
本实施例提供的像素电路的驱动方法的具体工作原理可参考上述任意实施例中关于像素电路的描述，具备与上述任意实施例所描述的相同的有益效果，在此不再赘述。
可选地，本申请实施例还提供了一种显示面板，包括上述实施例提供的像素电路，因此该显示面板同样具备上述任意实施例所描述的有益效果。图14为本申请实施例提供的一种显示面板的结构示意图，在本实施例中，该显示面板可以应用到手机，也可以应用到任何具有显示功能的电子产品，包括但不限于以下类别：电视机、笔记本电脑、桌上型显示器、平板电脑、数码相机、智能手环、智能眼镜、车载显示器、医疗设备、工控设备、触摸交互终端等，本申请实施例对此不作特殊限定。
应该理解，可以使用上面所示的各种形式的流程，重新排序、增加或删除步骤。例如，本申请中记载的各步骤可以并行地执行也可以顺序地执行也可以不同的次序执行，只要能够实现本申请的技术方案所期望的结果，本文在此不进行限制。
上述具体实施方式，并不构成对本申请保护范围的限制。本领域技术人员应该明白的是，根据设计要求和其他因素，可以进行各种修改、组合、子组合和替代。任何在本申请的精神和原则之内所作的修改、等同替换和改进等，均应包含在本申请保护范围之内。

Claims (10)

  1. 一种像素电路，包括：驱动模块、漏电抑制模块、初始化模块、第一补偿模块、第一存储模块、第二存储模块和发光模块；
    所述驱动模块的控制端与所述漏电抑制模块连接于第一节点，所述初始化模块与所述漏电抑制模块连接于第二节点，所述初始化模块用于在初始化阶段将初始化电压经所述漏电抑制模块传输至所述第一节点，对所述驱动模块的控制端初始化；所述驱动模块和所述发光模块连接于第一电源线和第二电源线之间，所述驱动模块用于在发光阶段驱动所述发光模块发光；
    所述第一存储模块与所述第一节点连接，用于存储所述第一节点的电压；所述第二存储模块与所述第二节点连接，用于存储所述第二节点的电压；
    所述第一补偿模块与所述第二节点连接，用于响应所述第一节点的电压信号，对所述第二节点进行电压补偿。
  2. 根据权利要求1所述的像素电路，其中，还包括第二补偿模块和数据写入模块；
    所述数据写入模块连接于数据线和所述驱动模块的第一端之间，所述第二补偿模块连接于所述驱动模块的第二端和所述第二节点之间；
    所述第一存储模块的第一端与所述第一电源线连接，所述第一存储模块的第二端与所述驱动模块的控制端连接于所述第一节点，所述漏电抑制模块的第一端与所述第一节点连接，所述漏电抑制模块的第二端与所述初始化模块的第二端连接于所述第二节点，所述初始化模块的第一端接入所述初始化电压，所述第二存储模块的第一端与所述第一电源线连接，所述第二存储模块的第二端与所述第二节点连接。
  3. 根据权利要求2所述的像素电路，其中，所述第一补偿模块包括第一补偿子单元和第二补偿子单元；
    所述第一补偿子单元的第一端与所述第一电源线连接，所述第一补偿子单元的第二端与所述第二节点连接，所述第一补偿子单元的控制端与所述第一节点连接；
    所述第二补偿子单元的第一端接入所述初始化电压，所述第二补偿子单元的第二端与所述第二节点连接，所述第二补偿子单元的控制端与所述第一节点连接；
    其中，所述第一补偿子单元和所述第二补偿子单元不同时导通。
  4. 根据权利要求3所述的像素电路，其中，所述驱动模块包括第一晶体管，所述第一补偿子单元包括第二晶体管，所述第二补偿子单元包括第三晶体管；
    所述第二晶体管的栅极与所述第一晶体管的栅极连接于所述第一节点，所述第二晶体管的第一极与所述第二节点连接，所述第二晶体管的第二极与所述第一电源线连接，所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的第一极与所述第二节点连接，所述第三晶体管的第二极接入所述初始化电压；
    所述第二晶体管与所述第三晶体管的沟道类型不同。
  5. 根据权利要求3所述的像素电路，其中，所述第一存储模块包括第一电容，所述第二存储模块包括第二电容；
    所述第一电容的第一端与所述第一电源线连接，所述第一电容的第二端与所述第一节点连接，所述第二电容的第一端与所述第一电源线连接，所述第二电容的第二端与所述第二节点连接；
    所述第一电容的容值大于所述第二电容的容值。
  6. 根据权利要求3所述的像素电路，其中，所述漏电抑制模块包括第四晶体管，所述初始化模块包括第五晶体管，所述第二补偿模块包括第六晶体管，所述数据写入模块包括第七晶体管；所述像素电路还包括第一发光控制模块和第二发光控制模块，所述第一发光控制模块包括第八晶体管，所述第二发光控制模块包括第九晶体管，所述发光模块包括发光二极管；
    所述第四晶体管的栅极接入第一扫描信号，所述第四晶体管的第一极与所述第一节点连接，所述第四晶体管的第二极与所述第二节点连接，所述第五晶体管的栅极接入第二扫描信号，所述第五晶体管的第一极接入所述初始化电压，所述第五晶体管的第二极与所述第二节点连接，所述第六晶体管的栅极接入第三扫描信号，所述第六晶体管的第一极与所述驱动模块的第二端连接，所述第六晶体管的第二极与所述第二节点连接，所述第七晶体管的栅极接入所述第三扫描信号，所述第七晶体管的第一极与所述数据线连接，所述第七晶体管的第二极与所述驱动模块的第一端连接；
    所述第八晶体管的栅极和所述第九晶体管的栅极均接入发光控制信号，所述第八晶体管的第一极与所述第一电源线连接，所述第八晶体管的第二极与所述驱动模块的第一端连接，所述第九晶体管的第一极与所述驱动模块的第二端连接，所述第九晶体管的第二极与所述发光二极管的第一极连接，所述发光二极管的第二极与所述第二电源线连接；
    优选地，所述第四晶体管、所述第五晶体管和所述第六晶体管为双栅晶体管。
  7. 根据权利要求2所述的像素电路，其中，所述第一补偿模块包括第一补偿子单元和第二补偿子单元；
    所述第一补偿子单元的第一端与所述第二补偿模块连接，所述第一补偿子单元的第二端与所述第二节点连接，所述第一补偿子单元的控制端与所述第一节点连接；
    所述第二补偿子单元的第一端与所述初始化模块连接，所述第二补偿子单元的第二端与所述第二节点连接，所述第二补偿子单元的控制端与所述第一节点连接；
    其中，所述第一补偿子单元和所述第二补偿子单元不同时导通。
  8. 一种像素电路的驱动方法，其中，所述像素电路包括驱动模块、漏电抑制模块、初始化模块、第一补偿模块、第一存储模块、第二存储模块和发光模块；所述驱动模块的控制端与所述漏电抑制模块连接于第一节点，所述初始化模块与所述漏电抑制模块连接于第二节点，所述驱动模块和所述发光模块连接于第一电源线和第二电源线之间，所述第一存储模块与所述第一节点连接，所述第二存储模块与所述第二节点连接，所述第一补偿模块与所述第二节点连接；
    所述像素电路的驱动方法包括：
    在初始化阶段，控制所述初始化模块将初始化电压经所述漏电抑制模块传输至所述第一节点，对所述驱动模块的控制端初始化；
    在发光阶段，控制所述驱动模块驱动所述发光模块发光，并控制所述第一补偿模块响应所述第一节点的电压信号导通，对所述第二节点进行电压补偿。
  9. 根据权利要求8所述的像素电路的驱动方法，其中，所述像素电路还包括第二补偿模块和数据写入 模块，所述数据写入模块连接于数据线和所述驱动模块的第一端之间，所述第二补偿模块连接于所述驱动模块的第二端和所述第二节点之间；
    在所述发光阶段之前，所述像素电路的驱动方法还包括：
    在数据写入阶段，控制所述数据写入模块将所述数据线上的数据电压经导通的所述第二补偿模块传输至所述驱动模块的控制端；
    所述第一补偿模块包括第一补偿子单元和第二补偿子单元，所述第一补偿子单元的第一端与所述第一电源线连接，所述第一补偿子单元的第二端与所述第二节点连接，所述第一补偿子单元的控制端与所述第一节点连接；所述第二补偿子单元的第一端接入所述初始化电压，所述第二补偿子单元的第二端与所述第二节点连接，所述第二补偿子单元的控制端与所述第一节点连接；
    所述控制所述第一补偿模块响应所述第一节点的电压信号导通，对所述第二节点进行电压补偿的步骤具体包括：
    当所述第二节点的电压负偏时，控制所述第一补偿子单元响应所述第一节点的电压信号导通，对所述第二节点的电压进行正补偿；
    当所述第二节点的电压正偏时，控制所述第二补偿子单元响应所述第一节点的电压信号导通，对所述第二节点的电压进行负补偿。
  10. 一种显示面板，包括如权利要求1-7任一项所述的像素电路。
PCT/CN2022/128102 2022-09-22 2022-10-28 像素电路及其驱动方法和显示面板 WO2024060355A1 (zh)

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