WO2024059976A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2024059976A1
WO2024059976A1 PCT/CN2022/119699 CN2022119699W WO2024059976A1 WO 2024059976 A1 WO2024059976 A1 WO 2024059976A1 CN 2022119699 W CN2022119699 W CN 2022119699W WO 2024059976 A1 WO2024059976 A1 WO 2024059976A1
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WIPO (PCT)
Prior art keywords
gate
via holes
array substrate
coupled
layer
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Application number
PCT/CN2022/119699
Other languages
English (en)
French (fr)
Inventor
张亚东
雷阳军
吴博
左雄灿
李挺
汤春苗
杨永菊
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/119699 priority Critical patent/WO2024059976A1/zh
Priority to CN202280003216.6A priority patent/CN118057966A/zh
Publication of WO2024059976A1 publication Critical patent/WO2024059976A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a display device.
  • TFT-LCD Thin film transistor-liquid crystal display
  • the array substrate in a TFT-LCD display device includes: a substrate with a display area and a non-display area, TFTs and electrodes located in the display area, and common electrodes located in the non-display area and arranged sequentially in a direction away from the display area. Electrode lines and gate driving circuits, as well as gate line leads and gate lines located in the display area and the non-display area and located in different layers.
  • the common electrode line is coupled to the electrodes and provides driving signals to the electrodes.
  • the gate drive circuit is coupled to the TFT through the gate line lead and the gate line, and provides a gate drive signal to the TFT. Moreover, since the gate line leads and the gate lines are located on different layers, the gate line leads and the gate lines need to be transferred through the transfer hole.
  • the non-display area requires a large area of the substrate, which is not conducive to the design of a narrow frame of the array substrate.
  • an array substrate which includes:
  • a substrate having a display area and a wiring area and a circuit area located on at least one side of the display area and sequentially arranged in a direction away from the display area;
  • a common electrode line extending along the first direction is located in the wiring area, the common electrode line has a plurality of dug holes arranged at intervals, and the common electrode line is coupled to the plurality of pixels;
  • a plurality of gate lines extending along a second direction are located in the display area and the wiring area, and the second direction intersects the first direction;
  • a plurality of gate line leads extending along the second direction are located in the circuit area and the wiring area, are located on a side of the gate line away from the substrate, and are located on the common electrode line close to the one side of the substrate;
  • a gate drive circuit is located in the circuit area, the gate drive circuit is coupled to the plurality of gate line leads, the plurality of gate line leads are connected to the multiple gate lines, and the transfer part is located at In the dug hole, the plurality of gate lines are also coupled to the plurality of pixels.
  • the plurality of The holes are dug at intervals along the first direction.
  • the gate driving circuit includes: a plurality of shift register units sequentially arranged and cascaded along the first direction, and the plurality of pixel arrays are arranged;
  • the plurality of shift register units are coupled to the plurality of gate line leads in a one-to-one correspondence
  • the plurality of gate line leads and the plurality of gate lines are connected in a one-to-one correspondence
  • the transfer parts are connected in a one-to-one correspondence.
  • the plurality of gate lines are coupled to the plurality of rows of pixels in one-to-one correspondence.
  • each of the gate line leads, each of the dug holes, and each of the gate lines in one-to-one correspondence are arranged in sequence along the same horizontal line in the second direction.
  • the array substrate also includes:
  • a first insulating layer located between the gate line and the gate line lead;
  • a second insulating layer located on a side of the gate line lead away from the substrate;
  • a first transfer portion located on the side of the second insulating layer away from the substrate
  • the orthographic projection of the gate line lead on the substrate is located within the orthographic projection of the gate line on the substrate, and the orthographic projection of the plurality of first via holes on the substrate is equal to Orthographic projections of the plurality of second via holes on the substrate do not overlap;
  • the first adapter part overlaps with the gate line leads through the plurality of first via holes, and overlaps with the gate line through the plurality of second via holes, so as to connect the gate The wire is connected to the grid wire lead.
  • the number of the plurality of first via holes is the same as the number of the plurality of second via holes.
  • the number of the plurality of first via holes and the number of the plurality of second via holes are both greater than or equal to 4 and less than or equal to 8.
  • the plurality of first via holes are divided into a plurality of first via hole groups arranged sequentially along the first direction, and each first via hole group includes a plurality of first via hole groups arranged sequentially along the second direction. a plurality of first via holes, and the number of first via holes included in each first via hole group is less than or equal to the number of the plurality of first via hole groups;
  • the plurality of second via holes are divided into a plurality of second via hole groups arranged sequentially along the first direction, and each second via hole group includes a plurality of second via hole groups arranged sequentially along the second direction. Two via holes, and the number of second via holes included in each second via hole group is less than or equal to the number of the plurality of second via hole groups.
  • the number of the plurality of first via holes and the number of the plurality of second via holes are both 4;
  • the plurality of first via holes are divided into two first via hole groups arranged sequentially along the first direction, and each first via hole group includes two first via hole groups arranged sequentially along the second direction. first via hole;
  • the plurality of second via holes are divided into two second via hole groups arranged sequentially along the first direction, and each second via hole group includes two second via hole groups arranged sequentially along the second direction. Second via hole.
  • the first transfer part and the common electrode line are located on the same layer.
  • the array substrate further comprises: a common electrode lead located in the routing area, the common electrode lead comprising: a first electrode line and a second electrode line located between the substrate and the common electrode line and sequentially stacked in a direction away from the substrate;
  • the array substrate further includes: a third insulating layer located between the first electrode line and the second electrode line, and a fourth insulating layer located between the second electrode line and the common electrode line;
  • the common electrode line overlaps with the second electrode line through a via hole penetrating the fourth insulating layer, and is connected to the second electrode line through a via hole penetrating the third insulating layer and the fourth insulating layer.
  • the first electrode lines are overlapped for receiving a common signal provided from the first electrode line and the second electrode line.
  • the first electrode line includes a plurality of first electrode blocks arranged at intervals
  • the second electrode line includes a plurality of second electrode blocks arranged at intervals.
  • the pixel includes: a gate metal layer, a gate insulating layer, a source and drain metal layer, a passivation layer and an electrode layer sequentially stacked in a direction away from the substrate;
  • first electrode line and the gate line are located on the same layer, and both are located on the same layer as the gate metal layer;
  • the second electrode line and the gate line lead are located on the same layer, and both are located on the same layer as the source and drain metal layers;
  • the first insulating layer and the third insulating layer are located on the same layer, and both are located on the same layer as the gate insulating layer;
  • the second insulating layer and the fourth insulating layer are located on the same layer, and both are located on the same layer as the passivation layer;
  • the common electrode line and the electrode layer are located on the same layer.
  • each shift register unit in the gate drive circuit includes: an input circuit and an output circuit;
  • the input circuit is coupled to a plurality of drive signal lines and a pull-up node respectively, and is used to charge the pull-up node in response to drive signals provided by the plurality of drive signal lines;
  • the output circuit is coupled to the pull-up node and the gate line lead respectively, and is used to transmit a gate driving signal to the gate line lead based on the potential of the pull-up node.
  • the input circuit, the output circuit and the plurality of drive signal lines include: a gate metal layer, a gate insulation layer, a source and drain metal layer and a passivation layer sequentially stacked in a direction away from the substrate. ;
  • the array substrate further includes: a second transfer portion located on a side of the passivation layer away from the substrate, and the second transfer portion is connected to the passivation layer through a plurality of third via holes penetrating the passivation layer.
  • the source and drain metal layers are overlapped, and are overlapped with the gate metal layer through a plurality of fourth via holes penetrating the passivation layer and the gate insulation layer, so as to connect the input circuit and the drive signal line. coupled at a coupling node, and coupling the input circuit and the output circuit at the pull-up node;
  • the orthographic projection of the source and drain metal layer on the substrate is located within the orthographic projection of the gate metal layer on the substrate, and the orthogonal projection of the plurality of third via holes on the substrate is The projection does not overlap with the orthographic projection of the plurality of fourth via holes on the substrate;
  • the number of third via holes that are coupled and penetrated at the pull-up node is greater than the number of third via holes that are coupled and penetrated at the coupling node; and, at the pull-up node
  • the number of fourth via holes penetrated by coupling is greater than the number of fourth via holes penetrated by coupling at the coupling node.
  • the number of third via holes penetrated by coupling at the pull-up node is the same as the number of fourth via holes penetrated;
  • the number of third via holes penetrated by coupling at the coupling node is the same as the number of fourth via holes penetrated.
  • the number of third via holes and the number of fourth via holes that are coupled through at the pull-up node are both greater than or equal to 3 and less than or equal to 6;
  • the number of third via holes and the number of fourth via holes penetrated are both less than or equal to 2.
  • a plurality of third via holes coupled through at the pull-up node and a plurality of third via holes coupled through at the coupling node are divided into lines along the first A plurality of third via groups arranged sequentially in two directions, each third via group including a third via hole;
  • a plurality of fourth via holes coupled through at the pull-up node, and a plurality of fourth via holes coupled through through at the coupling node are divided into sequential rows along the second direction.
  • a plurality of fourth via hole groups are arranged, each fourth via hole group includes a fourth via hole, and the fourth via hole group and the third via hole group are sequentially arranged along the first direction.
  • the number of the plurality of third via holes and the number of the plurality of fourth via holes that are coupled and penetrated at the pull-up node are both 3;
  • the number of third via holes and the number of fourth via holes are both 2;
  • the plurality of third via holes that are coupled and penetrated at the pull-up node are divided into three third via groups arranged sequentially along the second direction.
  • the plurality of third via holes that are coupled and penetrated at the pull-up node are
  • the plurality of fourth via holes include three fourth via hole groups arranged sequentially along the second direction;
  • the plurality of third via holes that are coupled and penetrated at the coupling node are divided into two third via hole groups arranged sequentially along the second direction.
  • the plurality of third via holes that are coupled and penetrated at the coupling node are
  • the plurality of fourth via holes include two fourth via hole groups arranged sequentially along the second direction.
  • the second transfer part and the common electrode line are located on the same layer.
  • the first direction is perpendicular to the second direction.
  • a display device which includes: a power supply component, and the array substrate as described in the above aspect;
  • the power supply component is coupled to the array substrate and used to power the array substrate.
  • the display device includes: a vehicle-mounted display device.
  • Figure 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
  • Figure 2 is a schematic cross-sectional view of the structure shown in Figure 1 in the a1-a2 direction;
  • Figure 3 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • Figure 4 is another schematic cross-sectional view of the structure shown in Figure 1 in the a1-a2 direction;
  • Figure 5 is a top view of a partial area of the structure shown in Figure 4.
  • Figure 6 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic cross-sectional view of the structure shown in Figure 6 in the b1-b2 direction;
  • Figure 8 is a schematic cross-sectional view of the structure shown in Figure 6 in the c1-c2 direction;
  • Figure 9 is a schematic cross-sectional view of pixels in a display area provided by an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of the structure of a shift register unit provided in an embodiment of the present disclosure.
  • Figure 11 is a schematic cross-sectional view of a shift register unit provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic diagram of an analog voltage provided by an embodiment of the present disclosure.
  • Figure 13 is a structural layout of a shift register unit provided by an embodiment of the present disclosure.
  • Figure 14 is a top view of different nodes of the structure shown in Figure 13;
  • Figure 15 is a flow chart of a method for preparing an array substrate provided by an embodiment of the present disclosure.
  • FIG. 16 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the frame of the array substrate can be compressed (that is, the array substrate with a narrow frame is designed). ) to improve the display effect and meet users’ needs for display effect.
  • array substrate row drive gate drive on array, GOA
  • GOA gate drive on array
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure. As shown in Figure 1, the array substrate includes:
  • the substrate 01 has a display area A1 and a wiring area A2 and a circuit area A3 located on at least one side of the display area A1 and sequentially arranged in a direction away from the display area A1. That is, on at least one of the sides of the display area A1, the circuit area A3 and the wiring area A2 are adjacent and in contact, and the wiring area A2 and the at least one side of the display area A1 are adjacent and in contact. Correspondingly, it can be seen that the wiring area A2 is located between the circuit area A3 and the display area A1. In the embodiment of the present disclosure, the wiring area A2 and the circuit area A3 may also be called a non-display area.
  • the display area A1 of the substrate 01 shown therein is rectangular and has four sides.
  • the substrate 01 has a wiring area A2 and a circuit area A3 located on the left side of the rectangular display area A1 and arranged in sequence in a direction away from the display area A1.
  • the wiring area A2 and the circuit area A3 it has may also be located on the right side, upper side and/or lower side of the display area A1.
  • the display area A1 may also be in other shapes, such as a circle, an ellipse, a trapezoid or a triangle.
  • FIG. 1 only schematically shows the area of each area in the display area A1, wiring area A2 and circuit area A3.
  • the area of the display area A1 is generally larger, while the area of the wiring area A2 and the area of the circuit area A3 can both be smaller, laying the foundation for the narrow frame design of the array substrate and ensuring a good display effect.
  • the area of each region refers to the area occupied by the substrate 01.
  • the array substrate recorded in the embodiment of the present disclosure also includes:
  • a plurality of pixels 02 are located in the display area A1.
  • the common electrode line Com1 extends along the first direction X1, and the common electrode line Com1 is located in the wiring area A2. Furthermore, the common electrode line Com1 is coupled (ie, electrically connected) to the plurality of pixels 02 and is used to provide a common signal to the plurality of pixels 02 .
  • the pixel 02 may include a common electrode, and the common electrode line Com1 may be coupled to the common electrode and used to provide a common signal to the common electrode. It should be noted that the coupling between the common electrode line Com1 and the pixel 02 is not shown in FIG. 1 .
  • the common electrode line Com1 recorded in the embodiment of the present disclosure may have a plurality of dug holes D arranged at intervals, and the dug holes D penetrate the common electrode line Com1.
  • a plurality of gate lines G1 extending along the second direction X2 are located in the display area A1 and the routing area A2. That is, each gate line G1 may be partially located in the display area A1 and partially located in the routing area A2. And the second direction X2 and the first direction X1 may intersect, that is, they may not be parallel.
  • the gate line G1, the gate line lead G2 and the common electrode line Com1 are respectively located in different layers and are sequentially stacked in a direction away from the substrate 01.
  • the positional relationship between the gate line G1, the gate line lead G2 and the common electrode line Com1 can also be changed.
  • the gate line G1 is located between the gate line lead G2 and the common electrode line Com1.
  • the gate driving circuit 03 is located in the circuit area A3. Furthermore, the gate driving circuit 03 is coupled to a plurality of gate line leads G2, the plurality of gate line leads G2 are connected to a plurality of gate lines G1, and the plurality of gate lines G1 are also coupled to a plurality of pixels 02. That is, the gate driving circuit 03 may be coupled to the pixel 02 through the gate line lead G2 and the gate line G1 that are connected to each other. And, the gate driving circuit 03 is used to provide gate driving signals to the plurality of pixels 02 through the plurality of gate line leads G2 and the plurality of gate lines G1.
  • the pixel 02 may include a TFT, and the gate driving circuit 03 may be coupled to the TFT through the mutually connected gate line lead G2 and the gate line G1 to provide a gate driving signal to the TFT and control the TFT to turn on or off.
  • the pixel 02 may also include a pixel electrode, and liquid crystal molecules located between the pixel electrode and the common electrode. After the TFT is turned on, it can charge the pixel electrode, and the liquid crystal molecules can be deflected by the voltage difference between the voltage on the pixel electrode and the voltage on the common electrode, so that pixel 02 is lit.
  • the array substrate including the pixel 02 is the LCD substrate.
  • the transfer portion between the gate line lead G2 and the gate line G1 located on different layers is located in the digging hole D. That is, it is located in the area defined by the common electrode line Com1, which can also be considered to be located inside the wiring area A2, and the orthographic projection of the transfer part on the substrate 01 is the same as the common electrode line Com1 with the hole D on the substrate 01 orthographic projections overlap.
  • the space of the wiring area A2 can be fully utilized, so that the area occupied by the non-display area including the wiring area A2 and the circuit area A3 of the substrate 01 can be smaller, thereby facilitating the narrow frame design of the array substrate.
  • the transfer part between the gate line lead G2 and the gate line G1 is generally located between the wiring area A2 and the circuit area A3, that is, on the side of the wiring area A2 away from the display area A1, but not located on the wiring area A2 .
  • the transfer part is close to the boundary of the substrate 01 where water vapor can enter, water vapor can easily invade the effective lines. Partly, this causes poor reliability problems, which are more obvious in scenarios with higher temperatures and higher humidity. This competes with some products that have strict reliability requirements (such as automotive display products).
  • the related technology also adjusts the transition part between the gate line lead G2 and the gate line G1 to between the wiring area A2 and the display area A1, that is, it is located on the side of the wiring area A2 close to the display area A1, but not Located in wiring area A2.
  • the transfer part is close to the display area A1
  • the electric field at the transfer part inevitably affects the driving electric field required to light up the pixel 02 in the display area A1, such as affecting the electric field that drives the deflection of liquid crystal molecules, causing the driving liquid crystal to The electric field deflected by the molecules deviates from the normal voltage, causing the pixel 02 close to the wiring area A2, that is, the edge of the display area A1, to emit abnormal light.
  • the display effect of the array substrate is poor and the product yield is low.
  • multiple pixels 02 include red pixels, green pixels and blue pixels, and the pixel 02 close to the wiring area A2 is a red pixel, it will cause the luminous brightness of the red pixel to be greater than the luminous brightness of the green pixel and the luminous brightness of the blue pixel. Brightness, light leakage occurs in red pixels.
  • the transition part in the routing area A2 and in the hole of the common electrode line Com1 not only can the narrow frame design of the array substrate be better facilitated as described in the above embodiment, but also the intrusion of external water vapor into the effective line part can be avoided, thereby improving the reliability of the product. It can also avoid the electric field of the transition part from affecting the electric field in the display area A1, thereby improving the light leakage problem, improving the display effect, and improving the product yield.
  • the frame can be made narrower while ensuring the high reliability requirements of the vehicle-mounted product, and at the same time, the light leakage phenomenon at the edge of the array substrate can be avoided.
  • the array substrate described in the embodiment of the present disclosure can be well applied to narrow-frame display products.
  • inventions of the present disclosure provide an array substrate.
  • the array substrate includes: a substrate with a display area, a wiring area and a circuit area adjacent in sequence, a pixel located in the display area, a common electrode line located in the wiring area and having a hole, a gate located in the wiring area and the circuit area Line leads, gate lines located in the wiring area and display area, and gate drive circuits located in the circuit area.
  • the gate line leads and the gate lines are located in different layers and are connected to each other.
  • the gate driving circuit is coupled to the pixel through the mutually connected gate line leads and gate lines, and provides gate driving signals to the pixels.
  • the common electrode lines are coupled to the pixels and provide common signals to the pixels.
  • the connecting part between the gate line lead and the gate line is located in the dug hole of the common electrode line, that is, it is located in the wiring area, making full use of the space, it can make other parts except the display area occupy a smaller area of the substrate. This can better facilitate the design of a narrow frame of the array substrate.
  • the first direction X1 and the second direction X2 recorded in the embodiment of the present disclosure may be perpendicular.
  • each dug hole D of the common electrode line Com1 may be arranged at intervals along the first direction X1.
  • the edge of each dug hole D of the common electrode line Com1 is spaced from the edge of the common electrode line Com1, and is equally spaced from any edge of the common electrode line Com1 in the second direction X2. That is, each dug hole D is surrounded by the remaining portion of the common electrode line Com1 except for the dug hole D.
  • the central axis of each dug hole D overlaps the central axis of the common electrode line Com1, and is located in the common At the center of electrode line Com1.
  • the gate driving circuit 03 recorded in the embodiment of the present disclosure may include: a plurality of shift register units 031 arranged in sequence and cascaded along the first direction X1.
  • the shift register unit 031 may also be called a GOA unit.
  • the plurality of pixels 02 recorded in the embodiment of the present disclosure may be arranged in an array. That is, the array substrate includes multiple rows and columns of pixels arranged along the row direction and the column direction.
  • the first direction X1 and the column direction can be the same direction
  • the second direction X2 and the row direction can be the same direction.
  • a plurality of shift register units 031 can be coupled one-to-one with a plurality of gate line leads G2, a plurality of gate line leads G2 can be switched one-to-one with a plurality of gate lines G1, and the switching portion can be located in a plurality of holes D one-to-one, and a plurality of gate lines G1 can be coupled one-to-one with a plurality of rows of pixels 02. That is, each shift register unit 031 can be coupled with a gate line lead G2, and each shift register unit 031 is coupled with different gate line leads G2. Each gate line lead G2 is switched with a gate line G1, and each gate line lead G2 is switched with different gate lines G1.
  • Each gate line G1 is coupled with a row of pixels 02, and each gate line G1 is coupled with different rows of pixels 02.
  • Each shift register unit 031 is used to provide a gate drive signal to a row of pixels 02 through a gate line lead G2 and a gate line G1, so that progressive scanning can be realized.
  • each shift register unit 031 may also be coupled to two or more rows of pixels 02 through gate line leads G2 and gate lines G1.
  • each gate line lead G2 , each digging hole D and each gate line G1 corresponding one-to-one can be along the second direction X2 .
  • the same horizontal line is arranged one after another. That is, for each gate line G2, the gate line lead G2, the digging hole D corresponding to the gate line lead G2, and the gate line G1 corresponding to the gate line lead G2 are located on the same line along the second direction.
  • the array substrate recorded in the embodiment of the present disclosure may also include:
  • the first insulating layer J1 is located between the gate line G1 and the gate line lead G2.
  • the second insulating layer J2 is located on the side of the gate line lead G2 away from the substrate 01 .
  • the first transition portion B1 is located on the side of the second insulating layer J2 away from the substrate 01 .
  • FIG. 4 only schematically shows two second via holes K2 and one first via hole K1.
  • the orthographic projection of the gate line lead G2 on the substrate 01 can be located within the orthographic projection of the gate line G1 on the substrate 01, and the plurality of first via holes K1 are located on the substrate 01.
  • the orthographic projection and the orthographic projection of the plurality of second via holes K2 on the substrate 01 may not overlap.
  • the first adapter portion B1 can overlap with the gate line lead G2 through a plurality of first via holes K1, and can overlap with the gate line G1 through a plurality of second via holes K2, so as to connect the gate line G1 and the gate line lead. G2 transfer.
  • the gate line G1 and the gate line lead G2 can be indirectly transferred through the first transfer portion B1, and the first via K1 and the second via K2 can be considered as transfer holes between the gate line G1 and the gate line lead G2.
  • the first via K1 and the second via K2 can be considered as transfer holes between the gate line G1 and the gate line lead G2.
  • a plurality of first via holes K1 and a plurality of second via holes K2 are connected in parallel.
  • the array substrate may only have a via hole that penetrates the first insulating layer J1 and exposes the gate line G1.
  • the gate line lead G2 may pass through the first insulating layer J1 and expose the gate line.
  • Line G1 directly overlaps the grid line.
  • the number of first vias K1 and the number of second vias K2 may be the same.
  • the number of first via holes K1 and second via holes K2 may be the same, it can be ensured that the resistance at the plurality of first via holes K1 and the resistance at the plurality of second via holes K2 are the same, further ensuring reliable transfer, and connection stability.
  • the number of the plurality of first via holes K1 and the number of the plurality of second via holes K2 may be greater than or equal to 4 and less than or equal to 8.
  • the plurality of first via holes K1 can be divided into a plurality of first via hole groups K10 arranged sequentially along the first direction X1.
  • Each first via hole The group K10 may include a plurality of first via holes K1 sequentially arranged along the second direction X2, and the number of the first via holes K1 included in each first via hole group K10 may be less than or equal to the plurality of first via hole groups K10 quantity.
  • the plurality of second via holes K2 may be divided into a plurality of second via hole groups K20 arranged sequentially along the first direction X1, and each second via hole group K20 may include a plurality of second via hole groups K20 arranged sequentially along the second direction X2.
  • There are a plurality of second via holes K2 and the number of the second via holes K2 included in each second via hole group K20 may be less than or equal to the number of the plurality of second via hole groups K20.
  • the length of the connecting portion of the gate line lead G2 and the gate line G1 in the first direction X1 is greater than or equal to the length in the second direction X2, that is, the length of the connecting portion of the gate line lead G2 and the gate line G1 is The length direction is parallel to the first direction X1. Furthermore, the space in the wiring area A2 can be better utilized, so that the area occupied by the non-display area of the substrate 01 can be small enough, laying a good foundation for the design of narrow borders.
  • the number of the plurality of first via holes K1 and the number of the plurality of second via holes K2 shown therein may both be four.
  • the plurality of first via holes K1 may be divided into two first via hole groups K10 arranged in sequence along the first direction X1, and each first via hole group K10 may include a group of first via holes K10 arranged in sequence in the second direction X2.
  • the plurality of second via holes K2 may be divided into two second via hole groups K20 arranged sequentially along the first direction X1, and each second via hole group K20 may include two second via hole groups K20 arranged sequentially along the second direction X2.
  • the first transfer part B1 and the common electrode line Com1 may be located on the same layer.
  • being on the same layer may refer to a layer structure formed by using the same film formation process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or portions located on "the same layer" are made of the same material and formed through the same patterning process. In this way, the manufacturing process and manufacturing costs can be saved, and the manufacturing efficiency can be accelerated.
  • Figure 6 shows a structural layout of an array substrate.
  • the common electrode line Com1 located in the wiring area has a digging hole D
  • the gate line lead G2 located in the circuit area A3 and the wiring area A2 and the gate line G1 located in the wiring area A2 and the display area A1 Connect through the transfer hole in the dug hole D.
  • Figure 4 can be considered as a cross-sectional view of the structural layout shown in Figure 6 in the a3-a4 direction.
  • Figure 7 shows a cross-sectional view of the structural layout shown in Figure 6 in the b1-b2 direction.
  • FIG. 8 shows a cross-sectional view of the structural layout shown in FIG. 6 in the c1-c2 direction. It can be seen from FIG. 4, FIG. 7 and FIG. 8 that the array substrate recorded in the embodiment of the present disclosure may also include: a common electrode lead Com2 located in the wiring area A2.
  • the common electrode lead Com2 may include: a first electrode line Com21 and a second electrode line Com22 that are located between the substrate 01 and the common electrode line Com1 and are sequentially stacked in a direction away from the substrate 01 .
  • the array substrate may further include: a third insulation layer J3 located between the first electrode line Com21 and the second electrode line Com22, and a fourth insulation layer J3 located between the second electrode line Com22 and the common electrode line Com1.
  • Layer J4 located between the first electrode line Com21 and the second electrode line Com22.
  • the common electrode line Com1 can overlap with the second electrode line Com22 through a via hole (not marked in the figure) that penetrates the fourth insulating layer J4, and can pass through a via hole that penetrates the third insulating layer J3 and the fourth insulating layer J4. (not identified in the figure) is connected to the first electrode line Com21 for receiving a common signal provided from the first electrode line Com21 and the second electrode line Com22. That is, the source of the common signal can be provided by an external integrated circuit (IC) to the common electrode lead Com2, and then the common electrode lead Com2 is conducted to the common electrode line Com1 located in the wiring area A2, and finally the common electrode lead Com2 The line Com1 is conducted to the common electrode located in the display area A1.
  • IC external integrated circuit
  • both the first electrode line Com21 and the second electrode line Com22 may include a plurality of electrode blocks arranged at intervals. That is, as shown in FIGS. 6 and 7 , neither the first electrode line Com21 nor the second electrode line Com22 is provided entirely on one side of the substrate 01 , but includes a plurality of spaced parts.
  • the common electrode line Com1 and the spaced parts All parts are connected. This design can also be considered as a grid design of the common electrode lead Com2.
  • the common electrode lead Com2 By designing the common electrode lead Com2 in a grid, it is possible to reduce the placement of large pieces of solid metal on the substrate 01 and prevent other film layers (such as active layers) from being burned due to the large heating area of the large piece of metal during the preparation process. damage to ensure better product yield. Based on the grid design of the common electrode lead Com2, it will lead to a certain waste of space. If combined with the layout method of related technologies, it will conflict with the requirements of narrow frame design. In the embodiment of the present disclosure, since the layout of the transfer part and the common electrode line Com1 is adjusted, the space waste problem caused by the grid design of the common electrode lead Com2 can be avoided.
  • FIG. 9 shows a cross-sectional view of pixels in a display area.
  • the pixel 02 recorded in the embodiment of the present disclosure may include: a gate metal layer Gate, a gate insulator (GI) layer GI, and a source and drain (SD) layer sequentially stacked in a direction away from the substrate 01 Metal layer SD, passivation layer PVX and electrode layer ITO.
  • a gate metal layer Gate a gate metal layer Gate
  • GI gate insulator
  • SD source and drain
  • the first electrode line Com21 recorded in the embodiment of the present disclosure can be located on the same layer as the gate line G1, and both can be located on the same layer as the gate metal layer Gate.
  • the second electrode line Com22 may be located on the same layer as the gate line lead G2, and both may be located on the same layer as the source-drain metal layer SD.
  • the first insulating layer J1 and the third insulating layer J3 may be located on the same layer, and both may be located on the same layer as the gate insulating layer GI.
  • the second insulating layer J2 and the fourth insulating layer J4 can be located on the same layer, and both can be located on the same layer as the passivation layer PVX.
  • the common electrode line Com1 may be located on the same layer as the electrode layer ITO. In this way, the manufacturing process and manufacturing cost can be further saved, and the manufacturing efficiency can be further accelerated.
  • the array substrate may include a gate metal layer Gate, a gate insulating layer GI, a source-drain metal layer SD, a passivation layer PVX and an electrode layer that are sequentially stacked in the direction away from the substrate 01 ITO.
  • the gate line lead G2 can be formed using the source-drain metal layer SD
  • the gate line G1 can be formed using the gate metal layer Gate
  • the source-drain metal layer SD and the gate metal layer Gate can be overlapped by the electrode layer ITO respectively, to achieve
  • the conduction between the source-drain metal layer SD and the gate metal layer Gate realizes reliable coupling between the gate line lead G2 and the gate line G1.
  • the common electrode lead Com2 can be formed by the source-drain metal layer SD and the gate metal layer Gate
  • the common electrode line Com1 can be formed by the electrode layer ITO
  • the common signal can be transmitted by the IC through the source-drain metal layer SD and the gate metal layer Gate conducts to the electrode layer ITO located in the wiring area A2, and finally conducts from the electrode layer ITO located in the wiring area A2 to the electrode layer ITO included in the pixel 02 located in the display area A1.
  • the pixel 02 recorded in the embodiment of the present disclosure may also include: an active layer Ac1 and another conductive layer located between the gate insulating layer GI and the source and drain metal layer SD. ITO.
  • the conductive layer ITO located on the same layer as the common electrode line Com1 is marked as "ITO (2)”
  • the other conductive layer ITO is marked as "ITO (2)”. is "ITO(1)”.
  • one electrode layer can be a pixel electrode, and the other electrode layer can be a common electrode.
  • the embodiment of the present disclosure takes the electrode layer ITO (2) as a common electrode and the electrode layer ITO (1) as a pixel electrode as an example for description.
  • the active layer Ac1 may overlap the source-drain metal layer SD, and the orthographic projection of the active layer Ac1 on the substrate 01 does not overlap with the orthographic projection of the electrode layer ITO (2) on the substrate 01 .
  • the via holes penetrating the passivation layer PVX and the gate insulating layer GI, and the via holes penetrating the passivation layer PVX can be drilled through a single mask process to simplify the manufacturing process, save manufacturing costs, and speed up manufacturing efficiency.
  • the 6mask process refers to the preparation of masks in 6 steps.
  • the six steps include: (1): Using a mask to form a gate metal layer Gate on the substrate 01. Afterwards, a deposition process may be used to form a gate insulating layer GI on the side of the gate metal layer Gate away from the substrate 01 . (2) Use a mask to form the active layer Ac1 on the side of the gate insulating layer GI away from the substrate 01. (3) Use a mask to form an electrode layer ITO (1) on the side of the gate insulating layer GI away from the substrate 01. (4) Use a mask to form the source and drain metal layer SD on the side of the active layer Ac1 away from the substrate 01. (5) Use a mask to form a passivation layer PVX on the side of the source and drain metal layer SD away from the substrate 01.
  • the TFT in pixel 02 prepared by this process can be called a bottom-gate TFT.
  • the TFT may also be a top-gate TFT.
  • the gate metal layer Gate may be located on the side of the active layer Ac1 away from the substrate 01 .
  • the material of the gate metal layer Gate may include: metal material or alloy material.
  • Metals such as molybdenum (Mo), aluminum (Al) and titanium (Ti).
  • the materials of the gate insulating layer GI and the passivation layer PVX may include inorganic materials. For example, silicon oxide (SiOx) or silicon nitride (SiNx).
  • the material of the active layer Ac1 may include: polysilicon material.
  • the material of the source and drain metal layer SD may include: metal materials or alloy materials.
  • the material of the source and drain metal layer SD may include Mo, aluminum (Al), titanium (Ti), etc.
  • the materials of the electrode layers ITO (1) and ITO (2) may include: indium tin oxide (ITO), which is a transparent material that can ensure good light transmittance.
  • ITO indium tin oxide
  • the materials of the electrode layers ITO (1) and ITO (2) may also include other types of transparent materials, such as indium zinc oxide or zinc oxide.
  • the substrate 01 may have a single-layer structure or a double-layer structure, and the substrate 01 may be a rigid substrate made of glass or a flexible substrate made of polyimide flexible material.
  • the array substrate may further include: a plurality of data lines located in the display area A1. Multiple data lines may be coupled to multiple columns of pixels 02 in one-to-one correspondence to provide data signals for the pixels 02 .
  • the data line may be located on the same layer as the source-drain metal layer SD.
  • FIG. 10 is a schematic structural diagram of a shift register unit 031 provided by an embodiment of the present disclosure.
  • each shift register unit 031 in the gate driving circuit 03 may include: an input circuit 0311 and an output circuit 0312.
  • the input circuit 0311 is coupled to a plurality of driving signal lines (not shown in the figure) and the pull-up node PU respectively, and can be used to charge the pull-up node PU in response to the driving signals provided by the plurality of driving signal lines.
  • the output circuit 0312 may be coupled to the pull-up node PU and the gate line lead G2 respectively, and may be used to transmit a gate driving signal to the gate line lead G2 based on the potential of the pull-up node PU. Based on this, it can be seen that the gate line lead G2 recorded in the embodiment of the present disclosure is actually the output terminal of the shift register unit 031.
  • the driving signal lines may include: clock signal lines, power lines and/or reset signal lines.
  • the output circuit 0312 can generally be coupled with a clock signal line to transmit a clock signal from the clock signal line to the gate line G2 based on the potential of the pull-up node PU, and the clock signal can be used as a gate drive signal.
  • FIG. 11 is a partial cross-sectional view of another shift register unit 031 provided by an embodiment of the present disclosure.
  • the input circuit 0311, the output circuit 0312 and the plurality of drive signal lines recorded in the embodiment of the present disclosure may also include: a gate metal layer Gate and a gate insulation layer sequentially stacked in the direction away from the substrate. GI, source and drain metal layer SD and passivation layer PVX.
  • the gate metal layer Gate, the gate insulating layer GI, the source and drain metal layers SD and the passivation layer PVX may be the same as the gate metal layer Gate, the gate insulating layer GI, the source and drain metal layers SD and the passivation layer PVX included in the pixel 02.
  • One-to-one correspondence is located on the same layer.
  • the array substrate may further include: a second transfer part B2 located on the side of the passivation layer PVX away from the substrate.
  • the second transfer portion B2 can overlap with the source and drain metal layer SD through a plurality of third via holes K3 penetrating the passivation layer PVX, and can pass through a plurality of third via holes K3 penetrating the passivation layer PVX and the gate insulating layer GI.
  • the four vias K4 overlap the gate metal layer Gate to couple the input circuit 0311 and the drive signal line at the coupling node P0, and couple the input circuit 0311 and the output circuit 0312 at the pull-up node PU.
  • the parts of the shift register unit 031 can also be connected by the second transfer portion B2 located on the side of the source-drain metal layer SD away from the substrate 01, by respectively overlapping the source-drain metal layer SD and the gate located on different layers.
  • Metal layer Gate to achieve reliable coupling between the source-drain metal layer SD and the gate metal layer Gate located at different layers.
  • the third via hole K3 and the fourth via hole K4 are transfer holes. In this scenario, it can also be considered that a plurality of third vias K3 and a plurality of fourth vias K4 are connected in parallel.
  • the array substrate may only have via holes that penetrate the gate insulating layer GI and expose the gate metal layer Gate.
  • the source-drain metal layer SD may pass through the gate insulating layer GI and expose the gate metal layer.
  • the layer Gate directly overlaps the gate metal layer Gate.
  • the second transfer part B2 may also be located on the same layer as the common electrode line Com1. Since the common electrode line Com1 is located on the same layer as the electrode layer ITO, it can also be considered that the second transfer portion B2 is located on the same layer as the electrode layer ITO. Moreover, the orthographic projection of the source and drain metal layer SD on the substrate 01 can also be located within the orthographic projection of the gate metal layer Gate on the substrate 01 , and the orthographic projection of the plurality of third via holes K3 on the substrate 01 is consistent with the plurality of third via holes K3 The orthographic projections of the fourth via hole K4 on the substrate 01 do not overlap.
  • the number of the third vias K3 coupled through at the pull-up node PU is greater than the number of the third vias K3 coupled through at the coupling node P0.
  • the number of the fourth vias K4 coupled through at the pull-up node PU is greater than the number of the fourth vias K4 coupled through at the coupling node P0. That is, the number of vias opened between the parts at the coupling pull-up node PU is greater than the number of vias opened between the parts at the coupling other coupling nodes P0.
  • the voltage at the pull-up node PU is generally much greater than the voltage at other coupling nodes P0 except the pull-up node PU.
  • V voltage at other coupling nodes
  • the abscissa refers to time
  • the unit is seconds (s)
  • the ordinate refers to voltage
  • the potential is V.
  • the higher the voltage the higher the possibility of electrochemical corrosion when encountering water vapor.
  • the transfer reliability can be improved. Reduces the probability of the possibility of electrochemical corrosion occurring. Since the voltage at the other coupling node P0 is relatively small, there is no need to provide a large number of vias to achieve overlapping.
  • FIG. 13 is a structural layout of a shift register unit provided by an embodiment of the present disclosure.
  • FIG. 14 is a partial structural layout of the structure shown in FIG. 13 at the pull-up node PU and a coupling node P0.
  • the number of the third via holes K3 penetrated by the coupling at the pull-up node PU and the number of the fourth via holes K4 penetrated can be the same.
  • the number of the third via holes K3 penetrated by the coupling at the coupling node P0 and the number of the fourth via holes K4 penetrated by the coupling node P0 may be the same. In this way, for any node, it can be ensured that the resistance at the plurality of third via holes K1 and the resistance at the plurality of fourth via holes K4 are the same, further ensuring reliable switching.
  • the number of the third via hole K3 and the number of the fourth via hole K4 that are coupled through at the pull-up node PU may both be greater than or equal to 3, and may be less than or equal to 6.
  • the number of the third via holes K3 penetrated by the coupling at the coupling node P0 and the number of the fourth via holes K4 penetrated by the coupling may both be less than or equal to 2.
  • a plurality of third vias K3 are coupled through at the pull-up node PU, and the through-holes are coupled at the coupling node P0.
  • Each of the plurality of third via holes K3 can be divided into a plurality of third via hole groups K30 arranged sequentially along the second direction X2, and each third via hole group K30 includes a third via hole K3.
  • the plurality of fourth via holes K4 coupled and penetrated at the pull-up node PU, and the plurality of fourth via holes K4 coupled and penetrated at the coupling node P0 can be divided into a plurality of fourth via hole groups.
  • K40, each fourth via hole group K40 includes a fourth via hole K4.
  • the fourth via hole group K40 and the third via hole group K30 may be arranged sequentially along the first direction X1.
  • the plurality of third vias K3 that are passed through can be arranged sequentially along the second direction
  • the plurality of fourth via holes K4 connected thereto may be arranged in sequence along the second direction X2, and the third via hole K3 and the fourth via hole K4 may be arranged in sequence along the first direction X1.
  • the length of the transfer portion at the node in the first direction X1 can be less than or equal to the length in the second direction X2, that is, the length direction of the transfer portion at the node is parallel to the second direction X2.
  • the space in the circuit area A3 can be better utilized, so that the area occupied by the non-display area of the substrate 01 can be small enough, laying a good foundation for the design of narrow borders.
  • the third via hole K3 and the fourth via hole K4 can be along the first direction. X1 arrangement.
  • the number of the plurality of third vias K3 and the number of the plurality of fourth vias K4 coupled through at the pull-up node PU are both 3.
  • the plurality of third vias K3 coupled through at the pull-up node PU can be divided into three third via groups K30 arranged in sequence along the second direction X2
  • the plurality of fourth vias K4 coupled through at the pull-up node PU can be divided into three fourth via groups K40 arranged in sequence along the second direction X2.
  • the source-drain metal layer SD and the gate metal layer Gate are connected through three pairs of vias to form three pairs of holes in parallel.
  • the number of the plurality of third vias K3 and the number of the plurality of fourth vias K4 coupled through at the coupling node P0 are both 2.
  • the plurality of third vias K3 coupled through at the coupling node P0 can be divided into two third via groups K30 arranged in sequence along the second direction X2
  • the plurality of fourth vias K4 coupled through at the coupling node P0 can be divided into two fourth via groups K40 arranged in sequence along the second direction X2.
  • inventions of the present disclosure provide an array substrate.
  • the array substrate includes: a substrate with a display area, a wiring area and a circuit area adjacent in sequence, a pixel located in the display area, a common electrode line located in the wiring area and having a hole, a gate located in the wiring area and the circuit area Line leads, gate lines located in the wiring area and display area, and gate drive circuits located in the circuit area.
  • the gate line leads and the gate lines are located in different layers and are connected to each other.
  • the gate driving circuit is coupled to the pixel through the mutually connected gate line leads and gate lines, and provides gate driving signals to the pixels.
  • the common electrode lines are coupled to the pixels and provide common signals to the pixels.
  • the connecting part between the gate line lead and the gate line is located in the dug hole of the common electrode line, that is, it is located in the wiring area, making full use of the space, it can make other parts except the display area occupy a smaller area of the substrate. This can better facilitate the design of a narrow frame of the array substrate.
  • FIG. 15 is a flow chart of a method for preparing an array substrate provided by an embodiment of the present disclosure. This method can be used to prepare an array substrate as described in the above embodiments. As shown in Figure 15, the method may include:
  • Step 1501 Provide a substrate.
  • the provided substrate 01 may have a display area A1 and a wiring area A2 and a circuit area A3 located on at least one side of the display area A1 and arranged in sequence in a direction away from the display area A1 .
  • Step 1502 Form multiple pixels in the display area.
  • Step 1503 Form a common electrode line extending along the first direction in the wiring area.
  • the formed common electrode line Com1 may have a plurality of dug holes D arranged at intervals.
  • the common electrode line Com1 may be coupled to the plurality of pixels 02 and used to provide a common signal to the plurality of pixels 02 .
  • Step 1504 Form a plurality of gate lines extending in the second direction in the display area and wiring area.
  • the second direction X2 and the first direction X1 may intersect.
  • the second direction X2 and the first direction X1 shown in FIG. 1 are perpendicular to each other.
  • Step 1505 Form a plurality of gate line leads extending in the second direction in the circuit area and wiring area.
  • the plurality of gate line leads G2 formed are located on the side of the gate line G1 away from the substrate 01 and are located on the side of the common electrode line Com1 close to the substrate 01 .
  • Step 1506 Form a gate driving circuit in the circuit area.
  • the formed gate driving circuit 03 can be coupled to a plurality of gate line leads G2, and the plurality of gate line leads G2 can be connected to a plurality of gate lines G1.
  • the plurality of gate lines G1 can also It can then be coupled to multiple pixels 02 to achieve reliable connection between the gate driving circuit 03 and the pixels 02 .
  • the gate driving circuit 03 may be used to provide gate driving signals to the plurality of pixels 02 through the plurality of gate line leads G2 and the plurality of gate lines G1.
  • the transfer part between the gate line lead G2 and the gate line G1 can be located in the digging hole D. In this way, the purpose of making full use of the space on the substrate 01 can be achieved, which is beneficial to the narrow frame of the array substrate. design.
  • the above-mentioned preparation method provided in the embodiment of the present disclosure should have the same characteristics and advantages as the array substrate provided in the embodiment of the present disclosure, so the characteristics and advantages of the above-mentioned preparation method provided in the embodiment of the present disclosure can refer to the characteristics and advantages of the array substrate described above, and will not be repeated here.
  • FIG. 16 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG. 16 , the display device includes: a power supply component J1 and an array substrate 00 as shown in any of the above figures. The power supply component J1 is coupled to the array substrate 00 and used to power the array substrate 00 .
  • the display device may include: a vehicle-mounted display device, an LCD display device, a mobile phone, a tablet computer, a television, a monitor, or any other product or component with a display function.

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Abstract

提供了一种阵列基板及显示装置，属于显示技术领域。该阵列基板包括：具有依次邻接的显示区、走线区和电路区的衬底，位于显示区的像素，位于走线区且具有挖孔的公共电极线，位于走线区和电路区的栅线引线，位于走线区和显示区的栅线，以及位于电路区的栅极驱动电路。其中，栅线引线与栅线位于不同层且相互转接，栅极驱动电路通过相互转接的栅线引线和栅线与像素耦接，并为像素提供栅极驱动信号。公共电极线与像素耦接，并为像素提供公共信号。因栅线引线与栅线的转接部分位于公共电极线具有的挖孔内，即位于走线区，充分利用了空间，故可以使得除显示区外的其他部分占用衬底的面积较小，进而能够更好的利于阵列基板的窄边框的设计。

Description

阵列基板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板及显示装置。
背景技术
薄膜晶体管液晶显示(thin film transistor-liquid crystal display，TFT-LCD)装置是显示领域中常见的显示装置之一。
相关技术中，TFT-LCD显示装置中的阵列基板包括：具有显示区和非显示区的衬底，位于显示区的TFT和电极，位于非显示区且沿远离显示区的方向依次排布的公共电极线和栅极驱动电路，以及位于显示区和非显示区且位于不同层的栅线引线和栅线。其中，公共电极线与电极耦接，并为电极提供驱动信号。栅极驱动电路通过栅线引线和栅线与TFT耦接，并为TFT提供栅极驱动信号。并且，因栅线引线和栅线位于不同层，故栅线引线与栅线需要通过转接孔转接。
但是，受转接孔和公共电极线的布局影响，目前的阵列基板中，非显示区所需占用衬底的面积较大，不利于阵列基板的窄边框的设计。
发明内容
提供了一种阵列基板及显示装置，所述技术方案如下：
一方面，提供了一种阵列基板，所述阵列基板包括：
衬底，具有显示区和位于所述显示区至少一侧，且沿远离所述显示区的方向依次排布的走线区和电路区；
多个像素，位于所述显示区；
沿第一方向延伸的公共电极线，位于所述走线区，所述公共电极线具有间隔排布的多个挖孔，所述公共电极线与所述多个像素耦接；
沿第二方向延伸的多条栅线，位于所述显示区和所述走线区，所述第二方向与所述第一方向相交；
沿所述第二方向延伸的多条栅线引线，位于所述电路区和所述走线区，位于所述栅线远离所述衬底的一侧，且位于所述公共电极线靠近所述衬底的一侧；
栅极驱动电路，位于所述电路区，所述栅极驱动电路与所述多条栅线引线 耦接，所述多条栅线引线与所述多条栅线转接，且转接部分位于所述挖孔内，所述多条栅线还与所述多个像素耦接。
可选的，每个挖孔的边缘均与所述公共电极线的边缘之间存在间距，且距所述公共电极线在所述第二方向上的任一边缘的间距相等；所述多个挖孔沿所述第一方向间隔排布。
可选的，所述栅极驱动电路包括：沿所述第一方向依次排布且级联的多个移位寄存器单元，所述多个像素阵列排布；
其中，所述多个移位寄存器单元与所述多条栅线引线一一对应耦接，所述多条栅线引线与所述多条栅线一一对应转接，且转接部分一一对应的位于所述多个挖孔内，所述多条栅线与多行像素一一对应耦接。
可选的，一一对应的每条所述栅线引线、每个所述挖孔和每条所述栅线在所述第二方向上，沿同一条水平线依次排布。
可选的，所述阵列基板还包括：
位于所述栅线与所述栅线引线之间的第一绝缘层；
位于所述栅线引线远离所述衬底一侧的第二绝缘层；
位于所述第二绝缘层远离所述衬底一侧的第一转接部；
以及，贯穿所述第二绝缘层的多个第一过孔，且贯穿所述第二绝缘层和所述第一绝缘层的多个第二过孔；
其中，所述栅线引线在所述衬底上的正投影位于所述栅线在所述衬底上的正投影内，所述多个第一过孔在所述衬底上的正投影与所述多个第二过孔在所述衬底上的正投影不交叠；
并且，所述第一转接部通过所述多个第一过孔与所述栅线引线搭接，并通过所述多个第二过孔与所述栅线搭接，以将所述栅线与所述栅线引线转接。
可选的，所述多个第一过孔的数量与所述多个第二过孔的数量相同。
可选的，所述多个第一过孔的数量与所述多个第二过孔的数量均大于等于4且小于等于8。
可选的，所述多个第一过孔被划分为沿所述第一方向依次排布的多个第一过孔组，每个第一过孔组包括沿所述第二方向依次排布的多个第一过孔，且每个第一过孔组包括的第一过孔的数量小于等于所述多个第一过孔组的数量；
所述多个第二过孔被划分为沿所述第一方向依次排布的多个第二过孔组，每个第二过孔组包括沿所述第二方向依次排布的多个第二过孔，且每个第二过 孔组包括的第二过孔的数量小于等于所述多个第二过孔组的数量。
可选的，所述多个第一过孔的数量与所述多个第二过孔的数量均为4；
所述多个第一过孔被划分为沿所述第一方向依次排布的两个第一过孔组，且每个第一过孔组包括沿所述第二方向依次排布的两个第一过孔；
所述多个第二过孔被划分为沿所述第一方向依次排布的两个第二过孔组，且每个第二过孔组包括沿所述第二方向依次排布的两个第二过孔。
可选的，所述第一转接部与所述公共电极线位于同层。
可选的，所述阵列基板还包括：位于所述走线区的公共电极引线，所述公共电极引线包括：位于所述衬底与所述公共电极线之间，且沿远离所述衬底的方向依次层叠的第一电极线和第二电极线；
所述阵列基板还包括：位于所述第一电极线与所述第二电极线之间的第三绝缘层，以及位于第二电极线与所述公共电极线之间的第四绝缘层；
其中，所述公共电极线通过贯穿所述第四绝缘层的过孔与所述第二电极线搭接，并通过贯穿所述第三绝缘层和所述第四绝缘层的过孔与所述第一电极线搭接，以用于接收来自所述第一电极线和所述第二电极线提供的公共信号。
可选的，所述第一电极线包括间隔排布的多个第一电极块，所述第二电极线包括间隔排布的多个第二电极块。
可选的，所述像素包括：沿远离所述衬底的方向依次层叠的栅金属层、栅绝缘层、源漏金属层、钝化层和电极层；
其中，所述第一电极线与所述栅线位于同层，且均与所述栅金属层位于同层；
所述第二电极线和所述栅线引线位于同层，且均与所述源漏金属层位于同层；
所述第一绝缘层和所述第三绝缘层位于同层，且均与所述栅绝缘层位于同层；
所述第二绝缘层和所述第四绝缘层位于同层，且均与所述钝化层位于同层；
所述公共电极线与所述电极层位于同层。
可选的，所述栅极驱动电路中每个移位寄存器单元包括：输入电路和输出电路；
所述输入电路分别与多条驱动信号线和上拉节点耦接，并用于响应于所述多条驱动信号线提供的驱动信号，为所述上拉节点充电；
所述输出电路分别与所述上拉节点和所述栅线引线耦接，并用于基于所述上拉节点的电位，向所述栅线引线传输栅极驱动信号。
可选的，所述输入电路、所述输出电路和所述多条驱动信号线包括：沿远离所述衬底的方向依次层叠的栅金属层、栅绝缘层、源漏金属层和钝化层；
所述阵列基板还包括：位于所述钝化层远离所述衬底一侧的第二转接部，所述第二转接部通过贯穿所述钝化层的多个第三过孔与所述源漏金属层搭接，并通过贯穿所述钝化层和所述栅绝缘层的多个第四过孔与所述栅金属层搭接，以将所述输入电路与所述驱动信号线在耦接节点处耦接，并将所述输入电路和所述输出电路在所述上拉节点处耦接；
其中，所述源漏金属层在所述衬底上的正投影位于所述栅金属层在所述衬底上的正投影内，所述多个第三过孔在所述衬底上的正投影与所述多个第四过孔在所述衬底上的正投影不交叠；
并且，在所述上拉节点处耦接所贯穿的第三过孔的数量，大于在所述耦接节点处耦接所贯穿的第三过孔的数量；以及，在所述上拉节点处耦接所贯穿的第四过孔的数量，大于在所述耦接节点处耦接所贯穿的第四过孔的数量。
可选的，在所述上拉节点处耦接所贯穿的第三过孔的数量与所贯穿的第四过孔的数量相同；
且，在所述耦接节点处耦接所贯穿的第三过孔的数量与所贯穿的第四过孔的数量相同。
可选的，在所述上拉节点处耦接所贯穿的第三过孔的数量和第四过孔的数量均大于等于3，且小于等于6；在所述耦接节点处耦接所贯穿的第三过孔的数量与所贯穿的第四过孔的数量均小于等于2。
可选的，在所述上拉节点处耦接所贯穿的多个第三过孔，以及在所述耦接节点处耦接所贯穿的多个第三过孔均被划分为沿所述第二方向依次排布的多个第三过孔组，每个第三过孔组包括一个第三过孔；
在所述上拉节点处耦接所贯穿的多个第四过孔，以及在所述耦接节点处耦接所贯穿的多个第四过孔均被划分为沿所述第二方向依次排布的多个第四过孔组，每个第四过孔组包括一个第四过孔，且所述第四过孔组与所述第三过孔组沿所述第一方向依次排布。
可选的，在所述上拉节点处耦接所贯穿的多个第三过孔的数量与多个第四过孔的数量均为3；在所述耦接节点处耦接所贯穿的多个第三过孔的数量与多个 第四过孔的数量均为2；
在所述上拉节点处耦接所贯穿的多个第三过孔被划分为沿所述第二方向依次排布的三个第三过孔组，在所述上拉节点处耦接所贯穿的多个第四过孔包括沿所述第二方向依次排布的三个第四过孔组；
在所述耦接节点处耦接所贯穿的多个第三过孔被划分为沿所述第二方向依次排布的两个第三过孔组，在所述耦接节点处耦接所贯穿的多个第四过孔包括沿所述第二方向依次排布的两个第四过孔组。
可选的，所述第二转接部与所述公共电极线位于同层。
可选的，所述第一方向与所述第二方向垂直。
另一方面，提供了一种显示装置，所述显示装置包括：供电组件，以及如上述方面所述的阵列基板；
其中，所述供电组件与所述阵列基板耦接，并用于为所述阵列基板供电。
可选的，所述显示装置包括：车载显示装置。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种阵列基板的结构示意图；
图2是图1所示结构在a1-a2方向上的一种截面示意图；
图3是本公开实施例提供的另一种阵列基板的结构示意图；
图4是图1所示结构在a1-a2方向上的另一种截面示意图；
图5是图4所示结构部分区域的俯视图；
图6是本公开实施例提供的又一种阵列基板的结构示意图；
图7是图6所示结构在b1-b2方向上的一种截面示意图；
图8是图6所示结构在c1-c2方向上的一种截面示意图；
图9是本公开实施例提供的一种显示区内像素的截面示意图；
图10是本公开实施例提供的一种移位寄存器单元的结构示意图；
图11是本公开实施例提供的一种移位寄存器单元的截面示意图；
图12是本公开实施例提供的一种模拟电压示意图；
图13是本公开实施例提供的一种移位寄存器单元的结构版图；
图14是图13所示结构不同节点的俯视图；
图15是本公开实施例提供的一种阵列基板的制备方法流程图；
图16是本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
因阵列基板的边框较大会降低阵列基板的整体显示效果，且整个阵列基板的视觉效果也较差，故随着显示技术的发展，可以通过压缩阵列基板的边框(即，设计窄边框的阵列基板)来改善显示效果，满足用户对显示效果的需求。其中，采用阵列基板行驱动(gate drive on array，GOA)技术将栅极驱动电路集成于衬底上即属于一种实现窄边框的方式。栅极驱动电路又称为GOA电路。但是，如背景技术记载，受GOA电路与TFT耦接所用栅线引线和栅线的转接孔(即，转接部分)和公共电极线的布局影响，依然无法可靠的实现窄边框设计。
本公开实施例提供了一种新的阵列基板，该阵列基板中对转接部分和公共电极线的布局进行了合理的空间优化，能够达到极致压缩非显示区的面积的目的，更利于阵列基板的窄边框设计，满足用户对窄边框的需求。图1是本公开实施例提供的一种阵列基板的结构示意图。如图1所示，该阵列基板包括：
衬底01。该衬底01具有显示区A1和位于显示区A1至少一侧，且沿远离显示区A1的方向依次排布的走线区A2和电路区A3。即，在显示区A1的各侧中的至少一侧，电路区A3和走线区A2相邻且接触，走线区A2和显示区A1的该至少一侧相邻且接触。相应的可知，走线区A2位于电路区A3与显示区A1之间。在本公开实施例中，走线区A2和电路区A3也可以称为非显示区。
例如，参考图1，其示出的衬底01具有的显示区A1呈矩形，具有四侧。该衬底01具有位于该呈矩形的显示区A1的左侧，且沿远离显示区A1的方向依次排布的走线区A2和电路区A3。当然，在一些其他实施例中，结合图1，对于具有呈矩形的显示区A1的衬底01而言，其具有的走线区A2和电路区A3也可以位于显示区A1的右侧、上侧和/或下侧。以及，在一些其他实施例中，显示区A1也可以呈其他形状，如圆形、椭圆形、梯形或三角形。
需要说明的是，图1仅是示意性示出显示区A1、走线区A2和电路区A3 中，各个区的面积。在实际产品中，显示区A1的面积一般较大，而走线区A2的面积和电路区A3的面积可以均较小，以为阵列基板的窄边框设计奠定基础，且同时确保显示效果较好。此处，各个区的面积均是指占用衬底01的面积。
继续参考图1，本公开实施例记载的阵列基板还包括：
多个像素02，该多个像素02位于显示区A1。
沿第一方向X1延伸的公共电极线Com1，该公共电极线Com1位于走线区A2。并且，该公共电极线Com1与多个像素02耦接(即，电连接)，并用于为多个像素02提供公共信号。如，像素02可以包括公共电极，公共电极线Com1可以与公共电极耦接，并用于为公共电极提供公共信号。需要说明的是，图1中未示出公共电极线Com1与像素02的耦接。此外，本公开实施例记载的公共电极线Com1可以具有间隔排布的多个挖孔D，挖孔D贯穿公共电极线Com1。
沿第二方向X2延伸的多条栅线G1，该多条栅线G1位于显示区A1和走线区A2，即，每条栅线G1可以部分位于显示区A1，部分位于走线区A2。且该第二方向X2与第一方向X1可以相交，即，不平行。
沿第二方向X2延伸的多条栅线引线G2，该多条栅线引线G2位于电路区A3和走线区A2。即，每条栅线引线G2可以部分位于电路区A3，部分位于走线区A2。并且，参考图2示出的图1在a1-a2方向上的截面图可知，多条栅线引线G2还位于栅线G1远离衬底01的一侧，且位于公共电极线Com1靠近衬底01的一侧。即，在本公开实施例中，栅线G1、栅线引线G2和公共电极线Com1分别位于不同层，且沿远离衬底01的方向依次层叠。当然，在一些其他实施例中，栅线G1、栅线引线G2和公共电极线Com1的位置关系也可以变更。如，栅线G1位于栅线引线G2和公共电极线Com1之间。
栅极驱动电路03，该栅极驱动电路03位于电路区A3。并且，该栅极驱动电路03与多条栅线引线G2耦接，多条栅线引线G2与多条栅线G1转接，多条栅线G1还与多个像素02耦接。即，栅极驱动电路03可以通过相互转接的栅线引线G2和栅线G1与像素02耦接。以及，该栅极驱动电路03用于通过多条栅线引线G2和多条栅线G1向多个像素02提供栅极驱动信号。
如，像素02可以包括TFT，栅极驱动电路03可以通过相互转接的栅线引线G2和栅线G1与TFT耦接，以为TFT提供栅极驱动信号，控制TFT开启或关闭。再结合上述关于公共电极的描述，像素02还可以包括像素电极，以及位于像素电极和公共电极之间的液晶分子。TFT开启后，可以为像素电极充电， 液晶分子可以在像素电极上的电压和公共电极上的电压的压差作用下发生偏转，从而像素02被点亮。包括该像素02的阵列基板即为LCD基板。
此外，结合图1和图2可以看出，在本公开实施例中，位于不同层的栅线引线G2与栅线G1的转接部分位于挖孔D内。即，位于公共电极线Com1所限定的区域内，也可以认为是位于走线区A2内部，且转接部分在衬底01上的正投影与具有挖孔D公共电极线Com1在衬底01上的正投影重叠。如此，可以达到充分利用走线区A2空间的目的，使得包括走线区A2和电路区A3的非显示区占用衬底01的面积可以较小，从而利于阵列基板的窄边框设计。
相关技术中，栅线引线G2与栅线G1的转接部分一般位于走线区A2与电路区A3之间，即位于走线区A2远离显示区A1的一侧，但不位于走线区A2。如此，不仅没有较好的充分利用衬底01上的空间，无法较好的实现窄边框设计，而且因转接部分距水汽可进入的衬底01的边界较近，故导致水汽易侵入有效线路部分，造成信赖性不良问题，该信赖性不良在温度较高湿度较大的场景下更为明显。这与一些对信赖性要求严格的产品(如，车载类显示产品)存在博弈。
考虑到这些问题，相关技术还将栅线引线G2与栅线G1的转接部分调整至走线区A2与显示区A1之间，即位于走线区A2靠近显示区A1的一侧，但不位于走线区A2。但是，因转接部分靠近显示区A1，故导致转接部分处的电场不可避免的影响点亮显示区A1中像素02时所需的驱动电场，如影响驱动液晶分子偏转的电场，使得驱动液晶分子偏转的电场偏离正常电压，进而导致靠近走线区A2，即显示区A1边缘的像素02发光异常，如出现漏光现象，造成阵列基板的显示效果较差，产品良率较低。如，假设多个像素02包括红色像素、绿色像素和蓝色像素，靠近走线区A2的像素02为红色像素，则会导致红色像素的发光亮度大于绿色像素的发光亮度和蓝色像素的发光亮度，红色像素发生漏光。
而在本公开实施例中，通过设置转接部分位于走线区A2内，且位于公共电极线Com1的挖孔内，不仅可以如上述实施例记载，较好的利于阵列基板的窄边框设计；而且可以避免外界水汽侵入有效线路部分，提高产品信赖性；以及还可以避免转接部分的电场影响显示区A1内的电场，改善漏光问题，改善显示效果，提高产品良率。即，通过合理布局公共电极线Com1，以及栅线G1与栅线引线G2的转接部分，可以在保证车载产品的高信赖性要求前提下使得边框更窄，且同时规避阵列基板边缘的漏光现象。本公开实施例记载的阵列基板能够较好的适用于窄边框类显示产品。
综上所述，本公开实施例提供了一种阵列基板。该阵列基板包括：具有依次邻接的显示区、走线区和电路区的衬底，位于显示区的像素，位于走线区且具有挖孔的公共电极线，位于走线区和电路区的栅线引线，位于走线区和显示区的栅线，以及位于电路区的栅极驱动电路。其中，栅线引线与栅线位于不同层且相互转接，栅极驱动电路通过相互转接的栅线引线和栅线与像素耦接，并为像素提供栅极驱动信号。公共电极线与像素耦接，并为像素提供公共信号。因栅线引线与栅线的转接部分位于公共电极线具有的挖孔内，即位于走线区，充分利用了空间，故可以使得除显示区外的其他部分占用衬底的面积较小，进而能够更好的利于阵列基板的窄边框的设计。
可选的，继续结合图1可以看出，本公开实施例中记载的第一方向X1与第二方向X2可以垂直。
可选的，继续结合图1，在本公开实施例中，多个挖孔D可以沿第一方向X1间隔排布。并且，公共电极线Com1具有的每个挖孔D的边缘均与公共电极线Com1的边缘之间存在间距，且距公共电极线Com1在第二方向X2上的任一边缘的间距相等。即，每个挖孔D均被公共电极线Com1除挖孔D外的其余部分所包围。并且，在公共电极线Com1和挖孔D均呈图1所示矩形基础上，在第一方向X1上，每个挖孔D的中轴线均与公共电极线Com1的中轴线所重叠，位于公共电极线Com1的中心处。如此设置，可以使得布局更为规则，且可以更好的提高产品信赖性，同时改善阵列基板的显示效果，提高产品良率。
可选的，在图1基础上，参考图3示出的另一种阵列基板的结构示意图可知，本公开实施例记载的栅极驱动电路03可以包括：沿第一方向X1依次排布且级联的多个移位寄存器单元031。移位寄存器单元031还可以称为GOA单元。
本公开实施例记载的多个像素02可以阵列排布。即，沿行方向和列方向排布，阵列基板包括多行多列个像素。可选的，结合图1和图3，第一方向X1与列方向可以为同一个方向，第二方向X2与行方向可以为同一个方向。
其中，多个移位寄存器单元031与多条栅线引线G2可以一一对应耦接，多条栅线引线G2与多条栅线G1可以一一对应转接，且转接部分可以一一对应的位于多个挖孔D内，多条栅线G1与多行像素02可以一一对应耦接。即，每个移位寄存器单元031可以与一条栅线引线G2耦接，各个移位寄存器单元031与不同的栅线引线G2耦接。每条栅线引线G2与一条栅线G1转接，各条栅线引 线G2与不同的栅线G1转接。每条栅线G1与一行像素02耦接，各条栅线G1与不同行像素02耦接。每个移位寄存器单元031用于通过一条栅线引线G2和一条栅线G1向一行像素02提供栅极驱动信号，从而可以实现逐行扫描。
当然，在一些其他实施例中，每个移位寄存器单元031还可以通过栅线引线G2和栅线G1与两行或两行以上像素02耦接。
可选的，继续参考图3可以看出，在本公开实施例中，一一对应的每条栅线引线G2、每个挖孔D和每条栅线G1在第二方向X2上，可以沿同一条水平线依次排布。即，对于每条栅线栅线G2而言，该栅线引线G2，与该栅线引线G2对应的挖孔D，以及与该栅线引线G2对应的栅线G1位于同一条沿第二方向X2延伸的水平线上。如此，可以进一步的确保布局更为规则，从而简化布线。
可选的，结合图2，以及图4示出的另一种阵列基板在a1-a2方向上的截面图可以看出，本公开实施例记载的阵列基板还可以包括：
位于栅线G1与栅线引线G2之间的第一绝缘层J1。
位于栅线引线G2远离衬底01一侧的第二绝缘层J2。
位于第二绝缘层J2远离衬底01一侧的第一转接部B1。
以及，贯穿第二绝缘层J2的多个第一过孔K1，且贯穿第二绝缘层J2和第一绝缘层J1的多个第二过孔K2。相应的可知，多个第一过孔K1可以暴露栅线引线G2，多个第二过孔K2可以暴露栅线G1。需要说明的是，图4仅示意性示出两个第二过孔K2和一个第一过孔K1。
其中，继续参考图4可以看出，栅线引线G2在衬底01上的正投影可以位于栅线G1在衬底01上的正投影内，多个第一过孔K1在衬底01上的正投影与多个第二过孔K2在衬底01上的正投影可以不交叠。并且，第一转接部B1可以通过多个第一过孔K1与栅线引线G2搭接，可以通过多个第二过孔K2与栅线G1搭接，以将栅线G1与栅线引线G2转接。即，栅线G1与栅线引线G2可以通过第一转接部B1间接转接，第一过孔K1和第二过孔K2可以认为是栅线G1与栅线引线G2的转接孔。该场景下，可以认为是多个第一过孔K1与多个第二过孔K2并联。通过设置并联的多个第一过孔K1和多个第二过孔K2，一方面可以减小转接孔的电阻，另一方面可以提高转接可靠性。
当然，在一些其他实施例中，阵列基板可以仅具有贯穿第一绝缘层J1且暴露栅线G1的过孔，在此基础上，栅线引线G2可以通过该贯穿第一绝缘层J1且暴露栅线G1与栅线直接搭接。
可选的，结合图5示出的一种阵列基板的局部示意图可知，在本公开实施例中，多个第一过孔K1的数量与多个第二过孔K2的数量可以相同。通过设置第一过孔K1与第二过孔K2的数量相同，可以确保多个第一过孔K1处的电阻和多个第二过孔K2处的电阻相同，进一步确保可靠转接，以及转接稳定性。
可选的，在本公开实施例中，多个第一过孔K1的数量与多个第二过孔K2的数量可以均大于等于4且小于等于8。
可选的，结合图5，在本公开实施例中，多个第一过孔K1可以被划分为沿第一方向X1依次排布的多个第一过孔组K10，每个第一过孔组K10可以包括沿第二方向X2依次排布的多个第一过孔K1，且每个第一过孔组K10包括的第一过孔K1的数量可以小于等于多个第一过孔组K10的数量。且，多个第二过孔K2可以被划分为沿第一方向X1依次排布的多个第二过孔组K20，每个第二过孔组K20可以包括沿第二方向X2依次排布的多个第二过孔K2，且每个第二过孔组K20包括的第二过孔K2的数量可以小于等于多个第二过孔组K20的数量。
如此，可以使得栅线引线G2与栅线G1的转接部分在第一方向X1上的长度大于等于在第二方向X2上的长度，即，栅线引线G2与栅线G1的转接部分的长度方向平行于第一方向X1。进而，可以更进一步的较好利用走线区A2内的空间，使得非显示区占用衬底01的面积能够足够小，为窄边框的设计奠定良好的基础。
例如，参考图5，其示出的多个第一过孔K1的数量与多个第二过孔K2的数量可以均为4。以及，多个第一过孔K1可以被划分为沿第一方向X1依次排布的两个第一过孔组K10，且每个第一过孔组K10可以包括第二方向X2依次排布的两个第一过孔K1。多个第二过孔K2可以被划分为沿第一方向X1依次排布的两个第二过孔组K20，且每个第二过孔组K20可以包括第二方向X2依次排布的两个第二过孔K2。此时，参考图5可以看出，可以认为栅线G1和栅线引线G2通过4对过孔转接，形成了4对孔的并联。
可选的，在本公开实施例中，参考图4还可以看出，第一转接部B1与公共电极线Com1可以位于同层。
需要说明的是，位于同层可以是指采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板(mask)通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。 即，位于“同层”的多个元件、部件、结构和/或部分由相同的材料构成，并通过同一次构图工艺形成。如此，可以节省制造工艺和制造成本，并且可以加快制造效率。
可选的，在图1至图5基础上，图6示出了一种阵列基板的结构版图。参考图6也可以看出，位于走线区的公共电极线Com1具有挖孔D，位于电路区A3和走线区A2的栅线引线G2与位于走线区A2和显示区A1的栅线G1在挖孔D内通过转接孔转接。图4可以认为是图6所示结构版图在a3-a4方向的截面图。
可选的，图7示出了图6所示结构版图在b1-b2方向的截面图。图8示出了图6所示结构版图在c1-c2方向的截面图。结合图4、图7和图8可以看出，本公开实施例记载的阵列基板还可以包括：位于走线区A2的公共电极引线Com2。
其中，公共电极引线Com2可以包括：位于衬底01与公共电极线Com1之间，且沿远离衬底01的方向依次层叠的第一电极线Com21和第二电极线Com22。在此基础上，阵列基板还可以包括：位于第一电极线Com21与第二电极线Com22之间的第三绝缘层J3，以及位于第二电极线Com22与公共电极线Com1之间的第四绝缘层J4。
其中，公共电极线Com1可以通过贯穿第四绝缘层J4的过孔(图中未标识)与第二电极线Com22搭接，并可以通过贯穿第三绝缘层J3和第四绝缘层J4的过孔(图中未标识)与第一电极线Com21搭接，以用于接收来自第一电极线Com21和第二电极线Com22提供的公共信号。即，公共信号的源头可以由外部集成电路(integrated circuit，IC)提供给公共电极引线Com2，然后再由公共电极引线Com2传导至位于走线区A2的公共电极线Com1上，最后再由公共电极线Com1传导至位于显示区A1的公共电极上。
可选的，参考图7和图8还可以看出，本公开实施例第一电极线Com21和第二电极线Com22均可以包括间隔排布的多个电极块。即，如图6和图7所示，第一电极线Com21和第二电极线Com22均非整片设置于衬底01的一侧，而是包括多个间隔的部分，公共电极线Com1与间隔的各部分均搭接。该设计也可以认为是对公共电极引线Com2进行网格化设计。
通过网格化设计公共电极引线Com2可以减少衬底01上大块实心金属的设置，防止在制备过程中因大块金属发热面积较大，而导致其他膜层(如，有源层)被烧损，确保产品良率较好。在对公共电极引线Com2进行网格化设计的 基础上，会导致一定的空间浪费，若结合相关技术的布局方式，则与窄边框设计的要求相悖。而在本公开实施例中，因调整了转接部分和公共电极线Com1的布局，故可以规避对公共电极引线Com2进行网格化设计带来的空间浪费问题。
可选的，图9示出了一种显示区内像素的截面图。如图9所示，本公开实施例记载的像素02可以包括：沿远离衬底01的方向依次层叠的栅金属层Gate、栅绝缘(gate insulator，GI)层GI、源漏(source&drain，SD)金属层SD、钝化(passivation)层PVX和电极层ITO。
其中，结合图4、图7和图8可以看出，本公开实施例记载的第一电极线Com21可以与栅线G1位于同层，且均可以与栅金属层Gate位于同层。第二电极线Com22可以和栅线引线G2位于同层，且均可以与源漏金属层SD位于同层。第一绝缘层J1可以和第三绝缘层J3位于同层，且均可以与栅绝缘层GI位于同层。第二绝缘层J2可以和第四绝缘层J4位于同层，且均可以与钝化层PVX位于同层。公共电极线Com1可以与电极层ITO位于同层。如此，可以进一步节省制造工艺和制造成本，并且可以进一步加快制造效率。
即，在走线区A2和电路区A3，阵列基板均可以包括沿远离衬底01的方向依次层叠的栅金属层Gate、栅绝缘层GI、源漏金属层SD、钝化层PVX和电极层ITO。并且，一方面，栅线引线G2可以采用源漏金属层SD形成，栅线G1可以采用栅金属层Gate形成，然后可以由电极层ITO分别搭接源漏金属层SD和栅金属层Gate，实现源漏金属层SD和栅金属层Gate之间的导通，即实现栅线引线G2与栅线G1之间的可靠耦接。另一方面，公共电极引线Com2可以由源漏金属层SD和栅金属层Gate形成，公共电极线Com1可以由电极层ITO形成，然后可以由IC将公共信号经源漏金属层SD和栅金属层Gate传导至位于走线区A2的电极层ITO，最后再由位于走线区A2的电极层ITO传导至位于显示区A1的像素02包括的电极层ITO。
可选的，参考图9还可以看出，本公开实施例记载的像素02还可以包括：位于栅绝缘层GI与源漏金属层SD之间的有源(active)层Ac1和另一导电层ITO。为与上述实施例记载的导电层ITO区分，本公开实施例图9中将与公共电极线Com1位于同层的导电层ITO标识为“ITO(2)”，以及将该另一导电层ITO标识为“ITO(1)”。
其中，电极层ITO(1)与电极层ITO(2)中，一个电极层可以为像素电极， 另一个电极层可以为公共电极。本公开实施例以电极层ITO(2)为公共电极，电极层ITO(1)为像素电极为例进行说明。有源层Ac1可以与源漏金属层SD搭接，且有源层Ac1在衬底01上的正投影与电极层ITO(2)在衬底01上的正投影不交叠。
对于图9所示结构而言，可以采用6mask工艺制备得到。并且，贯穿钝化层PVX和栅绝缘层GI的过孔，与，贯穿钝化层PVX的过孔可以通过一次mask工艺打孔得到，以简化制造工艺，节省制造成本，加快制造效率。6mask工艺即是指采用mask分6次步骤依次制备得到。
其中，6次步骤分别包括：(1)：采用mask在衬底01上形成栅金属层Gate。之后，可以采用沉积工艺在栅金属层Gate远离衬底01的一侧形成栅绝缘层GI。(2)采用mask在栅绝缘层GI远离衬底01的一侧形成有源层Ac1。(3)采用mask在栅绝缘层GI远离衬底01的一侧形成电极层ITO(1)。(4)采用mask在有源层Ac1远离衬底01的一侧形成源漏金属层SD。(5)采用mask在源漏金属层SD远离衬底01的一侧形成钝化层PVX。(6)采用mask在钝化层PVX远离衬底01的一侧形成电极层ITO(2)。该工艺制备得到的像素02中的TFT可以称为底栅型TFT。当然，在一些其他实施例中，TFT也可以为顶栅型TFT，此时，栅金属层Gate可以位于有源层Ac1远离衬底01的一侧。
可选的，栅金属层Gate的材料可以包括：金属材料或者合金材料。，金属钼(Mo)、铝(Al)和钛(Ti)等。栅绝缘层GI和钝化层PVX的材料可以包括：无机材料。如，氧化硅(SiOx)或氮化硅(SiNx)。有源层Ac1的材料可以包括：多晶硅材料。源漏金属层SD的材料可以包括：金属材料或者合金材料。如，源漏金属层SD的材料可以包括Mo、铝(Al)和钛(Ti)等。电极层ITO(1)和ITO(2)的材料可以包括：氧化铟锡(indium tin oxide，ITO)，为透明材料，可以确保透光率较好。当然，在一些其他实施例中，电极层ITO(1)和ITO(2)的材料也可以包括其他类型的透明材料，如氧化铟锌或氧化锌。衬底01可以为单层结构或双层结构，且该衬底01可以为玻璃制成的刚性基板，也可以为采用聚酰亚胺柔性材料制成的柔性基板。
再结合图1和图3，在本公开实施例中，阵列基板还可以包括：位于显示区A1的多条数据线。多条数据线可以与多列像素02一一对应耦接，以为像素02提供数据信号。其中，数据线可以与源漏金属层SD位于同层。
可选的，图10是本公开实施例提供的一种移位寄存器单元031的结构示意 图。如图10所示，栅极驱动电路03中每个移位寄存器单元031可以包括：输入电路0311和输出电路0312。
其中，输入电路0311分别与多条驱动信号线(图中未示出)和上拉节点PU耦接，并可以用于响应于多条驱动信号线提供的驱动信号，为上拉节点PU充电。
输出电路0312可以分别与上拉节点PU和栅线引线G2耦接，并可以用于基于上拉节点PU的电位，向栅线引线G2传输栅极驱动信号。在此基础上可知，本公开实施例记载的栅线引线G2其实就是移位寄存器单元031的输出端。
可选的，驱动信号线可以包括：时钟信号线、电源线和/或复位信号线。且，输出电路0312一般也可以与时钟信号线耦接，以基于上拉节点PU的电位，向栅线G2传输来自时钟信号线的时钟信号，该时钟信号即可作为栅极驱动信号。
可选的，图11是本公开实施例提供的另一种移位寄存器单元031的部分截面图。结合图9和图11可以看出，本公开实施例记载的输入电路0311、输出电路0312和多条驱动信号线也可以包括：沿远离衬底的方向依次层叠的栅金属层Gate、栅绝缘层GI、源漏金属层SD和钝化层PVX。此处，栅金属层Gate、栅绝缘层GI、源漏金属层SD和钝化层PVX，与像素02包括的栅金属层Gate、栅绝缘层GI、源漏金属层SD和钝化层PVX可以一一对应的分别位于同层。
参考图11可以看出，在本公开实施例中，阵列基板还可以包括：位于钝化层PVX远离衬底一侧的第二转接部B2。
其中，该第二转接部B2可以通过贯穿钝化层PVX的多个第三过孔K3与源漏金属层SD搭接，并可以通过贯穿钝化层PVX和栅绝缘层GI的多个第四过孔K4与栅金属层Gate搭接，以将输入电路0311与驱动信号线在耦接节点P0处耦接，并将输入电路0311和输出电路0312在上拉节点PU处耦接。
即，移位寄存器单元031中各部分之间也可以由位于源漏金属层SD远离衬底01一侧的第二转接部B2，通过分别搭接位于不同层的源漏金属层SD和栅金属层Gate，以实现位于不同层的源漏金属层SD和栅金属层Gate的可靠耦接。第三过孔K3和第四过孔K4为转接孔。该场景下，也可以认为是多个第三过孔K3与多个第四过孔K4并联。通过设置并联的多个第三过孔K3与多个第四过孔K4，一方面可以减小转接孔的电阻，另一方面可以提高转接可靠性。
当然，在一些其他实施例中，阵列基板可以仅具有贯穿栅绝缘层GI且暴露栅金属层Gate的过孔，在此基础上，源漏金属层SD可以通过该贯穿栅绝缘层GI且栅金属层Gate与栅金属层Gate直接搭接。
可选的，同第一转接部B1，此处第二转接部B2也可以与公共电极线Com1位于同层。因公共电极线Com1与电极层ITO位于同层，故也可以认为第二转接部B2是与电极层ITO位于同层。并且，源漏金属层SD在衬底01上的正投影同样可以位于栅金属层Gate在衬底01上的正投影内，多个第三过孔K3在衬底01上的正投影与多个第四过孔K4在衬底01上的正投影不交叠。
以及，在上拉节点PU处耦接所贯穿的第三过孔K3的数量，大于在耦接节点P0处耦接所贯穿的第三过孔K3的数量。在上拉节点PU处耦接所贯穿的第四过孔K4的数量，大于在耦接节点P0处耦接所贯穿的第四过孔K4的数量。即，耦接上拉节点PU处各部分之间开设的过孔数量大于耦接其他耦接节点P0处各部分之间开设的过孔数量。
因在输出栅极驱动信号时，上拉节点PU处的电压一般远大于除上拉节点PU外的其他耦接节点P0处的电压。如，参考图12所示的节点模拟电压示意图可知，上拉节点PU处的电压一般最大能达到30伏特(V)，而其他耦接节点P0处的电压一般最大仅能达到15V。图12中横坐标是指时间，单位为秒(s)，纵坐标是指电压，电位为V。此外，因在电压越大的位置遇水汽发生电化学腐蚀的可能性越高，故通过设置耦接上拉节点PU处各部分之间开设的过孔数量较多，可以提高转接可靠性，降低发生电化学腐蚀的可能性的概率。因其他耦接节点P0处的电压相对较小，故也无需设置较多数量的过孔实现搭接。
可选的，图13是本公开实施例提供的一种移位寄存器单元的结构版图。图14是图13所示结构在上拉节点PU处和一个耦接节点P0处的部分结构版图。参考图13和图14可以看出，在上拉节点PU处耦接所贯穿的第三过孔K3的数量与所贯穿的第四过孔K4的数量可以相同。且，在耦接节点P0处耦接所贯穿的第三过孔K3的数量与所贯穿的第四过孔K4的数量可以相同。如此，针对任一节点处，可以确保多个第三过孔K1处的电阻和多个第四过孔K4处的电阻相同，进一步确保可靠转接。
可选的，在本公开实施例中，在上拉节点PU处耦接所贯穿的第三过孔K3的数量和第四过孔K4的数量可以均大于等于3，且可以小于等于6。在耦接节点P0处耦接所贯穿的第三过孔K3的数量与所贯穿的第四过孔K4的数量可以均小于等于2。
可选的，继续参考图14还可以看出，在本公开实施例中，在上拉节点PU处耦接所贯穿的多个第三过孔K3，以及在耦接节点P0处耦接所贯穿的多个第 三过孔K3均可以被划分为沿第二方向X2依次排布的多个第三过孔组K30，每个第三过孔组K30包括一个第三过孔K3。在上拉节点PU处耦接所贯穿的多个第四过孔K4，以及在耦接节点P0处耦接所贯穿的多个第四过孔K4均可以被划分为多个第四过孔组K40，每个第四过孔组K40包括一个第四过孔K4。且，第四过孔组K40与第三过孔组K30可以沿第一方向X1依次排布。
即，在本公开实施例中，无论是上拉节点PU还是其他耦接节点P0的任一节点处，转接贯穿的多个第三过孔K3均可以沿第二方向X2依次排布，转接贯穿的多个第四过孔K4均可以沿第二方向X2依次排布，且第三过孔K3和第四过孔K4可以沿第一方向X1依次排布。如此，可以使得节点处转接部分在第一方向X1上的长度小于等于在第二方向X2上的长度，即，节点处转接部分的长度方向平行于第二方向X2。进而，可以更进一步的较好利用电路区A3内的空间，使得非显示区占用衬底01的面积能够足够小，为窄边框的设计奠定良好的基础。当然，在一些实施例中，假设某节点处转接贯穿的第三过孔K3和第四过孔K4数量均为1，则该第三过孔K3和第四过孔K4可以沿第一方向X1排布。
例如，参考图13和图14，其示出的在上拉节点PU处耦接所贯穿的多个第三过孔K3的数量与多个第四过孔K4的数量均为3。相应的，在上拉节点PU处耦接所贯穿的多个第三过孔K3可以被划分为沿第二方向X2依次排布的三个第三过孔组K30，在上拉节点PU处耦接所贯穿的多个第四过孔K4可以被划分为沿第二方向X2依次排布的三个第四过孔组K40。此时，参考图14可以看出，可以认为是上拉节点PU处，源漏金属层SD与栅金属层Gate通过3对过孔转接，形成了3对孔的并联。以及，其示出的在耦接节点P0处耦接所贯穿的多个第三过孔K3的数量与多个第四过孔K4的数量均为2。相应的，在耦接节点P0处耦接所贯穿的多个第三过孔K3可以被划分为沿第二方向X2依次排布的两个第三过孔组K30，在耦接节点P0处耦接所贯穿的多个第四过孔K4可以被划分为沿第二方向X2依次排布的两个第四过孔组K40。此时，参考图14可以看出，可以认为是其他耦接节点P0处，源漏金属层SD与栅金属层Gate通过2对过孔转接，形成了2对孔的并联。在此基础上，继续参考图6可以看出，在电路区A3内，可以在沿第一方向X1延伸的各竖线位置上开设竖条孔，这样可以做到即提高可靠性，又可以节省边框。
综上所述，本公开实施例提供了一种阵列基板。该阵列基板包括：具有依次邻接的显示区、走线区和电路区的衬底，位于显示区的像素，位于走线区且 具有挖孔的公共电极线，位于走线区和电路区的栅线引线，位于走线区和显示区的栅线，以及位于电路区的栅极驱动电路。其中，栅线引线与栅线位于不同层且相互转接，栅极驱动电路通过相互转接的栅线引线和栅线与像素耦接，并为像素提供栅极驱动信号。公共电极线与像素耦接，并为像素提供公共信号。因栅线引线与栅线的转接部分位于公共电极线具有的挖孔内，即位于走线区，充分利用了空间，故可以使得除显示区外的其他部分占用衬底的面积较小，进而能够更好的利于阵列基板的窄边框的设计。
图15是本公开实施例提供的一种阵列基板的制备方法流程图，该方法可以用于制备如上述实施例记载的阵列基板。如图15所示，该方法可以包括：
步骤1501、提供衬底。
并且，参考图1可以看出，提供的衬底01可以具有显示区A1和位于显示区A1至少一侧，且沿远离显示区A1的方向依次排布的走线区A2和电路区A3。
步骤1502、在显示区形成多个像素。
步骤1503、在走线区形成沿第一方向延伸的公共电极线。
并且，参考图1可以看出，形成的公共电极线Com1可以具有间隔排布的多个挖孔D。此外，公共电极线Com1可以与多个像素02耦接，并用于为多个像素02提供公共信号。
步骤1504、在显示区和走线区形成沿第二方向延伸的多条栅线。
并且，参考图1可以看出，第二方向X2与第一方向X1可以相交。如，图1所示的第二方向X2与第一方向X1相互垂直。
步骤1505、在电路区和走线区形成沿第二方向延伸的多条栅线引线。
并且，参考图2可以看出，形成的多条栅线引线G2位于栅线G1远离衬底01的一侧，且位于公共电极线Com1靠近衬底01的一侧。
步骤1506、在电路区形成栅极驱动电路。
并且，参考图2可以看出，形成的栅极驱动电路03可以与多条栅线引线G2耦接，多条栅线引线G2可以再与多条栅线G1转接，多条栅线G1还可以再与多个像素02耦接，从而实现栅极驱动电路03与像素02的可靠连接。在此基础上，栅极驱动电路03可以用于通过多条栅线引线G2和多条栅线G1向多个像素02提供栅极驱动信号。此外，在本公开实施例中，栅线引线G2与栅线G1的转接部分可以位于挖孔D内，如此，可以达到充分利用衬底01上的空间的目 的，有利于阵列基板的窄边框设计。
应当理解的是，本公开实施例的提供的上述制备方法应该具备与本公开实施例提供的阵列基板相同的特点和优点，所以本公开实施例提供的上述制备方法的特点和优点可以参照上文描述的阵列基板的特点和优点，在此不再赘述。
此外，尽管在附图中以特定顺序描述了方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，和/或将一个步骤分解为多个步骤执行等。此外，上面的一些步骤可以并行执行或顺序执行等等，并不局限于上文描述的具体操作顺序。各个方法步骤的具体方法可以参考上述装置侧实施例记载，在此不再赘述。
图16是本公开实施例提供的一种显示装置的结构示意图。如图16所示，该显示装置包括：供电组件J1，以及如上述任一附图所示的阵列基板00。其中，供电组件J1与阵列基板00耦接，并用于为阵列基板00供电。
可选的，该显示装置可以包括：车载显示装置、LCD显示装置、手机、平板电脑、电视机和显示器等任何具有显示功能的产品或部件。
需要说明的是，本公开的实施方式部分使用的术语仅用于对本公开的实施例进行解释，而非旨在限定本公开。除非另作定义，本公开的实施方式使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。
例如，本公开实施例中使用的“第一”、“第二”或者“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。
同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。
“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。
“上”、“下”、“左”或者“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存 在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (23)

  1. 一种阵列基板，所述阵列基板包括：
    衬底(01)，具有显示区(A1)和位于所述显示区(A1)至少一侧，且沿远离所述显示区(A1)的方向依次排布的走线区(A2)和电路区(A3)；
    多个像素(02)，位于所述显示区(A1)；
    沿第一方向(X1)延伸的公共电极线(Com1)，位于所述走线区(A2)，所述公共电极线(Com1)具有间隔排布的多个挖孔(D)，所述公共电极线(Com1)与所述多个像素(02)耦接；
    沿第二方向(X2)延伸的多条栅线(G1)，位于所述显示区(A1)和所述走线区(A2)，所述第二方向(X2)与所述第一方向(X1)相交；
    沿所述第二方向(X2)延伸的多条栅线引线(G2)，位于所述电路区(A3)和所述走线区(A2)，位于所述栅线(G1)远离所述衬底(01)的一侧，且位于所述公共电极线(Com1)靠近所述衬底(01)的一侧；
    栅极驱动电路(03)，位于所述电路区(A3)，所述栅极驱动电路(03)与所述多条栅线引线(G2)耦接，所述多条栅线引线(G2)与所述多条栅线(G1)转接，且转接部分位于所述挖孔(D)内，所述多条栅线(G1)还与所述多个像素(02)耦接。
  2. 根据权利要求1所述的阵列基板，其中，每个挖孔(D)的边缘均与所述公共电极线(Com1)的边缘之间存在间距，且距所述公共电极线(Com1)在所述第二方向(X2)上的任一边缘的间距相等；所述多个挖孔(D)沿所述第一方向(X1)间隔排布。
  3. 根据权利要求1所述的阵列基板，其中，所述栅极驱动电路(03)包括：沿所述第一方向(X1)依次排布且级联的多个移位寄存器单元(031)，所述多个像素(02)阵列排布；
    其中，所述多个移位寄存器单元(031)与所述多条栅线引线(G2)一一对应耦接，所述多条栅线引线(G2)与所述多条栅线(G1)一一对应转接，且转接部分一一对应的位于所述多个挖孔(D)内，所述多条栅线(G1)与多行像素(02)一一对应耦接。
  4. 根据权利要求3所述的阵列基板，其中，一一对应的每条所述栅线引线(G2)、每个所述挖孔(D)和每条所述栅线(G1)在所述第二方向(X2)上，沿同一条水平线依次排布。
  5. 根据权利要求1至4任一所述的阵列基板，其中，所述阵列基板还包括：
    位于所述栅线(G1)与所述栅线引线(G2)之间的第一绝缘层(J1)；
    位于所述栅线引线(G2)远离所述衬底(01)一侧的第二绝缘层(J2)；
    位于所述第二绝缘层(J2)远离所述衬底(01)一侧的第一转接部(B1)；
    以及，贯穿所述第二绝缘层(J2)的多个第一过孔(K1)，且贯穿所述第二绝缘层(J2)和所述第一绝缘层(J1)的多个第二过孔(K2)；
    其中，所述栅线引线(G2)在所述衬底(01)上的正投影位于所述栅线(G1)在所述衬底(01)上的正投影内，所述多个第一过孔(K1)在所述衬底(01)上的正投影与所述多个第二过孔(K2)在所述衬底(01)上的正投影不交叠；
    并且，所述第一转接部(B1)通过所述多个第一过孔(K1)与所述栅线引线(G2)搭接，并通过所述多个第二过孔(K2)与所述栅线(G1)搭接，以将所述栅线(G1)与所述栅线引线(G2)转接。
  6. 根据权利要求5所述的阵列基板，其中，所述多个第一过孔(K1)的数量与所述多个第二过孔(K2)的数量相同。
  7. 根据权利要求5所述的阵列基板，其中，所述多个第一过孔(K1)的数量与所述多个第二过孔(K2)的数量均大于等于4且小于等于8。
  8. 根据权利要求7所述的阵列基板，其中，所述多个第一过孔(K1)被划分为沿所述第一方向(X1)依次排布的多个第一过孔组(K10)，每个第一过孔组(K10)包括沿所述第二方向(X2)依次排布的多个第一过孔(K1)，且每个第一过孔组(K10)包括的第一过孔(K1)的数量小于等于所述多个第一过孔组(K10)的数量；
    所述多个第二过孔(K2)被划分为沿所述第一方向(X1)依次排布的多个 第二过孔组(K20)，每个第二过孔组(K20)包括沿所述第二方向(X2)依次排布的多个第二过孔(K2)，且每个第二过孔组(K20)包括的第二过孔(K2)的数量小于等于所述多个第二过孔组(K20)的数量。
  9. 根据权利要求8所述的阵列基板，其中，所述多个第一过孔(K1)的数量与所述多个第二过孔(K2)的数量均为4；
    所述多个第一过孔(K1)被划分为沿所述第一方向(X1)依次排布的两个第一过孔组(K10)，且每个第一过孔组(K10)包括沿所述第二方向(X2)依次排布的两个第一过孔(K1)；
    所述多个第二过孔(K2)被划分为沿所述第一方向(X1)依次排布的两个第二过孔组(K20)，且每个第二过孔组(K20)包括沿所述第二方向(X2)依次排布的两个第二过孔(K2)。
  10. 根据权利要求5所述的阵列基板，其中，所述第一转接部(B1)与所述公共电极线(Com1)位于同层。
  11. 根据权利要求5至10任一所述的阵列基板，其中，所述阵列基板还包括：位于所述走线区(A2)的公共电极引线(Com2)，所述公共电极引线(Com2)包括：位于所述衬底(01)与所述公共电极线(Com1)之间，且沿远离所述衬底(01)的方向依次层叠的第一电极线(Com21)和第二电极线(Com22)；
    所述阵列基板还包括：位于所述第一电极线(Com21)与所述第二电极线(Com22)之间的第三绝缘层(J3)，以及位于第二电极线(Com22)与所述公共电极线(Com1)之间的第四绝缘层(J4)；
    其中，所述公共电极线(Com1)通过贯穿所述第四绝缘层(J4)的过孔与所述第二电极线(Com22)搭接，并通过贯穿所述第三绝缘层(J3)和所述第四绝缘层(J4)的过孔与所述第一电极线(Com21)搭接。
  12. 根据权利要求11所述的阵列基板，其中，所述第一电极线(Com21)包括间隔排布的多个第一电极块，所述第二电极线(Com22)包括间隔排布的多个第二电极块。
  13. 根据权利要求11所述的阵列基板，其中，所述像素(02)包括：沿远离所述衬底(01)的方向依次层叠的栅金属层(Gate)、栅绝缘层(GI)、源漏金属层(SD)、钝化层(PVX)和电极层(ITO)；
    其中，所述第一电极线(Com21)与所述栅线(G1)位于同层，且均与所述栅金属层(Gate)位于同层；
    所述第二电极线(Com22)和所述栅线引线(G2)位于同层，且均与所述源漏金属层(SD)位于同层；
    所述第一绝缘层(J1)和所述第三绝缘层(J3)位于同层，且均与所述栅绝缘层(GI)位于同层；
    所述第二绝缘层(J2)和所述第四绝缘层(J4)位于同层，且均与所述钝化层(PVX)位于同层；
    所述公共电极线(Com1)与所述电极层(ITO)位于同层。
  14. 根据权利要求1至13任一所述的阵列基板，其中，所述栅极驱动电路中每个移位寄存器单元(031)包括：输入电路(0311)和输出电路(0312)；
    所述输入电路(0311)分别与多条驱动信号线和上拉节点(PU)耦接，并用于响应于所述多条驱动信号线提供的驱动信号，为所述上拉节点(PU)充电；
    所述输出电路(0312)分别与所述上拉节点(PU)和所述栅线引线(G2)耦接，并用于基于所述上拉节点(PU)的电位，向所述栅线引线(G2)传输栅极驱动信号。
  15. 根据权利要求14所述的阵列基板，其中，所述输入电路(0311)、所述输出电路(0312)和所述多条驱动信号线包括：沿远离所述衬底的方向依次层叠的栅金属层(Gate)、栅绝缘层(GI)、源漏金属层(SD)和钝化层(PVX)；
    所述阵列基板还包括：位于所述钝化层(PVX)远离所述衬底一侧的第二转接部(B2)，所述第二转接部(B2)通过贯穿所述钝化层(PVX)的多个第三过孔(K3)与所述源漏金属层(SD)搭接，并通过贯穿所述钝化层(PVX)和所述栅绝缘层(GI)的多个第四过孔(K4)与所述栅金属层(Gate)搭接，以将所述输入电路(0311)与所述驱动信号线在耦接节点(P0)处耦接，并将 所述输入电路(0311)和所述输出电路(0312)在所述上拉节点(PU)处耦接；
    其中，所述源漏金属层(SD)在所述衬底(01)上的正投影位于所述栅金属层(Gate)在所述衬底(01)上的正投影内，所述多个第三过孔(K3)在所述衬底(01)上的正投影与所述多个第四过孔(K4)在所述衬底(01)上的正投影不交叠；
    并且，在所述上拉节点(PU)处耦接所贯穿的第三过孔(K3)的数量，大于在所述耦接节点(P0)处耦接所贯穿的第三过孔(K3)的数量；以及，在所述上拉节点(PU)处耦接所贯穿的第四过孔(K4)的数量，大于在所述耦接节点(P0)处耦接所贯穿的第四过孔(K4)的数量。
  16. 根据权利要求15所述的阵列基板，其中，在所述上拉节点(PU)处耦接所贯穿的第三过孔(K3)的数量与所贯穿的第四过孔(K4)的数量相同；
    且，在所述耦接节点(P0)处耦接所贯穿的第三过孔(K3)的数量与所贯穿的第四过孔(K4)的数量相同。
  17. 根据权利要求15所述的阵列基板，其中，在所述上拉节点(PU)处耦接所贯穿的第三过孔(K3)的数量和第四过孔(K4)的数量均大于等于3，且小于等于6；在所述耦接节点(P0)处耦接所贯穿的第三过孔(K3)的数量与所贯穿的第四过孔(K4)的数量均小于等于2。
  18. 根据权利要求17所述的阵列基板，其中，在所述上拉节点(PU)处耦接所贯穿的多个第三过孔(K3)，以及在所述耦接节点(P0)处耦接所贯穿的多个第三过孔(K3)均被划分为沿所述第二方向(X2)依次排布的多个第三过孔组(K30)，每个第三过孔组(K30)包括一个第三过孔(K3)；
    在所述上拉节点(PU)处耦接所贯穿的多个第四过孔(K4)，以及在所述耦接节点(P0)处耦接所贯穿的多个第四过孔(K4)均被划分为沿所述第二方向(X2)依次排布的多个第四过孔组(K40)，每个第四过孔组(K40)包括一个第四过孔(K4)，且所述第四过孔组(K40)与所述第三过孔组(K30)沿所述第一方向(X1)依次排布。
  19. 根据权利要求18所述的阵列基板，其中，在所述上拉节点(PU)处耦接所贯穿的多个第三过孔(K3)的数量与多个第四过孔(K4)的数量均为3；在所述耦接节点(P0)处耦接所贯穿的多个第三过孔(K3)的数量与多个第四过孔(K4)的数量均为2；
    在所述上拉节点(PU)处耦接所贯穿的多个第三过孔(K3)被划分为沿所述第二方向(X2)依次排布的三个第三过孔组(K30)，在所述上拉节点(PU)处耦接所贯穿的多个第四过孔(K4)包括沿所述第二方向(X2)依次排布的三个第四过孔组(K40)；
    在所述耦接节点(P0)处耦接所贯穿的多个第三过孔(K3)被划分为沿所述第二方向(X2)依次排布的两个第三过孔组(K30)，在所述耦接节点(P0)处耦接所贯穿的多个第四过孔(K4)包括沿所述第二方向(X2)依次排布的两个第四过孔组(K40)。
  20. 根据权利要求15至19任一所述的阵列基板，其中，所述第二转接部(B2)与所述公共电极线(Com1)位于同层。
  21. 根据权利要求1至20任一所述的阵列基板，其中，所述第一方向(X1)与所述第二方向(X2)垂直。
  22. 一种显示装置，所述显示装置包括：供电组件(J1)，以及如权利要求1至21任一所述的阵列基板(00)；
    其中，所述供电组件(J1)与所述阵列基板(00)耦接，并用于为所述阵列基板(00)供电。
  23. 根据权利要求22所述的显示装置，其中，所述显示装置包括：车载显示装置。
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CN107085335A (zh) * 2017-04-20 2017-08-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法
CN107357475A (zh) * 2017-06-27 2017-11-17 上海天马微电子有限公司 触控面板和显示装置
US20190265566A1 (en) * 2018-02-28 2019-08-29 Panasonic Liquid Crystal Display Co., Ltd. Liquid crystal display device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107085335A (zh) * 2017-04-20 2017-08-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法
CN107357475A (zh) * 2017-06-27 2017-11-17 上海天马微电子有限公司 触控面板和显示装置
US20190265566A1 (en) * 2018-02-28 2019-08-29 Panasonic Liquid Crystal Display Co., Ltd. Liquid crystal display device

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