WO2024055408A1 - Dcdc变换器、开关电源及电子设备 - Google Patents

Dcdc变换器、开关电源及电子设备 Download PDF

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WO2024055408A1
WO2024055408A1 PCT/CN2022/132136 CN2022132136W WO2024055408A1 WO 2024055408 A1 WO2024055408 A1 WO 2024055408A1 CN 2022132136 W CN2022132136 W CN 2022132136W WO 2024055408 A1 WO2024055408 A1 WO 2024055408A1
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current
signal
output
current sampling
tube
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PCT/CN2022/132136
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English (en)
French (fr)
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张亮
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深圳英集芯科技股份有限公司
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/1566—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • This application relates to the field of electronic technology, specifically to a DCDC converter, switching power supply and electronic equipment.
  • Transient response means that DCDC can respond quickly when the load changes rapidly, providing sufficient power in a short period of time so that the output can be stable without large overshoot or undershoot.
  • fast transient response is very important.
  • solutions with better transient response are mainly proposed for buck converters.
  • COT constant on-time
  • COT can quickly increase or decrease the duty cycle by changing the frequency during load transient jumps, thus This prevents the output voltage from changing significantly.
  • this method cannot be used in some applications that require an operating frequency range.
  • Embodiments of the present application provide a DCDC converter, switching power supply and electronic equipment, which can improve load transient response speed.
  • inventions of the present application provide a DCDC converter.
  • the DCDC converter includes: an error amplifier, a compensation network, a comparator, a peak current sampling module, a power tube, a ramp generation module, and a driving module, wherein,
  • One end of the peak current sampling module is connected to the drain of the power tube, the input voltage is connected through an inductor, and the first output voltage is connected through a diode, and the other end of the peak current sampling module is connected to the ramp generation module;
  • One end of the ramp generation module is connected to an adder, and the other end is connected to the negative input end of the comparator.
  • the adder is also connected to a plurality of current sampling modules, and one end of the switch corresponding to each current sampling module is connected to the third an output voltage, and the other end of the switch outputs a corresponding second output voltage;
  • the first output voltage is divided by a first resistor and a second resistor.
  • the divided voltage signal of the first output voltage passes through the first resistor and is connected to the negative input terminal of the error amplifier.
  • the error amplifier The positive input terminal of the error amplifier is connected to the reference voltage, and the output terminal of the error amplifier is connected to the positive input terminal of the comparator through the compensation network;
  • the output end of the comparator is connected to one end of the driving module, the other end of the driving module is connected to the gate of the power tube, and the source of the power tube is grounded.
  • embodiments of the present application provide a switching power supply, which includes the DCDC converter described in the first aspect.
  • an embodiment of the present application provides an electronic device, characterized in that the electronic device includes the DCDC converter as described in the first aspect, or the switching power supply as described in the second aspect.
  • the DCDC converter, switching power supply and electronic equipment described in the embodiments of this application include: error amplifier, compensation network, comparator, peak current sampling module, power tube, ramp wave generation module, driver module, wherein one end of the peak current sampling module is connected to the drain of the power tube, the input voltage is connected through the inductor, and the first output voltage is connected through the diode, and the other end of the peak current sampling module is connected to the ramp wave generation module; the ramp wave generation module One end is connected to the adder, and the other end is connected to the negative input end of the comparator.
  • the adder is also connected to multiple current sampling modules.
  • One end of the switch corresponding to each current sampling module is connected to the first output voltage, and the other end of the switch outputs the corresponding the second output voltage;
  • the first output voltage is divided by the first resistor and the second resistor, the first output voltage passes through the divided voltage signal of the first resistor and is connected to the negative input terminal of the error amplifier, and the positive input terminal of the error amplifier
  • the reference voltage is connected, and the output end of the error amplifier is connected to the positive input end of the comparator through the compensation network;
  • the output end of the comparator is connected to one end of the drive module, and the other end of the drive module is connected to the gate of the power tube. Grounding the source can improve the load transient response speed.
  • Figure 1 is a schematic structural diagram of a BOOST converter provided by an embodiment of the present application.
  • Figure 2 is a schematic waveform diagram of a BOOST converter from light load to heavy load provided by the embodiment of the present application;
  • Figure 3 is a schematic waveform diagram of a BOOST converter switching from heavy load to light load according to the embodiment of the present application;
  • Figure 4 is a schematic structural diagram of a fast transient response DCDC converter provided by an embodiment of the present application.
  • Figure 5 is a schematic structural diagram of a ramp wave generation module provided by an embodiment of the present application.
  • Figure 6 is a schematic waveform diagram of a ramp wave generation module provided by an embodiment of the present application.
  • Figure 7 is a schematic waveform diagram of a DCDC converter switching from light load to heavy load according to an embodiment of the present application
  • FIG. 8 is a schematic waveform diagram of a DCDC converter switching from heavy load to light load according to an embodiment of the present application.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • Figure 1 is the schematic diagram of a multi-port output BOOST converter.
  • Ci is the input capacitor
  • L is the inductor
  • D is the freewheeling diode
  • BG is the power tube
  • Co is the output capacitor.
  • Vo is the output voltage
  • S1 ⁇ Sn are multi-port output switches
  • Vo1 ⁇ Von are the output voltages of each channel
  • R1 and R2 are voltage dividing resistors
  • EA is the error amplifier
  • C0, C1 and Rc1 form the compensation network
  • CMP is the comparison converter
  • Vslope is the slope compensation voltage
  • the multi-port output BOOST converter also includes a peak current sampling module and a driving module.
  • the working principle of the multi-port output BOOST converter is as follows: the divided voltage VFB of the output voltage and the reference voltage VREF are passed through the error amplifier EA to generate the error amplification signal Vea.
  • the peak current sampling module samples the peak current signal Vcs, Vcs and the ramp wave. After the compensation signal Vslope is superimposed, the triangular wave signal Vramp is obtained. Vramp and Vea are compared through the comparator CMP to obtain the duty cycle signal PWMON. After passing the drive signal DRIVE, the drive signal BG_DRV of the power tube BG is generated.
  • Figure 2 is the waveform of the multi-port output BOOST converter when it transitions from light load to heavy load.
  • the load current Iload will increase instantaneously.
  • the output voltage Vo begins to decrease, and its divided voltage VFB will be less than the reference voltage VREF, and the EA The output Vea will rise slowly, thereby increasing the duty cycle of the PWM signal and causing the inductor current to rise.
  • the output voltage will continue to fall until the inductor current rises to be greater than the load current. The output voltage just starts to rise and eventually stabilizes.
  • t1 The entire adjustment process time is shown as t1 in the figure.
  • the size of t1 has a positive and negative relationship with the loop bandwidth. Since the BOOST loop bandwidth is limited by the zero point of the right half plane, it cannot be very large, so the small signal response of the loop The speed cannot be very fast. When Vo jumps from light load to heavy load, the undershoot voltage ⁇ Vdrop will be very large.
  • Figure 3 is the waveform of the multi-port output BOOST converter when it transitions from heavy load to light load.
  • the branch switches S1 ⁇ Sn suddenly turn off one or more channels the load current will decrease instantly.
  • the output voltage Vo begins to rise, and its divided voltage VFB will be greater than the reference voltage VREF, EA
  • the output Vea will slowly decrease, thereby reducing the duty cycle of the PWM signal and causing the inductor current to decrease.
  • the output voltage will continue to rise until the inductor current drops to less than the load current. The output voltage just starts to drop and eventually stabilizes.
  • t2 The entire adjustment process time is shown as t2 in the figure.
  • the size of t2 has a positive and negative relationship with the loop bandwidth. Since the BOOST loop bandwidth is limited by the zero point of the right half plane, it cannot be very large. Therefore, the small signal response of the loop The speed cannot be very fast, and the overshoot voltage ⁇ Vshoot will be very large when Vo changes from heavy load to light load.
  • FIG. 4 is a schematic structural diagram of a DCDC converter provided by an embodiment of the present application.
  • the DCDC converter includes: an error amplifier EA, a compensation network, a comparator CMP, a peak value Current sampling module, power tube BG, ramp wave generation module, drive module DRIVE, among which,
  • One end of the peak current sampling module is connected to the drain of the power tube BG, the input voltage Vin is connected through the inductor L, and the first output voltage Vo is connected through the diode D.
  • the other end of the peak current sampling module is connected to the ramp wave. generate module;
  • the adder ADD is also connected to multiple current sampling modules, and each current sampling module corresponds to One end of the switch is connected to the first output voltage Vo, and the other end of the switch outputs the corresponding second output voltage;
  • the first output voltage is divided by a first resistor R1 and a second resistor R2, and the first output voltage is connected to the negative input end of the error amplifier EA through the divided voltage signal VFB of the first resistor ( -), the positive input terminal (+) of the error amplifier EA is connected to the reference voltage VREF, and the output terminal of the error amplifier EA is connected to the positive input terminal (+) of the comparator CMP through the compensation network;
  • the output end of the comparator CMP is connected to one end of the drive module DRIVE, the other end of the drive module DRIVE is connected to the gate of the power tube BG, and the source of the power tube BG is grounded.
  • n is an integer greater than 1
  • different current sampling modules correspond to different switches, as follows: the current sampling module corresponds to S1, and its corresponding branch sampling current Ics1 and the second output voltage Vo1; the current sampling module corresponds to S2, and its corresponding branch sampling current Ics2 and the second output voltage Vo2; ...; the current sampling module corresponds to Sn, and its corresponding branch sampling current Icsn and the second output voltage Von.
  • each branch of Vo1 to Von can be connected to a load, that is, each second output voltage is provided to a corresponding load.
  • Vo is the total voltage output
  • Vo1 ⁇ Von are the output voltage branches opened according to application requirements. Vo generally does not have a separate load.
  • the opened branches generally have loads, so each branch can be loaded.
  • the DCDC converter mentioned in the embodiments of this application can avoid the influence of low output loop bandwidth and respond quickly to load transient changes.
  • the input voltage Vin is grounded through the input capacitor Ci, and the output end of the diode D is grounded through the output capacitor Co.
  • the input voltage Vin is grounded through the input capacitor Ci, and the output terminal of the diode D is grounded through the output capacitor Co.
  • the compensation network includes: a first capacitor C0, a second capacitor C1 and a third resistor Rcl;
  • the output end of the error amplifier EA is connected to the third resistor Rcl and the second capacitor C1 in sequence, and the second capacitor C1 is grounded;
  • the error amplifier EA is connected to ground through the first capacitor C0.
  • C0, C1 and Rc1 form a compensation network.
  • the DCDC converter is used for:
  • the total output current sampling signal Ics, the peak sampling current Ipk sampled by the peak current sampling module, the ramp compensation current Islope and the DC current signal Idc are passed through the ramp generation module to obtain the triangular wave signal Vramp.
  • each branch has a current sampling module.
  • the current signals of the branches S1 ⁇ Sn are sampled to obtain the sampling signals Ics1 ⁇ Icsn. Then, the sampling currents can be superimposed to obtain the total output current sampling signal Ics. This signal is combined with the peak sampling signal.
  • the current Ipk, the ramp compensation current Islope, and the DC current signal Idc enter the ramp generation module to generate the triangular wave signal Vramp.
  • LOOP2 in the figure is the output voltage loop.
  • the divided voltage signal VFB of the output voltage Vo and the reference voltage VREF pass through the error amplifier EA to generate the error signal Vea, which is compared with the triangular wave signal Vramp to obtain the account.
  • the space ratio signal PWMON then drives the power tube BG to obtain a stable output voltage.
  • the gain of the LOOP2 loop is relatively large, so a compensation network composed of C0, C1 and Rc1 is required to ensure its stability.
  • LOOP1 is the output current loop.
  • the sampling currents Ics1 ⁇ Icsn of each branch are superimposed by the adder ADD to obtain the total output current sampling signal Ics.
  • the triangular wave signal Vramp is generated, which is compared with the error signal Vea.
  • the duty cycle signal PWMON is obtained, and then the power tube BG is driven to obtain a stable output voltage. It can be seen from this that the output current enters the LOOP1 loop and participates in controlling the output voltage. The gain of this loop is low, so no additional compensation network is needed. The bandwidth is large and can respond to instantaneous changes in the output current.
  • the LOOP2 loop refers to the output voltage loop.
  • the feedback signal comes from the output voltage Vo.
  • a signal with a certain duty cycle is generated to control the turning on and off of the power tube.
  • This feedback path is the loop LOOP2. Its specific working principle is as follows: when the output voltage is higher than the set voltage, VFB increases, the error signal Vea decreases after EA, and the duty cycle obtained after comparing with the ramp signal decreases, thereby reducing the turn-on time of the power tube BG.
  • the LOOP1 loop refers to the output current loop.
  • the feedback signal originates from the output current Ics1 ⁇ Icsn. After current superposition, the total output current feedback signal Ics is obtained. Then it enters the ramp wave generation module, passes through the comparator and driver module, and generates a duty cycle to control the turning on and off of the power tube.
  • This feedback path is loop LOOP1. Its specific working principle is as follows: When one or more of the S1 ⁇ Sn branches are suddenly turned on (the branches are loaded), Ics will increase, and the DC value of the ramp signal generated by the ramp module will decrease, so the duty cycle will decrease.
  • the BG turn-on time will increase, and the energy provided by the converter for the output will increase, so the output will not have a large undershoot voltage; similarly, when one or more channels of S1 ⁇ Sn are suddenly turned off, Ics will decrease, and the slope The DC value of the ramp signal generated by the wave module will increase, so the duty cycle will decrease after passing through the comparator, and the BG turn-on time will decrease. The energy provided by the converter for the output is too small, so the output will not have a large overshoot. Voltage.
  • both loops LOOP1 and LOOP2 can adjust the duty cycle. Since the gain of LOOP1 of the output current mode is very small and the bandwidth is large, that is, the adjustment speed is very fast. Because of this, it can respond quickly to load transient changes with large amplitude changes, and when there is no transient change in the load When the load current changes very little, the low loop gain will not introduce this small value into the duty cycle, so it will not affect the high-gain, low-bandwidth loop LOOP2, thereby ensuring two The loops do not affect each other, ensuring that the duty cycle is not chaotic, that is, ensuring stability.
  • the DCDC converter is used for:
  • the load current Iload When at least one branch corresponding to the plurality of current sampling modules is turned on, the load current Iload will suddenly increase, and the output current sampling signal of the current sampling module corresponding to the at least one branch will also rise rapidly.
  • the total output current sampling signal Ics after the device ADD will rise rapidly, and will rapidly reduce the DC level value of the triangular wave signal Vramp after entering the ramp wave generation module.
  • a larger peak current means that a longer BG turn-on time is required, that is, the duty cycle increases.
  • the inductor current will also increase, and the energy provided to the load will also increase. Since the instantaneous increase in load current is directly fed back to Vramp through the output current loop LOOP1 to increase the duty cycle, and no longer relies on the output voltage loop LOOP2, the response speed is very fast and the undershoot of the output voltage Vo is very small. , to achieve the purpose of improving the load transient response speed.
  • the DCDC converter is used for:
  • the load current Iload will suddenly decrease, and the current sampling module outputs Ics1 ⁇ Icsn of S1 ⁇ Sn will decrease rapidly corresponding to the conducting branches.
  • the total output current sampling signal Ics after the ADD of the device will drop rapidly.
  • the DC level value of the triangular wave Vramp will rapidly increase. Since the loop speed of LOOP1 is much larger than LOOP2, Vea will basically remain unchanged at this time. , when the peak value of triangular wave Vramp reaches the value of Vea, a smaller peak current is required, and the rising rate of the inductor current remains unchanged.
  • a smaller peak current means that a shorter BG turn-on time is required, that is, the duty cycle is reduced.
  • the inductor current will also decrease, and the energy provided to the load will also decrease. Since the instantaneous reduction of the load current is directly fed back to Vramp through the output current loop LOOP1 to reduce the duty cycle, instead of relying on the output voltage loop LOOP2, the response speed is very fast and the overshoot of the output voltage Vo is also very small. Thus, the purpose of improving the load transient response speed is achieved.
  • the ramp wave generation module includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP5.
  • PMOS transistor MP6 first NMOS transistor MN1 and second NMOS transistor MN2;
  • the slope compensation current Islope is connected to the drain and gate of the first PMOS transistor MP1, and the source of the first PMOS transistor is connected to the source of the second PMOS transistor MP2 and the third PMOS transistor.
  • the source electrode of MP3, the source electrode of the fourth PMOS transistor MP4, the source electrode of the fifth PMOS transistor MP5, the source electrode of the sixth PMOS transistor MP6, and the gate electrode of the first PMOS transistor MP1 are connected to each other.
  • the drain of the second PMOS transistor MP2 is connected to the drain of the fourth PMOS transistor MP4, the drain of the fifth PMOS transistor MP5, the drain of the second NMOS transistor MN2 and is connected to the ground through the fourth resistor R. , the drain of the second PMOS transistor MP2 is also used to output the triangular wave signal Vramp;
  • the peak sampling current Ipk is connected to the gate and drain of the third PMOS tube MP3, and the gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4; the fourth PMOS tube The drain of MP4 is connected to the drain of the second NMOS transistor MN2;
  • the total output current sampling signal Islope is connected to the gate and drain of the first NMOS transistor MN1, and the gate of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2.
  • the source of the NMOS transistor MN1 and the source of the second NMOS transistor MN2 are both grounded;
  • the direct current signal Idc is connected to the drain and gate of the sixth PMOS transistor MP6, and the gate of the sixth PMOS transistor MP6 is connected to the gate of the fifth PMOS transistor MP5.
  • the first PMOS tube and the second PMOS tube form a current mirror for mirroring the ramp compensation current
  • the third PMOS tube and the fourth PMOS tube form a current mirror for mirroring the peak sampling current
  • the fifth PMOS tube and the sixth PMOS tube form a current mirror for mirroring the DC current signal
  • the first NMOS tube and the second NMOS tube form a current mirror for mirroring the total output current sampling signal
  • the ramp compensation current, the peak sampling current, the DC current signal and the total output current sampling signal all flow into the fourth resistor and are converted into the triangle wave signal, which satisfies the following relationship:
  • Vramp (Islope+Ipk+Idc-Ics) ⁇ R
  • Vramp represents the triangle wave signal
  • Islope represents the slope compensation current
  • Ipk represents the peak sampling current
  • Idc represents the DC current signal
  • Ics represents the total output current sampling signal
  • R represents the resistance of the fourth resistor.
  • MP1 and MP2 form a current mirror, which mirrors the slope compensation current Islope signal.
  • MP3 and MP4 form a current mirror, which mirrors the peak sampling current Ipk.
  • MP5 and MP6 form a current mirror, which mirrors the DC current signal Idc.
  • MN1 and MN2 form a current.
  • Mirror, the mirror outputs the current signal Ics.
  • Vramp (Islope+Ipk+Idc-Ics) ⁇ R
  • VDC (Idc-Ics) ⁇ R
  • VDC represents the DC voltage signal of Vramp.
  • Islope and Ipk are signals that change from cycle to cycle. Assuming that the DC voltage signal of Vramp is VDC, then:
  • VDC (Idc-Ics) ⁇ R
  • Figure 6 is the waveform diagram of the ramp wave generation module.
  • Ipk is the peak current sampling signal when BG is turned on, so it is a ramp signal when BG is turned on, and is 0 when BG is turned off
  • Islope is a ramp compensation signal, which is also a ramp signal when BG is turned on, and BG is turned off. It is 0 when it is off
  • Idc is a DC current signal, so it does not change whether BG is turned on or off
  • Ics is an output current sampling signal, which will change when the load changes, especially when the S1 ⁇ Sn branch is turned on or off There will be an instantaneous change
  • Vramp is the final generated ramp signal. It can be seen that when Ics suddenly becomes larger, VDC will decrease rapidly, and when Ics suddenly becomes smaller, VDC will increase rapidly.
  • Figure 7 is a waveform diagram of the DCDC converter of the present invention from light load to heavy load. It can be seen from the figure that before the jump, that is, when the load is light load, the DC value VDC of Vramp is higher because the output current sampling signal Ico is smaller at this time. When one or more branches S1 ⁇ Sn are suddenly turned on, the load current Iload will suddenly increase. The outputs Ics1 ⁇ Icsn of the current sampling module of S1 ⁇ Sn will increase rapidly corresponding to the conduction branches.
  • the total after the adder ADD The output current sampling signal Ics will rise rapidly, causing the DC voltage value of Vramp to decrease rapidly, and the response speed of Vea is very slow, so the time for the peak value of Vramp to rise to Vea increases, that is, the duty cycle increases, and the inductor current also increases. Because the inductor current increases very quickly, the inductor current will exceed the load current in a short period of time, and the output voltage will stop falling and slowly rise. After that, the output voltage loop LOOP2 will adjust it to the set voltage value. After the heavy load is stable, the DC value VDC of Vramp is lower because the output current sampling signal Ics is larger.
  • Figure 8 is a waveform diagram of the DCDC converter of the present invention switching from heavy load to light load. It can be seen from the figure that before the jump, that is, when the load is heavy load, the DC value VDC of Vramp is low. This is because the output current sampling signal Ics is large at this time. When one or more branches S1 ⁇ Sn are suddenly turned off, the load current Iload will suddenly decrease, and the output Ics1 ⁇ Icsn of the current sampling module of S1 ⁇ Sn will decrease rapidly corresponding to the conduction branch.
  • the total output current sampling signal Ics will drop rapidly, causing the DC voltage value of Vramp to increase rapidly, and the response speed of Vea is very slow, so the time for the peak value of Vramp to rise to Vea is reduced, that is, the duty cycle is reduced, and the inductor current also decreased. Because the inductor current decreases very quickly, the inductor current will be lower than the load current in a short period of time, and the output voltage will stop rising and slowly decrease. After that, the output voltage loop LOOP2 will adjust it to the set voltage value. After the light load is stable, the DC value VDC of Vramp is higher because the output current sampling signal Ics is smaller.
  • the DCDC converter described in the embodiment of this application includes: an error amplifier, a compensation network, a comparator, a peak current sampling module, a power tube, a ramp generation module, and a driving module, where the peak One end of the current sampling module is connected to the drain of the power tube, the input voltage is connected through the inductor, and the first output voltage is connected through the diode.
  • the other end of the peak current sampling module is connected to the ramp wave generation module; one end of the ramp wave generation module is connected to the adder. , and the other end is connected to the negative input end of the comparator.
  • the adder is also connected to multiple current sampling modules.
  • One end of the switch corresponding to each current sampling module is connected to the first output voltage, and the other end of the switch outputs the corresponding second output voltage.
  • the first output voltage is divided by the first resistor and the second resistor, the first output voltage passes through the divided voltage signal of the first resistor and is connected to the negative input terminal of the error amplifier, and the positive input terminal of the error amplifier is connected to the reference voltage,
  • the output end of the error amplifier is connected to the positive input end of the comparator through the compensation network; the output end of the comparator is connected to one end of the drive module, the other end of the drive module is connected to the gate of the power tube, and the source of the power tube is grounded.
  • the load transient response performance of DCDC is poor, mainly due to the output loop bandwidth: for the BUCK converter, the output loop bandwidth is controlled by the switching frequency, and for the BOOST converter, the output loop bandwidth is also controlled by the switching frequency. Stack zero points with the right half plane.
  • the output load current is sampled and introduced into the ramp signal Vramp to establish an output current loop.
  • the duty cycle can be quickly adjusted by changing Vramp to stabilize the output. It is no longer necessary to pass The output voltage loop is slowly adjusted, thereby avoiding the limitation of the output loop bandwidth.
  • the newly added output current loop gain is very small, and there is no need to add an additional compensation network to adjust its stability, so the loop design complexity of the circuit is Nor will it increase.
  • a larger peak current means that a longer BG turn-on time is required, that is, the duty cycle increases.
  • the inductor current will also increase, and the energy provided to the load will also increase. Since the instantaneous increase in load current is directly fed back to Vramp through the output current loop LOOP1 to increase the duty cycle, and no longer relies on the output voltage loop LOOP2, the response speed is very fast and the undershoot of the output voltage Vo is very small.
  • the load current Iload will suddenly decrease, and the output Ics1 ⁇ Icsn of the current sampling module of S1 ⁇ Sn will decrease rapidly corresponding to the conduction branch.
  • the total output current sampling signal Ics will decrease rapidly.
  • the DC level value of the triangular wave Vramp will rapidly increase. Since the loop speed of LOOP1 is much larger than LOOP2, Vea will basically remain unchanged at this time, and the peak value of the triangular wave Vramp will be To rise to the value of Vea, a smaller peak current is required, and the inductor current rise rate remains unchanged. Therefore, a smaller peak current means that a shorter BG turn-on time is required, that is, the duty cycle is reduced. As the duty cycle decreases, the inductor current will also decrease, and the energy provided to the load will also decrease.
  • the response speed is very fast and the overshoot of the output voltage Vo is also very small. Furthermore, the load transient response speed can be improved.
  • An embodiment of the present application also provides a switching power supply, which may include any of the above-mentioned DCDC converters, and the switching power supply can improve the load transient response speed.
  • An embodiment of the present application also provides an electronic device, which may include any of the above-mentioned DCDC converters or switching power supplies.
  • the electronic device can improve the load transient response speed.
  • the electronic device may include at least one of the following: a chip, a charger, an outdoor power supply, etc., which are not limited here.

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Abstract

本申请提供了一种DCDC变换器、开关电源及电子设备，该DCDC变换器中的峰值电流采样模块的一端连接功率管的漏极、通过电感接入输入电压以及通过二极管连接第一输出电压，峰值电流采样模块的另一端接入斜波产生模块；斜波产生模块的一端连接加法器，另一端连接比较器的负输入端，加法器连接的每一电流采样模块对应的开关一端连接第一输出电压另一端输出对应的第二输出电压；第一输出电压的分压电压信号接入误差放大器的负输入端，误差放大器的正输入端接入参考电压，误差放大器的输出端通过补偿网络接入比较器的正输入端；比较器的输出端接入驱动模块的一端，驱动模块的另一端接入功率管的栅极。本申请实施例能够提升负载瞬态响应速度。

Description

DCDC变换器、开关电源及电子设备
本申请要求于2022年09月13日提交中国专利局、申请号为202211109551.2、申请名称为“DCDC变换器、开关电源及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，具体涉及一种DCDC变换器、开关电源及电子设备。
背景技术
瞬态响应是指DCDC在负载快速变化时，能够迅速反应，在短时间内提供足够的功率，使输出能够平稳，不会出现大的过冲或下冲。在一些应用中，比如，CPU内核电压或者是射频功率放大电路，快速瞬态响应非常重要。现阶段瞬态响应较好的解决方案主要是针对BUCK变换器提出来的，如COT(恒定开通时间)通过改变在负载瞬态跳变时的频率，可以快速增加或减小占空比，从而使输出电压不会出现大幅度的变化，然后，这种方式由于频率有改变，在一些对工作频率范围有要求的应用中无法使用。而对于BOOST与BUCK-BOOST变换器，由于有右半平面零点的存在，其穿越频率必须小于这个零点的一半，因而其带宽较小，负载瞬态响应速度很慢，现阶段还没有较好的方案能够解决这个问题。因此，如何提升负载瞬态响应速度的问题亟待解决。
发明内容
本申请实施例提供了一种DCDC变换器、开关电源及电子设备，能够提升负载瞬态响应速度。
第一方面，本申请实施例提供一种DCDC变换器，所述DCDC变换器包括：误差放大器、补偿网络、比较器、峰值电流采样模块、功率管、斜波产生模块、驱动模块，其中，
所述峰值电流采样模块的一端连接所述功率管的漏极、通过电感接入输入电压以及通过二极管连接第一输出电压，所述峰值电流采样模块的另一端接入所述斜波产生模块；
所述斜波产生模块的一端连接加法器，以及另一端连接所述比较器的负输入端，所述加法器还连接多个电流采样模块，每一电流采样模块对应的开关一端连接所述第一输出电压，以及该开关的另一端输出对应的第二输出电压；
所述第一输出电压通过第一电阻、第二电阻进行分压，所述第一输出电压经过所述第一电阻的分压电压信号接入所述误差放大器的负输入端，所述误差放大器的正输入端接入参考电压，所述误差放大器的输出端通过所述补偿网络接入所述比较器的正输入端；
所述比较器的输出端接入所述驱动模块的一端，所述驱动模块的另一端接入所述功率管的栅极，所述功率管的源极接地。
第二方面，本申请实施例提供一种开关电源，所述包括如第一方面所述的DCDC变换器。
第三方面，本申请实施例提供一种电子设备，其特征在于，所述电子设备包括如第一方面所述的DCDC变换器，或者，如第二方面所述的开关电源。
实施本申请实施例，具备如下有益效果：
可以看出，本申请实施例中所描述的DCDC变换器、开关电源及电子设备，DCDC变换器包括：误差放大器、补偿网络、比较器、峰值电流采样模块、功率管、斜波产生模块、驱 动模块，其中，峰值电流采样模块的一端连接功率管的漏极、通过电感接入输入电压以及通过二极管连接第一输出电压，峰值电流采样模块的另一端接入斜波产生模块；斜波产生模块的一端连接加法器，以及另一端连接比较器的负输入端，加法器还连接多个电流采样模块，每一电流采样模块对应的开关一端连接第一输出电压，以及该开关的另一端输出对应的第二输出电压；第一输出电压通过第一电阻、第二电阻进行分压，第一输出电压经过第一电阻的分压电压信号接入误差放大器的负输入端，误差放大器的正输入端接入参考电压，误差放大器的输出端通过补偿网络接入比较器的正输入端；比较器的输出端接入驱动模块的一端，驱动模块的另一端接入功率管的栅极，功率管的源极接地，能够提升负载瞬态响应速度。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种BOOST变换器的结构示意图；
图2是本申请实施例提供的一种BOOST变换器轻载跳变重载的波形示意图；
图3是本申请实施例提供的一种BOOST变换器重载跳变轻载的波形示意图；
图4是本申请实施例提供的一种快速瞬态响应的DCDC变换器的结构示意图；
图5是本申请实施例提供的一种斜波产生模块的结构示意图；
图6是本申请实施例提供的一种斜波产生模块的波形示意图；
图7是本申请实施例提供的一种DCDC变换器轻载跳变重载的波形示意图；
图8是本申请实施例提供的一种DCDC变换器重载跳变轻载的波形示意图。
具体实施方式
为了本技术领域人员更好理解本申请的技术方案，下面结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的部分实施例，而并非全部的实施例。基于本申请实施例的描述，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请所保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如，包含了一系列步骤或单元的过程、方法、软件、产品或设备没有限定于已列出的步骤或单元，而是还包括没有列出的步骤或单元，或还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
下面结合附图对本申请实施例进行介绍，附图中相交导线的交叉处有圆点表示导线相接，交叉处无圆点表示导线不相接。
相关技术中，请查阅图1，如图1是多口输出BOOST变换器的原理图，图中Ci为输入 电容，L为电感，D为续流二极管，BG为功率管，Co为输出电容，Vo为输出电压，S1～Sn为多口输出开关，Vo1～Von为每条通路的输出电压，R1与R2为分压电阻，EA为误差放大器，C0、C1与Rc1构成补偿网络，CMP为比较器，Vslope为斜波补偿电压，该多口输出BOOST变换器还包括峰值电流采样模块和驱动模块。
该多口输出BOOST变换器的工作原理如下：输出电压的分压VFB与基准电压VREF经过误差放大器EA后产生误差放大信号Vea，峰值电流采样模块采样得到的信号峰值电流信号Vcs，Vcs与斜波补偿信号Vslope叠加后得到三角波信号Vramp，Vramp与Vea通过比较器CMP比较得到占空比信号PWMON，经过驱动信号DRIVE后产生功率管BG的驱动信号BG_DRV。一个周期内，当BG_DRV为高时，BG导通，电感L上的电流会增加并存储能量，LX为低，续流二极管D关断，输出由电容Co提供能量；当BG_DRV为低时，BG关断，电感电流会使LX升高并导通二极管D续流，此时电感电流不仅为负载提供能量，同时会为电容Co充电，在此时段内，电感电流下降并最终值等于周期开始时的最初电感电流值，以达到磁平衡，下个周期开始重复这个过程。由此可知，只要BG有稳定的导通与关断时间(即稳定的占空比)，就可以得到稳定的输出Vo，然后根据不同的需求开通S1～Sn，就可以得到支路输出Vo1～Von。
接着，分析多口输出BOOST变换器得到稳定占空比的过程。假定支路开关S1～Sn突然开通一路或多路，电路负载电流会突然变大，Vo会下降，其分压VFB也会下降并低于基准VREF，经过EA后Vea会上升，与Vramp比较后得到的占空比PWMON信号高电平时间会增加，即占空比增加，因而BG的开通时间会增加，电感电流上升，为输出提供的能量也会增加，致使Vo会逐渐上升，多个周期后达到稳定值。然后，由于右半平面零点的限制，通过补偿网络C0、Rc1与C1确定的环路带宽很小，因而Vea的变化速率很慢，占空比增加也很慢，这导致电感电流只能缓慢的上升，输出电压Vo有很大的下冲电压。
反之，同理，假定支路开关S1～Sn突然关断一路或多路，负载电流会突然变小，Vo会上升，其分压VFB也会上升并高于基准VREF，经过EA后Vea会下降，与Vramp比较后得到的占空比PWMON信号高电平时间会减小，即占空比减小，因而BG的开通时间会减小，电感电流下降，为输出提供的能量也会减小，致使Vo会逐渐下降，多个周期后达到稳定值。然后由于右半平面零点的限制，通过补偿网络C0、Rc1与C1确定的环路带宽很小，因而Vea的变化速率很慢，占空比减小也很慢，这导致电感电流只能缓慢的减小，输出电压Vo有很大的上冲电压。
具体的，如图2所示，图2为多口输出BOOST变换器轻载跳变重载时的波形。当支路开关S1～Sn突然开通一路或多路时，负载电流Iload会瞬间增大，由于电感电流小于负载电流需求，因而输出电压Vo开始下降，其分压VFB将小于基准电压VREF，EA的输出Vea将会缓慢上升，从而加大PWM信号的占空比，使电感电流上升，在上升过程中，电感电流小于负载电流时，输出电压会持续下降，直到电感电流上升到大于负载电流后，输出电压才开始上升，并最终趋于稳定。整个调整过程时间如图中t1所示，t1的大小与环路带宽成正反例关系，又因BOOST环路带宽受右半平面零点限制，不能做到很大，因而环路的小信号响应速度不可能很快，Vo在轻载跳变重载的过程中下冲电压ΔVdrop会很大。
具体的，如图3所示，图3为多口输出BOOST变换器重载跳变轻载时的波形。当支路开关S1～Sn突然关断一路或多路时，负载电流会瞬间减小，由于电感电流大于负载电流需求，因而输出电压Vo开始上升，其分压VFB将大于基准电压VREF，EA的输出Vea将会缓慢下降，从而减小PWM信号的占空比，使电感电流下降，在下降过程中，电感电流大于负载电 流时，输出电压会持续上升，直到电感电流下降到小于负载电流后，输出电压才开始下降，并最终趋于稳定。整个调整过程时间如图中t2所示，t2的大小与环路带宽成正反例关系，又因BOOST环路带宽受右半平面零点限制，不能做到很大，因而环路的小信号响应速度不可能很快，Vo在重载跳变轻载的过程中上冲电压ΔVshoot会很大。
为了解决相关技术中的缺陷，请参阅图4，图4是本申请实施例提供的一种DCDC变换器的结构示意图，所述DCDC变换器包括：误差放大器EA、补偿网络、比较器CMP、峰值电流采样模块、功率管BG、斜波产生模块、驱动模块DRIVE，其中，
所述峰值电流采样模块的一端连接所述功率管BG的漏极、通过电感L接入输入电压Vin以及通过二极管D连接第一输出电压Vo，所述峰值电流采样模块的另一端接入斜波产生模块；
所述斜波产生模块的一端连接加法器ADD，以及另一端连接所述比较器CMP的负输入端(-)，所述加法器ADD还连接多个电流采样模块，每一电流采样模块对应的开关一端连接所述第一输出电压Vo，以及该开关的另一端输出对应的第二输出电压；
所述第一输出电压通过第一电阻R1、第二电阻R2进行分压，所述第一输出电压经过所述第一电阻的分压电压信号VFB接入所述误差放大器EA的负输入端(-)，所述误差放大器EA的正输入端(+)接入参考电压VREF，所述误差放大器EA的输出端通过所述补偿网络接入所述比较器CMP的正输入端(+)；
所述比较器CMP的输出端接入所述驱动模块DRIVE的一端，所述驱动模块DRIVE的另一端接入所述功率管BG的栅极，所述功率管BG的源极接地。
其中，假设有n个电流采样模块，n为大于1的整数，则不同的电流采样模块对应不同的开关，分别如下：电流采样模块对应S1，其对应的支路采样电流Ics1以及第二输出电压Vo1；电流采样模块对应S2，其对应的支路采样电流Ics2以及第二输出电压Vo2；…；电流采样模块对应Sn，其对应的支路采样电流Icsn以及第二输出电压Von。
其中，本申请实施例中，Vo1～Von每条支路都可以挂负载，即每一第二输出电压提供给一个相应的负载。Vo是总的电压输出，Vo1～Von是根据应用需求打开的输出电压支路，Vo一般不会单独挂负载，打开的支路一般都有负载，所以每条支路都可以挂负载。
本申请实施例中所述提及的DCDC变换器，能够避开输出环路带宽低的影响，对负载瞬态变化迅速反应。
可选的，所述输入电压Vin通过输入电容Ci接地，所述二极管D的输出端通过输出电容Co接地。
其中，输入电压Vin通过输入电容Ci接地，二极管D的输出端通过输出电容Co接地。
可选的，所述补偿网络包括：第一电容C0、第二电容C1和第三电阻Rcl；
所述误差放大器EA的输出端依次连接所述第三电阻Rcl和所述第二电容C1，所述第二电容C1接地；
所述误差放大器EA通过所述第一电容C0接地。
其中，C0、C1与Rc1构成补偿网络。
其中，所述DCDC变换器用于：
将所述多个电流采样模块中的每一路的输出电流采样信号进行叠加，得到总输出电流采样信号Ics；
将所述总输出电流采样信号Ics、所述峰值电流采样模块采样得到的峰值采样电流Ipk、 斜波补偿电流Islope以及直流电流信号Idc经过所述斜波产生模块，得到三角波信号Vramp。
其中，每个支路均有一个电流采样模块，采样支路S1～Sn的电流信号得到采样信号Ics1～Icsn，然后，可以将采样电流叠加，得到总输出电流采样信号Ics，该信号与峰值采样电流Ipk、斜波补偿电流Islope、直流电流信号Idc进入斜波产生模块，生成三角波信号Vramp。
具体的，如图4所示，图中LOOP2为输出电压环路，由输出电压Vo的分压信号VFB与基准电压VREF经过误差放大器EA后生成误差信号Vea，与三角波信号Vramp经过比较后得到占空比信号PWMON，然后驱动功率管BG得到稳定输出电压。为得到高精度的输出电压，LOOP2环路的增益较大，因而需要由C0、C1与Rc1构成的补偿网络保证其稳定性。图中LOOP1为输出电流环路，由每条支路采样电流Ics1～Icsn经过加法器ADD叠加后得到总的输出电流采样信号Ics，经过斜波产生模块后生成三角波信号Vramp，与误差信号Vea比较后得到占空比信号PWMON，然后驱动功率管BG得到稳定输出电压。由些可见，输出电流进入了LOOP1环路并参与控制输出电压，又此环路的增益较低，因而不需要额外的补偿网络，并且带宽很大，能够对输出电流的瞬间变化进行反应。
其中，本申请实施例中，LOOP2环路指输出电压环路。反馈信号来源于输出电压Vo，经过反馈分压、误差放大器、比较器、驱动模块后生成一定占空比的信号控制功率管的开通与关断，此条反馈路径即为环路LOOP2。其具体工作原理如下：当输出电压比设定电压偏高时，VFB增加，经过EA后误差信号Vea降低，与斜波信号比较后得到的占空比减小，从而功率管BG的开通时间减小，变换器为输出提供的能量降低，输出电压降低回归到设定电压；同理当输出电压比设定电压偏低时，VFB减小，经过EA后误差信号Vea会增加，比较得到的占空比增加，BG开通时间增加，变换器为输出提供的能量增加，从而使输出电压回归到正常值。
本申请实施例中，LOOP1环路指输出电流环路。反馈信号来源于输出电流Ics1～Icsn，经过电流叠加得到总的输出电流反馈信号Ics，然后进入到斜波产生模块、经过比较器、驱动模块后生成占空比控制功率管的开通与关断，此条反馈路径即为环路LOOP1。其具体工作原理如下：当S1～Sn支路突然导通(支路有负载)一路或多路时，Ics会增加，斜波模块产生的斜波信号直流值会减小，因而占空比会增加，BG开通时间会增加，变换器为输出提供的能量增加，因而输出不会出现大的下冲电压；同理，当S1～Sn突然关断一路或多路时，Ics会减小，斜波模块产生的斜波信号直流值会增加，因而通过比较器后占空比会减小，BG开通时间会减小，变换器为输出提供的能量太小，因而输出不会出现大的上冲电压。
本申请实施例中，LOOP1与LOOP2两条环路均可以调节占空比。由于输出电流模的LOOP1的增益很小，带宽很大，即调节速度非常快，也正因如此，才会对幅值变化较大的负载瞬态变化能快速反应，而在负载无瞬态变化时，负载电流的变化是很小的，低环路增益又不会将这个很小的值引入到占空比中，因而不会影响到高增益、低带宽的环路LOOP2，从而保证两条环路之间不相互影响，保证占空比不混乱，即保证稳定性。
可选的，所述DCDC变换器用于：
当所述多个电流采样模块对应的至少一个支路导通时，负载电流Iload会突然增加，且该至少一个支路对应的电流采样模块的输出电流采样信号也会迅速上升，经所述加法器ADD后的总输出电流采样信号Ics会迅速上升，进入到所述斜波产生模块后会迅速降低所述三角波信号Vramp的直流电平值。
具体实现中，当支路S1～Sn突然导通一路或多路时，负载电流Iload会突然增加，S1～Sn的电流采样模块输出Ics1～Icsn会对应导通支路迅速增加，经加法器ADD后的总的输出电流 采样信号Ics会迅速上升，进入到斜波产生模块后会迅速降低三角波Vramp的直流电平值，由于LOOP1环路速度远大于LOOP2，因而此时Vea基本还保持不变，三角波Vramp峰值上升到达Vea的值就需要更大的峰值电流，又电感电流上升速率不变，因而更大的峰值电流就意味着需要更长的BG开通时间，即占空比增加。占空比增加后电感电流也会增加，为负载提供的能量也会增加。由于负载电流瞬间变大是直接通过输出电流环路LOOP1反馈到Vramp增大占空比，而不再依赖于输出电压环路LOOP2，因而反应速度很快，输出电压Vo的下冲很小，从而，达到提升负载瞬态响应速度的目的。
可选的，所述DCDC变换器用于：
当所述多个电流采样模块对应的至少一个支路关断时，负载电流Iload会突然减小，且该至少一个支路对应的电流采样模块的输出电流采样信号也会迅速减小，经所述加法器ADD后的总输出电流采样信号Ics会迅速下降，进入到所述斜波产生模块后会迅速增加所述三角波信号Vramp的直流电平值。
具体实现中，当支路S1～Sn突然关断一路或多路时，负载电流Iload会突然减小，S1～Sn的电流采样模块输出Ics1～Icsn会对应导通支路迅速减小，经加法器ADD后的总的输出电流采样信号Ics会迅速下降，进入到斜波产生模块后会迅速增加三角波Vramp的直流电平值，由于LOOP1环路速度远大于LOOP2，因而此时Vea基本还保持不变，三角波Vramp峰值上升到达Vea的值就需要更小的峰值电流，又电感电流上升速率不变，因而更小的峰值电流就意味着需要更短的BG开通时间，即占空比减小。占空比减小后电感电流也会减小，为负载提供的能量也会减小。由于负载电流瞬间变小是直接通过输出电流环路LOOP1反馈到Vramp减小占空比，而不再依赖于输出电压环路LOOP2，因而反应速度很快，输出电压Vo的上冲也很小，从而，达到提升负载瞬态响应速度的目的。
可选的，如图5所示，所述斜波产生模块包括：第一PMOS管MP1、第二PMOS管MP2、第三PMOS管MP3、第四PMOS管MP4、第五PMOS管MP5、第六PMOS管MP6、第一NMOS管MN1和第二NMOS管MN2；
所述斜波补偿电流Islope接入所述第一PMOS管MP1的漏极和栅极，所述第一PMOS管的源极连接所述第二PMOS管MP2的源极、所述第三PMOS管MP3的源极、所述第四PMOS管MP4的源极、所述第五PMOS管MP5的源极、所述第六PMOS管MP6的源极，所述第一PMOS管MP1的栅极连接所述第二PMOS管MP2的栅极；
所述第二PMOS管MP2的漏极连接所述第四PMOS管MP4的漏极、所述第五PMOS管MP5的漏极、所述第二NMOS管MN2的漏极以及通过第四电阻R接地，所述第二PMOS管MP2的漏极还用于输出所述三角波信号Vramp；
所述峰值采样电流Ipk接入所述第三PMOS管MP3的栅极和漏极，所述第三PMOS管MP3的栅极连接所述第四PMOS管MP4的栅极；所述第四PMOS管MP4的漏极连接所述第二NMOS管MN2的漏极；
所述总输出电流采样信号Islope接入所述第一NMOS管MN1的栅极和漏极，所述第一NMOS管MN1的栅极连接所述第二NMOS管MN2的栅极，所述第一NMOS管MN1的源极、所述第二NMOS管MN2的源极均接地；
所述直流电流信号Idc接入所述第六PMOS管MP6的漏极和栅极，所述第六PMOS管MP6的栅极连接所述第五PMOS管MP5的栅极。
进一步的，其中，斜波产生模块的具体原理如下：
所述第一PMOS管与所述第二PMOS管构成电流镜，用于镜像所述斜波补偿电流；
所述第三PMOS管与所述第四PMOS管构成电流镜，用于镜像所述峰值采样电流；
所述第五PMOS管与所述第六PMOS管构成电流镜，用于镜像所述直流电流信号；
所述第一NMOS管与所述第二NMOS管构成电流镜，用于镜像总输出电流采样信号；
所述斜波补偿电流、所述峰值采样电流、所述直流电流信号以及所述总输出电流采样信号均流入所述第四电阻中，转换为所述三角波信号，该三角波信号满足如下关系：
Vramp＝(Islope+Ipk+Idc-Ics)×R
其中，Vramp表示三角波信号，Islope表示斜波补偿电流、Ipk表示峰值采样电流、Idc表示直流电流信号，Ics表示总输出电流采样信号，R表示第四电阻的阻值。
具体实现中，MP1与MP2构成电流镜，镜像斜波补偿电流Islope信号，MP3与MP4构成电流镜，镜像峰值采样电流Ipk，MP5与MP6构成电流镜，镜像直流电流信号Idc，MN1与MN2构成电流镜，镜像输出电流信号Ics，这些电流信号均流入电阻R中，转换为三角波信号Vramp，满足关系：
Vramp＝(Islope+Ipk+Idc-Ics)×R
可选的，在slope与Ipk均为逐周期变化的信号时，则按照如下公式确定Vramp的直流电压信号：
VDC＝(Idc-Ics)×R
其中，VDC表示Vramp的直流电压信号。
其中，Islope与Ipk均为逐周期变化的信号，假定Vramp的直流电压信号为VDC，那么：
VDC＝(Idc-Ics)×R
可以看出，当输出电流增加时，即Ics变大时，VDC会变小，即Vramp的直流部分会减小，反之，当输出电流减小时，Vramp的直流部分会增加。
具体实现中，如图6所示，图6为斜波产生模块波形图。其中，Ipk为BG开通时的峰值电流采样信号，因而在BG开通时为斜波信号，当BG关断时为0；Islope为斜波补偿信号，也是在BG开通时为斜波信号，BG关断时为0；Idc为直流电流信号，因而无论BG开通还是关断均不变；Ics为输出电流采样信号，当负载发生变化时会改变，特别是当S1～Sn支路导通或关断时会发生瞬时变化；Vramp为最终生成的斜波信号，可以看出，当Ics突然变大时，VDC会迅速降低，当Ics突然变小时，VDC会迅速增加。
为了更加清楚负载跳变过程中(典型的是S1～SN支路突然导通与关断过程)电路的工作原理，下面我们通过瞬态跳变的波形进一步分析。
进一步的，如图7所示，图7为本发明的DCDC变换器轻载跳变重载的波形图。由图中可以看出，在跳变之前，即负载为轻载时，Vramp的直流值VDC较高，这是因为此时输出电流采样信号Ico较小。当支路S1～Sn突然导通一路或多路时，负载电流Iload会突然增加，S1～Sn的电流采样模块输出Ics1～Icsn会对应导通支路迅速增加，经加法器ADD后的总的输出电流采样信号Ics会迅速上升，从而引起Vramp的直流电压值迅速降低，又Vea的反应速度很慢，因而Vramp峰值上升到Vea的时间增加了，即占空比增加，电感电流也增加。因为电感电流增加速度很快，所以很短的时间电感电流就会超过负载电流，输出电压就停止下降而缓慢上升，此后再由输出电压环路LOOP2将其调整到设定的电压值。重载稳定后，Vramp的直流值VDC较低，这是因为输出电流采样信号Ics较大。可以看出，负载由轻载跳变为重载的过程中，前半段输出电压下降的过程主要是由输出电流环路LOOP1来控制的，后半段输出电压上 升过程才是由输出电压环路LOOP2来控制的，因而相比于传统完全由LOOP2控制，其输出电压下冲ΔVdrop会减小很多。
进一步的，如图8所示，图8为本发明的DCDC变换器重载跳变轻载的波形图。由图中可以看出，在跳变之前，即负载为重载时，Vramp的直流值VDC较低，这是因为此时输出电流采样信号Ics较大。当支路S1～Sn突然关断一路或多路时，负载电流Iload会突然减小，S1～Sn的电流采样模块输出Ics1～Icsn会对应导通支路迅速减小，经加法器ADD后的总的输出电流采样信号Ics会迅速下降，从而引起Vramp的直流电压值迅速增加，又Vea的反应速度很慢，因而Vramp峰值上升到Vea的时间减小了，即占空比减小，电感电流也减小。因为电感电流减小速度很快，所以很短的时间电感电流就会低于负载电流，输出电压就停止上升而缓慢下降，此后再由输出电压环路LOOP2将其调整到设定的电压值。轻载稳定后，Vramp的直流值VDC较高，这是因为输出电流采样信号Ics较小。可以看出，负载由重载跳变为轻载的过程中，前半段输出电压上升的过程主要是由输出电流环路LOOP1来控制的，后半段输出电压下降过程才是由输出电压环路LOOP2来控制的，因而相比于传统完全由LOOP2控制，其输出电压上冲ΔVshoot会减小很多。
可以看出，本申请实施例中所描述的DCDC变换器，该DCDC变换器包括：误差放大器、补偿网络、比较器、峰值电流采样模块、功率管、斜波产生模块、驱动模块，其中，峰值电流采样模块的一端连接功率管的漏极、通过电感接入输入电压以及通过二极管连接第一输出电压，峰值电流采样模块的另一端接入斜波产生模块；斜波产生模块的一端连接加法器，以及另一端连接比较器的负输入端，加法器还连接多个电流采样模块，每一电流采样模块对应的开关一端连接第一输出电压，以及该开关的另一端输出对应的第二输出电压；第一输出电压通过第一电阻、第二电阻进行分压，第一输出电压经过第一电阻的分压电压信号接入误差放大器的负输入端，误差放大器的正输入端接入参考电压，误差放大器的输出端通过补偿网络接入比较器的正输入端；比较器的输出端接入驱动模块的一端，驱动模块的另一端接入功率管的栅极，功率管的源极接地，能够提升负载瞬态响应速度。
相关技术中，DCDC的负载瞬态响应性能差，主要是受制于输出环路带宽：对于BUCK变换器，输出环路带宽受制于开关频率，对于BOOST变换器，输出环路带宽同时受制于开关频率与右半平面堆零点。本申请实施例中，采样输出负载电流，并引入斜波信号Vramp中，为其建立一条输出电流环路，当负载电流变化时能够通过改变Vramp迅速调整占空比以稳定输出，不再需要通过输出电压环来进行缓慢调节，因而避免了输出环路带宽的限制，同时新加入的输出电流环路增益很小，不需要额外增加补偿网络来调节其稳定性，因而电路的环路设计复杂度也不会增加。
实际应用中，当支路S1～Sn突然导通一路或多路时，负载电流Iload会突然增加，S1～Sn的电流采样模块输出Ics1～Icsn会对应导通支路迅速增加，经加法器ADD后的总的输出电流采样信号Ics会迅速上升，进入到斜波产生模块后会迅速降低三角波Vramp的直流电平值，由于LOOP1环路速度远大于LOOP2，因而此时Vea基本还保持不变，三角波Vramp峰值上升到达Vea的值就需要更大的峰值电流，又电感电流上升速率不变，因而更大的峰值电流就意味着需要更长的BG开通时间，即占空比增加。占空比增加后电感电流也会增加，为负载提供的能量也会增加。由于负载电流瞬间变大是直接通过输出电流环路LOOP1反馈到Vramp增大占空比，而不再依赖于输出电压环路LOOP2，因而反应速度很快，输出电压Vo的下冲很小。当支路S1～Sn突然关断一路或多路时，负载电流Iload会突然减小，S1～Sn的电流采样模块输出Ics1～Icsn会对应导通支路迅速减小，经加法器ADD后的总的输出电流采样信号Ics 会迅速下降，进入到斜波产生模块后会迅速增加三角波Vramp的直流电平值，由于LOOP1环路速度远大于LOOP2，因而此时Vea基本还保持不变，三角波Vramp峰值上升到达Vea的值就需要更小的峰值电流，又电感电流上升速率不变，因而更小的峰值电流就意味着需要更短的BG开通时间，即占空比减小。占空比减小后电感电流也会减小，为负载提供的能量也会减小。由于负载电流瞬间变小是直接通过输出电流环路LOOP1反馈到Vramp减小占空比，而不再依赖于输出电压环路LOOP2，因而反应速度很快，输出电压Vo的上冲也很小，进而，能够提升负载瞬态响应速度。
本申请实施例中还提供一种开关电源，其可以包括上述任一DCDC变换器，通过该开关电源能够提升负载瞬态响应速度。
本申请实施例中还提供一种电子设备，其可以包括上述任一DCDC变换器或者开关电源，通过该电子设备能够提升负载瞬态响应速度。该电子设备可以包括以下至少一种：芯片、充电器、户外电源等等，在此不做限定。
以上是本申请实施例的实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请实施例原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (11)

  1. 一种DCDC变换器，其特征在于，所述DCDC变换器包括：误差放大器、补偿网络、比较器、峰值电流采样模块、功率管、斜波产生模块、驱动模块，其中，
    所述峰值电流采样模块的一端连接所述功率管的漏极、通过电感接入输入电压以及通过二极管连接第一输出电压，所述峰值电流采样模块的另一端接入所述斜波产生模块；
    所述斜波产生模块的一端连接加法器，以及另一端连接所述比较器的负输入端，所述加法器还连接多个电流采样模块，每一电流采样模块对应的开关一端连接所述第一输出电压，以及该开关的另一端输出对应的第二输出电压；
    所述第一输出电压通过第一电阻、第二电阻进行分压，所述第一输出电压经过所述第一电阻的分压电压信号接入所述误差放大器的负输入端，所述误差放大器的正输入端接入参考电压，所述误差放大器的输出端通过所述补偿网络接入所述比较器的正输入端；
    所述比较器的输出端接入所述驱动模块的一端，所述驱动模块的另一端接入所述功率管的栅极，所述功率管的源极接地。
  2. 根据权利要求1所述的DCDC变换器，其特征在于，所述输入电压通过输入电容接地，所述二极管的输出端通过输出电容接地。
  3. 根据权利要求2所述的DCDC变换器，其特征在于，所述补偿网络包括：第一电容、第二电容和第三电阻；
    所述误差放大器的输出端依次连接所述第三电阻和所述第二电容，所述第二电容接地；
    所述误差放大器通过所述第一电容接地。
  4. 根据权利要求1-3任一项所述的DCDC变换器，其特征在于，所述DCDC变换器用于：
    将所述多个电流采样模块中的每一路的输出电流采样信号进行叠加，得到总输出电流采样信号；
    将所述总输出电流采样信号、所述峰值电流采样模块采样得到的峰值采样电流、斜波补偿电流以及直流电流信号经过所述斜波产生模块，得到三角波信号。
  5. 根据权利要求4所述的DCDC变换器，其特征在于，所述DCDC变换器用于：
    当所述多个电流采样模块对应的至少一个支路导通时，负载电流会突然增加，且该至少一个支路对应的电流采样模块的输出电流采样信号也会迅速上升，经所述加法器后的总输出电流采样信号会迅速上升，进入到所述斜波产生模块后会迅速降低所述三角波信号的直流电平值。
  6. 根据权利要求4所述的DCDC变换器，其特征在于，所述DCDC变换器用于：
    当所述多个电流采样模块对应的至少一个支路关断时，负载电流会突然减小，且该至少一个支路对应的电流采样模块的输出电流采样信号也会迅速减小，经所述加法器后的总输出电流采样信号会迅速下降，进入到所述斜波产生模块后会迅速增加所述三角波信号的直流电平值。
  7. 根据权利要求4所述的DCDC变换器，其特征在于，所述斜波产生模块包括：第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第五PMOS管、第六PMOS管、第一NMOS管和第二NMOS管；
    所述斜波补偿电流接入所述第一PMOS管的漏极和栅极，所述第一PMOS管的源极连接所述第二PMOS管的源极、所述第三PMOS管的源极、所述第四PMOS管的源极、所述第五PMOS管的源极、所述第六PMOS管的源极，所述第一PMOS管的栅极连接所述第二PMOS管的栅极；
    所述第二PMOS管的漏极连接所述第四PMOS管的漏极、所述第五PMOS管的漏极、所述第二NMOS管的漏极以及通过第四电阻接地，所述第二PMOS管的漏极还用于输出所述三角波信号；
    所述峰值采样电流接入所述第三PMOS管的栅极和漏极，所述第三PMOS管的栅极连接所述第四PMOS管的栅极；所述第四PMOS管的漏极连接所述第二NMOS管的漏极；
    所述总输出电流采样信号接入所述第一NMOS管的栅极和漏极，所述第一NMOS管的栅极连接所述第二NMOS管的栅极，所述第一NMOS管的源极、所述第二NMOS管的源极均接地；
    所述直流电流信号接入所述第六PMOS管的漏极和栅极，所述第六PMOS管的栅极连接所述第五PMOS管的栅极。
  8. 根据权利要求7所述的DCDC变换器，其特征在于，
    所述第一PMOS管与所述第二PMOS管构成电流镜，用于镜像所述斜波补偿电流；
    所述第三PMOS管与所述第四PMOS管构成电流镜，用于镜像所述峰值采样电流；
    所述第五PMOS管与所述第六PMOS管构成电流镜，用于镜像所述直流电流信号；
    所述第一NMOS管与所述第二NMOS管构成电流镜，用于镜像总输出电流采样信号；
    所述斜波补偿电流、所述峰值采样电流、所述直流电流信号以及所述总输出电流采样信号均流入所述第四电阻中，转换为所述三角波信号，该三角波信号满足如下关系：
    Vramp＝(Islope+Ipk+Idc-Ics)×R
    其中，Vramp表示三角波信号，Islope表示斜波补偿电流、Ipk表示峰值采样电流、Idc表示直流电流信号，Ics表示总输出电流采样信号，R表示第四电阻的阻值。
  9. 根据权利要求8所述的DCDC变换器，其特征在于，
    在slope与Ipk均为逐周期变化的信号时，则按照如下公式确定Vramp的直流电压信号：
    VDC＝(Idc-Ics)×R
    其中，VDC表示Vramp的直流电压信号。
  10. 一种开关电源，其特征在于，所述开关电源包括如权利要求1-9任一项所述的DCDC变换器。
  11. 一种电子设备，其特征在于，所述电子设备包括如权利要求1-9任一项所述的DCDC变换器，或者，如权利要求10所述的开关电源。
PCT/CN2022/132136 2022-09-13 2022-11-16 Dcdc变换器、开关电源及电子设备 WO2024055408A1 (zh)

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