WO2024053135A1 - 高周波電源装置 - Google Patents

高周波電源装置 Download PDF

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Publication number
WO2024053135A1
WO2024053135A1 PCT/JP2023/008248 JP2023008248W WO2024053135A1 WO 2024053135 A1 WO2024053135 A1 WO 2024053135A1 JP 2023008248 W JP2023008248 W JP 2023008248W WO 2024053135 A1 WO2024053135 A1 WO 2024053135A1
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Prior art keywords
gate
high frequency
amplification
switching element
switching
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Ceased
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PCT/JP2023/008248
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English (en)
French (fr)
Japanese (ja)
Inventor
博史 國玉
卓矢 吉田
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Kyosan Electric Manufacturing Co Ltd
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Kyosan Electric Manufacturing Co Ltd
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Application filed by Kyosan Electric Manufacturing Co Ltd filed Critical Kyosan Electric Manufacturing Co Ltd
Priority to EP23862685.7A priority Critical patent/EP4586487A1/en
Priority to CN202380063640.4A priority patent/CN119836740A/zh
Priority to KR1020257008706A priority patent/KR20250061815A/ko
Priority to US19/109,776 priority patent/US20260081573A1/en
Publication of WO2024053135A1 publication Critical patent/WO2024053135A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/26—Push-pull amplifiers; Phase-splitters therefor
    • H03F3/265—Push-pull amplifiers; Phase-splitters therefor with field-effect transistors only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00—Generating plasma; Handling plasma
    • H05H1/24—Generating plasma
    • H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present invention relates to a high-frequency power supply device that outputs high-frequency waves by driving an amplifier element in a switching mode.
  • the high-frequency power supply device includes a high-frequency amplification section that amplifies the power of high-frequency waves using an amplification element and outputs the amplified power, and a gate drive section that applies a drive signal to the gate terminal of the amplification element of the high-frequency amplification section.
  • a MOSFET is known as an amplification element included in a high-frequency amplification section of a high-frequency power supply device.
  • Two types of MOSFETs are known: vertical MOSFETs (VDMOSFETs) and horizontal MOSFETs (LDMOSFETs).
  • VDMOSFETs Vertical MOSFETs
  • AC-DC switching power supplies and inverters due to their high breakdown voltage and large current characteristics. This switching operation is generally limited to a range of several tens of kHz to several tens of MHz. At higher frequencies, it is necessary to sacrifice the ON resistance due to the characteristics of the element.
  • lateral MOSFETs have the problem that it is difficult to achieve high breakdown voltage and low ON resistance, but on the other hand, they are characterized by low output capacitance C oss and small feedback capacitance C rss . Since the LDMOSFET has this low capacitance characteristic, it is an element suitable as an output control element of a high-frequency amplifier that requires high-frequency characteristics that can operate at very high speed.
  • LDMOSFETs are generally used in high-frequency linear amplifiers used in active operating regions such as class A amplifiers, class B amplifiers, class AB amplifiers, and class C amplifiers, and are used in switching mode class D amplifiers, class E amplifiers, and class F amplifiers. It is not used for switching purposes such as amplifiers.
  • a sinusoidal amplitude modulation signal is used as a gate signal, and a square wave signal for switching is not used.
  • a sinusoidal gate voltage V gs obtained by superimposing an alternating current voltage on a bias voltage is used.
  • the bias voltage the dead time DT and pulse width T on are determined by adjusting the reference level of the gate voltage V gs and comparing the level-adjusted gate voltage V gs with the threshold voltage V th .
  • FIG. 14 shows a configuration example of a conventional high frequency power supply device 100.
  • the high frequency power supply device 100 includes a high frequency amplifying section 110 and a gate driving section 120.
  • the high frequency amplification section 110 includes LDMOS1 and LDMOS2 as an LDMOSFET amplification element 111.
  • the gate driver 120 applies a gate signal to the gate terminals of LDMOS1 and LDMOS2.
  • LDMOS1 and LDMOS2 perform switching operations based on gate signals.
  • the gate drive circuit applies a sinusoidal gate voltage Vgs based on an AC voltage Vac of an AC power source to the gate terminals of the LDMOS1 and LDMOS2 in a manner superimposed on a bias voltage Vbias. Since the gate voltage V gs is shared by the gates of LDMOS1 and LDMOS2 from the AC power supply through the mutual inductance M g of the gate transformer, there is a problem that abnormal oscillation occurs during the off period of the LDMOSFET.
  • vertical VDMOSFETs satisfy the requirement (a) of switching the amplification element, but are capable of high-speed/high-frequency operation. Characteristic requirement (b) is not met.
  • As a solution to the requirement (b) of the high-speed/high-frequency operating characteristics of the amplifier element it is conceivable to use a horizontal LDMOSFET with low capacitance characteristics in place of the vertical VDMOSFET.
  • lateral LDMOSFETs do not satisfy requirement (a) for the switching operation of the amplifying element in the case of linear amplification that performs amplification operation using the active operating region of class A, B, and C amplifiers. .
  • horizontal LDMOSFETs have problems with the accuracy and reproducibility of adjusting the dead time DT and pulse width Ton in the switching operation using the sinusoidal gate voltage V gs in the gate drive section. Since it is stable, there is a problem in terms of requirement (c) for PWM control of the amplification element.
  • the dead time DT and the pulse width T on are determined by the threshold voltage V th and the gate voltage V gs of the amplification element. Therefore, the dead time DT and the pulse width T on are greatly influenced by the relationship between the threshold voltage V th . Since the threshold voltage V th varies depending on the characteristics of the elements constituting the gate driving section, the accuracy and reproducibility of adjusting the dead time DT and the pulse width T on are unstable. Therefore, in gate drive for driving a high frequency amplification element, it is difficult to perform PWM control by varying the pulse width of a gate signal using a sine wave.
  • the LDMOSFET amplification element is driven in the switching region (saturation region) as a configuration that satisfies the output requirements (a) and (b) of the high-frequency amplification section.
  • An amplifier has been proposed (see Patent Document 1).
  • the gate drive unit that performs PWM control that has been proposed in the past requires the accuracy of the dead time DT and pulse width T on of the rectangular wave (square wave) gate voltage V gs . There is a problem that reproducibility is insufficient.
  • a square wave gate that controls the amplification element of the LDMOSFET using PWM control is used. High accuracy and reproducibility are required for the signal dead time DT and pulse width Ton .
  • the gate drive unit proposed in Patent Document 2 proposes PWM control using a rectangular wave gate signal, but a PWM control IC using Bi-MOS (bipolar MOS) is used as a switching element constituting the gate drive unit. is used.
  • Bi-MOS bipolar MOS
  • Si-MOSFETs have individual differences in propagation delay from when the gate receives a control signal until the switching element turns on. For example, in conventional Si-MOSFETs, there is an individual difference of 1 [ns] to several [ns].
  • Patent Document 2 does not disclose a technical technique for performing PWM control at high output/high frequency.
  • the present invention solves the conventional problems described above, reduces individual differences in propagation delay of switching elements, and performs PWM control in a gate drive section of a high-frequency power supply device that outputs high-output/high-frequency radio waves.
  • the purpose of this invention is to improve precision and reproducibility by suppressing variations in dead time DT and pulse width T on of gate signals to be performed.
  • Another purpose is to improve high-speed response characteristics and suppress high-frequency resonance in a gate drive section of a high-frequency power supply device that outputs high-power/high-frequency radio waves.
  • the high frequency power supply device of the present invention includes a high frequency amplification section and a gate drive section.
  • the high frequency amplification section includes an amplification element, and performs high frequency amplification by a switching operation of the amplification element, and outputs high frequency output power.
  • the gate driving section includes a switching element, and a switching operation of the switching element inputs a gate signal to the gate terminal of the amplifying element of the high frequency amplifying section, and drives the amplifying element with the gate signal.
  • the present invention is a high frequency power supply device including a high frequency amplification section and a gate drive section, in which an LDMOSFET is used as the amplification element of the high frequency amplification section, and a GaNFET is used as a switching element of the gate drive section.
  • the GaNFET in the gate drive section generates a gate signal of a rectangular wave signal by a switching operation, and applies the generated gate signal to the gate terminal of the LDMOSFET in the high frequency amplification section to perform PWM control.
  • a high frequency wave with high output and high frequency is output.
  • GaNFET as the switching element of the gate drive section, individual differences in propagation delay of the switching element are reduced, and variations in the dead time DT and pulse width Ton of the gate signal for PWM control are suppressed, improving accuracy and reproducibility. improve sex.
  • the drain resistance ( R d ) to damp the resonant vibrations.
  • the drain resistance (R d ) damps vibrations caused by the LC circuit of the output parasitic capacitance C oss_GaN and the wiring inductance L 2 .
  • waveform distortion at the rise and fall of the rectangular waveform is reduced, and variations in the dead time DT and pulse width Ton of the gate signal are suppressed.
  • switching elements are required to have low resistance due to the requirement for highly efficient high frequency operation, but in the present invention, by adding a drain resistance (R d ) to a GaNFET with low resistance characteristics, LC resonance vibration can be suppressed. suppress.
  • the high frequency power supply device of the present invention requires a high frequency gate signal with a rectangular waveform in order to drive the amplification element of the high frequency amplification section at high frequency and under PWM control.
  • the gate drive section of the present invention has a configuration that enhances the high frequency response of the gate drive section in order to perform PWM control using a gate signal having a high frequency rectangular waveform. If the high frequency response of the gate driver is insufficient, the time constant becomes large at the rise and fall of the rectangular waveform of the gate signal, and the rise time/fall time becomes shorter than the pulse width of the rectangular wave signal. Waveform distortion phenomena occur due to a phenomenon in which the waveform becomes longer, a vibration phenomenon in which the waveform vibrates, and the like.
  • the present invention includes, in a gate drive section and a high frequency amplification section, features characteristic of (A) the electrical characteristics of the circuit elements and (B) the arrangement of the circuit elements as a structure for enhancing the high frequency responsiveness of the gate drive section.
  • (A) Electrical characteristics of circuit elements (a) Total gate charge (total gate charge) Q g As an electrical characteristic of a circuit element, there is a total gate charge (total gate charge amount) Q g of a switching element which is an active element of a gate drive section.
  • the present invention sets an upper limit value of the total gate charge Q g according to the switching frequency f sw of high-frequency switching operation, and uses a switching element having a total gate charge (total gate charge amount) Q g smaller than this upper limit value. .
  • the switching operation at the switching frequency f sw within the frequency range of the high frequency output is made faster.
  • the total gate charge (total gate charge amount) is also called by the name of the gate input charge amount. In the following, description will be made using the name of total gate charge (total gate charge amount).
  • LC resonant circuit of gate drive section In the gate drive section, an LC resonant circuit is formed by wiring inductance L and parasitic capacitance C of the switching element. If the resonant frequency f o of this LC resonant circuit is within the frequency range of the switching frequency f sw of the switching operation, it becomes a factor that causes waveform distortion in the waveform of the gate signal.
  • the high frequency power supply device of the present invention sets the resonant frequency of the LC resonant circuit to a frequency higher than the switching frequency fsw by limiting the wiring inductance, thereby reducing the influence of the resonance phenomenon.
  • the wiring inductance L1 is the inductance of the wiring that connects the switching element and the driving logic IC that applies a driving signal to the gate terminal of this switching element, and is the gate capacitance of the switching element.
  • An LC resonant circuit is configured with C iss_GaN . When the resonant frequency f o1 of the LC resonant circuit is within the frequency range of the switching frequency f sw of the switching operation, it becomes a factor that causes waveform distortion in the waveform of the gate signal.
  • the upper limit of the inductance value of the wiring inductance L1 is set so that the resonance frequency f o1 due to this LC resonance is higher than the switching frequency f sw of the high frequency switching operation.
  • the resonant frequency f o1 due to LC resonance becomes higher than the frequency range of the switching frequency f sw of the high-frequency switching operation.
  • the wiring length of the wiring is set so that the wiring inductance L1 is equal to or less than the upper limit value.
  • the wiring inductance L2 is the inductance of the wiring between the switching element and the bypass capacitor connected to the drain terminal of this switching element.
  • the wiring inductance L2 forms an LC resonant circuit with the output parasitic capacitance C oss_GaN of the switching element.
  • the bypass capacitor connected to the drain terminal reduces the alternating current impedance of the wiring to the ground potential (ground) and suppresses noise generated by the switching operation of the switching element from flowing into the power supply line.
  • the resonant frequency f o2 of the LC resonant circuit When the resonant frequency f o2 of the LC resonant circuit is within the frequency range of the switching frequency f sw of the switching operation, it becomes a factor that causes waveform distortion in the waveform of the gate signal.
  • the upper limit of the inductance value of the wiring inductance L2 is set so that the resonance frequency f o2 due to this LC resonance is higher than the switching frequency f sw of the high frequency switching operation.
  • the wiring length of the wiring is set so that the wiring inductance L2 is equal to or less than the upper limit value.
  • the resonance frequency f o2 due to LC resonance becomes higher than the frequency range of the switching frequency f sw of the high-frequency switching operation.
  • the switching frequency f sw of the switching operation is within the frequency range of high-frequency switching operation, the occurrence of the LC resonance phenomenon is suppressed, the waveform distortion phenomenon due to resonance vibration is suppressed, and the high frequency response is improved.
  • the wiring length of the wiring is set so that the wiring inductance L2 is equal to or less than the upper limit value.
  • the wiring inductance L3 is the inductance of the wiring between the source terminal of the switching element on the high side of the gate driving section and the gate terminal of the amplifying element.
  • the wiring inductance L3 forms an LC resonant circuit with the gate capacitance Ciss_LD of the amplification element.
  • the resonant frequency f o3 of the LC resonant circuit When the resonant frequency f o3 of the LC resonant circuit is within the frequency range of the switching frequency f sw of the switching operation, it becomes a factor that causes waveform distortion in the waveform of the gate signal.
  • the upper limit of the inductance value of the wiring inductance L3 is set so that the resonant frequency f o3 due to LC resonance is higher than the switching frequency f sw of the high frequency switching operation.
  • the wiring length of the wiring is set so that the wiring inductance L3 is equal to or less than the upper limit value.
  • the resonance frequency f o 3 due to LC resonance becomes higher than the frequency range of the switching frequency f sw of the high-frequency switching operation.
  • the switching frequency f sw of the switching operation is within the frequency range of high-frequency switching operation, the occurrence of the LC resonance phenomenon is suppressed, the waveform distortion phenomenon due to resonance vibration is suppressed, and the high frequency response is improved.
  • the wiring length of the wiring is set so that the wiring inductance L3 is equal to or less than the upper limit value.
  • the LDMOSFET in the high frequency amplification section has a built-in gate protection circuit to protect the gate.
  • the gate protection circuit is a circuit that prevents a negative reverse bias voltage from being applied in excess of the allowable voltage of the gate when a reverse voltage is applied when the LDMOSFET is used in the saturation region.
  • This protection circuit also has an allowable voltage range, and if the negative voltage applied from the gate driver exceeds the allowable voltage range of the gate protection circuit, there is a risk that the gate protection circuit will be destroyed.
  • the present invention includes a configuration that prevents the gate protection circuit from being destroyed by suppressing the negative voltage applied to the gate protection circuit within an allowable voltage range.
  • the gate drive section includes: (a) High-side switching element and low-side switching element connected in series (b) Series circuit of series resistor (R e ) and Zener diode (ZD) connected in parallel to DC power supply (V dd ) Equipped with
  • the series circuit of this series resistor (R e ) and Zener diode (ZD) is (c) The voltage across the series resistor (R e ) is applied as the drive voltage V H to the switching element on the high side, and the voltage across the Zener diode (ZD) is applied as the reverse bias voltage V L to the switching element on the low side. Apply as. (d) The drive voltage VH and the reverse bias voltage VL are set within the voltage range of the rated voltage of the protection circuit built into the high frequency amplification section.
  • the present invention inserts drain resistors (R dh , R dl ) on the drain side of the GaNFET.
  • the drain resistance (R dh , R dl ) a resistance value of about 0.5 [ohm] to 2 [ohm] is used, for example.
  • Gate resistance of amplification element (R g _LD)
  • R g _LD Gate resistance of amplification element
  • the switching element of the gate drive section includes a series circuit of a high-side switching element and a low-side switching element.
  • the wiring inductance L 3 between the connection point of the high-side and low-side switching elements and the gate terminal of the amplification element constitutes an LC resonant circuit together with the gate capacitance C iss_LD of the amplification element.
  • This resonance phenomenon of the LC resonant circuit causes waveform distortion such as ringing to occur in the waveform of the gate signal.
  • the gate resistor (R g _LD) of the present invention damps the resonance due to the LC resonant circuit.
  • the present invention includes the following first to sixth arrangements for the arrangement of circuit elements included in the gate drive section as a structure for improving the high frequency response of the gate drive section.
  • the first configuration and the second configuration are element arrangements that prevent electrical unevenness from occurring with respect to the reference potential, and the third configuration and the fourth configuration are element arrangements that enhance heat dissipation of the circuit elements.
  • the fifth configuration and the sixth configuration are element arrangements that shorten the path of the current loop.
  • the high-frequency amplification section is a push-pull circuit that connects the source terminals of two amplification elements to ground
  • the gate drive section is a push-pull circuit that connects the source terminals of two amplification elements to ground
  • the gate drive section includes each gate of the two amplification elements of the high-frequency amplification section. It includes two gate drive circuits that apply gate signals to the terminals.
  • the gate signal can be adjusted based on deviations from the reference potential, such as deviations in the dead time DT and pulse width Ton of the gate signal, and deviations in synchronization between both gate signals. The resulting deviation between the two gate signals is suppressed.
  • the second configuration related to circuit element arrangement has a radial arrangement as well as the line-symmetrical arrangement of the first structure.
  • a gate resistor (R g _GaN) is connected between the gate terminals of the high-side switching element and the low-side switching element included in each gate drive circuit and a drive logic IC that applies a drive signal to each gate terminal.
  • a series circuit is constructed. This series circuit of the driving logic IC and the gate resistor (R g _GaN) is arranged linearly with respect to the gate terminal and radially with respect to each switching element. The radial arrangement makes the wiring length and electrical length of each series circuit equal. This suppresses differences in wiring inductance due to different wiring lengths and deviations in delay times and the like due to different electrical lengths.
  • the third configuration related to circuit element arrangement is a configuration for cooling the circuit elements.
  • the gate driver includes an active element and a passive element. Passive elements such as bypass capacitors and resistive elements are placed on the surface layer of the substrate and are cooled by air cooling.
  • the active element of the GaNFET is disposed on the back side of the substrate and is cooled by a heat dissipation part that is contacted via a heat conductive member.
  • active elements and passive elements that generate different amounts of heat are arranged on opposite sides of the substrate.
  • passive elements with a small amount of heat on the surface of the board cooling by air is possible, and by placing active elements with a large amount of heat on the back side of the board, forced cooling by the heat dissipation part is possible. It is possible.
  • a water-cooled plate or fins can be used as the heat radiation part.
  • the fourth configuration related to circuit element arrangement is a configuration related to heat conduction and wiring inductance reduction.
  • the number of parallel elements (parallel number) and mounting pattern width of passive elements are such that their effective width is equal to or wider than the main body width of the amplification element of the high frequency amplification section. It is composed of
  • the effective width for reducing heat conduction and wiring inductance of passive elements is determined based on the number of passive elements arranged in parallel and the mounting pattern width. When this effective width is equal to or wider than the main body width of the amplification element of the high frequency amplification section, it is reflected in improved heat conduction efficiency from the passive elements and lower wiring inductance.
  • the fifth configuration related to circuit element arrangement is a configuration related to a current loop flowing between the gate drive section and the high frequency amplification section.
  • a conductive shield gasket is placed on the back surface directly below the gate resistor (R g _LD) on the surface layer side, with the substrate in between.
  • This conductive shield gasket becomes the ground potential (GND2) on the gate drive section side.
  • the source voltage of the amplification element becomes the ground potential (GND1) on the high frequency amplification section side.
  • the ground potential (GND2) on the gate drive section side and the ground potential (GND1) on the high frequency amplification section side are electrically connected via the heat dissipation section, and a current loop is formed between the gate drive section and the high frequency amplification section.
  • the sixth configuration related to circuit element arrangement is a configuration related to a current loop flowing between the gate drive section and the high frequency amplification section.
  • the switching element is disposed below the drain resistor (R d ) and the bypass capacitor with the substrate in between, and is electrically connected through a through hole provided in the substrate.
  • circuit elements such as the switching element, the drain resistor (R d ), and the bypass capacitor are arranged close to each other, thereby suppressing wiring inductance and shortening the electrical length of the current loop.
  • the present invention in the gate drive section of a high frequency power supply device that outputs high output/high frequency, individual differences in propagation delay of switching elements are reduced, and gate signals for PWM control are adjusted. Precision and reproducibility are improved by suppressing variations in dead time DT and pulse width Ton . Furthermore, high-speed response characteristics are improved and high-frequency resonance is suppressed in the gate drive section of a high-frequency power supply device that outputs high-output/high-frequency high-frequency waves.
  • FIG. 1 is a diagram for explaining the configuration of a high frequency power supply device of the present invention.
  • FIG. 3 is a diagram for explaining the operation of a gate driving section.
  • FIG. 3 is a diagram for explaining the operation of a gate driving section.
  • FIG. 3 is a diagram for explaining wiring inductance of a gate driving section.
  • FIG. 3 is a diagram for explaining protection of a gate protection circuit.
  • FIG. 3 is a diagram for explaining protection of a gate protection circuit.
  • FIG. 3 is a diagram for explaining protection of a gate protection circuit.
  • FIG. 3 is a diagram for explaining the arrangement of circuit elements.
  • FIG. 3 is a diagram for explaining the arrangement of circuit elements.
  • FIG. 3 is a diagram for explaining the arrangement of circuit elements.
  • FIG. 3 is a diagram for explaining the arrangement of circuit elements.
  • FIG. 3 is a diagram for explaining the arrangement of circuit elements.
  • FIG. 3 is a diagram for explaining the arrangement of circuit elements.
  • FIG. 3 is a diagram
  • FIG. 1 the configuration of the high frequency power supply device of the present invention will be explained using FIG. 1, the operation of the gate drive section will be explained using FIGS. 2 to 4, and the wiring inductance of the gate drive section will be explained using FIG.
  • the protection of the gate protection circuit will be explained using FIGS. 6 and 7, and the arrangement of circuit elements will be explained using FIGS. 8 to 13.
  • FIG. 1 is a diagram for explaining the configuration of a high frequency power supply device of the present invention.
  • the high frequency power supply device 1 of the present invention includes a high frequency amplifying section 10 and a gate driving section 20.
  • the high-frequency amplifying section 10 includes an amplifying element 11, and performs high-frequency amplification by switching operation of the amplifying element 11, and outputs high-frequency output power.
  • the gate drive section 20 includes a switching element 21.
  • the switching element 21 inputs the rectangular wave signal generated by the switching operation as a gate signal to the gate terminal (Gate) of the amplification element 11 of the high frequency amplification section 10, and drives the amplification element 11.
  • the high frequency amplification section 10 uses an LDMOSFET (horizontal MOSFET) as the amplification element 11, and the gate drive section 20 uses a GaNFET as the switching element 21.
  • the GaNFET of the gate drive section 20 generates a gate signal of a rectangular wave signal by a switching operation, and applies the generated gate signal to the gate terminal of the LDMOSFET of the high frequency amplification section 10 to perform PWM control.
  • a high-power/high-frequency high-frequency wave is output.
  • a GaNFET as the switching element 21 of the gate drive unit 20
  • individual differences in propagation delay of the switching element are reduced, and variations in the dead time DT and pulse width T on of the gate signal for PWM control are suppressed, thereby improving accuracy. and improve reproducibility.
  • the high frequency amplifying section 10 shown in FIG. 1 increases high frequency output by using two amplifying elements 11 in a push-pull configuration.
  • the amplifying elements 11 of LDMOS1 and LDMOS2 output drain-source voltages V ds1 and V ds2 that are in opposite phases to each other by switching operations that are in opposite phases to each other.
  • the parallel circuit of the inductance L O and the capacitance C O acts as a load impedance for the output circuit of the high frequency amplifier section 10, maximizing the gain of the amplification element at the resonant frequency and increasing the output of the drain-source voltages V ds1 and V ds2 .
  • the increased drain-source voltages V ds1 and V ds2 are outputted from an output terminal (OUTPUT) to a load via a transformer.
  • 50 [ohm] is connected as a load to perform impedance matching with the high frequency amplification section 10.
  • a gate resistor 12 (Rg_LD) is connected to the gate terminals of the amplifier elements 11 of LDMOS1 and LDMOS2.
  • the gate resistance 12 (R g _LD) is connected to the gate capacitance C iss _LD of the amplification element 11 , the source terminal of the high-side switching element 21 (QH1, QH2) of the gate drive section 20 , and the gate terminal of the amplification element 11 .
  • the resonant vibration of the LC resonant circuit formed by the wiring inductance L3 between the two is damped.
  • the gate drive section 20 includes a gate drive circuit 20A and a gate drive circuit 20B.
  • the gate drive circuit 20A is a circuit that applies a gate signal to the gate terminal of the amplification element 11 (LDMOS1)
  • the gate drive circuit 20B is a circuit that applies a gate signal to the gate terminal of the amplification element 11 (LDMOS2).
  • the gate drive circuit 20A is the circuit portion shown on the left
  • the gate drive circuit 20B is the circuit portion shown on the right.
  • the gate drive circuit 20A and the gate drive circuit 20B use the COM potential as a reference potential.
  • the source terminal of the switching element 21 (QH1) on the high side and the drain terminal of the switching element 21 (QL1) on the low side are connected to the drain resistance (R dl1 ), and the source terminal of the switching element 21 (QH1) on the high side is connected to the drain resistor (R dl1 ).
  • the source terminal is connected to the gate terminal of the amplification element 11 (LDMOS1) via the gate resistor 12 (R g _LD) of the high frequency amplification section 10 .
  • a drain terminal of the switching element 21 (QH1) is connected to the ground potential (GND2) via a drain resistor 26 (R dh1 ) and a bypass capacitor 24 (CH1).
  • the source terminal of the switching element 21 (QL1) is connected to the COM potential, and further connected to the ground potential (GND2) via the bypass capacitor 24 (CL1).
  • a power supply is configured by a parallel connection of a DC power supply 22 and a series circuit of a series resistor 27 (R e ) and a Zener diode 28 (ZD), and the midpoint of the series circuit is connected to the ground potential (GND2). connected to.
  • the DC power supply voltage V dd of the DC power supply 22 is divided into the drive voltage V H of the series resistor 27 (R e ) and the reverse bias voltage V L of the Zener diode 28 (ZD), and is applied to the high side switching element 21 (QH1). ) is applied with a positive driving voltage VH , and a negative reverse bias voltage VL is applied with the source terminal of the low-side switching element 21 (QL1).
  • the switching element 21 (QH1) applies a positive drive voltage VH as a gate signal to the gate terminal of the amplification element 11 (LDMOS1) when in the on state.
  • the low-side switching element 21 (QL1) applies a negative reverse bias voltage VL as a gate signal to the gate terminal of the amplification element 11 (LDMOS1) when in the on state.
  • a control signal is applied to the gate terminal of the switching element 21 (QH1) from the output terminal of the driving logic IC 23H, and the switching operation of the switching element 21 (QH1) is controlled. Further, a control signal is applied to the gate terminal of the switching element 21 (QL1) from the output terminal of the driving logic IC 23L, and the switching operation of the switching element 21 (QL1) is controlled.
  • These control signals become basic signals for PWM control of the high frequency amplification section.
  • the gate drive circuit 20B also has the same configuration as the gate drive circuit 20A.
  • the source terminal of the switching element 21 (QH2) on the high side and the switching element 21 (QL2) on the low side are connected to a drain resistor (R dl2 ), and the source terminal of the switching element 21 (QH2) is connected to the drain resistor (R dl2 ).
  • It is connected to the gate terminal of the amplification element 11 (LDMOS2) via the gate resistor 12 (R g _LD) of the high frequency amplification section 10 .
  • a drain terminal of the switching element 21 is connected to the ground potential (GND2) via a drain resistor 26 (R dh2 ) and a bypass capacitor 24 (CH2).
  • the source terminal of the switching element 21 is connected to the COM potential, and further connected to the ground potential (GND2) via the bypass capacitor 24 (CL2).
  • a positive driving voltage V H is applied to the drain side of the high-side switching element 21 (QH2), and a negative reverse bias voltage V L is applied to the source terminal side of the low-side switching element 21 (QL2). applied.
  • the switching element 21 applies a positive drive voltage VH as a gate signal to the gate terminal of the amplification element 11 (LDMOS2) when in the on state.
  • the low-side switching element 21 applies a negative reverse bias voltage VL as a gate signal to the gate terminal of the amplification element 11 (LDMOS2) when in the on state.
  • a control signal is applied to the gate terminal of the switching element 21 (QH2) from the output terminal of the driving logic IC 23H', and the switching operation of the switching element 21 (QH2) is controlled. Further, a control signal is applied to the gate terminal of the switching element 21 (QL2) from the output terminal of the driving logic IC 23L', and the switching operation of the switching element 21 (QL2) is controlled.
  • the control signal becomes a basic signal for PWM control of the high frequency amplification section.
  • the high frequency power supply device 1 in FIG. 1 is an example of a circuit with a push-pull configuration, it can also be applied to a single configuration.
  • a single configuration it is comprised of one amplification element 11 of the high frequency amplification section 10 in FIG. 1 and one gate drive circuit (20A or 20B) that drives this amplification element 11.
  • FIG. 2 shows the operation of the gate driving section 20 when turning on the amplification element 11 of the high frequency amplification section 10.
  • the solid line indicates the operating current of the gate drive circuit 20A
  • the broken line indicates the operating current of the gate drive circuit 20B. Note that 20A and 20B are not turned on at the same time, but operate alternately with a dead time DT in between.
  • gate drive circuit 20A In the gate drive circuit 20A, when the control signal causes the output of the drive logic IC 23H to become “high” and the output of the drive logic IC 23L to "low", the switching element 21 (QH1) is turned on, and the switching element 21 (QL1) is turned on. ) is in the off state. During this time, on the gate drive circuit 20B side, the switching element 21 (QH2) is turned off, and the switching element 21 (QL2) is turned on.
  • the switching element 21 (QH1) Since the drain resistor 26 (R dh1 ) connected in series to the drain terminal of the switching element 21 (QH1) is connected to the series resistor 27 (R e ), the switching element 21 (QH1) is turned on.
  • a driving voltage VH is applied from the source terminal of the switching element 21 (QH1) to the amplifying element 11 (LDMOS1) via the gate resistor 12 ( Rg_LD ), and the amplifying element 11 (LDMOS1) is turned on.
  • the source terminal of the switching element 21 (QH1) is connected to the gate resistor 12 (R g _LD) and the gate of the amplifying element 11 (LDMOS1).
  • the terminal is connected to the ground potential (GND1) on the high frequency amplification section 10 side via a path of the source terminal of the amplification element 11 (LDMOS1).
  • the drain terminal of the switching element 21 (QH1) is connected to the ground potential (GND2) on the gate drive unit 20 side via a path including the drain resistor 26 (R dh1 ) and the bypass capacitor 24 (CH1).
  • gate drive circuit 20B In the gate drive circuit 20B, when the control signal causes the output of the drive logic IC 23H' to go “high” and the output of the drive logic IC 23L' to go “low”, the switching element 21 (QH2) is turned on, and the switching element 21 ( QL2) is turned off. During this time, on the gate drive circuit 20A side, the switching element 21 (QL1) is turned on, and the switching element 21 (QH1) is turned off.
  • the switching element 21 (QH2) Since the drain resistor 26 (R dh2 ) connected in series to the drain terminal of the switching element 21 (QH2) is connected to the series resistor 27 (R e ), the switching element 21 (QH2) is turned on. , a driving voltage V H is applied from the source terminal of the switching element 21 (QH2) to the amplifying element 11 (LDMOS2) via the gate resistor 12 (R g _LD), and the amplifying element 11 (LDMOS2) is turned on.
  • the source terminal of the switching element 21 (QH2) is connected to the gate resistor 12 (R g _LD) and the gate of the amplifying element 11 (LDMOS2).
  • the terminal is connected to the ground potential (GND1) on the high frequency amplification section 10 side via a path of the source terminal of the amplification element 11 (LDMOS2).
  • the drain terminal of the switching element 21 (QH2) is connected to the ground potential (GND2) on the gate drive unit 20 side via a path including the drain resistor 26 (R dh2 ) and the bypass capacitor 24 (CH2).
  • FIG. 3 shows the operation of the gate driving section 20 when turning off the amplification element 11 of the high frequency amplification section 10.
  • the solid arrow indicates the voltage state of the gate drive circuit 20A
  • the broken line indicates the voltage state of the gate drive circuit 20B. Note that 20A and 20B may be turned off at the same time during dead time.
  • gate drive circuit 20A In the gate drive circuit 20A, when the output of the drive logic IC 23L becomes “high” and the output of the drive logic IC 23H becomes “low” due to the control signal, the switching element 21 (QL1) is turned on, and the switching element 21 (QH1) is turned on. is off.
  • the Zener diode 28 (ZD) Since the negative voltage side of the Zener diode 28 (ZD) is connected to the source terminal of the switching element 21 (QL1), when the switching element 21 (QL1) is turned on, the drain terminal of the switching element 21 (QL1) A reverse bias voltage V L is applied to the amplifying element 11 (LDMOS1) through the drain resistor 26 (R dl1 ) and the gate resistor 12 (R g _LD), and the amplifying element 11 (LDMOS1) is turned off.
  • the solid arrow indicates the reverse bias voltage VL applied to the amplification element 11 (LDMOS1).
  • the gate voltage V gs1 is applied to the gate terminal of the amplification element 11 (LDMOS1) via the path shown by the solid line in FIG.
  • gate drive circuit 20B In the gate drive circuit 20B, when the control signal causes the output of the drive logic IC 23L' to go “high” and the output of the drive logic IC 23H' to go “low”, the switching element 21 (QL2) is turned on, and the switching element 21 ( QH2) is turned off.
  • FIG. 2 shows LDMOS1 and LDMOS2 in an on state
  • FIG. 3 shows LDMOS1 and LDMOS2 in an off state.
  • the high frequency amplification section 10 outputs output power by turning on the LDMOS1 and the LDMOS2 in a complementary manner to each other. In mutually complementary on states, when LDMOS1 is on, LDMOS2 is off, and when LDMOS2 is on, LDMOS1 is off.
  • the high frequency amplification section 10 does not output power when LDMOS1 and LDMOS2 are in the off state. Further, even when the amplifying element 11 (LDMOS1, LDMOS2) is in the on state, the switching element 21 (QH1, QL1) included in the gate drive circuit 20A and the switching element 21 (QH2, QL2) included in the gate drive circuit 20B ) The high frequency amplifying section 10 may not operate normally depending on the combination of on states.
  • the high-frequency amplification unit 10 performs the following three combinations (c1) when the switching elements 21 (QH1, QL1) included in the gate drive circuit 20A and the switching elements 21 (QH2, QL2) included in the gate drive circuit 20B are in the on state. It operates in the operating states (c2) and (c3).
  • the combinations (c1) and (c2) are the case where the output voltage is output from the high frequency amplification section 10
  • the combination (c3) is the case where the output voltage is set to zero from the high frequency amplification section 10.
  • the first combination is an operating state in which the switching element 21 (QH1) of the gate drive circuit 20A and the switching element 21 (QL2) of the gate drive circuit 20B are both in the on state.
  • the switching element 21 (QH1) is turned on, which turns the amplifying element 11 (LDMOS1) on, and the switching element 21 (QL2) is turned on, which turns the amplifying element 11 (LDMOS2) is turned off. Due to this operating state, the drain-source voltage V ds1 of the amplification element 11 (LDMOS1) is output as an output voltage.
  • the second combination is an operating state in which the switching element 21 (QH2) of the gate drive circuit 20B and the switching element 21 (QL1) of the gate drive circuit 20A are both in the on state.
  • the switching element 21 (QH2) is turned on, so that the amplification element 11 (LDMOS2) is turned on, and the switching element 21 (QL1) is turned on, so that the amplification element 11 is turned on. (LDMOS1) is turned off. Due to this operating state, the drain-source voltage V ds2 of the amplification element 11 (LDMOS2) is output as an output voltage.
  • the third combination is an operating state in which the switching element 21 (QL1) of the gate drive circuit 20A and the switching element 21 (QL2) of the gate drive circuit 20B are both in the on state.
  • the switching element 21 (QL1) is turned on, which turns the amplifying element 11 (LDMOS1) off, and the switching element 21 (QL2) is turned on, which turns the amplifying element 11 (LDMOS2) is turned off. Due to this operating state, drain-source voltages V ds1 and V ds2 are not output from either the amplifying element 11 (LDMOS1) or the amplifying element 11 (LDMOS2).
  • FIG. 4 shows only the gate drive circuit 20A and shows the flow of a gate signal that drives the amplification element 11 (LDMOS).
  • FIG. 4 shows the wiring inductances L 1 , L 2 , L 3 , the gate capacitance (input parasitic capacitance) C iss _GaN, which is the parasitic capacitance of the GaNFET of the switching element 21 (QH, QL), and the output parasitic capacitance C oss _GaN. It shows.
  • the solid arrow shown in the figure indicates the gate current that turns on the amplification element 11 (LDMOS), and the broken line arrow shown in the figure shows the applied state of the voltage that turns the amplification element 11 (LDMOS) off. There is.
  • the driving logic IC 23H is connected to the gate terminal of the switching element 21H (QH) via a gate resistor 25H (R g _GaN), and performs a switching operation to turn on/off the switching element 21H (QH).
  • a gate resistor 25H R g _GaN
  • 5VCOM logic is used as the driving logic IC 23H.
  • the voltage of the driving logic IC 23H is converted into a current by the gate resistor 25H (R g _GaN), and is injected into the gate terminal of the switching element 21H (QH).
  • the drain terminal of the switching element 21H (QH) is connected to the positive voltage side of the series resistor 27 (R e ) via the drain resistor 26H (R dh ), and the source terminal side of the switching element 21H (QH) is connected to the gate resistor 12 ( It is connected to the gate terminal of the amplification element 11 (LDMOS) via Rg_LD ).
  • the conduction current of the switching element 21H flows from the source terminal through the gate resistor 12 (R g_LD ) to the amplification element 11 ( LDMOS), and switches the amplification element 11 (LDMOS1) to the on state.
  • the source terminal of the amplification element 11 (LDMOS1) is connected to the ground potential (GND1) on the high frequency amplification section 10 side, and further connected to the ground potential (GND2) on the gate drive side, so that the source terminal is connected to the ground potential (GND2) on the gate drive side.
  • a current path returning to the drain terminal of switching element 21H (QH) is formed.
  • the driving logic IC 23L is connected to the gate terminal of the switching element 21L (QL) via a gate resistor 25L (R g _GaN), and performs a switching operation to turn on/off the switching element 21L (QL).
  • a 5VCOM logic is used as the driving logic IC 23L.
  • the voltage of the driving logic IC 23L is converted into a current by the gate resistor 25L (R g _GaN), and is injected into the gate terminal of the switching element 21L (QL).
  • the source terminal of the switching element 21L (QL) is connected to the negative voltage side of the Zener diode 28 (ZD), and the drain terminal of the switching element 21L (QL) is connected to the switching element 21H (QH) via the drain resistor 26L (R dl ). ), and is connected to the gate terminal of the amplifying element 11 (LDMOS) via the gate resistor 12 (R g _LD).
  • the conduction of the switching element 21L (QL) causes the drain resistance 26L (R dl ) and the gate resistance 12 (R g _LD ) is applied to the gate terminal of the amplifying element 11 (LDMOS), and the amplifying element 11 (LDMOS) is switched to the OFF state.
  • the gate resistors 25H and 25L determine the gate current that charges the total gate charge Q g _GaN of the switching element 21 (QH, QL), and the gate resistor 12 (R g _LD) determines the gate current that charges the total gate charge Q g _GaN of the switching element 21 (QH, QL).
  • the bypass capacitors 24 reduce the alternating current impedance of the wiring to the ground potential (ground), thereby suppressing noise from the switching elements from flowing into the power supply line.
  • (C) Electrical Characteristics of Gate Driving Unit Improvement in high-speed response characteristics due to electrical characteristics in the gate driving unit 20 and high-frequency amplification unit 10 will be described using FIG. 5.
  • the total gate charge (total gate charge amount) Q g the electrical characteristics of the gate drive section 20 of the wiring inductances L 1 , L 2 , and L 3 that generate the LC resonant circuit, and the electrical characteristics of the gate drive unit 20 connected to the gate terminal of the amplifying element 11 will be explained.
  • the electrical characteristics of the high frequency amplification section 10 of the gate resistance (R g _LD) will be explained.
  • the high frequency power supply device of the present invention can speed up the switching operation using the switching frequency f sw within the frequency range of the high frequency output by limiting the upper limit of the total gate charge Q g of the switching element.
  • the total gate charge (total gate charge amount) Q g is the amount of charge injected into the gate necessary to drive the MOSFET. If the total gate charge Q g of the MOSFET is large, it takes a long time to charge the amount of charge necessary to turn on the MOSFET, and the switching operation becomes slow. Further, a dedicated IC is required for driving. On the other hand, if the total gate charge Qg of the MOSFET is small, the gate can be driven by a general-purpose logic IC. Furthermore, the switching operation becomes faster and switching operation at high frequency becomes possible.
  • the present invention reduces switching loss and speeds up the switching operation by using a GaNFET with a small total gate charge Q g as a switching element of a gate drive circuit.
  • the time width t sw of one period of a rectangular wave gate signal with a frequency of 100 [MHz] is 10 [ns].
  • the delay time td at the rise and fall has a large proportion compared to the time width of one cycle, waveform distortion will increase.
  • the ratio of the delay time t d to the time width t sw of one cycle of 10 [ns] is 1/10, the time for injecting charge into the gate terminal is 0.5 [ns]. is required.
  • the gate signal applied to the gate terminal of the GaNFET is supplied by the driving logic IC.
  • the output current of one driving logic IC is small, sufficient current to drive the GaNFET can be obtained by connecting a plurality of driving logic ICs in parallel.
  • the current fastest 5 [V] CMOS logic IC is 175 [MHz], so it has sufficient frequency characteristics as a driver IC that drives GaNFETs for 27 [MHz] to 100 [MHz]. There is.
  • the wiring inductance L1 is the inductance of a wiring that connects a switching element and a driving logic IC that applies a driving signal to a gate terminal of this switching element.
  • the wiring inductance L1 forms an LC resonant circuit LC1 with the gate capacitance Ciss_GaN of the switching element. If the resonant frequency f o1 of the LC resonant circuit LC1 is within the frequency range of the switching frequency f sw of the switching operation, it becomes a factor that causes waveform distortion (attenuation) in the waveform of the gate signal.
  • the upper limit value of the inductance value of the wiring inductance L1 is set so that the resonance frequency f o1 due to LC resonance is higher than the switching frequency f sw of the high frequency switching operation.
  • the wiring length of the wiring is set so that the wiring inductance L1 is equal to or less than the upper limit value.
  • the resonant frequency f o1 due to LC resonance becomes higher than the frequency range of the switching frequency f sw of the high-frequency switching operation.
  • the switching frequency f sw of the switching operation is within the frequency range of high-frequency switching operation, the occurrence of the LC resonance phenomenon is suppressed, the waveform distortion (attenuation) phenomenon due to resonance vibration is suppressed, and the high frequency response is improved.
  • the wiring inductance L1 of the wiring between the gate terminal of the switching element and the driving logic IC changes depending on the wiring length.
  • An LC resonant circuit is configured between this wiring inductance L1 and the gate capacitance Ciss_GaN of the switching element.
  • resonant frequency fo of an LC resonant circuit is expressed by the following equation (1).
  • f o (1/2 ⁇ ) ⁇ 1/(L ⁇ C) 1/2 ⁇ ...(1)
  • the resonant frequency f o in equation (1) is expressed as f o1
  • the resonant frequency f o1 is proportional to ⁇ 1/(L ⁇ C) 1/2 ⁇ and inversely proportional to L 1/2 .
  • the upper limit of the inductance value of the wiring inductance L1 is set, and the inductance value of the wiring inductance L1 is set to be an inductance value less than or equal to the upper limit value in the frequency range of the switching frequency fsw , and the resonant frequency f o1 is The frequency is set to be higher than the switching frequency fsw at which the operation is performed.
  • the frequency range of the switching frequency fsw that drives the amplification element 11 becomes a frequency lower than the resonance frequency fo1 , so the occurrence of LC resonance is suppressed, the waveform distortion (attenuation) phenomenon due to resonance vibration is suppressed, and the high frequency Responsiveness is improved.
  • the gate capacitance C iss _GaN of the GaNFET is generally about 200 [pF], so if the resonance frequency f o1 is set to, for example, 140 [MHz], the wiring inductance L 1 is 6 [nH]. Furthermore, when the switching frequency f sw of the switching operation is 100 [MHz], which is the upper limit frequency of the frequency band, the wiring inductance L 1 at which the resonance phenomenon occurs is 12 [nH], but the upper limit of the wiring inductance L 1 is 12 [nH]. is limited to 6 [nH], so no resonance phenomenon occurs at the switching frequency fsw .
  • the wiring inductance L 1 As described above, by limiting the wiring inductance L 1 to 6 [nH] or less, when driving the amplification element 11 with a gate signal of 140 [MHz] or less, the occurrence of resonance vibration is suppressed, In the frequency range from [MHz] to 100 [MHz], a low distortion square wave high frequency output is obtained. Since there is a positive increase/decrease relationship between the wiring inductance L and the wiring length, the wiring length of the wiring inductance L1 is set to be shorter than the wiring length corresponding to the upper limit value.
  • the wiring inductance L2 is the wiring inductance of the wiring between the switching element and the bypass capacitor connected to the drain terminal of this switching element.
  • the wiring inductance L2 forms an LC resonant circuit LC2 with the output parasitic capacitance C oss_GaN of the switching element.
  • bypass capacitor connected to the drain terminal reduces the alternating current impedance of the wiring to the ground potential (ground), and suppresses noise generated by the switching operation of the switching element from flowing into the power supply line.
  • the resonant frequency f o2 of the LC resonant circuit LC2 is within the frequency range of the switching frequency f sw of the switching operation, it becomes a factor that causes waveform distortion (attenuation) in the waveform of the gate signal applied to the LDMOS.
  • the upper limit value of the inductance value of the wiring inductance L 2 is set so that the resonance frequency f o2 due to LC resonance is higher than the switching frequency f sw of the high-frequency switching operation.
  • the wiring length of the wiring is set so that the wiring inductance L2 is equal to or less than the upper limit value.
  • the resonance frequency f o2 due to LC resonance becomes a frequency higher than the frequency range of the switching frequency f sw of the high-frequency switching operation.
  • the switching frequency f sw of the switching operation is within the frequency range of high-frequency switching operations, the occurrence of the LC resonance phenomenon is suppressed, the waveform distortion (attenuation) phenomenon due to resonance vibration is suppressed, and the high-frequency response is improved.
  • the wiring inductance L2 of the wiring between the drain terminal of the switching element and the bypass capacitor connected to the drain terminal of the switching element changes depending on the wiring length.
  • An LC resonant circuit LC2 is configured between this wiring inductance L2 and the output parasitic capacitance C oss_GaN of the switching element.
  • the resonant frequency f o of the LC resonant circuit is expressed by the above equation (1).
  • L is the wiring inductance L2
  • C is the output parasitic capacitance C oss_GaN .
  • the resonant frequency f o in equation (1) is expressed as f o2
  • the resonant frequency f o2 is proportional to ⁇ 1/(L ⁇ C) 1/2 ⁇ and inversely proportional to L 1/2 .
  • the inductance value of the wiring inductance L2 is set to be an inductance value below the upper limit value in the frequency range of the switching frequency fsw , and the resonant frequency f o2 is set to be a higher frequency than the switching frequency f sw at which the switching operation is performed.
  • the frequency range of the switching frequency f sw that drives the amplification element 11 becomes a frequency lower than the resonance frequency f o2 , so the occurrence of LC resonance is suppressed, the waveform distortion (attenuation) phenomenon due to resonance vibration is suppressed, and the high frequency Responsiveness is improved.
  • the wiring inductance L 2 is 4 [nH]. becomes. Furthermore, when the switching frequency f sw of the switching operation is 100 [MHz], which is the upper limit frequency of the frequency band, the wiring inductance L 2 at which the resonance phenomenon occurs is 8 [nH], but the upper limit of the wiring inductance L 2 is limited to 4 [nH], so no resonance phenomenon occurs at the switching frequency fsw .
  • the wiring length of the wiring inductance L2 is set to be shorter than the wiring length corresponding to the upper limit value.
  • the wiring inductance L 2 is limited by the number of parallel connections (parallel number) and mounting pattern width of the bypass capacitors 24H (CH), 24L ( CL ), drain resistors 26H (R dh ), 26L (R dl ), and the mounting pattern width of the switching element 21H. , 21L (GaNFET) by setting the width to be equal to or wider than the main body width.
  • the wiring inductance L 3 is the wiring inductance of the wiring between the source terminal of the high-side switching element of the gate driving section 20 and the gate terminal of the amplification element 11 of the high-frequency amplification section 10 .
  • the wiring inductance L3 forms an LC resonant circuit LC3 with the gate capacitance Ciss_LD of the amplifying element 11. Since the source terminal of the high-side switching element and the drain terminal of the low-side switching element are connected, the LC resonant circuit LC3 is also connected to the drain terminal of the low-side switching element.
  • the resonant frequency f o3 of the LC resonant circuit LC3 is within the frequency range of the switching frequency f w of the switching operation, it becomes a factor that causes waveform distortion (attenuation) in the waveform of the gate signal.
  • the upper limit of the inductance value of the wiring inductance L3 is set so that the resonant frequency f o3 due to LC resonance is higher than the switching frequency f sw of the high frequency switching operation.
  • the wiring length of the wiring is set so that the wiring inductance L3 is equal to or less than the upper limit value.
  • the resonance frequency f o 3 due to LC resonance becomes a frequency higher than the frequency range of the switching frequency f sw of the high-frequency switching operation.
  • the switching frequency f sw of the switching operation is within the frequency range of high-frequency switching operation, the occurrence of the LC resonance phenomenon is suppressed, the waveform distortion (attenuation) phenomenon due to resonance vibration is suppressed, and the high-frequency response is improved.
  • the wiring inductance L3 of the wiring between the source terminal of the switching element on the high side of the gate driving section 20 and the gate terminal of the amplification element 11 changes depending on the wiring length.
  • An LC resonant circuit LC3 is configured between this wiring inductance L3 and the gate capacitance Ciss_LD of the amplification element 11.
  • the resonant frequency f o of the LC resonant circuit is expressed by the above equation (1).
  • L is the wiring inductance L3
  • C is the gate capacitance Ciss_LD .
  • the upper limit value of the inductance value of the wiring inductance L3 is set, and the inductance value of the wiring inductance L3 is set to be an inductance value below the upper limit value in the frequency range of the switching frequency fsw , and the resonant frequency f o3 is The frequency is set to be higher than the switching frequency fsw at which the operation is performed. Since the frequency range of the switching frequency fsw that drives the amplification element 11 is lower than the resonance frequency fo3 , the occurrence of LC resonance is suppressed, the waveform distortion phenomenon due to resonance vibration is suppressed, and high frequency responsiveness is improved. .
  • the wiring length is set to be shorter than the wiring length corresponding to the upper limit value of the wiring inductance L3 .
  • switching elements 21H, 21L (QH, QL), bypass capacitors 24H, 24L (CH, CL), gate resistance 12 (R g _LD), drain resistance R d (R dh , R dl ) is placed in the immediate vicinity of the gate terminal of the amplification element 11 (LDMOS1, LDMOS2), for example within 25 [mm], and the gate resistor 12 (R g _LD) of the amplification element 11 (LDMOS1, LDMOS2) is arranged in parallel.
  • the number of connections (parameter number) and the mounting pattern width are set to a size that is equal to or larger than the width of the electrode of the gate resistor 12 (R g _LD) of the amplification element 11 (LDMOS1, LDMOS2).
  • a ground potential (GND2) is placed on the back side of the substrate 30 directly under the gate resistor 12 (R g _LD) provided on the front side of the substrate 30, and a conductive shield gasket 29 and the like are placed.
  • the configuration is such that the amplification elements 11 (LDMOS1, LDMOS2) are connected via the heat dissipation section 31 of the ground potential (GND1) on the source terminal side.
  • the shield gasket 29 used is one that is equal to or wider than the gate terminal of the amplification element 11 (LDMOS1, LDMOS2). Note that the symbols 29, 30, and 31 of the shield gasket 29, the substrate 30, and the heat radiation section 31 are shown in FIGS. 8 to 10.
  • the source terminals of the switching elements 21H, 21L are connected to the gate terminals of the amplification elements 11 (LDMOS1, LDMOS2) through the wiring with wiring inductance L3 and the gate resistor 12 ( Rg_LD ).
  • the diameter of the current loop which is connected to the source terminal of the amplifier element 11 (LDMOS1, LDMOS2) and connected to the ground potential (GND1) and the ground potential (GND2), is 10 [mm] or less when viewed from the cross-sectional direction. Thereby, the wiring inductance L3 is reduced. This point will be explained in the current loop below.
  • the LDMOSFET of the high frequency amplification section is provided with a gate protection circuit to protect the gate.
  • the gate protection circuit is a circuit that prevents a negative reverse bias voltage exceeding an allowable voltage from being applied to the gate when a reverse voltage is applied when the LDMOSFET is used in a saturation region.
  • a gate protection circuit a structure built in a high frequency amplification section is known.
  • FIG. 6(a) shows a circuit example of the gate protection circuit 13
  • FIG. 6(b) shows the protection voltage range of the gate protection circuit.
  • the protection circuit is a circuit that protects a semiconductor element from electrostatic discharge (ESD) caused by external static electricity.
  • the circuit example of the gate protection circuit 13 shown in FIG. 6(a) includes first npn-type bipolar transistors Q1 and Q2 whose base terminals are connected to a resistor, and an n-type first bipolar transistor whose gate terminal is connected to a source terminal. It consists of two MOS transistors M1 and M2.
  • the first bipolar transistors Q1 and Q2 operate as reverse biased diodes due to collector-emitter conduction due to collector-base leakage current.
  • the second MOS transistors M1 and M2 operate as diodes biased in the opposite direction by a parasitic diode.
  • the series circuit of the first bipolar transistor Q1 and the second MOS transistor M2 constitutes a first protection circuit when a positive voltage is applied to Gate
  • the series circuit of the first bipolar transistor Q2 and the second MOS transistor M1 constitutes a first protection circuit when a positive voltage is applied to Gate.
  • This constitutes a second protection circuit when a negative voltage is applied to the terminal.
  • the sum of the breakdown voltage of the first bipolar transistor Q1 and the breakdown voltage of the second MOS transistor M2 becomes the breakdown voltage of the gate protection circuit against positive voltage
  • the breakdown voltage of the first bipolar transistor Q2 and the breakdown voltage of the second MOS transistor M1 are the breakdown voltage of the gate protection circuit against positive voltage.
  • the sum with the down voltage becomes the breakdown voltage of the gate protection circuit against negative voltage.
  • the gate protection circuit has a permissible voltage range, and if the negative voltage supplied from the gate driver for reverse voltage application exceeds the permissible voltage range of the gate protection circuit, there is a risk that the gate protection circuit will be destroyed.
  • Drain resistance (R dh , R dl ) In order to suppress this resonance phenomenon, the present invention inserts a drain resistor 26 (R dh , R dl ) on the drain side of the GaNFET.
  • a drain resistor 26 (R dh , R dl ) As the drain resistance 26 (R dh , R dl ), a resistance value of about 0.5 [ohm] to 2 [ohm] is used, for example.
  • Si-MOSFETs are generally used as switching elements, and their ON resistance is relatively large at 0.5 [ohm] or more. , the possibility of resonance phenomena occurring is low.
  • the ON resistance of the GaNFET is low;
  • the resonance between the wiring inductance L 2 and the output parasitic capacitance C oss _GaN of the GaNFET is hardly attenuated.
  • the present invention includes drain resistors (R dh , R dl ).
  • FIG. 7 shows the gate voltage V gs applied to the gate of the amplification element 11 (LDMOS), and FIG. 7(a) shows the gate voltage V gs when there is no drain resistance 26 (R dh , R dl ), FIG. 7B shows the gate voltage V gs when the drain resistance 26 (R dh , R dl ) is present.
  • the rectangular waveform of S1 represented by a broken line indicates the ideal gate voltage V gs
  • the waveform of S2 represented by a solid line schematically represents the gate voltage V gs . Shows the actual signal waveform.
  • the broken line indicated by S3 indicates the reverse withstand voltage of the gate protection circuit. Note that each waveform shape is shown schematically and does not represent an actual waveform shape.
  • the present invention includes a configuration that prevents destruction of the gate protection circuit by suppressing the negative voltage applied to the gate protection circuit within an allowable voltage range.
  • the drive voltage V H and reverse bias voltage V L applied to the GaNFET are set within the rated voltage of the gate protection circuit.
  • the gate drive unit 20 has a DC power supply 22 (V dd ), a series resistor 27 (R e ) connected in parallel to the DC power supply 22, and a Zener diode 28 (ZD) as a power supply configuration. ) and a series circuit.
  • This series circuit of the series resistor 27 (R e ) and the Zener diode 28 (ZD) applies the voltage across the series resistor 27 (R e ) to the high-side switching element 21 (QH) as a drive voltage V H.
  • the voltage across the Zener diode 28 (ZD) is applied as a reverse bias voltage VL to the low-side switching element 21 (QL).
  • Gate resistance of amplification element (b5) Gate resistance of amplification element (R g _LD) One of the electrical characteristics of the high frequency amplification section 10 is a gate resistance (R g _LD) connected to the gate terminal of the amplification element 11 .
  • the switching element of the gate drive unit 20 includes a high-side switching element and a low-side switching element connected in series.
  • This resonance phenomenon of the LC resonance circuit LC3 causes waveform distortion such as ringing to occur in the waveform of the gate signal.
  • the gate resistor (R g _LD) of the present invention attenuates the resonance caused by the LC resonant circuit LC3.
  • the present invention attenuates the amplitude of vibration caused by the LC resonance circuit by connecting a gate resistor (R g _LD) between the output terminal of the switching element 21 of the gate drive unit 20 and the gate terminal of the amplifying element 11. Ringing within the turn- on time ton when the gate signal rises is suppressed.
  • R g _LD gate resistor
  • the gate resistance (R g _LD) By setting the gate resistance (R g _LD) to a predetermined value, the amplitude of vibration caused by the LC resonant circuit LC3 is attenuated, and ringing within the on time when the gate signal rises is suppressed.
  • FIG. 8 shows a planar arrangement
  • FIG. 9 shows a cross-sectional arrangement at a position indicated by broken line aa in FIG. 8
  • FIG. 10 is a perspective view of a portion of the high-frequency power supply device.
  • FIG. 11 shows current loops on the arrangement of circuit elements.
  • FIG. 12 shows a line-symmetric arrangement and a radial arrangement of circuit elements.
  • the high-frequency amplification section connects the source terminals of two amplification elements to ground to form a push-pull circuit
  • the gate drive section connects each of the two amplification elements of the high-frequency amplification section to the ground.
  • Two gate drive circuits are provided that apply gate signals to gate terminals.
  • FIG. 8 (a) Line-symmetric arrangement of circuit elements
  • two gate drive circuits 20A and 20B with the same circuit configuration constitute a push-pull circuit
  • the circuit elements with the same function constituting the gate drive circuits 20A and 20B are COM. They are arranged symmetrically with respect to the axis of symmetry passing through the potential.
  • a dashed-dotted line bb indicates a line of symmetry.
  • the amplification element 11 (LDMOS 1) of the high frequency amplification section and the gate drive circuit 20A of the gate drive section are arranged, and on the other side of the symmetry line bb On the side (right side in the figure), the amplification element 11 (LDMOS2) of the high frequency amplification section and the gate drive circuit 20B of the gate drive section are arranged.
  • the gate drive circuit 20A includes bypass capacitors 24 (CH1) and 24 (CL1), and a drain resistor 26L (R ) is arranged, and a gate resistor 12 (R g _LD) connected to the gate terminal of the amplification element 11 (LDMOS1) is arranged.
  • switching elements 21 (QH1) and 21 (QL1) and a drain resistor 26H (R dh1 ) are arranged on the back side of the substrate 30, and a conductive shield gasket is placed below the gate resistor 12 (R g_LD ). 29 is placed.
  • the gate drive circuit 20B includes bypass capacitors 24 (CH2) and 24 (CL2), and a drain resistor 26L (R dl2 ) is arranged, and a gate resistor 12 (R g _LD) connected to the gate terminal of the amplifying element 11 (LDMOS2) is arranged.
  • switching elements 21 (QH2) and 21 (QL2) and a drain resistor 26H (R dh2 ) are arranged on the back side of the substrate 30, and a conductive shield gasket is placed below the gate resistor 12 (R g_LD ). 29 is placed.
  • circuit elements having the same function are arranged at equal distances with respect to the line of symmetry bb, and a line-symmetrical arrangement is performed. .
  • each circuit element of the two gate drive circuits is electrically symmetrically arranged with the COM potential as a reference potential.
  • the gate signal is susceptible to deviations from the reference potential, such as deviations in the dead time DT and pulse width Ton of the gate signal, and deviations in synchronization between both gate signals. The deviation between the two gate signals generated based on this is suppressed.
  • FIG. 9 schematically shows a cross section taken along the dashed line aa in FIG. 8.
  • the gate terminal of the amplification element 11 (LDMOS) is connected to the gate resistor 12 (R g _LD), and the source terminal is placed in contact with the heat dissipation section 31 as the ground potential (GND1) on the high frequency amplification section side. be done.
  • the conductive shield gasket 29 placed on the back side of the substrate 30 is placed in contact with the heat dissipation section 31 as a ground potential (GND2) on the gate drive section side.
  • the switching element 21 GaNFET (QH, QL)
  • the heat dissipation section 31 is a conductive metal member having a heat dissipation function, such as a water cooling plate or a fin, and has conductivity to electrically connect between the ground potential (GND1) and the ground potential (GND2).
  • bypass capacitors 24 CH, CL
  • drain resistors 26 R dh , R dl
  • switching elements 21 QH, QL
  • FIG. 10 shows a part of the high frequency power supply device in a perspective view.
  • a bypass capacitor 24 (CH1) and a gate resistor 12 (Rg_LD) are arranged on the front side of the substrate 30, and a switching element 21 (GaNFET (QH1)) and a switching element 21 (GaNFET (QH1)) are arranged at a lower position on the back side.
  • a gate resistor 25 (Rg_GaN) connected to QH1)) is arranged.
  • the switching element 21 (GaNFET (QH1)) is connected to a driving logic IC 23 via a gate resistor 25 (Rg_GaN).
  • the driving logic IC 23 may be arranged on the back side of the substrate 30 or may also be arranged on the front side with the substrate 30 interposed therebetween. By arranging two driving logic ICs 23 on both the front and back sides of the substrate 30 as indicated by broken lines, it is possible to increase the current supplied to the switching element 21 (GaNFET (QH1)).
  • the bypass capacitor 24 (CH1) disposed on the front surface with the substrate 30 in between and the conductive shield gasket 29 disposed on the back surface can be connected through a through hole in the substrate 30.
  • the drain resistor 26 (R dh1 ) and the switching element 21 (GaNFET (QH1)) arranged on the back surface, which are arranged on the back surface with the substrate 30 in between, and the bypass capacitor 24 (CH1) arranged on the front surface. can be connected through the through holes of the substrate 30.
  • active elements and passive elements that generate different amounts of heat By arranging active elements and passive elements that generate different amounts of heat on opposite sides of the substrate, and arranging the passive elements that generate less heat on the front side of the substrate, air cooling is possible.
  • active elements that generate a large amount of heat are placed on the back side of the substrate and are forcibly cooled by the heat dissipation section.
  • a water-cooled plate or fins can be used as the heat radiation part.
  • the effective width of heat conduction of passive elements depends on the number of passive elements connected in parallel and the mounting pattern width. By making the effective width of this passive element equal to or wider than the main body width of the amplification element of the high frequency amplification section, mutual heat conduction efficiency is improved and thermal non-uniformity is eliminated. Furthermore, the wide effective width of the passive element contributes to reducing wiring inductance.
  • FIG. 11 is a diagram for explaining the current loop of the drive current.
  • FIG. 11(a) shows the current loop using the circuit diagram of FIG. 4
  • FIG. 11(b) shows the current loop using the circuit diagram of FIG. 9. Shows current loop.
  • the gate current that drives the gate of the amplification element 11 flows from the source terminal of the switching element 21H (QH) to the gate resistor 12. (R g _LD) is applied to the gate terminal of the amplification element 11 (LDMOS).
  • the drive current passes from the source terminal of the amplification element 11 (LDMOS) to the ground potential (GND1) on the high frequency amplification section side and the ground potential (GND2) on the gate drive section side. It returns to the drain terminal of the switching element 21H (QH) through the bypass capacitor 24H (CH) and the drain resistor 26H (R dh ).
  • the current from the source terminal of the switching element 21 (QH) provided on the back side of the substrate 30 passes through the through hole of the substrate 30, and the gate resistor 12 (R g_LD ) and drives the amplification element 11 (LDMOS) from the gate terminal of the amplification element 11 (LDMOS). Since the source terminal of the amplification element 11 (LDMOS) is at the ground potential (GND1), the heat flows through the heat dissipation section 31 to the conductive shield gasket 29 at the ground potential (GND2) on the gate drive section side.
  • the electrically conductive shield gasket 29 flows through the through hole in the substrate 30 to the bypass capacitor 24 (CH), and again through the through hole in the substrate 30 to the drain terminal of the switching element 21 (QH) provided on the back side of the substrate 30. Returns via drain resistor 26H (R dh ).
  • a conductive shield gasket 29 is placed on the back surface directly below the gate resistor 12 (R g _LD) on the surface layer side, with the substrate in between.
  • This conductive shield gasket 29 has a ground potential (GND2) on the gate drive section side.
  • the source voltage of the amplification element becomes the ground potential (GND1) on the high frequency amplification section side.
  • the ground potential (GND2) on the gate drive section side and the ground potential (GND1) on the high frequency amplification section side are electrically connected via the heat dissipation section, and a current loop is formed between the gate drive section and the high frequency amplification section.
  • the switching element 21 is arranged below the drain resistor 26 (R d ) and the bypass capacitor 24 with the substrate 30 interposed therebetween, and is electrically connected through a through hole provided in the substrate 30.
  • This arrangement allows circuit elements such as the switching element 21, the drain resistor 26 (R d ), and the bypass capacitor 24 to be placed close to each other. This shortens the electrical length of the current loop, thereby making it possible to suppress wiring inductance to a small value.
  • the diameter of the current loop when viewed from the cross-sectional direction is set to about 10 [mm] or less, it is possible to transmit the rectangular waveform gate signal while suppressing attenuation due to wiring inductance.
  • circuit elements of the high frequency power supply device of the present invention are arranged line-symmetrically and radially.
  • 12 and 13 are diagrams for explaining the radial arrangement.
  • 12(a) shows circuit elements arranged on the front side of the substrate 30, and
  • FIG. 12(b) shows circuit elements arranged on the back side of the substrate 30.
  • Each circuit element is arranged symmetrically with respect to the line of symmetry bb on the front side and the back side of the substrate 30, and the driving logic IC 23 and gate resistor 25 are arranged in a straight line, and the series circuit are arranged radially.
  • the driving logic IC 23 arranged on the back side of the substrate 30 forms a series circuit with the gate resistor 25 connected to the driving logic IC 23, and in this series circuit, both circuit elements are arranged linearly and
  • the driving logic ICs 23, which are arranged radially and arranged on the front side of the substrate 30, are also arranged radially.
  • the driving logic IC 23H and gate resistor 25 for driving the switching element 21 (QH1) are arranged in a straight line with respect to the switching element 21 (QH1). Furthermore, regarding the series circuit of the driving logic IC 23L and the gate resistor 25 for driving the switching element 21 (QL1), both circuit elements are arranged in a straight line. These series circuits are arranged radially.
  • the other series circuits are arranged in the same way, and are used for driving to apply a drive signal to each gate terminal of the high-side switching element and the low-side switching element included in each gate drive circuit 20A, 20B.
  • the series circuit of the logic IC and the gate resistor 25 (R g _GaN) is arranged linearly and radially. Due to the linear and radial arrangement of the series circuits, the electrical length of each series circuit and the electrical length between the gate terminal of the switching element are equal, and differences in wiring inductance and delay time due to different wiring lengths are avoided. etc. are suppressed.
  • FIG. 13A schematically shows a configuration in which a series circuit in which a driving logic IC and a gate resistor (R g _GaN) are arranged linearly is arranged radially.
  • a series circuit consisting of a driving logic IC 23H and a gate resistor 25H (R g _GaN) is arranged linearly and radially.
  • the series circuit consisting of the driving logic IC 23L and the gate resistor 25L (R g _GaN) is arranged linearly and radially with respect to the gate terminal of the switching element. This arrangement is also performed in both the gate drive circuits 20A and 20B, which are arranged line-symmetrically.
  • FIG. 13(b) shows a state in which the driving logic IC 23 and the gate resistor 25 (R g _GaN) are arranged in a non-linear manner.
  • the line length of the wiring connecting the driving logic IC 23 and the gate resistor 25 (R g _GaN), and the distance between the gate resistor 25 (R g _GaN) and the gate terminal of the switching element 21 are determined. Since the line lengths of the wiring connecting the two are different, each electrical length is different. This difference in electrical length causes a difference in wiring inductance and a difference in delay time. Note that even if the wiring is non-linear, a non-linear arrangement may be used as long as the line length and electrical length of each wiring are the same.
  • switching mode operation (class D to class F) of a high frequency amplifier using an LDMOSFET is possible, and the dead time DT and gate pulse width T on of the gate voltage V gs applied to the gate of the amplification element can be controlled. It can be made variable, and PWM control in a high frequency band from 27 [MHz] to 100 [MHz] is possible. Further, when the amplifying element (LDMOSFET) is off, the gate of the amplifying element (LDMOSFET) is always reverse biased, so that abnormal oscillations are suppressed from occurring.
  • the high frequency power supply device of the present invention is suitable for industrial applications such as semiconductor manufacturing equipment with an output of 1 kW or more and a frequency range of 27 [MHz] to 100 [MHz], flat panel display manufacturing equipment using liquid crystals or organic EL, and CO2 laser processing machines. Can be applied.

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PCT/JP2023/008248 2022-09-08 2023-03-06 高周波電源装置 Ceased WO2024053135A1 (ja)

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EP23862685.7A EP4586487A1 (en) 2022-09-08 2023-03-06 Radio-frequency power supply device
CN202380063640.4A CN119836740A (zh) 2022-09-08 2023-03-06 高频电源装置
KR1020257008706A KR20250061815A (ko) 2022-09-08 2023-03-06 고주파 전원 장치
US19/109,776 US20260081573A1 (en) 2022-09-08 2023-03-06 Radio-frequency power supply device

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08140341A (ja) 1994-09-16 1996-05-31 Toshiba Corp スイッチング素子を用いたマイクロ電源装置
JP2017092915A (ja) 2015-11-17 2017-05-25 株式会社東芝 増幅器
JP2021535702A (ja) * 2018-08-28 2021-12-16 エフィシェント・パワー・コンバージョン・コーポレイション 帰還を有する能動型プリドライバを使用するＧａＮドライバ
JP7068540B1 (ja) * 2021-12-16 2022-05-16 株式会社京三製作所 高周波電源装置及び高周波電力の出力制御方法
JP2022081242A (ja) * 2020-11-19 2022-05-31 株式会社京三製作所 スイッチングモジュール

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4852404B2 (ja) 2006-12-05 2012-01-11 株式会社リコー データ出力装置およびデータ出力方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08140341A (ja) 1994-09-16 1996-05-31 Toshiba Corp スイッチング素子を用いたマイクロ電源装置
JP2017092915A (ja) 2015-11-17 2017-05-25 株式会社東芝 増幅器
JP2021535702A (ja) * 2018-08-28 2021-12-16 エフィシェント・パワー・コンバージョン・コーポレイション 帰還を有する能動型プリドライバを使用するＧａＮドライバ
JP2022081242A (ja) * 2020-11-19 2022-05-31 株式会社京三製作所 スイッチングモジュール
JP7068540B1 (ja) * 2021-12-16 2022-05-16 株式会社京三製作所 高周波電源装置及び高周波電力の出力制御方法

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CN119836740A (zh) 2025-04-15
TW202429820A (zh) 2024-07-16

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