WO2002103894A1

WO2002103894A1 - A method of operating a voltage-controlled solid state power amplifyng device

Info

Publication number: WO2002103894A1
Application number: PCT/US2001/019615
Authority: WO
Inventors: Douglas M. Macheel; Peter B. Jones; Lee B. Max
Original assignee: Zeta, A Division Of Sierratech, Inc.
Priority date: 2001-06-19
Filing date: 2001-06-19
Publication date: 2002-12-27

Abstract

According to one embodiment, a circuit is disclosed. The circuit comprises a solid state power amplifying device (140), an input impedance matching circuit (110) and an output impedance matching circuit (120) coupled to the solid state amplifying device (140). The input impedance matching circuit (110) includes an input pitchfork trace pattern. The output impedance matching circuit includes an output pitchfork trace pattern. The output impedance matching circuit (120) includes an output pitchfork trace pattern. The circuit further discloses an input bias circuit and an output bias circuit (160).

Description

A METHOD OF OPERATING A VOLTAGE-CONTROLLED SOLID STATE POWER AMPLIFYING DEVICE

FIELD OF THE INVENTION

This invention relates generally to the field of voltage-controlled solid- state power amplifying devices including, but not limited to, laterally diffused metal oxide silicon (LDMOS), vertically diffused (DMOS) FETs, metal semiconductor (MESFETs), pseudomorphic high electron mobility field effect transistors (PHEMT FETs) and static induction transistors (SITs).

BACKGROUND

It is widely known that improving output current balance of the die within solid-state, power amplifying devices results in performance improvement of gain, efficiency, peak output power and linearity. An area of amplifier performance enhancement that has heretofore been overlooked is the utilization and optimization of the amplifier circuit components to assist in balancing the output current distribution of the die of the amplifying device. Therefore, a method of balancing a solid state, power amplifying device is desired.

SUMMARY

According to one embodiment, a method of operating a solid state voltage-controlled power-amplifying device is disclosed. The method includes applying one or more circuit techniques in order to balance the output current of the solid state device. BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:

Figure 1 is a block diagram of one embodiment of a radio frequency amplification circuit;

Figure 2A is a diagram of one embodiment of a radio frequency power FET coupled to an input impedance matching circuit;

Figure 2B is a diagram of one embodiment of a radio frequency power FET coupled to an output impedance matching circuit;

Figure 3A is a diagram of one embodiment of a gate bias circuit coupled to a radio frequency power FET; and

Figure 3B is a diagram of one embodiment of a drain bias circuit coupled to a radio frequency power FET.

DETAILED DESCRIPTION

In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

Figure 1 is a block diagram of one embodiment of a radio frequency amplification circuit 100. Circuit 100 includes an input impedance matching circuit 110, an output impedance matching circuit 120, a radio frequency (RF) power MOS FET 140, a gate bias circuit 150 and a drain bias circuit 160. According to one embodiment, circuit 100 receives input RF signals at input impedance matching circuit 110, amplifies the signal and transmits the amplified signal from output impedance matching circuit 120 to a load (not shown). According to one embodiment, FET 140 comprises a voltage controlled solid state amplifying device such as a lateral diffused MOS (LDMOS) transistor. In other embodiments, FET 140 may comprise a vertical DMOS. However, one of ordinary skill in the art will appreciate that FET 140 may be implemented with other solid state amplifying devices (e.g., MES FETs, PHEMT FETs, SITs, etc.).

INPUT IMPEDANCE MATCHING CIRCUIT

As described above, input impedance matching circuit 110 is designed to receive RF signals. According to one embodiment, the impedance at the interface between the RF input and input impedance matching circuit 110 is 50Ω. Input impedance matching circuit 110 transforms the impedance from the level of the RF input to the impedance of FET 140. Figure 2A is a diagram of FET 140 coupled to input impedance matching circuit 110.

Referring to Figure 2A, input impedance matching circuit 110 includes a multi-section "pitchfork feed" 220. According to one embodiment, pitchfork feed 220 is a printed trace that is configured to provide a balanced current feed into FET 140. Typical printed traces are relatively wide single lines that feed FET 140. However, whenever circuit 100 is operating at high frequency there is typically a higher current density towards the outside edges of the wide single trace. Such an occurrence results in an unbalanced current feed into FET 140. Therefore, pitchfork feed 220 provides for balanced current flow into FET 140 by evenly dividing the current across multiple connected traces resulting in a more uniform current distribution at the input of FET 140. Input impedance matching circuit 110 also includes series resistors 230 within branches of the pitchfork feed 220 traces. Resistors 230 further equalize the current paths into FET 140 so that the current will not prefer one side of the pitchfork feed 220 to the others. In addition, resistors 230 reduce the likelihood of low frequency oscillation of the high frequency FET 140. According to one embodiment, each resistor 230 has a 4.7Ω resistance. Nevertheless, one of ordinary skill in the art will appreciate that other values for resistors 230 may be used.

Input impedance matching circuit 110 further includes resistors 235. Resistors 235 are placed between pairs of branches of pitchfork feed 220 to further equalize the current between any two branches of pitchfork feed 220. For example, imbalances between the top two branches of pitchfork feed 220 are reduced by the resistor 235 between the two. According to one embodiment, each resistor 230 has a 10Ω resistance. Nevertheless, one of ordinary skill in the art will appreciate that other values for resistors 230 may be used.

OUTPUT IMPEDANCE MATCHING CIRCUIT

Output impedance matching circuit 120 is coupled to FET 140. Output impedance matching circuit 120 transforms the impedance from the level of FET 140 to the impedance level of load coupled to circuit 100. According to one embodiment, the impedance at the interface between output impedance matching circuit 120 and the load is 50Ω. Figure 2B is a diagram of FET 140 coupled to output impedance matching circuit 120.

Referring to Figure 2B, output impedance matching circuit 120 includes a multi-section pitchfork feed 260 similar to pitchfork feed 220 in input impedance matching circuit 110. In addition to the advantages described above, the pitchfork feed 260 configuration in output impedance matching circuit 120 also presents a low impedance at the second and third harmonic frequencies to the output of FET 140. The low impedance at the harmonic frequencies minimizes the RF voltage peaks at the output of FET 140.

GATE BIAS CIRCUIT

Gate bias circuit 150 connects a power supply voltage to FET 140 without having an affect on the RF signal amplified by FET 140. According to one embodiment, gate bias circuit 150 presents a low impedance, resistive load to the gates of FET 140 at frequencies from 1 MHz to one-third of the operating RF frequency of FET 140. In addition, gate bias circuit 150 provides the appropriate DC voltage level to the gate of FET 140 to optimize RF performance.

Figure 3A is a diagram of one embodiment of gate bias circuit 150 coupled to FET 140. According to one embodiment, bias circuit 150 includes a pair of resistors (R) and capacitors (C) coupled in series. The input of the resistors are coupled to a supply voltage (VGG), while the capacitors are terminated at ground. According to a further embodiment, bias circuit 150 supplies 2-5 volts DC to the gates of the transistor cells within FET 140.

The resistors in bias circuit 150 limit the low frequency gain of high frequency FET 140. Typically, if the gain at FET 140 increases beyond a particular threshold, FET 140 may oscillate and be damaged. Therefore, the gain limitations performed by bias circuit 150 improve the stability of FET 140. One of ordinary skill in the art will appreciate that other magnitudes of series coupled resistors and capacitors (e.g., 1, 3, 4, etc.) may be included within bias circuit 150.

DRAIN BIAS CIRCUIT

Drain bias circuit 160 connects a DC power supply voltage to FET 140 without affecting the RF signal amplified by FET 140. According to one embodiment, bias circuit 160 results in uniform voltage across the entire lead 270 of FET 140 coupled to the drain of transistor 240. Figure 3B is a diagram of one embodiment of drain bias circuit 160 coupled to FET 140. Bias circuit 160 includes a transient voltage suppressor 310, a capacitor (C) and an inductor (L). Transient voltage suppressor 310 is connected between a supply voltage (V_DD) and ground.

According to one embodiment, FET 140 has a DC breakdown voltage of 70V and V_DD supplies 45-50 volts DC at 10A to the drain of FET 140. Transient voltage suppressor 110 suppresses voltage spikes within circuit 100 caused during the switching between high and low current levels. In one embodiment, transient voltage suppressor 110 is implemented using a diode. However, one of ordinary skill in the art will appreciate that other fast voltage clipping devices may be used to implement transient voltage suppressor 110.

Inductor L is coupled between the supply voltage and FET 140. Inductor L provides a predetermined impedance value that prevents RF current flow from FET 140 through bias circuit 160. However, according to one embodiment, inductor L is designed to be sufficiently small so as to minimize voltage spikes caused by transient currents that occur due to changing current through the circuit. For example, whenever the output power of circuit 100 is quickly switched from low to high (e.g., 50 ns rise/ fall time), or vice versa, the current flow through inductor L changes, resulting in a transient voltage spike. The larger the inductance of inductor L, the higher the magnitude of the voltage spike. In cases where the voltage spike is sufficiently large, severe damage to FET 140 may occur. Therefore, the small size of inductor L and the presence of transient voltage suppressor 110 permits FET 140 to operate at higher voltages (e.g., 50 volts).

Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as the invention.

Claims

CLAIMSWhat is claimed is:

1. A method of operating a solid state voltage-controlled power amplifying device comprising applying one or more circuit techniques in order to balance the output current of the solid state device.

2. The method of claim 1 wherein the process of applying one or more circuit techniques in order to balance the output current of the solid state device comprises coupling an input pitchfork trace pattern to the input of the solid state device.

3. The method of claim 2 wherein the process of applying one or more circuit techniques in order to balance the output current of the solid state device comprises coupling an output pitchfork trace pattern to the output of the solid state device.

4. The method of claim 2 wherein the process of applying one or more circuit techniques in order to balance the output current of the solid state device further comprises inserting a resistor within one or more branches of the input pitchfork trace pattern.

5. The method of claim 2 wherein the process of applying one or more circuit techniques in order to balance the output current of the solid state device further comprises inserting a resistor between one or more pairs of branches of the input pitchfork trace pattern.

6. The method of claim 1 further comprising applying one or more circuit techniques in order to reduce voltage spikes at the solid state device.

7. The method of claim 6 wherein the process of applying one or more circuit techniques in order to reduce voltage spikes at the solid state device comprises rrunimizing radio frequency (RF) voltage peaks at the solid state device.

8. The method of claim 6 wherein the process of applying one or more circuit techniques in order to reduce voltage spikes at the solid state device comprises coupling a transient voltage suppressor to the solid state device.

9. The method of claim 7 wherein the process of minimizing RF voltage peaks at the solid state device comprises presenting a matching impedance at a fundamental frequency of the solid state device.

10. The method of claim 7 wherein the process of minimizing RF voltage peaks at the solid state device further comprises presenting a matching impedance appearing at the odd harmonic frequencies of the solid state device.

11. The method of claim 7 wherein the process of rninirnizing RF voltage peaks at the solid state device further comprises presenting a matching impedance appearing at the even harmonic frequencies of the solid state device.

12. The method of claim 1 wherein the solid state device is a lateral diffused metal oxide semiconductor field effect transistor (LDMOS FET).

13. The method of claim 1 wherein the solid state device is a vertical diffused metal oxide semiconductor field effect transistor (DMOS FET).

14. The method of claim 1 wherein the solid state device is a metal semiconductor field effect transistor (MES FET).

15. The method of claim 1 wherein the solid state device is a pseudomorphic high electron mobility field effect transistor (PHEMT FET).

16. The method of claim 1 wherein the solid state device is a static inductance transistor (SIT).

17. An amplification circuit comprising: a voltage controlled solid state amplifying device; and an output impedance matching circuit coupled to the solid state amplifying device, wherein the output impedance matching circuit includes an output pitchfork trace pattern of one or more sections, wherein each section comprises two or more branches.

18. An amplification circuit comprising: a voltage controlled solid state amplifying device; and an input impedance matching circuit coupled to the solid state amplifying device, wherein the input impedance matching circuit includes an input pitchfork trace pattern of one or more sections, wherein each section comprises two or more branches.

19. The circuit of claim 18 wherein the input impedance matching circuit further comprises a resistor inserted within one or more branches of the pitchfork trace pattern.

20. The circuit of claim 18 wherein the input impedance matching circuit further comprises a resistor connected across one or more pairs of branches of the pitchfork trace pattern.

21. The circuit of claim 18 further comprising: a radio frequency source coupled to the input impedance matching circuit; an output impedance matching circuit coupled to the amplifying device; and a load coupled to the output impedance matching circuit.

22. The circuit of claim 18 further comprising an output bias circuit coupled to the solid state amplifying device.

23. The circuit of claim 22 wherein the output bias circuit comprises a transient voltage suppressor.

24. The circuit of claim 18 further comprising an input bias circuit coupled to the amplifying device and the input impedance matching circuit.

25. The circuit of claim 18 wherein the amplifying device comprises a lateral diffused metal oxide semiconductor field effect transistor (LDMOS FET).

26. The circuit of claim 18 wherein the amplifying device comprises a vertical diffused metal oxide semiconductor field effect transistor (DMOS FET).

27. The circuit of claim 18 wherein the amplifying device is a metal semiconductor field effect transistor (MES FET).

28. The circuit of claim 18 wherein the amplifying device is a pseudomorphic high electron mobility field effect transistor (PHEMT FET).

29. The circuit of claim 18 wherein the amplifying device is a static inductance transistor (SIT).

30. An amplification circuit comprising: a voltage controlled solid state amplifying device; and an output bias circuit coupled to the solid state amplifying device, wherein the output bias circuit comprises a transient voltage suppressor.

31. An amplification circuit comprising a voltage controlled solid state amplifying device operated at direct current (DC) voltage greater than fifty percent of the DC breakdown voltage of the amplifying device.