WO2024051450A1

WO2024051450A1 - Dual-processor device and control method therefor, and processor

Info

Publication number: WO2024051450A1
Application number: PCT/CN2023/112998
Authority: WO
Inventors: 唐亚海
Original assignee: 深圳市恒运昌真空技术股份有限公司
Priority date: 2022-09-08
Filing date: 2023-08-15
Publication date: 2024-03-14

Abstract

The present application discloses a dual-processor device and a control method therefor, and a processor. The dual processors comprise a control processor and a computing processor. The method is implemented by the control processor. The method comprises: upon detection that an electric arc occurs, sending a pre-turn-off output front-end handshake to the computing processor, so that the computing processor stops a related computing operation according to the pre-turn-off output front-end handshake; receiving a computing stop notification sent by the computing processor, the computing stop notification being sent by the computing processor after receiving the pre-turn-off output front-end handshake and completing computing of received data; and executing a turn-off operation. The problem in the prior art of poor correctness of data between the control processor and the computing processor caused by asynchronization between the control processor and the computing processor is solved.

Description

A dual-processor device and its control method and processor

Technical field

The present invention relates to the technical field of equipment control, and in particular to a dual-processor device, a control method thereof, and a processor.

Background technique

In the traditional dual-processor equipment control scheme, processor A is used to control the circuit and detect arcs. Processor B performs PID calculations to provide processor A with control circuit operating parameters. When processor A detects the occurrence of arcs, it performs disabling control ( DISABLE), immediately disconnects the circuit or stops signal output, but the PID operation cannot be interrupted. Therefore, when processor A performs disabling control, processor B still continues to perform PID calculations and feeds back the control circuit to processor A. Operating parameters. For processor A, the operating parameters fed back by processor B at this time are redundant, useless and wrong. In addition, the failure control of processor A is sudden, and the operation parameters fed back by processor B are redundant, useless and wrong. Parameters may also prevent processor A from connecting to subsequent monitoring data, causing the overall control data set to become invalid.

Therefore, how to design a high-reliability, high-accuracy dual-processor device and its control method is a technical problem to be solved.

Contents of the invention

Therefore, the technical problem to be solved by the present invention is to overcome the problem in the prior art that when dual processors perform PID control, the control processor control circuit immediately executes an interrupt, while the operation processor continues to perform PID operations, thus affecting the control processor. and data correctness between computing processors. Therefore, a dual-processor device and its control method and processor are provided.

In order to solve the above technical problems, disclosed embodiments of the present invention at least provide a dual-processor device, a control method thereof, and a processor.

In a first aspect, disclosed embodiments of the present invention provide a dual-processor device control method, which Characteristically, the dual processors include a control processor and an arithmetic processor, the method is implemented by the control processor, and the method includes:

If an arc is detected, a pre-shutdown output pre-handshake is sent to the arithmetic processor, so that the arithmetic processor stops relevant computing operations according to the pre-shutdown output pre-handshake;

Receive a stop operation notification sent by the operation processor. The operation stop notice is issued after the operation processor receives the pre-shutdown output pre-handshake and completes the operation of the received data;

Perform shutdown operation.

Preferably, the method further includes:

When the restart condition is met, send a restart pre-handshake to the computing processor, so that the computing processor resumes computing preparations according to the restart pre-handshake;

After receiving the recovery confirmation message fed back by the computing processor, resume obtaining the device operation data, and resume sending the device operation data to the computing processor. The recovery confirmation message is after the computing processor completes the computing preparation. Sent.

Preferably, before sending a restart pre-handshake to the computing processor, the method further includes:

Determine whether the computing processor is in a sleep state;

The step of sending a restart pre-handshake to the arithmetic processor is: if the arithmetic processor is in a sleep state, sending a restart pre-handshake to the arithmetic processor.

If the computing processor is not in the sleep state, the device operation data is directly obtained and sent to the computing processor.

Preferably, the restart condition includes: whether the shutdown time meets a preset shutdown duration; and/or whether restart instruction information is received.

Preferably, it also includes:

After performing the shutdown operation, it enters the sleep state.

Preferably, before entering the dormant state, the method further includes: freezing equipment operating data during arc generation.

In a second aspect, disclosed embodiments of the present invention provide a control processing unit for a dual-processor device. processor, which is characterized by including:

A pre-shutdown indication module is used to send a pre-shutdown output pre-handshake to the arithmetic processor when an arc is detected, so that the arithmetic processor stops relevant operations according to the pre-shutdown output pre-handshake. operate;

A pre-shutdown execution module, configured to receive a stop operation notification sent by the arithmetic processor. The stop arithmetic notification is after the arithmetic processor receives the pre-shutdown output pre-handshake and completes the received data. Emitted after the operation;

Shutdown module, used to perform shutdown operations.

In a third aspect, disclosed embodiments of the present invention provide a method for controlling a dual-processor device, characterized in that the dual-processor includes a control processor and an arithmetic processor, and the method is implemented by the arithmetic processor. include:

Receive the pre-shutdown output pre-handshake sent by the control processor;

After completing the operation of the received data, stop the relevant operation;

Send a stop operation notification to the control processor, so that the control processor performs a shutdown operation after receiving the stop operation notification.

Preferably, it also includes:

Receive a restart pre-handshake sent by the control processor;

Complete recovery operation preparations according to the pre-restart handshake;

Send a recovery confirmation message to the control processor so that the control processor resumes obtaining device operating data according to the recovery confirmation message;

Receive the device operation data sent by the control processor.

Preferably, after sending the operation stop notification to the control processor, the method further includes: entering a sleep state.

In a fourth aspect, disclosed embodiments of the present invention provide an arithmetic processor for a dual-processor device, which is characterized in that it includes:

The pre-shutdown indication receiving module is used to receive the pre-shutdown output pre-interface sent by the control processor. grip;

The operation stop control module is used to stop related operation operations after completing the operation of the received data;

The operation stop notification module is configured to send a stop operation notification to the control processor, so that the control processor performs a shutdown operation after receiving the operation stop notification.

In a fifth aspect, disclosed embodiments of the present invention provide a dual-processor device, which is characterized in that it includes the control processor for the dual-processor device of the second aspect and the operation processor for the dual-processor device of the fourth aspect. processor.

In the sixth aspect, the disclosed embodiments of the present invention provide a dual-processor device control method, characterized in that the dual-processor device includes a control processor, an operation processor and a shared memory, and the shared memory is provided with an interrupt Indicates the identification, and the method is implemented by the control processor, and the method includes:

If an arc is detected, a shutdown operation is performed;

The shutdown indication flag in the shared memory is set to a shutdown state, so that the computing processor skips obtaining the first device operation data according to the state of the shutdown indication flag, and the first device operation data is the equipment operating data obtained by the control processor during arc generation.

Preferably, before the arc is detected, the method further includes:

Obtain the second device operating data;

Send the second device operating data to the computing processor through the shared memory.

Preferably, sending the second device operating data to the computing processor through the shared memory includes:

The second device operation data is stored in the shared memory so that the computing processor can obtain the second device operation data from the shared memory.

Preferably, after performing the shutdown operation, the method further includes: entering a sleep state.

Preferably, the method further includes:

Restart when the restart conditions are met;

Set the shutdown indication flag in the shared memory to a normal state;

Resume obtaining the operating data of the second device;

Resume sending the second device operating data to the computing processor through the shared memory, so that the computing processor obtains the second device operating data from the shared memory according to the state identified by the shutdown indication.

Preferably, the restart conditions include:

Whether the shutdown time meets the preset shutdown duration; and/or whether a restart instruction message is received.

In the seventh aspect, disclosed embodiments of the present invention provide a dual-processor device, characterized in that the dual-processor device includes a control processor, an operation processor and a shared memory, and a shutdown indication flag is provided in the shared memory. , the control processor includes:

A shutdown indication module is used to perform a shutdown operation when an arc is detected;

A shutdown state setting module, configured to set the shutdown indication flag in the shared memory to a shutdown state, so that the computing processor skips acquiring the first device operating data according to the status of the shutdown indication flag. , the first equipment operating data is equipment operating data obtained by the control processor during arc generation.

In an eighth aspect, disclosed embodiments of the present invention provide a method for controlling a dual-processor device, characterized in that the dual-processor device includes a control processor, an arithmetic processor, and a shared memory, and a shutdown indication is provided in the shared memory. identification, the method is implemented by the computing processor, and the method includes:

Obtain the status of the shutdown indication flag in the shared memory;

If the shutdown indication flag is in the shutdown state, the acquisition of the first equipment operation data is skipped according to the status of the shutdown indication flag. The first equipment operation data is obtained by the control processor during arc generation. Equipment operating data.

Preferably, it also includes:

If the shutdown indication flag is in a normal state, obtain the first device operating data from the shared memory;

Calculate control parameters based on the first equipment operating data;

The calculated control parameters are sent to the control processor via the shared memory.

Preferably, the method further includes: entering the sleep state when the shutdown indication indicates the shutdown state.

Preferably, before obtaining the status of the shutdown indicator in the shared memory, the method further includes:

Restart when the restart conditions are met;

The step of obtaining the status of the shutdown indication flag in the shared memory is to restore and obtain the status of the shutdown indication flag in the shared memory.

In a ninth aspect, disclosed embodiments of the present invention provide a dual-processor device, characterized in that the dual-processor device includes a control processor, an operation processor and a shared memory, and a shutdown indication flag is provided in the shared memory. , the computing processor includes:

A shutdown identification acquisition module, configured to obtain the status of the shutdown indication identification in the shared memory;

A shutdown data processing module, configured to, if the shutdown indication flag is in a shutdown state, skip acquiring the first device operation data according to the status of the shutdown indication flag, and the first device operation data is the control Equipment operating data acquired by the processor during arc generation.

In a tenth aspect, disclosed embodiments of the present invention provide a dual-processor device, which is characterized in that it includes a shared memory, the control processor described in the ninth aspect, and the operation processor described in the ninth aspect, and the shared memory There is a shutdown indicator mark in it.

In an eleventh aspect, disclosed embodiments of the present invention provide a computer device, which is characterized in that it includes: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the computer device When running, the processor and the memory communicate through a bus, and when the machine-readable instructions are executed by the processor, they are executed as described in one of the first aspect, the third aspect, the sixth aspect, or the eighth aspect. The dual-processor device control method described above.

In a twelfth aspect, disclosed embodiments of the present invention provide a computer-readable storage medium, which is characterized in that a computer program is stored on the computer-readable storage medium, and the computer program is executed when the processor runs as in the first aspect, As mentioned in one of the third aspect, sixth aspect or eighth aspect Dual-processor device control method.

The technical solution provided by the embodiments of the present invention can have the following beneficial effects: During the control process based on dual processors, if the control processor detects the occurrence of an arc, it will perform a shutdown operation, which may stop the processor being operated from obtaining equipment operation data. , or it can be to send a shutdown operation instruction to the operation processor; the operation processor can determine based on whether the device operation data is obtained, or according to whether the shutdown operation instruction is received, interrupt the operation of the relevant control parameters, or stop sending data to the control The processor sends the relevant control parameters that have been calculated to ensure that the control processor obtains the correct control parameters and ensures arc generation. When the control processor turns off the circuit, the data between the two processors can maintain better accuracy. Stop the PID operation in a timely manner to avoid prolonging the shutdown timing, and at the same time reduce the situation of discarding data. When one end of the circuit is turned off, the other end is still executing, causing the overall circuit to run in disorder. As long as the overall PID operation has not started, the operation can be interrupted or not Send the operating parameters of the completed operation, suitable for instructions, handshaking or shared data. When shutting down, the data is frozen to ensure the stability and consistency of data transmission between the control processor and the operation processor and avoid controlling the processor circuit. When turned off, the other end of the arithmetic processor is still performing unnecessary operations, causing the overall circuit to run erratically, effectively ensuring the accuracy of data between the control processor and the arithmetic processor when an arc occurs.

Description of the drawings

Exemplary embodiments of the present invention may be more fully understood by reference to the following drawings. The drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the description. They are used to explain the present invention together with the embodiments of the present application and do not constitute a limitation of the present invention. In the drawings, like reference numbers generally represent like components or steps.

Figure 1 is a flow chart of a dual-processor device control method provided by a disclosed embodiment of the present invention;

Figure 2 shows a flow chart of another dual-processor device control method provided by the disclosed embodiment of the present invention;

Figures 3, 4, 5, and 6 show the interaction and timing diagrams of the control processor and the operation processor in the disclosed embodiments of the present invention;

Figure 7 shows a flow chart of yet another dual-processor device control method provided by the disclosed embodiment of the present invention;

Figure 8 shows a flow chart of yet another dual-processor device control method provided by the disclosed embodiment of the present invention;

Figure 9 shows a schematic structural diagram of a control processor for a dual-processor device provided by a disclosed embodiment of the present invention;

Figure 10 shows a schematic structural diagram of an arithmetic processor for a dual-processor device provided by a disclosed embodiment of the present invention;

Figure 11 shows a schematic structural diagram of a dual-processor device provided by an embodiment of the present invention;

Figure 12 shows a flow chart of a dual-processor device control method provided by a disclosed embodiment of the present invention;

Figure 13 shows a flow chart of another dual-processor device control method provided by the disclosed embodiment of the present invention;

Figure 14 shows a flow chart of yet another dual-processor device control method provided by the disclosed embodiment of the present invention;

Figure 15 shows a flow chart of yet another dual-processor device control method provided by the disclosed embodiment of the present invention;

Figure 16 shows a schematic structural diagram of a control processor in a dual-processor device provided by a disclosed embodiment of the present invention;

Figure 17 shows a schematic structural diagram of an arithmetic processor in another dual-processor device provided by an embodiment of the present invention;

Figure 18 shows a schematic structural diagram of a dual-processor device provided by a disclosed embodiment of the present invention;

Figures 19, 20, and 21 show timing diagrams of a dual-processor device control method provided by disclosed embodiments of the present invention;

Figure 22 shows a flow chart of another dual-processor device control method provided by the disclosed embodiment of the present invention;

Figure 23 shows a flow chart of another dual-processor device control method provided by the disclosed embodiment of the present invention.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a thorough understanding of the disclosure, and to fully convey the scope of the disclosure to those skilled in the art.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description. It does not indicate or imply that the device or element referred to must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations of the invention. Furthermore, the terms “first”, “second” and “third” are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.

In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

Example 1

As shown in Figure 1, there is a flow chart of a dual-processor device control method provided by an embodiment of the present invention. The dual-processor includes a control processor and an operation processor. The method is implemented by the control processor. The method includes:

S11: If an arc is detected, the pre-shutdown output pre-handshake is sent to the arithmetic processor, so that the arithmetic processor stops relevant computing operations based on the pre-shutdown output pre-handshake;

S12: Receive the stop operation notification sent by the operation processor. The stop operation notification is issued after the operation processor receives the pre-shutdown output pre-handshake and completes the operation of the received data;

S13: Perform shutdown operation.

It can be understood that, according to the technical solution provided by this embodiment, during the control process of the dual-processor device, if the control processor detects the occurrence of an arc, it will send a pre-shutdown output pre-handshake to the computing processor, and the computing processor will The shutdown output pre-handshake completes the calculation of the received data and stops the relevant calculation operations. The control processor performs the shutdown operation after receiving the stop calculation notification sent by the calculation processor. Through handshaking, the control processor and the calculation processor are ensured. The stability and consistency of data transmission between the two ends prevents the control processor circuit from being turned off while the other end of the operation processor is still performing unnecessary operations, causing the overall circuit to run erratically. This effectively ensures that when an arc occurs, the control processor and Data correctness between computing processors.

Example 2

As an improvement of Embodiment 1, as shown in Figure 2, the present invention discloses a flow chart of another dual-processor device control method provided by the embodiment of the present invention. The dual-processor includes a control processor and an operation processor. This method Implemented by the control processor, the method includes:

S21: When the restart condition is met, the control processor determines whether the arithmetic processor is in a sleep state. If the arithmetic processor is in a sleep state, S22 is executed. If the arithmetic processor is not in a sleep state, S24 is executed;

S22: The control processor sends a restarted pre-handshake to the arithmetic processor, so that the arithmetic processor can resume computing preparations based on the restarted pre-handshake;

S23: The control processor receives the recovery confirmation message fed back by the operation processor, and resumes execution of S24. The recovery confirmation message is sent by the operation processor after completing the operation preparation;

S24: The control processor obtains the device operating data and sends the device operating data to the computing processor;

S25: If an arc is detected, the control processor sends a pre-shutoff output pre-handshake to the arithmetic processor, so that the arithmetic processor stops relevant computing operations according to the pre-shutdown output pre-handshake;

S26: The control processor receives the stop operation notification sent by the operation processor. The stop operation notification is issued after the operation processor receives the pre-shutdown output pre-handshake and completes the operation of the received data;

S27: Control the processor to perform a shutdown operation;

S28: The control processor freezes the equipment operating data during arc generation;

S29: Control the processor to enter the sleep state.

In some optional embodiments, the restart conditions include: whether the shutdown time meets the preset shutdown duration; and/or whether restart instruction information is received.

Further, data can be frozen, CPUB alone or CPUA and CPUB can enter limited sleep at the same time.

It should be noted that the embodiments recorded in this specific implementation mode are only illustrative descriptions of specific implementations under the concept of the present invention. The execution order of the steps in each embodiment is not limited to the embodiments provided herein. In specific engineering practice , those skilled in the art can adjust the execution order of each step according to the actual situation. For example, there is no inevitable causal relationship and sequence between S21 and S27. The restart operation of S21 can also be described as after the shutdown operation of S27. .

In order to facilitate readers' understanding, the interaction process and timing relationship of the dual-processor device control method in the embodiment of the present invention are described in detail below with reference to Figures 3, 4, 5, and 6. CPUA serves as the control processor and CPUB serves as the operation processor. Description: First sequence: CPUA transmits necessary data for PID operation to CPUB; CPUB obtains data for PID operation; CPUA detects arc and sends pre-shutdown output pre-handshake; CPUB's PID operation completes the correct data received and returns Passed to CPUA; CPUB feedbacks to CPUA according to the handshake that the timing PID operation preparation has been stopped; CPUA obtains CPUB feedback and performs shutdown output; CPUA abandons the PID data fed back at this timing.

The Nth sequence, an integer with N>1, is divided into two situations: CUPB sleeping and CUPB not sleeping: 1. When CPUB does not sleep: CPUA restarts the control circuit for power output; CPUA transmits necessary data for PID operation to CPUB; CPUB obtains data Perform PID operation.

2. When CPUB is in sleep state, CPUA outputs a pre-restart handshake; CPUB feeds back to CPUA Preparation is complete; CPUA transmits the necessary data for PID operation to CPUB; CPUB obtains the data for PID operation.

Example 3

As shown in Figure 7, an embodiment of the present invention also provides a dual-processor device control method. The dual-processor includes a control processor and an arithmetic processor. The method is implemented by the arithmetic processor. The method includes:

S31: Receive the pre-shutdown output pre-handshake sent by the control processor;

S32: After completing the operation of the received data, stop the relevant operation;

S33: Send a stop operation notification to the control processor, so that the control processor performs a shutdown operation after receiving the stop operation notification.

Example 4

As an improvement of Embodiment 3, as shown in Figure 8, this embodiment of the present invention also provides a dual Processor device control method, the dual processor includes a control processor and an operation processor, the method is implemented by the operation processor, the method includes:

S41: The operation processor receives the pre-shutdown output pre-handshake sent by the control processor;

S42: After completing the operation of the received data, the operation processor stops related operation operations;

S43: The computing processor freezes the equipment operating data during arc generation;

S44: The operation processor sends a stop operation notification to the control processor, so that the control processor performs a shutdown operation after receiving the stop operation notification;

S45: The computing processor enters sleep state;

S46: The operation processor receives the restart pre-handshake sent by the control processor;

S47: The computing processor completes preparations for resuming computing according to the pre-restart handshake;

S48: The operation processor sends a recovery confirmation message to the control processor, so that the control processor can resume obtaining the device operating data according to the recovery confirmation message;

S49: The operation processor receives the device operation data sent by the control processor.

Example 5

As shown in Figure 9, an embodiment of the present invention also provides a control processor for a dual-processor device, including: a pre-shutdown indication module 51, configured to send a pre-shutdown instruction module 51 to the computing processor when an arc is detected. The pre-shutdown output pre-handshake is used to enable the computing processor to stop relevant computing operations according to the pre-shutdown output pre-handshake; the pre-shutdown execution module 52 is used to receive a stop computing notification sent by the computing processor, and the stop computing notification is a computing operation. The processor receives the pre-shutdown output pre-handshake and sends it after completing the operation of the received data; the shutdown module 53 is used to perform the shutdown operation.

In some optional embodiments, as shown in the dotted line part of the figure, the control processor also includes: a restart handshake module 54, configured to send a restart pre-handshake to the computing processor when the restart conditions are met, so that The operation processor resumes operation preparation according to the pre-handshake of restart; the recovery confirmation module 55 is used to resume obtaining the equipment operation data after receiving the recovery confirmation message fed back by the operation processor, and resume sending the equipment operation data to the operation processor, If the computing processor is not in the sleep state, the device operating data is directly obtained and sent to the computing processor. The recovery confirmation message is sent after the computing processor completes the computing preparation.

In some optional embodiments, as shown in the dotted line part of the figure, the control processor also includes: a first data freezing module 56, used to freeze the equipment operating data during arc generation; a first sleep start module 57, used to freeze the operating data of the equipment during arc generation; After performing the shutdown operation, the processor is controlled to enter the sleep state; the sleep judgment module 58 is used to determine whether the computing processor is in the sleep state.

The restart handshake module 54 sends a restart pre-handshake to the arithmetic processor: if the arithmetic processor is in a sleep state, the restart handshake module 54 sends a restart pre-handshake to the arithmetic processor.

Example 6

As shown in Figure 10, an embodiment of the present invention also provides an arithmetic processor for a dual-processor device, including: a pre-shutdown instruction receiving module 61, configured to receive the pre-shutdown output pre-interface sent by the control processor. Hold; the operation stop control module 62 is used to stop the operation after completing the operation of the received data. Related computing operations; the computing stop notification module 63 is used to send a computing stop notification to the control processor, so that the control processor performs a shutdown operation after receiving the computing stop notification.

In some optional embodiments, as shown in the dotted line in the figure, the computing processor also includes: a second data freezing module 64, used to freeze the equipment operating data during arc generation; a second sleep start module 65, used to freeze the operating data of the equipment during arc generation; After the operation processor enters the sleep state; the handshake receiving module 66 is used to receive the restart pre-handshake sent by the control processor; the operation recovery module 67 is used to complete the recovery operation preparation according to the restart pre-handshake; the recovery message The sending module 68 is configured to send a recovery confirmation message to the control processor, so that the control processor can resume obtaining the device operation data according to the recovery confirmation message and resume sending the device operation data.

The equipment data receiving module 69 is used to receive equipment operation data sent by the control processor.

Example 7

As shown in Figure 11, an embodiment of the present invention also provides a dual-processor device, including the control processor for the dual-processor device of the above-mentioned Embodiment 5 and the arithmetic processing for the dual-processor device of the above-mentioned Embodiment 6. device.

It can be understood that, according to the technical solution provided by this embodiment, during the control process of the dual-processor device, if the control processor detects the occurrence of an arc, it will send a pre-shutdown output pre-handshake to the computing processor, and the computing processor will The shutdown output pre-handshake completes the calculation of the received data and stops the relevant calculation operations. The control processor performs the shutdown operation after receiving the stop calculation notification sent by the calculation processor. Through handshaking, the control processor and the calculation processor are ensured. The stability and consistency of data transmission between the two devices prevents the other end's computing processor from still performing unnecessary operations when the control processor circuit is turned off. This causes the overall circuit to run erratically, effectively ensuring the correctness of data between the control processor and the operation processor when an arc occurs.

Example 8

As shown in Figure 12, there is a flow chart of a dual-processor device control method provided by an embodiment of the present invention. The dual-processor device includes a control processor, an operation processor and a shared memory. The shared memory is provided with a shutdown indication flag. , this method is implemented by the control processor and includes:

S81: If an arc is detected, the shutdown operation is performed;

S82: Set the shutdown indication flag in the shared memory to the shutdown state, so that the computing processor skips acquiring the first device operation data according to the state of the shutdown indication flag. The first device operation data is to control the processor during arc generation. Obtained device operating data.

It can be understood that, in the technical solution provided by this embodiment, during the PID control process based on dual processors, if the control processor detects the occurrence of an arc, it will perform a shutdown operation; and set the shutdown indication flag in the shared memory to In the shutdown state, the computing processor skips the acquisition of the equipment operating data obtained by the control processor during the arc generation according to the status of the shutdown indicator. Through the shared memory, even if one CPU writes to generate area protection, the other CPU can still read The adopted data sharing mode enables the CPUs of both parties to immediately obtain the changing data and working status of the other CPU from the high-speed storage unit when executing any job, ensuring the stability of data transmission between the control processor and the operation processor. and consistency, to avoid that when the control processor circuit is turned off, the other end of the arithmetic processor is still performing unnecessary operations, causing the overall circuit to run erratically, effectively ensuring that when an arc occurs, the control processor and the arithmetic processor data correctness.

Example 9

As an improvement of Embodiment 8, as shown in Figure 13, the present invention discloses a flow chart of another dual-processor device control method provided by the embodiment. The dual-processor device includes a control processor, an operation processor and a shared memory. A shutdown indication flag is provided in the shared memory, and the method is implemented by the control processor. The method includes:

S91: The control processor obtains the operating data of the second device;

S92: The control processor sends the second device operating data to the operation processor through the shared memory;

S93: If an arc is detected, the control processor performs a shutdown operation;

S94: The control processor sets the shutdown indication flag in the shared memory to the shutdown state, so that the operation processor skips acquiring the first device operation data according to the state of the shutdown instruction flag. The first device operation data is the control processor's Equipment operating data acquired during arc generation;

S95: The control processor freezes the equipment operating data during arc generation;

S96: Control the processor to enter sleep state;

S97: When the restart conditions are met, the control processor restarts;

S98: The control processor sets the shutdown indication flag in the shared memory to the normal state and resumes execution of S91.

In some optional embodiments, the control processor stores the second device operating data in the shared memory so that the operation processor can obtain the second device operating data from the shared memory.

It should be noted that the embodiments recorded in this specific implementation mode are only illustrative descriptions of specific implementations under the concept of the present invention. The execution order of the steps in each embodiment is not limited to the embodiments provided herein. In specific engineering practice , those skilled in the art can adjust the execution order of each step according to the actual situation. For example, there is no inevitable causal relationship and sequence between S91 and S97. The restart operation of S97 can also be described as obtaining the second device in S91. After running the data.

Example 10

As shown in Figure 14, an embodiment of the present invention also provides a method for controlling a dual-processor device. The dual-processor device includes a control processor, an arithmetic processor, and a shared memory. The shared memory is provided with a shutdown indication flag. The method consists of an arithmetic processing unit. Device implementation, this method includes:

S101: Obtain the status of the shutdown indication flag in the shared memory;

S102: If the shutdown indication flag is in the shutdown state, skip acquiring the first equipment operation data according to the status of the shutdown instruction flag. The first equipment operation data is equipment operation data obtained by the control processor during arc generation.

It can be understood that, in the technical solution provided by this embodiment, during the PID control process based on dual processors, if the control processor detects the occurrence of an arc, it will perform a shutdown operation; and set the shutdown indication flag in the shared memory to In the shutdown state, the computing processor skips the acquisition of the equipment operating data obtained by the control processor during the arc generation according to the status of the shutdown indicator. Through the shared memory, even if one CPU writes to generate area protection, the other CPU can still read The adopted data sharing mode enables the CPUs of both parties to immediately obtain the changing data or working status of the other CPU from the high-speed storage unit when executing any job, ensuring the stability of data transmission between the control processor and the operation processor. and consistency, to avoid that when the control processor circuit is turned off, the other end of the arithmetic processor is still performing unnecessary operations, causing the overall circuit to run erratically, effectively ensuring that when an arc occurs, the control processor and the arithmetic processor data correctness.

Example 11

As an improvement of Embodiment 10, as shown in Figure 15, this embodiment of the present invention also provides a dual-processor device control method. The dual-processor device includes a control processor, an arithmetic processor, and a shared memory. The shared memory is configured with relevant Break indicator flag, this method is implemented by the operation processor, this method includes:

S111: When the restart conditions are met, the computing processor restarts and resumes execution of S42;

S112: The operation processor obtains the status of the shutdown indication flag in the shared memory;

S113: If the shutdown indication flag is in the normal state, the computing processor obtains the first device operating data from the shared memory;

S114: The computing processor calculates control parameters based on the first device operating data;

S115: The operation processor sends the calculated control parameters to the control processor through the shared memory;

S116: If the shutdown indication flag is in the shutdown state, the computing processor skips acquiring the first equipment operation data according to the status of the shutdown indication flag. The first equipment operation data is the equipment operation data obtained by the control processor during arc generation. ;

S117: The computing processor freezes the equipment operating data during arc generation;

S118: When the shutdown indication mark is in the shutdown state, the computing processor enters the sleep state and waits for the restart condition to be triggered.

Example 12

An embodiment of the present invention also provides a dual-processor device. The dual-processor device includes a control processor, an operation processor and a shared memory. The shared memory is provided with a shutdown indication flag, as shown in Figure 16, where the control processor includes : The shutdown indication module 121 is used to perform a shutdown operation when an arc is detected.

The shutdown state setting module 122 is used to set the shutdown indication flag in the shared memory to the shutdown state, so that the computing processor skips obtaining the first device operation data according to the state of the shutdown instruction flag. The first device operation data is Equipment operating data acquired by the control processor during arc generation.

In some optional embodiments, as shown in the dotted line part in the figure, the device may also include: The row data acquisition module 123 is used to acquire the second device operating data.

The operation data sending module 124 is configured to send the second device operation data to the operation processor through the shared memory, restore the acquisition and send the second device operation data to the operation processor through the shared memory, so that the operation processor can determine the status according to the shutdown indication. Obtain the second device operating data from the shared memory.

The first data freezing module 125 is used to freeze equipment operating data during arc generation.

The first sleep module 126 is used to enter the sleep state.

The first restart module 127 is used to restart when restart conditions are met.

The shared flag setting module 128 is used to set the shutdown indication flag in the shared memory to a normal state.

Example 13

An embodiment of the present invention also provides a dual-processor device. The dual-processor device includes a control processor, an arithmetic processor and a shared memory. The shared memory is provided with a shutdown indication flag, as shown in Figure 17, where the arithmetic processor includes : Shutdown flag acquisition module 131, used to obtain the status of the shutdown indication flag in the shared memory.

The shutdown data processing module 132 is used to process the shutdown data according to the shutdown indication if the shutdown indication is in the shutdown state. The status of the fault indicator flag skips obtaining the first equipment operation data. The first equipment operation data is equipment operation data obtained by the control processor during arc generation.

In some optional embodiments, as shown in the dotted line part of the figure, the device also includes: an operating data extraction module 133, configured to obtain the first device operating data from the shared memory if the shutdown indication is in a normal state, After restarting, resume obtaining the status of the shutdown indication flag in the shared memory.

The control parameter calculation module 134 is used to calculate control parameters based on the first equipment operating data.

The control parameter sending module 135 is used to send the calculated control parameters to the control processor through the shared memory.

The second sleep module 1313 is configured to enter the sleep state when the shutdown indication flag is in the shutdown state.

The second restart module 137 is used to restart when the restart conditions are met.

The second data freezing module 138 is used to freeze equipment operating data during arc generation.

Example 14

As shown in Figure 18, an embodiment of the present invention also provides a dual-processor device, including a shared memory 141, a control processor 142 and an arithmetic processor 143 in the dual-processor device, wherein the shared memory 141 is provided with a shutdown Instructions.

In order to facilitate readers' understanding, the dual-processor device is described in detail below in conjunction with the timing diagrams in Figure 19, Figure 20, and Figure 21. CPUA is the control processor, CPUB is the operation processor, RAM is the shared memory, and FLAG is the shutdown indication. Identification:

In general mode, dual-processor device PID control includes the following processes:

CPUA does not detect arc and does not rewrite CPUA's working FLAG in RAM;

CPUA transfers the necessary data for PID operation and writes it into RAM;

CPUB reads the working FLAG of CPUA in RAM and determines it as ENABLE;

CPUB reads RAM to obtain data for PID operation;

CPUB writes the circuit control parameters generated by the operation into RAM;

CPUA reads RAM to obtain parameters to control circuit operation and power output.

Through the shared storage mode, dual-processor device PID control includes the following processes:

During the 1st sequence:

CPUA detects arc and rewrites CPUA's working FLAG in RAM to DISABLE;

CPUA executes shutdown output;

CPUB reads the working FLAG of CPUA in RAM and determines it as DISABLE;

CPUB does not read RAM and does not perform the PID operation of the current sequence.

Further, data can be frozen, and CPUB or dual CPU can enter limited sleep.

At the Nth timing, N>1 is an integer:

CPUA restarts the control circuit for power output;

CPUA rewrites CPUA’s working FLAG in RAM;

CPUA transfers the necessary data for PID operation and writes it into RAM;

CPUB reads the working FLAG of CPUA in RAM and determines it as ENABLE;

CPUB reads RAM to obtain data for PID operation;

CPUB writes the circuit control parameters generated by the operation into RAM.

It can be understood that, in the technical solution provided by this embodiment, during the PID control process based on dual processors, if the control processor detects the occurrence of an arc, it will perform a shutdown operation; and set the shutdown indication flag in the shared memory to In the shutdown state, the operation processor skips the acquisition of the equipment operating data obtained by the control processor during the arc generation according to the status of the shutdown indicator, and uses the shared memory to Memory, using the data sharing mode that even if one CPU writes to generate area protection, the other CPU can still read it, so that when both CPUs perform any job, they can immediately obtain the changed data of the other CPU from the high-speed storage unit and working status to ensure the stability and consistency of data transmission between the control processor and the arithmetic processor, and to avoid that when the control processor circuit is turned off, the other end arithmetic processor is still performing unnecessary operations, causing overall circuit chaos. operation, effectively ensuring the correctness of data between the control processor and the operation processor when an arc occurs.

Example 15

A dual-processor device provided by the disclosed embodiments of the present invention has a schematic structural diagram similar to that shown in Figure 11. The device includes:

The control processor 151 (not shown in the figure), if an arc is detected, performs a specified operation. The specified operation includes at least one of the following operations: Operation 1: Stop the processor 152 (not shown in the figure). ) Obtain equipment operating data; operation two, send a shutdown operation instruction to the operation processor 152;

The operation processor 152 determines the operation strategy according to the results generated by the specified operation to ensure that the control processor 11 obtains correct control parameters. The results generated by the specified operation include: whether the equipment operation data is obtained and whether the shutdown operation instruction is received. Strategies include at least one of the following methods:

Method 1: interrupt the operation of relevant control parameters;

Method 2: Stop sending the relevant control parameters that have been calculated to the control processor 151 .

It can be understood that, according to the technical solution provided by this embodiment, during the control process of a dual-processor device, if the control processor detects the occurrence of an arc, it can stop the operation processor from obtaining the device operation data, and can also send a notification to the operation processor. Shutdown operation instruction; the operation processor can determine whether to interrupt the relevant control parameter operation operation based on whether it obtains the device operation data or whether it receives the shutdown operation instruction, or to stop sending the completed calculated related control to the control processor. Parameters to ensure that the control processor obtains correct control parameters to ensure arc generation. When the control processor turns off the circuit, the data between the two processors can maintain better accuracy and stop the PID operation in a timely manner to avoid prolonged shutdown. shutdown timing, and at the same time reduce the situation of discarding data, to avoid that when one end of the circuit is shut down, the other end is still executing, causing the overall circuit to run erratically, as long as the PID adjustment is not started. Body computing can interrupt the operation or not send the operation parameters of the completed operation. It is suitable for instructions, handshaking or sharing data. When shutting down, the data is frozen to ensure the stability and stability of data transmission between the control processor and the operation processor. consistency to avoid controlling the processor circuitry when the other end

The arithmetic processor is still performing unnecessary operations, causing the overall circuit to run erratically, effectively ensuring the correctness of data between the control processor and the arithmetic processor when an arc occurs.

Example 16

As an improvement of Embodiment 15, the schematic diagram is the same as that of Figure 18. The present invention discloses another dual-processor device provided by the embodiment. The device includes:

Control the processor to perform specified operations if arc generation is detected, and the specified operations include at least one of the following operations:

Operation 1: Stop the processor being processed from obtaining device operating data;

Operation 2: Send a shutdown operation instruction to the operation processor;

The operation processor determines the operation strategy according to the results generated by the specified operation to ensure that the control processor 21 obtains the correct control parameters. The results generated by the specified operation include: whether the equipment operation data is obtained and whether the shutdown operation instruction is received, the operation strategy Including at least one of the following methods:

Method 1: interrupt the operation of relevant control parameters;

Method 2: Stop sending the relevant control parameters that have been calculated to the control processor.

In some optional embodiments, the control processor performs a shutdown operation while stopping the operation processor from obtaining device operating data.

It should be noted that as for the way in which the operation control module obtains the equipment operation data, the control processor can actively send the equipment operation data to the operation processor, or the operation processor can read the equipment operation data from the control processor. In the embodiment of the present invention, the control processor stops the operation processor from obtaining the device operation data. This can be understood as the control processor stopping actively sending the device operation data to the operation processor. It can also be understood as the operation processor stopping actively reading the operation processor's data. Equipment operating data.

In some optional embodiments, the device further includes a shared memory. The shared memory is provided with a shutdown indication flag. The status of the shutdown indication flag includes a shutdown state and a normal state. The control processor Sending a shutdown operation instruction to the operation processor includes: controlling the processor to perform a shutdown operation and setting the status of the shutdown instruction flag to the shutdown state. The operation processor obtains the status of the shutdown instruction flag from the shared memory and sets the shutdown instruction flag to the shutdown state. The off state is regarded as the off operation instruction.

In some optional embodiments, the control processor obtains device operating data from the computing processor through the shared memory; the computing processor obtains the device operating data from the shared memory and sends control parameters to the control processor through the shared memory.

In some optional embodiments, the control processor sends the shutdown operation instruction to the operation processor as:

The control processor sends a pre-shutdown output pre-handshake to the operation processor;

The operation processor receives the pre-shutdown output pre-handshake, stops relevant operation operations according to the pre-shutdown output pre-handshake, and sends a stop operation notification to the control processor after completing the operation of the received data;

The control processor performs a shutdown operation after receiving the stop operation notification sent by the operation processor.

In some optional embodiments, when the control processor detects that an arc is generated, if it queries that there are control parameters that have not been sent, it stops sending the control parameters that are currently not sent.

In some optional embodiments, if the operation processor does not obtain the device operation data sent by the control processor, it stops all current control parameter calculations.

In some optional embodiments, the control parameter operation includes a PID calculation stage and a digital-to-analog conversion stage in sequence. The operation processor determines the operation strategy based on the results generated by the specified operation. The operation processor receives the shutdown operation sent by the control processor. After the instruction, the current control parameter calculation progress is judged; if the relevant equipment operation data is obtained, and the analog-to-digital conversion has been started, but the PID calculation has not yet started, the PID calculation and subsequent digital-to-analog conversion will not be performed; if the relevant equipment operation data is obtained data, and the PID calculation has started, but the digital-analog operation has not yet started, then the current PID calculation is completed.

In some optional embodiments, the computing processor does not obtain the device operation data sent by the control processor, or the computing processor obtains a shutdown indication flag from the shared memory to indicate the shutdown state, and the computing processor enters a limited sleep state.

In some optional embodiments, after the computing processor stops relevant computing operations according to the pre-shutdown output pre-handshake, the computing processor enters a limited sleep state.

In some optional embodiments, a shared memory is also included. The shared memory is provided with a shutdown indication flag, and the status of the shutdown indication flag includes a shutdown state and a normal state; the control processor enters a limited sleep state after performing the shutdown operation. ; When the restart conditions are met, the control processor restarts, sets the shutdown indication flag in the shared memory to the normal state, and resumes sending the reacquired device operation data to the computing processor through the shared memory; the computing processor resumes Get the status of the shutdown indication flag in the shared memory.

In some optional embodiments, the control processor enters a limited sleep state after performing a shutdown operation;

The control processor, when the restart conditions are met, sends a restart pre-handshake to the computing processor. After receiving the recovery confirmation message fed back by the computing processor, it resumes obtaining the device operation data, and resumes the acquisition of device operation by the computing processor. Data; operation processor, receives the restart pre-handshake sent by the control processor, completes the recovery operation preparation according to the restart pre-handshake, and sends a recovery confirmation message to the control processor.

In some optional embodiments, the operation processor freezes the acquired equipment operation data during the arc generation before entering the limited sleep state; the control processor freezes the equipment operation data during the arc generation before entering the limited sleep state. Data freeze.

It can be understood that, according to the technical solution provided by this embodiment, during the control process of the dual-processor device, if the control processor block detects the occurrence of an arc, it can stop the operation processor from obtaining the device operation data, and can also send the operation data to the operation processor. Shutdown operation instruction; the operation processor can determine whether to interrupt the relevant control parameter operation operation based on whether it obtains the device operation data, or whether it receives the shutdown operation instruction, or to stop sending the completed calculated related control to the control processor. Parameters to ensure that the control processor obtains correct control parameters to ensure arc generation. When the control processor turns off the circuit, the data between the two processors can maintain better accuracy and stop the PID operation in a timely manner to avoid prolonged shutdown. Shut down timing, while reducing the situation of discarding data, to avoid that when one end of the circuit is shut down, the other end is still executing, causing the entire circuit to run erratically. As long as the overall PID operation has not started, the operation can be interrupted or the operation parameters of the completed operation can not be sent. Applicable During instruction, handshake or shared data, the data is frozen when it is shut down to ensure the stability and consistency of data transmission between the control processor and the operation processor, and to avoid that when the control processor circuit is shut down, the other end of the operation processor The processor is still performing unnecessary operations, causing the overall circuit to run erratically, effectively ensuring the correctness of data between the control processor and the operation processor when an arc occurs.

Example 17

As shown in Figure 22, an embodiment of the present invention also provides a method for controlling a dual-processor device. The method is used for a dual-processor device. The dual-processor includes a control processor and an arithmetic processor. The method is used for controlling the processor. The method includes:

S171: If an arc is detected, the control processor performs a specified operation. The specified operation includes at least one of the following operations: operation one, stop the operation processor from obtaining equipment operating data; operation two, send a notification to the operation processor. Break operation instructions;

S172: The operation processor determines the operation strategy based on the results generated by the specified operation to ensure that the control processor obtains correct control parameters. The results generated by the specified operation include: whether the device operating data is obtained and whether the shutdown operation instruction is received, the operation strategy Including at least one of the following methods: method one, interrupting the calculation operation of the relevant control parameters; method two, stopping sending the relevant control parameters that have been calculated to the control processor.

In some optional embodiments, the aforementioned specified operation also includes: controlling the processor to stop the operation processor from obtaining device operating data and performing a shutdown operation at the same time.

In some optional embodiments, the dual-processor device also includes a shared memory, and the shared memory is provided with a shutdown indication flag. The status of the shutdown indication flag includes a shutdown state and a normal state. In this solution, the control processor controls the operation process. The processor sends a shutdown operation instruction including: controlling the processor to perform a shutdown operation and setting the status of the shutdown instruction flag to the shutdown state, so that the operation processor obtains the status of the shutdown instruction flag from the shared memory and identifies the shutdown state. Indicates the shutdown operation.

In some optional embodiments, the control processor sends device operation data to the operation processor through the shared memory.

In some optional embodiments, the control processor sends a shutdown operation instruction to the operation processor as follows: the control processor sends a pre-shutdown output pre-handshake to the operation processor, and after receiving the stop operation notification sent by the operation processor , perform a shutdown operation, and the computing processor determines whether the device operation Row data determines operational strategies.

In some optional embodiments, the control processor enters a limited sleep state after performing the shutdown operation; the control processor restarts when the restart conditions are met, and sets the shutdown indication flag in the shared memory to the normal state, And resume sending the reacquired device operation data to the computing processor through the shared memory, or, when the restart conditions are met, the control processor sends a restart pre-handshake to the computing processor, and after receiving the recovery feedback from the computing processor After confirming the message, the acquisition of device operation data is resumed, and the operation processor is resumed to obtain device operation data.

It can be understood that, according to the technical solution provided by this embodiment, during the control process of a dual-processor device, if the control processor detects the occurrence of an arc, it can stop the operation processor from obtaining the device operation data, and can also send a notification to the operation processor. Shutdown operation instruction; the operation processor can determine whether to interrupt the relevant control parameter operation operation based on whether it obtains the device operation data, or whether it receives the shutdown operation instruction, or to stop sending the completed calculated relevant control parameters to the control processor. , to ensure that the control processor obtains correct control parameters and ensures arc generation. When the control processor turns off the circuit, the data between the two processors can maintain better accuracy and stop the PID operation in a timely manner to avoid prolonged shutdown. Timing, while reducing the situation of discarding data, to avoid that when one end of the circuit is turned off, the other end is still executing, causing the entire circuit to run erratically. As long as the overall PID operation has not started, the operation can be interrupted or the operation parameters of the completed operation can not be sent. It is suitable for Instructions, handshakes or shared data are frozen when the control processor is turned off to ensure the stability and consistency of data transmission between the control processor and the computing processor, and to prevent the other end of the computing processor from still being connected when the control processor circuit is turned off. When performing unnecessary operations, causing the overall circuit to run erratically, it effectively ensures the correctness of data between the control processor and the operation processor when an arc occurs.

Example 18

As shown in Figure 23, an embodiment of the present invention also provides a dual-processor device control method. The method is used in a dual-processor device. The dual-processor includes a control processor and an arithmetic processor. The method is used in an arithmetic processor. Methods include:

S181: The operation processor obtains the result generated after the control processor performs the specified operation. The specified operation includes at least one of the following operations: Operation 1, stop the operation processor from obtaining device operation data; Operation 2, send the operation data to the operation processor. Break operation instruction, specify the result of the operation Including whether the equipment operating data is obtained and whether a shutdown operation instruction is received;

S182: The operation processor determines the operation strategy based on the results generated by the specified operation to ensure that the control processor obtains correct control parameters. The operation strategy includes at least one of the following methods: Method 1, interrupt the relevant control parameter operation; Method 2, stop Sends the relevant control parameters that have been calculated to the control processor.

In some optional embodiments, the dual-processor device also includes a shared memory, and the shared memory is provided with a shutdown indication flag, and the status of the shutdown indication flag includes a shutdown state and a normal state; in this solution, the control processor performs a shutdown operation Then, the state of the shutdown indication flag is set to the shutdown state; the operation processor obtains the status of the shutdown indication flag from the shared memory, and identifies the shutdown state as the shutdown operation instruction.

In some optional embodiments, the computing processor obtains device operating data from the shared memory and sends control parameters to the control processor through the shared memory.

In some optional embodiments, if the control processor sends a pre-shutdown output pre-handshake to the arithmetic processor, the arithmetic processor receives the pre-shutdown output pre-handshake, and stops the correlation according to the pre-shutdown output pre-handshake. In the operation operation, after completing the operation of the received data, a stop operation notification is sent to the control processor, so that the control processor performs a shutdown operation after receiving the stop operation notice sent by the operation processor.

In some optional embodiments, if the operation processor fails to obtain the device operation data of the control processor, it stops all current control parameter calculations.

In some optional embodiments, the computing processor does not obtain the device operation data that controls the processor, or the computing processor obtains a shutdown indication flag from the shared memory to indicate the shutdown state, and the computing processor enters a limited sleep state.

In some optional embodiments, if the control processor sets the shutdown indication flag in the shared memory to a normal state and resumes sending the reacquired device operating data to the computing processor through the shared memory; the computing processor resumes acquiring the shared memory The state of the shutdown indication flag; or, after receiving the restart pre-handshake sent by the control processor, the operation processor completes preparations for resuming operation according to the restart pre-handshake and sends a recovery confirmation message to the control processor.

In some optional embodiments, the computing processor freezes the acquired equipment operating data during arc generation before entering a limited sleep state.

Example 19

To facilitate readers' understanding, the dual-processor device and its control method provided by embodiments of the present invention are described below through specific examples.

In this embodiment, CPUA serves as the control processor and CPUB serves as the operation processor. The two CPUs operate independently and control the respective connected control circuits and PID operation circuits. Dual CPU Through the provision of commands (COMMAND/ORDER), handshakes (SHAKE HANDS), flags (FLAG), or data sharing, CPUB can perform PID interrupt operations. The overall PID operation block is divided into three stages: analog-to-digital conversion stage, PID calculation stage and digital-to-analog conversion stage, namely DC-PID-DAC.

The overall PID control process is as follows:

1st timing:

CPUA transmits the necessary data for PID operation to CPUB;

CPUB obtains data for PID operation;

CPUA detects arc, sends shutdown instruction or rewrites FLAG;

CPUB obtains the instruction or FLAG and determines which stage to interrupt the operation based on the current operating status:

If it is between ADC and PID, stop the calculation after PID;

If the PID period reaches before the DAC, the operation is completed, but the operation data is not output.

or,

When CPUA decides to shut down, it does not send any data or information;

When CPUB does not obtain data or information from CPUA at the time when it obtains data;

Or directly interrupt all PID operations when data or information is not updated in the shared RAM.

Nth timing, integer N>1:

CPUA restarts the control circuit for power output;

CPUA transmits the necessary data for PID operation to CPUB;

CPUB obtains data for PID operation.

or,

CPUA restarts the control circuit for power output;

CPUA rewrites CPUA’s working FLAG in RAM;

CPUA transfers the necessary data for PID operation and writes it into RAM;

CPUB reads the working FLAG of CPUA in RAM and determines it as ENABLE;

CPUB reads RAM to obtain data for PID operation;

CPUB writes the circuit control parameters generated by the operation into RAM.

Example 19

Based on the same technical concept, embodiments of the present application also provide a computer device, including a memory and a processor. The memory stores a computer program. When the processor executes the computer program, it implements any of the above dual-processor device control. method.

Wherein, the memory includes at least one type of readable storage medium, and the readable storage medium includes flash memory, hard disk, multimedia card, card-type memory (for example, SD or DX memory, etc.), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory may be an internal storage unit of the OTT video service monitoring system, such as a hard disk. In other embodiments, the memory can also be an external storage device of the OTT video service monitoring system, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash memory card ( Flash Card), etc.

Further, the memory may also include both an internal storage unit of the OTT video service monitoring system and an external storage device. The memory can not only be used for storage and installation in OTT video service monitoring The application software and various data of the control system, such as the code of the OTT video service monitoring program, can also be used to temporarily store the data that has been output or will be output.

In some embodiments, the processor may be a central processing unit (Central Processing Unit, processor), a controller, a microcontroller, a microprocessor or other data processing chips, used to run program codes stored in the memory or process data. , such as executing OTT video service monitoring programs, etc.

Disclosed embodiments of the present invention also provide a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is run by a processor, it executes the dual-processor device control method described in the above method embodiment. A step of. Wherein, the storage medium may be a volatile or non-volatile computer-readable storage medium. The computer program product of the dual-processor device control method provided by the disclosed embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the dual-processor device described in the above method embodiment. For details about the steps of the processor device control method, please refer to the above method embodiments and will not be described again here.

Disclosed embodiments of the present invention also provide a computer program, which when executed by a processor, implements any of the methods in the foregoing embodiments. The computer program product can be implemented specifically through hardware, software or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a Software Development Kit (SDK). etc.

It can be understood that the same or similar parts in the above-mentioned embodiments can be referred to each other, and the content that is not described in detail in some embodiments can be referred to the same or similar content in other embodiments.

It should be noted that in the description of the present invention, the terms "first", "second", etc. are only used for description purposes and cannot be understood as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise stated, the meaning of "plurality" means at least two.

Any process or method descriptions in flowcharts or otherwise described herein may be understood to represent modules, segments, or portions of code that include one or more executable instructions for implementing the specified logical functions or steps of the process. , and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed out of the order shown or discussed, including in a substantially simultaneous manner or in the reverse order, depending on the functionality involved, which shall It should be understood by those skilled in the art to which embodiments of the present invention belong.

It should be understood that various parts of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if it is implemented in hardware, as in another embodiment, it can be implemented by any one or a combination of the following technologies known in the art: a logic gate circuit with a logic gate circuit for implementing a logic function on a data signal. Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

Those of ordinary skill in the art can understand that all or part of the steps involved in implementing the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. The program can be stored in a computer-readable storage medium. When executed, one of the steps of the method embodiment or a combination thereof is included.

In addition, each functional unit in various embodiments of the present invention can be integrated into a processor, each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software function modules. If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

The storage media mentioned above can be read-only memory, magnetic disks or optical disks, etc.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above-mentioned embodiments are illustrative and should not be construed as limitations of the present invention. Those of ordinary skill in the art can make modifications to the above-mentioned embodiments within the scope of the present invention. The embodiments are subject to changes, modifications, substitutions and variations.

Claims

A dual-processor device control method, characterized in that the dual processors include a control processor and an arithmetic processor, the method is implemented by the control processor, and the method includes:

If an arc is detected, a pre-shutdown output pre-handshake is sent to the arithmetic processor, so that the arithmetic processor stops relevant computing operations according to the pre-shutdown output pre-handshake;

Receive a stop operation notification sent by the operation processor. The operation stop notice is issued after the operation processor receives the pre-shutdown output pre-handshake and completes the operation of the received data;

Perform shutdown operation.
The dual-processor device control method according to claim 1, characterized in that the method further includes:

When the restart condition is met, send a restart pre-handshake to the computing processor, so that the computing processor resumes computing preparations according to the restart pre-handshake;

After receiving the recovery confirmation message fed back by the computing processor, resume obtaining the device operation data, and resume sending the device operation data to the computing processor. The recovery confirmation message is after the computing processor completes the computing preparation. Sent.
The dual-processor device control method according to claim 2, characterized in that, before sending a restart pre-handshake to the computing processor, it further includes:

Determine whether the computing processor is in a sleep state;

The step of sending a restart pre-handshake to the arithmetic processor is: if the arithmetic processor is in a sleep state, sending a restart pre-handshake to the arithmetic processor.
The dual-processor device control method according to claim 3, characterized in that, before sending a restart pre-handshake to the computing processor, it further includes:

If the computing processor is not in the sleep state, the device operation data is directly obtained and sent to the computing processor.
The dual-processor device control method according to claim 2, characterized in that: Restart conditions include:

Whether the shutdown time meets the preset shutdown time;

and/or, whether a restart instruction message is received.
The dual-processor device control method according to claim 5, further comprising:

After performing the shutdown operation, it enters the sleep state.
The dual-processor device control method according to claim 6, wherein before entering the sleep state, the method further includes: freezing the device operating data during arc generation.
A control processor for a dual-processor device, characterized by including:

A pre-shutdown indication module is used to send a pre-shutdown output pre-handshake to the arithmetic processor when an arc is detected, so that the arithmetic processor stops relevant operations according to the pre-shutdown output pre-handshake. operate;

A pre-shutdown execution module, configured to receive a stop operation notification sent by the arithmetic processor. The stop arithmetic notification is after the arithmetic processor receives the pre-shutdown output pre-handshake and completes the received data. Emitted after the operation;

Shutdown module, used to perform shutdown operations.
A dual-processor device control method, characterized in that the dual-processor includes a control processor and an arithmetic processor, the method is implemented by the arithmetic processor, and the method includes:

Receive the pre-shutdown output pre-handshake sent by the control processor;

After completing the operation of the received data, stop the relevant operation;

Send a stop operation notification to the control processor, so that the control processor performs a shutdown operation after receiving the stop operation notification.
The dual-processor device control method according to claim 9, further comprising:

Receive a restart pre-handshake sent by the control processor;

Complete recovery operation preparations according to the pre-restart handshake;

Send a recovery confirmation message to the control processor so that the control processor resumes obtaining device operating data according to the recovery confirmation message;

Receive the device operation data sent by the control processor.
The dual-processor device control method according to claim 9 or 10, characterized in that, after sending the stop operation notification to the control processor, the method further includes: entering a sleep state.
The dual-processor device control method according to claim 11, wherein before entering the sleep state, the method further includes: freezing the device operating data during arc generation.
An arithmetic processor for a dual-processor device, characterized by including:

The pre-shutdown indication receiving module is used to receive the pre-shutdown output pre-handshake sent by the control processor;

The operation stop control module is used to stop related operation operations after completing the operation of the received data;

The operation stop notification module is configured to send a stop operation notification to the control processor, so that the control processor performs a shutdown operation after receiving the operation stop notification.
A dual-processor device, characterized by comprising the control processor for the dual-processor device of claim 8 and the arithmetic processor for the dual-processor device of claim 13.
A method for controlling a dual-processor device, characterized in that the dual-processor device includes a control processor, an arithmetic processor and a shared memory, the shared memory is provided with a shutdown indication flag, and the method is processed by the control processor Implemented by the processor, the methods include:

If an arc is detected, a shutdown operation is performed;

The shutdown indication flag in the shared memory is set to a shutdown state, so that the computing processor skips obtaining the first device operation data according to the state of the shutdown indication flag, and the first device operation data is the equipment operating data obtained by the control processor during arc generation.
The dual-processor device control method according to claim 15, characterized in that: Before the arc is detected, the method further includes:

Obtain the second device operating data;

Send the second device operating data to the computing processor through the shared memory.
The dual-processor device control method according to claim 16, wherein sending the second device operating data to the computing processor through the shared memory includes:

The second device operation data is stored in the shared memory so that the computing processor can obtain the second device operation data from the shared memory.
The method for controlling a dual-processor device according to claim 17, wherein after performing a shutdown operation, the method further includes: entering a sleep state.
The dual-processor device control method according to claim 18, characterized in that the method further includes:

Restart when the restart conditions are met;

Set the shutdown indication flag in the shared memory to a normal state;

Resume obtaining the operating data of the second device;

Resume sending the second device operating data to the computing processor through the shared memory, so that the computing processor obtains the second device operating data from the shared memory according to the state identified by the shutdown indication.
The dual-processor device control method according to claim 19, wherein the restart condition includes:

Whether the shutdown time meets the preset shutdown time;

and/or, whether a restart instruction message is received.
The dual-processor device control method according to claim 20, wherein before entering the sleep state, the method further includes: freezing the device operating data during arc generation.
A dual-processor device, characterized in that the dual-processor device includes a control processor, an arithmetic processor and a shared memory, the shared memory is provided with a shutdown indication flag, and the control processor includes:

A shutdown indication module is used to perform a shutdown operation when an arc is detected;

A shutdown state setting module, configured to set the shutdown indication flag in the shared memory to a shutdown state, so that the computing processor skips acquiring the first device operating data according to the status of the shutdown indication flag. , the first equipment operating data is equipment operating data obtained by the control processor during arc generation.
A method for controlling a dual-processor device, characterized in that the dual-processor device includes a control processor, an arithmetic processor and a shared memory, and a shutdown indication flag is provided in the shared memory. The method is performed by the arithmetic processor. Implementation, the method includes:

Obtain the status of the shutdown indication flag in the shared memory;

If the shutdown indication flag is in the shutdown state, the acquisition of the first equipment operation data is skipped according to the status of the shutdown indication flag. The first equipment operation data is obtained by the control processor during arc generation. Equipment operating data.
A dual-processor device control method according to claim 23, further comprising:

If the shutdown indication flag is in a normal state, obtain the first device operating data from the shared memory;

Calculate control parameters based on the first equipment operating data;

The calculated control parameters are sent to the control processor via the shared memory.
A dual-processor device control method according to claim 24, further comprising: entering a sleep state when the shutdown indication mark is in a shutdown state.
A dual-processor device control method according to claim 24, characterized in that before obtaining the status of the shutdown indication flag in the shared memory, the method further includes:

Restart when the restart conditions are met;

The step of obtaining the status of the shutdown indication flag in the shared memory is to restore and obtain the status of the shutdown indication flag in the shared memory.
A dual-processor device control method according to claim 25, characterized in that, before entering the sleep state, the method further includes: operating the device during arc generation. Data freeze.
A dual-processor device, characterized in that the dual-processor device includes a control processor, an arithmetic processor and a shared memory, the shared memory is provided with a shutdown indication flag, and the arithmetic processor includes:

A shutdown identification acquisition module, configured to obtain the status of the shutdown indication identification in the shared memory;

A shutdown data processing module, configured to, if the shutdown indication flag is in a shutdown state, skip acquiring the first device operation data according to the status of the shutdown indication flag, and the first device operation data is the control Equipment operating data acquired by the processor during arc generation.
A dual-processor device, characterized in that it includes a shared memory, the control processor of claim 22 and the operation processor of claim 28, and a shutdown indication flag is provided in the shared memory.
A computer device, characterized in that it includes: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the computer device is running, the connection between the processor and the memory is communicate through a bus, and when the machine-readable instructions are executed by the processor, the dual-processor device control method according to one of claims 1 to 7, 9 to 12, 15 to 21, or 23 to 27 is performed.
A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and the computer program is executed when the processor is run as claimed in claims 1 to 7, 9 to 12, 15 to 21 or 23 to The dual-processor device control method described in one of 27.