CN115168079A - Dual-processor device and control method thereof - Google Patents
Dual-processor device and control method thereof Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4418—Suspend and resume; Hibernate and awake
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/442—Shutdown
Abstract
The present disclosure provides a dual processor apparatus and a control method thereof, wherein the method includes: if the occurrence of the arc is detected, controlling the processor to execute a turn-off operation; and the turn-off indication mark in the shared memory is set to be in a turn-off state, the operation processor skips obtaining first equipment operation data according to the state of the turn-off indication mark, and the first equipment operation data is the equipment operation data obtained by the control processor during the generation of the electric arc, so that the problem of data correctness between the control processor and the operation processor caused by the asynchrony of the control processor and the operation processor in the prior art is solved.
Description
Technical Field
The invention relates to the technical field of equipment control, in particular to dual-processor equipment and a control method thereof.
Background
In a conventional PID control scheme based on dual processors, a processor a is used for controlling a circuit and detecting an arc, a processor B performs PID calculation to provide a control circuit operation parameter for the processor a, and performs DISABLE control (DISABLE) when the processor a detects the arc, immediately turns off the circuit or stops signal output, but the PID calculation cannot be interrupted, so that, when the processor a performs the DISABLE control, the processor B continues to perform PID calculation and feeds back the control circuit operation parameter to the processor a, and for the processor a, the operation parameter fed back by the processor B is redundant, useless and erroneous, and in addition, the DISABLE control of the processor a is abrupt, the operation parameter fed back by the processor B may not enable the processor a to connect with subsequent monitoring data, so that the whole control data set fails.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the problem in the prior art that when PID control is performed between two processors, the control circuit of the control processor immediately executes an interrupt, and the arithmetic processor continues to perform PID operation, resulting in data correctness between the control processor and the arithmetic processor. Thereby providing a dual processor apparatus and a control method thereof.
To solve the above technical problem, the disclosed embodiments of the present invention at least provide a dual-processor device and a control method thereof.
In a first aspect, an embodiment disclosed in the present invention provides a method for controlling a dual-processor device, where the dual-processor device includes a control processor, an arithmetic processor, and a shared memory, where the shared memory is provided with a shutdown indicator, and the method is implemented by the control processor, and the method includes:
if the arc is detected to occur, executing a turn-off operation;
and setting the turn-off indication mark in the shared memory to be in a turn-off state, so that the arithmetic processor skips acquiring first equipment operation data according to the state of the turn-off indication mark, wherein the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation.
Optionally, before the detecting that the arc occurs, the method further comprises: acquiring second equipment operation data; and sending the second equipment operation data to the operation processor through the shared memory.
Optionally, the sending, by the shared memory, the second device operation data to the arithmetic processor includes: and storing the second device operation data into the shared memory so that the operation processor can acquire the second device operation data from the shared memory.
Optionally, after performing the shutdown operation, the method further includes: entering a sleep state.
Optionally, the method further comprises: restarting when the restarting condition is met; setting a shutdown indication mark in the shared memory to be in a normal state; recovering and acquiring the second equipment operation data; and resuming to send the second device operating data to the arithmetic processor through the shared memory, so that the arithmetic processor acquires the second device operating data from the shared memory according to the state of the turn-off indication identifier.
Optionally, the restart condition includes: whether the turn-off time meets the preset turn-off duration or not; and/or whether restart indication information is received.
Optionally, before the entering the sleep state, the method further comprises: the plant operating data during arc generation is frozen.
In a second aspect, an embodiment of the present disclosure further provides a method for controlling a dual-processor device, where the dual-processor device includes a control processor arithmetic processor and a shared memory, and a shutdown indicator is set in the shared memory, and the method is implemented by the arithmetic processor, and the method includes:
acquiring the state of the turn-off indication mark in the shared memory;
and if the turn-off indication mark is in a turn-off state, skipping to acquire first equipment operation data according to the state of the turn-off indication mark, wherein the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation period.
Optionally, the method further comprises: if the turn-off indication mark is in a normal state, acquiring first equipment operation data from the shared memory; calculating control parameters according to the first equipment operation data; and sending the calculated control parameters to the control processor through the shared memory.
Optionally, the method further comprises: and entering a dormant state when the turn-off indication mark is in the turn-off state.
Optionally, before the obtaining the state of the shutdown indication identifier in the shared memory, the method further includes: restarting when the restarting condition is met; the state of the turn-off indication mark in the shared memory is acquired as follows: and recovering and acquiring the state of the shutdown indication mark in the shared memory.
Optionally, before the entering the sleep state, the method further comprises: the equipment operating data during arc generation is frozen.
In a third aspect, an embodiment of the present disclosure further provides a dual-processor device, where the dual-processor device includes a control processor, an arithmetic processor, and a shared memory, where the shared memory is provided with a shutdown indicator, and the control processor includes:
the shutdown indicating module is used for executing shutdown operation when the occurrence of the electric arc is detected;
and the turn-off state setting module is used for setting the turn-off indication identifier in the shared memory to be in a turn-off state so that the arithmetic processor can skip to acquire first equipment operation data according to the state of the turn-off indication identifier, wherein the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation period.
In a fourth aspect, an embodiment of the present disclosure further provides a dual-processor device, where the dual-processor device includes a control processor, an arithmetic processor, and a shared memory, where the shared memory is provided with a shutdown indicator, and the arithmetic processor includes:
a shutdown indicator obtaining module, configured to obtain a state of the shutdown indicator in the shared memory;
and the turn-off data processing module is used for skipping to acquire first equipment operation data according to the state of the turn-off indication mark if the turn-off indication mark is in the turn-off state, wherein the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation period.
In a fourth aspect, an embodiment of the disclosure further provides a dual-processor device, including a shared memory, a control processor in the dual-processor device, and an operation processor in the dual-processor device, where the shared memory is provided with a shutdown indicator.
In a fifth aspect, an embodiment of the present disclosure further provides a computer device, including: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating via the bus when the computer device is running, the machine-readable instructions when executed by the processor performing the steps of the first aspect, the second aspect, or any possible implementation of the first aspect or the second aspect.
In a sixth aspect, the disclosed embodiments of the present invention further provide a computer-readable storage medium, where a computer program is stored, and the computer program is executed by a processor to perform the steps in the first aspect or any one of the possible implementation manners of the first aspect.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
in the PID control process based on the dual processors, if the control processor detects that an electric arc occurs, a turn-off operation is executed; the shutdown indication mark in the shared memory is set to be in a shutdown state, the operation processor skips over to obtain the equipment operation data obtained by the control processor during the arc generation period according to the state of the shutdown indication mark, and the data sharing mode that even if one CPU is written into the generation region for protection, the other CPU can still read is utilized through the shared memory, so that the CPUs of the two parties can obtain the changed data and the working state of the other CPU from the high-speed storage unit at the first time when executing any operation, the stability and the consistency of data transmission between the control processor and the operation processor are ensured, the operation processor at the other end can be prevented from executing unnecessary operation when the circuit of the control processor is shut down, the disordered operation of the whole circuit is caused, and the data correctness between the control processor and the operation processor is effectively ensured when the arc is generated.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart illustrating a dual processor device control method provided by a disclosed embodiment of the invention;
FIG. 2 is a flow chart illustrating another dual-processor device control method provided by the disclosed embodiment of the invention;
FIG. 3 is a flow chart illustrating a method for controlling a dual processor device according to an embodiment of the present disclosure;
FIG. 4 is a flow chart illustrating yet another dual processor device control method provided by the disclosed embodiments;
FIG. 5 is a schematic diagram illustrating a control processor in a dual processor device according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram illustrating an architecture of an arithmetic processor in another dual-processor device according to an embodiment of the disclosure;
FIG. 7 is a schematic diagram illustrating a dual processor device architecture provided by the disclosed embodiments;
FIGS. 8, 9, and 10 are timing diagrams illustrating a method for controlling a dual processor device according to a disclosed embodiment of the invention;
fig. 11 shows a schematic structural diagram of a computer device according to an embodiment of the disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.
Example 1
As shown in fig. 1, a flowchart of a method for controlling a dual-processor device according to an embodiment of the present disclosure is provided, where the dual-processor device includes a control processor, an arithmetic processor, and a shared memory, and the shared memory is provided with a shutdown indicator, and the method is implemented by the control processor, and the method includes:
s11: if the arc is detected to occur, executing a turn-off operation;
s12: and setting the turn-off indication mark in the shared memory to be in a turn-off state so that the arithmetic processor skips acquiring first equipment operation data according to the state of the turn-off indication mark, wherein the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation.
It can be understood that, in the PID control process based on the dual processor, if the control processor detects that an arc occurs, the shutdown operation is performed according to the technical solution provided in this embodiment; the shutdown indication mark in the shared memory is set to be in a shutdown state, the operation processor skips over to obtain the equipment operation data obtained by the control processor during the arc generation period according to the state of the shutdown indication mark, and the data sharing mode which can be still read by the CPU of the other party even if the CPU of one party writes in the generation region protection is utilized through the shared memory, so that the CPUs of the two parties can obtain the changed data and the working state of the CPU of the other party from the high-speed storage unit at the first time when executing any operation, the stability and the consistency of data transmission between the control processor and the operation processor are ensured, the phenomenon that the operation processor of the other party still executes unnecessary operation when the circuit of the control processor is shut down is avoided, the integral circuit is disordered to run, and the data correctness between the control processor and the operation processor is effectively ensured when the arc is generated.
Example 2
As an improvement of embodiment 1, as shown in fig. 2, a flowchart of another method for controlling a dual-processor device according to an embodiment of the present disclosure is provided, where the dual-processor device includes a control processor, an arithmetic processor, and a shared memory, and a shutdown indicator is set in the shared memory, and the method is implemented by the control processor, and the method includes:
s21: the control processor acquires the second equipment operation data;
s22: the control processor sends second equipment operation data to the operation processor through the shared memory;
s23: if the occurrence of the arc is detected, controlling the processor to execute a turn-off operation;
s24: the control processor sets a turn-off indication mark in the shared memory to be in a turn-off state, so that the arithmetic processor skips acquiring first equipment operation data according to the state of the turn-off indication mark, wherein the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation period;
s25: the control processor freezes the device operating data during arc generation;
s26: controlling the processor to enter a sleep state;
s27: when the restarting condition is met, controlling the processor to restart;
s28: the control processor sets the shutdown indication flag in the shared memory to a normal state, and resumes executing S21.
In some alternative embodiments, the control processor stores the second device operating data in the shared memory so that the computing processor can retrieve the second device operating data from the shared memory.
In some optional embodiments, the restart condition comprises: whether the turn-off time meets the preset turn-off duration or not; and/or whether restart indication information is received.
It should be noted that the embodiments described in the present embodiment are only exemplary descriptions of specific implementations under the concept of the present invention, the execution sequence of the steps in each embodiment is not limited to the embodiments provided herein, and in specific engineering practice, a person skilled in the art may adjust the execution sequence of each step according to actual situations, for example, there is no necessary causal relationship and precedence relationship between S21 and S27, and the restart operation of S27 may also be described as after the second device operation data is acquired in S21.
It can be understood that, in the PID control process based on the dual processors, if the control processor detects that an arc occurs, the shutdown operation is performed; the shutdown indication mark in the shared memory is set to be in a shutdown state, the operation processor skips over to obtain the equipment operation data obtained by the control processor during the arc generation period according to the state of the shutdown indication mark, and the data sharing mode which can be still read by the CPU of the other party even if the CPU of one party writes in the generation region protection is utilized through the shared memory, so that the CPUs of the two parties can obtain the changed data and the working state of the CPU of the other party from the high-speed storage unit at the first time when executing any operation, the stability and the consistency of data transmission between the control processor and the operation processor are ensured, the phenomenon that the operation processor of the other party still executes unnecessary operation when the circuit of the control processor is shut down is avoided, the integral circuit is disordered to run, and the data correctness between the control processor and the operation processor is effectively ensured when the arc is generated.
Example 3
As shown in fig. 3, an embodiment of the present invention further provides a method for controlling a dual-processor device, where the dual-processor device includes an arithmetic processor of a control processor and a shared memory, and a shutdown indicator is set in the shared memory, and the method is implemented by the arithmetic processor, and the method includes:
s31: acquiring the state of a turn-off indication mark in a shared memory;
s32: and if the turn-off indication mark is in the turn-off state, skipping to acquire first equipment operation data according to the state of the turn-off indication mark, wherein the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation.
It can be understood that, in the PID control process based on the dual processors, if the control processor detects that an arc occurs, the shutdown operation is performed; the shutdown indication mark in the shared memory is set to be in a shutdown state, the operation processor skips over to obtain the equipment operation data obtained by the control processor during the arc generation period according to the state of the shutdown indication mark, and the data sharing mode that even if one CPU is written into the generation region for protection, the other CPU can still read is utilized through the shared memory, so that the CPUs of the two parties can obtain the changed data or working state of the other CPU from the high-speed storage unit at the first time when executing any operation, the stability and consistency of data transmission between the control processor and the operation processor are ensured, the operation processor at the other end can be prevented from executing unnecessary operation when the circuit of the control processor is shut down, the disordered operation of the whole circuit is caused, and the data correctness between the control processor and the operation processor is effectively ensured when the arc is generated.
Example 4
As an improvement of embodiment 3, as shown in fig. 4, an embodiment of the present invention further provides a method for controlling a dual-processor device, where the dual-processor device includes a control processor arithmetic processor and a shared memory, and the shared memory is provided with a shutdown indicator, where the method is implemented by the arithmetic processor, and the method includes:
s41: when the restarting condition is met, restarting the arithmetic processor, and resuming to execute S42;
s42: the operation processor acquires the state of a turn-off indication mark in the shared memory;
s43: if the turn-off indication mark is in a normal state, the operation processor acquires the running data of the first equipment from the shared memory;
s44: the operation processor calculates control parameters according to the first equipment operation data;
s45: the operation processor sends the calculated control parameters to the control processor through the shared memory;
s46: if the turn-off indication mark is in a turn-off state, the operation processor skips acquiring first equipment operation data according to the state of the turn-off indication mark, wherein the first equipment operation data is equipment operation data acquired by the control processor during the arc generation period;
s47: the arithmetic processor freezes the equipment operation data during the arc generation;
s48: and when the shutdown indication mark is in a shutdown state, the operation processor enters a dormant state and waits for the triggering of a restart condition.
It can be understood that, in the PID control process based on the dual processors, if the control processor detects that an arc occurs, the shutdown operation is performed; the shutdown indication mark in the shared memory is set to be in a shutdown state, the operation processor skips over to obtain the equipment operation data obtained by the control processor during the arc generation period according to the state of the shutdown indication mark, and the data sharing mode that even if one CPU is written into the generation region for protection, the other CPU can still read is utilized through the shared memory, so that the CPUs of the two parties can obtain the changed data and the working state of the other CPU from the high-speed storage unit at the first time when executing any operation, the stability and the consistency of data transmission between the control processor and the operation processor are ensured, the operation processor at the other end can be prevented from executing unnecessary operation when the circuit of the control processor is shut down, the disordered operation of the whole circuit is caused, and the data correctness between the control processor and the operation processor is effectively ensured when the arc is generated.
Example 5
An embodiment of the present invention further provides a dual-processor device, where the dual-processor device includes a control processor, an arithmetic processor, and a shared memory, and a shutdown indicator is set in the shared memory, as shown in fig. 5, where the control processor includes:
and a shutdown indication module 51, configured to perform a shutdown operation when the occurrence of the arc is detected.
And the turn-off state setting module 52 is configured to set the turn-off indication flag in the shared memory to the turn-off state, so that the arithmetic processor skips acquiring the first device operation data according to the state of the turn-off indication flag, where the first device operation data is the device operation data acquired by the control processor during the arc generation.
In some alternative embodiments, as shown in the dotted line part, the apparatus may further include:
and an operation data obtaining module 53, configured to obtain second device operation data.
And an operation data sending module 54, configured to send the second device operation data to the operation processor through the shared memory, resume obtaining, and send the second device operation data to the operation processor through the shared memory, so that the operation processor obtains the second device operation data from the shared memory according to the state of the shutdown indicator.
A first data freezing module 55 for freezing the device operating data during arc generation.
A first hibernate module 56 for entering a hibernate state.
A first restarting module 57, configured to restart when a restarting condition is satisfied.
And a shared flag setting module 58, configured to set the shutdown indication flag in the shared memory to a normal state.
In some optional embodiments, the restart condition comprises: whether the turn-off time meets the preset turn-off duration or not; and/or whether restart indication information is received.
It can be understood that, in the PID control process based on the dual processor, if the control processor detects that an arc occurs, the shutdown operation is performed according to the technical solution provided in this embodiment; the shutdown indication mark in the shared memory is set to be in a shutdown state, the operation processor skips over to obtain the equipment operation data obtained by the control processor during the arc generation period according to the state of the shutdown indication mark, and the data sharing mode that even if one CPU is written into the generation region for protection, the other CPU can still read is utilized through the shared memory, so that the CPUs of the two parties can obtain the changed data and the working state of the other CPU from the high-speed storage unit at the first time when executing any operation, the stability and the consistency of data transmission between the control processor and the operation processor are ensured, the operation processor at the other end can be prevented from executing unnecessary operation when the circuit of the control processor is shut down, the disordered operation of the whole circuit is caused, and the data correctness between the control processor and the operation processor is effectively ensured when the arc is generated.
Example 6
An embodiment of the present invention further provides a dual-processor device, where the dual-processor device includes a control processor, an arithmetic processor, and a shared memory, and a turn-off indicator is set in the shared memory, as shown in fig. 6, where the arithmetic processor includes:
and a shutdown flag obtaining module 61, configured to obtain a state of a shutdown indication flag in the shared memory.
And a shutdown data processing module 62, configured to skip obtaining first device operation data according to the state of the shutdown indication flag if the shutdown indication flag is in the shutdown state, where the first device operation data is device operation data obtained by the control processor during the arc generation.
In some alternative embodiments, as shown in phantom, the apparatus further comprises:
and the running data extracting module 63 is configured to, if the shutdown indicator is in a normal state, obtain the running data of the first device from the shared memory, and after the shutdown indicator is restarted, resume obtaining the state of the shutdown indicator in the shared memory.
And the control parameter operation module 64 is used for calculating the control parameters according to the first equipment operation data.
And a control parameter sending module 65, configured to send the calculated control parameter to the control processor through the shared memory.
A second sleep module 66 for entering a sleep state when the shutdown indication is identified as the shutdown state.
And a second restart module 67, configured to restart when a restart condition is met.
A second data freezing module 68 for freezing the plant operating data during arc generation.
It can be understood that, in the PID control process based on the dual processors, if the control processor detects that an arc occurs, the shutdown operation is performed; the shutdown indication mark in the shared memory is set to be in a shutdown state, the operation processor skips over to obtain the equipment operation data obtained by the control processor during the arc generation period according to the state of the shutdown indication mark, and the data sharing mode which can be still read by the CPU of the other party even if the CPU of one party writes in the generation region protection is utilized through the shared memory, so that the CPUs of the two parties can obtain the changed data and the working state of the CPU of the other party from the high-speed storage unit at the first time when executing any operation, the stability and the consistency of data transmission between the control processor and the operation processor are ensured, the phenomenon that the operation processor of the other party still executes unnecessary operation when the circuit of the control processor is shut down is avoided, the integral circuit is disordered to run, and the data correctness between the control processor and the operation processor is effectively ensured when the arc is generated.
Example 7
As shown in fig. 7, an embodiment of the present invention further provides a dual-processor device, which includes a shared memory 71, a control processor 72 and an operation processor 73 in the dual-processor device, where the shared memory 71 is provided with a shutdown indicator.
For the convenience of the reader to understand, the following describes in detail the dual-processor apparatus with reference to the timing diagrams of fig. 8, fig. 9, and fig. 10, CPUA is a control processor, CPUB is an operation processor, RAM is a shared memory, and FLAG is an off indication FLAG:
in a general mode, the dual-processor device PID control comprises the following processes:
the CPUA does not detect the electric arc, and does not rewrite the working FLAG of the CPUA in the RAM;
CPUA transmits PID operation necessary data to be written into RAM;
CPUB reads the working FLAG of CPUA in RAM and judges the working FLAG as ENABLE;
the CPUB reads the RAM to obtain data and carries out PID operation;
the CPUB writes the circuit control parameters generated by operation into the RAM;
the cpu reads the RAM acquisition parameters to control circuit operation and power output.
With the shared stored pattern, dual processor device PID control includes the following processes:
timing sequence 1:
detecting an electric arc by using the CPUA, and rewriting a working FLAG of the CPUA in the RAM to DISABLE;
the CPUA executes the shutdown output;
CPUB reads the working FLAG of CPUA in RAM and judges it as DISABLE;
CPUB does not read RAM and does not perform PID operation of the current time sequence.
Further, data may be frozen, CPUB or dual CPU may enter limited sleep.
At the time of the Nth time sequence, N >1 integer:
the CPUA restarts the control circuit to output power;
the CPUA rewrites the working FLAG of the CPUA in the RAM;
CPUA transmits PID operation necessary data to be written into RAM;
CPUB reads the working FLAG of CPUA in RAM and judges the working FLAG as ENABLE;
the CPUB reads the RAM to obtain data and carries out PID operation;
CPUB writes the circuit control parameters generated by the operation into RAM.
It can be understood that, in the PID control process based on the dual processors, if the control processor detects that an arc occurs, the shutdown operation is performed; the shutdown indication mark in the shared memory is set to be in a shutdown state, the operation processor skips over to obtain the equipment operation data obtained by the control processor during the arc generation period according to the state of the shutdown indication mark, and the data sharing mode which can be still read by the CPU of the other party even if the CPU of one party writes in the generation region protection is utilized through the shared memory, so that the CPUs of the two parties can obtain the changed data and the working state of the CPU of the other party from the high-speed storage unit at the first time when executing any operation, the stability and the consistency of data transmission between the control processor and the operation processor are ensured, the phenomenon that the operation processor of the other party still executes unnecessary operation when the circuit of the control processor is shut down is avoided, the integral circuit is disordered to run, and the data correctness between the control processor and the operation processor is effectively ensured when the arc is generated.
Example 8
Based on the same technical concept, an embodiment of the present application further provides a computer device, which includes a memory 1 and a processor 2, as shown in fig. 11, where the memory 1 stores a computer program, and the processor 2 implements the dual-processor device control method described in any one of the above when executing the computer program.
The memory 1 includes at least one type of readable storage medium, which includes a flash memory, a hard disk, a multimedia card, a card type memory (e.g., SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, and the like. The memory 1 may in some embodiments be an internal storage unit of the OTT video traffic monitoring system, e.g. a hard disk. The memory 1 may also be an external storage device of the OTT video service monitoring system in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory 1 may also include both an internal storage unit and an external storage device of the OTT video service monitoring system. The memory 1 may be used to store not only application software installed in the OTT video service monitoring system and various data, such as codes of OTT video service monitoring programs, but also temporarily store data that has been output or is to be output.
The processor 2 may be a Central Processing Unit (cpu), a controller, a microcontroller, a microprocessor or other data Processing chip in some embodiments, and is used to execute program codes stored in the memory 1 or process data, such as executing OTT video service monitoring programs.
It can be understood that, in the PID control process based on the dual processors, if the control processor detects that an arc occurs, the shutdown operation is performed; the shutdown indication mark in the shared memory is set to be in a shutdown state, the operation processor skips over to obtain the equipment operation data obtained by the control processor during the arc generation period according to the state of the shutdown indication mark, and the data sharing mode that even if one CPU is written into the generation region for protection, the other CPU can still read is utilized through the shared memory, so that the CPUs of the two parties can obtain the changed data and the working state of the other CPU from the high-speed storage unit at the first time when executing any operation, the stability and the consistency of data transmission between the control processor and the operation processor are ensured, the operation processor at the other end can be prevented from executing unnecessary operation when the circuit of the control processor is shut down, the disordered operation of the whole circuit is caused, and the data correctness between the control processor and the operation processor is effectively ensured when the arc is generated.
The disclosed embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program executes the steps of the dual-processor device control method described in the above method embodiment. The storage medium may be a volatile or non-volatile computer-readable storage medium.
The computer program product of the dual-processor device control method provided in the embodiments disclosed in the present invention includes a computer readable storage medium storing a program code, where instructions included in the program code may be used to execute the steps of the dual-processor device control method described in the above method embodiments, which may be specifically referred to the above method embodiments and are not described herein again.
The disclosed embodiments also provide a computer program which, when executed by a processor, implements any one of the methods of the preceding embodiments. The computer program product may be embodied in hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK), or the like.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried out in the method of implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (17)
1. A dual-processor device control method is characterized in that the dual-processor device comprises a control processor, an operation processor and a shared memory, wherein a turn-off indication mark is arranged in the shared memory, the method is realized by the control processor, and the method comprises the following steps:
if the arc is detected to occur, executing a turn-off operation;
and setting the turn-off indication identifier in the shared memory to be in a turn-off state, so that the arithmetic processor skips acquiring first equipment operation data according to the state of the turn-off indication identifier, wherein the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation.
2. The dual-processor device control method of claim 1, wherein prior to the detecting an arc occurrence, the method further comprises:
acquiring second equipment operation data;
and sending the second device operation data to the operation processor through the shared memory.
3. The dual-processor device control method according to claim 2, wherein the sending the second device operation data to the arithmetic processor through the shared memory comprises:
and storing the second device operation data into the shared memory so that the operation processor can acquire the second device operation data from the shared memory.
4. The dual-processor device control method according to claim 3, wherein after performing a shutdown operation, the method further comprises: entering a sleep state.
5. The dual-processor device control method of claim 4, further comprising:
restarting when the restarting condition is met;
setting a shutdown indication mark in the shared memory to be in a normal state;
recovering and acquiring the second equipment operation data;
and resuming to send the second device operating data to the arithmetic processor through the shared memory, so that the arithmetic processor can acquire the second device operating data from the shared memory according to the state of the turn-off indication identifier.
6. The dual-processor device control method according to claim 5, wherein the restart condition includes:
whether the turn-off time meets the preset turn-off duration or not; and/or the presence of a gas in the atmosphere,
whether restart indication information is received.
7. The dual-processor device control method of claim 6, wherein prior to the entering the sleep state, the method further comprises: the equipment operating data during arc generation is frozen.
8. A dual-processor device control method is characterized in that the dual-processor device comprises a control processor operation processor and a shared memory, wherein a turn-off indication mark is arranged in the shared memory, the method is realized by the operation processor, and the method comprises the following steps:
acquiring the state of the turn-off indication mark in the shared memory;
and if the turn-off indication mark is in a turn-off state, skipping to acquire first equipment operation data according to the state of the turn-off indication mark, wherein the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation period.
9. The dual-processor device control method according to claim 8, further comprising:
if the turn-off indication mark is in a normal state, acquiring first equipment operation data from the shared memory;
calculating control parameters according to the first equipment operation data;
and sending the calculated control parameters to the control processor through the shared memory.
10. The dual-processor device control method according to claim 9, further comprising: and entering a dormant state when the turn-off indication mark is in the turn-off state.
11. The dual-processor device control method according to claim 9, wherein prior to said obtaining the state of the shutdown indication flag in the shared memory, the method further comprises:
restarting when the restarting condition is met;
the state of the turn-off indication mark in the shared memory is acquired as follows: and recovering and acquiring the state of the shutdown indication mark in the shared memory.
12. The dual-processor device control method according to claim 10, wherein before said entering into the sleep state, the method further comprises: the equipment operating data during arc generation is frozen.
13. A dual processor device, comprising a control processor, an arithmetic processor, and a shared memory, wherein a shutdown indicator is provided in the shared memory, the control processor comprising:
the turn-off indicating module is used for executing turn-off operation when the occurrence of the electric arc is detected;
and the turn-off state setting module is used for setting the turn-off indication identifier in the shared memory to be in a turn-off state, so that the operation processor skips acquiring first equipment operation data according to the state of the turn-off indication identifier, wherein the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation period.
14. A dual processor device, comprising a control processor, an arithmetic processor, and a shared memory, wherein a shutdown indicator is provided in the shared memory, and wherein the arithmetic processor comprises:
a shutdown indicator obtaining module, configured to obtain a state of the shutdown indicator in the shared memory;
and the turn-off data processing module is used for skipping to acquire first equipment operation data according to the state of the turn-off indication mark if the turn-off indication mark is in the turn-off state, wherein the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation period.
15. A dual processor device comprising a shared memory in which a shutdown indicator is set, a control processor according to claim 13, and an arithmetic processor according to claim 14.
16. A computer device, comprising: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating over the bus when a computer device is operating, the machine-readable instructions when executed by the processor performing the dual-processor device control method of any one of claims 1 to 12.
17. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, performs a dual-processor apparatus control method as claimed in any one of claims 1 to 12.
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| CN202211094823.6A CN115168079B (en) | 2022-09-08 | 2022-09-08 | Dual-processor device and control method thereof |
| PCT/CN2023/112998 WO2024051450A1 (en) | 2022-09-08 | 2023-08-15 | Dual-processor device and control method therefor, and processor |
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Address after: 518102 Room 101, 201, 301, Building B, Functional Support Area, Taohuayuan Zhichuang Town, Tiegang Community, Xixiang Street, Baoan District, Shenzhen, Guangdong Province Patentee after: Shenzhen Hengyunchang Vacuum Technology Co.,Ltd. Address before: Room 101, 201, 301, Building B, Functional Supporting Area, Taohuayuan Zhichuang Town, Tiegang Community, Xixiang Street, Baoan District, Shenzhen, Guangdong 518100 Patentee before: SHENZHEN HENGYUNCHANG VACUUM TECHNOLOGY CO.,LTD. |