CN115167933B - Dual-processor equipment, control method thereof and processor - Google Patents
Dual-processor equipment, control method thereof and processor Download PDFInfo
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- CN115167933B CN115167933B CN202211094813.2A CN202211094813A CN115167933B CN 115167933 B CN115167933 B CN 115167933B CN 202211094813 A CN202211094813 A CN 202211094813A CN 115167933 B CN115167933 B CN 115167933B
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- 238000000034 method Methods 0.000 title claims abstract description 88
- 238000010891 electric arc Methods 0.000 claims abstract description 9
- 238000011084 recovery Methods 0.000 claims description 23
- 230000009977 dual effect Effects 0.000 claims description 22
- 238000012790 confirmation Methods 0.000 claims description 17
- 230000007958 sleep Effects 0.000 claims description 17
- 238000002360 preparation method Methods 0.000 claims description 13
- 238000004590 computer program Methods 0.000 claims description 12
- 230000008569 process Effects 0.000 description 13
- 230000005540 biological transmission Effects 0.000 description 9
- 238000012544 monitoring process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000008014 freezing Effects 0.000 description 4
- 238000007710 freezing Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 230000005059 dormancy Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 208000022249 Sleep-Wake Transition disease Diseases 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4418—Suspend and resume; Hibernate and awake
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1438—Restarting or rejuvenating
Abstract
The application discloses a dual-processor device, a control method thereof and a processor, wherein the dual-processor device comprises a control processor and an operation processor, the method is realized by the control processor, and the method comprises the following steps: if the electric arc is detected to occur, sending pre-turn-off output pre-handshake to the operation processor so that the operation processor stops relevant operation according to the pre-turn-off output pre-handshake; receiving a stop operation notification sent by the operation processor, wherein the stop operation notification is sent after the operation processor receives the pre-shutdown output pre-handshake and completes the operation of received data; and the shutdown operation is executed, so that the problem of data correctness between the control processor and the arithmetic processor caused by asynchronism of the control processor and the arithmetic processor in the prior art is solved.
Description
Technical Field
The invention relates to the technical field of equipment control, in particular to dual-processor equipment, a control method thereof and a processor.
Background
In a conventional dual-processor apparatus control scheme, a processor a is used for controlling a circuit and detecting an arc, a processor B performs PID calculation to provide a control circuit operation parameter for the processor a, and performs DISABLE control (DISABLE) when the processor a detects the arc, immediately turns off the circuit or stops signal output, but the PID calculation cannot be interrupted, so that, when the processor a performs the DISABLE control, the processor B continues to perform PID calculation and feeds back the control circuit operation parameter to the processor a, and for the processor a, the operation parameter fed back by the processor B is redundant, useless and erroneous, and the DISABLE control of the processor a is abrupt, the operation parameter fed back by the processor B may not link subsequent monitoring data, so that the entire control data set fails.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the problem in the prior art that when PID control is performed between two processors, the control circuit of the control processor immediately executes an interrupt, and the arithmetic processor continues to perform PID operation, resulting in data correctness between the control processor and the arithmetic processor. Thus, a dual processor apparatus, a control method thereof, and a processor are provided.
To solve the foregoing technical problem, an embodiment of the present disclosure at least provides a dual-processor device, a control method thereof, and a processor.
In a first aspect, an embodiment disclosed in the present invention provides a method for controlling a dual-processor device, where the dual-processor device includes a control processor and an operation processor, and the method is implemented by the control processor, and the method includes:
if the electric arc is detected to occur, sending pre-turn-off output pre-handshake to the operation processor so that the operation processor stops relevant operation according to the pre-turn-off output pre-handshake;
receiving a computation stopping notification sent by the computation processor, wherein the computation stopping notification is sent after the computation processor receives the pre-shutdown output pre-handshake and completes the computation of received data;
a shutdown operation is performed.
Optionally, before the detecting that the arc occurs, the method further comprises: when a restarting condition is met, sending a restarted preposed handshake to the operation processor so that the operation processor can restore operation preparation according to the restarted preposed handshake; and after receiving a recovery confirmation message fed back by the operation processor, recovering to acquire equipment operation data, and recovering to send the equipment operation data to the operation processor, wherein the recovery confirmation message is sent after the operation processor finishes operation preparation.
Optionally, before the sending the restarted pre-handshake to the operation processor, the method further includes: judging whether the operation processor is in a dormant state or not; the sending of the restarted pre handshake to the arithmetic processor is as follows: and if the operation processor is in a dormant state, sending a restarted preposed handshake to the operation processor.
Optionally, before the sending the restarted pre-handshake to the operation processor, the method further includes: and if the operation processor is not in the dormant state, directly acquiring and sending the equipment operation data to the operation processor.
Optionally, the restart condition includes: whether the turn-off time meets the preset turn-off duration or not; and/or whether restart indication information is received.
Optionally, the method further comprises: after the shutdown operation is performed, a sleep state is entered.
Optionally, before the entering the sleep state, the method further comprises: the equipment operating data during arc generation is frozen.
In a second aspect, a dual processor apparatus control method, the dual processor including a control processor and an operation processor, the method being implemented by the operation processor, the method comprising:
receiving pre-turn-off output pre-handshake sent by the control processor;
stopping the related operation after finishing the operation of the received data;
and sending a stop operation notification to the control processor so that the control processor executes shutdown operation after receiving the stop operation notification.
Optionally, the method further comprises: receiving a restarted preposed handshake sent by the control processor; completing recovery operation preparation according to the restarted preposed handshake; sending a recovery confirmation message to the control processor so that the control processor can recover and acquire the equipment operation data according to the recovery confirmation message; and receiving the operation data of the equipment sent by the control processor.
Optionally, after the sending of the stop operation notification to the control processor, the method further includes: entering a sleep state.
Optionally, before the entering the sleep state, the method further comprises: the equipment operating data during arc generation is frozen.
In a third aspect, an embodiment of the present disclosure further provides a control processor for a dual-processor device, including:
the pre-turn-off indicating module is used for sending pre-turn-off output pre-handshake to the operation processor when the occurrence of electric arc is detected, so that the operation processor stops related operation according to the pre-turn-off output pre-handshake;
the pre-shutdown execution module is used for receiving a computation stopping notification sent by the computation processor, wherein the computation stopping notification is sent after the computation processor receives the pre-shutdown output pre-handshake and completes the computation of received data;
and the turn-off module is used for executing turn-off operation.
In a fourth aspect, an embodiment of the present disclosure further provides an operation processor for a dual-processor device, including:
the pre-turn-off indication receiving module is used for receiving pre-turn-off output pre-handshake sent by the control processor;
the operation stopping control module is used for stopping related operation after completing the operation of the received data;
and the operation stop notification module is used for sending a stop operation notification to the control processor so that the control processor executes shutdown operation after receiving the stop operation notification.
In a fourth aspect, the disclosed embodiments of the present invention further provide a dual-processor device, which includes the aforementioned control processor for the dual-processor device and the aforementioned operation processor for the dual-processor device.
In a fifth aspect, an embodiment of the present disclosure further provides a computer device, including: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating via the bus when the computer device is running, the machine-readable instructions when executed by the processor performing the steps of the first aspect, the second aspect, or any possible implementation of the first aspect or the second aspect.
In a fourth aspect, the disclosed embodiments of the present invention further provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and the computer program is executed by a processor to perform the steps in the first aspect or any possible implementation manner of the first aspect.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
in the control process of the dual-processor equipment, if the control processor detects that an electric arc occurs, the control processor sends pre-turn-off output pre-handshake to the operation processor, the operation processor completes the operation of received data according to the pre-turn-off output pre-handshake and stops related operation, the control processor executes turn-off operation after receiving a stop operation notification sent by the operation processor, and through the handshake, the stability and consistency of data transmission between the control processor and the operation processor are ensured, the phenomenon that the operation processor at the other end still executes unnecessary operation when a circuit of the control processor is turned off to cause disordered operation of the whole circuit is avoided, and the data correctness between the control processor and the operation processor is effectively ensured when the electric arc occurs.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart illustrating a method for controlling a dual processor device in accordance with a disclosed embodiment of the invention;
FIG. 2 is a flow chart illustrating another dual-processor device control method provided by the disclosed embodiment of the invention;
FIGS. 3, 4, 5, and 6 are schematic diagrams illustrating interaction and timing of a control processor and an arithmetic processor in accordance with embodiments of the present disclosure;
FIG. 7 is a flow chart illustrating a method for controlling a dual processor device according to an embodiment of the present disclosure;
FIG. 8 is a flow chart illustrating a method for controlling a dual processor device according to yet another embodiment of the present disclosure;
FIG. 9 is a block diagram of a control processor for a dual processor device according to an embodiment of the disclosure;
FIG. 10 is a schematic diagram illustrating an architecture of an arithmetic processor for a dual processor device according to an embodiment of the present disclosure;
FIG. 11 is a schematic diagram illustrating an architecture of a dual processor device according to an embodiment of the present disclosure;
fig. 12 shows a schematic structural diagram of a computer device according to an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the summary of the invention.
Example 1
As shown in fig. 1, a flowchart of a method for controlling a dual-processor device according to an embodiment of the present disclosure is provided, where the dual processor device includes a control processor and an operation processor, and the method is implemented by the control processor, and the method includes:
s11: if the arc is detected to occur, sending pre-turn-off output pre-handshake to the operation processor so that the operation processor stops relevant operation according to the pre-turn-off output pre-handshake;
s12: receiving a stop operation notification sent by the operation processor, wherein the stop operation notification is sent after the operation processor receives the pre-shutdown output pre-handshake and completes the operation of received data;
s13: a shutdown operation is performed.
It can be understood that, in the technical scheme provided in this embodiment, in the control process of the dual-processor device, if the control processor detects that an arc occurs, the control processor sends a pre-shutdown output pre-handshake to the operation processor, the operation processor completes the operation of received data according to the pre-shutdown output pre-handshake and stops related operation, the control processor executes a shutdown operation after receiving a stop operation notification sent by the operation processor, and through the handshake, the stability and consistency of data transmission between the control processor and the operation processor are ensured, thereby avoiding that the operation processor at the other end still executes unnecessary operation when a circuit of the control processor is shut down, which causes a disordered operation of an entire circuit, and effectively ensuring the correctness of data between the control processor and the operation processor when the arc occurs.
Example 2
As an improvement of embodiment 1, as shown in fig. 2, a flowchart of another dual-processor apparatus control method provided in the embodiment of the present disclosure is a method for controlling a dual-processor apparatus, where the dual-processor apparatus includes a control processor and an operation processor, and the method is implemented by the control processor, and the method includes:
s21: when the restarting condition is met, the control processor judges whether the operation processor is in a dormant state, if the operation processor is in the dormant state, S22 is executed, and if the operation processor is not in the dormant state, S24 is executed;
s22: the control processor sends the restarted preposed handshake to the operation processor so that the operation processor recovers operation preparation according to the restarted preposed handshake;
s23: the control processor receives a recovery confirmation message fed back by the operation processor, and the S24 is recovered to be executed, wherein the recovery confirmation message is sent after the operation processor finishes operation preparation;
s24: the control processor acquires equipment operation data and sends the equipment operation data to the operation processor;
s25: if the electric arc is detected to occur, the control processor sends pre-turn-off output pre-handshake to the operation processor, so that the operation processor stops related operation according to the pre-turn-off output pre-handshake;
s26: the control processor receives a stop operation notification sent by the operation processor, wherein the stop operation notification is sent after the operation processor receives the pre-turn-off output pre-handshake and completes the operation of received data;
s27: controlling the processor to perform a shutdown operation;
s28: the control processor freezes the device operating data during arc generation;
s29: the control processor enters a sleep state.
In some optional embodiments, the restart condition comprises: whether the turn-off time meets the preset turn-off duration or not; and/or whether restart indication information is received.
Further, the data may be frozen, CPUB alone or CPUA and CPUB simultaneously go to a limited degree of dormancy.
It should be noted that, the embodiments described in the present embodiment are only exemplary descriptions of specific implementations under the concept of the present invention, and the execution order of the steps in each embodiment is not limited to the embodiments provided herein, and in specific engineering practice, a person skilled in the art may adjust the execution order of each step according to actual situations, for example, there is no necessary causal relationship and precedence relationship between S21 and S27, and the restart operation of S21 may also be described as after the shutdown operation of S27.
For the convenience of reader understanding, in the following, referring to fig. 3, fig. 4, fig. 5, and fig. 6, cpua is used as a control processor, and CPUB is used as an operation processor, and details of the interaction process and the timing relationship of the dual-processor device control method in the embodiment of the present invention are described:
timing sequence 1:
the CPUA transmits PID operation necessary data to the CPUB;
the CPUB acquires data to perform PID operation;
the CPUA detects the electric arc and sends a pre-handshake of pre-turn-off output;
the PID operation of the CPUB completes the received correct data and returns the correct data to the CPUA;
the CPUB feeds back the stopped time sequence PID operation preparation to the CPUA according to handshaking;
the CPUA acquires the feedback of the CPUB and executes the cut-off output;
the CPUA discards the timing-fed PID data.
The Nth time sequence, N >1 integer, is divided into two conditions of CUPB dormancy and CUPB dormancy:
1. case of CPUB without sleep:
the CPUA restarts the control circuit to output power;
CPUA transmits PID operation necessary data to CPUB;
and the CPUB acquires data to perform PID operation.
2. Case of CPUB sleep
The CPUA outputs the restarted preposed handshake;
the CPUB feeds back that the CPUA is ready to finish;
the CPUA transmits PID operation necessary data to the CPUB;
and the CPUB acquires data to perform PID operation.
It can be understood that, in the technical solution provided in this embodiment, in the control process of the dual-processor device, if the control processor detects that an arc occurs, the control processor sends a pre-shutdown output pre-handshake to the operation processor, the operation processor completes the operation of the received data and stops the related operation according to the pre-shutdown output pre-handshake, the control processor executes a shutdown operation after receiving a stop operation notification sent by the operation processor, and by handshaking, stability and consistency of data transmission between the control processor and the operation processor are ensured, so as to avoid that the operation processor at the other end still executes unnecessary operation when the control processor is turned off, which causes a whole circuit to run in a disorderly manner, and effectively ensure data correctness between the control processor and the operation processor when the arc occurs.
Example 3
As shown in fig. 7, an embodiment of the present invention further provides a dual-processor device control method, where a dual processor includes a control processor and an arithmetic processor, and the method is implemented by the arithmetic processor, and the method includes:
s71: receiving pre-turn-off output pre-handshake sent by a control processor;
s72: stopping the related operation after finishing the operation of the received data;
s73: and sending a stop operation notification to the control processor so that the control processor executes a shutdown operation after receiving the stop operation notification.
It can be understood that, in the technical scheme provided in this embodiment, in the control process of the dual-processor device, if the control processor detects that an arc occurs, the control processor sends a pre-shutdown output pre-handshake to the operation processor, the operation processor completes the operation of received data according to the pre-shutdown output pre-handshake and stops related operation, the control processor executes a shutdown operation after receiving a stop operation notification sent by the operation processor, and through the handshake, the stability and consistency of data transmission between the control processor and the operation processor are ensured, thereby avoiding that the operation processor at the other end still executes unnecessary operation when a circuit of the control processor is shut down, which causes a disordered operation of an entire circuit, and effectively ensuring the correctness of data between the control processor and the operation processor when the arc occurs.
Example 4
As an improvement of embodiment 3, as shown in fig. 8, an embodiment of the present invention further provides a dual-processor device control method, where a dual processor includes a control processor and an arithmetic processor, and the method is implemented by the arithmetic processor, and the method includes:
s81: the operation processor receives pre-turn-off output pre-handshake sent by the control processor;
s82: after the operation of the received data is completed, the operation processor stops the related operation;
s83: the arithmetic processor freezes the equipment operation data during the arc generation;
s84: the operation processor sends an operation stopping notification to the control processor, so that the control processor executes a shutdown operation after receiving the operation stopping notification;
s85: the operation processor enters a dormant state;
s86: the operation processor receives a restarted preposed handshake sent by the control processor;
s87: the operation processor completes the preparation of recovery operation according to the restarted preposed handshake;
s88: the operation processor sends a recovery confirmation message to the control processor so that the control processor recovers and acquires the equipment operation data according to the recovery confirmation message;
s89: and the operation processor receives the equipment operation data sent by the control processor.
It can be understood that, in the technical scheme provided in this embodiment, in the control process of the dual-processor device, if the control processor detects that an arc occurs, the control processor sends a pre-shutdown output pre-handshake to the operation processor, the operation processor completes the operation of received data according to the pre-shutdown output pre-handshake and stops related operation, the control processor executes a shutdown operation after receiving a stop operation notification sent by the operation processor, and through the handshake, the stability and consistency of data transmission between the control processor and the operation processor are ensured, thereby avoiding that the operation processor at the other end still executes unnecessary operation when a circuit of the control processor is shut down, which causes a disordered operation of an entire circuit, and effectively ensuring the correctness of data between the control processor and the operation processor when the arc occurs.
Example 5
As shown in fig. 9, an embodiment of the present invention further provides a control processor for a dual-processor device, including:
the pre-turn-off indicating module 91 is configured to send a pre-turn-off output pre-handshake to the operation processor when an arc is detected, so that the operation processor stops a related operation according to the pre-turn-off output pre-handshake;
the pre-shutdown execution module 92 is configured to receive a computation stopping notification sent by the computation processor, where the computation stopping notification is sent after the computation processor receives the pre-shutdown output pre-handshake and completes the computation of the received data;
and a shutdown module 93, configured to perform a shutdown operation.
In some alternative embodiments, as shown in phantom, the control processor further comprises:
a restart handshake module 94, configured to send a restarted pre-handshake to the operation processor when a restart condition is met, so that the operation processor recovers operation preparation according to the restarted pre-handshake;
and a recovery confirmation module 95, configured to, after receiving a recovery confirmation message fed back by the operation processor, resume acquiring the device operation data, and resume sending the device operation data to the operation processor, if the operation processor is not in a sleep state, directly acquire the device operation data, and send the device operation data to the operation processor, where the recovery confirmation message is sent after the operation processor completes preparation for operation.
In some optional embodiments, as shown in the dotted line part, the control processor further comprises:
a first data freezing module 96 for freezing the device operating data during arc generation;
a first sleep start module 97, configured to control the processor to enter a sleep state after performing a shutdown operation;
the sleep determination module 98 is configured to determine whether the arithmetic processor is in a sleep state.
The restarting handshake module 94 sends the restarted pre-handshake to the operation processor, where the restarting pre-handshake is: if the arithmetic processor is in the sleep state, the restart handshake module 94 sends a restart pre-handshake to the arithmetic processor.
In some optional embodiments, the restart condition comprises: whether the turn-off time meets the preset turn-off duration or not; and/or whether restart indication information is received.
It can be understood that, in the technical scheme provided in this embodiment, in the control process of the dual-processor device, if the control processor detects that an arc occurs, the control processor sends a pre-shutdown output pre-handshake to the operation processor, the operation processor completes the operation of received data according to the pre-shutdown output pre-handshake and stops related operation, the control processor executes a shutdown operation after receiving a stop operation notification sent by the operation processor, and through the handshake, the stability and consistency of data transmission between the control processor and the operation processor are ensured, thereby avoiding that the operation processor at the other end still executes unnecessary operation when a circuit of the control processor is shut down, which causes a disordered operation of an entire circuit, and effectively ensuring the correctness of data between the control processor and the operation processor when the arc occurs.
Example 6
As shown in fig. 10, an embodiment of the present invention further provides an operation processor for a dual-processor device, including:
a pre-shutdown indication receiving module 101, configured to receive a pre-shutdown output pre-handshake sent by the control processor;
an operation stop control module 102, configured to stop a related operation after completing an operation on received data;
and the operation stop notification module 103 is configured to send a stop operation notification to the control processor, so that the control processor executes a shutdown operation after receiving the stop operation notification.
In some alternative embodiments, as shown in the dotted line, the operation processor further includes:
a second data freezing module 104 for freezing the device operation data during arc generation;
a second sleep start module 105, configured to enable the arithmetic processor to enter a sleep state;
a handshake receiving module 106, configured to receive a restarted pre-handshake sent by the control processor;
an operation recovery module 107, configured to complete recovery operation preparation according to the restarted pre-handshake;
and a recovery message sending module 108, configured to send a recovery confirmation message to the control processor, so that the control processor recovers to obtain the device operation data according to the recovery confirmation message, and recovers to send the device operation data.
And the device data receiving module 109 is configured to receive the device operation data sent by the control processor.
It can be understood that, in the technical scheme provided in this embodiment, in the control process of the dual-processor device, if the control processor detects that an arc occurs, the control processor sends a pre-shutdown output pre-handshake to the operation processor, the operation processor completes the operation of received data according to the pre-shutdown output pre-handshake and stops related operation, the control processor executes a shutdown operation after receiving a stop operation notification sent by the operation processor, and through the handshake, the stability and consistency of data transmission between the control processor and the operation processor are ensured, thereby avoiding that the operation processor at the other end still executes unnecessary operation when a circuit of the control processor is shut down, which causes a disordered operation of an entire circuit, and effectively ensuring the correctness of data between the control processor and the operation processor when the arc occurs.
Example 7
As shown in fig. 11, an embodiment of the present invention further provides a dual processor device, including the control processor for the dual processor device of embodiment 5 above and the operation processor for the dual processor device of embodiment 6 above.
It can be understood that, in the technical solution provided in this embodiment, in the control process of the dual-processor device, if the control processor detects that an arc occurs, the control processor sends a pre-shutdown output pre-handshake to the operation processor, the operation processor completes the operation of the received data and stops the related operation according to the pre-shutdown output pre-handshake, the control processor executes a shutdown operation after receiving a stop operation notification sent by the operation processor, and by handshaking, stability and consistency of data transmission between the control processor and the operation processor are ensured, so as to avoid that the operation processor at the other end still executes unnecessary operation when the control processor is turned off, which causes a whole circuit to run in a disorderly manner, and effectively ensure data correctness between the control processor and the operation processor when the arc occurs.
Example 8
Based on the same technical concept, an embodiment of the present application further provides a computer device, which includes a memory 1 and a processor 2, as shown in fig. 12, where the memory 1 stores a computer program, and the processor 2 implements any one of the dual-processor device control methods when executing the computer program.
The memory 1 includes at least one type of readable storage medium, which includes a flash memory, a hard disk, a multimedia card, a card type memory (e.g., SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, and the like. The memory 1 may in some embodiments be an internal storage unit of the OTT video traffic monitoring system, e.g. a hard disk. The memory 1 may also be an external storage device of the OTT video service monitoring system in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory 1 may also include both an internal storage unit and an external storage device of the OTT video service monitoring system. The memory 1 may be used to store not only application software installed in the OTT video service monitoring system and various data, such as codes of OTT video service monitoring programs, but also temporarily store data that has been output or is to be output.
The processor 2 may be a Central Processing Unit (cpu), a controller, a microcontroller, a microprocessor or other data Processing chip in some embodiments, and is used to execute program codes stored in the memory 1 or process data, such as executing OTT video service monitoring programs.
It can be understood that, in the technical scheme provided in this embodiment, in the control process of the dual-processor device, if the control processor detects that an arc occurs, the control processor sends a pre-shutdown output pre-handshake to the operation processor, the operation processor completes the operation of received data according to the pre-shutdown output pre-handshake and stops related operation, the control processor executes a shutdown operation after receiving a stop operation notification sent by the operation processor, and through the handshake, the stability and consistency of data transmission between the control processor and the operation processor are ensured, thereby avoiding that the operation processor at the other end still executes unnecessary operation when a circuit of the control processor is shut down, which causes a disordered operation of an entire circuit, and effectively ensuring the correctness of data between the control processor and the operation processor when the arc occurs.
The disclosed embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the dual-processor device control method described in the above method embodiment are executed. The storage medium may be a volatile or non-volatile computer-readable storage medium.
The computer program product of the dual-processor device control method provided in the embodiments disclosed in the present invention includes a computer readable storage medium storing a program code, where instructions included in the program code may be used to execute the steps of the dual-processor device control method described in the above method embodiments, which may be referred to in the above method embodiments specifically, and are not described herein again.
The embodiments disclosed herein also provide a computer program, which when executed by a processor implements any one of the methods of the preceding embodiments. The computer program product may be embodied in hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK) or the like.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar contents in other embodiments may be referred to for the contents which are not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (16)
1. A dual-processor device control method, wherein the dual processor includes a control processor and an arithmetic processor, the method being implemented by the control processor, the method comprising:
if the electric arc is detected to occur, sending pre-turn-off output pre-handshake to the operation processor so that the operation processor stops relevant operation according to the pre-turn-off output pre-handshake;
receiving a computation stopping notification sent by the computation processor, wherein the computation stopping notification is sent after the computation processor receives the pre-shutdown output pre-handshake and completes the computation of received data;
a shutdown operation is performed.
2. The dual-processor device control method according to claim 1, wherein after said performing a shutdown operation, the method further comprises:
when a restarting condition is met, sending a restarted preposed handshake to the operation processor so that the operation processor can restore operation preparation according to the restarted preposed handshake;
and after receiving a recovery confirmation message fed back by the operation processor, recovering to acquire the equipment operation data of the dual-processor equipment, and recovering to send the equipment operation data to the operation processor, wherein the recovery confirmation message is sent after the operation processor finishes operation preparation.
3. The dual-processor device control method according to claim 2, further comprising, before the sending of the restarted pre-handshake to the arithmetic processor:
judging whether the operation processor is in a dormant state or not;
the sending of the restarted pre-handshake to the arithmetic processor is as follows: and if the operation processor is in a dormant state, sending a restarted preposed handshake to the operation processor.
4. The dual-processor device control method according to claim 3, further comprising, before the sending of the restarted pre-handshake to the arithmetic processor:
and if the operation processor is not in the dormant state, directly acquiring the equipment operation data and sending the equipment operation data to the operation processor.
5. The dual-processor device control method according to claim 2, wherein the restart condition includes:
whether the turn-off time meets the preset turn-off duration or not; and/or the presence of a gas in the gas,
whether restart indication information is received.
6. The dual-processor device control method according to claim 5, further comprising:
after the shutdown operation is performed, a sleep state is entered.
7. The dual-processor device control method of claim 6, wherein prior to the entering the sleep state, the method further comprises: the equipment operating data during arc generation is frozen.
8. A dual-processor apparatus control method, wherein the dual processor includes a control processor and an arithmetic processor, the method being implemented by the arithmetic processor, the method comprising:
receiving pre-turn-off output pre-handshake sent by the control processor, wherein the pre-turn-off output pre-handshake is sent by the control processor after the control processor detects that an arc occurs;
stopping the related operation after finishing the operation of the received data;
and sending a stop operation notification to the control processor so that the control processor executes shutdown operation after receiving the stop operation notification.
9. The dual-processor device control method according to claim 8, further comprising, after said performing a shutdown operation:
receiving a restarted preposed handshake sent by the control processor;
completing recovery operation preparation according to the restarted preposed handshake;
sending a recovery confirmation message to the control processor so that the control processor recovers and acquires the equipment operation data of the dual-processor equipment according to the recovery confirmation message;
and receiving the equipment operation data sent by the control processor.
10. The dual-processor device control method according to claim 8 or 9, wherein after said sending a stop operation notification to said control processor, said method further comprises: entering a sleep state.
11. The dual-processor device control method of claim 10, wherein prior to the entering the sleep state, the method further comprises: the plant operating data during arc generation is frozen.
12. A control processor for a dual processor device, comprising:
the pre-turn-off indicating module is used for sending pre-turn-off output pre-handshake to the operation processor when the occurrence of electric arc is detected, so that the operation processor stops related operation according to the pre-turn-off output pre-handshake;
the pre-shutdown execution module is used for receiving a computation stopping notification sent by the computation processor, wherein the computation stopping notification is sent after the computation processor receives the pre-shutdown output pre-handshake and completes the computation of received data;
and the turn-off module is used for executing turn-off operation.
13. An arithmetic processor for a dual processor device, comprising:
the pre-turn-off indication receiving module is used for receiving pre-turn-off output pre-handshake sent by the control processor, wherein the pre-turn-off output pre-handshake is sent by the control processor after the control processor detects that an arc occurs;
the operation stopping control module is used for stopping related operation after completing the operation of the received data;
and the operation stop notification module is used for sending a stop operation notification to the control processor so that the control processor executes shutdown operation after receiving the stop operation notification.
14. A dual processor device comprising the control processor for a dual processor device of claim 12 and the operation processor for a dual processor device of claim 13.
15. A computer device, comprising: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating over the bus when a computer device is operating, the machine-readable instructions when executed by the processor performing the dual-processor device control method of any one of claims 1 to 11.
16. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, performs a dual-processor device control method as claimed in any one of claims 1 to 11.
Priority Applications (2)
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| CN202211094813.2A CN115167933B (en) | 2022-09-08 | 2022-09-08 | Dual-processor equipment, control method thereof and processor |
| PCT/CN2023/112998 WO2024051450A1 (en) | 2022-09-08 | 2023-08-15 | Dual-processor device and control method therefor, and processor |
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| CN202211094813.2A CN115167933B (en) | 2022-09-08 | 2022-09-08 | Dual-processor equipment, control method thereof and processor |
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| WO2024051450A1 (en) * | 2022-09-08 | 2024-03-14 | 深圳市恒运昌真空技术股份有限公司 | Dual-processor device and control method therefor, and processor |
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