WO2024051238A1 - 芯片封装结构及制备方法 - Google Patents

芯片封装结构及制备方法 Download PDF

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Publication number
WO2024051238A1
WO2024051238A1 PCT/CN2023/099210 CN2023099210W WO2024051238A1 WO 2024051238 A1 WO2024051238 A1 WO 2024051238A1 CN 2023099210 W CN2023099210 W CN 2023099210W WO 2024051238 A1 WO2024051238 A1 WO 2024051238A1
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Prior art keywords
chip
heat dissipation
substrate
dam structure
fixedly connected
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PCT/CN2023/099210
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English (en)
French (fr)
Inventor
陈彦亨
林正忠
杨进
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盛合晶微半导体(江阴)有限公司
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Publication of WO2024051238A1 publication Critical patent/WO2024051238A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials

Definitions

  • the present invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and a preparation method.
  • Integrated Circuit also known as chip
  • IC Integrated Circuit
  • the industry generally divides IC into digital chips, analog chips, memory chips, radio frequency chips, power chips, optical chips, passive chips, etc.
  • logic systems, computing systems, and communication systems composed of digital chips and memory chips have been leading the development of IC manufacturing and integration technology.
  • thermal interface material TIM
  • the current thermal interface material is mainly made of polymers, but this thermal interface material has Thermal conductivity is relatively poor, resulting in poor heat dissipation effect of the packaging structure.
  • the purpose of the present invention is to provide a chip packaging structure and a preparation method to solve the problem in the prior art that the semiconductor packaging structure has poor heat dissipation effect, resulting in reduced performance of the packaging structure.
  • the present invention provides a method for preparing a chip packaging structure.
  • the preparation method includes the following steps:
  • a dam structure is formed on the chip, the dam structure is sealed and fixedly connected to the chip, and the dam structure has a receiving cavity exposing the chip;
  • a heat dissipation component is formed on the thermal interface material layer, and the heat dissipation component is sealed and fixedly connected to the dam structure.
  • the method further includes the step of forming virtual chips on the substrate, the virtual chips being symmetrically distributed on both sides of the chip and fixedly connected to the substrate.
  • the material of the liquid metal includes one of gallium, indium or tin.
  • the dam structure is made of a flexible material, including one of foam, PDMS or EPDM.
  • the heat dissipation component includes a heat dissipation cover or a heat dissipation element
  • the heat dissipation element includes a heat dissipation base and heat dissipation fins evenly arranged on the heat dissipation base.
  • dam structure and the chip are sealed and fixedly connected through ultraviolet curing glue; the dam structure and the heat dissipation component are sealed and fixedly connected through ultraviolet curing glue.
  • the substrate includes a wafer level substrate.
  • the invention also provides a chip packaging structure, which includes:
  • a chip, the chip is located on the substrate and is electrically connected to the substrate;
  • Thermal interface material layer includes a dam structure and liquid metal, the dam structure is located on the chip and is sealed and fixedly connected to the chip, and the dam structure has a receiving cavity exposing the chip, Liquid metal is located in the containing cavity;
  • a heat dissipation component is formed on the thermal interface material layer, and the heat dissipation component is sealed and fixedly connected to the dam structure.
  • the chip packaging structure further includes virtual chips fixedly connected to the substrate and symmetrically distributed on both sides of the chip.
  • the heat dissipation component includes a heat dissipation cover or a heat dissipation element
  • the heat dissipation element includes a heat dissipation base and heat dissipation fins evenly arranged on the heat dissipation base.
  • the chip packaging structure includes a substrate, a chip, a thermal interface material layer and a heat dissipation component, wherein the chip is located on the substrate and is electrically connected to the substrate;
  • the thermal interface material layer includes a dam structure and liquid metal filled in a receiving cavity of the dam structure.
  • the dam structure is located on the chip and is sealed and fixedly connected to the chip.
  • the heat dissipation component Formed on the thermal interface material layer, and the heat dissipation component is sealed and fixedly connected to the dam structure, so that a heat sink containing liquid metal is formed between the heat dissipation component and the chip through the dam structure.
  • Interface material layer is provided on the thermal interface material layer, and the heat dissipation component is sealed and fixedly connected to the dam structure, so that a heat sink containing liquid metal is formed between the heat dissipation component and the chip through the dam structure.
  • the present invention reduces the thermal resistance of the package by introducing liquid metal as a thermal interface material, thereby greatly improving the thermal diffusion efficiency during the packaging process; the dam structure prepared by using flexible materials can prevent the overflow of liquid metal during the packaging and application process, thereby The probability of the electrical performance of the device being degraded thereby is reduced, and since the thermal interface material layer is sealed and fixed with UV curing glue, the disassembly and replacement process is simple and effective.
  • FIG. 1 shows a flow chart of a method for manufacturing a chip packaging structure in an embodiment of the present invention.
  • FIG. 2 shows a schematic cross-sectional view of a substrate provided for an embodiment of the present invention.
  • FIG. 3 shows a schematic cross-sectional view of a chip bonded according to an embodiment of the present invention.
  • FIG. 4 shows a schematic cross-sectional view after forming a virtual chip according to an embodiment of the present invention.
  • Figure 5 shows a schematic cross-sectional view of forming a UV curable glue according to an embodiment of the present invention.
  • FIG. 6 shows a schematic cross-sectional view after forming a thermal interface material layer according to an embodiment of the present invention.
  • FIG. 7 shows a schematic structural diagram of a chip packaging structure provided by an embodiment of the present invention.
  • FIG. 8 shows a schematic structural diagram of another chip packaging structure provided by an embodiment of the present invention.
  • Component label description 101 Substrate, 102: Chip, 103: Virtual chip, 104: UV curing glue, 105: Thermal interface material layer, 1051: Dam structure, 1052: liquid metal, 106: heat dissipation cover, 108: heat dissipation element, 1081: heat dissipation base, 1082: heat dissipation fins, S1 ⁇ S5: steps.
  • spatial relationship words such as “below”, “below”, “below”, “below”, “above”, “on”, etc. may be used herein to describe an element or element shown in the drawings.
  • a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • the present invention provides a method for preparing a chip packaging structure, which includes the following steps:
  • S3 Form a dam structure 1051 on the chip 102, the dam structure 1051 is sealed and fixedly connected to the chip 102, and the dam structure 1051 has a receiving cavity exposing the chip 102;
  • step S1 referring to Figures 1 and 2, a substrate 101 is provided.
  • the substrate 101 includes a wafer-level substrate.
  • the substrate 101 includes one of a silicon oxide substrate, a glass substrate, a ceramic substrate, and an organic substrate. Its shape can be circular, square, or any other desired shape, and its surface area can support subsequent packaging structures. allow.
  • an organic substrate with a low thermal expansion coefficient is selected as the substrate 101.
  • the organic substrate has a low thermal expansion coefficient, which can reduce warpage generated during the packaging process.
  • step S2 please refer to FIGS. 1 and 3 , a chip 102 is bonded on the substrate 101 , and the chip 102 is electrically connected to the substrate 101 .
  • the chip 102 can be any existing semiconductor chip suitable for packaging, and can be multiple chips of the same type or multiple different types, for example, it can be a system on a chip (SOC).
  • the device can also be a memory chip, such as HBM, etc., which is not limited here.
  • multiple chips 102 are generally packaged at the same time.
  • the number of chips 102 is shown as one, but the number of chips 102 is not limited to this. , the number of chips 102 may be greater than or equal to 1, such as 2, 3, 4 or more according to requirements.
  • the step of forming virtual chips 103 on the substrate 101 it also includes the step of forming virtual chips 103 on the substrate 101.
  • the virtual chips 103 are preferably symmetrically distributed on both sides of the chip 102 and are sealed and fixedly connected to the substrate 101, so as to The deformation of the packaging structure is reduced through the virtual chip 103.
  • the virtual chip 103 is a passive chip.
  • the virtual chip 103 is sealed and fixedly connected to the substrate 101.
  • the connection method is not limited to glue connection.
  • the number of virtual chips 103 is shown as 2, but the number of virtual chips 103 is not limited to this.
  • the number of virtual chips 103 can be greater than or equal to 2, such as 3, 4 or more according to requirements.
  • the step of forming the virtual chip 103 may be bonded to the substrate 101 before, after or simultaneously with the step of forming the chip 102, which is not limited here.
  • a dam structure 1051 is formed on the chip 102.
  • the dam structure 1051 is sealed and fixedly connected to the chip 102, and the dam structure 1051 is sealed and fixedly connected to the chip 102.
  • the structure 1051 has a receiving cavity exposing the chip 102 .
  • the dam structure 1051 is sealed and fixedly connected to the chip 102 and the virtual chip 103 through UV curing glue 104 .
  • An accommodating cavity is formed between the virtual chips 103, and the accommodating cavity can expose the chip 102 and the virtual chip 103 respectively.
  • the fixed connection method between the dam structure 1051 and the chip is to use the ultraviolet curing glue to seal and fix the connection, but the type of adhesive glue is not limited to this, and other methods can also be used. colloid.
  • the UV curing glue 104 may be placed above the chip 102 and the virtual chip 103 , and the dam structure 1051 is fixed on the chip 102 and the virtual chip 103 Above, the ultraviolet curing glue 104 is irradiated with ultraviolet light of the required wavelength. After being irradiated by the ultraviolet light, the ultraviolet curing glue 104 can be quickly solidified and formed, thereby sealing and fixing the dam structure 1051 above the corresponding chip. .
  • the dam structure 1051 when the dam structure 1051 needs to be repaired or removed, acetone or other solvents with the same function only need to be used to remove the UV curing glue 104, and the dam structure can be repaired or safely removed. 1051. During this process, no secondary damage will be caused to other parts.
  • the dam structure 1051 is made of a flexible material, including one of foam, PDMS (polydimethylsiloxane) or EPDM (ethylene propylene diene monomer).
  • the material of the dam structure 1051 is preferably PDMS, which has strong corrosion resistance, high dielectric strength and excellent compatibility with the chip 103 .
  • step S4 please refer to FIGS. 1 and 6 , liquid metal 1052 is filled into the accommodation cavity to combine with the dam structure 1051 to form a thermal interface material layer 105 on the chip 102 .
  • the accommodation cavity is filled with liquid metal 1052 .
  • the liquid metal 1052 and the dam structure 1051 jointly form the thermal interface material layer 105 .
  • the thermal interface material layer 105 The chip 102 and the virtual chip 103 are sealed and fixedly connected through the ultraviolet curing glue 104 .
  • the material of the liquid metal 1052 includes one of gallium, indium or tin.
  • gallium, indium or tin have thermal conductivity coefficients generally greater than 30W/(m ⁇ K). This value is higher than conventional polymer thermal interface materials, and they have lower contact thermal resistance and With certain fluidity, the liquid metal 1052 can reduce the thermal resistance of the package, thereby greatly improving the heat diffusion efficiency during the packaging process and improving the packaging quality.
  • step S5 please refer to FIGS. 1 , 7 and 8 , a heat dissipation component is formed on the thermal interface material layer 105 , and the heat dissipation component is sealed and fixedly connected to the dam structure 1051 .
  • the heat dissipation component may include a heat dissipation cover 106 or a heat dissipation element 108 , wherein the heat dissipation element 108 may include a heat dissipation base 1081 and a heat dissipation base 1081 on the heat dissipation base 1081 . Evenly arranged heat dissipation fins 1082.
  • the dam structure 1051 and the heat dissipation component are sealed and fixedly connected through the ultraviolet curing glue 104 .
  • the heat dissipation cover 106 when used as the heat dissipation component, it can be above the dam structure 1051, at the bottom of the side wall to be bonded with the substrate 101 in the heat dissipation cover 106, or at the corresponding
  • the surface of the substrate 101 is coated with the UV curing glue 104, and will be cured under the action of ultraviolet light, so that the top of the dam structure 1051 can be sealed and fixedly connected with the heat dissipation cover 106 to provide
  • the liquid metal 1052 provides sealing protection to prevent the liquid metal 1052 from overflowing.
  • the heat generated by the chip 102 can be directly conducted to the heat dissipation cover 106 through the liquid metal 1052 and transferred to the outside through the heat dissipation cover 106 to achieve the heat dissipation function.
  • the structural strength of the substrate 101 is greatly improved. Under the fixation effect, the surface can be kept flush to prevent the substrate 101 from warping.
  • the heat dissipation base 1081 in the heat dissipation element 108 is directly connected to the dam structure 1051 in a sealed and fixed manner, so that The liquid metal 1052 can directly contact the chip and the heat dissipation element 108 to achieve good heat dissipation.
  • it may include the step of dotting the ultraviolet curable glue 104 above the dam structure 1051.
  • the ultraviolet curable glue 104 will be cured under the action of ultraviolet light to realize the connection between the dam structure 1051 and the dam structure 1051.
  • the heat dissipation element 108 is sealed and fixedly connected to achieve sealing of the liquid metal 1052 and prevent the liquid metal 1052 from overflowing during packaging and use.
  • This embodiment provides a chip packaging structure, which includes:
  • Chip 102 the chip 102 is located on the substrate 101 and is electrically connected to the substrate 101;
  • Thermal interface material layer 105 includes a dam structure 1051 and liquid metal 1052.
  • the dam structure 1051 is located on the chip 102 and is sealed and fixedly connected to the chip 102, and the dam structure 1051 has a structure that exposes the chip.
  • the accommodation cavity of 102, the liquid metal 1052 is located in the accommodation cavity;
  • a heat dissipation component is formed on the thermal interface material layer 105 , and is sealed and fixedly connected to the dam structure 1051 .
  • the chip packaging structure is prepared by the above-mentioned preparation method, so as to the preparation of the chip packaging structure, the selection of materials, etc. , please refer to Embodiment 1 and will not be described in detail here.
  • the chip packaging structure further includes virtual chips 103 fixedly connected to the substrate 101 and symmetrically distributed on both sides of the chip 102 .
  • the heat dissipation component includes a heat dissipation cover 106 or a heat dissipation element 108.
  • the heat dissipation element 108 includes a heat dissipation base 1081 and heat dissipation elements evenly arranged on the heat dissipation base 1081. Fin 1082.
  • the heat dissipation base 1081 is sealed and fixedly connected to the thermal interface material layer 105 .
  • the present invention provides a chip packaging structure and a preparation method.
  • the chip packaging structure includes: a substrate; a chip, the chip is located on the substrate and is electrically connected to the substrate; a thermal interface material layer, Includes dam structure and fill In the liquid metal within the dam structure, the thermal interface material layer and the chip are sealed and fixedly connected through UV curing glue; a heat dissipation component is formed on the thermal interface material layer, and the heat dissipation component is connected to the The dam structure is sealed and fixedly connected, including heat dissipation covers or heat dissipation elements.
  • the present invention reduces the thermal resistance of the package by introducing liquid metal as a thermal interface material, thereby greatly improving the thermal diffusion efficiency during the packaging process; the dam structure prepared by using flexible materials can prevent the overflow of liquid metal during the packaging and application process, thereby The probability of the electrical performance of the device being degraded thereby is reduced, and since the thermal interface material layer is sealed and fixed with UV curing glue, the disassembly and replacement process is simple and effective. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

本发明的芯片封装结构及制备方法，包括基板、芯片、热界面材料层及散热部件，其中，芯片位于基板上与基板电连接；热界面材料层包括围坝结构和容置腔内的液态金属，围坝结构位于芯片上与其密封固定连接，散热部件形成在热界面材料层上，与围坝结构密封固定连接，从而通过围坝结构形成位于散热部件与芯片之间的含有液态金属的热界面材料层。本发明通过引入液态金属作为热界面材料，从而降低封装热阻，进而提高封装过程中的热扩散效率；使用柔性材料制备的围坝结构可以防止液态金属在封装及应用过程中的溢出，从而减少由此造成的器件电性能下降的概率，且由于采用紫外固化胶密封固定连接热界面材料层，从而拆卸和更换的工艺更简单。

Description

芯片封装结构及制备方法 技术领域
本发明涉及半导体封装技术领域，特别是涉及一种芯片封装结构及制备方法。
背景技术
集成电路(Integrated Circuit，IC，又称芯片)在现代电子系统、计算机系统、通信系统中被广泛的应用。按照应用领域不同，业界一般将IC分为数字芯片、模拟芯片、存储芯片、射频芯片、电源芯片、光芯片、无源芯片等。其中由数字芯片和存储芯片构成的逻辑系统、计算系统、通信系统一直引领着IC制造及其集成技术的发展。
随着先进封装工艺的不断发展，高端服务器功率也在持续升高，GPU甚至提升至1000W以上，面对当下这种情况芯片的散热显得尤为重要。目前常用的散热技术是将热界面材料(TIM)黏附于芯片表面，以将芯片所产生的热量散逸至外界，现行热界面材料主要是由高分子聚合物所形成，但这种热界面材料的导热性能比较差，从而导致封装结构的散热效果不佳。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种芯片封装结构及制备方法，用于解决现有技术中半导体封装结构存在散热效果较差导致封装结构性能下降的问题。
为实现上述目的，本发明提供一种芯片封装结构的制备方法，所述制备方法包括以下步骤：
提供基板；
于所述基板上键合芯片，且所述芯片与所述基板电连接；
于所述芯片上形成围坝结构，所述围坝结构与所述芯片之间密封固定连接，且所述围坝结构具有显露所述芯片的容置腔；
于所述容置腔内填充液态金属以结合所述围坝结构形成位于所述芯片上的热界面材料层；
于所述热界面材料层上形成散热部件，且所述散热部件与所述围坝结构密封固定连接。
可选地，还包括在所述基板上形成虚拟芯片的步骤，所述虚拟芯片对称分布于所述芯片两侧并与所述基板固定连接。
可选地，所述液态金属的材质包括镓、铟或锡中的一种。
可选地，所述围坝结构的材质为柔性材料，包括泡沫、PDMS或EPDM中的一种。
可选地，所述散热部件包括散热盖板或散热元件，所述散热元件包括散热基座以及位于所述散热基座上均匀排列的散热翅片。
可选地，所述围坝结构与所述芯片通过紫外固化胶密封固定连接；所述围坝结构与所述散热部件通过紫外固化胶密封固定连接。
可选地，所述基板包括晶圆级基板。
本发明还提供一种芯片封装结构，所述芯片封装结构包括：
基板；
芯片，所述芯片位于所述基板上且与所述基板电连接；
热界面材料层，包括围坝结构和液态金属，所述围坝结构位于所述芯片上并与所述芯片密封固定连接，且所述围坝结构具有显露所述芯片的容置腔，所述液态金属位于所述容置腔内；
散热部件，形成在所述热界面材料层上，且所述散热部件与所述围坝结构密封固定连接。
可选地，所述芯片封装结构还包括与所述基板固定连接且对称分布于所述芯片两侧的虚拟芯片。
可选地，所述散热部件包括散热盖板或散热元件，所述散热元件包括散热基座以及位于所述散热基座上均匀排列的散热翅片。
如上所述，本发明的芯片封装结构及制备方法，所述芯片封装结构包括基板、芯片、热界面材料层及散热部件，其中，所述芯片位于所述基板上且与所述基板电连接；所述热界面材料层包括围坝结构和填充于所述围坝结构的容置腔内的液态金属，所述围坝结构位于所述芯片上并与所述芯片密封固定连接，所述散热部件形成在所述热界面材料层上，且所述散热部件与所述围坝结构密封固定连接，从而通过所述围坝结构形成位于所述散热部件与所述芯片之间的含有液态金属的热界面材料层。本发明通过引入液态金属作为热界面材料，从而降低封装热阻，进而大幅提高封装过程中的热扩散效率；使用柔性材料制备的围坝结构可以防止液态金属在封装及应用过程中的溢出，从而减少由此造成的器件电性能下降的概率，且由于采用紫外固化胶密封固定连接所述热界面材料层，从而拆卸和更换的工艺简单有效。
附图说明
图1显示为本发明实施例中的一种芯片封装结构的制备方法的流程图。
图2显示为本发明实施例提供的基板的截面示意图。
图3显示为本发明实施例提供的键合芯片后的截面示意图。
图4显示为本发明实施例提供的形成虚拟芯片后的截面示意图。
图5显示为本发明实施例提供的形成紫外固化胶的截面示意图。
图6显示为本发明实施例提供的形成热界面材料层后的截面示意图。
图7显示为本发明实施例提供的一种芯片封装结构的结构示意图。
图8显示为本发明实施例提供的另一种芯片封装结构的结构示意图。
元件标号说明
101：基板，102：芯片，103：虚拟芯片，104：紫外固化胶，105：热界面材料层，1051：
围坝结构，1052：液态金属，106：散热盖板，108：散热元件，1081：散热基座，1082：散热翅片，S1～S5：步骤。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。
请参阅图1至图8。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
请参阅图1至图8，本发明提供了一种芯片封装结构的制备方法，包括以下步骤：
S1：提供基板101；
S2：于所述基板101上键合芯片102，且所述芯片102与所述基板101电连接；
S3：于所述芯片102上形成围坝结构1051，所述围坝结构1051与所述芯片102之间密封固定连接，且所述围坝结构1051具有显露所述芯片102的容置腔；
S4：于所述容置腔内填充液态金属1052以结合所述围坝结构1051形成位于所述芯片102上的热界面材料层105；
S5：于所述热界面材料层105上形成散热部件，且所述散热部件与所述围坝结构1051密封固定连接。
以下结合附图对有关所述芯片封装结构的制备方法做进一步的介绍，具体如下：
在步骤S1中，请参阅图1和图2，提供基板101。
可选地，所述基板101包括晶圆级基板。
可选地，所述基板101包括氧化硅基板、玻璃基板、陶瓷基板、有机基板中的一种，其形状可以为圆形、方形或其它任意所需形状，其表面积以能承载后续封装结构为准。
具体的，在本实施例中，所述基板101选用热膨胀系数较低的有机基板，所述有机基板的热膨胀系数较低，可以减少封装过程中产生的翘曲。
在步骤S2中，请参阅图1和图3，于所述基板101上键合芯片102，且所述芯片102与所述基板101电连接。
可选地，如图3所示，所述芯片102可以是现有的任意适用于封装的半导体芯片，可以是多个同类型或者多个不同类型的芯片，例如，可以是片上系统(SOC)器件，也可以是存储器芯片，如HBM等，在此不做限制。另外，基于封装效率、封装尺寸等的要求，一般会同时封装多个所述芯片102，在本实施例中所述芯片102的数量显示为1个，但所述芯片102的数量并非局限于此，根据需求所述芯片102的数量可大于等于1个，比如2个、3个、4个或更多。
具体的，如图4所示，还包括在所述基板101上形成虚拟芯片103的步骤，所述虚拟芯片103优选对称分布于所述芯片102两侧并与所述基板101密封固定连接，以通过所述虚拟芯片103降低所述封装结构的形变，其中，所述虚拟芯片103为无源芯片，所述虚拟芯片103与所述基板101密封固定连接，连接方式不限于胶连接，在本实施例中虚拟芯片103的数量显示为2个，但虚拟芯片103的数量并非局限于此，根据需求虚拟芯片103的数量可大于等于2个，比如3个、4个或更多。其中，形成所述虚拟芯片103的步骤可在形成所述芯片102的步骤之前、之后或与所述芯片102同时键合在所述基板101，此处不作限定。
在步骤S3中，请参阅图1、图5及图6，于所述芯片102上形成围坝结构1051，所述围坝结构1051与所述芯片102之间密封固定连接，且所述围坝结构1051具有显露所述芯片102的容置腔。
具体的，如图6所示，所述围坝结构1051与所述芯片102及所述虚拟芯片103之间通过紫外固化胶104密封固定连接，所述围坝结构1051与所述芯片102和所述虚拟芯片103之间形成容置腔，所述容置腔可分别显露所述芯片102和所述虚拟芯片103。
本实施例中，如图5及图6，所述围坝结构1051与芯片的固定连接方式为采用所述紫外固化胶密封固定连接，但粘合胶的种类并非局限于此，也可采用其他胶体。当采用所述紫外 固化胶104进行固定操作时，可包括将所述紫外固化胶104点至所述芯片102和所述虚拟芯片103的上方，所述围坝结构1051固定于所述芯片102和所述虚拟芯片103的上方，利用所需波长的紫外光照射所述紫外固化胶104，经紫外光照射后，所述紫外固化胶104可以快速固化成型，从而将所述围坝结构1051密封固定于对应芯片的上方。
进一步的，当需要维修或者去除所述围坝结构1051时，只需要使用丙酮或其它具有同种功能的溶剂去除所述紫外固化胶104，即可实现维修或者安全的移除所述围坝结构1051，在这个过程中，不会对其它部位造成二次损坏。可选地，所述围坝结构1051的材质为柔性材料，包括泡沫、PDMS(聚二甲基硅氧烷)或EPDM(三元乙丙橡胶)中的一种。
具体的，在本实施例中，所述围坝结构1051的材料优选为耐腐蚀性强、具有高介电强度且与所述芯片103兼容性优良的PDMS。
在步骤S4中，请参阅图1和图6，于所述容置腔内填充液态金属1052以结合所述围坝结构1051形成位于所述芯片102上的热界面材料层105。
具体的，如图6所示，于所述容置腔内填充液态金属1052，所述液态金属1052结合所述围坝结构1051共同构成所述热界面材料层105，所述热界面材料层105与所述芯片102和所述虚拟芯片103通过所述紫外固化胶104密封固定连接。
可选地，所述液态金属1052的材质包括镓、铟或锡中的一种。
具体的，镓、铟或锡作为常见的液态金属，其导热系数一般大于30W/(m·K)，此数值相对于常规的聚合物热界面材料较高，且具有较低的接触热阻和一定的流动性，所述液态金属1052可以降低封装热阻，进而大幅提高封装过程中的热扩散效率，提高封装质量。
在步骤S5中，请参阅图1、图7和图8，于所述热界面材料层105上形成散热部件，且所述散热部件与所述围坝结构1051密封固定连接。
可选地，如图7和图8所示，所述散热部件可包括散热盖板106或散热元件108，其中，所述散热元件108可包括散热基座1081以及于所述散热基座1081上均匀排列的散热翅片1082。
可选地，所述围坝结构1051与所述散热部件通过所述紫外固化胶104密封固定连接。
具体的，当所述散热部件采用所述散热盖板106时，可在所述围坝结构1051的上方、所述散热盖板106中与所述基板101待键合的侧壁底部或对应的所述基板101的表面分别涂覆所述紫外固化胶104，并在紫外光的作用下会进行固化，从而所述围坝结构1051的顶部结合所述散热盖板106可密封固定连接，以给所述液态金属1052提供密封保护，防止所述液态金属1052溢出。
其中，所述芯片102产生的热量可以直接通过所述液态金属1052传导至所述散热盖板106，并通过所述散热盖板106传递到外部，实现散热功能。同时，由于所述散热盖板106与所述基板101粘接成一体，极大地提高了所述基板101的结构强度，所述基板101在所述紫外固化胶104和所述散热盖板106的固定作用下能够保持表面平齐，避免所述基板101出现翘曲的情况。
可选地，如图8所示，当所述散热部件采用所述散热元件108时，所述散热元件108中的所述散热基座1081直接与所述围坝结构1051进行密封固定连接，从而所述液态金属1052可直接与芯片及所述散热元件108接触，以实现良好散热。其中，可包括步骤在所述围坝结构1051的上方点所述紫外光固化胶104，所述紫外光固化胶104在紫外光的作用下会进行固化，实现所述围坝结构1051与所述散热元件108的密封固定连接，从而实现对所述液态金属1052的密封，防止所述液态金属1052在封装及使用过程中的溢出。
实施例二
本实施例提供了一种芯片封装结构，所述封装结构包括：
基板101；
芯片102，所述芯片102位于所述基板101上且与所述基板101电连接；
热界面材料层105，包括围坝结构1051和液态金属1052，所述围坝结构1051位于所述芯片102上并与所述芯片102密封固定连接，且所述围坝结构1051具有显露所述芯片102的容置腔，所述液态金属1052位于所述容置腔内；
散热部件，形成在所述热界面材料层105上，且所述散热部件与所述围坝结构1051密封固定连接。
关于所述芯片封装结构的制备可参阅上述制备方法，但并非局限于此，本实施例中，所述芯片封装结构采用上述制备方法制备，从而关于所述芯片封装结构的制备、材质等的选择，可参阅实施例一，此处不作赘述。
可选地，如图4所示，所述芯片封装结构还包括与所述基板101固定连接且对称分布于所述芯片102两侧的虚拟芯片103。
可选地，如图7和图8所示，所述散热部件包括散热盖板106或散热元件108，所述散热元件108包括散热基座1081以及位于所述散热基座1081上均匀排列的散热翅片1082。
具体的，所述散热基座1081与所述热界面材料层105密封固定连接。
综上所述，本发明提供了一种芯片封装结构及制备方法，所述芯片封装结构包括：基板；芯片，所述芯片位于所述基板上且与所述基板电连接；热界面材料层，包括围坝结构和填充 于所述围坝结构内的液态金属，所述热界面材料层与所述芯片通过紫外固化胶密封固定连接；散热部件，形成在所述热界面材料层上，且所述散热部件与所述围坝结构密封固定连接，包括散热盖板或散热元件。本发明通过引入液态金属作为热界面材料，从而降低封装热阻，进而大幅提高封装过程中的热扩散效率；使用柔性材料制备的围坝结构可以防止液态金属在封装及应用过程中的溢出，从而减少由此造成的器件电性能下降的概率，且由于采用紫外固化胶密封固定连接所述热界面材料层，从而拆卸和更换的工艺简单有效。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种芯片封装结构的制备方法，其特征在于，包括以下步骤：
    提供基板；
    于所述基板上键合芯片，且所述芯片与所述基板电连接；
    于所述芯片上形成围坝结构，所述围坝结构与所述芯片之间密封固定连接，且所述围坝结构具有显露所述芯片的容置腔；
    于所述容置腔内填充液态金属以结合所述围坝结构形成位于所述芯片上的热界面材料层；
    于所述热界面材料层上形成散热部件，且所述散热部件与所述围坝结构密封固定连接。
  2. 根据权利要求1所述的制备方法，其特征在于：还包括在所述基板上形成虚拟芯片的步骤，所述虚拟芯片对称分布于所述芯片两侧并与所述基板固定连接。
  3. 根据权利要求1所述的制备方法，其特征在于：所述液态金属的材质包括镓、铟或锡中的一种。
  4. 根据权利要求1所述的制备方法，其特征在于：所述围坝结构的材质为柔性材料，包括泡沫、PDMS或EPDM中的一种。
  5. 根据权利要求1所述的制备方法，其特征在于：所述散热部件包括散热盖板或散热元件，所述散热元件包括散热基座以及位于所述散热基座上均匀排列的散热翅片。
  6. 根据权利要求1所述的制备方法，其特征在于：所述围坝结构与所述芯片通过紫外固化胶密封固定连接；所述围坝结构与所述散热部件通过紫外固化胶密封固定连接。
  7. 根据权利要求1所述的制备方法，其特征在于：所述基板包括晶圆级基板。
  8. 一种芯片封装结构，其特征在于：所述芯片封装结构包括：
    基板；
    芯片，所述芯片位于所述基板上且与所述基板电连接；
    热界面材料层，包括围坝结构和液态金属，所述围坝结构位于所述芯片上并与所述芯 片密封固定连接，且所述围坝结构具有显露所述芯片的容置腔，所述液态金属位于所述容置腔内；
    散热部件，形成在所述热界面材料层上，且所述散热部件与所述围坝结构密封固定连接。
  9. 根据权利要求8所述的芯片封装结构，其特征在于：所述芯片封装结构还包括与所述基板固定连接且对称分布于所述芯片两侧的虚拟芯片。
  10. 根据权利要求8所述的芯片封装结构，其特征在于：所述散热部件包括散热盖板或散热元件，所述散热元件包括散热基座以及位于所述散热基座上均匀排列的散热翅片。
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