WO2024046093A1 - 半导体结构、射频前端模组、电源转换模组、电子设备 - Google Patents

半导体结构、射频前端模组、电源转换模组、电子设备 Download PDF

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Publication number
WO2024046093A1
WO2024046093A1 PCT/CN2023/112597 CN2023112597W WO2024046093A1 WO 2024046093 A1 WO2024046093 A1 WO 2024046093A1 CN 2023112597 W CN2023112597 W CN 2023112597W WO 2024046093 A1 WO2024046093 A1 WO 2024046093A1
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Prior art keywords
semiconductor structure
silicon
silicon substrate
epitaxial layer
opening
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PCT/CN2023/112597
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English (en)
French (fr)
Inventor
何林峰
魏巍
张亚文
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华为技术有限公司
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Publication of WO2024046093A1 publication Critical patent/WO2024046093A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a radio frequency front-end module, a power conversion module, and an electronic device.
  • Si material has become the most widely used material in the semiconductor industry due to its excellent properties such as stable properties and low preparation cost.
  • more and more application scenarios such as radio frequency, power electronics and other fields
  • have put forward requirements for chips such as faster speed and higher withstand voltage.
  • Si material cannot meet the above requirements at the same time due to its material limitations.
  • Some wide-bandgap compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), and gallium nitride (GaN), have the properties of high carrier mobility, higher carrier density, and higher withstand voltage. Advantages, gradually being widely used in the semiconductor industry.
  • heterojunctions which are stacked with different materials usually exist in wide-bandgap semiconductor devices prepared using wide-bandgap compound semiconductors.
  • the thermal expansion coefficients and piezoelectric coefficients of different materials on the heterojunction interface are different, resulting in wide bandgap semiconductor devices.
  • Bandgap semiconductor devices are prone to heterojunction interface damage under high-voltage and high-current conditions caused by electrostatic discharge (ESD events). Therefore, the antistatic (ESD immunity) performance of current wide bandgap semiconductor devices is mostly weak.
  • Embodiments of the present application provide a semiconductor structure, a radio frequency front-end module, a power conversion module, and an electronic device, which are used to improve the antistatic performance of wide bandgap semiconductor devices in the semiconductor structure.
  • a first aspect of the embodiment of the present application provides a semiconductor structure.
  • the semiconductor structure may be a PA chip, an LNA chip, a power conversion chip with electrostatic discharge protection, etc.
  • the semiconductor structure includes a silicon substrate and an epitaxial layer disposed on the silicon substrate.
  • the epitaxial layer can be a single layer or a multi-layer structure.
  • the epitaxial layer has an opening that exposes the silicon substrate (penetrating the epitaxial layer). The opening is formed through an etching process.
  • the atoms on the contour surface surrounding the opening are amorphous or polycrystalline. state arrangement.
  • the electrode is arranged on the epitaxial layer and forms a wide bandgap device with the epitaxial layer.
  • the wide bandgap device can be a FET, and the electrodes can be the source, drain and gate.
  • the wide bandgap device can be a BJT, then the electrodes can be the base, collector, and emitter.
  • the silicon-based device serves as an electrostatic discharge protection device, located within the opening and extending into the silicon substrate.
  • the semiconductor structure provided by the embodiments of the present application integrates wide bandgap devices and silicon-based devices into the same silicon substrate, making full use of the strong electrostatic discharge protection capabilities of silicon-based devices to make up for the shortcomings of the wide bandgap device's insufficient antistatic ability. board to improve the antistatic ability of wide bandgap devices. Moreover, there is no need to package wide bandgap devices and silicon-based devices, and the area of the semiconductor structure is smaller.
  • the epitaxial layer is set on the surface of the silicon substrate. During the preparation process, the epitaxial process is first performed in the epitaxial process factory, and then the silicon-based devices and wide bandgap devices are formed in the device process factory.
  • the openings where the silicon-based devices are located are The formation is completed in the process flow after the epitaxial wafer preparation, realizing the process decoupling of the epitaxial process and the device process, increasing the flexibility of the entire process and reducing costs. Furthermore, except for the area where the opening in the epitaxial layer is used to prepare silicon-based devices, all other areas can be used to prepare wide bandgap devices. The flexibility in the use of epitaxial layers is improved, and the area of silicon-based devices is smaller, which can reduce parasitic effects (parasitic capacitance, leakage current) and reduce the impact of silicon-based devices on the performance of wide bandgap devices. Moreover, the wide bandgap device in this application can be applied to any wide bandgap semiconductor material, and is not limited to epitaxial growth only on SiC semiconductor materials. And silicon-based devices can be of various types and have a wide range of applications.
  • the opening has an upper port and a lower port, the lower port is closer to the silicon substrate relative to the upper port; the upper port has a first projection on the silicon substrate, and the lower port has a second projection on the silicon substrate. , the first projection covers the second projection.
  • the area of the upper port is greater than the area of the lower port.
  • the contour surface of the opening is a bevel, and the film layer stacked on the contour surface of the opening in the subsequent preparation process is also a bevel.
  • the metal line layer in the subsequently formed wiring stack can be deposited on the inclined surface instead of on the right-angled surface, which can reduce the risk of the metal line layer breaking at the position corresponding to the opening outline surface (cross-region interconnection line).
  • the distance between the first profile of the upper port and the second profile of the lower port is greater than 200 nm.
  • the slope formed by the contour surface can facilitate the deposition of the metal line layer, thereby greatly reducing the risk of the metal line layer breaking at the position corresponding to the opening contour surface.
  • the distance from the first projected outline to the second projected outline is less than 1 ⁇ m.
  • the angle between the contour surface and the bottom surface of the epitaxial layer ranges from 45° to 88°.
  • the inclination of the profile surface is not affected by the thickness of the epitaxial layer, so that the yield of the metal line layer of various types of semiconductor structures is guaranteed.
  • the surface of the silicon substrate facing the epitaxial layer is flat. That is to say, in this application, the epitaxial layer is directly epitaxially formed after the silicon substrate is wafered. There is no need to dope the silicon substrate to form SiC and then perform epitaxy. The process is simple and the cost is low.
  • the area of the silicon-based device is larger than the area of the wide bandgap device. In this way, the electrostatic discharge protection effect of silicon-based devices is good.
  • the semiconductor structure includes an electrostatic discharge protection device unit, and the electrostatic discharge protection device unit includes a silicon-based device. In this way, the semiconductor structure becomes a chip with electrostatic discharge protection effect.
  • the silicon-based device is a bipolar transistor, a diode, a silicon controlled rectifier or a metal-oxide semiconductor field effect transistor. This is one possible way to do it.
  • the wide bandgap device is a field effect transistor or a bipolar transistor. This is one possible way to do it.
  • the semiconductor structure further includes a wiring stack, the wiring stack covers the wide bandgap device unit and the silicon-based device unit; the wide bandgap device unit and the silicon-based device unit are coupled through the wiring stack.
  • the wiring stack formed by the back-end process is used to couple the wide bandgap device to the silicon-based device. It can provide full-process electrostatic discharge protection from the back-end process to the chip packaging, avoiding the need for off-chip protection solutions (silicon-based devices). devices and gallium nitride-based device packaging).
  • the semiconductor structure is a power amplifier chip, a low-noise amplifier chip or a power conversion chip. This is one possible way to do it.
  • a second aspect of the embodiment of the present application provides a method for preparing a semiconductor structure, which includes: forming an epitaxial film on a silicon substrate; using an etching process to form an opening on the epitaxial film to form an epitaxial layer; wherein the opening exposes the silicon substrate ; An electrode is formed on the epitaxial layer, and the electrode and the epitaxial layer form a wide bandgap device; a silicon-based device is formed in the area where the silicon substrate is exposed by the opening, and a silicon substrate is formed; the silicon-based device is located in the opening and extends into the silicon liner Bottom center.
  • the opening has an upper port and a lower port, the lower port is closer to the silicon substrate relative to the upper port; the upper port has a first projection on the silicon substrate, and the lower port has a second projection on the silicon substrate. , the first projection covers the second projection.
  • the distance between the first profile of the upper port and the second profile of the lower port is greater than 200 nm.
  • the slope formed by the contour surface can facilitate the deposition of the metal line layer, thereby greatly reducing the risk of the metal line layer breaking at the position corresponding to the opening contour surface.
  • the distance from the first projected outline to the second projected outline is less than 1 ⁇ m.
  • the angle between the contour surface surrounding the opening and the bottom surface of the epitaxial layer ranges from 45° to 88°.
  • the inclination of the profile surface is not affected by the thickness of the epitaxial layer, so that the yield of the metal line layer of various types of semiconductor structures is guaranteed.
  • atoms on the contour surface surrounding the opening are arranged in an amorphous or polycrystalline state.
  • the silicon-based device is a bipolar transistor, a diode, a silicon controlled rectifier or a metal-oxide semiconductor field effect transistor.
  • forming an electrode on the epitaxial layer includes: forming a source electrode and a drain electrode on the epitaxial layer; forming a silicon-based device, including forming a first electrode and a second electrode on a silicon substrate; forming After the source electrode and the drain electrode, and the first electrode and the second electrode, an ohmic contact annealing process is performed.
  • the preparation method further includes: forming a wiring stack; the wiring stack covers the wide bandgap device and the silicon-based device; and the wide bandgap device and the silicon-based device are coupled through the wiring stack.
  • a third aspect of the embodiment of the present application provides a radio frequency front-end module, including the semiconductor structure of any one of the first aspects and a radio frequency switch, and the radio frequency switch is coupled to the semiconductor structure.
  • the radio frequency front-end module provided by the embodiment of the present application includes the semiconductor structure of the first aspect, and its beneficial effects are the same as those of the semiconductor structure, which will not be described again here.
  • a fourth aspect of the embodiments of the present application provides a power conversion module, including the semiconductor structure of any one of the first aspects and a transformer, and the semiconductor structure is coupled to the transformer.
  • the power conversion module provided by the embodiment of the present application includes the semiconductor structure of the first aspect, and its beneficial effects are the same as those of the semiconductor structure, which will not be described again here.
  • a fifth aspect of the embodiments of the present application provides an electronic device, including the radio frequency front-end module of the third aspect and/or the power conversion module of the fourth aspect.
  • Figure 1A is a schematic framework diagram of an electronic device provided by an embodiment of the present application.
  • Figure 1B is a schematic diagram of a partial frame of an electronic device provided by an embodiment of the present application.
  • Figure 1C is a schematic framework diagram of a radio frequency system illustrating an embodiment of the present application
  • Figure 1D is a schematic framework diagram of a radio frequency system provided by an embodiment of the present application.
  • Figure 2A is a schematic framework diagram of a power conversion module illustrating an embodiment of the present application
  • Figure 2B is a schematic framework diagram of a power conversion chip provided by an embodiment of the present application.
  • Figure 3A is a schematic structural diagram of a P-i-N tube illustrating an embodiment of the present application
  • Figure 3B is a schematic framework diagram of another power conversion chip provided by an embodiment of the present application.
  • Figure 4A is a schematic diagram of the preparation process of a semiconductor structure illustrating an embodiment of the present application
  • Figure 4B is a schematic diagram of the region division of the semiconductor structure shown in Figure 4A;
  • Figure 5A is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application.
  • Figure 5B is a schematic diagram of an arrangement of atoms provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of a preparation process of a semiconductor structure provided by an embodiment of the present application.
  • FIGS. 7A-9F are schematic diagrams of the preparation process of a semiconductor structure provided by embodiments of the present application.
  • Figure 10 is a schematic diagram of region division of a semiconductor structure provided by an embodiment of the present application.
  • Figures 11A and 11B are schematic diagrams of a silicon-based device width measurement method provided by embodiments of the present application.
  • Figure 12 is a schematic diagram of the relative positional relationship between a silicon-based device and a wide bandgap device provided by an embodiment of the present application;
  • FIGS. 13A-13E are schematic diagrams of the preparation process of another semiconductor structure provided by embodiments of the present application.
  • FIGS 14A-14E are schematic diagrams of the preparation process of yet another semiconductor structure provided by embodiments of the present application.
  • orientation terms such as “upper”, “lower”, “left”, and “right” may include but are not limited to being defined relative to the orientation of the components in the drawings. It should be understood that, These directional terms may be relative concepts and are used for relative description and clarification, which may change accordingly according to changes in the orientation in which components are placed in the drawings.
  • connection should be understood in a broad sense, for example, “connection” "Connection” can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection or an indirect connection through an intermediary.
  • phase coupling can be a direct electrical connection or a direct electrical connection through an intermediary. Indirect electrical connection through an intermediary.
  • contact can mean direct contact or indirect contact through an intermediary.
  • the electronic equipment is, for example, consumer electronic products, household electronic products, vehicle-mounted electronic products, financial terminal products, and communication electronic products.
  • consumer electronic products include mobile phones, tablets, laptops, e-readers, personal computers (PC), personal digital assistants (PDA), desktop monitors, Smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, cars, etc.
  • Home electronic products include smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (such as soymilk machines, sweeping robots), etc.
  • Vehicle-mounted electronic products such as car navigation systems, vehicle-mounted high-density digital video discs (digital video discs, DVDs), etc.
  • Financial terminal products include automated teller machines (ATMs), self-service terminals, etc.
  • Communication electronic products include servers, memories, radars, base stations and other communication equipment.
  • FIG. 1A is a schematic structural diagram of an electronic device illustratively provided by an embodiment of the present application.
  • the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management unit 140, a power management unit 141, and a battery. 142.
  • Wired communication system 150 wireless communication system 160, audio unit 170, speaker 170A, receiver 170B, microphone 170C, headphone interface 170D, sensor unit 180, button 190, motor 191, indicator 192, camera 193, display screen 194, Subscriber identification unit (subscriber identification module, SIM) card interface 195 and antenna 1, antenna 2, etc.
  • SIM Subscriber identification module
  • the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100 .
  • the electronic device 100 may include more or fewer components than shown in the figures, or some components may be combined, some components may be separated, or some components may be arranged differently.
  • the components illustrated may be implemented in hardware, software, or a combination of software and hardware.
  • the processor 110 may include one or more processing units.
  • the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (GPU), and an image signal processor. (image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural network processor (neural-network processing unit, NPU), etc.
  • image signal processor image signal processor, ISP
  • controller video codec
  • digital signal processor digital signal processor
  • DSP digital signal processor
  • baseband processor baseband processor
  • neural network processor neural-network processing unit
  • NPU neural-network processing unit
  • different processing units can be independent devices or integrated in one or more processors.
  • the controller can generate operation control signals based on the instruction operation code and timing signals to complete the control of fetching and executing instructions.
  • the processor 110 may also be provided with a memory for storing instructions and data.
  • the memory in processor 110 is cache memory. This memory may hold instructions or data that have been recently used or recycled by processor 110 . If the processor 110 needs to use the instructions or data again, it can be called directly from the memory. Repeated access is avoided and the waiting time of the processor 110 is reduced, thus improving the efficiency of the system.
  • processor 110 may include one or more interfaces.
  • Interfaces may include integrated circuit (inter-integrated circuit, I2C) interface, integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, pulse code modulation (pulse code modulation, PCM) interface, universal asynchronous receiver and transmitter (universal asynchronous receiver/transmitter (UART) interface, mobile industry processor interface (MIPI), general-purpose input/output (GPIO) interface, subscriber identity module (SIM) interface, and /or universal serial bus (USB) interface, etc.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • UART universal asynchronous receiver and transmitter
  • MIPI mobile industry processor interface
  • GPIO general-purpose input/output
  • SIM subscriber identity module
  • USB universal serial bus
  • the USB interface 130 is an interface that complies with the USB standard specification, and may be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc.
  • the charging management unit 140 is used to receive charging input from the charger.
  • the charger can be a wireless charger or a wired charger.
  • the power management unit 141 is used to connect the battery 142, the charging management unit 140 and the processor 110.
  • the power management unit 141 receives input from the battery 142 and/or the charge management unit 140 to power the processor 110, the internal memory 121, the display screen 194, the camera 193, the wireless communication system 160, and the like.
  • the power management unit 141 can also be used to monitor battery capacity, battery cycle times, Battery health status (leakage, impedance) and other parameters.
  • the electronic device 100 implements display functions through a GPU, a display screen 194, an application processor, and the like.
  • the GPU is an image processing microprocessor and is connected to the display screen 194 and the application processor.
  • the display screen 194 is used to display images, videos, etc.
  • the electronic device 100 may include 1 or N display screens 194, where N is a positive integer greater than 1.
  • the electronic device 100 can implement the shooting function through an ISP, a camera 193, a video codec, a GPU, a display screen 194, an application processor, and the like.
  • the ISP is used to process the data fed back by the camera 193, which is used to capture still images or videos, and the video codec is used to compress or decompress the digital video.
  • the external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100.
  • an external memory card such as a Micro SD card
  • Internal memory 121 may be used to store computer executable program code, which includes instructions.
  • the electronic device 100 can implement audio functions through the audio unit 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone interface 170D, and the application processor.
  • the audio unit 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals.
  • Speaker 170A is used to convert audio electrical signals into sound signals.
  • the receiver 170B is used to convert audio electrical signals into sound signals.
  • Microphone 170C is used to convert sound signals into electrical signals.
  • the headphone interface 170D is used to connect wired headphones.
  • the sensor unit 180 may include an image sensor, a pressure sensor, a magnetic sensor, a distance sensor, etc.
  • the image sensor may be a contact image sensor (CIS), for example.
  • the buttons 190 include a power button, a volume button, etc.
  • the motor 191 can generate vibration prompts.
  • the indicator 192 may be an indicator light, which may be used to indicate charging status, power changes, or may be used to indicate messages, missed calls, notifications, etc.
  • the SIM card interface 195 is used to connect a SIM card.
  • the communication function of the electronic device 100 can be implemented through the antenna 1, the antenna 2, the wired communication system 150, the wireless communication system 160, the modem processor and the baseband processor.
  • a modem processor may include a modulator and a demodulator.
  • the modulator is used to modulate the low-frequency baseband signal to be sent into a medium-high frequency signal.
  • the demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal.
  • the demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing.
  • the baseband processor After the low-frequency baseband signal is processed by the baseband processor, it is passed to the application processor.
  • the application processor outputs sound signals through audio devices (not limited to speakers, receivers, etc.), or displays images or videos through the display screen 194.
  • Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals.
  • Each antenna in electronic device 100 may be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example: Antenna 1 can be reused as a diversity antenna for a wireless LAN. In other embodiments, antennas may be used in conjunction with tuning switches.
  • the wired communication system 150 can provide wireless communication solutions including 2G/3G/4G/5G applied to the electronic device 100 .
  • Wired communication system 150 may include radio frequency front-end modules.
  • the wired communication system 150 can receive electromagnetic waves through the antenna 1, filter and amplify the received electromagnetic waves through the radio frequency front-end module, and transmit them to the modem processor for demodulation.
  • the wired communication system 150 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves through the antenna 1 for radiation.
  • at least some of the functional units of the wired communication system 150 may be disposed in the processor 110 .
  • at least part of the functional units of the wired communication system 150 may be provided in the same device as at least part of the units of the processor 110 .
  • the wireless communication system 160 may provide applications on the electronic device 100 including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) network), Bluetooth (bluetooth, BT), and global navigation satellites. Wireless communication solutions such as global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technology. Wireless communication system 160 may be one or more devices integrating one or more communication processing units.
  • the wireless communication system 160 receives electromagnetic waves via the antenna 2 , frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110 .
  • the wireless communication system 160 can also receive the signal to be sent from the processor 110, frequency modulate it, amplify it, and convert it into electromagnetic waves through the antenna 2 for radiation.
  • the antenna 1 of the electronic device 100 is coupled to the wired communication system 150, and the antenna 2 is coupled to the wireless communication system 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology.
  • the wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (code division multiple access, CDMA), broadband code Wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (long term evolution, LTE), BT, GNSS, WLAN, NFC, FM, IR technology, etc.
  • the GNSS may include global positioning system (GPS), global navigation satellite system (GLONASS), Beidou navigation satellite system (BDS), quasi-zenith satellite system (quasi- zenith satellite system (QZSS) and/or satellite based augmentation systems (SBAS).
  • GPS global positioning system
  • GLONASS global navigation satellite system
  • BDS Beidou navigation satellite system
  • QZSS quasi-zenith satellite system
  • SBAS satellite based augmentation systems
  • the above-mentioned electronic device 100 also includes a circuit board, such as a printed circuit board (PCB).
  • a circuit board such as a printed circuit board (PCB).
  • Some electronic devices in the electronic device 100 such as the processor 100, internal memory 121, radio frequency front-end module, power management unit 141, etc., may be disposed on the circuit board.
  • an embodiment of the present application provides a radio frequency system, which can be applied to the wireless communication system 160 of the above-mentioned electronic device 100 .
  • the radio frequency system includes a radio frequency transceiver 200, a transceiver 300, a baseband 400 and a general processor 500.
  • the radio frequency transceiver 200 includes a radio frequency front-end module 210 and an antenna 2.
  • the radio frequency front-end module 210 is coupled with the antenna 2 through a matching network.
  • the antenna 2 receives the signal and transmits it to the radio frequency front-end module 210.
  • the radio frequency front-end module 210 performs mixing filtering and signal amplification on the received signal.
  • the radio frequency front-end module 210 mixes and power amplifies the signal, and then transmits it to the antenna 2 .
  • the antenna 2 may be packaged inside the radio frequency front-end module 210 , or may not be packaged inside the radio frequency front-end module 210 . In this embodiment, the antenna 2 is not packaged inside the radio frequency front-end module 210 as an example.
  • the radio frequency front-end module 210 , the transceiver 300 , the baseband 400 and the general processor 500 may be disposed on a circuit board of the electronic device 100 , for example.
  • the embodiment of the present application also provides a radio frequency front-end module 210, as shown in Figure 1C, including a radio frequency switch chip 211, a matching network 212, a low noise amplifier (low noise amplifier, LNA) chip 213, and a power amplifier (power amplifier, PA ) chip 214, etc.
  • a radio frequency front-end module 210 including a radio frequency switch chip 211, a matching network 212, a low noise amplifier (low noise amplifier, LNA) chip 213, and a power amplifier (power amplifier, PA ) chip 214, etc.
  • the signal received by the antenna 2 is transferred to the matching network 212 through the radio frequency switch chip 211, amplified by the LNA chip 213, and then output to the transceiver 300; after down-conversion and filtering by the transceiver 300, the demodulated signal is It is output to the baseband 400 for decoding (converting the analog signal into a digital signal); the valid data decoded by the baseband 400 is transmitted to the general processor 500 for use.
  • the general processor 500 transmits the data to the baseband 400 for encoding; the baseband 400 transmits the encoded signal to the transceiver 300; the transceiver 300 modulates the signal and transfers it to the PA chip 214 for amplification, and then passes through the radio frequency switch chip 211 transmitted to antenna 2 for transmission.
  • the LNA chip 213 includes a plurality of cascaded amplifiers
  • the PA chip 214 includes a plurality of cascaded amplifiers.
  • the LNA and the PA may, for example, be circuit structures composed of wide bandgap semiconductor devices, so that the LNA and the PA have faster speeds. and higher voltage resistance performance.
  • the antistatic performance (immunity to electrostatic discharge, also known as ESD immunity) of wide bandgap semiconductor devices is weak, causing LNA and PA to be easily damaged, which is a technical problem that needs to be solved.
  • the embodiment of the present application also provides an LNA chip 213 and a PA chip 214.
  • the LNA chip 213 and the PA chip 214 can be applied to the above-mentioned radio frequency front-end module 210.
  • the LNA chip 213 includes a first electrostatic discharge (ESD) protection unit coupled to the LNA
  • the PA chip 214 includes a second ESD protection unit coupled to the PA.
  • the circuit composed of wide bandgap semiconductor devices in the electronic device 100 also includes a power conversion module.
  • the power conversion module is used in the power management unit 141 of the electronic device 100.
  • the power conversion module also has the problem of weak antistatic performance.
  • the power conversion module 60 includes a power The conversion chip 61 and the transformer 62 are coupled, and the output end of the power conversion chip 61 is coupled to the transformer 62 .
  • the power conversion chip includes a control port 611 , a protected circuit 612 , a power line 613 , a ground line 614 and a power clamping unit 615 .
  • the protected circuit 612 includes a wide bandgap semiconductor device, the protected circuit 612 may include, for example, a high electron mobility transistor (HEMT). Therefore, as shown in FIG. 2A , the power conversion chip 61 further includes two electrostatic discharge protection units ESD, and the electrostatic discharge protection units ESD are, for example, diodes.
  • FIG. 2A illustrates a power rail-based electrostatic discharge protection network composed of diodes and power clamping units 615.
  • the forward pulse input to the control port 611 can be discharged to the power line 613 through the pull-up diode, and then discharged to the ground line 614 by the power clamping unit 615.
  • the voltage from the control port 611 to the ground line 614 is clamped to the sum of the voltage drop when the diode is turned on and the voltage drop of the power clamping unit 615 .
  • the negative pulse input to the control port 611 is clamped by the power clamping unit 615 and the pull-up diode.
  • This solution has two diodes, one positive and one negative, viewed from the control port 611.
  • the parasitic capacitance is large, so it is not suitable for scenarios that are sensitive to parasitic parameters.
  • embodiments of the present application also provide a power conversion chip 61 , and the power conversion chip 61 can be applied in the power conversion module 60 .
  • the power conversion chip 61 also includes a control port 611, a protected circuit 612, a power line 613, a ground line 614, and an electrostatic discharge protection unit ESD.
  • FIG. 2B schematically illustrates a local electrostatic discharge protection network.
  • the electrostatic discharge protection unit ESD is used both for electrostatic discharge protection of the protected circuit 612 and for bidirectional clamping of the protected circuit 612 .
  • the electrostatic discharge protection unit ESD is a diode.
  • the local electrostatic discharge protection network may refer to the protection of a single port.
  • Wide bandgap compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (GaO), etc. happen to have high carrier mobility, higher carrier density and higher
  • SiC silicon carbide
  • GaAs gallium arsenide
  • GaN gallium nitride
  • GaO gallium oxide
  • a low-cost preparation method is to epitaxially grow the above-mentioned wide-bandgap compound semiconductor layer on a Si (silicon) wafer, and then manufacture devices based on the wide-bandgap compound semiconductor.
  • a wide bandgap compound semiconductor layer is epitaxially grown on a Si substrate.
  • the wide bandgap compound semiconductor layer includes a buffer layer and a GaN stack.
  • An electrostatic discharge protection unit ESD is prepared in a wide bandgap compound semiconductor stack.
  • the electrostatic discharge protection unit ESD is a P-i-N diode.
  • the epitaxial layer can be stacked vertically A P-i-N diode is formed in it.
  • Si or C (carbon) is doped to form N-type GaN
  • Mg (magnesium) is doped to form P-type GaN.
  • i-type GaN does not need to be doped, and the i-type GaN layer can also be called an intrinsic GaN layer.
  • the surface of the GaN stack is covered with a dielectric layer 70.
  • the metal anode P is in contact with the P-type GaN layer through the first opening 71 on the dielectric layer 70.
  • the metal anode N is in contact with the N-type GaN layer through the second opening 72 on the dielectric layer 70.
  • the forward conduction voltage of the P-i-N diode can be adjusted by the thickness of the i-GaN layer, and the negative breakdown voltage is higher.
  • Si-based devices Compared with the electrostatic discharge protection unit ESD prepared by a wide bandgap compound semiconductor stack, Si-based devices have more types to choose from as electrostatic discharge protection devices and have stronger performance. Based on this, in other technologies, Si-based devices are used as the electrostatic discharge protection unit ESD to improve the electrostatic discharge protection effect of the electrostatic discharge protection unit ESD.
  • Si-based devices and GaN-based devices are respectively bound to a substrate, and a semiconductor structure combining Si-based devices and GaN-based devices is formed through packaging. This results in a complicated process and a larger size of the formed semiconductor structure.
  • Si containing C crystallizes at high temperature to form SiC.
  • the atoms on the side surfaces of the epitaxial layer formed through step S3 should be arranged in a crystalline state. That is to say, at the junction of the SiC region and the Si region, the atoms on the side of the epitaxial layer should be arranged in a crystalline state.
  • Si-based devices and GaN-based devices can be connected through the back end of line.
  • the GaN-based device area needs to be fixed, that is to say, the range of the epitaxial layer coverage area is fixed , except for the epitaxial layer coverage area, the remaining areas are Si-based device areas.
  • the filled part belongs to the epitaxial layer coverage area, and the non-filled part belongs to the Si-based device area.
  • the above preparation method can integrate GaN-based devices and Si-based devices in the same semiconductor structure, and the corresponding device areas must be defined before epitaxial growth, making the use of epitaxial wafers less flexible.
  • the process of forming SiC by injecting C into the Si substrate and then annealing is relatively difficult and the cost is high.
  • the above method is only applicable to semiconductor devices in which SiC is used as a transition buffer layer, and the scope of application is limited.
  • SiC needs to be formed in the device process factory first (steps S1 and S2), then epitaxy is performed in the epitaxial process factory (step S3), and finally returned to the device process factory to form Si-based devices and GaN-based devices (step S3). S4). Then, it is necessary to switch back and forth between the device process factory and the epitaxial process factory, and the device process factory and the epitaxial process factory need to cooperate, which leads to an increase in preparation costs.
  • embodiments of the present application also provide a semiconductor structure in which a wide bandgap compound-based device and a Si-based device are integrated.
  • the wide bandgap compound-based device includes a protected circuit
  • the Si-based device includes an electrostatic discharge protection unit ESD. .
  • the semiconductor structure provided by the embodiments of the present application may be a bare chip (die), a packaged chip or a wafer (wafer), etc.
  • the semiconductor structure mainly includes: silicon substrate 10 , epitaxial layer 20 , wide bandgap device 30 and silicon-based device 40 .
  • the epitaxial layer 20 is disposed on the surface of the silicon substrate 10 and covers the silicon substrate 10 .
  • the epitaxial layer 20 has an opening 201 penetrating the epitaxial layer 20 along the thickness direction of the epitaxial layer 20.
  • the atoms on the contour plane Z surrounding the opening 201 are arranged in an amorphous or polycrystalline state.
  • the crystal atoms are arranged in a fixed (or regular) lattice.
  • the crystal atoms are stacked in an irregular position (it can also be said that the position is irregular).
  • the atoms are in a state of long-range disorder and short-range order. That is, the atoms in each cubic lattice are arranged in an orderly manner, but the atoms in the cubic lattice are arranged in a disorderly manner.
  • the wide bandgap device 30 is disposed on the epitaxial layer 20 , and the silicon-based device 40 is located in the opening 201 and extends into the silicon substrate 10 .
  • the wide bandgap device 30 may be a field effect transistor (FET) or a bipolar junction transistor (BJT).
  • the silicon-based device 40 may be a bipolar transistor, a diode, a silicon controlled rectifier, or a metal-oxide semiconductor field effect transistor.
  • the semiconductor structure provided by the embodiment of the present application will be schematically described in conjunction with the method for preparing the semiconductor structure provided by the embodiment of the present application.
  • the wide bandgap device 30 in the semiconductor structure is a junction field effect transistor (JFET).
  • JFET junction field effect transistor
  • embodiments of the present application provide a method for preparing a semiconductor structure, including:
  • an epitaxial film 20' is formed on the silicon substrate 10'.
  • the silicon substrate 10' can be, for example, a silicon wafer, or a single-grain structure obtained by cutting a silicon wafer.
  • the silicon substrate 10' may include multiple chip areas, and the finally prepared semiconductor device may be a wafer.
  • the wafer can also be cut through cutting to obtain a bare chip (die) or a packaged chip.
  • the finally prepared semiconductor device may be a bare chip (die) or a packaged chip.
  • the preparation process illustrated below is only a schematic explanation of the structure of a chip area.
  • the crystal orientation and pre-doping concentration of the silicon substrate 10' depend on the type of epitaxial material and the application scenario.
  • the crystal orientation index of the silicon substrate 10' is [111]
  • the doping type may be intrinsic (no doping) or P-type doping (concentration is 1e15cm ⁇ -3, or 1*1015/cm3).
  • the crystallographic direction refers to the direction of any straight line passing through many particle points in the crystal
  • the crystallographic direction index is the simplest integer ratio of the atomic coordinates of a certain particle point in the crystallographic direction. It should be understood that different crystal orientations in crystals often have different properties such as different linear densities. In order to distinguish these crystal orientations of crystals, the crystal orientation index is introduced.
  • the crystal orientation index of [111] in this application is only for illustration and is not intended to be limiting.
  • the material everywhere in the silicon substrate 10' is silicon, and the surface of the silicon substrate 10' is flat.
  • the surface height difference within the process error range should fall within the protection range of the plane in the embodiment of the present application.
  • the epitaxial film 20' may include one or more epitaxial film layers. It can also be understood as an epitaxial wafer commonly known in this field.
  • the epitaxial film 20' includes multiple epitaxial film layers, and the epitaxial film 20' is a heterojunction stacked film.
  • Heterojunction is a junction formed by the contact of two different film layers of materials.
  • the lattice constants of the two materials are different, so a lattice mismatch will occur.
  • the epitaxial film 20 ′ includes a nucleation film, a buffer film, a channel film, an insertion film, a barrier film and a protective film that are sequentially stacked on the silicon substrate 10 ′.
  • the embodiments of the present application do not limit the materials of the nucleation film, buffer film, channel film, insertion film, barrier film and protective film.
  • the materials of the channel film and barrier film are different, and the materials of each film layer belong to the broad Bandgap semiconductor compounds are sufficient.
  • the material of each film layer is a III-V semiconductor (a semiconductor compound composed of group IIIA elements and group VA elements), a III-VI semiconductor (a semiconductor compound composed of group IIIA elements and group VIA elements) or a V-VI semiconductor ( Semiconductor compounds composed of group VA elements and group VIA elements).
  • III-V semiconductor a semiconductor compound composed of group IIIA elements and group VA elements
  • III-VI semiconductor a semiconductor compound composed of group IIIA elements and group VIA elements
  • V-VI semiconductor Semiconductor compounds composed of group VA elements and group VIA elements
  • the nucleation film is disposed on the silicon substrate 10', for example, the nucleation film is disposed on the surface of the silicon substrate 10'.
  • the nucleation film can be formed by, for example, a metal-organic chemical vapor deposition (MOCVD) growth method or a molecular beam epitaxy (MBE) growth method.
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the material of the nucleation film may include, for example, one or more of GaN, AlGaN, and aluminum nitride (AlN).
  • the function of the nucleation film is to match the lattice structure of the silicon substrate 10' with the lattice structure of the channel film. For example, a small difference in the lattice structure of the silicon substrate 10' can be placed on the silicon substrate 10' first. A nucleation film is formed, and then a channel film with a smaller lattice structure difference from the nucleation film is produced on the nucleation film.
  • the buffer film is disposed on a surface of the nucleation film far away from the silicon substrate 10'.
  • the buffer film is disposed on a surface of the nucleation film far away from the silicon substrate 10'.
  • the method of forming the buffer film can be, for example, using MOCVD or MBE process to epitaxially grow the buffer film.
  • the material of the buffer film may include GaN, for example.
  • the function of the buffer film is that the buffer film and the channel film have different bandgaps, which can make the potential well depth of the heterojunction formed by the barrier film and the channel film deeper, thus improving the two-dimensional electron gas. , 2DEG) concentration.
  • the channel film is disposed on the buffer film, for example, the channel film is disposed on the surface of the buffer film.
  • the channel film may be formed by, for example, MOCVD growth or MBE growth.
  • the material of the channel film may include, for example, one or more of GaN, AlGaN, indium aluminum nitride (InAlN), AlN, and scandium aluminum nitride (ScAlN).
  • the insertion film is disposed on the channel film, for example, the insertion film is disposed on the surface of the channel film.
  • a method of forming the insertion film for example, MOCVD growth method or MBE growth method can be used.
  • the material of the inserted film may be, for example, one or more of GaN, AlGaN, and AlN.
  • Placing an insertion film between the channel film and the barrier film can increase the concentration of 2DEG.
  • the barrier film is disposed on the interposer film, for example, the barrier film is disposed on the surface of the interposer film.
  • the barrier film can be formed by, for example, MOCVD growth method or MBE growth method.
  • the material of the barrier film may include, for example, one or more of GaN, AlGaN, InAlN, AIN, and ScAlN.
  • the channel film and the barrier film constitute a heterojunction of the semiconductor device, and a two-dimensional electron gas is generated above the channel film. Therefore, the channel film and barrier film are made of different materials.
  • the material of the channel film includes GaN
  • the material of the barrier film includes AlGaN.
  • the capping film is disposed on the barrier film, for example, the capping film is disposed on the surface of the barrier film.
  • the capping film can be formed by, for example, MOCVD growth or MBE growth.
  • the material of the capping film may be GaN or silicon nitride (Si3N4), for example.
  • the barrier film By forming a cap film on the barrier film, the barrier film can be protected, the surface of the barrier film can be prevented from being oxidized, and the surface state of the semiconductor device can be reduced. Reducing the on-resistance of the semiconductor device can reduce the gate leakage and power consumption of the semiconductor device, thereby improving the reliability of the semiconductor device.
  • the structure of the epitaxial film 20' shown in FIG. 7A is only an illustration and is not limited in any way.
  • the epitaxial film 20' includes at least a channel film and a barrier film.
  • an etching process is used to form an opening 201 on the epitaxial film 20' to form the epitaxial layer 20.
  • the opening 201 penetrates the epitaxial film 20' along the thickness direction of the epitaxial film 20', and the opening 201 exposes the silicon substrate 10'. Therefore, the nucleation film, the buffer film, the channel film, the insertion film, the barrier film and the protective film each have openings, and the openings on each film layer are connected to form the opening 201 on the epitaxial film 20'.
  • the epitaxial layer 20 includes a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, and a protective layer. It should be understood that the structure of the epitaxial layer 20 shown in FIG. 7B is only an illustration without any limitation.
  • the epitaxial layer 20 at least includes a channel layer and a barrier layer.
  • the epitaxial film 20' is formed on the surface of the silicon substrate 10', so that the epitaxial film 20' covers the entire surface of the silicon substrate 10'.
  • the opening 201 is formed on the epitaxial film 20', except for the portion exposed by the opening 201, the rest of the silicon substrate 10' is covered by the epitaxial layer 20.
  • step S20 includes:
  • the photoresist layer has a photoresist pattern, or photoresist opening, and the photoresist opening corresponds to the opening 201 to be formed.
  • the photoresists mentioned in the embodiments of this application are all positive photoresists, that is, the photoresist can be activated after illumination, and then the activated photoresist can be removed.
  • negative photoresist can also be used in actual operations. It should be noted that negative photoresist will not be activated after illumination, but will be activated without illumination. Whether positive photoresist or negative photoresist is used, they all fall within the protection scope of the embodiments of the present application.
  • dry etching may be used to remove the epitaxial film 20' under the photoresist opening.
  • the opening is formed using etching processes such as reactive ion etching (RIE), inductively coupled plasma (ICP), and ion beam etching (IBE). 201.
  • RIE reactive ion etching
  • ICP inductively coupled plasma
  • IBE ion beam etching
  • the atoms in the epitaxial film 20' are arranged in a crystalline state, and the side surfaces of the epitaxial film 20' will have a relatively complete crystal lattice structure.
  • the epitaxial film 20' after etching the epitaxial film 20', there will be etching marks on the etched surface (the contour surface surrounding the opening 201), leaving physical damage.
  • the lattice structure on the etched surface is destroyed, and the atomic arrangement is amorphous or polycrystalline.
  • FIB focused ion beam
  • TEM transmission electron microscope
  • the opening 201 has an upper port a and a lower port b
  • the lower port b is closer to the silicon substrate 10 ′ relative to the upper port a
  • the upper port a has a first projection on the silicon substrate 10 ′
  • the lower port b has a second projection on the silicon substrate 10'
  • the first projection covers the second projection.
  • the contour surface Z of the opening 201 forms a certain angle with the silicon substrate 10', and the opening 201 presents a shape with a larger upper side and a smaller lower side.
  • the projection of the contour of the lower port b on the silicon substrate 10' is located within the projection of the contour of the upper port a on the silicon substrate 10'.
  • the area of the upper port a is larger than the area of the lower port b of the opening 201, and the areas of the upper port a and the lower port b can be understood as the area where the upper port a and the lower port b are parallel to the cross-section of the silicon substrate 10'. area.
  • the area of the upper port a is the area of the hole in the upper surface of the epitaxial layer 20 away from the silicon substrate 10 ′, and the area of the lower port b is the area of the hole in the lower surface of the epitaxial layer 20 that is in contact with the silicon substrate 10 ′.
  • the angle ⁇ between the profile surface Z and the bottom surface of the epitaxial layer 20 ranges from 45° to 88°, and the bottom surface of the epitaxial layer 20 is the surface in contact between the epitaxial layer 20 and the silicon substrate 10'.
  • the value of the angle ⁇ between the profile surface Z and the bottom surface of the epitaxial layer 20 is 50°, 55°, 60°, 65°, 70°, 75°, 80° or 85°.
  • the spacing S between the first profile of the upper port a and the second profile of the lower port b is greater than 200 nm.
  • the distance between the first projected profile of the upper port a on the silicon substrate 10' and the second projected profile of the lower port b on the silicon substrate 10' is greater than 200 nm.
  • the first detection point is determined on the first contour and the second detection point is determined on the second contour.
  • the outer tangent line of the first contour at the first detection point should be consistent with the first detection point.
  • the outer tangents of the two contours at the second detection point are parallel, and measure whether the distance between the first detection point and the second detection point is greater than 200nm.
  • the spacing S between the first profile of the upper port a and the second profile of the lower port b is less than 1 ⁇ m.
  • the spacing S between the first profile and the second profile is 250nm-300nm, 300nm-350nm, 350nm-100nm, 400nm-450nm, 450nm-5000nm, 500nm-550nm, 550nm-600nm, 600nm-650nm, 650nm- 700nm, 700nm-750nm, 750nm-800nm, 800nm-850nm, 850nm-900nm, 900nm-950nm or 950nm-1 ⁇ m.
  • the embodiment of the present application does not limit the shape of the opening 201, and the outline of the opening 201 can be any closed shape.
  • the outline of the upper port a can be any closed figure
  • the outline of the lower port b can be any closed figure.
  • the outline of the upper port a and the outline of the lower port b are concentric similar figures.
  • the area where the opening 201 is located corresponds to the Si-based device area, and other areas are wide bandgap device areas.
  • the contour surface Z surrounding the opening 201 is a slope
  • the film layer stacked on the contour surface Z in the subsequent preparation process is also a slope.
  • the metal line layer in the subsequently formed wiring stack can be deposited on the inclined surface instead of on the right-angled surface, which can reduce the risk of the metal line layer breaking at the position corresponding to the contour surface Z (cross-region interconnection line).
  • the epitaxial film 20 ′ may be over-etched. That is to say, a part of the surface of the silicon substrate 10' will be etched away to ensure that the opening 201 penetrates the epitaxial film 20'.
  • an electrode is formed on the epitaxial layer 20 to form a wide bandgap device 30.
  • the wide bandgap device 30 is a FET, and the electrodes formed on the epitaxial layer are the source S, the drain D and the gate G.
  • the source S and the drain D form ohmic contact with the epitaxial layer 20
  • the gate G forms a Schottky contact with the epitaxial layer 20
  • the source S and the drain D form ohmic contact with the barrier layer in the epitaxial layer 20
  • the gate G forms Schottky contact with the barrier layer in the epitaxial layer 20
  • the source S, the drain D and the gate G, together with the epitaxial layer 20 form the wide bandgap device 30 .
  • the semiconductor structure may include one or more wide bandgap devices 30.
  • the wide bandgap device 30 can be understood as a semiconductor device with a bandgap width greater than 1.5eV. For example, it can be measured by energy dispersive spectroscopy. EDS) to determine the bandgap width of semiconductor devices.
  • the wide bandgap device 30 can also be understood as a semiconductor device formed of third-generation semiconductor materials. Third-generation semiconductor materials may include, for example, GaN, GaO, SiC, and zinc oxide (ZnO).
  • the wide bandgap device 30 includes a heterojunction semiconductor device.
  • the wide bandgap device 30 is a high electron mobility transistor (HEMT).
  • HEMT high electron mobility transistor
  • the wide bandgap device 30 is a semiconductor device including III-V semiconductor material, III-VI semiconductor material, or V-VI semiconductor material.
  • the wide bandgap device 30 is a GaAs-based semiconductor device or a GaN-based semiconductor device.
  • the semiconductor device provided by the embodiment of the present application is a power conversion chip.
  • the semiconductor structure includes a power conversion device unit including a wide bandgap device 30 .
  • the power conversion device unit may also include passive devices such as resistors, capacitors, and inductors, or active devices such as diodes. These passive devices and active devices are coupled to the wide bandgap device 30 through the subsequently formed metal stack to form a circuit structure for power conversion.
  • the power conversion device unit can be understood as a device unit composed of devices included in the power conversion circuit, and these devices have not been coupled through subsequent processes. Or it can be understood that the power conversion device unit is a device included in the circuit for realizing the power conversion function, and does not include wiring for coupling the device into a path.
  • the semiconductor device provided by the embodiment of the present application is a PA chip.
  • the semiconductor structure includes a power amplifier device unit including a wide bandgap device 30 .
  • power The amplifier device unit may also include passive devices such as resistors, capacitors, and inductors, or active devices such as diodes. These passive devices and active devices are coupled to the wide bandgap device 30 through the subsequently formed metal stack to form the circuit structure of the power amplifier.
  • the power amplifier device unit can be understood as a device unit composed of devices included in the power amplifier, and these devices have not been coupled through subsequent processes. Or it can be understood that the power amplifier device unit is a device included in a circuit for realizing the power amplification function, and does not include wiring for coupling the devices into a path.
  • the semiconductor device provided by the embodiment of the present application is an LNA chip.
  • the semiconductor structure includes a low noise amplifier device unit including a wide bandgap device 30 .
  • the low-noise amplifier device unit may also include passive devices such as resistors, capacitors, and inductors, or active devices such as diodes. These passive devices and active devices are coupled with the wide bandgap device 30 through the subsequently formed metal stack to form the circuit structure of the low-noise amplifier.
  • the low-noise amplifier device unit can be understood as a device unit composed of devices included in the low-noise amplifier, and these devices have not been coupled through subsequent processes. Or it can be understood that the low-noise amplifier device unit is a device included in a circuit for realizing a low-noise amplification function, and does not include wiring for coupling the devices into a path.
  • the wide bandgap device 30 as a HEMT device as an example, the preparation process of the source S, the drain D, and the gate G is schematically explained.
  • step S30 includes:
  • the photoresist layer has a source opening in the region where the source S is to be formed, and a drain window in the region where the drain D is to be formed.
  • the photoresist of the photoresist layer may be a positive photoresist or a negative photoresist.
  • dry etching may be used to form source openings and drain openings on the protective layer, and the source openings and drain openings expose the barrier layer.
  • an ion implantation process can be used to inject donor impurities through source openings and drain openings.
  • the donor impurity may be, for example, silicon ions, and the donor impurity may be a single element or a mixture of multiple elements.
  • the injection of donor impurities can reduce the resistivity of the ohmic contact resistance between the source electrode S and the drain electrode D to be formed and the barrier layer, and can also reduce the resistivity of the barrier layer.
  • step S36 can be performed directly without removing the photoresist layer.
  • the photoresist layer has a source opening in the area where the source S is to be formed, and a drain window in the area where the drain D is to be formed.
  • a metal deposition process for example, a metal deposition process, a sputtering process, an evaporation process or an electroplating process can be used to produce the metal film.
  • the source S and the drain D form ohmic contact with the barrier layer.
  • the material of the source electrode S and the drain electrode D may be a single substance, an alloy, or a multi-layer laminated metal.
  • the materials of the source S and the drain D can be, for example, a titanium (Ti) layer, an Al layer, a nickel (Ni) layer, and a gold (Au) layer stacked in sequence, that is, Ti/Al/Ni/ Au.
  • the materials of the source electrode S and the drain electrode D may be a Ti layer, an Al layer, a platinum (Pt) layer, and an Au layer stacked in sequence, that is, Ti/Al/Pt/Au.
  • the materials of the source electrode S and the drain electrode D may be a Ti layer, a tantalum (Ta) layer and a Ti layer stacked in sequence, that is, Ti/Ta/Ti.
  • the source S and drain D may be made of Au or palladium (Pd).
  • a gate dielectric film may be deposited first and then etched to form a gate dielectric layer.
  • a metal film is first deposited, and then the metal film is etched to form a gate S, which is located above the gate dielectric layer.
  • the material of the gate S may be, for example, Au or Pd.
  • a silicon-based device 40 is formed in the area of the silicon substrate 10' exposed by the opening 201, and the silicon substrate 10 is formed.
  • the silicon-based device 40 includes one or more silicon-based devices.
  • the silicon-based device can be understood as a device prepared by doping in the silicon substrate 10'.
  • the silicon-based device 40 is a bipolar transistor or a device included in a circuit having certain functions.
  • the semiconductor structure includes an electrostatic discharge protection unit, and the silicon-based device 40 is a device in the electrostatic discharge protection device unit.
  • the electrostatic discharge protection unit may include a single silicon-based device 40 , or the electrostatic discharge protection unit may be a circuit composed of multiple silicon-based devices 40 .
  • the electrostatic discharge protection device unit includes at least one of a diode, a bipolar transistor, a silicon controlled rectifier, or a metal-oxide semiconductor field effect transistor.
  • silicon-based device 40 is a diode.
  • the diode is a PN junction diode.
  • the diode includes a deep N well (Deep N Well, DNW) 41, a P well (P Well, PW) 42, a P-type active region 43, an N-type active region 44, an isolation portion 45, a first electrode 46 and a second electrode 47.
  • the diode may also be a Schottky diode or a P-i-N diode, which is not limited in the embodiments of the present application.
  • Step S40 includes:
  • S41 First, implant phosphorus ions into the silicon substrate 10' below the opening 201 through ion implantation, and anneal to form a deep N well 41.
  • the photoresist layer has a P-type active region window. Boron ions are injected into the P-type active region window to form a P-type active region 43 (P-type heavily doped) located in the silicon substrate 10'. miscellaneous area).
  • the photoresist layer has an N-type active area window. Arsenic ions are injected into the N-type active area window to form an N-type active area 44 (N-type heavily doped) located in the silicon substrate 10'. miscellaneous area).
  • the P-type active region 43 corresponds to the anode of the diode to be formed
  • the N-type active region 44 corresponds to the cathode of the diode to be formed.
  • the isolation portion 45 is formed through local oxidation. There is also an isolation portion 45 between the P-type active region 43 and the N-type active region 44. Isolation part 45.
  • the silicon substrate 10 is also prepared.
  • the main difference between the silicon substrate 10 and the silicon substrate 10' is that the partial structure of the silicon substrate 10' corresponding to the opening 201 is doped and oxidized and serves as the structure of the silicon-based semiconductor device unit, and the silicon substrate 10' is doped and oxidized. part, and the remaining part is used as the silicon substrate 10.
  • the first electrode forms an ohmic contact with the P-type active region 43
  • the second electrode forms an ohmic contact with the N-type active region 44 .
  • the first electrode can be understood as, for example, the anode of the diode
  • the second electrode can be understood as, for example, the cathode of the diode.
  • the material of the first electrode and the second electrode may be, for example, metal silicide.
  • the materials of the first electrode and the second electrode include metals such as Ti, Pt, and Ni.
  • the metal annealing process for achieving ohmic contact is only performed once, and the annealing process is not performed twice.
  • the source electrode S and the drain electrode D are being formed on the epitaxial layer 20 .
  • the source electrode S and the drain electrode D can be formed in a reasonable sequence of steps. D.
  • the semi-finished devices of the first electrode and the second electrode are annealed.
  • step S34 is not executed before step S35 is executed. Before step S47 is executed, step S46 is not executed. Step S34 and step S46 may be the same step. If step S40 is performed after step S30, then the one-side annealing process (step S34 and step S46) can be performed after step S39 and step S47 are performed. Alternatively, step S40 is performed before step S30. Then, the one-side annealing process (step S34 and step S46) can be performed after steps S47 and S37 are performed. Of course, the annealing process (step S34 and step S46) can also be performed after other steps, as long as only one annealing process is performed during the preparation of the two structures of the wide bandgap device 30 and the silicon-based device 40 .
  • the process steps can be simplified and the thermal budget of the semiconductor structure can be reduced.
  • the preparation sequence of each step can also be reasonably adjusted according to the thermal budget of the semiconductor structure.
  • the silicon-based device 40 is a bipolar transistor.
  • the bipolar transistor includes a deep N well 61, a P well 62, a P-type heavily doped region 63, an N-type heavily doped region 64, an N well 65, an isolation portion 66, a collector 67, a base 68 and an emitter. Extreme 69.
  • P well 62 and N well 65 are located in deep N well 61 , and N wells 65 are provided on opposite sides of P well 62 .
  • a P-type heavily doped region 63 and an N-type heavily doped region 64 are formed on the surface of the P well 62 close to the silicon substrate 10 .
  • P-type heavily doped regions 63 are provided on opposite sides of the N-type heavily doped region 64 .
  • An N-type heavily doped region 64 is formed near the surface of the N well 65 of the silicon substrate 10 .
  • Isolation portions 66 are provided on both sides of the P-type heavily doped region 63 and the N-type heavily doped region 64 .
  • a collector electrode 67 is provided on the surface of the N-type heavily doped region 64 located in the N well 65 , and the collector electrode 67 forms an ohmic contact with the N-type heavily doped region 64 .
  • a base electrode 68 is provided on the surface of the P-type heavily doped region 63 , and the base electrode 68 forms an ohmic contact with the P-type heavily doped region 63 .
  • An emitter 69 is disposed on the surface of the N-type heavily doped region 64 of the P well 62 , and the emitter forms an ohmic contact with the N-type heavily doped region 64 .
  • the collector 67 can be used as the first electrode (positive electrode) of the silicon-based device 40 , for example.
  • the base 68 and the emitter 69 can be used as the second electrode (negative electrode) of the silicon-based device 40 .
  • the base 68 and the emitter 69 are connected to the ground. coupling.
  • Silicon-based device 40 is an NPN bipolar transistor with base 68 connected to ground.
  • the method of forming the well, the heavily doped region, and the isolation part can be the same as the method of forming the diode described above, and will not be described again here.
  • the silicon-based device 40 is a PNP bipolar transistor.
  • the silicon-based device 40 is a silicon controlled rectifier (SCR).
  • SCR silicon controlled rectifier
  • the silicon controlled rectifier includes a deep N well 71, a P well 72, a P-type heavily doped region 73, an N-type heavily doped region 74, an N well 75, an isolation part 76, an anode 77, a cathode 78 and a power electrode 79 .
  • P well 72 and N well 75 are located in deep N well 71 , and N wells 75 are provided on opposite sides of P well 72 .
  • a P-type heavily doped region 73 and an N-type heavily doped region 74 are formed near the surface of the P well 72 of the silicon substrate 10 .
  • a P-type heavily doped region 73 and an N-type heavily doped region 74 are formed near the surface of the first N well 75 of the silicon substrate 10 .
  • An N-type heavily doped region 74 is formed near the surface of the second N well 75 of the silicon substrate 10 .
  • the heavily doped regions are arranged in the order of P-type heavily doped region 73, N-type heavily doped region 74, P-type heavily doped region 73, N-type heavily doped region 74, and N-type heavily doped region 74.
  • Isolation portions 76 are provided on both sides of the P-type heavily doped region 73 and the N-type heavily doped region 74 .
  • the P-type heavily doped region 73 and the N-type heavily doped region 74 located in the P well 72 are respectively provided with first electrodes 77 (positive electrodes) on their surfaces.
  • the P-type heavily doped region 73 and the N-type heavily doped region 73 located in the first N well 75 Second electrodes 78 (negative electrodes) are respectively provided on the surface of the heavily doped region 74 , and a power electrode 79 is provided on the surface of the N-type heavily doped region 74 located in the second N well 75 .
  • SCR has both high trigger voltage and high current conduction capability. After the SCR is triggered, both electrons and holes in the N-well and P-well participate in conduction, and their net charges cancel each other out. There will be a hysteresis phenomenon in which the current increases but the voltage decreases. This principle is called conductance modulation. Therefore, after the SCR is turned on, the clamping voltage is lower, the current conduction ability is stronger, and the target protection specification can be achieved with a smaller area.
  • the structure of the SCR can be seen as two small-area forward PN junctions and a large-area reverse PN junction connected in series. The junction capacitance of the forward PN junction and the junction capacitance of the reverse PN junction show an opposite trend with the voltage change.
  • the silicon-based device 40 is a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • the MOSFET includes a source region and a drain region located in the silicon substrate 10.
  • a source S' of the MOSFET is disposed on the source region, and the source S' is in ohmic contact with the source region.
  • the drain D' of the MOSFET is arranged on the drain region, and the drain D' is in ohmic contact with the drain region.
  • the gate G' of the MOSFET is disposed between the source S' and the drain D', and a gate insulating layer is disposed between the gate G' and the silicon substrate 10.
  • the silicon-based device 40 shown in FIGS. 8A to 8D is only an illustration. According to specific electrostatic discharge protection requirements, different silicon-based devices 40 can be prepared in the corresponding area of the opening 201 .
  • step S10 is executed, step S30 may be executed first, and then step S20 and step S40 may be executed in sequence.
  • step S40 is executed first, and then step S30 is executed.
  • the above preparation process is only an illustration without any limitation.
  • the surface of the silicon substrate 10 facing the epitaxial layer 20 is flat.
  • the surface of the silicon substrate 10 facing the epitaxial layer 20 can be understood as the plane where the portion of the silicon substrate 10 in contact with the epitaxial layer 20 is located.
  • the silicon substrate 10' when the silicon substrate 10' is cut, the surface of the silicon substrate 10' is flat. After the part of the silicon substrate 10' located below the opening 201 is doped, this part becomes the structure of the silicon-based device 40, which is equivalent to The silicon-based device 40 is disposed in the silicon substrate 10 .
  • the silicon-based device 40 is located in the opening 201 , and part of the structure of the silicon-based device 40 is located in the silicon substrate 10 . Part of the structure of the silicon-based device 40 is located in the silicon substrate 10 . It can be understood that part of the structure of the silicon-based device 40 is located below the level of the surface where the silicon substrate 10 contacts the epitaxial layer 20 .
  • the wiring stack 50 covers the wide bandgap device 30 and the silicon-based device 40 , and the wide bandgap device die 30 and the silicon-based device 40 are coupled through the wiring stack 50 .
  • the wide bandgap device 30 as a MOSFET and the silicon-based device 40 as a diode as an example, the coupling of the wide bandgap device 30 and the silicon-based device 40 will be schematically explained.
  • step S50 includes:
  • a first interlayer dielectric film 51' is formed on the epitaxial layer 20.
  • first interlayer dielectric film 51' may include, for example, low dielectric constant inorganic compounds or organic compounds such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc.
  • a plurality of first through holes 511 are formed on the first interlayer dielectric film 51' through an etching process to form the first interlayer dielectric layer 51.
  • the first through hole 511 is formed using etching processes such as RIE process, ICP etching process, and IBE process.
  • the plurality of first through holes 511 expose electrodes in the wide bandgap device 30 and the silicon-based device 40 .
  • the plurality of first through holes 511 respectively expose the source S, drain D, and gate G of the MOSFET and the anode 46 and cathode 47 of the diode.
  • the first metal layer 52 includes a plurality of first metal patterns 521.
  • the plurality of first metal patterns 521 fill the first through holes 511 and are respectively coupled to the source S and the gate G of the MOSFET and the cathode 47 of the diode.
  • the first metal layer 52 also includes a first metal line 522, the first metal line 522 fills the first through hole 511, and the drain D and the anode 46 are coupled to the first metal line 522.
  • a metal wire 522 is a metal wire 522.
  • the structure coupled to one of the source electrode S, the drain electrode D, the gate electrode G, the anode 46, and the cathode 47 is the first metal pattern 521.
  • Two coupled structures among the gate G, the positive electrode 46 and the negative electrode 47 are the first metal lines 522 .
  • the material of the first metal layer 52 may include, for example, copper, aluminum, gold, etc.
  • a second interlayer dielectric layer 53 is formed.
  • the second interlayer dielectric layer 53 has a plurality of second through holes 531 , and the second through holes 531 expose the first metal patterns 521 corresponding to the source electrode S, the gate electrode G, and the electrodes to be coupled in the negative electrode 47 .
  • the plurality of second through holes 531 expose the first metal pattern 521 coupled to the gate electrode G and the first metal pattern 521 coupled to the negative electrode 47 .
  • the method of forming the second interlayer dielectric layer 53 may be, for example, the same as the method of forming the first interlayer dielectric layer 51 .
  • a second metal layer 54 is formed, and the second metal layer 54 fills the second through hole 531.
  • the second metal layer 54 is coupled to the first metal pattern 521 above the gate G.
  • the second metal layer 54 is also coupled to the first metal pattern 521 above the negative electrode 47 , so that the gate G is connected through the second metal layer 54 . and the negative electrode 47 is coupled.
  • the method of forming the second metal layer 54 may be, for example, the same as the method of forming the first metal layer 52 .
  • Step S50 may also include repeating the steps of forming the interlayer dielectric layer and the metal layer until all required metal layers in the subsequent process are prepared. That is to say, the above-mentioned step S50 can be understood as a back-end process commonly referred to in this field.
  • the silicon-based device 40 is used to implement clamping protection between the gate G and the drain D of the wide bandgap device 30 , thereby achieving the purpose of electrostatic discharge protection.
  • the semiconductor structure formed through the above preparation process viewed from a top view, as shown in FIG. 10 , in the area of the silicon substrate 10 within the scope, except for the area where silicon-based devices are installed, which is the silicon-based device area, the remaining areas are all epitaxial layer coverage areas.
  • the wiring stack 50 of the semiconductor device also includes structures such as power lines and ground lines.
  • the area of the silicon-based device 40 is larger than the area of the wide bandgap device 30 .
  • the areas of the silicon-based device 40 and the wide bandgap device 30 can be understood as the area of the outer contour of the electrode in the silicon-based device 40 and the area of the outer contour of the electrode in the wide bandgap device 30 .
  • the width of the silicon-based device 40 ranges from tens of ⁇ m to tens of thousands of ⁇ m.
  • the width of the silicon-based device 40 is 1000 ⁇ m-2000 ⁇ m, 2000 ⁇ m-3000 ⁇ m, 3000 ⁇ m-4000 ⁇ m, 4000 ⁇ m-5000 ⁇ m, 5000 ⁇ m-6000 ⁇ m, 6000 ⁇ m-7000 ⁇ m, 7000 ⁇ m-8000 ⁇ m, 8000 ⁇ m-9000 ⁇ m, 90 00 ⁇ m-10000 ⁇ m, 10000 ⁇ m-15000 ⁇ m, 15000 ⁇ m -20000 ⁇ m, 20000 ⁇ m-30000 ⁇ m, 30000 ⁇ m-40000 ⁇ m.
  • the silicon-based device 40 has a width of 100 ⁇ m-1000 ⁇ m.
  • the width of the silicon-based device 40 is 200 ⁇ m-300 ⁇ m, 300 ⁇ m-400 ⁇ m, 400 ⁇ m-500 ⁇ m, 500 ⁇ m-600 ⁇ m, 600 ⁇ m-700 ⁇ m, 700 ⁇ m-800 ⁇ m, 800 ⁇ m-900 ⁇ m, 900 ⁇ m-1000 ⁇ m.
  • the width of the silicon-based device 40 can be understood as the size of the electrode in the silicon-based device 40 along the direction perpendicular to the current flow direction of the silicon-based device 40 .
  • the flow direction of the current I in the silicon-based device 40 is from the first electrode to the second electrode.
  • the width L of the silicon-based device 40 is perpendicular to the direction from the first electrode or the second electrode along the direction from the first electrode to the second electrode. The dimension from one electrode to the second electrode.
  • the flow direction of the current I in the silicon-based device 40 is from the source S′ to the drain D′. Then, the width L of the silicon-based device 40 is perpendicular to the direction from the source to the gate G′. The dimension in the direction from S′ to drain D′.
  • the silicon-based device 40 is usually arranged on the periphery of the core device area including the wide bandgap device 30, and the silicon-based device 40 is close to the semiconductor
  • Silicon-based devices 40 are typically coupled to I/O ports.
  • silicon-based device 40 is coupled between an I/O port and a power/ground line in a semiconductor structure.
  • the trigger voltage of the silicon-based device 40 is smaller than the failure voltage of the wide bandgap device 30 .
  • the semiconductor structure provided by the embodiment of the present application integrates the wide bandgap device 30 and the silicon-based device 40 into the same silicon substrate 10, making full use of the strong electrostatic discharge protection capability of the silicon-based device 40 to supplement the resistance of the wide bandgap device 30.
  • the shortcomings of insufficient electrostatic capability are used to improve the anti-static capability of the wide bandgap device 30 .
  • the epitaxial layer 20 is disposed on the surface of the silicon substrate 10.
  • the epitaxial process is first performed in an epitaxial process factory (step S10), and then the silicon-based device 40 and the wide bandgap device 30 are formed in the device process factory. (Step S20 to Step S40), the formation of the opening 201 where the silicon-based device 40 is located is completed in the process flow after the epitaxial wafer preparation, realizing the process decoupling of the epitaxial process and the device process, and increasing the flexibility of the entire process. degree and reduce costs.
  • the silicon-based device 40 occupies a smaller area, which can reduce parasitic effects (parasitic capacitance, leakage current) and reduce the impact of the silicon-based device 40 on the performance of the wide bandgap device 30 .
  • the wide bandgap device 30 in the present application can be applied to any wide bandgap semiconductor material, and is not limited to epitaxial growth only on SiC semiconductor materials.
  • the silicon-based device 40 can be a variety of types of devices and has a wide range of applications.
  • the wiring stack 50 formed by the back-end process is used to couple the wide bandgap device 30 and the silicon-based device 40, which can provide full-process electrostatic discharge protection from the back-end process to chip packaging and avoid off-chip protection.
  • the wide bandgap device 30 is a homojunction semiconductor device.
  • the wide bandgap device 30 is a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • Embodiments of the present application provide a method for preparing a semiconductor structure, including:
  • an epitaxial film 20' is formed on the silicon substrate 10'.
  • epitaxial film 20' is a homojunction stacked film.
  • a homogeneous junction is a junction formed by the contact of two layers of the same material.
  • film layers with the same material means that the main body material is the same.
  • a buffer film and a surface functional film are formed on the silicon substrate 10'.
  • the buffer film may be one layer, or the buffer film may be multiple layers.
  • the embodiment of the present application is only an illustration.
  • the material of the buffer film may be polycrystalline SiC or polycrystalline gallium oxide (GaO).
  • the material of the surface functional film can be, for example, doped SiC or GaO, and the doping material can be, for example, nitrogen, phosphorus, arsenic, etc.
  • the wide bandgap device 30 may be a SiC-based semiconductor device or a GaO-based semiconductor device.
  • the buffer film and the surface functional film can be formed by the MOCVD growth method or the MBE growth method.
  • an etching process is used to form an opening 201 on the epitaxial film 20' to form the epitaxial layer 20.
  • the method of forming the epitaxial layer 20 may be the same as the method of step S20 in Example 1, and reference may be made to the above related descriptions.
  • the formed epitaxial layer 20 includes a buffer layer and a surface functional layer.
  • an electrode is formed on the epitaxial layer 20 to form a wide bandgap device 30.
  • the wide bandgap device 30 is a FET, and the electrodes formed on the epitaxial layer are the source S, the drain D and the gate G.
  • step S30′ includes:
  • S31' Dope the surface functional layer to form a P-type doped region.
  • the P-type doped region corresponds to the region of the gate G to be formed, and the P-type doped region serves as a channel.
  • the method of forming the N-type doped region can be similar to the method of forming the N-type doped region in Example 1, except that the type of doped donor impurity is different. Please refer to the relevant description of Example 1.
  • S32' Dope the surface functional layer to form an N-type doped region.
  • the N-type doped region corresponds to the region where the source S and drain D are to be formed, and the P-type doped region is located on both sides of the N-type doped region.
  • the method of forming the N-type doped region can be the same as in Example 1. Please refer to the relevant description of Example 1.
  • the source S forms an ohmic contact with the N-type doped region
  • the drain D forms an ohmic contact with another N-type doped region.
  • the gate D is located above the P-type doped region, and a gate insulation layer is provided between the gate D and the P-type doped region.
  • FIG. 13C only takes the wide bandgap device 30 as an N-type MOSFET as an example, and the wide bandgap device 30 may also be a P-type MOSFET.
  • a silicon-based device 40 is formed.
  • Step S40' may be the same as S40 in Example 1, and will not be described again here.
  • Step S50' may be the same as S50 in Example 1, and will not be described again here.
  • the semiconductor structure provided by the embodiment of the present application can be applied to various types of wide bandgap devices 30 and has a wide range of applications.
  • wide bandgap device 30 is not a FET, but a BJT.
  • an epitaxial film 20′ is formed on the silicon substrate 10′.
  • the epitaxial film 20' can be formed by a MOCVD growth method, an MBE growth method, or the like.
  • the epitaxial film 20' is a single film layer.
  • an opening 201 is formed on the epitaxial film 20′ to form the epitaxial layer 20.
  • Step S20′′ may be the same as step S20 in Example 1, and reference may be made to the above related descriptions.
  • an electrode is formed on the epitaxial layer 20 to form a wide bandgap device 30.
  • the wide bandgap device 30 is a BJT
  • the electrodes formed on the epitaxial layer 20 are a base electrode (B), a collector electrode (C), and an emitter electrode (E).
  • step S30′′ includes:
  • a silicon-based device 40 is formed.
  • Step S40′′ may be the same as S40 in Example 1, and will not be described again here.
  • Step S50′′ may be the same as S50 in Example 1, and will not be described again here.
  • the BJT can be an NPN transistor or a PNP transistor.
  • This example is just an illustration.
  • the above illustrates a BJT, and the wide bandgap device 30 in the embodiment of the present application may also be a heterojunction bipolar transistor (HBT).
  • HBT heterojunction bipolar transistor
  • the semiconductor structure provided by the embodiment of the present application can be applied to various types of wide bandgap devices 30 and has a wide range of applications.

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Abstract

本申请实施例提供一种半导体结构及制备方法、射频前端模组、电源转换模组、电子设备，涉及半导体技术领域，用于提高半导体结构中宽禁带器件的抗静电性能。半导体结构可以是PA芯片、LNA芯片、电源转换芯片带静电放电防护的芯片等。半导体结构包括硅衬底和设置在硅衬底上的外延层。外延层具有露出硅衬底的开口，开口是通过刻蚀工艺形成，围成开口的轮廓面上的原子呈非晶态或者多晶态排布。电极，设置于外延层上、与外延层构成宽禁带器件。硅基器件作为静电放电防护器件，位于开口内、且伸入硅衬底中。

Description

半导体结构、射频前端模组、电源转换模组、电子设备
本申请要求于2022年08月27日提交国家知识产权局、申请号为202211036160.2、申请名称为“半导体结构、射频前端模组、电源转换模组、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构、射频前端模组、电源转换模组、电子设备。
背景技术
硅(Si)材料因为性质稳定、制备成本低等优良特性，成为了半导体产业中使用最为广泛的材料。但随着工业智能化的推进，越来越多的应用场景(如射频、功率电子等领域)对芯片提出了诸如更快速度、更高耐压的要求。Si材料由于其材料本身的限制，无法同时满足上述需求。而部分宽禁带化合物半导体如碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)等恰好拥有高载流子迁移率、更高载流子密度和更高耐压的性能优势，逐渐被广泛的应用于半导体产业中。
然而，采用宽禁带化合物半导体制备而成的宽禁带半导体器件中通常存在异质结(不同材料层叠而成)，而异质结界面上不同材料的热膨胀系数和压电系数不同，导致宽禁带半导体器件在静电放电(ESD event)的高压、大电流条件下易发生异质结界面损坏。因此，目前宽禁带半导体器件的抗静电(ESD immunity)性能大都较弱。
发明内容
本申请实施例提供一种半导体结构、射频前端模组、电源转换模组、电子设备，用于提高半导体结构中宽禁带半导体器件的抗静电性能。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种半导体结构，半导体结构可以是PA芯片、LNA芯片、电源转换芯片带静电放电防护的芯片等。半导体结构包括硅衬底和设置在硅衬底上的外延层。外延层可以为单层或者多层结构，外延层具有露出硅衬底的开口(贯穿外延层)，开口是通过刻蚀工艺形成，围成开口的轮廓面上的原子呈非晶态或者多晶态排布。电极，设置于外延层上、与外延层构成宽禁带器件。宽禁带器件作为被保护器件，宽禁带器件可以是FET，那么，电极可以是源极、漏极以及栅极。或者，宽禁带器件可以是BJT，那么，电极可以是基极、集电极以及发射极。硅基器件作为静电放电防护器件，位于开口内、且伸入硅衬底中。
本申请实施例提供的半导体结构，将宽禁带器件与硅基器件集成在同一硅衬底中，充分利用硅基器件较强的静电放电防护能力，补足宽禁带器件抗静电能力不足的短板，以提高宽禁带器件的抗静电能力。且，无需对宽禁带器件与硅基器件进行封装，半导体结构的面积较小。另外，外延层设置在硅衬底的表面上，在制备过程中，先在外延工艺厂进行外延工艺，然后再在器件工艺厂形成硅基器件和宽禁带器件，硅基器件所在的开口的形成，是在外延片制备之后的工艺流程中完成，实现外延工艺与器件工艺在流程上的解耦，增加了整套流程的灵活度，降低成本。再者，除了外延层中的开口所在区域用于制备硅基器件，其余区域全都可以用于制备宽禁带器件。外延层使用的灵活性提高，且硅基器件的面积占较小，可减小寄生效应(寄生电容、漏电流)，降低硅基器件对宽禁带器件性能的影响。而且，本申请中的宽禁带器件可以适用于任意宽禁带半导体材料，不限定为仅在SiC半导体材料上外延生长。且硅基器件可以为多种类型的器件，适用范围广。
在一种可能的实现方式中，开口具有上端口和下端口，下端口相对上端口靠近硅衬底；上端口在硅衬底上具有第一投影，下端口在硅衬底上具有第二投影，第一投影覆盖第二投影。或者理 解为，上端口的面积大于下端口的面积。这样一来，开口的轮廓面为斜面，在后续制备过程中在开口轮廓面上层叠的膜层也为斜面。那么后续形成的布线叠层中的金属线层能够沉积在斜面上，而不是沉积在直角面上，可降低金属线层在开口轮廓面对应位置处(跨区域互连线)断裂的风险。
在一种可能的实现方式中，上端口的第一轮廓与下端口的第二轮廓之间的间距大于200nm。通过使上端口比下端口大至少200nm，可使轮廓面形成的坡度有助于金属线层的沉积，较大程度的降低金属线层在开口轮廓面对应位置处断裂的风险。
在一种可能的实现方式中，第一投影的轮廓到第二投影的轮廓的距离小于1μm。通过将上端口与下端口的尺寸之差限定在小于1μm，可减小轮廓面的占用面积，提高半导体结构的集成度。
在一种可能的实现方式中，轮廓面与外延层底面的夹角的取值范围为45°～88°。通过限定轮廓面与外延层底面的夹角的取值范围，使得轮廓面的倾斜程度不受外延层厚度的影响，以使得各种类型的半导体结构的金属线层的良率均有保证。
在一种可能的实现方式中，硅衬底朝向外延层的表面为平面。也就是说，本申请中是在硅衬底来片后，直接外延形成外延层，无需在硅衬底中进行掺杂形成SiC后再进行外延，工艺简单，成本低。
在一种可能的实现方式中，硅基器件的面积大于宽禁带器件的面积。这样一来，硅基器件的静电放电防护效果好。
在一种可能的实现方式中，半导体结构包括静电放电保护器件单元，静电放电保护器件单元包括硅基器件。这样一来，半导体结构为具有静电放电防护效果的芯片。
在一种可能的实现方式中，硅基器件为双极性晶体管、二极管、可控硅整流器或者金属-氧化物半导体场效应晶体管。这是一种可能的实现方式。
在一种可能的实现方式中，宽禁带器件为场效应晶体管或者双极型晶体管。这是一种可能的实现方式。
在一种可能的实现方式中，半导体结构还包括布线叠层，布线叠层覆盖宽禁带器件单元和硅基器件单元；宽禁带器件单元和硅基器件单元通过布线叠层耦接。利用后段制程形成的布线叠层将宽禁带器件与硅基器件耦接，能够从后段制程开始至贴片封装，提供全流程的静电放电防护，避免了片外防护方案(将硅基器件与氮化镓基器件封装)带来的防护空白期。
在一种可能的实现方式中，半导体结构为功率放大器芯片、低噪声放大器芯片或者电源转换芯片。这是一种可能的实现方式。
本申请实施例的第二方面，提供一种半导体结构的制备方法，包括：在硅基底上形成外延膜；采用刻蚀工艺，在外延膜上形成开口，形成外延层；其中，开口露出硅基底；在外延层上形成电极，电极与外延层构成宽禁带器件；在硅基底被开口露出的区域内形成硅基器件，并形成硅衬底；硅基器件位于开口内、且伸入硅衬底中。
本申请实施例提供半导体结构的制备方法的有益效果与第一方面提供的半导体结构的有益效果相同，此处不再赘述。
在一种可能的实现方式中，开口具有上端口和下端口，下端口相对上端口靠近硅衬底；上端口在硅衬底上具有第一投影，下端口在硅衬底上具有第二投影，第一投影覆盖第二投影。
在一种可能的实现方式中，上端口的第一轮廓与下端口的第二轮廓之间的间距大于200nm。通过使上端口比下端口大至少200nm，可使轮廓面形成的坡度有助于金属线层的沉积，较大程度的降低金属线层在开口轮廓面对应位置处断裂的风险。
在一种可能的实现方式中，第一投影的轮廓到第二投影的轮廓的距离小于1μm。通过将上端口与下端口的尺寸之差限定在小于1μm，可减小轮廓面的占用面积，提高半导体结构的集成度。
在一种可能的实现方式中，围成开口的轮廓面与外延层底面的夹角的取值范围为45°～88°。通过限定轮廓面与外延层底面的夹角的取值范围，使得轮廓面的倾斜程度不受外延层厚度的影响，以使得各种类型的半导体结构的金属线层的良率均有保证。
在一种可能的实现方式中，围成开口的轮廓面上的原子呈非晶态或者多晶态排布。
在一种可能的实现方式中，硅基器件为双极性晶体管、二极管、可控硅整流器或者金属-氧化物半导体场效应晶体管。
在一种可能的实现方式中，在外延层上形成电极，包括：在外延层上形成源极和漏极；形成硅基器件，包括在硅衬底上形成第一电极和第二电极；形成源极和漏极、以及第一电极和第二电极之后，进行欧姆接触退火处理。
在一种可能的实现方式中，制备方法还包括：形成布线叠层；布线叠层覆盖宽禁带器件和硅基器件；宽禁带器件和硅基器件通过布线叠层耦接。
本申请实施例的第三方面，提供一种射频前端模组，包括第一方面任一项的半导体结构和射频开关，射频开关与半导体结构耦接。
本申请实施例提供的射频前端模组包括第一方面的半导体结构，其有益效果与半导体结构的有益效果相同，此处不再赘述。
本申请实施例的第四方面，提供一种电源转换模组，包括第一方面任一项的半导体结构和变压器，半导体结构与变压器耦接。
本申请实施例提供的电源转换模组包括第一方面的半导体结构，其有益效果与半导体结构的有益效果相同，此处不再赘述。
本申请实施例的第五方面，提供一种电子设备，包括第三方面的射频前端模组和/或第四方面的电源转换模组。
附图说明
图1A为本申请实施例提供的电子设备的框架示意图；
图1B为本申请实施例提供的电子设备局部框架示意图；
图1C为本申请实施例示意的一种射频系统的框架示意图；
图1D为本申请实施例提供的一种射频系统的框架示意图；
图2A为本申请实施例示意的一种电源转换模组的框架示意图；
图2B为本申请实施例提供的一种电源转换芯片的框架示意图；
图3A为本申请实施例示意的一种P-i-N管的结构示意图；
图3B为本申请实施例提供的另一种电源转换芯片的框架示意图；
图4A为本申请实施例示意的一种半导体结构的制备过程示意图；
图4B为图4A所示的半导体结构的区域划分示意图；
图5A为本申请实施例提供的一种半导体结构的结构示意图；
图5B为本申请实施例提供的一种原子的排布方式示意图；
图6为本申请实施例提供的一种半导体结构的制备流程示意图；
图7A-图9F为本申请实施例提供的一种半导体结构的制备过程示意图；
图10为本申请实施例提供的一种半导体结构的区域划分示意图；
图11A和图11B为本申请实施例提供的硅基器件宽度测量方法示意图；
图12为本申请实施例提供的一种硅基器件和宽禁带器件的相对位置关系示意图；
图13A-图13E为本申请实施例提供的另一种半导体结构的制备过程示意图；
图14A-图14E为本申请实施例提供的又一种半导体结构的制备过程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第二”、“第一”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第二”、“第一”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请实施例中，“上”、“下”、“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连 接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“相耦接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。术语“接触”可以是直接接触，也可以是通过中间媒介间接的接触。
本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
本申请实施例提供一种的电子设备。该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、通信电子产品。其中，消费性电子产品如为手机(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机、汽车等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载高密度数字视频光盘(digital video disc，DVD)等。金融终端产品如为自动取款机(automated teller machine，ATM)机、自助办理业务的终端等。通信电子产品如为服务器、存储器、雷达、基站等通信设备。
图1A为本申请实施例示例性地提供的一种电子设备的结构示意图。如图1A所示，该电子设备100可以包括处理器110，外部存储器接口120，内部存储器121，通用串行总线(universal serial bus，USB)接口130，充电管理单元140，电源管理单元141，电池142，有线通信系统150，无线通信系统160，音频单元170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，传感器单元180，按键190，马达191，指示器192，摄像头193，显示屏194，用户标识单元(subscriber identification module，SIM)卡接口195以及天线1，天线2等。
可以理解的是，本申请实施例示意的结构并不构成对电子设备100的具体限定。在本申请另一些实施例中，电子设备100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
处理器110可以包括一个或多个处理单元，例如：处理器110可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。控制器可以根据指令操作码和时序信号，产生操作控制信号，完成取指令和执行指令的控制。
处理器110中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器110中的存储器为高速缓冲存储器。该存储器可以保存处理器110刚用过或循环使用的指令或数据。如果处理器110需要再次使用该指令或数据，可从所述存储器中直接调用。避免了重复存取，减少了处理器110的等待时间，因而提高了系统的效率。
在一些实施例中，处理器110可以包括一个或多个接口。接口可以包括集成电路(inter-integrated circuit，I2C)接口，集成电路内置音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口，用户标识单元(subscriber identity module，SIM)接口，和/或通用串行总线(universal serial bus，USB)接口等。
USB接口130是符合USB标准规范的接口，具体可以是Mini USB接口，Micro USB接口，USB Type C接口等。
充电管理单元140用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器。
电源管理单元141用于连接电池142，充电管理单元140与处理器110。电源管理单元141接收电池142和/或充电管理单元140的输入，为处理器110，内部存储器121，显示屏194，摄像头193和无线通信系统160等供电。电源管理单元141还可以用于监测电池容量，电池循环次数， 电池健康状态(漏电，阻抗)等参数。
电子设备100通过GPU，显示屏194，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏194和应用处理器。
显示屏194用于显示图像，视频等。在一些实施例中，电子设备100可以包括1个或N个显示屏194，N为大于1的正整数。
电子设备100可以通过ISP，摄像头193，视频编解码器，GPU，显示屏194以及应用处理器等实现拍摄功能。
ISP用于处理摄像头193反馈的数据，摄像头193用于捕获静态图像或视频，视频编解码器用于对数字视频压缩或解压缩。
外部存储器接口120可以用于连接外部存储卡，例如Micro SD卡，实现扩展电子设备100的存储能力。
内部存储器121可以用于存储计算机可执行程序代码，所述可执行程序代码包括指令。
电子设备100可以通过音频单元170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，以及应用处理器等实现音频功能。
音频单元170用于将数字音频信息转换成模拟音频信号输出，也用于将模拟音频输入转换为数字音频信号。扬声器170A用于将音频电信号转换为声音信号。受话器170B用于将音频电信号转换成声音信号。麦克风170C用于将声音信号转换为电信号。耳机接口170D用于连接有线耳机。
传感器单元180可以包括图像传感器、压力传感器、磁传感器、距离传感器等，图像传感器例如可以为接触式图像传感器(contact image sensor，CIS)。
按键190包括开机键，音量键等。马达191可以产生振动提示。指示器192可以是指示灯，可以用于指示充电状态，电量变化，也可以用于指示消息，未接来电，通知等。SIM卡接口195用于连接SIM卡。
电子设备100的通信功能可以通过天线1，天线2，有线通信系统150、无线通信系统160、调制解调处理器以及基带处理器等实现。
调制解调处理器可以包括调制器和解调器。其中，调制器用于将待发送的低频基带信号调制成中高频信号。解调器用于将接收的电磁波信号解调为低频基带信号。随后解调器将解调得到的低频基带信号传送至基带处理器处理。低频基带信号经基带处理器处理后，被传递给应用处理器。应用处理器通过音频设备(不限于扬声器，受话器等)输出声音信号，或通过显示屏194显示图像或视频。
天线1和天线2用于发射和接收电磁波信号。电子设备100中的每个天线可用于覆盖单个或多个通信频带。不同的天线还可以复用，以提高天线的利用率。例如：可以将天线1复用为无线局域网的分集天线。在另外一些实施例中，天线可以和调谐开关结合使用。
有线通信系统150可以提供应用在电子设备100上的包括2G/3G/4G/5G等无线通信的解决方案。有线通信系统150可以包括射频前端模组。有线通信系统150可以由天线1接收电磁波，并通过射频前端模组对接收的电磁波进行滤波，放大等处理，传送至调制解调处理器进行解调。有线通信系统150还可以对经调制解调处理器调制后的信号放大，经天线1转为电磁波辐射出去。在一些实施例中，有线通信系统150的至少部分功能单元可以被设置于处理器110中。在一些实施例中，有线通信系统150的至少部分功能单元可以与处理器110的至少部分单元被设置在同一个器件中。
无线通信系统160可以提供应用在电子设备100上的包括无线局域网(wireless local area networks，WLAN)(如无线保真(wireless fidelity，Wi-Fi)网络)，蓝牙(bluetooth，BT)，全球导航卫星系统(global navigation satellite system，GNSS)，调频(frequency modulation，FM)，近距离无线通信技术(near field communication，NFC)，红外(infrared，IR)技术等无线通信的解决方案。无线通信系统160可以是集成一个或多个通信处理单元的一个或多个器件。无线通信系统160经由天线2接收电磁波，将电磁波信号调频以及滤波处理，将处理后的信号发送到处理器110。无线通信系统160还可以从处理器110接收待发送的信号，对其进行调频，放大，经天线2转为电磁波辐射出去。
在一些实施例中，电子设备100的天线1和有线通信系统150耦合，天线2和无线通信系统160耦合，使得电子设备100可以通过无线通信技术与网络以及其他设备通信。该无线通信技术可以包括全球移动通讯系统(global system for mobile communications，GSM)，通用分组无线服务(general packet radio service，GPRS)，码分多址接入(code division multiple access，CDMA)，宽带码分多址(wideband code division multiple access，WCDMA)，时分码分多址(time-division code division multiple access，TD-SCDMA)，长期演进(long term evolution，LTE)，BT，GNSS，WLAN，NFC，FM，IR技术等。该GNSS可以包括全球卫星定位系统(global positioning system，GPS)，全球导航卫星系统(global navigation satellite system，GLONASS)，北斗卫星导航系统(beidou navigation satellite system，BDS)，准天顶卫星系统(quasi-zenith satellite system，QZSS)和/或星基增强系统(satellite based augmentation systems，SBAS)。
上述的电子设备100还包括电路板，例如印刷电路板(printed circuit board，PCB)。电子设备100中的一些电子器件例如处理器100、内部存储器121、射频前端模组、电源管理单元141等可以设置在电路板上。
如图1B所示，本申请实施例提供一种射频系统，射频系统可以应用于上述电子设备100的无线通信系统160中。射频系统包括射频收发机200、收发器300、基带400以及通用处理器500。
其中，射频收发机200包括射频前端模组210和天线2，射频前端模组210通过匹配网络与天线2耦合。接收路径中，天线2接收信号，传输至射频前端模组210，射频前端模组210对接收到的信号进行混频滤波和信号放大。发送路径中，射频前端模组210对信号进行混频和功率放大后，传输至天线2。
天线2可以封装在射频前端模组210内部，也可以不封装在射频前端模组210内部，本申请实施例以天线2不封装在射频前端模组210内部为例进行示意。
继续参考图1B，射频前端模组210、收发器300、基带400以及通用处理器500例如可以设置在电子设备100的电路板上。
本申请实施例还提供一种射频前端模组210，如图1C所示，包括射频开关芯片211、匹配网络212、低噪声放大器(low noise amplifier，LNA)芯片213、功率放大器(power amplifier，PA)芯片214等。
接收通道中，天线2接收到的信号，通过射频开关芯片211转至匹配网络212经LNA芯片213进行信号放大后输出至收发器300；通过收发器300进行下变频、滤波后，将解调信号输出至基带400进行解码(将模拟信号转换为数字信号)；基带400解码的有效数据传输至通用处理器500使用。
发射通道中，通用处理器500将数据传至基带400进行编码；基带400将编码后的信号传至收发器300；收发器300将信号调制后转由PA芯片214放大后，经由射频开关芯片211传至天线2进行发射。
其中，LNA芯片213包括多个级联的放大器，PA芯片214包括多个级联的放大器，LNA和PA例如可以是由宽禁带半导体器件构成的电路结构，以使LNA和PA具有更快速度和更高耐压的性能。
然而，宽禁带半导体器件的抗静电性能(immunity to electrostatic discharge，又称ESD immunity)较弱，导致LNA和PA容易损坏，是一个需要解决的技术问题。
基于此，如图1D所示，本申请实施例还提供一种LNA芯片213和PA芯片214，LNA芯片213和PA芯片214可以应用于上述射频前端模组210中。
如图1D所示，LNA芯片213包括与LNA耦接的第一静电放电(electrostatic discharge，ESD)保护单元，PA芯片214包括与PA耦接的第二ESD保护单元。通过在LNA芯片213中设置与LNA耦接的第一ESD保护单元，以弥补LNA抗静电性能弱的短板。同理，通过在PA芯片214中设置与PA耦接的第二ESD保护单元，以弥补PA抗静电性能弱的短板。
电子设备100中由宽禁带半导体器件构成的电路还包括电源转换模组，电源转换模组应用于电子设备100的电源管理单元中141，电源转换模组也存在抗静电性能较弱的问题。
基于此，本申请实施例还提供一种电源转换模组，如图2A所示，电源转换模组60包括电源 转换芯片61和变压器62，电源转换芯片61的输出端和变压器62耦接。
继续参考图2A，电源转换芯片包括控制端口611、被保护电路612、电源线613、地线614以及电源钳位单元615。由于被保护电路612包括宽禁带半导体器件，被保护电路612例如可以包括高电子迁移率晶体管(high electron mobility transistor，HEMT)。因此，如图2A所示，电源转换芯片61还包括两个静电放电保护单元ESD，静电放电保护单元ESD例如为二极管。
图2A示意一种由二极管和电源钳位单元615组成的基于电源轨的静电放电防护网络。控制端口611输入的正向脉冲可通过上拉二极管泄放至电源线613，再由电源钳位单元615泄放至地线614。控制端口611至地线614的电压被钳制为二极管导通时的压降及电源钳位单元615的压降之和。控制端口611输入的负向脉冲则由电源钳位单元615和上拉二极管完成钳位。这种方案从控制端口611视入会有一正一负两个二极管，寄生电容较大，因此不适用于对寄生参数敏感的场景。
基于此，本申请实施例还提供一种电源转换芯片61，电源转换芯片61可以应用于电源转换模组60中。如图2B所示，电源转换芯片61还包括控制端口611、被保护电路612、电源线613、地线614以及静电放电保护单元ESD。图2B示意的为一种局部静电放电防护网络，静电放电保护单元ESD既用于对被保护电路612进行静电放电保护，又用于对被保护电路612进行双向钳位。示例的，静电放电保护单元ESD为二极管，当控制端口611输入的正向脉冲超过PN结导通电压后，电流随电压指数增长，实现正向电压钳位。当控制端口611输入的负向脉冲超过PN结反向击穿电压后，雪崩电离产生，电流随电压指数增长，实现反向电压钳位。在一个实施例中，局部静电放电防护网络可以是指的是对单端口的保护。
下面，对图1D所示的LNA芯片213和PA芯片214中的静电放电保护单元ESD、以及图2B所示的电源转换芯片中的静电放电保护单元ESD的结构，进行示意说明。
宽禁带化合物半导体如碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)、氧化镓(GaO)等恰好拥有高载流子迁移率、更高载流子密度和更高耐压的性能优势，逐渐被广泛的应用于半导体产业中。但是，限制其大规模应用的因素之一是材料制备成本。
一种低成本制备方法是在Si(硅)晶圆上外延生长上述宽禁带化合物半导体层，再以宽禁带化合物半导体为基础制作器件。
示例的，在一些技术中，如图3A所示，在Si衬底上外延生长宽禁带化合物半导体层，在一个实施例中，宽禁带化合物半导体层包括缓冲层和GaN叠层。
在宽禁带化合物半导体叠层中制备静电放电保护单元ESD，在一个实施例中，静电放电保护单元ESD为P-i-N二极管，通过调控外延生长GaN层阶段的掺杂物，可在纵向层叠的外延层中形成P-i-N二极管。在一个实施例中，掺入Si或C(碳)形成N型GaN，掺入Mg(镁)形成P型GaN，i型GaN无需掺杂，i型GaN层也可以称为本征GaN层。GaN叠层表面覆盖有介质层70，金属正极P通过介质层70上的第一开口71与P型GaN层接触耦接，金属负极N通过介质层70上的第二开口72与N型GaN层接触耦接。P-i-N二极管正向导通电压可由i-GaN层的厚度来调节，负向击穿电压较高。
当需要应用于图2B中满足双向钳位时，可以按照图3B所示的方式，将两个相反的P-i-N二极管并联，就可实现双向钳位。
但是，图3A示意的P-i-N二极管，由于P型GaN层和N型GaN层之间有i型GaN层，导致P型GaN层和N型GaN层之间的距离增大，所以P-i-N二极管的导通电阻较大，作为静电放电保护单元ESD效率不高。而且，如图3B所示，采用两个相反的P-i-N二极管并联构成静电放电保护单元ESD，从控制端口视入也是有一正一负两个二极管，寄生电容依旧较大。再者，由于同一个晶圆(wafer)上的i-GaN层的厚度是固定的，无法调节。导致在同一晶圆上无法制备出不同导通电压的P-i-N二极管，无法满足不同需求。此外，P-i-N二极管反偏结电容受偏压影响较大，用于高速端口会引起辐射杂散(radiated spurious emission，RSE)问题。
相较于宽禁带化合物半导体叠层制备的静电放电保护单元ESD，Si基器件作为静电放电防护器件可挑选的种类更多且性能更强。基于此，在另一些技术中，采用Si基器件作为静电放电保护单元ESD，以提高静电放电保护单元ESD的静电放电保护效果。
在一些实现方式中，将Si基器件与GaN基器件分别绑定在基板中，通过封装的方式形成结合有Si基器件与GaN基器件的半导体结构。这样会导致工艺复杂，且形成的半导体结构的尺寸较大。
在另一些实现方式中，如图4A所示，将宽禁带化合物基器件和Si基器件集成在同一半导体结构中的实现方式如下：
S1、先用光刻在Si衬底表面定义GaN基器件区和Si基器件区，光刻胶保护住Si基器件区。
S2、离子注入C，使C进入GaN基器件区的Si衬底。
然后，去除光刻胶，并高温退火，含C的Si在高温下结晶形成SiC。
S3、控制外延生长条件，使缓冲层、GaN层和AlGaN(铝镓氮)层等外延层只在SiC上形成。
可以理解的是，通过步骤S3形成的外延层的侧面的原子应呈晶态排布。也就是说，SiC区和Si区交界处，外延层的侧面的原子应呈晶态(crystalline)排布。
S4、在Si基器件区域制作Si基器件，在GaN基器件区域制作GaN基器件。
后续可以通过后段制程(back end of line)，将Si基器件和GaN基器件连接。
如图4B所示，以半导体器件为电源转换芯片为例，通过上述制备方法制备得到的半导体器件中，需要设置GaN基器件区是固定的，也就是说，外延层覆盖区的范围是固定的，除外延层覆盖区之外，其余区域都是Si基器件区。也就是说，Si基底中，填充部分属于外延层覆盖区，非填充部分属于Si基器件区。
上述制备方法可以将GaN基器件和Si基器件集成在同一半导体结构中，并在外延生长前就要定义出对应的器件区域，使得外延片使用的灵活度较低。另外，通过向Si衬底注入C后退火形成SiC的工艺难度较高，成本较高。再者，上述方法只适用于SiC作为过渡缓冲层的半导体器件中，适用范围局限。此外，在制备过程中，需要先在器件工艺厂形成SiC(步骤S1和S2)，然后在外延工艺厂进行外延(步骤S3)，最后再返回器件工艺厂形成Si基器件和GaN基器件(步骤S4)。那么，需要在器件工艺厂和外延工艺厂来回调换，且需要器件工艺厂和外延工艺厂相配合，从而导致制备成本增加。
基于此，本申请实施例还提供一种半导体结构，半导体结构中集成有宽禁带化合物基器件和Si基器件，宽禁带化合物基器件包括被保护电路，Si基器件包括静电放电保护单元ESD。
此处需要说明的是，本申请实施例提供的半导体结构，可以是裸芯片(die)、封装后的芯片或者晶圆(wafer)等。
如图5A所示，半导体结构主要包括：硅衬底10、外延层20、宽禁带器件30以及硅基器件40。
外延层20设置在硅衬底10的表面，且覆盖硅衬底10。外延层20上具有沿外延层20厚度方向贯穿外延层20的开口201，围成开口201的轮廓面Z上的原子呈非晶态(amorphous)或者多晶态(polycrystalline)排布。
如图5B中的左图所示，原子呈晶态排布时，晶体原子是位置固定(也可以说，位置规律)的晶格排列。如图5B中位于中间的图所示，原子呈非晶态排布时，晶体原子是位置不固定(也可以说，位置没有规律)的堆积排列。如图5B中位于右侧的图所示，原子呈多晶态排布时，原子呈长程无序、短程有序的状态。即，每个立方体格中的原子呈有序排列，但立方体格之间呈杂乱无章排布。
宽禁带器件30设置在外延层20上，硅基器件40位于开口201内、且伸入硅衬底10中。
其中，宽禁带器件30可以为场效应晶体管(field effect transistor，FET)或者双极型晶体管(bipolar junction transistor，BJT)。硅基器件40可以为双极性晶体管、二极管、可控硅整流器或者金属-氧化物半导体场效应晶体管。
下面，结合本申请实施例提供的半导体结构的制备方法，对本申请实施例提供的半导体结构进行示意说明。示例的，半导体结构中宽禁带器件30为结型场效应管(junction field effect transistor，JFET)。下面，结合半导体结构的制备方法对半导体结构进行示意说明。
如图6所示，本申请实施例提供一种半导体结构的制备方法，包括：
S10、如图7A所示，在硅基底10′上形成外延膜20′。
硅基底10′例如可以是硅晶圆，或者对硅晶圆进行切割得到的单粒结构。在硅基底10′为硅晶圆的情况下，硅基底10′中可以包括多个芯片区，最终制备得到的半导体器件可以为晶圆。当然也可以通过切割，对晶圆进行切割，得到裸芯片(die)或者封装后的芯片。在硅基底10′为单粒结构的情况下，最终制备得到的半导体器件可以为裸芯片(die)，或者封装后的芯片。下面示意的制备过程仅是对一个芯片区的结构进行示意说明。
其中，硅基底10′的晶向和预掺杂浓度取决于外延材料的类型和应用场景。示例的，硅基底10′的晶向指数为[111]，掺杂类型可能为本质(无掺杂)或P型掺杂(浓度为1e15cm^-3，或者是1*1015/cm3)。其中，晶向是指在晶体中任何一条穿过许多质点的直线方向，晶向指数为晶向上某质点原子坐标的最简整数比。应理解，晶体中不同的晶向，常常具有不同的线密度等不同属性，为区分晶体的这些晶向，引入晶向指数。本申请中的晶向指数为[111]仅作为示意，并不用于限定。
除掺杂外，硅基底10′的各处材料为硅，硅基底10′的表面为平面。当然，工艺误差范围内的表面高度差应属于本申请实施例中平面的保护范围。
此处，外延膜20′可以包括一层或者多层外延膜层。也可以理解为是本领域常称的外延片。
在一些实施例中，外延膜20′包括多层外延膜层，外延膜20′为异质结堆叠膜。
异质结，是由两种材料不同的膜层相接触形成的结，这两种材料的晶格常数是不同的，因此会产生晶格失配。
示例的，如图7A所示，外延膜20′包括依次层叠设置在硅基底10′上的成核膜、缓冲膜、沟道膜、插入膜、势垒膜以及保护膜。
本申请实施例对成核膜、缓冲膜、沟道膜、插入膜、势垒膜以及保护膜的材料不做限定，沟道膜和势垒膜的材料不同、且各膜层的材料属于宽禁带半导体化合物即可。
示例的，各膜层的材料为III-V半导体(IIIA族元素和VA族元素构成的半导体化合物)、III-VI半导体(IIIA族元素和VIA族元素构成的半导体化合物)或者V-VI半导体(VA族元素和VIA族元素构成的半导体化合物)。
在一个实施例中，成核膜设置在硅基底10′上，例如，成核膜设置在硅基底10′的表面上。形成成核膜的方法，例如可以通过金属有机化合物化学气相沉淀(metal-organic chemical vapor deposition，MOCVD)生长法或分子束外延(molecular beam epitaxy，MBE)生长法等。成核膜的材料，例如可以包括GaN、AlGaN、氮化铝(AlN)中一种或多种。
成核膜的作用是将硅基底10′的晶格结构与沟道膜的晶格结构进行匹配，例如，可以先在硅基底10′上放置与硅基底10′的晶格结构差异较小的成核膜，然后再在成核膜上制作与成核膜的晶格结构差异较小的沟道膜。
在一个实施例中，缓冲膜设置于成核膜远离硅基底10′上，例如，缓冲膜设置于成核膜远离硅基底10′的表面上。形成缓冲膜的方法，例如可以采用MOCVD或者MBE工艺外延生缓冲膜。缓冲膜的材料，例如可以包括GaN。
缓冲膜的作用是，缓冲膜和沟道膜的禁带宽度不同，可以使得势垒膜与沟道膜形成的异质结的势阱深度更深，从而提高二维电子气(two-dimensional electron gas，2DEG)的浓度。
在一个实施例中，沟道膜设置于缓冲膜上，例如沟道膜设置于缓冲膜的表面上。形成沟道膜的方法，例如可以通过MOCVD生长法或MBE生长法等。上述沟道膜的材料例如可以包括GaN、AlGaN、铟氮化铝(InAlN)、AlN、钪氮化铝(ScAlN)中一种或多种。
在一个实施例中，插入膜设置于沟道膜上，例如，插入膜设置于沟道膜的表面上。形成插入膜的方法，例如可以采用MOCVD生长法或MBE生长法等。插入膜的材料例如可以是GaN、AlGaN、AlN中一种或多种。
在沟道膜和势垒膜之间设置插入膜，可以提高2DEG的浓度。
在一个实施例中，势垒膜设置于插入膜上，例如，势垒膜设置于插入膜的表面上。形成势垒膜的方法，例如可以通过MOCVD生长法或MBE生长法等。势垒膜的材料例如可以包括GaN、AlGaN、InAlN、AlN、ScAlN中一种或多种。
可以理解的是，沟道膜和势垒膜构成半导体器件的异质结，沟道膜的上方产生二维电子气。 因此，沟道膜和势垒膜的材料不相同。示例的，沟道膜的材料包括GaN，势垒膜的材料包括AlGaN。
在一个实施例中，盖帽膜设置于势垒膜上，例如，盖帽膜设置于势垒膜的表面上。形成盖帽膜的方法，例如可以通过MOCVD生长法或MBE生长法形成盖帽膜。盖帽膜的材料，例如可以为GaN或者氮化硅(Si3N4)。
通过在势垒膜上形成盖帽膜，可对势垒膜起到保护作用，防止势垒膜表面被氧化，可降低半导体器件的表面态。降低半导体器件的导通电阻，可以降低半导体器件的栅极漏电和功耗，从而提高半导体器件的可靠性。
图7A所示的外延膜20′的结构仅为一种示意，不做任何限定。外延膜20′中至少包括沟道膜以及势垒膜。
S20、如图7B所示，采用刻蚀工艺，在外延膜20′上形成开口201，以形成外延层20。
其中，开口201沿外延膜20′的厚度方向贯穿外延膜20′，开口201露出硅基底10′。因此，成核膜、缓冲膜、沟道膜、插入膜、势垒膜以及保护膜分别具有开口，各膜层上的开口连通，构成外延膜20′上的开口201。在一个实施例中，外延层20包括成核层、缓冲层、沟道层、插入层、势垒层以及保护层。应可理解，如图7B所示的外延层20的结构仅为一种示意，不做任何限定，外延层20至少包括沟道层以及势垒层。
另外，外延膜20′形成在硅基底10′的表面上，那么，外延膜20′覆盖硅基底10′的全部表面。在外延膜20′上形成开口201后，硅基底10′中除了被开口201露出的部分，其余部分均被外延层20覆盖。
在一些实施例中，步骤S20包括：
S21、在外延膜20′上形成光刻胶层，光刻胶层具有光刻胶图案，或者称为光刻胶开口，光刻胶开口对应待形成的开口201。
需要注意的是，本申请实施例中所提及的光刻胶均为正性光刻胶，即光照后可将光刻胶激活，然后去除激活的光刻胶。当然在现实的操作中也可以采用负性光刻胶，需要注意的是负性光刻胶是光照后不会被激活，没有光照的会被激活。无论是使用正性光刻胶和负性光刻胶，均属于本申请的实施例的保护范围。
S22、采用刻蚀工艺，去除光刻胶开口下方的外延膜20′，形成具有开口201的外延层20，开口201露出硅基底10′。
例如，可以采用干法刻蚀去除光刻胶开口下方的外延膜20′。示例的，采用反应离子刻蚀(reactive ion etching，RIE)工艺、电感耦合等离子体(Inductive Coupled Plasma，ICP)刻蚀工艺、离子束刻蚀(Ion Beam Etching，IBE)工艺等刻蚀工艺形成开口201。
正常情况下，外延膜20′中原子呈晶态排布，外延膜20′的侧面会具有较为完整的晶格结构。但对外延膜20′进行刻蚀后，刻蚀面(围成开口201的轮廓面)会有刻蚀的痕迹，留下物理损伤。刻蚀面上的晶格结构被破坏，原子排布呈非晶态或者多晶态。通过聚焦离子束(focused ion beam，FIB)切片和透射电子显微镜(transmission electron microscope，TEM)观察器件形貌，即可判断开口201是否是经过刻蚀工艺制备得到。
在一些实施例中，如图7B所示，开口201具有上端口a和下端口b，下端口b相对上端口a靠近硅基底10′，上端口a在硅基底10′上具有第一投影，下端口b在硅基底10′上具有第二投影，第一投影覆盖第二投影。
也就是说，开口201的轮廓面Z与硅基底10′呈一定夹角，开口201呈现出上边大下边小的形状。或者理解为，下端口b的轮廓在硅基底10′上的投影位于上端口a的轮廓在硅基底10′上的投影内。
也可以理解为，上端口a的面积大于开口201的下端口b的面积，上端口a和下端口b的面积，可以理解为是上端口a和下端口b平行于硅基底10′的截面的面积。或者理解为，上端口a的面积是外延层20远离硅基底10′的上表面中孔的面积，下端口b的面积是外延层20与硅基底10′接触的下表面中孔的面积。
在一些实施例中，轮廓面Z与外延层20底面的夹角θ的取值范围为45°～88°，外延层20的底面为外延层20与硅基底10′接触的表面。
示例的，轮廓面Z与外延层20底面的夹角θ的取值为50°、55°、60°、65°、70°、75°、80°或者85°。
在一些实施例中，如图7B所示，上端口a的第一轮廓与下端口b的第二轮廓之间的间距S大于200nm。
或者理解为，上端口a在硅基底10′上的第一投影的轮廓与下端口b在硅基底10′上的第二投影的轮廓之间的间距大于200nm。
检测第一轮廓和第二轮廓之间的距离时，在第一轮廓上确定第一检测点和第二轮廓上确定第二检测点，第一轮廓在第一检测点处的外切线应与第二轮廓在第二检测点处的外切线平行，测量第一检测点和第二检测点的距离是否大于200nm。
在一些实施例中，上端口a的第一轮廓与下端口b的第二轮廓之间的间距S小于1μm。
示例的，第一轮廓与第二轮廓之间的间距S为250nm-300nm、300nm-350nm、350nm-100nm、400nm-450nm、450nm-5000nm、500nm-550nm、550nm-600nm、600nm-650nm、650nm-700nm、700nm-750nm、750nm-800nm、800nm-850nm、850nm-900nm、900nm-950nm或者950nm-1μm。需要说明的是，本申请实施例对开口201的形状不做限定，开口201的轮廓可以是任意封闭图形。在开口201的上端口a和下端口b的面积不一致的情况下，上端口a的轮廓可以是任意封闭图形，下端口b的轮廓可以是任意封闭图形。例如，上端口a的轮廓和下端口b的轮廓为同心的相似图形。
可以理解的是，本申请实施例中，开口201所在的区域对应Si基器件区，其他区域是宽禁带器件区。
这样一来，围成开口201的轮廓面Z为斜面，在后续制备过程中在轮廓面Z上层叠的膜层也为斜面。那么后续形成的布线叠层中的金属线层能够沉积在斜面上，而不是沉积在直角面上，可降低金属线层在轮廓面Z对应位置处(跨区域互连线)断裂的风险。其中，在一些实施例中，如图7B所示，刻蚀形成开口201时，可以对外延膜20′进行过刻。也就是说，会刻蚀掉硅基底10′的一部分表面，以确保开口201贯穿外延膜20′。
S23、去除光刻胶层。
S30、如图7C所示，在外延层20上形成电极，以形成宽禁带器件30。
示例的，宽禁带器件30为FET，在外延层上形成的电极为源极S、漏极D以及栅极G。
其中，源极S和漏极D与外延层20形成欧姆接触，栅极G与外延层20形成肖特基接触。例如，源极S和漏极D与外延层20中的势垒层形成欧姆接触，栅极G与外延层20中的势垒层形成肖特基接触。源极S、漏极D以及栅极G，与外延层20构成宽禁带器件30。
本申请实施例中半导体结构可以包括一个或多个宽禁带器件30，宽禁带器件30可以理解为是禁带宽度大于1.5eV的半导体器件，例如，可以通过能谱仪(energy dispersive spectroscopy，EDS)来判定半导体器件的禁带宽度。宽禁带器件30也可以理解为是第三代半导体材料形成的半导体器件。第三代半导体材料例如可以包括GaN、GaO、SiC、氧化锌(ZnO)。
示例的，宽禁带器件30包括异质结半导体器件。宽禁带器件30为高电子迁移率晶体管(high electron mobility transistor，HEMT)。
宽禁带器件30是包括III-V半导体材料、III-VI半导体材料或者V-VI半导体材料的半导体器件。例如，根据沟道层材料的不同，宽禁带器件30为GaAs基半导体器件或者GaN基半导体器件。在一些实施例中，本申请实施例提供的半导体器件为电源转换芯片。
半导体结构包括电源转换器件单元，电源转换器件单元包括宽禁带器件30。当然，电源转换器件单元还可以包括电阻、电容、电感等无源器件或者二极管等有源器件。这些无源器件和有源器件通过后续形成的金属叠层与宽禁带器件30耦接，构成电源转换的电路结构。
基于此，电源转换器件单元可以理解为是电源转换电路所包括的器件构成的器件单元，这些器件之间还没有通过后段制程耦接。或者理解为，电源转换器件单元为用于实现电源转换功能的电路中所包括的器件，不包含用于将器件耦接成通路的走线。
在另一些实施例中，本申请实施例提供的半导体器件为PA芯片。
半导体结构包括功率放大器器件单元，功率放大器器件单元包括宽禁带器件30。当然，功率 放大器器件单元还可以包括电阻、电容、电感等无源器件或者二极管等有源器件。这些无源器件和有源器件通过后续形成的金属叠层与宽禁带器件30耦接，构成功率放大器的电路结构。
基于此，功率放大器器件单元可以理解为是功率放大器所包括的器件构成的器件单元，这些器件之间还没有通过后段制程耦接。或者理解为，功率放大器器件单元为用于实现功率放大功能的电路中所包括的器件，不包含用于将器件耦接成通路的走线。
在又一些实施例中，本申请实施例提供的半导体器件为LNA芯片。
半导体结构包括低噪声放大器器件单元，低噪声放大器器件单元包括宽禁带器件30。当然，低噪声放大器器件单元还可以包括电阻、电容、电感等无源器件或者二极管等有源器件。这些无源器件和有源器件通过后续形成的金属叠层与宽禁带器件30耦接，构成低噪声放大器的电路结构。
基于此，低噪声放大器器件单元可以理解为是低噪声放大器所包括的器件构成的器件单元，这些器件之间还没有通过后段制程耦接。或者理解为，低噪声放大器器件单元为用于实现低噪声放大功能的电路中所包括的器件，不包含用于将器件耦接成通路的走线。
下面，以宽禁带器件30为HEMT器件为例，对源极S、漏极D以及栅极G的制备过程进行示意说明。
在一些实施例中，步骤S30包括：
S31、制作覆盖外延层20的光刻胶层，光刻胶层在待形成源极S的区域具有源极开窗，在待形成漏极D的区域具有漏极开窗。
其中，光刻胶层的光刻胶可以为正性光刻胶，也可以为负性光刻胶。
S32、对保护层进行刻蚀，露出源极开窗和漏极开窗下方的势垒层。
例如可以采用干法刻蚀，在保护层上形成源极开口和漏极开口，源极开口和漏极开口露出势垒层。
S33、通过源极开窗和漏极开窗注入杂质，激活后形成掺杂区。
其中，可以采用离子注入的工艺通过源极开窗和漏极开窗注入施主杂质。施主杂质例如可以是硅离子，施主杂质可以是单一元素也可以是多种元素的混合物。施主杂质的注入，可以降低待形成的源极S和漏极D与势垒层的欧姆接触电阻的电阻率，还可以降低势垒层的电阻率。
S34、去除光刻胶层，通过退火工艺激活施主杂质的载流子，形成N型掺杂区。
当然，也可以采用后续其他膜层制作中的退火工艺对注入的施主杂质的载流子进行激活，在这种情况下，可以先不去除光刻胶层，直接执行步骤S36。
S35、再制作覆盖外延层20的光刻胶层，光刻胶层在待形成源极S的区域具有源极开窗，在待形成漏极D的区域具有漏极开窗。
S36、形成覆盖光刻胶层的金属膜，金属膜填充源极开窗和漏极开窗。
例如，可以采用金属沉积工艺、溅射工艺、蒸镀工艺或者电镀工艺制作金属膜。
S37、去除光刻胶层及位于光刻胶层上方的金属膜，保留位于源极开窗中的源极S，和位于漏极开窗中的漏极D。
其中，源极S和漏极D与势垒层形成欧姆接触。
源极S和漏极D的材料可以是单质，也可以是合金或多层叠层金属。在一个实施例中，源极S、漏极D的材料，例如可以为依次层叠的钛(Ti)层、Al层、镍(Ni)层和金(Au)层，即Ti/Al/Ni/Au。在一个实施例中，源极S、漏极D的材料可以为依次层叠的Ti层、Al层、铂(Pt)层和Au层，即Ti/Al/Pt/Au。在一个实施例中，源极S、漏极D的材料可以为依次层叠的Ti层、钽(Ta)层和Ti层，即Ti/Ta/Ti。在一个实施例中，源极S、漏极D的材料可以为Au或者钯(Pd)。
S38、形成栅介质层，栅介质层与待形成的栅极对应。
例如，可以先沉积形成栅介质膜，然后对栅介质膜进行刻蚀形成栅介质层。
S39、在栅介质层上形成栅极S。
例如，先沉积金属膜，然后对金属膜进行刻蚀，形成栅极S，栅极S位于栅介质层上方。
栅极S的材料，例如可以是Au或者Pd。
S40、如图7D所示，在硅基底10′被开口201露出的区域内形成硅基器件40，并形成硅衬底10。
本申请实施例中硅基器件40包括一个或多个硅基器件，硅基器件可以理解为是在硅基底10′中掺杂制备得到的器件。
在一些实施例中，硅基器件40为双极性晶体管或者具有某种功能的电路所包括的器件。
在另一些实施例中，半导体结构包括静电放电保护单元，硅基器件40为静电放电保护器件单元中的器件。
其中，静电放电保护单元可以包括单个硅基器件40，静电放电保护单元也可以为多个硅基器件40构成的电路。在一个实施例中，静电放电保护器件单元包括二极管、双极性晶体管、可控硅整流器或者金属-氧化物半导体场效应晶体管中的至少一种。
在一些实施例中，如图8A所示，硅基器件40为二极管。
在一个实施例中，二极管为PN结二极管。二极管包括深N阱(Deep N Well，DNW)41、P阱(P Well，PW)42、P型有源区43、N型有源区44、隔离部45、第一电极46以及第二电极47。
当然，二极管也可以为肖特基二极管或者P-i-N二极管，本申请实施例对此不做限定。
下面，以二极管为PN二极管为例，对步骤S40进行示意，步骤S40包括：
S41、先通过离子注入，向开口201下方的硅基底10′中注入磷离子，并退火形成深N阱41。
S42、再通过离子注入，向开口201下方的硅基底10′中注入硼离子，并退火形成P阱42。
S43、形成光刻胶层，光刻胶层具有P型有源区窗口，向P型有源区窗口注入硼离子，形成位于硅基底10′中的P型有源区43(P型重掺杂区)。
S44、形成光刻胶层，光刻胶层具有N型有源区窗口，向N型有源区窗口注入砷离子，形成位于硅基底10′中的N型有源区44(N型重掺杂区)。
P型有源区43对应待形成的二极管的正极，N型有源区44对应待形成的二极管的负极。
S45、对P型有源区43和N型有源区44以外的部分进行局部氧化(local oxidation of silicon)，形成隔离部45。
开口201露出的区域中，除P型有源区43和N型有源区44以外的区域，通过局部氧化形成隔离部45，P型有源区43和N型有源区44之间也具有隔离部45。
至此，硅衬底10也制备完成。硅衬底10的硅基底10′的主要区别在于，硅基底10′对应开口201的部分结构，被掺杂和氧化后作为硅基半导体器件单元的结构，去除硅基底10′被掺杂和氧化的部分，得到的剩余部分作为硅衬底10。
S46、通过退火工艺激活硼离子和砷离子的载流子，形成重掺杂区域。
S47、在P型有源区43上方形成第一电极，在N型有源区44上方形成第二电极。
第一电极与P型有源区43形成欧姆接触，第二电极与N型有源区44形成欧姆接触。第一电极例如可以理解为是二极管的正极，第二电极例如可以理解为是二极管的负极。
第一电极和第二电极的材料，例如可以是金属硅化物。示例的，第一电极和第二电极的材料包括Ti、Pt、Ni等金属。
在一些实施例中，半导体器件的制备过程中，仅执行一次用于实现欧姆接触的金属退火处理，不执行两次退火处理。
也就是说，正在外延层20上形成源极S和漏极D，在硅衬底10上形成第一电极和第二电极之后，可以在合理的步骤顺序中对形成有源极S、漏极D、第一电极和第二电极的半成品器件进行退火处理。
例如，执行步骤S35之前，不执行步骤S34。执行步骤S47之前，不执行步骤S46。步骤S34和步骤S46可以为同一步骤。若步骤S40在步骤S30之后执行，那么，可以在执行完步骤S39和步骤S47后，执行一侧退火工艺(步骤S34和步骤S46)。或者，步骤S40在步骤S30之前执行，那么，可以在执行完步骤S47和步骤S37后，执行一侧退火工艺(步骤S34和步骤S46)。当然，退火工艺(步骤S34和步骤S46)也可以处于其他步骤之后，只要制备宽禁带器件30和制备硅基器件40这两个结构的过程中，只执行一次退火工艺即可。
通过将两次欧姆接触退火工艺合并为一次欧姆接触退火工艺，减小退火次数，可以简化工艺步骤，减小半导体结构的热预算。当然，也可以根据半导体结构的热预算，合理调整各步骤的制备顺序。
在另一些实施例中，如图8B所示，硅基器件40为双极性晶体管(bipolar transistor)。
示例的，双极性晶体管包括深N阱61、P阱62、P型重掺杂区63、N型重掺杂区64、N阱65、隔离部66、集电极67、基极68以及发射极69。
P阱62和N阱65位于深N阱61内，P阱62相对的两侧设置有N阱65。P阱62靠近硅衬底10的表面处形成有P型重掺杂区63和N型重掺杂区64，N型重掺杂区64相对的两侧设置有P型重掺杂区63。N阱65靠近硅衬底10的表面处形成有N型重掺杂区64。P型重掺杂区63和N型重掺杂区64的两侧均设置有隔离部66。位于N阱65的N型重掺杂区64表面设置有集电极67，集电极67与该N型重掺杂区64形成欧姆接触。P型重掺杂区63表面设置有基极68，基极68与该P型重掺杂区63形成欧姆接触。位于P阱62的N型重掺杂区64表面设置有发射极69，发射极与该N型重掺杂区64形成欧姆接触。
集电极67例如可以作为硅基器件40的第一电极(正极)，基极68和发射极69例如可以作为硅基器件40的第二电极(负极)，基极68和发射极69与地线耦接。硅基器件40为基极68接地的NPN型双极性晶体管。
形成阱、重掺杂区、隔离部的方法，可以与上述形成二极管的方法相同，此处不再赘述。
当然，硅基器件40为PNP型双极性晶体管。
在又一些实施例中，如图8C所示，硅基器件40为可控硅整流器(silicon controlled rectifier，SCR)。
示例的，可控硅整流器包括深N阱71、P阱72、P型重掺杂区73、N型重掺杂区74、N阱75、隔离部76、正极77、负极78以及电源极79。
P阱72和N阱75位于深N阱71内，P阱72相对的两侧设置有N阱75。P阱72靠近硅衬底10的表面处形成有P型重掺杂区73和N型重掺杂区74。第一个N阱75靠近硅衬底10的表面处形成有P型重掺杂区73和N型重掺杂区74。第二个N阱75靠近硅衬底10的表面处形成有N型重掺杂区74。重掺杂区以P型重掺杂区73、N型重掺杂区74、P型重掺杂区73、N型重掺杂区74、N型重掺杂区74的顺序依次排布。P型重掺杂区73和N型重掺杂区74的两侧均设置有隔离部76。
位于P阱72的P型重掺杂区73和N型重掺杂区74表面分别设置有第一电极77(正极)，位于第一个N阱75的P型重掺杂区73和N型重掺杂区74表面分别设置有第二电极78(负极)，位于第二N阱75的N型重掺杂区74表面设置有电源极79。
SCR既有较高的触发电压，又有高电流导通能力。SCR触发后，在N阱和P阱中电子和空穴均参与导电，他们的净电量互相抵消，会出现电流升高但电压下降的回滞现象，该原理被称作电导调制。因此，SCR在导通后，钳位电压更低，电流导通能力更强，可以用更小的面积实现目标保护规格。另外，SCR的结构可以看作两个小面积正向PN结与一个大面积反向PN结串联，正向PN结的结电容与反向PN结的结电容随电压变化呈相反的变化趋势，因此二者在一定程度上抵消，使总的结电容随电压的变化更小。因此，用SCR作为静电放电保护单元ESD，能够用更小的面积提供更强的静电放电保护效果、且寄生参数较小(如寄生电容与漏电流)，而且一个SCR器件就能够提供双向的防护。
在又一些实施例中，如图8D所示，硅基器件40为金属-氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)。
MOSFET包括位于硅衬底10中的源极区和漏极区，源极区上设置有MOSFET的源极S′,源极S′与源极区欧姆接触。漏极区上设置有MOSFET的漏极D′，漏极D′与漏极区欧姆接触。源极S′和漏极D′之间设置有MOSFET的栅极G′，栅极G′与硅衬底10之间设置有栅绝缘层。
图8A-图8D所示的硅基器件40仅为一种示意，根据具体的静电放电防护需求，可以在开口201对应区域制备不同的硅基器件40。
需要强调的是，本申请实施例提供的半导体结构的制备方法，并不限定于按照步骤S10-S40的顺序来制备。也可以是执行完步骤S10后，先执行步骤S30，再依次执行步骤S20和步骤S40。还可以是，执行完步骤S10和S20后，先执行步骤S40，再执行步骤S30。上述制备过程仅为一种示意，不做任何限定。
在一些实施例中，如图8A-图8D所示，硅衬底10朝向外延层20的表面为平面。硅衬底10朝向外延层20的表面，可以理解为是，硅衬底10与外延层20接触的部分所在的平面。
也就是说，硅基底10′来片时，硅基底10′的表面为平面，对硅基底10′位于开口201下方的部分进行掺杂处理后，该部分变为了硅基器件40的结构，相当于硅基器件40设置于硅衬底10内。
通过上述对硅基器件40的制备方法及制备得到的硅基器件40的描述可知，硅基器件40位于开口201内，且硅基器件40的部分结构位于硅衬底10中。硅基器件40的部分结构位于硅衬底10中，可以理解为，硅基器件40的部分结构位于硅衬底10与外延层20接触的表面所在水平面以下。
S50、如图9A所示，形成布线叠层50。
布线叠层50覆盖宽禁带器件30和硅基器件40，宽禁带器件模30和硅基器件40通过布线叠层50耦接。
下面，以宽禁带器件30为MOSFET，硅基器件40为二极管为例，对宽禁带器件30和硅基器件40的耦接进行示意说明。
示例的，步骤S50包括：
S51、如图9B所示，在外延层20上形成第一层间介质(interlayer dielectric)膜51′。
例如，可以采用沉积工艺，形成第一层间介质膜51′。第一层间介质膜51′的材料，例如可以包括氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiON)等低介电常数的无机化合物或有机化合物。
S52、如图9C所示，通过刻蚀工艺，在第一层间介质膜51′上形成多个第一通孔511，以形成第一层间介质层51。
例如，采用RIE工艺、ICP刻蚀工艺、IBE工艺等刻蚀工艺形成第一通孔511。
其中，多个第一通孔511露出宽禁带器件30和硅基器件40中的电极。例如，多个第一通孔511分别露出MOSFET中的源极S、漏极D、栅极G以及二极管中的正极46、负极47。
S53、如图9D所示，形成金属膜，并对金属膜进行图案化，形成第一金属层52。
其中，第一金属层52包括多个第一金属图案521，多个第一金属图案521填充第一通孔511，与MOSFET中的源极S、栅极G以及二极管中的负极47分别耦接，且多个第一金属图案521之间具有间隙，第一金属层52还包括第一金属线522，第一金属线522填充第一通孔511，将漏极D和正极46耦接的第一金属线522。
也就是说，第一金属层52中，与源极S、漏极D、栅极G、正极46、负极47中的一个耦接的结构为第一金属图案521，与源极S、漏极D、栅极G、正极46、负极47中的两个耦接的结构为第一金属线522。
第一金属层52的材料，例如可以包括铜、铝、金等。
S54、如图9E所示，形成第二层间介质层53。
第二层间介质层53具有多个第二通孔531，第二通孔531露出源极S、栅极G以及负极47中待耦接的电极对应的第一金属图案521。例如，多个第二通孔531露出与栅极G耦接的第一金属图案521以及与负极47耦接的第一金属图案521。
形成第二层间介质层53的方法，例如可以与形成第一层间介质层51的方法相同。
S55、如图9F所示，形成第二金属层54，第二金属层54填充第二通孔531。
第二金属层54与栅极G上方的第一金属图案521耦接，第二金属层54还与负极47上方的第一金属图案521耦接，从而实现通过第二金属层54将栅极G和负极47耦接。
形成第二金属层54的方法，例如可以与形成第一金属层52的方法相同。
步骤S50还可以包括重复形成层间介质层和金属层的步骤，直至后段制程中所有所需的金属层制备完成。也就是说，上述步骤S50可以理解为是本领域常称的后段制程。
图9F所示的半导体结构中，通过硅基器件40对宽禁带器件30的栅极G与漏极D之间实现钳位保护，从而达到静电放电防护的目的。
通过上述制备工艺形成的半导体结构，从俯视图上来看，如图10所示，在硅衬底10的区域 范围内，除了设置硅基器件的区域为硅基器件区，其余区域全是外延层覆盖区。
当然，在半导体器件为电源转换芯片的情况下，半导体器件的布线叠层50还包括电源线、地线等结构。
关于半导体结构中宽禁带器件30与硅基器件40的尺寸关系，在一些实施例中，硅基器件40的面积大于宽禁带器件30的面积。
其中，硅基器件40和宽禁带器件30的面积，可以理解为是硅基器件40中电极的外轮廓的面积和宽禁带器件30中电极的外轮廓的面积。
在一些实施例中，硅基器件40的宽度为数十μm～上万μm。例如，硅基器件40的宽度为1000μm-2000μm、2000μm-3000μm、3000μm-4000μm、4000μm-5000μm、5000μm-6000μm、6000μm-7000μm、7000μm-8000μm、8000μm-9000μm、9000μm-10000μm、10000μm-15000μm、15000μm-20000μm、20000μm-30000μm、30000μm-40000μm。
在一些实施例中，硅基器件40的宽度为100μm-1000μm。例如，硅基器件40的宽度为200μm-300μm、300μm-400μm、400μm-500μm、500μm-600μm、600μm-700μm、700μm-800μm、800μm-900μm、900μm-1000μm。
其中，硅基器件40的宽度，可以理解为硅基器件40中电极沿垂直于硅基器件40电流流动方向上的尺寸。
例如，如图11A所示，硅基器件40中电流I的流动方向为从第一电极到第二电极，那么，硅基器件40的宽度L为第一电极或者第二电极沿垂直于从第一电极到第二电极的方向上的尺寸。
或者，如图11B所示，硅基器件40中电流I的流动方向为从源极S′到漏极D′，那么，硅基器件40的宽度L为栅极G′沿垂直于从源极S′到漏极D′的方向上的尺寸。
关于半导体结构中宽禁带器件30与硅基器件40的位置关系，如图12所示，硅基器件40通常设置在包括宽禁带器件30的核心器件区的外围，硅基器件40靠近半导体结构的I/O(输入/输出)端口设置。硅基器件40通常与I/O端口耦接。例如，硅基器件40耦接于I/O端口和半导体结构中电源线/地线之间。
关于半导体结构中宽禁带器件30与硅基器件40的性能关系，硅基器件40的触发电压小于宽禁带器件30的失效电压。
本申请实施例提供的半导体结构，将宽禁带器件30与硅基器件40集成在同一硅衬底10中，充分利用硅基器件40较强的静电放电防护能力，补足宽禁带器件30抗静电能力不足的短板，以提高宽禁带器件30的抗静电能力。且，无需对宽禁带器件30与硅基器件40进行封装，半导体结构的面积较小。
另外，外延层20设置在硅衬底10的表面上，在制备过程中，先在外延工艺厂进行外延工艺(步骤S10)，然后再在器件工艺厂形成硅基器件40和宽禁带器件30(步骤S20～步骤S40)，硅基器件40所在的开口201的形成，是在外延片制备之后的工艺流程中完成，实现外延工艺与器件工艺在流程上的解耦，增加了整套流程的灵活度，降低成本。
再者，除了外延层20中的开口区域用于制备硅基器件40，其余区域全都可以用于制备宽禁带器件30。外延层20使用的灵活性提高，且硅基器件40的面积占较小，可减小寄生效应(寄生电容、漏电流)，降低硅基器件40对宽禁带器件30性能的影响。
而且，本申请中的宽禁带器件30可以适用于任意宽禁带半导体材料，不限定为仅在SiC半导体材料上外延生长。且硅基器件40可以为多种类型的器件，适用范围广。
此外，利用后段制程形成的布线叠层50将宽禁带器件30与硅基器件40耦接，能够从后段制程开始至贴片封装，提供全流程的静电放电防护，避免了片外防护方案(将硅基器件与氮化镓基器件封装)带来的防护空白期。
在一个实施例中，宽禁带器件30为同质结半导体器件。宽禁带器件30为金属-氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)。
本申请实施例提供一种半导体结构的制备方法，包括：
S10′、如图13A所示，在硅基底10′上形成外延膜20′。
在一些实施例中，外延膜20′为同质结堆叠膜。
同质结，是由两种材料相同的膜层相接触形成的结。当然，材料相同的膜层是指主体材料相同。
示例的，如图13A所示，在硅基底10′上形成缓冲膜和表面功能膜。
其中，缓冲膜可以为一层膜层，缓冲膜也可以为多层膜层，本申请实施例仅为一种示意。
示例的，缓冲膜的材料例如可以为多晶SiC或者多晶氧化镓(GaO)。表面功能膜的材料例如可以为掺杂的SiC或者GaO，掺杂材料例如可以为氮、磷、砷等。那么，宽禁带器件30可以为SiC基半导体器件或者GaO基半导体器件。
例如，可以通过MOCVD生长法或MBE生长法形成缓冲膜和表面功能膜。
S20′、如图13B所示，采用刻蚀工艺，在外延膜20′上形成开口201，以形成外延层20。
形成外延层20的方法，可以与示例一中步骤S20的方法相同，可参考上述相关描述。
基于此，形成的外延层20包括缓冲层和表面功能层。
S30′、如图13C所示，在外延层20上形成电极，以形成宽禁带器件30。
示例的，宽禁带器件30为FET，在外延层上形成的电极为源极S、漏极D以及栅极G。
示例的，步骤S30′包括：
S31′、对表面功能层进行掺杂，形成P型掺杂区。
P型掺杂区与待形成的栅极G的区域对应，P型掺杂区作为沟道。
形成N型掺杂区的方法，可以与示例一中形成N型掺杂区的方法类似，仅是掺杂的施主杂质的类型不同，可参考示例一的相关描述。
S32′、对表面功能层进行掺杂，形成N型掺杂区。
N型掺杂区与待形成的源极S和漏极D的区域对应，P型掺杂区位于N型掺杂区的两侧。
形成N型掺杂区的方法，可以与示例一中相同，可参考示例一的相关描述。
S33′、形成源极S和漏极D。
源极S与N型掺杂区形成欧姆接触，漏极D与另一个N型掺杂区形成欧姆接触。
S34′、形成栅极G。
栅极D位于P型掺杂区的上方，栅极D与P型掺杂区之间设置有栅绝缘层。
其中，图13C仅是以宽禁带器件30为N型MOSFET为例进行示意，宽禁带器件30也可以为P型MOSFET。
S40′、如图13D所示，形成硅基器件40。
其中，步骤S40′可以与示例一中的S40相同，此处不再赘述。
S50′，如图13E所示，形成布线叠层50。
其中，步骤S50′可以与示例一中的S50相同，此处不再赘述。
本申请实施例提供的半导体结构，可以适用于多种类型的宽禁带器件30，适用范围广。
在一个实施例中，宽禁带器件30不是FET，而是BJT。
S10″、如图14A所示，在硅基底10′上形成外延膜20′。
例如可以通过MOCVD生长法或MBE生长法等形成外延膜20′。示例的，外延膜20′为单层膜层。
S20″、如图14B所示，在外延膜20′上形成开口201，以形成外延层20。
步骤S20″，可以与示例一中步骤S20相同，可参考上述相关描述。
S30″、如图14C所示，在外延层20上形成电极，以形成宽禁带器件30。
示例的，宽禁带器件30为BJT，在外延层20上形成的电极为基极(base electrode，B)、集电极(collector electrode，C)以及发射极(emitter electrode，E)。
示例的，步骤S30″包括：
S31″、同步形成用于隔离发射区、集电区、基区的沟槽隔离区(shallow trench isolation，STI)。
S32″、在待形成发射区和基区的区域内进行离子注入形成P阱P-Well；在待形成集电区的区域内进行离子注入形成N阱N-Well，P阱和N阱的上表面高于STI的底部。
S33″、在待形成发射区的P阱上以及在待形成集电区的N阱上分别进行N型离子重掺杂 形成发射区和集电区，在待形成基区的P阱上进行P型离子重掺杂形成基区。
S34″、在发射区和集电区上分别形成发射极E和集电极C，在基区上形成基极B。
S40″、如图14D所示，形成硅基器件40。
其中，步骤S40″可以与示例一中的S40相同，此处不再赘述。
S50″，如图14E所示，形成布线叠层50。
其中，步骤S50″可以与示例一中的S50相同，此处不再赘述。
当然，BJT可以为NPN型晶体管，也可以为PNP型晶体管，本示例中仅为一种示意。另外，上述示意了一种BJT，本申请实施例中的宽禁带器件30也可以为异质结双极晶体管(heterojunction bipolar transistor，HBT)。
本申请实施例提供的半导体结构，可以适用于多种类型的宽禁带器件30，适用范围广。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种半导体结构，其特征在于，包括：
    硅衬底；
    外延层，设置于所述硅衬底的表面；所述外延层具有贯穿所述外延层的开口；围成所述开口的轮廓面上的原子呈非晶态或者多晶态排布；
    电极，设置于所述外延层上、与所述外延层构成宽禁带器件；
    硅基器件，位于所述开口内、且伸入所述硅衬底中。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述开口具有上端口和下端口，所述下端口相对所述上端口靠近所述硅衬底；
    所述上端口在所述硅衬底上具有第一投影，所述下端口在所述硅衬底上具有第二投影，所述第一投影覆盖所述第二投影。
  3. 根据权利要求2所述的半导体结构，其特征在于，所述上端口的第一轮廓与所述下端口的第二轮廓之间的间距大于200nm。
  4. 根据权利要求1-3任一项所述的半导体结构，其特征在于，所述轮廓面与所述外延层底面的夹角的取值范围为45°～88°。
  5. 根据权利要求1-4任一项所述的半导体结构，其特征在于，所述硅衬底朝向所述外延层的表面为平面。
  6. 根据权利要求1-5任一项所述的半导体结构，其特征在于，所述硅基器件的面积大于所述宽禁带器件的面积。
  7. 根据权利要求1-6任一项所述的半导体结构，其特征在于，所述半导体结构包括静电放电保护器件单元，所述静电放电保护器件单元包括所述硅基器件。
  8. 根据权利要求7所述的半导体结构，其特征在于，所述硅基器件为双极性晶体管、二极管、可控硅整流器或者金属-氧化物半导体场效应晶体管。
  9. 根据权利要求1-8任一项所述的半导体结构，其特征在于，所述宽禁带器件为场效应晶体管或者双极型晶体管。
  10. 根据权利要求1-9任一项所述的半导体结构，其特征在于，所述半导体结构还包括布线叠层，所述布线叠层覆盖所述宽禁带器件单元和所述硅基器件单元；所述宽禁带器件单元和所述硅基器件单元通过所述布线叠层耦接。
  11. 根据权利要求1-10任一项所述的半导体结构，其特征在于，所述半导体结构为功率放大器芯片、低噪声放大器芯片或者电源转换芯片。
  12. 一种半导体结构的制备方法，其特征在于，包括：
    在硅基底的表面上形成外延膜；
    采用刻蚀工艺，在所述外延膜上形成开口，形成外延层；其中，所述开口露出所述硅基底；
    在所述外延层上形成电极；所述电极与所述外延层构成宽禁带器件；
    在所述硅基底被所述开口露出的区域内形成硅基器件，并形成硅衬底；所述硅基器件位于所述开口内、且伸入所述硅衬底中。
  13. 根据权利要求12所述的半导体结构的制备方法，其特征在于，所述开口具有上端口和下端口，所述下端口相对所述上端口靠近所述硅衬底；
    所述上端口在所述硅衬底上具有第一投影，所述下端口在所述硅衬底上具有第二投影，所述第一投影覆盖所述第二投影。
  14. 根据权利要求13所述的半导体结构的制备方法，其特征在于，所述上端口的第一轮廓与所述下端口的第二轮廓之间的间距大于200nm。
  15. 根据权利要求12-14任一项所述的半导体结构的制备方法，其特征在于，围成所述开口的轮廓面与所述外延层底面的夹角的取值范围为45°～88°。
  16. 根据权利要求12-15任一项所述的半导体结构的制备方法，其特征在于，围成所述开口的轮廓面上的原子呈非晶态或者多晶态排布。
  17. 根据权利要求12-16任一项所述的半导体结构的制备方法，其特征在于，所述硅基器件 为双极性晶体管、二极管、可控硅整流器或者金属-氧化物半导体场效应晶体管。
  18. 根据权利要求12-17任一项所述的半导体结构的制备方法，其特征在于，
    在所述外延层上形成电极，包括：在所述外延层上形成源极和漏极；
    形成硅基器件，包括在所述硅衬底上形成第一电极和第二电极；
    形成所述源极和所述漏极、以及所述第一电极和所述第二电极之后，进行欧姆接触退火处理。
  19. 根据权利要求12-18任一项所述的半导体结构的制备方法，其特征在于，所述制备方法还包括：
    形成布线叠层；所述布线叠层覆盖所述宽禁带器件和所述硅基器件；所述宽禁带器件和所述硅基器件通过所述布线叠层耦接。
  20. 一种射频前端模组，其特征在于，包括权利要求1-11任一项所述的半导体结构和射频开关，所述射频开关与所述半导体结构耦接。
  21. 一种电源转换模组，其特征在于，包括权利要求1-11任一项所述的半导体结构和变压器，所述半导体结构与所述变压器耦接。
  22. 一种电子设备，其特征在于，包括权利要求20所述的射频前端模组和/或权利要求21所述的电源转换模组。
PCT/CN2023/112597 2022-08-27 2023-08-11 半导体结构、射频前端模组、电源转换模组、电子设备 WO2024046093A1 (zh)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194830A (zh) * 2010-01-28 2011-09-21 英特赛尔美国股份有限公司 氮化镓与硅器件和电路的单片集成、结构和方法
CN102403302A (zh) * 2010-09-14 2012-04-04 台湾积体电路制造股份有限公司 在基板上形成SiC结晶以实现GAN和Si电子器件集成的机理
CN105529305A (zh) * 2015-12-17 2016-04-27 中航（重庆）微电子有限公司 三层混合晶向绝缘体上半导体结构及其制作方法
US20190006171A1 (en) * 2015-08-28 2019-01-03 Intel Corporation Methods and devices integrating iii-n transistor circuitry with si transistor circuitry
US20200295045A1 (en) * 2019-03-15 2020-09-17 International Business Machines Corporation ULTRA LOW PARASITIC INDUCTANCE INTEGRATED CASCODE GaN DEVICES
US20210111192A1 (en) * 2019-10-14 2021-04-15 International Business Machines Corporation Integrated power amplifier
CN112786538A (zh) * 2021-01-15 2021-05-11 深圳市汇芯通信技术有限公司 一种基于GaN HEMT的开关集成芯片与制作方法
CN113782529A (zh) * 2021-08-27 2021-12-10 深圳市汇芯通信技术有限公司 一种集成芯片及其制作方法和集成电路

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194830A (zh) * 2010-01-28 2011-09-21 英特赛尔美国股份有限公司 氮化镓与硅器件和电路的单片集成、结构和方法
CN102403302A (zh) * 2010-09-14 2012-04-04 台湾积体电路制造股份有限公司 在基板上形成SiC结晶以实现GAN和Si电子器件集成的机理
US20190006171A1 (en) * 2015-08-28 2019-01-03 Intel Corporation Methods and devices integrating iii-n transistor circuitry with si transistor circuitry
CN105529305A (zh) * 2015-12-17 2016-04-27 中航（重庆）微电子有限公司 三层混合晶向绝缘体上半导体结构及其制作方法
US20200295045A1 (en) * 2019-03-15 2020-09-17 International Business Machines Corporation ULTRA LOW PARASITIC INDUCTANCE INTEGRATED CASCODE GaN DEVICES
US20210111192A1 (en) * 2019-10-14 2021-04-15 International Business Machines Corporation Integrated power amplifier
CN112786538A (zh) * 2021-01-15 2021-05-11 深圳市汇芯通信技术有限公司 一种基于GaN HEMT的开关集成芯片与制作方法
CN113782529A (zh) * 2021-08-27 2021-12-10 深圳市汇芯通信技术有限公司 一种集成芯片及其制作方法和集成电路

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