WO2018236406A1

WO2018236406A1 - Group iii-nitride heterostructure diodes

Info

Publication number: WO2018236406A1
Application number: PCT/US2017/039160
Authority: WO
Inventors: Han Wui Then; Sansaptak DASGUPTA; Marko Radosavljevic
Original assignee: Intel Corporation
Priority date: 2017-06-24
Filing date: 2017-06-24
Publication date: 2018-12-27

Abstract

Diodes employing a Group III-N heterostructure that may provide lower on-resistance for a given diode area relative to conventional III-N diode structures. A III-N heterostructure may include two or more first III-N material layers interleaved with two or more second III-N material layers, thereby forming a heterostructure with three or more heterojunctions. Through control of the III-N material layer composition, a two-dimensional charge sheet (e.g., 2D electron gas) may be induced within each of the first III-N material layers.

Description

Group Ill-Nitride Heterostructure Diodes

BACKGROUND

Diodes are a common circuit element used in integrated circuits (ICs). Schottky diodes employing a rectifying metal-semiconductor junction are particularly useful for protecting circuitry from over-voltages, such as those associated with electrostatic discharge (ESD) events. Absent a protection circuit, discharge through a device such as a transistor, can cause catastrophic damage to an IC. Diodic protection circuits may therefore be configured as part of a functional IC to shunt surges in potential away from circuitry that could otherwise be damaged. Group Ill-Nitride ("III-N" or IUPAC "13-N") semiconductor materials offer the benefit of a relatively wide bandgap (~3.4eV), enabling higher breakdown voltages than Si-based devices. III-N materials also offer high carrier mobility. However, III-N diodes with sufficiently low on-resistance tend to be an area-intensive circuit element. III-N diode structures offering lower on-resistance for a given area are therefore advantageous at least for enabling dimensional scaling of the device platforms that employ them. BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified "ideal" forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, corner-rounding, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:

FIG. 1 is a schematic of an ESD protection circuit including at least one III-N heterostructure diode, in accordance with some embodiments; FIG. 2A is a cross-sectional view of III-N heterostructure diodes, in accordance with some embodiments;

FIG. 2B is a plan view of III-N heterostructure diodes, in accordance with some embodiments; FIG. 2C is a plan view of III-N heterostructure diodes, in accordance with some embodiments;

FIG. 3 is a cross-sectional view of III-N heterostructure diodes, in accordance with some embodiments;

FIG. 4 is a flow diagram illustrating methods of forming a III-N heterostructure diode, in accordance with some embodiments;

FIG. 5A, 5B, 5C, 5D, 5E, and 5F are cross-sectional views of III-N heterostructure diodes evolving as selected operations in the methods illustrated in FIG. 4 are performed, in accordance with some embodiments;

FIG. 6 illustrates a mobile computing platform and a data server machine employing an IC having a III-N heterostructure diode, in accordance with embodiments; and

FIG. 7 is a functional block diagram of an electronic computing device, in accordance with some embodiments.

DETAILED DESCRIPTION

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of or "one or more of can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

Diodes employing a III-N heterostructure are described herein. Diode

heterostructures in accordance with one or more of the embodiments described herein may provide lower on-resistance for a given diode area relative to conventional diode structures. As described further below, a III-N heterostructure that includes a plurality of III-N material layers or lamella may be employed within a diode. The III-N material layers may include two or more first III-N material layers interleaved with two or more second III-N material layers, thereby forming a heterostructure with three or more heterojunctions. Through control of the III-N material layer composition, a two-dimensional charge carrier sheet (e.g., 2DEG) may be induced within each of the first III-N material layers. The multiple charge carrier sheets present within the III-N heterostructure may be contacted at first locations by an impurity-doped semiconductor (e.g., having n-type conductivity), and are then operable as a first terminal of a diode. The multiple charge carrier sheets present within the III-N heterostructure may be further contacted at second locations by a metal suitable for forming a rectifying metal-semiconductor (i.e., Schottky) barrier to the first III-N material layers. Hence, on-resistance associated with a diodic III-N heterostructure of a given footprint may be scaled down by increasing the number of charge carrier sheets present with a stack of layers in a III-N heterostructure. Any number of charge carrier sheets may be formed, for example limited only by the practicality of coupling plural material layers to the diode terminals. FIG. 1 is schematic of an electrical circuit 100 including at least one III-N heterostructure diode, in accordance with some embodiments. Circuit 100 may, for example, be implemented by one or more IC chip, discrete components and combinations thereof. Circuit 100 may be implemented in any electronic device, such as, but not limited to, smartphones, ultrabook computers, embedded devices (e.g., internet of things, automotive applications, etc.), wearables, and the like. In circuit 100, one or more transistors 105 are to be protected from electrical surges by diodes 1 11 , 1 12, and 1 13. Transistors 105 include a first terminal (e.g., source) coupled to a first supply rail 106 maintained at a nominal supply voltage (e.g., Vcc), and a second terminal (e.g., drain) coupled to second supply rail 107 maintained at a nominal reference voltage (e.g., Vss). A third terminal (e.g., gate) of transistors 105 is coupled to a signal input 108, which conveys an input voltage Vin. In circuit 100, transistors 105 are protected by diodes 1 1 1 and 112 connecting signal input 108 to the supply rails 106, 107 (e.g., Vcc and Vss, respectively), and by diode 113 connecting supply rail 106 to supply rail 107.

Under normal operating conditions, diodes 1 1 1, 112 and 113 are maintained in the off-state (e.g., reverse biased) such that signal input 108 is effectively disconnected from supply rails 106, 107 while transistors 105 are driven by the supply voltage across rails 106, 107. However, upon experiencing a potential surge between signal input 108 and supply rails 106 and 107, the transient will forward bias one or more of diodes 1 1 1, 112 and 1 13, turning them on. Which of diodes 1 11 , 1 12 and 113 become forward biased is dependent on the charge polarity of the surge relative to the supply rail potentials. Charge accumulated at voltage input 108 is thereby dissipated or shunted through the diode path around transistors 105. In accordance with some embodiments, one or more diodes of a protection circuit (e.g., diodes 11 1, 112 and 113) employ a III-N heterostructure having one or more of the features described further below. The lower on-resistance of such diodes may reduce the footprint of circuit 100.

In some exemplary embodiments where transistors 105 are silicon-based, based on another group IV semiconductor, a III-V semiconductor, or III-N compound, at least one of diodes 1 11 , 112 and 113 that employ a III-N heterostructure in accordance with

embodiments herein are implemented as discrete devices (i.e., not monolithic with transistors 105). In some other embodiments where transistors 105 are silicon-based, based on another group IV semiconductor, a III-V semiconductor, or III-N compound, at least one of diodes 1 1 1, 112 and 1 13 that employ a III-N heterostructure in accordance with embodiments herein are implemented monolithically with transistor 105 as portions of an IC. In either case, any of the III-N heterostructure diodes described further herein may be employed in circuit 100. Any of the III-N heterostructure diodes described further herein may also be employed in any other suitable protection circuit designs. Any of the III-N heterostructure diodes described further herein may also be employed in circuits having functions other than ESD protection (e.g., high voltage power management circuitry).

FIG. 2A is a cross-sectional view of III-N heterostructure diodes 21 1, in accordance with some embodiments. Any of diodes 1 11 , 1 12, or 113 (FIG. 1) may have one or more of the features further described in the context of III-N heterostructure diodes 21 1, for example. As shown in FIG. 2A, III-N heterostructure diodes 21 1 comprise two diodes sharing in common a first terminal (e.g., anode) and having separate second terminals (e.g., cathodes). Although three diode terminals are illustrated in FIG. 2A, various features described in the context of FIG. 2A are also applicable to a single III-N heterostructure diode having two terminals (cathode and anode). As shown in FIG. 2A, III-N heterostructure diodes 21 1 have a first terminal (e.g., cathode) that includes a metal 250. Metal 250 may be any elemental metal or a metal alloy that forms a suitable metal-semiconductor junction with a semiconductor terminal 631 , for example as further described below. In the illustrated example, semiconductor terminal 631 has n-type conductivity. Diodes 211 have a second terminal (e.g., anode) that includes a metal 255. Metal 255 may be any elemental metal or a metal alloy that forms a suitable metal-semiconductor junction, for example as further described below. Diodes 211 further include a heterostructure 215 that includes at least three heteroj unctions, which are illustrated in FIG. 2A as solid lines between compositionally distinct III-N material layers 220, 230 221, and 231. Hence, heterostructure 215 includes a stack of four III-N material layers with a heteroj unction at each interface between these material layers. Functionally, at least III-N material layers 220 and 221 may be considered part of the same diode terminal as semiconductor terminal 631, with a rectifying junction between metal 255 and material layers of heterostructure 215.

In exemplary embodiments, heterostructure 215 includes two first III-N material layers (e.g., 220 and 221) interleaved with two second III-N material layers (e.g., 230 and 231). Differences in the composition between the material layers 220, 230, 221, and 231 result in a periodic modulation of the polarization field strength. The polarization field strength associated with each of material layers 220, 230, 221, 231 may vary as a function of the spontaneous polarization field strength as well as the piezoelectric polarization field strength associated with each layer. As shown in FIG. 2A, modulation of the polarization field strength with heterostructure 215 is such that material layer 230 induces a first 2D charge sheet 241 within material layer 220, and material layer 231 induces a second 2D charge sheet 242 within material layer 221 in the absence of any externally applied field. III- N material layers 230 and 231 are therefore both referred to herein as "polarization" layers. Within each 2D charge sheet 241 and 242, charge carrier density is sufficient to provide a conduction path between the diode terminals. Hence, the plural 2D charge sheets 241 and 242 provide plural current carrying paths between or through the diode terminals improving on-state current density (reducing on-state resistance) for a given footprint of heterostructure diodes 211.

In exemplary embodiments, III-N heterostructure 215 has monocrystalline microstructure (e.g., Wurtzite). Although monocrystalline, it is noted that crystal quality of III-N heterostructure 215 may vary dramatically, for example as a function of the techniques employed to form III-N heterostructure 215. In exemplary embodiments, dislocation density with III-N heterostructure 215 ranges between 10⁸-10ⁿ/cm². Wurtzite crystallinity lacks inversion symmetry, and more particularly the {0001 } planes are not equivalent. One of the {0001 } planes is typically referred to as the Ga-face (+c polarity) and the other referred to as the N-face (-c polarity). For the illustrated embodiment, the oaxis of the III-N

heterostructure 215 is aligned approximately normal to a top surface of substrate 205 (e.g., parallel with the z-axis in FIG. 2A). Practically however, the oaxis may be slightly tilted, for example a few degrees from normal, for example as a result of imperfect epitaxial growth on an offcut or off-axis substrate, etc. In some embodiments, the {000-1 } plane of III-N heterostructure 215 is more proximate to substrate 205. Such embodiments may be referred to as Ga polarity (+c) because the three bonds of Ga (or other group III element) point towards substrate 205. For this orientation, 2D charge sheets 241 and 242 are formed within material layers 220 and 221 within about 3-4 nm of the heteroj unction formed with the overlying polarization material layers 230, 231 , respectively. For alternate embodiments where the three bonds of Ga (or other group III element) point in the opposite direction, a comparable III-N heterostructure would be referred to as N polarity (-c), and a similar 2D charge sheet may be formed within a III-N material layer proximate to a heteroj unction formed with an underlying polarization layer. In other words, where the polarity of a III-N heterostructure is inverted relative to that of heterostructure 215, the relative positions of material layers 220 and 230 may swapped to provide equivalent 2D charge sheets of complementary conductivity type. Differences in composition between material layer 220 and 230 induce 2D charge sheet 241 while differences in composition between material layer 221 and 231 induce 2D charge sheet 242. The composition of material layer 220 may differ from the composition of material layer 221, or material layer 220 may have the same composition as material layer 221. Likewise, material layer 230 may have a different composition than material layer 231, or material layer 230 may have the same composition as material layer 231. In some embodiments where the composition of material layer 220 is the same as material layer 221 , and the composition of material layer 230 is the same as material layer 231, heterostructure 215 includes two different material compositions forming a superlattice with a periodic variation in the material composition between first material layers 220 and 221 and second material layers 230 and 231. As the bandgap for first material layers 220 and 221 will also be different than second material layers 230 and 231, heterostructure 215 may then also be considered a multiple quantum well (MQW) structure. Where the composition of material layer 220 is not the same as material layer 221 , and/or the composition of material layer 230 is not the same as material layer 231, heterostructure 215 may include three or four different material compositions forming a superlattice with quasiperiodic variation in layer composition sufficient to induce 2D charge sheets 241, 242.

In some embodiments, III-N material layer 230 has at least a higher Al content than material layer 220. III-N material layer 230 may be binary A1N, for example. III-N material layer 230 may also be an AlGaN alloy. Exemplary AlGaN embodiments include 25-40% Al (AlxGai-xN where 0.25 < x < 0.4). III-N material layer 230 may alternatively be an InAlN alloy, which is also suitable as a polarization material and may also offer advantages with respect to tuning the lattice constant to better match that of one or more other material layers within heterostructure 215. Exemplary InAlN embodiments include less than 20% In

(InxAli-xN where 0 < x < 0.2), with 17% In having the advantage of an exceptional lattice match with binary GaN.

In some embodiments, III-N material layer 231 also has at least a higher Al content than material layer 221. III-N material layer 231 may be binary A1N, for example. III-N material layer 231 may also be an AlGaN alloy. Exemplary AlGaN embodiments include 25-40% Al (AlxGai-xN where 0.25 < x < 0.4). III-N material layer 231 may also be an InAlN alloy, which while also being suitable as a polarization material may also offer advantages with respect to tuning the lattice constant to better match that of one or more other material layers within heterostructure 215. Exemplary InAlN embodiments include less than 20% In (InxAli-xN where 0 < x < 0.2), with 17% In having the advantage of an exceptional lattice match with binary GaN. In some advantageous embodiments where both material layers 220 and 221 are binary GaN, both III-N material layers 230 and 231 are binary A1N, the same AlGaN alloy (e.g., ALGai-xN where 0.25 < x < 0.4), or the same InAlN alloy (In_xAli-_xN where 0 < x < 0.2). However, it is noted that all material layers 220, 230, 221, 231 may be a tertiary or a quaternary III-N compound with variations in the group three species and/or the group III concentration varying between the layers by amounts sufficient to induce 2D charge sheets 241 and 242. For example, quaternary alloys such as In_xGa_yAli-x-yN where 0 < x < 0.2, 0 < y < 0.2 are also possible for any or all of layers 220, 230, 221, 231.

In some advantageous embodiments, at least III-N material layers 220 and 221 are intrinsic and not intentionally doped with impurities associated with a particular conductivity type. Material layers 220 and 221 in the intrinsic state can be expected to have higher charge carrier mobility than is possible for materials of higher impurity doping. Intrinsic impurity (e.g., Si) levels in material layers 220 and 221 is advantageously less than lel7 atoms/cm³, and in some exemplary embodiments is between lel4 and lel6 atoms/cm³. In the example illustrated in FIG. 2A, both material layers 220 and 221 are intrinsic binary GaN (i-GaN). Material layers 230 and 231 may also be intrinsic and not intentionally doped with impurities, for example to simplify formation of heterostructure 215.

Differences in composition within heterostructure 215 may induce strain within the III-N material layers where lattice constants are not well-matched. Strain levels may be managed through control of material layer composition and thickness so as to avoid film cracking (i.e., relaxation) within heterostructure 215. In some exemplary embodiments where material layer lattice constants are not matched, material layer thicknesses are below the critical thickness to avoid strain relaxation. In other exemplary embodiments where the material layer lattice constant remains the same between different material layers, material layer thicknesses need not be so constrained. In some exemplary embodiments, III-N material layers 220 and 221 have a thickness (TO and T2) of at least 3-4 nm to accommodate 2D charge sheets 241 and 242. Material layers 220 and 221 may be considerably thicker than 3-4 nm, and need not be the same thickness. For example, as shown in FIG. 2A, material layer 220 may be part of a buffer structure with TO being over a micrometer in thickness, while T2 may be 10 nm, or less. Generally, lower thicknesses for at least material layer 221 will simplify fabrication of III-N diode heterostructure 211, as described further below.

A reduced thickness of III-N material layers 230 and 231 (Tl and T3) also simplifies fabrication of III-N diode heterostructure 211. III-N material layers 230 and 231 may also be constrained by any associated lattice-mismatch based critical thickness (e.g., Tl and T3 in the range of 1-3 nm for A1N on a GaN 220 and 221). Thickness Tl may also be limited to mitigate any tendency to form a complementary charge sheet within the overlying material layer 221. Although a complementary charge sheet (e.g., 2D hole gas) is unlikely absent a source of complementary charge carriers (e.g., holes) in diodes 211, the thickness Tl may nevertheless be limited to less than 30 nm to help the 2D charge sheet 242 (e.g., 2DEG) overwhelm any complementary charge sheet that might form within III-N material layer 221 proximal to the heteroj unction of III-N material layer 230. III-N material layer 231, being the uppermost layer of heterostructure 215, may then be thicker than III-N material layer 230 (i.e., T3>T1). III-N heterostructure diodes 211 include a rectifying metal semiconductor contact (e.g., a semiconductor Schottky barrier). In exemplary embodiments, the rectifying metal- semiconductor junction is between the III-N material within which the 2D charge sheet resides and a metal serving as the complementary diode terminal. For the illustrated embodiments where the 2D charge sheet is a 2D electron gas (2DEG), the III-N material layers 220 and 221 within which the charge sheets 241, 242 reside are operable as the cathode while metal 255 forms an n-type semiconductor Schottky barrier and is operable as the anode. For alternative embodiments where a 2D charge sheet is a 2D hole gas (2DHG), a III-N material layer within which a 2DHG resides is operable as the anode while the Schottky metal contacting the III-N material layer forms a p-type semiconductor Schottky barrier and is operable as the cathode. Therefore, the composition of metal 255 may be selected based on the metal-semiconductor workfunction difference and surface states of material layers 220, 221 to provide the desired Schottky barrier height relative to the energy level of the charge sheets 241 , and 242. In exemplary embodiments where metal 255 makes contact to both III-N material layers 220 and 221 , the Schottky barrier height relative to each of charge sheets 241 and 242 may be substantially equal where both III-N material layers 220 and 221 have substantially the same composition. In some such embodiments, where material layers 220 and 221 are both binary GaN, and charge sheets 241 , 242 are both 2DEGs, metal 255 advantageously includes at least one of Ni, W, Pt, or TiN. Other metals or metallic compounds known to make ohmic contacts to p-type III-N materials may also be suitable for making a rectifying (n-type semiconductor Schottky barrier) contact to material layers 220 and 221. Although metal 255 is illustrated as homogeneous in FIG. 2A, a stack or laminate of metals may also be employed as the rectifying terminal. For example, where material layers 220 and 221 are compositionally distinct, a stack of two different metals may be employed to match the semiconductor Schottky barriers between the two distinct material layers 220 and 221.

Metal 255 extends through at least a portion of heterostructure 215, making direct contact on a sidewall of at least the III-N material layers 220 and 221 in which the 2D charge carrier sheets 241, 242 reside. As shown in FIG. 2A, a bottom surface of metal 255 lands on III-N material layer 220, extending a depth (z-dimension) into III-N material layer 220 that meets or exceeds the depth within which 2D sheet charge 241 resides (e.g., 2-3 nm). The z-dimension height of metal 255 is therefore at least equal to the total thickness of material layers 230, 221 and 231 summed with at least a partial thickness of material layer 220 (e.g., 2-3 nm). Metal layer 255 may therefore have a height of 100-200 nm, for example. For some such embodiments, metal layer 255 may have a lateral width (e.g., x-dimension) of 30-250 nm, for example. A second terminal of III-N heterostructure diodes in accordance with some embodiments includes a non-rectifying metal semiconductor contact (e.g., an ohmic metal- semiconductor junction or a tunneling junction contact). In the example show in FIG. 2A, the non-rectifying metal semiconductor contact is between metal 250 and semiconductor terminal 631. Alternatively, semiconductor terminal 631 may be replaced with a metal, such as one capable of forming an alloy contact with III-N material layers 220, 221. For such embodiments, the non-rectifying metal semiconductor contact is between III-N material layers 220, 221 and the metal, which, for example, may occupy the same physical space as illustrated for semiconductor terminal 631.

For embodiments illustrated by FIG. 2A where semiconductor terminal 631 is n- type, metal 250 may include at least one of Ti, Al, or W, for example. Other metals known to make ohmic contacts to n-type III-N materials may also be suitable for making an ohmic contact to semiconductor terminal 631, or an ohmic contact directly to III-N material layers

220 and 221. As shown in FIG. 2A, semiconductor terminal 631 also makes contact to both the III-N material layers 220 and 221, thereby electrically coupling to charge sheets 241 , 242. In exemplary embodiments where semiconductor terminal 631 makes contact to both III-N material layers 220 and 221, contact resistance to each of charge sheets 241 and 242 may be substantially equal where both III-N material layers 220 and 221 have substantially the same composition. The conductivity type of semiconductor terminal 631 matches the conductivity type of charge sheets 241 and 242. For example, where material layers 220 and

221 are both binary GaN and charge sheets 241, 242 are both 2DEGs, semiconductor terminal 631 has n-type conductivity. Impurity doping levels are advantageously as high as practical (e.g., N+) for lowest diode on-state resistance.

Semiconductor terminal 631 may have any composition, but is advantageously also a III-N material. For some such embodiments, semiconductor terminal 631 is epitaxial, having the same crystallinity and orientation as heterostructure 215. In some exemplary

embodiments, semiconductor terminal 631 has a narrower band gap than that of material layers 220 and 221. For example, semiconductor terminal 631 may be an III-N alloy that includes more Indium (In) than material layers 220 and 221. In some embodiments where material layers 220 and 221 and both binary GaN, semiconductor terminal 631 is InGaN. Exemplary InGaN embodiments include 5-20% In (In_xGai-_xN with 5% < x < 20%). The III- N alloy composition may be constant or graded between heterostructure 215 and metal 250. For embodiments where semiconductor terminal 631 is a III-N material, n-type doping may be in the form of Si or Ge impurities, for example. Impurity doping levels are

advantageously at least lel7 atom/cm³, and more advantageously at least lel8 atom/cm³.

Semiconductor terminal 631 extends through at least a portion of heterostructure 215, making direct contact on a sidewall of layers 220 and 221 in which the 2D charge carrier sheets 241, 242 reside. As shown in FIG. 2 A, semiconductor terminal 631 lands on III-N material layer 220, extending a depth (z-dimension) into III-N material layer 220 that meets or exceeds the depth within which 2D sheet charge 241 resides (e.g., 3-4 nm). The z- dimension height of semiconductor terminal 631 is therefore at least equal to the total thickness of material layers 230, 221 and 231 summed with at least a partial thickness of material layer 220 (e.g., 3-4 nm). Semiconductor terminal 631 may extend to a depth into III-N material layer 220 that is significantly (e.g., 10-30 nm) greater than that of the metal 255 as formation of the semiconductor-semiconductor junction is less sensitive to surface chemistry/states than is the rectifying metal-semiconductor junction.

Substrate 205 may be any substrate suitable for the formation of III-N heterostructure 215. In some embodiments, substrate 205 includes, or is, SiC. In other embodiments, growth substrate 205 is a cubic semiconductor, such as monocrystalline silicon. For such embodiments, template structures may be formed on a cubic substrate surface, such as a (100) surface. III-N heterostructure 215 may also be grown on other surfaces (e.g., 110, 111, miscut or offcut, for example 2-10° toward [110] etc.). Substrate 205 may also merely be a carrier upon which heterostructure 215 has been bonded, in which case substrate 205 may be crystalline, or not (e.g., glass, polymer, etc.). As further shown in FIG. 2A, an insulative dielectric material 260 is over III-N heterostructure 215. Dielectric material 260 may be of any composition known to be suitable as a passivation and/or protective encapsulant of III-N devices, such as, but not limited to silicon oxides (SiO), silicon nitrides (SiN), silicon oxynitrides (SiON), silicon carbonitrides (SiCN), or low-k materials (e.g., carbon doped silicon dioxide (SiOC), porous dielectrics, etc.), and metal oxides (e.g., AI2O3). FIG. 2B and FIG 2C are plan views of III-N heterostructure diodes 211 , in accordance with some embodiments. The dot-dashed A- A' line in FIG. 2B and FIG. 2C denotes the cross-sectional plane illustrated in FIG. 2A. As shown in FIG. 2B and FIG. 2C, the length (e.g., y-dimension) of diode terminal metals 250 and 255 may be varied to achieve a given on-state resistance. Additionally, or in the alternative, a given on-state resistance may be achieved by varying the number of diode terminal metals 250 and 255 operated in electrical parallel. In either case however, the footprint (area) of the diode will vary as the x or y dimension(s) of the diode terminals vary. In the views shown in FIG. 2B and 2C, the footprint (area) occupied by III-N heterostructure diodes 211 is denoted by a diode cell perimeter line 271. Diode cell perimeter line 271 associated with III-N

heterostructure diodes 211 is compared with a diode cell perimeter line 275 associated with a III-N diode lacking heterostructure 215, but having a comparable on-state resistance. The area occupied within diode cell perimeter line 275 may be nearly twice that of the area occupied within diode perimeter line 271. Accordingly, III-N heterostructure diodes 211 may display a figure of merit (e.g., resistance* capacitance* area) improved by nearly a factor of two.

FIG. 3 is a cross-sectional view of III-N heterostructure diodes 31 1 , in accordance with some embodiments. III-N heterostructure diodes 31 1 share many of the structural features of III-N heterostructure diodes 211 (e.g., FIG. 2A), with the shared features having the same reference number. III-N heterostructure diodes 31 1 further illustrate how additional III-N material layers may be included to further improve diode figures of merit (e.g., resistance*capacitance*area). As shown, III-N heterostructure diodes 31 1 include additional III-N material layers 321 and 331 formed over heterostructure 215. Material layers 321 and 331 may replicate material layers 221 and 231, respectively, so as to generate a third charge carrier sheet 343. With each additional charge carrier sheet, on-state resistance may be reduced for a given diode footprint as limited only by practicality of fabricating the more aggressive feature aspect ratios resulting from the incremental increase in z-height associated with each pair of additional III-N material layers.

The III-N heterostructure diodes described above may be fabricated using a variety of methods. FIG. 4 is a flow diagram illustrating methods 401 for forming III-N

heterostructure diodes, in accordance with some embodiments. Methods 401 begin at operation 405 where a substrate including a crystalline seed layer is received. The substrate received at operation 405 may be any of those described above, for example. At operation 410, a III-N epitaxial growth process is employed to form a III-N heterostructure on the substrate seeding surface. Such epitaxial growth may form continuous crystals over an entire surface of a substrate, or may be limited to islands or mesas occupying only a portion of a substrate surface as controlled through a templating pattern.

Methods 401 continue at operation 415 where a first trench that is to host one of the diode terminals is etched into the III-N heterostructure, exposing sidewalls of the various material layers included within the III-N heterostructure. Any etch process suitable for the III-N materials may be employed at operation 415. In the exemplary embodiment illustrated in FIG. 4, the first trench etched at operation 415 exposes at least three heteroj unctions and is to host an impurity-doped semiconductor that is formed within the trench at operation 420. While any deposition process suitable for forming a poly crystalline material may be performed at operation 420, in some advantageous embodiments an epitaxial growth process is employed at operation 420 to grow a monocrystalline III-N impurity-doped

semiconductor within the first trench. Impurity doping may be in-situ during the growth or deposition, but a subsequent implant and activation process may also be performed (in the alternative, or in addition to in-situ doping).

Methods 401 continue at operation 425 where a second trench is etched into the III-N heterostructure, again exposing at least the three heteroj unctions exposed by the first trench. Any etch process suitable for the III-N materials may be employed at operation 425. The second trench formed at operation 425 is to host a metal deposited into the trench at operation 430 to form a rectifying (Schottky) metal-semiconductor junction at the sidewalls of two or more material layers exposed by the trench. Any deposition process suitable for the chosen metal may be employed at operation 430. Methods 401 complete at operation 435 where one or more interconnect levels, for example including diode contact metallization, are formed using any techniques known to be suitable for the purpose. For embodiments where the diodes are to be monolithically integrated into an IC, any known back-end-of-line (BEOL) processing may be performed at operation 435 to complete the IC. Following operation 435, an IC including III-N heterostructure diodes, or discrete III-N heterostructure diodes are substantially complete and may be singulated and packaged following any suitable techniques. FIG. 5A, 5B, 5C, 5D, 5E and 5F are cross-sectional views of III-N heterostructure diodes 21 1 evolving as selected operations in the methods 401 are performed, in accordance with some embodiments. In FIG. 5 A, III-N heterostructure 215 has been epitaxially grown over a crystalline seeding surface of substrate 205. III-N heterostructure 215 may have been grown within an opening of amorphous material (not depicted) defining any suitable template structure. In some embodiments the seeding surface is SiC. In other embodiments, the seeding surface is a (100) cubic semiconductor surface is exposed within trenches extending in a <1 10> direction of the substrate.

Growth of III-N heterostructure 215 may include deposition of a seed layer, such as A1N (not depicted) and further include intrinsic GaN growth using first epitaxial growth conditions (e.g., a first growth pressure, a first growth temperature, and a first V/III growth precursor ratio) to form III-N material layer 220. Following an initial growth period, growth conditions may be changed to a second growth pressure, temperature, and/or a second V/III growth precursor ratio to form III-N material layer 230. Following this second growth period, growth conditions may be changed back to the first growth conditions, or changed to a third growth pressure, temperature, and/or a third V/III growth precursor ratio to form III- N material layer 221. Following this third growth period, growth conditions may be returned to the second growth conditions, or changed to a fourth growth pressure, temperature, and/or a fourth V/III growth precursor ratio to form III-N material layer 231. These III-N material growths may be by any known technique, such as, but not limited to metal-organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE). In some embodiments, elevated temperatures of 900 °C, or more, are employed.

As further shown in FIG. 5B, a dielectric material 260 has been deposited over III-N heterostructure 215 using any suitable technique and first trenches 505 have been etched into III-N heterostructure 215. Trenches 505 may be separated by a distance of no more than 100 nm, for example. Trenches 505 may be defined with a first lithographic masking process followed by an anisotropic (e.g., dry/plasma) etch through III-N material layers 231 , 221 and 230, with the etch front stopping within III-N material layer 220 at a depth sufficient for the trench sidewall to expose 2D charge carrier sheet 241. Overetch of trenches 505 may 20 nm, or more, for example.

As shown in Fig. 5C, impurity-doped III-N semiconductor material 231 has been epitaxially grown within trenches 505 to at least partially backfill trenches 505, contacting at least the sidewalls of III-N material layers 220 and 221. In some embodiments, in-situ doped n+ III-N material has been epitaxially grown at nucleation sites on an exposed c-plane of III- N material layer 220. In some specific embodiments, trenches 505 are backfilled with n+ InGaN material. With the high-temperature semiconductor material processing now complete, the rectifying metal-semiconductor junction may be formed.

As shown in FIG. 5D, dielectric material 260 has been planarized over

semiconductor terminal 631, and a second trench 506 has been etched through dielectric material 260 and into III-N heterostructure 215. Trench 506 may be defined with a second lithographic masking process defining an opening with a lateral dimension no more than 50 nm, for example. As illustrated, trench 506 has been aligned to the first trench pattern to bifurcate the III-N heterostructure 215 disposed between two adjacent impurity -doped semiconductor materials 231. Trench 506 may be formed with an anisotropic (e.g., dry/plasma) etch that passes through III-N material layers 231, 221 and 230, with the etch front stopping within III-N material layer 220 at a depth sufficient for the trench sidewall to expose 2D charge carrier sheet 241. Advantageously, overetch of trench 506 may be minimal (e.g., less than 10 nm) to limit the trench aspect ratio. Trench 506 may also be finished with a wet chemical etch or other surface treatment to improve the quality of the sidewall surface where the Schottky junction is to be formed.

As shown in FIG. 5E, metal 255 has been deposited to at least partially backfill trench 506, contacting exposed sidewalls of III-N material layers 220, 230, 221 and 231. Any metal deposition process, such as, but not limited to, physical vapor deposition, chemical vapor deposition, atomic layer deposition, and the like, may be employed to deposit any suitable metal 255, such as any of those examples described elsewhere herein. Contact trenches or openings may then be etched into dielectric material 260 overlying semiconductor terminal 631. As illustrated in FIG. 5F, contact metal 250 may then be deposited with any suitable process and planarized with at metal 255 and/or dielectric material 260 to arrive at III-N heterostructure diodes 211.

FIG. 6 illustrates a system 600 in which a mobile computing platform 605 and/or a data server machine 606 employs an circuitry including at least one III-N heterostructure diode, in accordance with some embodiments. The server machine 606 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes circuitry 650. The mobile computing platform 605 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 605 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 610, and a battery 615.

Whether disposed within the integrated system 610 illustrated in the expanded view 620, or as a stand-alone packaged chip within the server machine 606, the a IC includes at least one III-N heterostructure diode, for example as describe elsewhere herein. The circuitry 650 may be further affixed to a board, a substrate, or an interposer 660 along with a power management integrated circuit (PMIC). Functionally, PMIC 630 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 615 and with an output providing a current supply to other functional modules.

Circuitry 650, in some embodiments, includes RF (wireless) integrated circuitry (RFIC) further including a wideband RF (wireless) transmitter and/or receiver (TX/RX including a digital baseband and an analog front end module comprising a power amplifier on a transmit path and a low noise amplifier on a receive path). The RFIC includes at least one III-N heterostructure diode, for example in a over-voltage protection circuit as describe elsewhere herein. The RFIC has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. FIG. 7 is a functional block diagram of a computing device 700, arranged in accordance with at least some implementations of the present disclosure. Computing device 700 may be found inside platform 605 or server machine 606, for example. Device 700 further includes a motherboard 702 hosting a number of components, such as, but not limited to, a processor 704 (e.g., an applications processor), which may further incorporate at least one III-N heterostructure diode, in accordance with embodiments of the present invention. Processor 704 may be physically and/or electrically coupled to motherboard 702. In some examples, processor 704 includes an integrated circuit die packaged within the processor 704. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory. In various examples, one or more communication chips 706 may also be physically and/or electrically coupled to the motherboard 702. In further implementations,

communication chips 706 may be part of processor 704. Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to motherboard 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.

Communication chips 706 may enable wireless communications for the transfer of data to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 706 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 700 may include a plurality of communication chips 706. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other

implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure. It will be recognized that the invention is not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below. In one or more first examples, a Group Ill-nitride (III-N) diode structure comprises a first terminal comprising one or more first metals, and a second terminal comprising a III-N heterostructure including three or more III-N material heteroj unctions and two or more III-N material layers that are electrically coupled to one or more second metals.

In one or more second examples, for any of the first examples the one or more first metals form a rectifying Schottky barrier with the two or more III-N material layers of the heterostructure, and the second terminal further comprises an n-type III-N material contacting the two or more III-N material layers.

In one or more third examples, for any of the first or second examples the heterostructure comprises the two or more III-N material layers interleaved with two or more second III-N material layers of higher Al content.

In one or more fourth examples, for any of the first through third examples the two or more III-N material layers comprise binary GaN and the two or more second III-N material layers comprise Al_xGai-_xN, In_yAh-_yN, or In_yAli-y-zGa_zN.

In one or more fifth examples, for any of the fourth examples x is between 0.25 and 0.4, y is less than 0.2, or z is less than 0.2.

In one or more sixth examples, for any of the first through fifth examples individual ones of the two or more III-N material layers have substantially the same III-N composition, and individual ones of the two or more second III-N material layers have substantially the same composition. In one or more seventh examples, for any of the first through sixth examples two or more of the III-N material layers have a thickness less than lOnm.

In one or more eighth examples, for any of the first through seventh examples the heterostructure is disposed over a substrate with a oaxis of the heterostructure oriented substantially normal to the substrate and an N-face of the heterostructure proximal to the substrate, an impurity-doped semiconductor extends through the heterostructure with a sidewall of the impurity-doped semiconductor contacting the two or more III-N material layers, and the one or more first metals extend through the heterostructure with a sidewall of the first metals contacting the two or more III-N material layers.

In one or more ninth examples, for any of the eighth examples the impurity-doped semiconductor extends through the heterostructure to a first depth in the substrate, and the one or more first metals extend through the heterostructure to a second depth in the substrate, different than the first.

In one or more tenth examples, for any of the eighth through ninth examples the impurity-doped semiconductor comprises In_xGai-_xN with x between 0.05 and 0.2, the impurity-doped semiconductor has an impurity concentration of at least l ei 8 atoms/cm³, and the each of the III-N material layers of the heterostructure have an impurity doping level below l ei 6 atoms/cm³.

In one or more eleventh examples, for any of the first through tenth examples the one or more metals include at least one of Ni, W, Pt, or TiN, the second terminal further comprises one or more second metals in contact with the two or more III-N material layers, or in contact with an impurity-doped semiconductor that is in contact with the two or more III-N material layers, and the one or more second metals includes at least one of Al or Ti.

In one or more twelfth examples, for any of the first through eleventh examples the heterostructure is disposed over a substrate with a oaxis of the heterostructure oriented substantially normal to an interface between the heterostructure and the substrate, and the substrate comprises a (100), (1 11), or (1 10) silicon surface.

In one or more thirteenth examples, a computer platform includes one or more RF transceiver, and an antenna coupled to the RF transceiver, wherein the RF transceiver has one or more signal input coupled to the first or second terminal of the diode structure in any one of the first through twelfth examples.

In one or more fourteenth examples, for any of the thirteenth examples the platform includes a processor communicatively coupled to the RF transceiver, and a battery coupled to at least one of the processor and RF transceiver. In one or more fifteenth examples, a Group Ill-nitride (III-N) diode structure comprises a first terminal comprising one or more first metals, and a pair of second terminals on opposite sides of the first terminal, wherein individual ones of the second terminals comprise a III-N heterostructure including three or more III-N material heteroj unctions and two or more III-N material layers that are electrically coupled to one or more second metals.

In one or more sixteenth examples, for any of the fifteenth examples, one or more first metals form a rectifying Schottky barrier with the two or more III-N material layers of the heterostructure, the second terminal further comprises an n-type III-N material contacting the two or more III-N material layers, and the heterostructure comprises the two or more III-N material layers interleaved with two or more second III-N material layers of higher Al content.

In one or more seventeenth examples, for any of the fifteenth or sixteenth examples the two or more III-N material layers comprise binary GaN and the two or more second III- N material layers comprise Al_xGai-_xN, In_yAh-_yN, or In_yAli-_y-_zGazN, with x between 0.25 and 0.4, y is less than 0.2, or z is less than 0.2.

In one or more eighteenth examples, a method of forming a semiconductor device comprises epitaxially growing a Group Ill-nitride (III-N) heterostructure comprising three or more III-N material heteroj unctions, etching a first trench into the heterostructure exposing two or more III-N material layers of the heterostructure, forming a first contact to the two or more III-N material layers by at least partially backfilling the first trench with an impurity- doped semiconductor or metal, etching a second trench into the heterostructure exposing the two or more III-N material layers, and forming a second contact to the two or more III-N material layers by at least partially backfilling the second trench with one or more second metals.

In one or more nineteenth examples for any of the eighteenth examples epitaxially growing the heterostructure further comprises growing the two or more III-N material layers interleaved with two or more second III-N material layers of a higher Al content, etching the first and second trenches further comprises etching through the two or more III-N material layers and etching through the two or more second III-N material layers, and backfilling the first trench with the impurity-doped semiconductor or metal further comprises epitaxially growing in-situ doped n-type In_xGai-_xN with x between 0.05 and 0.2 in contact with at least the first III-N material layers.

In one or more twentieth examples, for any of the eighteenth through nineteenth examples the two or more III-N material layers comprise binary GaN and the two or more second III-N material layers comprise AkGai-xN, In_yAh-_yN, or In_yAli-_y-zGazN.

In one or more twenty-first examples, for any of the eighteenth through twentieth examples at least partially backfilling the second trench further comprises depositing at least one of Ni, W, Pt, or TiN in contact with at least the two or more III-N material layers.

In one or more twenty-second examples, for any of the eighteenth through twenty- first examples the method comprises depositing a dielectric layer over the heterostructure, and etching the second trench further comprises patterning a mask over the dielectric layer after backfilling the first trench, the mask having an opening with a lateral dimension no more than 50 nm where the second trench is to be formed.

In one or more twenty -third examples, for any of the eighteenth through twenty - second examples the first and second trenches are separated by a distance no more than 100 nm.

In one or more twenty -fourth examples, for any of the eighteenth through twenty- third examples epitaxially growing the heterostructure further comprises growing the heterostructure with the oaxis of the heterostructure oriented substantially normal to a substrate.

In one or more twenty-fifth examples, for any of the eighteenth through twenty- fourth examples the substrate comprises a (100), (11 1), or (1 10) silicon surface.

However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMS What is claimed is:

1. A Group Ill-nitride (III-N) diode structure, comprising:

a first terminal comprising one or more first metals; and

a second terminal comprising a III-N heterostructure including three or more III-N material heteroj unctions and two or more III-N material layers that are electrically coupled to one or more second metals.

2. The diode structure of claim 1, wherein:

the one or more first metals form a rectifying Schottky barrier with the two or more III-N material layers of the heterostructure; and

the second terminal further comprises an n-type III-N material contacting the two or more

III-N material layers.

3. The diode structure of claim 1, wherein:

the heterostructure comprises the two or more III-N material layers interleaved with two or more second III-N material layers of higher Al content.

4. The diode structure of claim 3, wherein the two or more III-N material layers comprise binary GaN and the two or more second III-N material layers comprise Al_xGai-_xN, In_yAli-_yN, or In_yAli-y-zGa_zN.

5. The diode structure of claim 4, wherein x is between 0.25 and 0.4, y is less than 0.2, or z is less than 0.2.

6. The diode structure of claim 3, wherein individual ones of the two or more III-N material layers have substantially the same III-N composition, and individual ones of the two or more second III-N material layers have substantially the same composition.

7. The diode structure of claim 3, wherein two or more of the III-N material layers have a thickness less than lOnm.

8. The diode structure of claim 1 , wherein:

the heterostructure is disposed over a substrate with a oaxis of the heterostructure oriented substantially normal to the substrate and an N-face of the heterostructure proximal to the substrate;

an impurity-doped semiconductor extends through the heterostructure with a sidewall of the impurity-doped semiconductor contacting the two or more III-N material layers; and the one or more first metals extend through the heterostructure with a sidewall of the first metals contacting the two or more III-N material layers.

9. The diode structure of claim 8, wherein the impurity-doped semiconductor extends

through the heterostructure to a first depth in the substrate, and the one or more first metals extend through the heterostructure to a second depth in the substrate, different than the first.

10. The diode structure of claim 9, wherein

the impurity-doped semiconductor comprises In_xGai-_xN with x between 0.05 and 0.2;

the impurity-doped semiconductor has an impurity concentration of at least l ei 8 atoms/cm³; and

the each of the III-N material layers of the heterostructure have an impurity doping level below l ei 6 atoms/cm³.

11. The diode structure of claim 1, wherein:

the one or more metals include at least one of Ni, W, Pt, or TiN;

the second terminal further comprises one or more second metals in contact with the two or more III-N material layers, or in contact with an impurity-doped semiconductor that is in contact with the two or more III-N material layers; and

the one or more second metals includes at least one of Al or Ti.

12. The diode structure of any one of claims 1 -11 , wherein:

the heterostructure is disposed over a substrate with a oaxis of the heterostructure oriented substantially normal to an interface between the heterostructure and the substrate; and

the substrate comprises a (100), (1 11), or (110) silicon surface.

13. A computer platform including:

one or more RF transceiver; and

an antenna coupled to the RF transceiver, wherein the RF transceiver has one or more signal input coupled to the first or second terminal of the diode structure recited in any one of claims 1-12.

14. The computer platform of claim 13, comprising:

a processor communicatively coupled to the RF transceiver; and

a battery coupled to at least one of the processor and RF transceiver.

15. A Group Ill-nitride (III-N) diode structure, comprising:

a first terminal comprising one or more first metals; and

a pair of second terminals on opposite sides of the first terminal, wherein individual ones of the second terminals comprise a III-N heterostructure including three or more III-N material heteroj unctions and two or more III-N material layers that are electrically coupled to one or more second metals.

16. The diode structure of claim 15, wherein:

one or more first metals form a rectifying Schottky barrier with the two or more III-N

material layers of the heterostructure;

III-N material layers; and

17. The diode structure of claim 16, wherein the two or more III-N material layers comprise binary GaN and the two or more second III-N material layers comprise Al_xGai-_xN, In_yAli-_yN, or In_yAli-y-zGa_zN, with x between 0.25 and 0.4, y is less than 0.2, or z is less than 0.2.

18. A method of forming a semiconductor device, the method comprising:

epitaxially growing a Group Ill-nitride (III-N) heterostructure comprising three or more III- N material heteroj unctions; etching a first trench into the heterostructure exposing two or more III-N material layers of the heterostructure;

forming a first contact to the two or more III-N material layers by at least partially

backfilling the first trench with an impurity-doped semiconductor or metal;

etching a second trench into the heterostructure exposing the two or more III-N material layers; and

forming a second contact to the two or more III-N material layers by at least partially

backfilling the second trench with one or more second metals.

19. The method of claim 18, wherein:

epitaxially growing the heterostructure further comprises growing the two or more III-N material layers interleaved with two or more second III-N material layers of a higher Al content;

etching the first and second trenches further comprises etching through the two or more III- N material layers and etching through the two or more second III-N material layers; and

backfilling the first trench with the impurity-doped semiconductor or metal further

comprises epitaxially growing in-situ doped n-type In_xGai-_xN with x between 0.05 and 0.2 in contact with at least the first III-N material layers.

20. The method of claim 19, wherein the two or more III-N material layers comprise binary

GaN and the two or more second III-N material layers comprise Al_xGai-_xN, In_yAli- yN, or In_yAli-y-zGazN.

21. The method of claim 19, wherein at least partially backfilling the second trench further comprises depositing at least one of Ni, W, Pt, or TiN in contact with at least the two or more III-N material layers.

22. The method of claim 19, further comprising depositing a dielectric layer over the

heterostructure; and wherein etching the second trench further comprises patterning a mask over the dielectric layer after backfilling the first trench, the mask having an opening with a lateral dimension no more than 50 nm where the second trench is to be formed.

23. The method of claim 19, wherein the first and second trenches are separated by a distance no more than 100 nm.

24. The method of any one of claims 18-23, wherein:

epitaxially growing the heterostructure further comprises growing the heterostructure with the oaxis of the heterostructure oriented substantially normal to a substrate.

25. The method of claim 24, wherein the substrate comprises a (100), (1 11), or (110) silicon surface.