WO2024045637A1 - 一种显示面板及其制备方法 - Google Patents

一种显示面板及其制备方法 Download PDF

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Publication number
WO2024045637A1
WO2024045637A1 PCT/CN2023/089251 CN2023089251W WO2024045637A1 WO 2024045637 A1 WO2024045637 A1 WO 2024045637A1 CN 2023089251 W CN2023089251 W CN 2023089251W WO 2024045637 A1 WO2024045637 A1 WO 2024045637A1
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WIPO (PCT)
Prior art keywords
layer
opening
type electrode
bonding layer
display panel
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PCT/CN2023/089251
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English (en)
French (fr)
Inventor
黄凯
张箫巍
杨旭
李金钗
张�荣
Original Assignee
厦门大学
嘉庚创新实验室
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Publication of WO2024045637A1 publication Critical patent/WO2024045637A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel and a preparation method thereof.
  • LED Light Emitting Diode
  • LED Light Emitting Diode
  • Micro-LED has found relevant applications in display, optical communication, indoor positioning, biological and medical fields, and is expected to be further expanded to wearable/implantable devices, augmented reality/virtual reality, and vehicle-mounted displays. , ultra-large displays, optical communications/optical interconnection, medical detection, smart car lights, space imaging and other fields, it has clear and promising market prospects.
  • Micro-LED chips to display technology requires millions or even tens of millions of Micro-LED chips to be accurately and efficiently moved to the display panel. Taking a 4K TV as an example, the Micro-LED chips that need to be transferred There are as many as 24 million chips (calculated based on 4000 ⁇ 2000 ⁇ R/G/B three colors). Even if 10,000 Micro-LED chips are transferred at one time, it needs to be repeated 2,400 times.
  • the existing technology has poor accuracy in the bonding position between the Micro-LED chip and the substrate, causing bonding failure between the Micro-LED chip and the bonding layer.
  • the technical problem to be solved by this application is to overcome the bonding failure problem between the Micro-LED chip and the bonding layer in the prior art, thereby providing a display panel and a preparation method thereof.
  • the present application provides a method for preparing a display panel, which includes: providing a first substrate with several spaced Micro-LED chips on one side of the first substrate.
  • the Micro-LED chip includes: a chip body; a P-type electrode and N-type electrodes are located on part of the surface on one side of the chip body; a second substrate is provided, and one side surface of the second substrate has several conductive layers; an isolation layer is formed on the second substrate, and the isolation layer
  • each opening group includes spaced first openings and second openings, the first openings and the second openings respectively expose the surface of the conductive layer, and the width of the first opening is smaller than that of the P-type
  • the width of the electrode, the width of the second opening is smaller than the width of the N-type electrode; a first bonding layer is formed in the first opening, and a second bonding layer is formed in the second opening; with the isolation layer
  • the chip body is supported, and the P-type electrode is bonded to the first bonding layer while the N-type electrode is
  • the chip body includes: an N-type semiconductor layer; an active layer located on part of the surface on one side of the N-type semiconductor layer; and a P layer located on a side surface of the active layer away from the N-type semiconductor layer.
  • type semiconductor layer the P-type electrode is located on a side surface of the P-type semiconductor layer facing away from the active layer
  • the N-type electrode is located on the side of the active layer, the P-type semiconductor layer and the P-type electrode Part of the surface on one side of the N-type semiconductor layer; during the process of bonding the P-type electrode to the first bonding layer and bonding the N-type electrode to the second bonding layer,
  • the isolation layer supports the P-type semiconductor layer around the P-type electrode.
  • the method further includes: before forming the first bonding layer in the first opening, forming a first slope surface at the interface between the side wall of the first opening and the top surface of the isolation layer around the first opening; Before forming the second bonding layer in the second opening, a second slope surface is formed at the interface between the sidewall of the second opening and the top surface of the isolation layer around the second opening.
  • ⁇ 1 is the first included angle.
  • ⁇ 1 is the friction coefficient of the first slope surface.
  • ⁇ 2 is the second included angle.
  • ⁇ 2 is the friction coefficient of the second slope surface.
  • it also includes: forming a barrier layer on the isolation layer around the opening group before bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, There is a third opening in the barrier layer, and the width of the third opening is greater than the width of the Micro-LED chip.
  • the width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.
  • the blocking layer is a light-shielding blocking layer.
  • the light-shielding blocking layer is made of light-shielding resin.
  • the height of the barrier layer away from the top surface of the side of the second substrate is Greater than the height of the top surface of the side of the Micro-LED chip away from the second substrate.
  • the binding equipment used has characteristic alignment accuracy; the first The width of the opening is greater than or equal to the sum of the width of the P-type electrode and 2 times the feature alignment accuracy, and the width of the second opening is greater than or equal to the sum of the N-type electrode and 2 times the feature alignment accuracy. The sum of precisions.
  • the thickness of the first bonding layer is greater than or equal to 80% of the depth of the first opening. % and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is greater than or equal to 80% of the depth of the second opening and less than or equal to the depth of the second opening.
  • the thickness of the isolation layer is less than or equal to 50% of the thickness difference between the N-type electrode and the P-type electrode.
  • the thickness of the isolation layer is 500 nm to 1000 nm.
  • the material of the first bonding layer and the second bonding layer is solder; the material of the first bonding layer and the second bonding layer is conductive glue.
  • the application also provides a display panel, including: a first substrate.
  • One side of the first substrate has several spaced Micro-LED chips.
  • the Micro-LED chip includes: a chip body; a P-type electrode and an N-type electrode. , a part of the surface located on one side of the chip body; a second substrate, one side surface of the second substrate has several conductive layers; an isolation layer located on one side of the second substrate, the isolation layer has several Opening groups, each opening group includes spaced first openings and second openings, the first openings and second openings are respectively located on the conductive layer, the width of the first opening is smaller than the width of the P-type electrode, The width of the second opening is smaller than the width of the N-type electrode; a first bonding layer located in the first opening; a second bonding layer located in the second opening; the P-type electrode is embedded in the first bonding layer layer, the N-type electrode is embedded in the second bonding layer; the chip body is in contact with the top surface of part of the isolation layer.
  • the chip body includes: an N-type semiconductor layer; an active layer located on part of the surface on one side of the N-type semiconductor layer; and a P layer located on a side surface of the active layer away from the N-type semiconductor layer.
  • type semiconductor layer the P-type electrode is located on a side surface of the P-type semiconductor layer facing away from the active layer
  • the N-type electrode is located on the side of the active layer, the P-type semiconductor layer and the P-type electrode Part of the surface on one side of the N-type semiconductor layer
  • the P-type semiconductor layer around the P-type electrode is in contact with the top surface of the isolation layer around the first opening.
  • first slope surface between the side wall of the first opening and the top surface of the isolation layer around the first opening; and there is a first slope surface between the side wall of the second opening and the top surface of the isolation layer around the second opening.
  • Second slope surface there is a first slope surface between the side wall of the second opening and the top surface of the isolation layer around the second opening.
  • ⁇ 1 is the first included angle.
  • ⁇ 1 is the friction coefficient of the first slope surface.
  • ⁇ 2 is the second included angle.
  • ⁇ 2 is the friction coefficient of the second slope surface.
  • the method further includes: a barrier layer located on the isolation layer around the opening group, the barrier layer having a third opening, the width of the third opening being greater than the width of the Micro-LED chip.
  • the width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.
  • the blocking layer is a light-shielding blocking layer.
  • the light-shielding blocking layer is made of light-shielding resin.
  • the height of the barrier layer away from the top surface of the side of the second substrate is Greater than the height of the top surface of the side of the Micro-LED chip away from the second substrate.
  • the width of the first opening is greater than or equal to the sum of the width of the P-type electrode and 2 times the feature alignment accuracy
  • the width of the second opening is greater than or equal to the sum of the width of the N-type electrode and 2 times the feature alignment accuracy.
  • the sum of feature alignment accuracy is 0.5 ⁇ m to 2 ⁇ m.
  • the thickness of the first bonding layer is greater than or equal to 80% of the depth of the first opening and less than or equal to the depth of the first opening
  • the thickness of the second bonding layer is greater than or equal to the depth of the second opening. 80% of the depth and less than or equal to the depth of the second opening.
  • the thickness of the isolation layer is less than or equal to 50% of the thickness difference between the N-type electrode and the P-type electrode.
  • the thickness of the isolation layer is 500 nm to 1000 nm.
  • the material of the first bonding layer and the second bonding layer is solder; the material of the first bonding layer and the second bonding layer is conductive glue.
  • the isolation layer is used to support the chip body, and the P-type electrode is bonded to the first bonding layer while the N-type electrode is bonded to the first bonding layer.
  • the second bonding layer performs bonding, the P-type electrode is embedded in the first bonding layer, and the N-type electrode is embedded in the second bonding layer.
  • the first opening allows the P-type electrode to enter, and the second opening allows the N-type electrode to enter.
  • the isolation layer supports the chip body around the P-type electrode, increasing the self-alignment function.
  • the Micro-LED chip is laterally offset. The amount is limited by the side wall of the first opening and the side wall of the second opening, ensuring the stability of the bonding.
  • the material of the first bonding layer can be confined in the first opening, and the material of the second bonding layer can be confined in the second opening, reducing the number of materials of the first bonding layer and the second bonding layer during the bonding process.
  • the lateral offset of the material of the layer prevents short circuit between the first bonding layer and the second bonding layer.
  • Figures 1 to 2 are schematic diagrams of a preparation process of a display panel
  • FIGS 3 to 4 are schematic diagrams of the preparation process of another display panel
  • 5 to 10 are schematic diagrams of the preparation process of a display panel provided by an embodiment of the present application.
  • 11 to 13 are schematic diagrams of the preparation process of a display panel provided by another embodiment of the present application.
  • 14 to 16 are schematic diagrams of a preparation process of a display panel provided by another embodiment of the present application.
  • a method of preparing a display panel including: referring to Figure 1, providing a first substrate 101 with conductive pillars on the first substrate 102.
  • the surface of the conductive pillar 102 facing away from the first substrate 101 is provided with solder 103;
  • a second substrate 105 is provided, and one side surface of the second substrate 105 has several spaced Micro-LED chips 104; connect the second substrate 105 and the first substrate 105.
  • a substrate 101 is arranged oppositely, and the electrode of the Micro-LED chip 104 faces the solder 103; referring to Figure 2, the electrode of the Micro-LED chip 104 is welded to the solder 103.
  • a first substrate 101a is provided.
  • the surface of the first substrate 101a has several electrodes (not shown).
  • the surface of the electrodes has a conductive colloid 102a.
  • the inside of the conductive colloid 102a is There are conductive particles 106; refer to Figure 3, a second substrate 105 is provided, and one side surface of the second substrate 105 has several spaced Micro-LED chips 104.
  • the Micro-LED chip 104 includes P-type electrodes and N-type electrodes; Refer to Figure 4 , the second substrate 105 and the first substrate 101a are arranged oppositely, the P-type electrode of the Micro-LED chip 104 is bonded to part of the conductive colloid 102a, and the N-type electrode of the Micro-LED chip 104 is bonded to part of the conductive colloid 102a. combine together.
  • This application provides a display panel and a preparation method thereof, which can avoid bonding failure between the Micro-LED chip and the bonding layer.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediary; it can also be an internal connection between two components; it can be a wireless connection or a wired connection connect.
  • connection or integral connection
  • connection or integral connection
  • connection can be a mechanical connection or an electrical connection
  • it can be a direct connection or an indirect connection through an intermediary
  • it can also be an internal connection between two components
  • it can be a wireless connection or a wired connection connect.
  • An embodiment of the present application provides a method for manufacturing a display panel, including:
  • S1 Provide a first substrate.
  • One side of the first substrate has several spaced Micro-LED chips.
  • the Micro-LED chip includes: a chip body; P-type electrodes and N-type electrodes, located on one side of the chip body. part of the surface;
  • S2 Provide a second substrate, one side surface of the second substrate has several conductive layers;
  • S3 Form an isolation layer on the second substrate.
  • the isolation layer has several opening groups. Each opening group includes spaced first openings and second openings. The first openings and the second openings are respectively exposed. On the surface of the conductive layer, the width of the first opening is smaller than the width of the P-type electrode, and the width of the second opening is smaller than the width of the N-type electrode;
  • S5 Use the isolation layer to support the chip body, bond the P-type electrode to the first bonding layer, and simultaneously bond the N-type electrode to the second bonding layer. , the P-type electrode is embedded in the first bonding layer, and the N-type electrode is embedded in the second bonding layer.
  • the first opening allows the P-type electrode to enter
  • the second opening allows the N-type electrode to enter.
  • the isolation layer supports the chip body around the P-type electrode, adding a self-alignment function.
  • the Micro-LED chip The lateral offset is limited by the side walls of the first opening and the side walls of the second opening, ensuring bonding stability.
  • the material of the first bonding layer can be confined in the first opening
  • the material of the second bonding layer can be confined in the second opening, reducing the number of materials of the first bonding layer and the second bonding layer during the bonding process.
  • the lateral offset of the material of the layer prevents short circuit between the first bonding layer and the second bonding layer. In summary, bonding failure between the Micro-LED chip and the first bonding layer and the second bonding layer is avoided.
  • a first substrate 300 is provided.
  • One side of the first substrate 300 has several spaced Micro-LED chips.
  • the Micro-LED chip includes: a chip body; a P-type electrode 304 and an N-type electrode 305 located at Part of the surface on one side of the chip body.
  • the chip body includes: an N-type semiconductor layer 301; an active layer 302 located on part of the surface on one side of the N-type semiconductor layer 301; P-type semiconductor layer 303; the P-type electrode 304 is located on a side surface of the P-type semiconductor layer 303 facing away from the active layer 302; the N-type electrode 305 is located on the active layer 302 and P-type semiconductor layer 303 and a portion of the surface of the N-type semiconductor layer 301 side of the P-type electrode 304 .
  • the P-type electrode 304 is located on a side surface of the P-type semiconductor layer 303 away from the active layer 302 , that is, part of the surface of the P-type semiconductor layer 303 is not covered by the P-type electrode 304 .
  • the difference between the total area of the side surface of the P-type semiconductor layer 303 facing away from the active layer 302 and the projected area of the P-type electrode 304 on the surface of the P-type semiconductor layer 303 is 50 ⁇ m 2 to 200 ⁇ m 2 , for example, 50 ⁇ m 2 , 80 ⁇ m 2 , 100 ⁇ m 2 , 120 ⁇ m 2 , 150 ⁇ m 2 , 180 ⁇ m 2 or 200 ⁇ m 2 .
  • the distance between the N-type electrode 305 and the P-type electrode 304 in the Micro-LED chip is 5 microns to 6 microns.
  • a second substrate 201 is provided.
  • One side surface of the second substrate 201 has a plurality of conductive layers 206 .
  • the second substrate 201 is a drive substrate, and the second substrate 201 includes a substrate body and a driver located on one side surface of the substrate body. circuit.
  • the conductive layer is located on a side surface of the driving circuit away from the substrate body, and the conductive layer 206 is electrically connected to the driving circuit.
  • the conductive layer 206 is a contact electrode, and the conductive layer 206 is formed by film formation, photolithography, and etching.
  • the material of the conductive layer 206 includes metal or alloy.
  • the metal is, for example, Al, Ti or Mo.
  • an isolation layer 207 is formed on the second substrate 201 .
  • the isolation layer 207 has several opening groups. Each opening group includes spaced first openings 2071 and second openings 2072 .
  • the first openings 2071 are spaced apart from each other.
  • the opening 2071 and the second opening 2072 respectively expose the surface of the conductive layer 206.
  • the width of the first opening 2071 is smaller than the width of the P-type electrode 304, and the width of the second opening 2072 is smaller than the width of the N-type electrode 305. width.
  • the step of forming the isolation layer 207 includes: forming an initial isolation layer (not shown) covering the conductive layer 206 on the second substrate 201; patterning the initial isolation layer so that the initial isolation layer forms the desired shape.
  • the isolation layer 207 includes: forming an initial isolation layer (not shown) covering the conductive layer 206 on the second substrate 201; patterning the initial isolation layer so that the initial isolation layer forms the desired shape.
  • the thickness of the isolation layer 207 is less than or equal to 50% of the thickness difference between the N-type electrode 305 and the P-type electrode 304 .
  • the thickness of the isolation layer 207 refers to the dimension perpendicular to the surface direction of the second substrate 201; the thickness of the N-type electrode 305 and the thickness of the P-type electrode 304 both refer to the dimension perpendicular to the surface direction of the first substrate.
  • the advantage of this arrangement is that the isolation layer 207 is thinner and saves costs; at the same time, it can ensure better contact between the P-type electrode 304 and the subsequent first bonding layer material, and the N-type electrode 305 and the subsequent second bonding layer. layers of materials for better contact.
  • the thickness of the isolation layer 207 is 500 nm to 1000 nm.
  • the material of the isolation layer 207 includes SiO 2 or Si 3 N 4 .
  • the width of the conductive layer 206 at the bottom of the first opening 2071 is greater than or equal to the width of the first opening 2071
  • the width of the conductive layer 206 at the bottom of the second opening 2072 is greater than or equal to the width of the second opening 2072 .
  • the width of the conductive layer 206 at the bottom of the first opening 2071 is greater than or equal to the sum of the width of the P-type electrode 304 and twice the feature alignment accuracy.
  • the width of the conductive layer 206 at the bottom of the second opening 2072 is greater than or equal to the sum of the width of the N-type electrode 305 and 2 times the feature alignment accuracy. 2 times the sum of feature alignment accuracy.
  • the characteristic alignment accuracy is the alignment accuracy of the binding equipment used in the subsequent bonding process of the P-type electrode 304 and the first bonding layer 2081 and the N-type electrode 305 and the second bonding layer 2082.
  • a first bonding layer 2081 is formed in the first opening 2071, and a second bonding layer 2082 is formed in the second opening 2072.
  • the material of the first bonding layer 2081 and the second bonding layer 2082 is solder, and the solder includes In solder or tin-containing lead-free solder.
  • the material of the first bonding layer 2081 and the second bonding layer 2082 is conductive glue, and the conductive glue is anisotropic conductive glue.
  • the melting point of the first bonding layer 2081 is lower than the melting point of the conductive layer 206 and lower than the melting point of the isolation layer 207 .
  • the melting point of the second bonding layer 2082 is lower than the melting point of the conductive layer 206 and lower than the melting point of the isolation layer 207 .
  • the thickness of the first bonding layer 2081 is greater than or equal to the depth of the first opening 2071
  • the thickness of the second bonding layer 2082 is greater than or equal to 80% of the depth of the second opening 2072 and less than or equal to the depth of the second opening 2072 .
  • the material of the first bonding layer 2081 can surround the P-type electrode
  • the material of the second bonding layer 2082 can surround the N-type electrode, and prevent the material of the first bonding layer 2081 and the third The material of the second bonding layer 2082 overflows and causes a short circuit.
  • the thickness of the first bonding layer 2081 is 400nm-800nm
  • the thickness of the second bonding layer 2082 is 400nm-800nm.
  • the isolation layer 207 is used to support the chip body, the P-type electrode 304 is bonded to the first bonding layer 2081, and the N-type electrode 305 is bonded to the second bonding layer 2081.
  • the bonding layer 2082 performs bonding, the P-type electrode 304 is embedded in the first bonding layer 2081 , and the N-type electrode 305 is embedded in the second bonding layer 2082 .
  • the P-type electrode 304 is bonded to the first bonding layer 2081 by the isolation layer 207.
  • the P-type semiconductor layer 303 around the type electrode 304 serves as a support.
  • the binding equipment used has characteristic alignment accuracy; the first The width of the opening 2071 is greater than or equal to the sum of the width of the P-type electrode 304 and 2 times the feature alignment accuracy.
  • the width of the second opening 2072 is greater than or equal to the sum of the width of the N-type electrode 305 and 2 times the feature alignment accuracy.
  • the feature alignment accuracy is 0.5 ⁇ m to 2 ⁇ m.
  • the P-type electrode 304 is bonded to the first bonding layer 2081 , and the N-type electrode 305 is Reflow soldering is used for bonding with the second bonding layer 2082 .
  • the material of the first bonding layer 2081 and the second bonding layer 2082 is conductive glue
  • the P-type electrode 304 and the first bonding layer 2081 are extruded, and the P-type electrode 304 and the first bonding layer
  • the conductive particles in 2081 are interconnected, the N-type electrode 305 and the second bonding layer 2082 are squeezed, and the N-type electrode 305 and the conductive particles in the second bonding layer 2082 are interconnected.
  • the first opening 2071 allows the P-type electrode 304 to enter, and the second opening 2072 allows the N-type electrode 305 to enter.
  • the isolation layer 207 supports the P-type semiconductor layer 303 around the P-type electrode 304 . This not only increases the self-alignment function, but also ensures to a certain extent the flatness of the top surfaces of all Micro-LED chips facing away from the second substrate, thereby enhancing the consistency of the light emission angles of the Micro-LED chips; and Micro -The effective light-emitting area of the LED chip increases.
  • the Micro-LED chip and the first substrate 300 are debonded.
  • ultraviolet light irradiation is used to debond the first substrate 300 and the Micro-LED chip.
  • Figure 11 is a schematic diagram based on Figure 7.
  • a first slope A1 is formed at the junction between the side wall of the first opening 2071 and the top surface of the isolation layer 207 around the first opening 2071; in the The junction between the side walls of the two openings 2072 and the top surface of the isolation layer 207 around the second opening 2072 forms a second slope surface A2.
  • ⁇ 1 is the first included angle
  • ⁇ 1 is the friction coefficient of the first slope surface
  • the advantage of setting the above-mentioned first included angle and the second included angle is to ensure that the P-type electrode 304 of the Micro-LED chip can automatically enter the first opening, and the N-type electrode 305 of the Micro-LED chip can automatically enter the second opening. , reducing yield loss to a certain extent.
  • a first bonding layer 2081a is formed in the first opening 2071; after forming the second slope surface A2, a second bonding layer 2082a is formed in the second opening 2072.
  • the isolation layer 207 is used to support the chip body, the P-type electrode 304 is bonded to the first bonding layer 2081a, and the N-type electrode 305 is bonded to the second bonding layer 2081a.
  • the bonding layer 2082a is bonded, the P-type electrode 304 is embedded in the first bonding layer 2081a, and the N-type electrode 305 is embedded in the second bonding layer 2082a; after that, the Micro-LED chip and the first substrate are 300 debonding.
  • Figure 14 is a schematic diagram based on Figure 7.
  • a barrier layer 211 is formed on the isolation layer 207 around the opening group.
  • the barrier layer 211 has a third opening, and the width of the third opening is greater than The width of the Micro-LED chip.
  • the material of the barrier layer 211 is a light-shielding resin, and the light-shielding resin is a resin with a light-shielding effect.
  • the material of the barrier layer 211 is not limited to this material.
  • the width of the third opening should be slightly larger than that of the Micro-LED chip. The width size ensures that the Micro-LED chip can smoothly fall into the third opening. A third opening corresponds to a Micro-LED chip.
  • the functions of the barrier layer 211 include: limiting the position of the Micro-LED chip, and a Micro-LED chip falls into a third opening.
  • the blocking layer 211 is a light-shielding blocking layer.
  • the blocking layer 211 is used to block crosstalk between light emitted by adjacent Micro-LED chips.
  • the material of the light-shielding blocking layer may be, for example, light-shielding resin.
  • the barrier layer 211 may also be made of non-light-shielding material.
  • the width of the third opening is greater than the width of the Micro-LED chip and less than or equal to 1.5 times the width of the Micro-LED chip.
  • the barrier layer 211 is a light-shielding barrier layer. After bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the barrier layer 211 The height of the top surface on the side facing away from the second substrate is greater than the height of the top surface on the side of the Micro-LED chip facing away from the second substrate. The advantage of this setting is that it can better avoid crosstalk between the light emitted by adjacent Micro-LED chips.
  • the barrier layer 211 is away from the second bonding layer.
  • the height of the top surface on one side of the substrate is less than or equal to the height of the top surface of the Micro-LED chip away from the second substrate.
  • the method further includes: forming a first slope surface at the interface between the side wall of the first opening 2071 and the top surface of the isolation layer 207 around the first opening 2071; The junction between the top surfaces of the isolation layer 207 around the two openings 2072 forms a second slope surface. After forming the first slope surface and the second slope surface, the barrier layer 211 is formed.
  • the description of the first slope surface and the second slope surface refers to the previous embodiment and will not be described in detail.
  • the first slope surface and the second slope surface may not be provided.
  • a first bonding layer 2081b is formed in the first opening 2071; a second bonding layer 2082b is formed in the second opening 2072.
  • the barrier layer 211 is formed, the first bonding layer 2081b and the second bonding layer 2082b are formed. In other embodiments, the barrier layer 211 may be formed after forming the first bonding layer 2081b and the second bonding layer 2082b.
  • the isolation layer 207 is used to support the chip body, and the P-type electrode 304 and the first bonding layer 2081b are While bonding, the N-type electrode 305 is bonded to the second bonding layer 2082b, the P-type electrode 304 is embedded in the first bonding layer 2081b, and the N-type electrode 305 is embedded in the second bonding layer 2082b. .
  • This embodiment provides a display panel, referring to Figure 10, including:
  • the Micro-LED chip includes: a chip body; P-type electrode 304 and N-type electrode 305, located on part of the surface on one side of the chip body;
  • the second substrate 201 has a plurality of conductive layers 206 on one side surface of the second substrate 201;
  • the isolation layer 207 is located on one side of the second substrate 201.
  • the isolation layer 207 has several opening groups. Each opening group includes spaced first openings and second openings. The first openings and the second openings are spaced apart. The openings are respectively located on the conductive layer 206, the width of the first opening is smaller than the width of the P-type electrode 304, and the width of the second opening is smaller than the width of the N-type electrode 305;
  • the P-type electrode 304 is embedded in the first bonding layer, and the N-type electrode 305 is embedded in the second bonding layer; the chip body is in contact with the top surface of part of the isolation layer 207 .
  • the chip body includes: an N-type semiconductor layer 301; an active layer 302 located on part of the surface on one side of the N-type semiconductor layer 301; P-type semiconductor layer 303; the P-type electrode 304 is located on a side surface of the P-type semiconductor layer 303 facing away from the active layer 302; the N-type electrode 305 is located on the active layer 302 and P-type semiconductor layer 303 and a portion of the surface of the N-type semiconductor layer 301 side of the P-type electrode 304 .
  • the P-type semiconductor layer 303 around the P-type electrode 304 is in contact with the top surface of the isolation layer 207 around the first opening.
  • the width of the first opening is greater than or equal to the sum of the width of the P-type electrode 304 and 2 times the feature alignment accuracy
  • the width of the second opening is greater than or equal to the N-type electrode.
  • the sum of 305 and 2 times the feature alignment accuracy is 0.5 ⁇ m to 2 ⁇ m.
  • the thickness of the first bonding layer is greater than or equal to 80% of the depth of the first opening and less than or equal to the depth of the first opening
  • the thickness of the second bonding layer is greater than or equal to the second 80% of the depth of the opening and less than or equal to the depth of the second opening.
  • the thickness of the isolation layer 207 is less than or equal to 50% of the thickness difference between the N-type electrode and the P-type electrode.
  • the thickness of the isolation layer 207 is 500 nm to 1000 nm.
  • the material of the first bonding layer and the second bonding layer is solder; the material of the first bonding layer and the second bonding layer is conductive glue.
  • ⁇ 1 is the first included angle
  • ⁇ 1 is the friction coefficient of the first slope surface
  • the included angle, ⁇ 2, is the friction coefficient of the second slope surface.
  • the display panel further includes: a barrier layer 211 located on the isolation layer 207 around the opening group, and the barrier layer 211 has a third opening, so The width of the third opening is greater than the width of the Micro-LED chip.
  • the width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.
  • the blocking layer 211 is a light-shielding blocking layer.
  • the material of the light-shielding blocking layer is light-shielding resin.
  • the material of the barrier layer 211 may also be a non-light-shielding material.
  • the barrier layer 211 is a light-shielding barrier layer, and the height of the top surface of the barrier layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate. The height of the surface.
  • a height of the top surface of the barrier layer facing away from the second substrate is less than or equal to a height of the top surface of the Micro-LED chip facing away from the second substrate.
  • the display panel further includes: a barrier layer located on the isolation layer around the opening group, the barrier layer has a third opening, and the width of the third opening is greater than The width of the Micro-LED chip. In one embodiment, the width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.
  • the blocking layer 211 is a light-shielding blocking layer.
  • the material of the light-shielding blocking layer is light-shielding resin.
  • the material of the barrier layer 211 may also be a non-light-shielding material.
  • the barrier layer 211 is a light-shielding barrier layer, and the height of the top surface of the barrier layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate. The height of the surface. In another embodiment, a height of the top surface of the barrier layer facing away from the second substrate is less than or equal to a height of the top surface of the Micro-LED chip facing away from the second substrate.

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Abstract

一种显示面板及其制备方法，制备方法包括：提供第一基板（300），第一基板（300）的一侧有若干间隔的Micro-LED芯片；提供第二基板（201），第二基板（201）的一侧表面有若干导电层（206）；在第二基板（201）上形成隔离层（207），隔离层（207）中有若干开口组，每个开口组均包括暴露出导电层（206）的表面的第一开口（2071）和第二开口（2072），第一开口（2071）的宽度大于P型电极（304）的宽度，第二开口（2072）的宽度大于N型电极（305）的宽度；在第一开口（2071）中形成第一键合层（2081），在第二开口（2072）中形成第二键合层（2082）；以隔离层（207）对芯片本体支撑，将P型电极（304）与第一键合层（2081）进行键合的同时将N型电极（305）与第二键合层（2082）进行键合，P型电极（304）嵌入第一键合层（2081）中，N型电极（305）嵌入第二键合层（2082）中。

Description

一种显示面板及其制备方法
相关申请的交叉引用
本申请要求在2022年08月29日提交中国专利局、申请号为202211043484.9、发明名称为“一种显示面板及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及其制备方法。
背景技术
发光二极管(Light Emitting Diode，LED)是一种重要的光电半导体元件。发光二极管具有低功耗、尺寸小、亮度高、易与集成电路匹配、可靠性高等优点，因而作为光源被广泛应用。随着技术的发展，Micro-LED已经在显示、光通信、室内定位、生物和医疗领域获得了相关的应用，并有望进一步扩展到可穿戴/可植入器件、增强现实/虚拟现实、车载显示、超大型显示以及光通信/光互联、医疗探测、智能车灯、空间成像等多个领域，具有明确可观的市场前景。Micro-LED芯片运用到显示技术上，则需要把数百万甚至数千万颗Micro-LED芯片准确且有效率的移动到显示面板上，以一个4K电视为例，需要转移的Micro-LED芯片就高达2400万颗(以4000×2000×R/G/B三色计算)，即使一次转移1万颗Micro-LED芯片，也需要重复2400次。
然而，现有技术存在Micro-LED芯片和基板键合位置的准确度较差，造成Micro-LED芯片和键合层之间键合失效。
发明内容
因此，本申请要解决的技术问题在于克服现有技术中Micro-LED芯片和键合层之间键合失效的问题，从而提供一种显示面板及其制备方法。
本申请提供一种显示面板的制备方法，包括：提供第一基板，所述第一基板的一侧具有若干间隔的Micro-LED芯片，所述Micro-LED芯片包括：芯片本体；P型电极和N型电极，位于所述芯片本体一侧的部分表面；提供第二基板，所述第二基板的一侧表面具有若干导电层；在所述第二基板上形成隔离层，所述隔离层中具有若干开口组，每个开口组均包括间隔的第一开口和第二开口，所述第一开口和第二开口分别暴露出导电层的表面，所述第一开口的宽度小于所述P型电极的宽度，所述第二开口的宽度小于所述N型电极的宽度；在第一开口中形成第一键合层，在第二开口中形成第二键合层；以所述隔离层对所述芯片本体支撑，将所述P型电极与所述第一键合层进行键合的同时将所述N型电极与所述第二键合层进行键合，所述P型电极嵌入第一键合层中，所述N型电极嵌 入第二键合层中。
可选的，所述芯片本体包括：N型半导体层；位于所述N型半导体层一侧的部分表面的有源层；位于所述有源层背离所述N型半导体层一侧表面的P型半导体层；所述P型电极位于部分所述P型半导体层背离所述有源层的一侧表面；所述N型电极位于有源层、P型半导体层和P型电极的侧部的所述N型半导体层一侧的部分表面；将所述P型电极与第一键合层进行键合、以及将所述N型电极与第二键合层进行键合的过程中，以所述隔离层对所述P型电极周围的所述P型半导体层为支撑。
可选的，还包括：在第一开口中形成第一键合层之前，在第一开口的侧壁和第一开口周围的隔离层的顶面之间的交界处形成第一斜坡面；在第二开口中形成第二键合层之前，在第二开口的侧壁和第二开口周围的隔离层的顶面之间的交界处形成第二斜坡面。
可选的，与第一斜坡面连接的隔离层的顶面和所述第一斜坡面之间具有第一夹角；tan(180°-θ1)>μ1，θ1为第一夹角，μ1为第一斜坡面的摩擦系数。
可选的，与第二斜坡面连接的隔离层的顶面和所述第二斜坡面之间具有第二夹角；tan(180°-θ2)>μ2；θ2为第二夹角，μ2为第二斜坡面的摩擦系数。
可选的，还包括：将所述P型电极与第一键合层、所述N型电极与第二键合层进行键合之前，在所述开口组周围的隔离层上形成阻挡层，所述阻挡层中具有第三开口，所述第三开口的宽度大于所述Micro-LED芯片的宽度。
可选的，所述第三开口的宽度小于或等于所述Micro-LED芯片的宽度的1.5倍。
可选的，所述阻挡层为遮光阻挡层。
可选的，所述遮光阻挡层的材料为遮光树脂。
可选的，将所述P型电极与第一键合层、所述N型电极与第二键合层进行键合之后，所述阻挡层背离所述第二基板一侧的顶面的高度大于所述Micro-LED芯片背离所述第二基板一侧的顶面的高度。
可选的，将所述P型电极与第一键合层、所述N型电极与第二键合层进行键合的过程中，采用的绑定设备具有特征对位精度；所述第一开口的宽度大于或等于所述P型电极的宽度与2倍的所述特征对位精度之和，所述第二开口的宽度大于或等于所述N型电极与2倍的所述特征对位精度之和。
可选的，在第一开口中形成第一键合层，在第二开口中形成第二键合层的步骤中，所述第一键合层的厚度大于或等于第一开口的深度的80％且小于或等于第一开口的深度，所述第二键合层的厚度大于或等于第二开口的深度的80％且小于或等于第二开口的深度。
可选的，所述隔离层的厚度小于或等于所述N型电极与所述P型电极的厚度差的50％。
可选的，所述隔离层的厚度为500nm～1000nm。
可选的，所述第一键合层和所述第二键合层的材料为焊料；所述第一键合层和所述第二键合层的材料为导电胶。
本申请还提供一种显示面板，包括：第一基板，所述第一基板的一侧具有若干间隔的Micro-LED芯片，所述Micro-LED芯片包括：芯片本体；P型电极和N型电极，位于所述芯片本体一侧的部分表面；第二基板，所述第二基板的一侧表面具有若干导电层；位于所述第二基板的一侧的隔离层，所述隔离层中具有若干开口组，每个开口组均包括间隔的第一开口和第二开口，所述第一开口和第二开口分别位于导电层上，所述第一开口的宽度小于所述P型电极的宽度，所述第二开口的宽度小于所述N型电极的宽度；位于第一开口中的第一键合层；位于第二开口中的第二键合层；所述P型电极嵌入第一键合层中，所述N型电极嵌入第二键合层中；所述芯片本体与部分隔离层的顶面接触。
可选的，所述芯片本体包括：N型半导体层；位于所述N型半导体层一侧的部分表面的有源层；位于所述有源层背离所述N型半导体层一侧表面的P型半导体层；所述P型电极位于部分所述P型半导体层背离所述有源层的一侧表面；所述N型电极位于有源层、P型半导体层和P型电极的侧部的所述N型半导体层一侧的部分表面；所述P型电极周围的所述P型半导体层与第一开口周围的隔离层的顶面接触。
可选的，第一开口的侧壁和第一开口周围的隔离层的顶面之间具有第一斜坡面；在第二开口的侧壁和第二开口周围的隔离层的顶面之间具有第二斜坡面。
可选的，与第一斜坡面连接的隔离层的顶面和所述第一斜坡面之间具有第一夹角；tan(180°-θ1)>μ1，θ1为第一夹角，μ1为第一斜坡面的摩擦系数。
可选的，与第二斜坡面连接的隔离层的顶面和所述第二斜坡面之间具有第二夹角；tan(180°-θ2)>μ2；θ2为第二夹角，μ2为第二斜坡面的摩擦系数。
可选的，还包括：阻挡层，位于所述开口组周围的隔离层上，所述阻挡层中具有第三开口，所述第三开口的宽度大于所述Micro-LED芯片的宽度。
可选的，所述第三开口的宽度小于或等于所述Micro-LED芯片的宽度的1.5倍。
可选的，所述阻挡层为遮光阻挡层。
可选的，所述遮光阻挡层的材料为遮光树脂。
可选的，将所述P型电极与第一键合层、所述N型电极与第二键合层进行键合之后，所述阻挡层背离所述第二基板一侧的顶面的高度大于所述Micro-LED芯片背离所述第二基板一侧的顶面的高度。
可选的，所述第一开口的宽度大于或等于所述P型电极的宽度与2倍的特征对位精度之和，所述第二开口的宽度大于或等于所述N型电极与2倍的特征对位精度之和，所述特征对位精度为0.5μm～2μm。
可选的，所述第一键合层的厚度大于或等于第一开口的深度的80％且小于或等于第一开口的深度，所述第二键合层的厚度大于或等于第二开口的深度的80％且小于或等于第二开口的深度。
可选的，所述隔离层的厚度小于或等于所述N型电极与所述P型电极的厚度差的50％。
可选的，所述隔离层的厚度为500nm～1000nm。
可选的，所述第一键合层和所述第二键合层的材料为焊料；所述第一键合层和所述第二键合层的材料为导电胶。
本申请的技术方案具有以下有益效果：
本申请技术方案提供的显示面板的制备方法，以所述隔离层对所述芯片本体支撑，将所述P型电极与所述第一键合层进行键合的同时将所述N型电极与所述第二键合层进行键合，所述P型电极嵌入第一键合层中，所述N型电极嵌入第二键合层中。第一开口允许P型电极进入，第二开口允许N型电极进入，所述隔离层对所述P型电极周围的芯片本体支撑，增加了自对位功能，Micro-LED芯片的在横向偏移量受到第一开口的侧壁和第二开口的侧壁的限制，保证了键合的稳定性。其次，第一键合层的材料能限制在第一开口中，第二键合层的材料能限制在第二开口中，减少在键合过程中第一键合层的材料和第二键合层的材料的横向偏移，避免第一键合层和第二键合层发生短路。综上，避免Micro-LED芯片与第一键合层、第二键合层之间键合失效。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1至图2为一种显示面板的制备过程的示意图；
图3至图4为另一种显示面板的制备过程的示意图；
图5至图10为本申请一实施例提供的显示面板的制备过程的示意图；
图11至图13为本申请另一实施例提供的显示面板的制备过程的示意图；
图14至图16为本申请另一实施例提供的显示面板的制备过程的示意图。
具体实施方式
正如背景技术所述，现有技术存在Micro-LED芯片和基板键合位置的准确度较差，造成键合失效。
一种显示面板的制备方法，包括：参考图1，提供第一基板101，所述第一基板上具有导电柱 102，导电柱102背离所述第一基板101的表面设置有焊料103；提供第二基板105，第二基板105的一侧表面具有若干间隔的Micro-LED芯片104；将第二基板105和第一基板101相对设置，Micro-LED芯片104的电极朝向焊料103；参考图2，将Micro-LED芯片104的电极与焊料103焊接。
然而，将Micro-LED芯片104的电极与焊料103焊接在一起的过程中，Micro-LED芯片104的电极与焊料103会产生一定的偏离，造成虚焊甚至短路，经研究发现，原因在于：1.在Micro-LED芯片104的电极与焊料103对位的过程中，受到对位设备的对位精度的限制；2.将Micro-LED芯片104的电极与焊料103的焊接采用的是回流焊，在回流焊的过程中焊料103会熔化，Micro-LED芯片104的电极相对于焊料103的位置偏移；3.将Micro-LED芯片104的电极与焊料103焊接在一起采用的共晶真空炉不具备压力系统，无法保证Micro-LED芯片104与焊料103的相对位置不变。
另一种显示面板的制备方法，参考图3，提供第一基板101a，所述第一基板101a的表面具有若干电极(未图示)，所述电极的表面具有导电胶体102a，导电胶体102a内部具有导电粒子106；参考图3，提供第二基板105，第二基板105的一侧表面具有若干间隔的Micro-LED芯片104，Micro-LED芯片104包括P型电极和N型电极；参考图4，将第二基板105和第一基板101a相对设置，将Micro-LED芯片104的P型电极与部分导电胶体102a键合在一起，将Micro-LED芯片104的N型电极与部分导电胶体102a键合在一起。
然而，将Micro-LED芯片104的N型电极与部分导电胶体102a键合在一起的过程中，当N型电极和P型电极之间的间距较小时，容易导致N型电极和P型电极之间短路。
上述方法中，Micro-LED芯片104的电极与键合层(焊料103或导电胶体102a)均键合失效的风险较大。
本申请提供一种显示面板及其制备方法，能避免Micro-LED芯片和键合层之间键合失效。
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，还可以是两个元件内部的连通，可以是无线连接，也可以是有线连接。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
实施例1
本申请一实施例提供一种显示面板的制备方法，包括：
S1:提供第一基板，所述第一基板的一侧具有若干间隔的Micro-LED芯片，所述Micro-LED芯片包括：芯片本体；P型电极和N型电极，位于所述芯片本体一侧的部分表面；
S2:提供第二基板，所述第二基板的一侧表面具有若干导电层；
S3:在所述第二基板上形成隔离层，所述隔离层中具有若干开口组，每个开口组均包括间隔的第一开口和第二开口，所述第一开口和第二开口分别暴露出导电层的表面，所述第一开口的宽度小于所述P型电极的宽度，所述第二开口的宽度小于所述N型电极的宽度；
S4:在第一开口中形成第一键合层，在第二开口中形成第二键合层；
S5:以所述隔离层对所述芯片本体支撑，将所述P型电极与所述第一键合层进行键合的同时将所述N型电极与所述第二键合层进行键合，所述P型电极嵌入第一键合层中，所述N型电极嵌入第二键合层中。
本实施例中，第一开口允许P型电极进入，第二开口允许N型电极进入，所述隔离层对所述P型电极周围的芯片本体支撑，增加了自对位功能，Micro-LED芯片的在横向偏移量受到第一开口的侧壁和第二开口的侧壁的限制，保证了键合的稳定性。其次，第一键合层的材料能限制在第一开口中，第二键合层的材料能限制在第二开口中，减少在键合过程中第一键合层的材料和第二键合层的材料的横向偏移，避免第一键合层和第二键合层发生短路。综上，避免Micro-LED芯片与第一键合层、第二键合层之间键合失效。
下面结合图5至图10进行详细的说明。
参考图5,提供第一基板300，所述第一基板300的一侧具有若干间隔的Micro-LED芯片，所述Micro-LED芯片包括：芯片本体；P型电极304和N型电极305，位于所述芯片本体一侧的部分表面。
所述芯片本体包括：N型半导体层301；位于所述N型半导体层301一侧的部分表面的有源层302；位于所述有源层302背离所述N型半导体层301一侧表面的P型半导体层303；所述P型电极304位于部分所述P型半导体层303背离所述有源层302的一侧表面；所述N型电极305位于有源层302、P型半导体层303和P型电极304的侧部的所述N型半导体层301一侧的部分表面。
本实施例中，所述P型电极304位于部分所述P型半导体层303背离所述有源层302的一侧表面，也就是P型半导体层303的部分表面没有被P型电极304覆盖。
在一个实施例中，P型半导体层303背离有源层302的一侧表面的总面积与P型电极304在P型半导体层303表面的投影面积之差为50μm2～200μm2，例如50μm2、80μm2、100μm2、120μm2、150μm2、180μm2或200μm2。
在一个实施例中，Micro-LED芯片中的N型电极305和P型电极304之间的间距为5微米～6微米。
参考图6,提供第二基板201，所述第二基板201的一侧表面具有若干导电层206。
所述第二基板201为驱动基板，所述第二基板201包括基板本体和位于基板本一侧表面的驱动 电路。导电层位于驱动电路背离基板本体的一侧表面，所述导电层206与所述驱动电路电连接。
导电层206为接触电极，所述导电层206通过成膜、光刻和刻蚀而形成。所述导电层206的材料包括金属或者合金，金属例如为Al、Ti或Mo。
参考图7,在所述第二基板201上形成隔离层207，所述隔离层207中具有若干开口组，每个开口组均包括间隔的第一开口2071和第二开口2072，所述第一开口2071和第二开口2072分别暴露出导电层206的表面，所述第一开口2071的宽度小于所述P型电极304的宽度，所述第二开口2072的宽度小于所述N型电极305的宽度。
形成所述隔离层207的步骤包括：所述第二基板201上形成覆盖所述导电层206的初始隔离层(未图示)；对所述初始隔离层进行图形化，使初始隔离层形成所述隔离层207。
在一个实施例中，所述隔离层207的厚度小于或等于所述N型电极305与所述P型电极304的厚度差的50％。隔离层207的厚度指的是垂直于第二基板201的表面方向上的尺寸；N型电极305的厚度、P型电极304的厚度均指的是垂直于第一基板的表面方向上的尺寸。这样设置的好处在于：隔离层207的厚度较薄，节省成本；同时能够保证P型电极304与后续的第一键合层的材料更好的接触，N型电极305与后续的第二键合层的材料更好的接触。
在一个具体的实施例中，所述隔离层207的厚度为500nm～1000nm。
所述隔离层207的材料包括SiO2或Si3N4。
第一开口2071底部的导电层206的宽度大于或等于第一开口2071的宽度，第二开口2072底部的导电层206的宽度大于或等于第二开口2072的宽度。第一开口2071底部的导电层206的宽度大于或等于P型电极304的宽度与2倍的特征对位精度之和，第二开口2072底部的导电层206的宽度大于或等于N型电极305与2倍的特征对位精度之和。特征对位精度为后续将所述P型电极304与第一键合层2081、所述N型电极305与第二键合层2082进行键合的过程中采用的绑定设备的对位精度。
参考图8,在第一开口2071中形成第一键合层2081，在第二开口2072中形成第二键合层2082。
在一个实施例中，所述第一键合层2081和所述第二键合层2082的材料为焊料，焊料包括In焊料或含锡的无铅焊料。
在另一个实施例中，所述第一键合层2081和所述第二键合层2082的材料为导电胶，所述导电胶为各向异性导电胶。
所述第一键合层2081的熔点小于导电层206的熔点且小于隔离层207的熔点。所述第二键合层2082的熔点小于导电层206的熔点且小于隔离层207的熔点。
在第一开口2071中形成第一键合层2081，在第二开口2072中形成第二键合层2082的步骤中，所述第一键合层2081的厚度大于或等于第一开口2071的深度的80％且小于或等于第一开口2071的深度，所述第二键合层2082的厚度大于或等于第二开口2072的深度的80％且小于或等于第二开口2072的深度。这样使得后续进行键合的过程中，第一键合层2081的材料能包围P型电极，第二键合层2082的材料能包围N型电极，且防止第一键合层2081的材料和第二键合层2082的材料的溢出而短路。
在一个具体的实施例中，第一键合层2081的厚度为400nm～800nm，第二键合层2082的厚度为400nm～800nm。
参考图9,以所述隔离层207对所述芯片本体支撑，将所述P型电极304与所述第一键合层2081进行键合的同时将所述N型电极305与所述第二键合层2082进行键合，所述P型电极304嵌入第一键合层2081中，所述N型电极305嵌入第二键合层2082中。
将所述P型电极304与第一键合层2081进行键合、以及将所述N型电极305与第二键合层2082进行键合的过程中，以所述隔离层207对所述P型电极304周围的所述P型半导体层303为支撑。
将所述P型电极304与第一键合层2081、所述N型电极305与第二键合层2082进行键合的过程中，采用的绑定设备具有特征对位精度；所述第一开口2071的宽度大于或等于所述P型电极304的宽度与2倍的所述特征对位精度之和，所述第二开口2072的宽度大于或等于所述N型电极305与2倍的所述特征对位精度之和。在一个实施例中，所述特征对位精度为0.5μm～2μm。
当所述第一键合层2081和所述第二键合层2082的材料为焊料时，将所述P型电极304与第一键合层2081进行键合、以及将所述N型电极305与第二键合层2082进行键合采用回流焊。
当所述第一键合层2081和所述第二键合层2082的材料为导电胶时，将P型电极304与第一键合层2081挤压，P型电极304与第一键合层2081中的导电粒子进行互联，将N型电极305与第二键合层2082挤压，N型电极305与第二键合层2082中的导电粒子进行互联。
第一开口2071允许P型电极304进入，第二开口2072允许N型电极305进入，所述隔离层207对所述P型电极304周围的所述P型半导体层303为支撑。这样不仅增加了自对位功能，还能一定程度上保证所有Micro-LED芯片背离所述第二基板一侧的顶面的平整性，使得Micro-LED芯片的出光角度的一致性增强；且Micro-LED芯片的有效发光面积增加。
参考图10,将Micro-LED芯片与第一基板300解键合。
在一个具体的实施例中，采用紫外光照射的方式将第一基板300和Micro-LED芯片解键合。
实施例2
参考图11,图11为在图7基础上的示意图，在第一开口2071的侧壁和第一开口2071周围的隔离层207的顶面之间的交界处形成第一斜坡面A1；在第二开口2072的侧壁和第二开口2072周围的隔离层207的顶面之间的交界处形成第二斜坡面A2。
在一个实施例中，与第一斜坡面A1连接的隔离层207的顶面和所述第一斜坡面A1之间具有第一夹角；tan(180°-θ1)>μ1，θ1为第一夹角，μ1为第一斜坡面的摩擦系数。
在一个实施例中，与第二斜坡面A2连接的隔离层207的顶面和所述第二斜坡面A2之间具有第二夹角；tan(180°-θ2)>μ2；θ2为第二夹角，μ2为第二斜坡面的摩擦系数。
上述第一夹角和第二夹角的设置的好处在于：保证Micro-LED芯片的P型电极304能够自动进入第一开口中，Micro-LED芯片的N型电极305能够自动进入第二开口中，一定程度上减少良率损失。
参考图12,形成第一斜坡面A1之后，在第一开口2071中形成第一键合层2081a；形成第二斜坡面A2之后，在第二开口2072中形成第二键合层2082a。
参考图13,以所述隔离层207对所述芯片本体支撑，将所述P型电极304与所述第一键合层2081a进行键合的同时将所述N型电极305与所述第二键合层2082a进行键合，所述P型电极304嵌入第一键合层层2081a中，所述N型电极305嵌入第二键合层2082a中；之后，将Micro-LED芯片与第一基板300解键合。
实施例3
参考图14,图14为在图7基础上的示意图，在所述开口组周围的隔离层207上形成阻挡层211，所述阻挡层211中具有第三开口，所述第三开口的宽度大于Micro-LED芯片的宽度。
在一个实施例中，阻挡层211的材料是遮光树脂，遮光树脂为带有遮光效果的树脂，但阻挡层211的材料不局限于此材料，第三开口的宽度应略大于Micro-LED芯片的宽度尺寸，保证Micro-LED芯片能够顺利掉落第三开口。一个第三开口对应一个Micro-LED芯片。
所述阻挡层211的作用包括：限制Micro-LED芯片的位置，一个Micro-LED芯片落入一个第三开口中。
在一个实施例中，所述阻挡层211为遮光阻挡层。所述阻挡层211用于阻挡相邻的Micro-LED芯片发出的光之间的串扰。遮光阻挡层的材料例如可以为遮光树脂。
所述阻挡层211还可以选择非遮光材料。
在一个实施例中，所述第三开口的宽度大于Micro-LED芯片的宽度且小于或等于所述Micro-LED芯片的宽度的1.5倍。
在一个实施例中，所述阻挡层211为遮光阻挡层，将所述P型电极与第一键合层、所述N型电极与第二键合层进行键合之后，所述阻挡层211背离所述第二基板一侧的顶面的高度大于所述Micro-LED芯片背离所述第二基板一侧的顶面的高度。这样设置的好处在于：能够更好的避免相邻的Micro-LED芯片发出的光相互间的串扰。
需要说明的是，在其他实施例中，将所述P型电极与第一键合层、所述N型电极与第二键合层进行键合之后，所述阻挡层211背离所述第二基板一侧的顶面的高度小于或等于所述Micro-LED芯片背离所述第二基板一侧的顶面的高度。
本实施例中，还包括：在第一开口2071的侧壁和第一开口2071周围的隔离层207的顶面之间的交界处形成第一斜坡面；在第二开口2072的侧壁和第二开口2072周围的隔离层207的顶面之间的交界处形成第二斜坡面。形成第一斜坡面和第二斜坡面之后，形成阻挡层211。第一斜坡面和第二斜坡面的描述参照前述实施例，不再详述。
需要说明的是，在其他实施例中，在形成阻挡层211的情况下，可以不设置第一斜坡面和第二斜坡面。
参考图15,在第一开口2071中形成第一键合层2081b；在第二开口2072中形成第二键合层2082b。
本实施例中，在形成阻挡层211之后，形成第一键合层2081b和第二键合层2082b。在其他实施例中，可以是：形成第一键合层2081b和第二键合层2082b之后，形成阻挡层211。
参考图16,以所述隔离层207对所述芯片本体支撑，将P型电极304与所述第一键合层2081b 进行键合的同时将N型电极305与第二键合层2082b进行键合，所述P型电极304嵌入第一键合层2081b中，所述N型电极305嵌入第二键合层2082b中。
实施例4
本实施例提供一种显示面板，参考图10,包括：
若干间隔的Micro-LED芯片，所述Micro-LED芯片包括：芯片本体；P型电极304和N型电极305，位于所述芯片本体一侧的部分表面；
第二基板201，所述第二基板201的一侧表面具有若干导电层206；
位于所述第二基板201的一侧的隔离层207，所述隔离层207中具有若干开口组，每个开口组均包括间隔的第一开口和第二开口，所述第一开口和第二开口分别位于导电层206上，所述第一开口的宽度小于所述P型电极304的宽度，所述第二开口的宽度小于所述N型电极305的宽度；
位于第一开口中的第一键合层；
位于第二开口中的第二键合层；
所述P型电极304嵌入第一键合层中，所述N型电极305嵌入第二键合层中；所述芯片本体与部分隔离层207的顶面接触。
所述芯片本体包括：N型半导体层301；位于所述N型半导体层301一侧的部分表面的有源层302；位于所述有源层302背离所述N型半导体层301一侧表面的P型半导体层303；所述P型电极304位于部分所述P型半导体层303背离所述有源层302的一侧表面；所述N型电极305位于有源层302、P型半导体层303和P型电极304的侧部的所述N型半导体层301一侧的部分表面。所述P型电极304周围的所述P型半导体层303与第一开口周围的隔离层207的顶面接触。
在一个实施例中，所述第一开口的宽度大于或等于所述P型电极304的宽度与2倍的特征对位精度之和，所述第二开口的宽度大于或等于所述N型电极305与2倍的特征对位精度之和，所述特征对位精度为0.5μm～2μm。
在一个实施例中，所述第一键合层的厚度大于或等于第一开口的深度的80％且小于或等于第一开口的深度，所述第二键合层的厚度大于或等于第二开口的深度的80％且小于或等于第二开口的深度。
在一个实施例中，所述隔离层207的厚度小于或等于所述N型电极与所述P型电极的厚度差的50％。
在一个实施例中，所述隔离层207的厚度为500nm～1000nm。
所述第一键合层和所述第二键合层的材料为焊料；所述第一键合层和所述第二键合层的材料为导电胶。
实施例5
本实施例与实施例4的区别在于；参考图13，第一开口的侧壁和第一开口周围的隔离层207的顶面之间具有第一斜坡面A1(参考图12)；在第二开口的侧壁和第二开口周围的隔离层207的顶面之间具有第二斜坡面A2(参考图12)。
在一个实施例中，与第一斜坡面连接的隔离层的顶面和所述第一斜坡面之间具有第一夹角；tan (180°-θ1)>μ1，θ1为第一夹角，μ1为第一斜坡面的摩擦系数。
在一个实施例中，与第二斜坡面连接的隔离层的顶面和所述第二斜坡面之间具有第二夹角；tan(180°-θ2)>μ2；θ2为第二夹角，μ2为第二斜坡面的摩擦系数。
实施例6
本实施例与实施例5的区别在于；参考图16，所述显示面板还包括：阻挡层211，位于所述开口组周围的隔离层207上，所述阻挡层211中具有第三开口，所述第三开口的宽度大于所述Micro-LED芯片的宽度。
在一个实施例中，所述第三开口的宽度小于或等于所述Micro-LED芯片的宽度的1.5倍。
在一个实施例中，所述阻挡层211为遮光阻挡层。所述遮光阻挡层的材料为遮光树脂。在其他实施例中，所述阻挡层211的材料还可以为非遮光材料。
在一个实施例中，所述阻挡层211为遮光阻挡层，所述阻挡层背离所述第二基板一侧的顶面的高度大于所述Micro-LED芯片背离所述第二基板一侧的顶面的高度。
在另一个实施例中，所述阻挡层背离所述第二基板一侧的顶面的高度小于或等于所述Micro-LED芯片背离所述第二基板一侧的顶面的高度。
关于本实施例与实施例5相同的内容不再详述。
实施例7
本实施例与实施例4的区别在于：所述显示面板还包括：阻挡层，位于所述开口组周围的隔离层上，所述阻挡层中具有第三开口，所述第三开口的宽度大于所述Micro-LED芯片的宽度。在一个实施例中，所述第三开口的宽度小于或等于所述Micro-LED芯片的宽度的1.5倍。
在一个实施例中，所述阻挡层211为遮光阻挡层。所述遮光阻挡层的材料为遮光树脂。在其他实施例中，所述阻挡层211的材料还可以为非遮光材料。
在一个实施例中，所述阻挡层211为遮光阻挡层，所述阻挡层背离所述第二基板一侧的顶面的高度大于所述Micro-LED芯片背离所述第二基板一侧的顶面的高度。在另一个实施例中，所述阻挡层背离所述第二基板一侧的顶面的高度小于或等于所述Micro-LED芯片背离所述第二基板一侧的顶面的高度。
关于本实施例与实施例4相同的内容不再详述。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之中。

Claims (30)

  1. 一种显示面板的制备方法，其特征在于，包括：
    提供第一基板，所述第一基板的一侧具有若干间隔的Micro-LED芯片，所述Micro-LED芯片包括：芯片本体；P型电极和N型电极，位于所述芯片本体一侧的部分表面；
    提供第二基板，所述第二基板的一侧表面具有若干导电层；
    在所述第二基板上形成隔离层，所述隔离层中具有若干开口组，每个开口组均包括间隔的第一开口和第二开口，所述第一开口和第二开口分别暴露出导电层的表面，所述第一开口的宽度小于所述P型电极的宽度，所述第二开口的宽度小于所述N型电极的宽度；
    在第一开口中形成第一键合层，在第二开口中形成第二键合层；
    以所述隔离层对所述芯片本体支撑，将所述P型电极与所述第一键合层进行键合的同时将所述N型电极与所述第二键合层进行键合，所述P型电极嵌入第一键合层中，所述N型电极嵌入第二键合层中。
  2. 根据权利要求1所述的显示面板的制备方法，其特征在于，所述芯片本体包括：N型半导体层；位于所述N型半导体层一侧的部分表面的有源层；位于所述有源层背离所述N型半导体层一侧表面的P型半导体层；
    所述P型电极位于部分所述P型半导体层背离所述有源层的一侧表面；所述N型电极位于有源层、P型半导体层和P型电极的侧部的所述N型半导体层一侧的部分表面；
    将所述P型电极与第一键合层进行键合、以及将所述N型电极与第二键合层进行键合的过程中，以所述隔离层对所述P型电极周围的所述P型半导体层为支撑。
  3. 根据权利要求1所述的显示面板的制备方法，其特征在于，还包括：在第一开口中形成第一键合层之前，在第一开口的侧壁和第一开口周围的隔离层的顶面之间的交界处形成第一斜坡面；在第二开口中形成第二键合层之前，在第二开口的侧壁和第二开口周围的隔离层的顶面之间的交界处形成第二斜坡面。
  4. 根据权利要求3所述的显示面板的制备方法，其特征在于，与第一斜坡面连接的隔离层的顶面和所述第一斜坡面之间具有第一夹角；tan(180°-θ1)>μ1，θ1为第一夹角，μ1为第一斜坡面的摩擦系数。
  5. 根据权利要求3所述的显示面板的制备方法，其特征在于，与第二斜坡面连接的隔离层的顶面和所述第二斜坡面之间具有第二夹角；tan(180°-θ2)>μ2；θ2为第二夹角，μ2为第二斜坡面的摩擦 系数。
  6. 根据权利要求1至5任意一项所述的显示面板的制备方法，其特征在于，还包括：将所述P型电极与第一键合层、所述N型电极与第二键合层进行键合之前，在所述开口组周围的隔离层上形成阻挡层，所述阻挡层中具有第三开口，所述第三开口的宽度大于所述Micro-LED芯片的宽度。
  7. 根据权利要求6所述的显示面板的制备方法，其特征在于，所述第三开口的宽度小于或等于所述Micro-LED芯片的宽度的1.5倍。
  8. 根据权利要求6所述的显示面板的制备方法，其特征在于，所述阻挡层为遮光阻挡层。
  9. 根据权利要求8所述的显示面板的制备方法，其特征在于，所述遮光阻挡层的材料为遮光树脂。
  10. 根据权利要求6所述的显示面板的制备方法，其特征在于，还包括：
    将所述P型电极与第一键合层、所述N型电极与第二键合层进行键合之后，所述阻挡层背离所述第二基板一侧的顶面的高度大于所述Micro-LED芯片背离所述第二基板一侧的顶面的高度。
  11. 根据权利要求1所述的显示面板的制备方法，其特征在于，将所述P型电极与第一键合层、所述N型电极与第二键合层进行键合的过程中，采用的绑定设备具有特征对位精度；
    所述第一开口的宽度大于或等于所述P型电极的宽度与2倍的所述特征对位精度之和，所述第二开口的宽度大于或等于所述N型电极与2倍的所述特征对位精度之和。
  12. 根据权利要求1所述的显示面板的制备方法，其特征在于，在第一开口中形成第一键合层，在第二开口中形成第二键合层的步骤中，所述第一键合层的厚度大于或等于第一开口的深度的80％且小于或等于第一开口的深度，所述第二键合层的厚度大于或等于第二开口的深度的80％且小于或等于第二开口的深度。
  13. 根据权利要求1所述的显示面板的制备方法，其特征在于，所述隔离层的厚度小于或等于所述N型电极与所述P型电极的厚度差的50％。
  14. 根据权利要求13所述的显示面板的制备方法，其特征在于，所述隔离层的厚度为500nm～1000nm。
  15. 根据权利要求1所述的显示面板的制备方法，其特征在于，所述第一键合层和所述第二键合层的材料为焊料；所述第一键合层和所述第二键合层的材料为导电胶。
  16. 一种显示面板，其特征在于，包括：
    第一基板，所述第一基板的一侧具有若干间隔的Micro-LED芯片，所述Micro-LED芯片包括：芯片本体；P型电极和N型电极，位于所述芯片本体一侧的部分表面；
    第二基板，所述第二基板的一侧表面具有若干导电层；
    位于所述第二基板的一侧的隔离层，所述隔离层中具有若干开口组，每个开口组均包括间隔的第一开口和第二开口，所述第一开口和第二开口分别位于导电层上，所述第一开口的宽度小于所述P型电极的宽度，所述第二开口的宽度小于所述N型电极的宽度；
    位于第一开口中的第一键合层；
    位于第二开口中的第二键合层；
    所述P型电极嵌入第一键合层中，所述N型电极嵌入第二键合层中；所述芯片本体与部分隔离层的顶面接触。
  17. 根据权利要求16所述的显示面板，其特征在于，所述芯片本体包括：N型半导体层；位于所述N型半导体层一侧的部分表面的有源层；位于所述有源层背离所述N型半导体层一侧表面的P型半导体层；
    所述P型电极位于部分所述P型半导体层背离所述有源层的一侧表面；所述N型电极位于有源层、P型半导体层和P型电极的侧部的所述N型半导体层一侧的部分表面；所述P型电极周围的所述P型半导体层与第一开口周围的隔离层的顶面接触。
  18. 根据权利要求16所述的显示面板，其特征在于，第一开口的侧壁和第一开口周围的隔离层的顶面之间具有第一斜坡面；在第二开口的侧壁和第二开口周围的隔离层的顶面之间具有第二斜坡面。
  19. 根据权利要求18所述的显示面板，其特征在于，与第一斜坡面连接的隔离层的顶面和所述第一斜坡面之间具有第一夹角；tan(180°-θ1)>μ1，θ1为第一夹角，μ1为第一斜坡面的摩擦系数。
  20. 根据权利要求18所述的显示面板，其特征在于，与第二斜坡面连接的隔离层的顶面和所述第二斜坡面之间具有第二夹角；tan(180°-θ2)>μ2；θ2为第二夹角，μ2为第二斜坡面的摩擦系数。
  21. 根据权利要求16至20任意一项所述的显示面板，其特征在于，还包括：阻挡层，位于所述开口组周围的隔离层上，所述阻挡层中具有第三开口，所述第三开口的宽度大于所述Micro-LED芯片的宽度。
  22. 根据权利要求21所述的显示面板，其特征在于，所述第三开口的宽度小于或等于所述Micro-LED芯片的宽度的1.5倍。
  23. 根据权利要求21所述的显示面板，其特征在于，所述阻挡层为遮光阻挡层。
  24. 根据权利要求23所述的显示面板，其特征在于，所述遮光阻挡层的材料为遮光树脂。
  25. 根据权利要求21所述的显示面板，其特征在于，所述阻挡层背离所述第二基板一侧的顶面的高度大于所述Micro-LED芯片背离所述第二基板一侧的顶面的高度。
  26. 根据权利要求16所述的显示面板，其特征在于，所述第一开口的宽度大于或等于所述P型电极的宽度与2倍的特征对位精度之和，所述第二开口的宽度大于或等于所述N型电极与2倍的特征对位精度之和，所述特征对位精度为0.5μm～2μm。
  27. 根据权利要求16所述的显示面板，其特征在于，所述第一键合层的厚度大于或等于第一开口的深度的80％且小于或等于第一开口的深度，所述第二键合层的厚度大于或等于第二开口的深度的80％且小于或等于第二开口的深度。
  28. 根据权利要求16所述的显示面板，其特征在于，所述隔离层的厚度小于或等于所述N型电极与所述P型电极的厚度差的50％。
  29. 根据权利要求28所述的显示面板，其特征在于，所述隔离层的厚度为500nm～1000nm。
  30. 根据权利要求16所述的显示面板，其特征在于，所述第一键合层和所述第二键合层的材料为焊料；所述第一键合层和所述第二键合层的材料为导电胶。
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