WO2024045485A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2024045485A1
WO2024045485A1 PCT/CN2023/073676 CN2023073676W WO2024045485A1 WO 2024045485 A1 WO2024045485 A1 WO 2024045485A1 CN 2023073676 W CN2023073676 W CN 2023073676W WO 2024045485 A1 WO2024045485 A1 WO 2024045485A1
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WIPO (PCT)
Prior art keywords
transistor
gate
voltage
driving
electrode
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PCT/CN2023/073676
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English (en)
French (fr)
Inventor
郭恩卿
盖翠丽
李俊峰
邢汝博
郭双
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云谷（固安）科技有限公司
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Publication of WO2024045485A1 publication Critical patent/WO2024045485A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance

Definitions

  • the present application relates to the field of display technology, for example, to a pixel circuit and its driving method, and a display panel.
  • a pixel circuit is used to drive a light-emitting device for display, so the stability of the output signal of the pixel circuit becomes an important factor affecting the display quality.
  • the driving transistor in the pixel circuit has the problem of threshold voltage drift, which makes the threshold compensation effect poor and affects the improvement of the image quality of the display panel.
  • This application provides a pixel circuit, a driving method thereof, and a display panel to suppress the threshold voltage drift of the driving transistor in the pixel circuit and improve the threshold compensation effect, thereby improving the display quality of the display panel.
  • This application provides a pixel circuit, including:
  • a driving module including a driving transistor; the driving transistor is a double-gate transistor, including a first gate and a second gate; the driving transistor is configured to respond to the voltage of the second gate to the threshold voltage of the driving transistor performing regulation and generating a driving current in response to the voltage of the first gate;
  • a threshold voltage control module is electrically connected to the drive module; the threshold voltage control module is configured to write preset voltages into the first gate and the second gate respectively to control the threshold voltage of the drive transistor. is the preset threshold voltage;
  • a data writing module electrically connected to the driving module; the data writing module is configured to write data voltage into the driving transistor;
  • a first storage module is electrically connected to the driving module; the first storage module is configured to store the voltage of the first gate;
  • a second storage module is electrically connected to the driving module; the second storage module is configured to store the voltage of the second gate.
  • This application also provides a driving method for a pixel circuit, using the pixel circuit described in any embodiment of this application.
  • the driving method includes:
  • the threshold voltage control module writes the preset voltage into the first gate and the second gate respectively, and controls the drive transistor to control its threshold voltage to the preset value in the self-conducting state. threshold voltage;
  • the data writing module writes the data voltage into the driving transistor
  • the driving module During the light-emitting phase, the driving module generates a driving current in response to the voltage of the first gate.
  • This application also provides a display panel, including the pixel circuit described in any embodiment of this application.
  • the driving module is configured to include a driving transistor, and the driving transistor is a double-gate transistor; and corresponding to the setting method of the driving transistor, a threshold voltage control module is set to be electrically connected to the drive module, and the threshold voltage control module is set to write the preset voltage respectively.
  • the threshold voltages of the first gate, the second gate, and the control driving transistor are the preset threshold voltages; the second storage module is electrically connected to the driving module and is configured to store the voltage of the second gate. Therefore, the embodiments of the present application realize active regulation of the threshold voltage of the driving transistor, thereby suppressing the drift of the threshold voltage of the driving transistor. Compared with the method of passively compensating the threshold voltage, the embodiments of the present application improve the threshold compensation effect of the pixel circuit, thereby improving the display quality of the display panel.
  • Figure 1 is a schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • Figure 2 is a schematic diagram of the IDVG characteristic curve of a double-gate transistor provided by an embodiment of the present application
  • Figure 3 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 4 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 5 is a schematic diagram of the driving timing of a pixel circuit provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 7 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present application.
  • Figure 9 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 10 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 11 is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present application.
  • Figure 12 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 13 is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present application.
  • Figure 14 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 15 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 16 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 17 is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present application.
  • Figure 18 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 19 is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present application.
  • FIG. 20 is a schematic flowchart of a driving method for a pixel circuit provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit includes: a driving module 100 , a threshold voltage control module 200 , a data writing module 300 , a first storage module 400 and a second storage module 500 .
  • the driving module 100 includes a driving transistor M0; the driving transistor M0 is a double-gate transistor, including a first gate G, a second gate BG, a first electrode (source S) and a second electrode (drain D); the driving transistor M0 It is configured to regulate its threshold voltage Vth in response to the voltage of the second gate BG, and to generate a driving current in response to the voltage of the first gate G.
  • the threshold voltage control module 200 is electrically connected to the drive module 100; the threshold voltage control module 200 is configured to write preset voltages into the first gate G and the second gate BG respectively, and regulate the threshold voltage Vth of the drive transistor M0 to the preset threshold. Voltage Vth0.
  • the threshold voltage adjustment module 200 is connected to both the first gate G and the second gate BG of the driving transistor M0.
  • the data writing module 300 is electrically connected to the driving module 100; the data writing module 300 is configured to write the data voltage Vdata into the driving transistor M0.
  • the first storage module 400 is electrically connected to the driving module 100; the first storage module 400 is configured to store the voltage of the first gate G.
  • the second storage module 500 is electrically connected to the driving module 100; the second storage module 500 is configured to store the voltage of the second gate BG.
  • the driving transistor M0 is configured as a vertical double-gate transistor, so that the threshold voltage Vth of the driving transistor M0 can be adjusted.
  • FIG. 2 is a schematic diagram of the IDVG characteristic curve of a double-gate transistor provided by an embodiment of the present application. Referring to FIG. 2 , the abscissa represents the voltage difference V GS between the first gate G and the source S of the driving transistor M0 , and the ordinate represents the driving current I DS generated by the driving transistor M0 . Each characteristic curve in Figure 2 varies with the voltage difference V BS between the second gate BG and the source S of the driving transistor M0 And movement occurs.
  • Figure 2 shows the change of the voltage difference V BS from -4V to +4V.
  • the characteristic curve shifts to the left, indicating that the driving transistor M0 can be turned on with a smaller voltage difference V GS , that is, the threshold voltage Vth of the driving transistor M0 decreases.
  • the threshold voltage Vth can be adjusted by adjusting the voltage difference V BS , and the larger the voltage difference V BS is, the more negative (smaller) the threshold voltage Vth is.
  • the driving process of the pixel circuit includes a threshold control stage, a data writing stage and a light emitting stage.
  • the threshold control stage the threshold voltage control module 200 writes the preset voltages into the first gate G and the second gate BG respectively, and controls the driving transistor M0 to regulate its threshold voltage Vth to the preset threshold in the self-conducting state. Voltage Vth0.
  • the data writing stage the data writing module 300 writes the data voltage Vdata into the driving transistor M0.
  • the driving module 100 generates a driving current in response to the voltage of the first gate G.
  • the voltage difference V BS between the second gate BG and the source S is 4V, corresponding to the left-to-left direction.
  • the first characteristic curve on the right.
  • the voltage difference V GS between the first gate G and the source S is 0V, it can be seen from the characteristic curve that the driving transistor M0 is in the on state.
  • the second gate BG discharges through the self-conducting driving transistor M0, and the corresponding characteristic curve of the driving transistor M0 moves to the right, thereby regulating the threshold voltage Vth of the driving transistor M0.
  • the driving transistor M0 no longer conducts when the voltage difference V GS reaches 0V.
  • the second memory module 500 stores the voltage of the second gate BG, thereby storing the threshold voltage Vth.
  • the driving module 100 in the embodiment of the present application includes a driving transistor M0, which is a vertical double-gate transistor; and corresponding to the setting method of the driving transistor M0, the threshold voltage control module 200 is electrically connected to the driving module 100, and the threshold voltage control module 200 is electrically connected to the driving module 100.
  • the voltage control module 200 is configured to write the preset voltages into the first gate G and the second gate BG respectively to control the threshold voltage Vth of the driving transistor M0 to the preset threshold voltage Vth0; the second storage module 500 and the driving module 100 Electrically connected and configured to store the voltage of the second gate BG.
  • the embodiment of the present application realizes active regulation of the threshold voltage Vth of the driving transistor M0, thereby suppressing the drift of the threshold voltage Vth of the driving transistor M0. with quilt Compared with the method of dynamically compensating the threshold voltage Vth, the embodiments of the present application improve the threshold compensation effect of the pixel circuit, thereby improving the display quality of the display panel.
  • the first gate G and the second gate BG are the top gate and the bottom gate of each other.
  • the first gate G is a top gate
  • the second gate BG is a low gate
  • the first gate G is a bottom gate
  • the second gate BG is a top gate.
  • FIG. 3 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • the threshold voltage regulation module 200 includes: a first initialization unit 210 , a first regulation writing unit 220 and a second initialization unit 230 .
  • the first initialization unit 210 is electrically connected to the first gate G of the driving transistor M0; the first initialization unit 210 is configured to write the first reference voltage Vref1 to the first gate G.
  • the first regulation writing unit 220 is electrically connected to the second gate BG of the driving transistor M0; the first regulation writing unit 220 is configured to write the first fixed voltage V1 to the second gate BG.
  • the second initialization unit 230 is electrically connected to the first pole of the drive transistor M0; the second initialization unit 230 is configured to write the second reference voltage Vref2 to the first pole of the drive transistor M0.
  • the voltage difference between the first reference voltage Vref1 and the second reference voltage Vref2 is the preset threshold voltage Vth0.
  • the driving transistor M0 has a symmetrical structure, and the definitions of its source S and drain D are determined by the type and circuit connection relationship of the driving transistor M0.
  • FIG. 3 exemplarily shows that the driving transistor M0 is an N-type transistor. In other embodiments, the driving transistor M0 can also be configured as a P-type transistor.
  • FIG. 3 exemplarily shows that the first pole of the driving transistor M0 is the source S, and the second pole is the drain D. In other embodiments, the first pole of the driving transistor M0 can also be set to the drain D, and the second pole is the drain D. The second pole is the source S.
  • the working principle of the threshold voltage control module 200 is as follows: the first initialization unit 210 writes the first reference voltage Vref1 into the first gate G, and the second initialization unit 230 writes the second reference voltage Vref2 into the first pole of the driving transistor M0, The voltage difference V GS between the first gate G and the source S of the driving transistor M0 is Vref1-Vref2.
  • the second gate BG discharges through the self-conducting driving transistor M0, the voltage difference V BS decreases, and the characteristic curve corresponding to the driving transistor M0 moves to the right, corresponding to the second characteristic curve from left to right.
  • the second gate BG no longer discharges.
  • the threshold voltage regulation module 200 can realize the function of regulating the threshold voltage Vth of the driving transistor M0, and the first reference voltage
  • the voltage difference between Vref1 and the second reference voltage Vref2 is the preset threshold voltage Vth0.
  • the first memory module 400 is connected between the first gate G and the first electrode (source S) of the driving transistor M0 and is configured to store The voltage difference V GS is used to store the voltage of the first gate G.
  • the second storage module 500 is connected between the second gate BG and the first electrode (source S) of the driving transistor M0, and is configured to store the voltage difference V BS , to store the voltage of the second gate BG.
  • the data writing module 300 is electrically connected to the first gate G of the driving transistor M0; the data writing module 300 is configured to write to the first gate G (i.e., the first storage device).
  • Module 400 writes the data voltage Vdata.
  • the second initialization unit 230 is provided between the driving module 100 and the light-emitting module 600, for example, between the first electrode (source S) and the light-emitting module 600.
  • the driving method of the pixel circuit includes: a threshold control stage, a data writing stage and a light emitting stage, where the threshold control stage includes a first sub-stage and a second sub-stage.
  • the first initialization unit 210 writes the first gate G to the first gate G.
  • the second initialization unit 230 writes the second reference voltage Vref2 to the first pole (source S) of the driving transistor M0;
  • the first regulation writing unit 220 writes the first fixed voltage to the second gate BG V1.
  • the driving module 100 During the light-emitting phase, the driving module 100 generates a driving current in response to the voltage of the first gate G.
  • K is related to the size and mobility of the driving transistor M0 and is determined by the manufacturing process;
  • Vth0 Vref1-Vref2
  • Vdata and Vref1 are both set values.
  • the resulting drive current is determined by the set value and is not affected by the threshold voltage.
  • the pixel circuit provided by the embodiment of the present application suppresses the threshold voltage drift of the driving transistor in the pixel circuit, is less affected by the fluctuation of the threshold voltage of the driving transistor M0, and is less affected by the fluctuation of the first power supply voltage VDD. ;
  • the output driving current is relatively stable, thereby improving the display quality of the display panel.
  • FIG. 4 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • the first initialization unit 210 includes a first transistor M1.
  • the gate of the first transistor M1 is connected to the first scan signal S1
  • the first electrode of the first transistor M1 is electrically connected to the first gate G
  • the second electrode of the first transistor M1 is connected to the first reference voltage Vref1.
  • This setting makes the first initialization unit 210
  • the circuit structure is simple and easy to implement.
  • the first control writing unit 220 includes a second transistor M2, the gate of the second transistor M2 is connected to the second scan signal S2, and the first electrode of the second transistor M2 is connected to the second scan signal S2. Electrically connected to the second gate BG, the second electrode of the second transistor M2 is connected to the first fixed voltage V1.
  • the second pole (drain D) of the driving transistor M0 is connected to the first power supply voltage VDD, and the first power supply voltage VDD is multiplexed into the first fixed voltage V1, that is, the second pole of the second transistor M2 is connected to the first power supply voltage VDD. a supply voltage VDD.
  • the second initialization unit 230 includes: a third transistor M3 and a fourth transistor M4.
  • the gate of the third transistor M3 is connected to the third scan signal S3, the first electrode of the third transistor M3 is connected to the second reference voltage Vref2, and the second electrode of the third transistor M3 is electrically connected to the first electrode of the fourth transistor M4.
  • the gate electrode of the fourth transistor M4 is connected to the fourth scanning signal S4, and the second electrode of the fourth transistor M4 is electrically connected to the first electrode (source electrode S) of the driving transistor M0.
  • the data writing module 300 includes a fifth transistor M5, the gate of the fifth transistor M5 is connected to the fifth scan signal S5, and the first electrode of the fifth transistor M5 is connected to Data voltage Vdata, the second electrode of the fifth transistor M5 is electrically connected to the first gate G of the driving transistor M0.
  • a fifth transistor M5 the gate of the fifth transistor M5 is connected to the fifth scan signal S5
  • the first electrode of the fifth transistor M5 is connected to Data voltage Vdata
  • the second electrode of the fifth transistor M5 is electrically connected to the first gate G of the driving transistor M0.
  • the first memory module 400 includes a first capacitor Cst1, a first electrode of the first capacitor Cst1 is electrically connected to the first gate G, and a second electrode of the first capacitor Cst1 It is electrically connected to the first electrode (source S) of the drive transistor M0.
  • a first capacitor Cst1 a first electrode of the first capacitor Cst1 is electrically connected to the first gate G, and a second electrode of the first capacitor Cst1 It is electrically connected to the first electrode (source S) of the drive transistor M0.
  • the second memory module 500 includes a second capacitor Cst2, a first electrode of the second capacitor Cst2 is electrically connected to the second gate BG, and a second electrode of the second capacitor Cst2 It is electrically connected to the first electrode (source S) of the drive transistor M0.
  • a second capacitor Cst2 a first electrode of the second capacitor Cst2 is electrically connected to the second gate BG, and a second electrode of the second capacitor Cst2 It is electrically connected to the first electrode (source S) of the drive transistor M0.
  • each transistor is exemplarily an N-type transistor, which is produced using a metal oxide semiconductor process. For example, it can be produced using Indium Gallium Zinc Oxide (IGZO).
  • IGZO Indium Gallium Zinc Oxide
  • An N-type transistor is on when its gate is high and off when its gate is low.
  • the driving method of the pixel circuit includes: a threshold control stage T1, a data writing stage T2 and a light emitting stage T3, wherein the threshold control stage T1 includes a first sub-stage T11 and a second sub-stage T12.
  • the first scanning signal S1, the second scanning signal S2, the third scanning signal S3 and the fourth scanning signal S4 are all high level, and the fifth scanning signal S5 is low level.
  • the fifth transistor M5 is turned off under the control of the fifth scan signal S5, and the other transistors are all turned on, that is, the first transistor M1 to the fourth transistor M4 are all turned on.
  • the first transistor M1 writes the first reference voltage Vref1 into the first gate G;
  • the third transistor M3 and the fourth transistor M4 write the second reference voltage Vref2 into the first electrode (source S) of the driving transistor M0;
  • the second The transistor M2 writes the first power supply voltage VDD into the second gate BG.
  • the voltage difference V GS between the first gate G and the first electrode (source S) of the driving transistor M0 Vref1-Vref2
  • the voltage difference V BS between the second gate BG and the source S VDD-Vref2 .
  • the first scanning signal S1 and the fourth scanning signal S4 switch from high level to low level, and other scanning signals maintain the state of the first sub-stage T11.
  • the fifth transistor M5 remains in an off state; the first transistor M1 switches from the on state to the off state under the control of the first scan signal S1; the fourth transistor M4 switches from the on state under the control of the fourth scan signal S4. Switch to disconnected state.
  • the voltage difference V GS between the first gate G and the first electrode (source S) of the driving transistor M0 is maintained by the first capacitor Cst1.
  • the first scanning signal S1 and the second scanning signal S2 are low level, and the third scanning signal S3, the fourth scanning signal S4 and the fifth scanning signal S5 are all high level.
  • the fifth transistor M5 is turned on under the control of the fifth scan signal S5, and writes the data voltage Vdata into the first gate G;
  • the driving transistor M0 generates a driving current in response to the voltage of the first gate G.
  • K is related to the size and mobility of the driving transistor M0 and is determined by the manufacturing process; Vdata and Vref1 are both set values.
  • the pixel circuit provided by the embodiment of the present application suppresses the threshold voltage drift of the driving transistor in the pixel circuit, is less affected by the fluctuation of the threshold voltage of the driving transistor M0, and is less affected by the fluctuation of the first power supply voltage VDD. ;
  • the output driving current is relatively stable, thereby improving the display quality of the display panel.
  • the changes of the third scanning signal S3 and the fourth scanning signal S4 are set to be the same, switching from high level to is low level.
  • the third transistor M3 switches from the on state to the off state under the control of the third scan signal S3, and the second reference voltage Vref2 is no longer written to the anode of the light emitting device D1.
  • the voltage difference V GS between the first gate G and the first electrode (source S) of the driving transistor M0 is maintained by the first capacitor Cst1.
  • the driving transistor M0 is self-conductive, and the voltage of its first electrode (source S) gradually increases until the driving transistor M0 is turned off.
  • the magnitude of the driving current is related to the first reference voltage Vref1 and has nothing to do with the second reference voltage Vref2.
  • the first reference voltage Vref1 and the second reference voltage Vref2 are not related to each other.
  • the difference between the reference voltage Vref2 determines the threshold voltage of the driving transistor M0.
  • it is still necessary to adjust the first reference voltage Vref1 and the second reference voltage The size relationship of pressure Vref2 is limited.
  • each transistor is an N-type transistor, and the first reference voltage Vref1 is greater than or equal to the second reference voltage Vref2, so that the preset threshold voltage Vth0 of the driving transistor M0 is greater than or equal to 0V.
  • the driving transistor M0 is an N-type transistor, the threshold voltage Vth of the driving transistor M0 is greater than 0 under normal circumstances, and the preset threshold voltage Vth0 is the difference between the first reference voltage Vref1 and the second reference voltage Vref2, Accordingly, setting the first reference voltage Vref1 to be greater than or equal to the second reference voltage Vref2 is beneficial to the normal operation of the driving transistor M0.
  • the first reference voltage Vref1 is equal to the second reference voltage Vref2, so that the preset threshold voltage Vth0 of the driving transistor M0 is equal to 0V.
  • Such an arrangement is beneficial to multiplexing the first reference voltage Vref1 into the second reference voltage Vref2, thereby reducing the number of signal lines.
  • the light-emitting module 600 is also connected to the second power supply voltage VSS.
  • the first power supply voltage VDD is greater than the second reference voltage Vref2; the second reference voltage Vref2 is greater than the second power supply voltage VSS; and the difference between the second reference voltage Vref2 and the second power supply voltage VSS is less than the turn-on voltage of the light-emitting module 600.
  • the light-emitting module 600 includes a light-emitting device D1.
  • the anode of the light-emitting device D1 is electrically connected to the first electrode of the fourth transistor M4.
  • the cathode of the light-emitting device D1 is connected to the second power supply voltage VSS.
  • the conditions for turning on the driving transistor M0 include, in addition to the voltage difference V GS >threshold voltage Vth, the drain voltage V D > the source voltage V S .
  • the drain voltage V D is the first power supply voltage
  • the source voltage V S is the second reference voltage Vref2. Therefore, it is also necessary to set the first power supply voltage VDD to be greater than the second reference voltage Vref2.
  • the second reference voltage Vref2 is written into the anode of the light-emitting module 600 through the third transistor M3.
  • the voltage difference between the two ends of the light-emitting module 600 is Vref2-VSS. Setting Vref2-VSS smaller than the turn-on voltage of the light-emitting module 600 is helpful to prevent the light-emitting module 600 from misleadingly turning on during the threshold control stage.
  • FIG. 6 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • the data writing module 300 is electrically connected to the first pole (source S) of the driving transistor M0; the data writing module 300 is set to the data voltage Vdata Writing to the first pole (source S) of the driving transistor M0, the data writing module 300 is configured to write the data voltage Vdata into the first memory module 400.
  • the driving method of the pixel circuit includes: a threshold control stage, a data writing stage and a light emitting stage, wherein the threshold control stage includes a first sub-stage and a second sub-stage.
  • the first initialization unit 210 writes the first reference voltage Vref1 to the first gate G; the second initialization unit 230 writes the first reference voltage Vref1 to the first electrode (source S) of the driving transistor M0. Two reference voltages Vref2; the first control writing unit 220 writes the first fixed voltage V1 to the second gate BG.
  • the driving transistor M0 is self-conductive, and the threshold voltage Vth of the driving transistor M0 is controlled to be the preset threshold voltage Vth0; the preset threshold voltage Vth0 is the first reference voltage Vref1 and the second reference voltage Vref2 difference.
  • the driving module 100 During the light-emitting phase, the driving module 100 generates a driving current in response to the voltage of the first gate G.
  • K is related to the size and mobility of the driving transistor M0 and is determined by the manufacturing process; Vdata and Vref1 are both set values.
  • the pixel circuit provided by the embodiment of the present application suppresses the threshold voltage drift of the driving transistor in the pixel circuit, is less affected by the fluctuation of the threshold voltage of the driving transistor M0, and is less affected by the fluctuation of the first power supply voltage VDD. ;
  • the output driving current is relatively stable, thereby improving the display quality of the display panel.
  • FIG. 7 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • the data writing module 300 includes a sixth transistor M6 , the gate of the sixth transistor M6 is connected to the sixth scanning signal S6 , and the first electrode of the sixth transistor M6 is connected to the data voltage Vdata.
  • the sixth transistor M6 The second pole of the drive transistor M0 is electrically connected to the first pole of the drive transistor M0.
  • FIG. 8 is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present application. 7 and 8 , exemplarily, each transistor is an N-type transistor.
  • the driving method of the pixel circuit includes: a threshold control stage T1, a data writing stage T2 and a light emitting stage T3, wherein the threshold control stage T1 includes a first sub-stage T11 and a second sub-stage T12.
  • the first scanning signal S1, the second scanning signal S2, the third scanning signal S3 and the fourth scanning signal S4 are all high level, and the sixth scanning signal S6 is low level.
  • the sixth transistor M6 is turned off under the control of the sixth scan signal S6, and the other transistors are all turned on, that is, the first transistor M1 to the fourth transistor M4 are all turned on.
  • the first transistor M1 writes the first reference voltage Vref1 into the first gate G;
  • the third transistor M3 and the fourth transistor M4 write the second reference voltage Vref2 into the first electrode (source S) of the driving transistor M0;
  • the second The transistor M2 writes the first power supply voltage VDD into the second gate BG.
  • the voltage difference V GS between the first gate G and the first electrode (source S) of the driving transistor M0 Vref1-Vref2
  • the voltage difference V BS between the second gate BG and the source S VDD-Vref2 .
  • the first scanning signal S1, the third scanning signal and the fourth scanning signal S4 switch from high level to low level, and the second scanning signal S2 and the sixth scanning signal S6 remain The state of the first sub-stage T11.
  • the sixth transistor M6 remains in an off state; the first transistor M1 switches from the on state to the off state under the control of the first scan signal S1; the third transistor M3 switches from the on state under the control of the third scan signal S3. Switch to the off state; the fourth transistor M4 switches from the on state to the off state under the control of the fourth scan signal S4.
  • the voltage difference V GS between the first gate G and the first electrode (source S) of the driving transistor M0 is maintained by the first capacitor Cst1.
  • the driving transistor M0 is self-conductive, and the voltage of its first electrode (source S) gradually increases until the driving transistor M0 is turned off.
  • the first scanning signal S1 and the sixth scanning signal S6 are at high level, and the second scanning signal S2, the third scanning signal S3 and the fourth scanning signal S4 are all at a low level.
  • the driving transistor M0 generates a driving current in response to the voltage of the first gate G.
  • K is related to the size and mobility of the driving transistor M0 and is determined by the manufacturing process; Vdata and Vref2 are both set values.
  • the pixel circuit provided by the embodiment of the present application suppresses the threshold voltage drift of the driving transistor M0 in the pixel circuit, is less affected by the fluctuation of the threshold voltage of the driving transistor M0, and is less affected by the fluctuation of the first power supply voltage VDD. Small; the output driving current is relatively stable, thereby improving the display quality of the display panel.
  • the relationship between the first reference voltage Vref1, the second reference voltage Vref2, the first power supply voltage VDD and the second power supply voltage VSS is similar to that in the previous embodiments, and will not be repeated here. Repeat.
  • FIG. 9 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • the threshold voltage regulation module 200 includes: a second regulation writing unit 240 and a third regulation writing unit 250 .
  • the second regulation writing unit 240 is electrically connected to the first gate G of the driving transistor M0 and to the first electrode (source S) of the driving transistor M0; the second regulation writing unit 240 is configured to write to the driving transistor M0 Write the preset threshold voltage Vth0.
  • the preset threshold voltage Vth0 is stored in the form of a voltage difference between the first gate G and the source S of the driving transistor M0, that is, the voltage difference between the first gate G and the source S of the driving transistor M0.
  • the voltage difference V GS is Vth0.
  • the third regulation writing unit 250 is electrically connected to the second electrode (drain D) of the driving transistor M0 and to the second gate BG of the driving transistor M0; the third regulation writing unit 250 is configured to write to the second electrode of the driving transistor M0.
  • the first fixed voltage V1 is written into the gate BG, and the first power supply voltage VDD is written into the second electrode (drain D) of the driving transistor M0.
  • the first power supply voltage VDD is multiplexed into the first fixed voltage V1.
  • the working principle of the threshold voltage regulation module 200 is: the second regulation writing unit 240 writes the preset threshold voltage Vth0 into the driving transistor M0, so that the voltage difference V GS between the first gate G and the source S of the driving transistor M0 is Vth0.
  • the third regulation writing unit 250 writes the first power supply voltage VDD into the second gate BG, so that the voltage difference V BS between the second gate BG and the source S of the driving transistor M0 is VDD-Vth0, and its value is based on The setting mode of the second control writing unit 240 is determined.
  • the second gate BG discharges through the self-conducting driving transistor M0, the voltage difference V BS decreases, and the characteristic curve corresponding to the driving transistor M0 moves to the right, corresponding to the second characteristic curve from left to right.
  • the threshold voltage of the driving transistor M0 is the preset threshold voltage Vth0.
  • the threshold voltage adjustment module 200 can realize the function of adjusting the threshold voltage Vth of the driving transistor M0.
  • the first storage module 400 , the second storage module 500 and the data writing module 300 are arranged in a manner similar to the previous embodiment.
  • the data writing module 300 is electrically connected to the first gate G, or the data writing module 300 is connected to the first pole (source S) of the driving transistor M0. Electrical connection.
  • the following describes the driving method of the pixel circuit shown in FIG. 9 by taking the data writing module 300 to be electrically connected to the first gate G as an example.
  • the driving method of the pixel circuit includes: a threshold control stage, a data writing stage and a light emitting stage, wherein the threshold control stage includes a first sub-stage and a second sub-stage.
  • the second regulation writing unit 240 sets the preset threshold voltage Vth0 Write the driving transistor M0; the third regulation writing unit 250 writes the first power supply voltage VDD to the second gate BG and the second electrode (source D) of the driving transistor M0.
  • the second regulation writing unit 240 continues to write the preset threshold voltage Vth0 into the driving transistor M0 and remains unchanged; the first power supply voltage VDD is no longer written into the second gate BG and the driving transistor M0.
  • the second electrode (source D) of the transistor M0, but the second gate BG and the second electrode (source D) of the driving transistor M0 are still turned on, so that the driving transistor M0 self-conducts to regulate the voltage of the driving transistor M0.
  • the threshold voltage Vth is the preset threshold voltage Vth0.
  • the data writing module 300 writes the data voltage Vdata into the first gate G.
  • the writing method of the data voltage Vdata is determined according to the setting method of the second control writing unit 240 .
  • the driving module 100 During the light-emitting phase, the driving module 100 generates a driving current in response to the voltage of the first gate G.
  • K is related to the size and mobility of the driving transistor M0 and is determined by the manufacturing process; Vdata, V S and Vth0 are all set values.
  • the pixel circuit provided by the embodiment of the present application suppresses the threshold voltage drift of the driving transistor in the pixel circuit, is less affected by the threshold voltage fluctuation of the driving transistor M0, and the output driving current is relatively stable, thus improving the performance of the display panel. Display quality.
  • FIG. 10 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • the third control writing unit 250 includes: a seventh transistor M7 and an eighth transistor M8.
  • the gate of the seventh transistor M7 is connected to the seventh scan signal S7, the first electrode of the seventh transistor M7 is electrically connected to the second gate BG, and the second electrode of the seventh transistor M7 is connected to the second electrode (drain) of the driving transistor M0. Pole D) electrical connection.
  • the gate of the eighth transistor M8 is connected to the eighth scan signal S8, the first electrode of the eighth transistor M8 is electrically connected to the second electrode (drain D) of the driving transistor M0, and the second electrode of the eighth transistor M8 is connected to the eighth scan signal S8. a supply voltage VDD.
  • the second control writing unit 240 includes: a ninth transistor M9 and a tenth transistor M10.
  • the gate of the ninth transistor M9 is connected to the ninth scanning signal S9, the first electrode of the ninth transistor M9 is electrically connected to the first gate G, and the second electrode of the ninth transistor M9 is connected to the first reference voltage Vref1.
  • the gate of the tenth transistor M10 is connected to the tenth scan signal S10, the first electrode of the tenth transistor M10 is electrically connected to the first electrode (source S) of the driving transistor M0, and the second electrode of the tenth transistor M10 is connected to the 2 reference voltage Vref2.
  • the voltage difference between the first reference voltage Vref1 and the second reference voltage Vref2 is the preset threshold voltage Vth0.
  • the seventh scan signal S7 is multiplexed into the ninth scan signal S9 to reduce the number of signal lines.
  • FIG. 11 is a schematic diagram of the driving timing of yet another pixel circuit provided by an embodiment of the present application.
  • each transistor is an N-type transistor.
  • the driving method of the pixel circuit includes: a threshold control stage T1, a data writing stage T2 and a light emitting stage T3, wherein the threshold control stage T1 includes a first sub-stage T11 and a second sub-stage T12.
  • the seventh scan signal S7 (ninth scan signal S9), the eighth scan signal S8 and the tenth scan signal S10 are all high level, and the fifth scan signal S5 is low level.
  • the fifth transistor M5 is turned off under the control of the fifth scan signal S5, and the other transistors are all turned on, that is, the seventh transistor M7 to the tenth transistor M10 are all turned on.
  • the ninth transistor M9 writes the first reference voltage Vref1 into the first gate G; the tenth transistor M10 writes the second reference voltage Vref2 into the first pole (source S) of the driving transistor M0; the seventh transistor M7 and the eighth transistor M7
  • the transistor M8 writes the first power supply voltage VDD into the second gate BG.
  • the eighth scan signal S8 switches from high level to low level, and other scan signals maintain the state of the first sub-stage T11.
  • the fifth transistor M5 remains in the off state; the eighth transistor M8 switches from the on state to the off state under the control of the eighth scan signal S8.
  • the seventh transistor M7 is in a conductive state and connects the second electrode (drain) of the driving transistor M0 and the second gate electrode BG.
  • the driving transistor M0 is self-conductive, and the voltage of its second gate BG is discharged through the driving transistor M0, and its voltage gradually decreases until the driving transistor M0 is turned off.
  • the threshold voltage Vth of the driving transistor M0 is adjusted to the preset threshold voltage Vth0.
  • the seventh scan signal S7 (the ninth scan signal S9) and the eighth scan signal S8 are low level, and the tenth scan signal S10 and the fifth scan signal S5 are both high level.
  • the seventh scanning signal S7 (the ninth scanning signal S9), the tenth scanning signal S10 and the fifth scanning signal S5 are all low level, and the eighth scanning signal S8 is high level.
  • the eighth transistor M8 is turned on, and the driving transistor M0 generates a driving current in response to the voltage of the first gate G.
  • K is related to the size and mobility of the driving transistor M0 and is determined by the manufacturing process; Vdata and Vref1 are both set values.
  • the pixel circuit provided by the embodiment of the present application suppresses the threshold voltage drift of the driving transistor in the pixel circuit, is less affected by the fluctuation of the threshold voltage of the driving transistor M0, and is less affected by the fluctuation of the first power supply voltage VDD. ;
  • the output driving current is relatively stable, thereby improving the display quality of the display panel.
  • the seventh scan signal S7 and the ninth scan signal S9 are set separately.
  • the eighth scan signal S8 In the second sub-phase T12 of the threshold control phase T1, the eighth scan signal S8, The ninth scanning signal S9 and the tenth scanning signal S10 both switch from high level to low level, and other scanning signals maintain the state of the first sub-stage T11.
  • the fifth transistor M5 remains in an off state; the eighth transistor The tube M8 switches from the on state to the off state under the control of the eighth scan signal S8.
  • the ninth transistor M9 and the tenth transistor M10 are switched from the on state to the off state, and the voltage difference V GS between the first gate G and the first electrode (source S) of the driving transistor M0 is maintained by the first capacitor Cst1 .
  • the seventh transistor M7 is in a conductive state and connects the second electrode (drain) of the driving transistor M0 and the second gate electrode BG.
  • the driving transistor M0 is self-conductive, and the voltage of its second gate BG is discharged through the driving transistor M0, and its voltage gradually decreases until the driving transistor M0 is turned off.
  • the threshold voltage Vth of the driving transistor M0 is adjusted to the preset threshold voltage Vth0.
  • the seventh scanning signal S7 and the ninth scanning signal S9 are set separately, and the data writing module 300 and the driving transistor M0
  • the first electrode (source electrode S) is electrically connected; the data writing module 300 is configured to write the data voltage Vdata into the first electrode (source electrode S) of the driving transistor M0.
  • the relationship between the first reference voltage Vref1, the second reference voltage Vref2, the first power supply voltage VDD and the second power supply voltage VSS is similar to that in the previous embodiments, and will not be repeated here. Repeat.
  • FIG. 12 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • the second regulation writing unit 240 includes: an eleventh transistor M11 and a twelfth transistor M12.
  • the gate of the eleventh transistor M11 is connected to the eleventh scanning signal S11, the first electrode of the eleventh transistor M11 is electrically connected to the first gate G, and the second electrode of the eleventh transistor M11 is connected to the first reference voltage. Vref1.
  • the gate of the twelfth transistor M12 is connected to the twelfth scanning signal S12, the first electrode of the twelfth transistor M12 is electrically connected to the first electrode (source S) of the driving transistor M0, and the second electrode of the twelfth transistor M12
  • the pole is electrically connected to the first pole of the eleventh transistor M11; wherein the preset threshold voltage Vth0 is 0.
  • the eleventh scanning signal S11 is multiplexed into the twelfth scanning signal S12 to reduce the number of signal lines.
  • each transistor is an N-type transistor.
  • the driving method of the pixel circuit includes: a threshold control stage T1, a data writing stage T2 and a light emitting stage T3, wherein the threshold control stage T1 includes a first sub-stage T11 and a second sub-stage T12.
  • the seventh scan signal S7 (eleventh scan signal S11/twelfth scan signal S12) and the eighth scan signal S8 are both high level, and the fifth scan signal S5 is low. level.
  • the fifth transistor M5 is turned off under the control of the fifth scan signal S5, and all other transistors are turned on, that is, the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are all turned on.
  • the eleventh transistor M11 writes the first reference voltage Vref1 into the first gate G; the twelfth transistor M12 writes the first reference voltage Vref1 into the first pole (source S) of the driving transistor M0; the seventh transistor M7 and The eighth transistor M8 writes the first power supply voltage VDD into the second gate BG.
  • the eighth scan signal S8 switches from high level to low level, and other scan signals maintain the state of the first sub-stage T11.
  • the fifth transistor M5 remains in the off state; the eighth transistor M8 switches from the on state to the off state under the control of the eighth scan signal S8.
  • the seventh transistor M7 is in a conductive state and connects the second electrode (drain) of the driving transistor M0 and the second gate electrode BG.
  • the threshold voltage Vth of the driving transistor M0 is adjusted to the preset threshold voltage Vth0.
  • the seventh scanning signal S7 (the eleventh scanning signal S11/the twelfth scanning signal S12) and the eighth scanning signal S8 are low level, and the fifth scanning signal S5 is both high level.
  • the fifth transistor M5 is turned on under the control of the fifth scan signal S5, and writes the data voltage Vdata into the first gate G, The voltage of the first gate G rises by Vdata-Vref1.
  • the voltage rise of the second gate BG is equal to the voltage rise of the first electrode (source S), and the voltage difference V BS remains consistent with the previous stage. Therefore, the driving The threshold voltage of transistor M0 remains consistent with the previous stage.
  • the seventh scanning signal S7 (the eleventh scanning signal S11/the twelfth scanning signal S12) and the fifth scanning signal S5 are both low level, and the eighth scanning signal S8 is high level.
  • the eighth transistor M8 is turned on, and the driving transistor M0 generates a driving current in response to the voltage of the first gate G.
  • the driving current I K*(V GS -Vth0) 2
  • K is related to the size and mobility of the driving transistor M0 and is determined by the manufacturing process; Vdata and Vref1 are both set values; Cst1 and Cd1 are both capacitance values.
  • the pixel circuit provided by the embodiment of the present application suppresses the threshold voltage drift of the driving transistor in the pixel circuit, is less affected by the fluctuation of the threshold voltage of the driving transistor M0, and is less affected by the fluctuation of the first power supply voltage VDD. ;
  • the output driving current is relatively stable, thereby improving the display quality of the display panel.
  • the eleventh scanning signal S11 and the twelfth scanning signal S12 are set separately, and the data writing module 300 and the driving The first electrode (source electrode S) of the transistor M0 is electrically connected; the data writing module 300 is configured to write the data voltage Vdata into the first electrode (source electrode S) of the driving transistor M0.
  • FIG. 14 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • a fifteenth transistor M15 is also included.
  • the gate of the fifteenth transistor M15 is connected to the fifth scanning signal S5, the first electrode of the fifteenth transistor M15 is connected to the first reference voltage Vref1, and the second electrode of the fifteenth transistor M15 is connected to the second electrode of the first capacitor Cst1. poles are electrically connected, that is, the second pole of the fifteenth transistor M15 is electrically connected to the first pole (source S) of the driving transistor M0.
  • the fifteenth transistor M15 and the fifth transistor M5 are both controlled by the fifth scanning signal S5.
  • the fifteenth transistor M15 and the fifth transistor M5 are turned on simultaneously.
  • the first pole of the first capacitor Cst1 is written with the data voltage Vdata
  • the second pole of the first capacitor Cst1 is written with the first reference voltage Vref1, which can prevent the second pole of the first capacitor Cst1 from being in a floating state and causing voltage deviation. shift, which is conducive to fast writing of the data voltage Vdata.
  • the magnitude relationship between the first reference voltage Vref1, the first power supply voltage VDD, and the second power supply voltage VSS is similar to the previous embodiments, and will not be described again here.
  • FIG. 15 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • the threshold voltage regulation module 200 includes: a second regulation writing unit 240 and a fourth regulation writing unit 260 .
  • the fourth regulation writing unit 260 is electrically connected to the second gate BG of the driving transistor M0; the fourth regulation writing unit 260 is configured to write the first fixed voltage V1 to the second gate BG.
  • the working principle of the threshold voltage regulation module 200 is: the second regulation writing unit 240 writes the preset threshold voltage Vth0 into the driving transistor M0, so that the voltage difference V GS between the first gate G and the source S of the driving transistor M0 is Vth0.
  • the fourth control writing unit 260 writes the first fixed voltage V1 into the second gate BG, so that the voltage difference V BS between the second gate BG and the source S of the driving transistor M0 is V1-Vth0, and its value is based on The setting mode of the second control writing unit 240 is determined.
  • the driving transistor M0 is in a conductive state.
  • the second gate BG discharges through the self-conducting driving transistor M0, the voltage difference V BS decreases, and the characteristic curve corresponding to the driving transistor M0 moves to the right, corresponding to the second characteristic curve from left to right.
  • the threshold voltage adjustment module 200 can realize the function of adjusting the threshold voltage Vth of the driving transistor M0.
  • the embodiment of the present application also sets the values of the preset threshold voltage Vth0 and the first fixed voltage V1 of the write drive transistor M0 to ensure that during the threshold voltage control stage, although the first voltage of the drive transistor M0 is One pole (source S) is connected to the light-emitting module 600, and the driving transistor M0 is in a conductive state.
  • the voltage difference between the first pole (source S) of the driving transistor M0 and the second power supply voltage VSS is less than that of the light-emitting module 600. Turn on voltage.
  • the first storage module 400 , the second storage module 500 and the data writing module 300 are arranged in a manner similar to the previous embodiment.
  • the data writing module 300 is electrically connected to the first gate G, or the data writing module 300 is connected to the first pole (source S) of the driving transistor M0. Electrical connection.
  • the following describes the driving method of the pixel circuit shown in FIG. 15 by taking the data writing module 300 to be electrically connected to the first gate G as an example.
  • the driving method of the pixel circuit includes: a threshold control stage, a data writing stage and a light emitting stage, wherein the threshold control stage includes a first sub-stage and a second sub-stage.
  • the second regulation writing unit 240 writes the preset threshold voltage Vth0 into the driving transistor M0; the fourth regulation writing unit 260 writes the first fixed voltage V1 into the second gate BG.
  • the driving transistor M0 is self-conductive to regulate the threshold voltage Vth of the driving transistor M0 to the preset threshold voltage Vth0.
  • the data writing module 300 writes the data voltage Vdata into the first gate G.
  • the writing method of the data voltage Vdata is determined according to the setting method of the second control writing unit 240 .
  • the driving module 100 During the light-emitting phase, the driving module 100 generates a driving current in response to the voltage of the first gate G.
  • K is related to the size and mobility of the driving transistor M0 and is determined by the manufacturing process; Vdata, V S and Vth0 are all set values.
  • the pixel circuit provided by the embodiment of the present application suppresses the threshold voltage drift of the driving transistor in the pixel circuit, is less affected by the threshold voltage fluctuation of the driving transistor M0, and the output driving current is relatively stable, thus improving the performance of the display panel. Display quality.
  • the arrangement of the second control writing unit 240 is similar to the previous embodiments, and will not be described again.
  • FIG. 16 is a schematic diagram of another pixel circuit provided by an embodiment of the present application.
  • the second electrode (drain D) of the driving transistor M0 is connected to the first power supply voltage VDD, and the first power supply voltage VDD is multiplexed into a first fixed voltage V1 to reduce the number of signal lines.
  • the fourth control writing unit 260 includes a thirteenth transistor M13 , the gate of the thirteenth transistor M13 is connected to the thirteenth scanning signal S13 , The first electrode of the thirteenth transistor M13 is electrically connected to the second gate BG, and the second electrode of the thirteenth transistor M13 is connected to the first fixed voltage V1.
  • FIG. 17 is a schematic diagram of the driving timing of yet another pixel circuit provided by an embodiment of the present application.
  • each transistor is an N-type transistor.
  • the driving method of the pixel circuit includes: a threshold control stage T1, a data writing stage T2 and a light emitting stage T3, wherein the threshold control stage T1 includes a first sub-stage T11 and a second sub-stage T12.
  • the ninth scanning signal S9, the tenth scanning signal S10 and the thirteenth scanning signal S13 are all high level, and the fifth scanning signal S5 is low level.
  • the fifth transistor M5 is turned off under the control of the fifth scan signal S5, and the other transistors are all turned on, that is, the ninth transistor M9, the tenth transistor M10, and the thirteenth transistor M13 are all turned on.
  • the ninth transistor M9 switches the first reference voltage Vref1 is written into the first gate G; the tenth transistor M10 writes the second reference voltage Vref2 into the first electrode (source S) of the driving transistor M0; the thirteenth transistor M13 writes the first power supply voltage VDD into the second gate Extremely BG.
  • the ninth scan signal S9 and the tenth scan signal S10 switch from high level to low level, and other scan signals maintain the state of the first sub-stage T11.
  • the fifth transistor M5 remains in an off state; the ninth transistor M9 switches from the on state to the off state under the control of the ninth scan signal S9; the tenth transistor M10 switches from the on state under the control of the tenth scan signal S10 Switch to disconnected state.
  • the voltage difference V GS between the first gate G and the first electrode (source S) of the driving transistor M0 is maintained by the first capacitor Cst1.
  • the thirteenth transistor M13 is in a conductive state, connecting the second electrode (drain) of the driving transistor M0 and the second gate electrode BG.
  • the driving transistor M0 is self-conductive, and the voltage of its second gate BG is discharged through the driving transistor M0, and its voltage gradually decreases until the driving transistor M0 is turned off.
  • the threshold voltage Vth of the driving transistor M0 is adjusted to the preset threshold voltage Vth0.
  • the ninth scanning signal S9 and the thirteenth scanning signal S13 are low level, and the tenth scanning signal S10 and the fifth scanning signal S5 are both high level.
  • the ninth scanning signal S9, the tenth scanning signal S10, the thirteenth scanning signal S13 and the fifth scanning signal S5 are all low level.
  • the driving transistor M0 generates a driving current in response to the voltage of the first gate G. Among them, the driving current
  • K K*(Vdata-Vref1) 2 .
  • K is related to the size and mobility of the driving transistor M0, which is determined by the manufacturing process;
  • Vdata and Vref1 are both set values.
  • the pixel circuit provided by the embodiment of the present application suppresses the threshold voltage drift of the driving transistor in the pixel circuit, is less affected by the fluctuation of the threshold voltage of the driving transistor M0, and is less affected by the fluctuation of the first power supply voltage VDD. ;
  • the output driving current is relatively stable, thereby improving the display quality of the display panel.
  • the data writing module 300 is electrically connected to the first pole (source S) of the driving transistor M0; the data writing module 300 is electrically connected to the first electrode (source S) of the driving transistor M0; The module 300 is arranged to write the data voltage Vdata to the first pole (source S) of the drive transistor M0.
  • the relationship between the first reference voltage Vref1, the second reference voltage Vref2, the first power supply voltage VDD and the second power supply voltage VSS is similar to that in the previous embodiments, and will not be repeated here. Repeat.
  • the driving transistor M0 is prevented from self-conducting by setting the magnitude relationship between the first reference voltage Vref1, the second reference voltage Vref2, the first power supply voltage VDD, and the second power supply voltage VSS.
  • the light-emitting module 600 mis-communicates, the problem occurs. This arrangement is beneficial to reducing the number of transistors in the pixel circuit.
  • FIG. 18 is a schematic diagram of yet another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit further includes a light emission control module 700 .
  • the light emitting control module 700 is connected between the first electrode (source electrode S) of the driving transistor M0 and the light emitting module 600 .
  • the light-emitting control module 700 is configured to disconnect the driving transistor M0 and the light-emitting module 600 during the threshold control stage to ensure that the driving transistor M0 is during self-conduction and avoid false turn-on of the light-emitting module 600.
  • the lighting control module 700 includes a fourteenth transistor M14 .
  • the gate of the fourteenth transistor M14 is connected to the fourteenth scanning signal S14.
  • the first electrode of the fourteenth transistor M14 is electrically connected to the first electrode (source S) of the driving transistor M0.
  • the second pole of the fourteenth transistor M14 is electrically connected to the light emitting module 600 .
  • Such arrangement makes the structure of the lighting control module 700 simple and easy to implement.
  • FIG. 19 is a schematic diagram of the driving timing of yet another pixel circuit provided by an embodiment of the present application. 18 and 19, what is different from the previous embodiments is that during the threshold control phase T1 and the data writing phase T2, the fourteenth scan signal S14 is low level, and the fourteenth transistor M14 is in the fourteenth scan signal S14. is turned off under the control of the driving transistor M0 to prevent the current generated by the driving transistor M0 from flowing into the light-emitting module 600 .
  • the fourteenth scan signal S14 is high level
  • the fourteenth transistor M14 is turned on under the control of the fourteenth scan signal S14
  • the drive transistor M0 generates a drive current in response to the voltage of the first gate G.
  • the driving transistor M0 is an N-type transistor as an example for description, which does not limit the present application.
  • the driving transistor M0 can also be set as a P-type transistor, which can be set as needed in actual applications.
  • FIG. 20 is a schematic flowchart of a driving method for a pixel circuit provided by an embodiment of the present application. Referring to Figure 20, the driving method includes the following steps:
  • the threshold voltage control module writes the preset voltage into the first gate and the second gate respectively, and controls the drive transistor to adjust its threshold voltage to the preset threshold voltage in the self-conduction state.
  • the data writing module writes the data voltage into the driving transistor.
  • the driving module In the light-emitting stage, the driving module generates a driving current in response to the voltage of the first gate.
  • the embodiment of the present application executes the threshold control phase and the data writing phase separately. Compared with executing the threshold compensation process and the data writing process at the same time, it is beneficial to shorten the duration of the threshold control phase, thereby helping to improve high-resolution images.
  • Rate display panel refresh frequency Especially for driving transistors using metal oxides, their mobility is low and the compensation process takes a relatively long time.
  • the driving method provided by the embodiments of the present application has a better effect on improving the refresh frequency of the display panel.
  • the driving methods are described for different pixel circuits. These driving methods can all be considered as the driving methods of the pixel circuit provided by the embodiments of the present application. Repeated content will not be repeated here.
  • An embodiment of the present application also provides a display panel, including a pixel circuit as provided in any embodiment of the present application.
  • the technical principles are similar and will not be described again.

Abstract

本申请公开了一种像素电路及其驱动方法、显示面板。像素电路包括驱动模块，驱动模块包括驱动晶体管；驱动晶体管为双栅晶体管，包括第一栅极和第二栅极；驱动晶体管设置为响应第二栅极的电压对驱动晶体管的阈值电压进行调控，以及响应第一栅极的电压而产生驱动电流。像素电路还包括阈值电压调控模块，与驱动模块电连接；阈值电压调控模块设置为将预设电压分别写入第一栅极和第二栅极，调控驱动晶体管的阈值电压为预设阈值电压。

Description

像素电路及其驱动方法、显示面板
本申请要求在2022年8月30日提交中国专利局、申请号为202211059032.X的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如涉及一种像素电路及其驱动方法、显示面板。
背景技术
随着显示技术的不断发展，人们对显示面板的要求越来越高，尤其是显示面板的显示画质，始终是人们不断追求的目标之一。在显示面板中，采用像素电路驱动发光器件进行显示，因此像素电路输出信号的稳定性成为影响显示画质的重要因素。然而，像素电路中的驱动晶体管存在阈值电压漂移的问题，使得阈值补偿效果较差，影响了显示面板的画质提升。
发明内容
本申请提供了一种像素电路及其驱动方法、显示面板，以抑制像素电路中驱动晶体管的阈值电压漂移，提升阈值补偿效果，从而提升显示面板的显示画质。
本申请提供了一种像素电路，包括：
驱动模块，包括驱动晶体管；所述驱动晶体管为双栅晶体管，包括第一栅极和第二栅极；所述驱动晶体管设置为响应所述第二栅极的电压对所述驱动晶体管的阈值电压进行调控，以及响应所述第一栅极的电压而产生驱动电流；
阈值电压调控模块，与所述驱动模块电连接；所述阈值电压调控模块设置为将预设电压分别写入所述第一栅极和所述第二栅极，调控所述驱动晶体管的阈值电压为预设阈值电压；
数据写入模块，与所述驱动模块电连接；所述数据写入模块设置为将数据电压写入所述驱动晶体管；
第一存储模块，与所述驱动模块电连接；所述第一存储模块设置为存储所述第一栅极的电压；
第二存储模块，与所述驱动模块电连接；所述第二存储模块设置为存储所述第二栅极的电压。
本申请还提供了一种像素电路的驱动方法，采用如本申请任意实施例所述的像素电路，所述驱动方法包括：
在阈值调控阶段，所述阈值电压调控模块将预设电压分别写入所述第一栅极和所述第二栅极，控制所述驱动晶体管在自导通状态下调控其阈值电压为预设阈值电压；
在数据写入阶段，所述数据写入模块将数据电压写入所述驱动晶体管；
在发光阶段，所述驱动模块响应所述第一栅极的电压而产生驱动电流。
本申请还提供了一种显示面板，包括如本申请任意实施例所述的像素电路。
本申请实施例设置驱动模块包括驱动晶体管，驱动晶体管为双栅晶体管；并对应驱动晶体管的设置方式，设置阈值电压调控模块与驱动模块电连接，阈值电压调控模块设置为将预设电压分别写入第一栅极和第二栅极，以及调控驱动晶体管的阈值电压为预设阈值电压；第二存储模块与驱动模块电连接，设置为存储第二栅极的电压。因此，本申请实施例实现了主动调控驱动晶体管的阈值电压，从而抑制了驱动晶体管的阈值电压发生漂移的情况。与被动补偿阈值电压的方式相比，本申请实施例提升了像素电路阈值补偿效果，从而提升了显示面板的显示画质。
附图说明
图1为本申请实施例提供的一种像素电路的示意图；
图2为本申请实施例提供的一种双栅晶体管的IDVG特性曲线的示意图；
图3为本申请实施例提供的另一种像素电路的示意图；
图4为本申请实施例提供的又一种像素电路的示意图；
图5为本申请实施例提供的一种像素电路的驱动时序的示意图；
图6为本申请实施例提供的又一种像素电路的示意图；
图7为本申请实施例提供的又一种像素电路的示意图；
图8为本申请实施例提供的另一种像素电路的驱动时序的示意图；
图9为本申请实施例提供的又一种像素电路的示意图；
图10为本申请实施例提供的又一种像素电路的示意图；
图11为本申请实施例提供的又一种像素电路的驱动时序的示意图；
图12为本申请实施例提供的又一种像素电路的示意图；
图13为本申请实施例提供的又一种像素电路的驱动时序的示意图；
图14为本申请实施例提供的又一种像素电路的示意图；
图15为本申请实施例提供的又一种像素电路的示意图；
图16为本申请实施例提供的又一种像素电路的示意图；
图17为本申请实施例提供的又一种像素电路的驱动时序的示意图；
图18为本申请实施例提供的又一种像素电路的示意图；
图19为本申请实施例提供的又一种像素电路的驱动时序的示意图；
图20为本申请实施例提供的一种像素电路的驱动方法的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具 有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请实施例提供了一种像素电路。图1为本申请实施例提供的一种像素电路的示意图。参见图1，像素电路包括：驱动模块100、阈值电压调控模块200、数据写入模块300、第一存储模块400和第二存储模块500。
驱动模块100包括驱动晶体管M0；驱动晶体管M0为双栅晶体管，包括第一栅极G、第二栅极BG、第一极(源极S)和第二极(漏极D)；驱动晶体管M0设置为响应第二栅极BG的电压对其阈值电压Vth进行调控，以及响应第一栅极G的电压而产生驱动电流。
阈值电压调控模块200与驱动模块100电连接；阈值电压调控模块200设置为将预设电压分别写入第一栅极G和第二栅极BG，调控驱动晶体管M0的阈值电压Vth为预设阈值电压Vth0。示例性地，阈值电压调控模块200与驱动晶体管M0的第一栅极G和第二栅极BG均连接。
数据写入模块300与驱动模块100电连接；数据写入模块300设置为将数据电压Vdata写入驱动晶体管M0。
第一存储模块400与驱动模块100电连接；第一存储模块400设置为存储第一栅极G的电压。
第二存储模块500与驱动模块100电连接；第二存储模块500设置为存储第二栅极BG的电压。
本申请实施例将驱动晶体管M0设置为垂直型双栅晶体管，使得驱动晶体管M0的阈值电压Vth可调控。图2为本申请实施例提供的一种双栅晶体管的IDVG特性曲线的示意图。参见图2，横坐标表示驱动晶体管M0的第一栅极G和源极S之间的电压差VGS，纵坐标表示驱动晶体管M0产生的驱动电流IDS。图2中的各条特性曲线随着驱动晶体管M0的第二栅极BG和源极S之间的电压差VBS 而发生移动。以N型晶体管为例，图2中示出了电压差VBS由-4V～+4V的变化情况。随着电压差VBS的增大，特性曲线左移，表明采用较小的电压差VGS即可导通驱动晶体管M0，即驱动晶体管M0的阈值电压Vth减小。由此可见，通过调控电压差VBS能够调控阈值电压Vth，且电压差VBS越大，阈值电压Vth越负(越小)。
示例性地，该像素电路的驱动过程包括阈值调控阶段、数据写入阶段和发光阶段。其中，在阈值调控阶段，阈值电压调控模块200将预设电压分别写入第一栅极G和第二栅极BG，控制驱动晶体管M0在自导通状态下调控其阈值电压Vth为预设阈值电压Vth0。在数据写入阶段，数据写入模块300将数据电压Vdata写入驱动晶体管M0。在发光阶段，驱动模块100响应第一栅极G的电压而产生驱动电流。
结合图2，示例性地，在第一栅极G和第二栅极BG写入预设电压后，第二栅极BG和源极S之间的电压差VBS为4V，对应由左向右的第一条特性曲线。此时，若第一栅极G和源极S之间的电压差VGS为0V，则由特性曲线可知，驱动晶体管M0处于导通状态。第二栅极BG通过自导通的驱动晶体管M0进行放电，驱动晶体管M0对应的特性曲线向右移动，从而调控驱动晶体管M0的阈值电压Vth。直至电压差VBS为0V，对应由左向右的第五条特性曲线，电压差VGS为0V时驱动晶体管M0不再导通。此时，第二存储模块500存储第二栅极BG的电压，从而存储阈值电压Vth。
由此可见，本申请实施例设置驱动模块100包括驱动晶体管M0，驱动晶体管M0为垂直型双栅晶体管；并对应驱动晶体管M0的设置方式，设置阈值电压调控模块200与驱动模块100电连接，阈值电压调控模块200设置为将预设电压分别写入第一栅极G和第二栅极BG，以调控驱动晶体管M0的阈值电压Vth为预设阈值电压Vth0；第二存储模块500与驱动模块100电连接，设置为存储第二栅极BG的电压。因此，本申请实施例实现了主动调控驱动晶体管M0的阈值电压Vth，从而抑制了驱动晶体管M0的阈值电压Vth发生漂移的情况。与被 动补偿阈值电压Vth的方式相比，本申请实施例提升了像素电路阈值补偿效果，从而提升了显示面板的显示画质。
在上述各实施例的基础上，可选地，第一栅极G和第二栅极BG互为顶栅和底栅。示例性地，若第一栅极G为顶栅，则第二栅极BG为低栅；若第一栅极G为底栅，则第二栅极BG为顶栅。
在上述各实施例中，各模块的设置方式以及组合方式有多种，下面就其中的几种进行说明，但不作为对本申请的限定。
图3为本申请实施例提供的另一种像素电路的示意图。参见图3，在本申请的一种实施方式中，可选地，阈值电压调控模块200包括：第一初始化单元210、第一调控写入单元220和第二初始化单元230。
第一初始化单元210与驱动晶体管M0的第一栅极G电连接；第一初始化单元210设置为向第一栅极G写入第一参考电压Vref1。
第一调控写入单元220与驱动晶体管M0的第二栅极BG电连接；第一调控写入单元220设置为向第二栅极BG写入第一固定电压V1。
第二初始化单元230与驱动晶体管M0的第一极电连接；第二初始化单元230设置为向驱动晶体管M0的第一极写入第二参考电压Vref2。其中，第一参考电压Vref1和第二参考电压Vref2的电压差为预设阈值电压Vth0。
其中，驱动晶体管M0为对称结构，其源极S和漏极D的定义由驱动晶体管M0的类型和电路连接关系确定。图3中示例性地示出了驱动晶体管M0为N型晶体管，在其他实施例中，还可以设置驱动晶体管M0为P型晶体管。以及，图3中示例性地示出了驱动晶体管M0的第一极为源极S，第二极为漏极D，在其他实施例中，还可以设置驱动晶体管M0的第一极为漏极D，第二极为源极S。
阈值电压调控模块200的工作原理为：第一初始化单元210将第一参考电压Vref1写入第一栅极G，第二初始化单元230将第二参考电压Vref2写入驱动晶体管M0的第一极，使得驱动晶体管M0的第一栅极G和源极S之间的电压差VGS为Vref1-Vref2。第一调控写入单元220将第一固定电压V1写入第二栅极 BG，使得驱动晶体管M0的第二栅极BG和源极S之间的电压差VBS为V1-Vref2。示例性地，Vref1-Vref2＝0V，V1-Vref2＝4V。结合图2，电压差VBS＝4V，对应由左向右的第一条特性曲线；且电压差VGS＝0V，驱动晶体管M0处于导通状态。第二栅极BG通过自导通的驱动晶体管M0进行放电，电压差VBS减小，驱动晶体管M0对应的特性曲线向右移动，对应由左向右的第二条特性曲线。且电压差VGS＝0V，驱动晶体管M0仍处于导通状态，直至电压差VBS＝0V，对应由左向右的第五条特性曲线；电压差VGS＝0V使得驱动晶体管M0不再导通，第二栅极BG不再放电。
因此，当驱动晶体管M0截止时，电压差VGS＝阈值电压Vth＝电压差VBS＝Vref1-Vref2，阈值电压调控模块200能够实现调控驱动晶体管M0的阈值电压Vth的功能，且第一参考电压Vref1和第二参考电压Vref2的电压差为预设阈值电压Vth0。
继续参见图3，在本申请的一种实施方式中，可选地，第一存储模块400连接于驱动晶体管M0的第一栅极G和第一极(源极S)之间，设置为存储电压差VGS，以存储第一栅极G的电压。
在本申请的一种实施方式中，可选地，第二存储模块500连接于驱动晶体管M0的第二栅极BG和第一极(源极S)之间，设置为存储电压差VBS，以存储第二栅极BG的电压。
在本申请的一种实施方式中，可选地，数据写入模块300与驱动晶体管M0的第一栅极G电连接；数据写入模块300设置为向第一栅极G(即第一存储模块400)写入数据电压Vdata。
在本申请的一种实施方式中，可选地，第二初始化单元230设置于驱动模块100和发光模块600之间，例如设置于第一极(源极S)和发光模块600之间。
继续参见图3，示例性地，该像素电路的驱动方法包括：阈值调控阶段、数据写入阶段和发光阶段，其中，阈值调控阶段包括第一子阶段和第二子阶段。
在阈值调控阶段的第一子阶段，第一初始化单元210向第一栅极G写入第 一参考电压Vref1；第二初始化单元230向驱动晶体管M0的第一极(源极S)写入第二参考电压Vref2；第一调控写入单元220向第二栅极BG写入第一固定电压V1。
在阈值调控阶段的第二子阶段，驱动晶体管M0自导通，以调控驱动晶体管M0的阈值电压Vth为预设阈值电压Vth0；预设阈值电压Vth0为第一参考电压Vref1和第二参考电压Vref2的差值，即Vth0＝Vref1-Vref2。
在数据写入阶段，数据写入模块300将数据电压Vdata写入第一栅极G；第二初始化单元230向驱动晶体管M0的第一极(源极S)写入第二参考电压Vref2，以确保在发光阶段，电压差VGS＝Vdata-Vref2。
在发光阶段，驱动模块100响应第一栅极G的电压而产生驱动电流。其中，驱动电流I＝K*(VGS-Vth0)2＝K*(Vdata-Vref2-Vth0)2。K与驱动晶体管M0的大小和迁移率相关，由制备工艺确定；Vdata、Vref2和Vth0均为设定值。示例性地，若Vref1＝Vref2，Vth0＝0V，则驱动电流I＝K*(Vdata-Vref2)2＝K*(Vdata-Vref1)2。其中，Vth0＝Vref1-Vref2，因此，驱动电流的公式还可以直接改写为I＝K*(Vdata-Vref2-(Vref1-Vref2))2＝K*(Vdata-Vref1)2。在该公式中，Vdata和Vref1均为设定值。综上，无论采用哪种公式，得到的驱动电流均由设定值决定，不受阈值电压的影响。
由此可见，本申请实施例提供的像素电路抑制了像素电路中驱动晶体管的阈值电压漂移，受驱动晶体管M0的阈值电压波动的影响较小；以及受第一电源电压VDD的波动的影响较小；输出的驱动电流较为稳定，从而提升了显示面板的显示画质。
下面对图3所示像素电路中各模块的设置方式进行说明。图4为本申请实施例提供的又一种像素电路的示意图。参见图4，在本申请的一种实施方式中，可选地，第一初始化单元210包括第一晶体管M1。第一晶体管M1的栅极接入第一扫描信号S1，第一晶体管M1的第一极与第一栅极G电连接，第一晶体管M1的第二极接入第一参考电压Vref1。这样设置，使得第一初始化单元210的 电路结构简单，易于实现。
在本申请的一种实施方式中，可选地，第一调控写入单元220包括第二晶体管M2，第二晶体管M2的栅极接入第二扫描信号S2，第二晶体管M2的第一极与第二栅极BG电连接，第二晶体管M2的第二极接入第一固定电压V1。可选地，驱动晶体管M0的第二极(漏极D)接入第一电源电压VDD，第一电源电压VDD复用为第一固定电压V1，即第二晶体管M2的第二极接入第一电源电压VDD。这样设置，使得第一调控写入单元220的电路结构简单，易于实现。
在本申请的一种实施方式中，可选地，第二初始化单元230包括：第三晶体管M3和第四晶体管M4。第三晶体管M3的栅极接入第三扫描信号S3，第三晶体管M3的第一极接入第二参考电压Vref2，第三晶体管M3的第二极与第四晶体管M4的第一极电连接，第四晶体管M4的栅极接入第四扫描信号S4，第四晶体管M4的第二极与驱动晶体管M0的第一极(源极S)电连接。这样设置，使得第二初始化单元230的电路结构简单，易于实现。
在本申请的一种实施方式中，可选地，数据写入模块300包括第五晶体管M5，第五晶体管M5的栅极接入第五扫描信号S5，第五晶体管M5的第一极接入数据电压Vdata，第五晶体管M5的第二极与驱动晶体管M0的第一栅极G电连接。这样设置，使得数据写入模块300的电路结构简单，易于实现。
在本申请的一种实施方式中，可选地，第一存储模块400包括第一电容Cst1，第一电容Cst1的第一极与第一栅极G电连接，第一电容Cst1的第二极与驱动晶体管M0的第一极(源极S)电连接。这样设置，使得第一存储模块400的电路结构简单，易于实现。
在本申请的一种实施方式中，可选地，第二存储模块500包括第二电容Cst2，第二电容Cst2的第一极与第二栅极BG电连接，第二电容Cst2的第二极与驱动晶体管M0的第一极(源极S)电连接。这样设置，使得第二存储模块500的电路结构简单，易于实现。
下面结合驱动时序对图4所示的像素电路的驱动方法进行说明。图5为本 申请实施例提供的一种像素电路的驱动时序的示意图。结合图4和图5，示例性地，各晶体管均为N型晶体管，采用金属氧化物半导体工艺制备，例如可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)制备。N型晶体管在其栅极为高电平时导通，在其栅极为低电平时断开。该像素电路的驱动方法包括：阈值调控阶段T1、数据写入阶段T2和发光阶段T3，其中，阈值调控阶段T1包括第一子阶段T11和第二子阶段T12。
在阈值调控阶段T1的第一子阶段T11，第一扫描信号S1、第二扫描信号S2、第三扫描信号S3和第四扫描信号S4均为高电平，第五扫描信号S5为低电平。第五晶体管M5在第五扫描信号S5的控制下断开，其他晶体管均导通，即第一晶体管M1～第四晶体管M4均导通。第一晶体管M1将第一参考电压Vref1写入第一栅极G；第三晶体管M3和第四晶体管M4将第二参考电压Vref2写入驱动晶体管M0的第一极(源极S)；第二晶体管M2将第一电源电压VDD写入第二栅极BG。驱动晶体管M0的第一栅极G和第一极(源极S)之间的电压差VGS＝Vref1-Vref2，第二栅极BG和源极S之间的电压差VBS＝VDD-Vref2。
在阈值调控阶段T1的第二子阶段T12，第一扫描信号S1和第四扫描信号S4由高电平切换为低电平，其他扫描信号保持第一子阶段T11的状态。第五晶体管M5保持断开的状态；第一晶体管M1在第一扫描信号S1的控制下由导通状态切换为断开状态；第四晶体管M4在第四扫描信号S4的控制下由导通状态切换为断开状态。驱动晶体管M0的第一栅极G和第一极(源极S)之间的电压差VGS由第一电容Cst1保持。驱动晶体管M0自导通，其第一极(源极S)的电压逐渐抬升，直至驱动晶体管M0截止，电压差VGS＝阈值电压Vth＝电压差VBS＝Vref1-Vref2。实现了调控驱动晶体管M0的阈值电压Vth为第一参考电压Vref1和第二参考电压Vref2的差值。
在数据写入阶段T2，第一扫描信号S1和第二扫描信号S2为低电平、第三扫描信号S3、第四扫描信号S4和第五扫描信号S5均为高电平。第五晶体管M5在第五扫描信号S5的控制下导通，将数据电压Vdata写入第一栅极G；第 三晶体管M3和第四晶体管M4导通，将第二参考电压Vref2写入驱动晶体管M0的第一极(源极S)。这样，以确保在发光阶段T3，电压差VGS＝Vdata-Vref2。
在发光阶段T3，第一扫描信号S1、第二扫描信号S2、第三扫描信号S3和第五扫描信号S5均为低电平，第四扫描信号S4为高电平。驱动晶体管M0响应第一栅极G的电压而产生驱动电流。其中，驱动电流I＝K*(VGS-Vth0)2＝K*(Vdata-Vref2-Vth0)2＝K*(Vdata-Vref2-(Vref1-Vref2))2＝K*(Vdata-Vref1)2。K与驱动晶体管M0的大小和迁移率相关，由制备工艺确定；Vdata和Vref1均为设定值。
由此可见，本申请实施例提供的像素电路抑制了像素电路中驱动晶体管的阈值电压漂移，受驱动晶体管M0的阈值电压波动的影响较小；以及受第一电源电压VDD的波动的影响较小；输出的驱动电流较为稳定，从而提升了显示面板的显示画质。
在本申请的另一种实施方式中，可选地，在阈值调控阶段T1的第二子阶段T12，还可以设置第三扫描信号S3与第四扫描信号S4的变化相同，由高电平切换为低电平。第三晶体管M3在第三扫描信号S3的控制下由导通状态切换为断开状态，第二参考电压Vref2不再写入发光器件D1的阳极。驱动晶体管M0的第一栅极G和第一极(源极S)之间的电压差VGS由第一电容Cst1保持。驱动晶体管M0自导通，其第一极(源极S)的电压逐渐抬升，直至驱动晶体管M0截止，电压差VGS＝阈值电压Vth＝电压差VBS＝Vref1-Vref2。实现了调控驱动晶体管M0的阈值电压Vth为第一参考电压Vref1和第二参考电压Vref2的差值。由此可见，在阈值调控阶段T1的第二子阶段T12，第三晶体管M3是否导通对像素电路的工作过程没有影响。
在上述各实施例中，由驱动电流的计算公式可知，驱动电流的大小与第一参考电压Vref1相关，而与第二参考电压Vref2无关，但是由前述分析可知，第一参考电压Vref1和第二参考电压Vref2的差值决定了驱动晶体管M0的阈值电压。为了确保像素电路正常工作，仍然需要对第一参考电压Vref1和第二参考电 压Vref2的大小关系进行限定。可选地，各晶体管均为N型晶体管，第一参考电压Vref1大于或等于第二参考电压Vref2，以使驱动晶体管M0的预设阈值电压Vth0大于或等于0V。示例性地，若驱动晶体管M0为N型晶体管，则驱动晶体管M0的阈值电压Vth在正常情况下大于0，且预设阈值电压Vth0为第一参考电压Vref1和第二参考电压Vref2的差值，据此，设置第一参考电压Vref1大于或等于第二参考电压Vref2有利于驱动晶体管M0正常工作。可选地，第一参考电压Vref1等于第二参考电压Vref2，以使驱动晶体管M0的预设阈值电压Vth0等于0V。这样设置，有利于将第一参考电压Vref1复用为第二参考电压Vref2，从而减少信号线的数量。
在上述各实施例的基础上，可选地，发光模块600还接入第二电源电压VSS。第一电源电压VDD大于第二参考电压Vref2；第二参考电压Vref2大于第二电源电压VSS；且第二参考电压Vref2与第二电源电压VSS的差值小于发光模块600的启亮电压。示例性地，发光模块600包括发光器件D1，发光器件D1的阳极与第四晶体管M4的第一极电连接，发光器件D1的阴极接入第二电源电压VSS。
示例性地，驱动晶体管M0导通的条件，除了电压差VGS＞阈值电压Vth，还包括漏极电压VD＞源极电压VS。其中，漏极电压VD为第一电源电压，源极电压VS为第二参考电压Vref2，因此，还需要设置第一电源电压VDD大于第二参考电压Vref2。
另外，由像素电路的驱动过程可知，在阈值调控阶段，第二参考电压Vref2通过第三晶体管M3写入了发光模块600的阳极。此时，发光模块600两端的电压差为Vref2-VSS，设置Vref2-VSS小于发光模块600的启亮电压，有利于防止发光模块600在阈值调控阶段误导通。
图6为本申请实施例提供的又一种像素电路的示意图。参见图6，在本申请的一种实施方式中，可选地，与图3不同的是，数据写入模块300与驱动晶体管M0的第一极(源极S)电连接；数据写入模块300设置为将数据电压Vdata 写入驱动晶体管M0的第一极(源极S)，数据写入模块300设置为将数据电压Vdata写入第一存储模块400。
示例性地，该像素电路的驱动方法包括：阈值调控阶段、数据写入阶段和发光阶段，其中，阈值调控阶段包括第一子阶段和第二子阶段。
在阈值调控阶段的第一子阶段，第一初始化单元210向第一栅极G写入第一参考电压Vref1；第二初始化单元230向驱动晶体管M0的第一极(源极S)写入第二参考电压Vref2；第一调控写入单元220向第二栅极BG写入第一固定电压V1。
在阈值调控阶段的第二子阶段，驱动晶体管M0自导通，以调控驱动晶体管M0的阈值电压Vth为预设阈值电压Vth0；预设阈值电压Vth0为第一参考电压Vref1和第二参考电压Vref2的差值。
在数据写入阶段，数据写入模块300将数据电压Vdata写入驱动晶体管M0的第一极(源极S)；第一初始化单元210向第一栅极G写入第一参考电压Vref1，以确保在发光阶段，电压差VGS＝Vref1-Vdata。
在发光阶段，驱动模块100响应第一栅极G的电压而产生驱动电流。其中，驱动电流I＝K*(VGS-Vth0)2＝K*(Vref1-Vdata-Vth0)2＝K*(Vdata-Vref2-(Vref1-Vref2))2＝K*(Vdata-Vref1)2。K与驱动晶体管M0的大小和迁移率相关，由制备工艺确定；Vdata和Vref1均为设定值。
由此可见，本申请实施例提供的像素电路抑制了像素电路中驱动晶体管的阈值电压漂移，受驱动晶体管M0的阈值电压波动的影响较小；以及受第一电源电压VDD的波动的影响较小；输出的驱动电流较为稳定，从而提升了显示面板的显示画质。
图7为本申请实施例提供的又一种像素电路的示意图。参见图7，与图4不同的是，数据写入模块300包括第六晶体管M6，第六晶体管M6的栅极接入第六扫描信号S6，第六晶体管M6的第一极接入数据电压Vdata，第六晶体管M6 的第二极与驱动晶体管M0的第一极电连接。
下面结合驱动时序对图7所示的像素电路的驱动方法进行说明。图8为本申请实施例提供的另一种像素电路的驱动时序的示意图。结合图7和图8，示例性地，各晶体管均为N型晶体管。该像素电路的驱动方法包括：阈值调控阶段T1、数据写入阶段T2和发光阶段T3，其中，阈值调控阶段T1包括第一子阶段T11和第二子阶段T12。
在阈值调控阶段T1的第一子阶段T11，第一扫描信号S1、第二扫描信号S2、第三扫描信号S3和第四扫描信号S4均为高电平，第六扫描信号S6为低电平。第六晶体管M6在第六扫描信号S6的控制下断开，其他晶体管均导通，即第一晶体管M1～第四晶体管M4均导通。第一晶体管M1将第一参考电压Vref1写入第一栅极G；第三晶体管M3和第四晶体管M4将第二参考电压Vref2写入驱动晶体管M0的第一极(源极S)；第二晶体管M2将第一电源电压VDD写入第二栅极BG。驱动晶体管M0的第一栅极G和第一极(源极S)之间的电压差VGS＝Vref1-Vref2，第二栅极BG和源极S之间的电压差VBS＝VDD-Vref2。
在阈值调控阶段T1的第二子阶段T12，第一扫描信号S1、第三扫描信号和第四扫描信号S4由高电平切换为低电平，第二扫描信号S2和第六扫描信号S6保持第一子阶段T11的状态。第六晶体管M6保持断开的状态；第一晶体管M1在第一扫描信号S1的控制下由导通状态切换为断开状态；第三晶体管M3在第三扫描信号S3的控制下由导通状态切换为断开状态；第四晶体管M4在第四扫描信号S4的控制下由导通状态切换为断开状态。驱动晶体管M0的第一栅极G和第一极(源极S)之间的电压差VGS由第一电容Cst1保持。驱动晶体管M0自导通，其第一极(源极S)的电压逐渐抬升，直至驱动晶体管M0截止，电压差VGS＝阈值电压Vth0＝电压差VBS＝Vref1-Vref2。实现了调控驱动晶体管M0的阈值电压Vth为第一参考电压Vref1和第二参考电压Vref2的差值。
在数据写入阶段T2，第一扫描信号S1和第六扫描信号S6为高电平，第二扫描信号S2、第三扫描信号S3和第四扫描信号S4均为低电平。第六晶体管 M6在第六扫描信号S6的控制下导通，将数据电压Vdata写入驱动晶体管M0的第一极(源极S)；第一晶体管M1导通，将第一参考电压Vref1写入第一栅极G。这样，以确保在发光阶段T3，电压差VGS＝Vref1-Vdata。
在发光阶段T3，第一扫描信号S1、第二扫描信号S2、第三扫描信号S3和第六扫描信号S6均为低电平，第四扫描信号S4为高电平。驱动晶体管M0响应第一栅极G的电压而产生驱动电流。其中，驱动电流I＝K*(VGS-Vth0)2＝K*(Vref1-Vdata-Vth0)2＝K*(Vref1-Vdata-(Vref1-Vref2))2＝K*(Vref2-Vdata)2。K与驱动晶体管M0的大小和迁移率相关，由制备工艺确定；Vdata和Vref2均为设定值。
由此可见，本申请实施例提供的像素电路抑制了像素电路中驱动晶体管M0的阈值电压漂移，受驱动晶体管M0的阈值电压波动的影响较小；以及受第一电源电压VDD的波动的影响较小；输出的驱动电流较为稳定，从而提升了显示面板的显示画质。
在上述各实施例的基础上，可选地，第一参考电压Vref1、第二参考电压Vref2、第一电源电压VDD以及第二电源电压VSS之间的大小关系与前述实施例类似，这里不再赘述。
图9为本申请实施例提供的又一种像素电路的示意图。参见图9，在本申请的一种实施方式中，可选地，阈值电压调控模块200包括：第二调控写入单元240和第三调控写入单元250。
第二调控写入单元240与驱动晶体管M0的第一栅极G电连接，以及与驱动晶体管M0的第一极(源极S)电连接；第二调控写入单元240设置为向驱动晶体管M0写入预设阈值电压Vth0。示例性地，该预设阈值电压Vth0以电压差的形式保存于驱动晶体管M0的第一栅极G和源极S之间，即驱动晶体管M0的第一栅极G和源极S之间的电压差VGS为Vth0。
第三调控写入单元250与驱动晶体管M0的第二极(漏极D)电连接，以及与驱动晶体管M0的第二栅极BG电连接；第三调控写入单元250设置为向第二 栅极BG写入第一固定电压V1，以及向驱动晶体管M0的第二极(漏极D)写入第一电源电压VDD，第一电源电压VDD复用为第一固定电压V1。
阈值电压调控模块200的工作原理为：第二调控写入单元240将预设阈值电压Vth0写入驱动晶体管M0，使得驱动晶体管M0的第一栅极G和源极S之间的电压差VGS为Vth0。第三调控写入单元250将第一电源电压VDD写入第二栅极BG，使得驱动晶体管M0的第二栅极BG和源极S之间的电压差VBS为VDD-Vth0，其值根据第二调控写入单元240的设置方式确定。
示例性地，写入驱动晶体管M0的预设阈值电压Vth0预设为0V，即VGS＝Vth0＝0V；写入驱动晶体管M0的第二栅极BG和源极S之间的电压差VBS预设为4V，即VBS＝4V。结合图2，VBS＝4V对应由左向右的第一条特性曲线；且电压差VGS＝0V，驱动晶体管M0处于导通状态。第二栅极BG通过自导通的驱动晶体管M0进行放电，电压差VBS减小，驱动晶体管M0对应的特性曲线向右移动，对应由左向右的第二条特性曲线。且电压差VGS＝0V，驱动晶体管M0仍处于导通状态，直至电压差VBS＝0V，对应由左向右的第五条特性曲线；电压差VGS＝0V使得驱动晶体管M0不再导通，第二栅极BG不再放电。因此，当驱动晶体管M0截止时，电压差VBS＝预设阈值电压Vth0，此时，驱动晶体管M0的阈值电压为预设阈值电压Vth0。阈值电压调控模块200能够实现调控驱动晶体管M0的阈值电压Vth的功能。
继续参见图9，第一存储模块400、第二存储模块500和数据写入模块300的设置方式与前述实施例类似。示例性地，数据写入模块300的设置方式也有两种，即数据写入模块300与第一栅极G电连接，或者数据写入模块300与驱动晶体管M0的第一极(源极S)电连接。下面以数据写入模块300与第一栅极G电连接为例对图9所示的像素电路的驱动方法进行说明。
示例性地，该像素电路的驱动方法包括：阈值调控阶段、数据写入阶段和发光阶段，其中，阈值调控阶段包括第一子阶段和第二子阶段。
在阈值调控阶段的第一子阶段，第二调控写入单元240将预设阈值电压Vth0 写入驱动晶体管M0；第三调控写入单元250向第二栅极BG和驱动晶体管M0的第二极(源极D)写入第一电源电压VDD。
在阈值调控阶段的第二子阶段，第二调控写入单元240持续将预设阈值电压Vth0写入驱动晶体管M0并维持不变；第一电源电压VDD不再写入第二栅极BG和驱动晶体管M0的第二极(源极D)，但第二栅极BG和驱动晶体管M0的第二极(源极D)仍导通，以使驱动晶体管M0自导通，以调控驱动晶体管M0的阈值电压Vth为预设阈值电压Vth0。
在数据写入阶段，数据写入模块300将数据电压Vdata写入第一栅极G。其中，数据电压Vdata的写入方式根据第二调控写入单元240的设置方式确定。
在发光阶段，驱动模块100响应第一栅极G的电压而产生驱动电流。其中，驱动电流I＝K*(VGS-Vth0)2＝K*(Vdata-VS-Vth0)2。K与驱动晶体管M0的大小和迁移率相关，由制备工艺确定；Vdata、VS和Vth0均为设定值。
由此可见，本申请实施例提供的像素电路抑制了像素电路中驱动晶体管的阈值电压漂移，受驱动晶体管M0的阈值电压波动的影响较小，输出的驱动电流较为稳定，从而提升了显示面板的显示画质。
在上述实施例的基础上，下面对第三调控写入单元250和第二调控写入单元240的设置方式进行说明，但不作为对本申请的限定。图10为本申请实施例提供的又一种像素电路的示意图。参见图10，在本申请的一种实施方式中，可选地，第三调控写入单元250包括：第七晶体管M7和第八晶体管M8。
第七晶体管M7的栅极接入第七扫描信号S7，第七晶体管M7的第一极与第二栅极BG电连接，第七晶体管M7的第二极与驱动晶体管M0的第二极(漏极D)电连接。第八晶体管M8的栅极接入第八扫描信号S8，第八晶体管M8的第一极与驱动晶体管M0的第二极(漏极D)电连接，第八晶体管M8的第二极接入第一电源电压VDD。这样设置，使得第三调控写入单元250的电路结构简单，易于实现。
继续参见图10，在本申请的一种实施方式中，可选地，第二调控写入单元 240包括：第九晶体管M9和第十晶体管M10。第九晶体管M9的栅极接入第九扫描信号S9，第九晶体管M9的第一极与第一栅极G电连接，第九晶体管M9的第二极接入第一参考电压Vref1。第十晶体管M10的栅极接入第十扫描信号S10，第十晶体管M10的第一极与驱动晶体管M0的第一极(源极S)电连接，第十晶体管M10的第二极接入第二参考电压Vref2。其中，第一参考电压Vref1和第二参考电压Vref2的电压差为预设阈值电压Vth0。这样设置，使得第二调控写入单元240的电路结构简单，易于实现。
可选地，第七扫描信号S7复用为第九扫描信号S9，以减少信号线的数量。
下面结合驱动时序对图10所示的像素电路的驱动方法进行说明。图11为本申请实施例提供的又一种像素电路的驱动时序的示意图。结合图10和图11，示例性地，各晶体管均为N型晶体管。该像素电路的驱动方法包括：阈值调控阶段T1、数据写入阶段T2和发光阶段T3，其中，阈值调控阶段T1包括第一子阶段T11和第二子阶段T12。
在阈值调控阶段的第一子阶段T11，第七扫描信号S7(第九扫描信号S9)、第八扫描信号S8和第十扫描信号S10均为高电平，第五扫描信号S5为低电平。第五晶体管M5在第五扫描信号S5的控制下断开，其他晶体管均导通，即第七晶体管M7～第十晶体管M10均导通。第九晶体管M9将第一参考电压Vref1写入第一栅极G；第十晶体管M10将第二参考电压Vref2写入驱动晶体管M0的第一极(源极S)；第七晶体管M7和第八晶体管M8将第一电源电压VDD写入第二栅极BG。驱动晶体管M0的第一栅极G和第一极(源极S)之间的电压差VGS＝Vref1-Vref2，第二栅极BG和源极S之间的电压差VBS＝VDD-Vref2。
在阈值调控阶段T1的第二子阶段T12，第八扫描信号S8由高电平切换为低电平，其他扫描信号保持第一子阶段T11的状态。第五晶体管M5保持断开的状态；第八晶体管M8在第八扫描信号S8的控制下由导通状态切换为断开状态。第九晶体管M9持续将第一参考电压Vref1写入第一栅极G；第十晶体管M10持续将第二参考电压Vref2写入驱动晶体管M0的第一极(源极S)；以使 驱动晶体管M0的第一栅极G和第一极(源极S)之间保持电压差VGS＝Vref1-Vref2。第七晶体管M7处于导通状态，连通驱动晶体管M0的第二极(漏极)和第二栅极BG。驱动晶体管M0自导通，其第二栅极BG的电压通过驱动晶体管M0进行放电，其电压逐渐降低，直至驱动晶体管M0截止，预设阈值电压Vth0＝电压差VBS＝Vref1-Vref2。实现了调控驱动晶体管M0的阈值电压Vth为预设阈值电压Vth0。
在数据写入阶段T2，第七扫描信号S7(第九扫描信号S9)和第八扫描信号S8为低电平、第十扫描信号S10和第五扫描信号S5均为高电平。第五晶体管M5在第五扫描信号S5的控制下导通，将数据电压Vdata写入第一栅极G；第十晶体管M10导通，将第二参考电压Vref2写入驱动晶体管M0的第一极(源极S)。这样，以确保在发光阶段T3，电压差VGS＝Vdata-Vref2。
在发光阶段T3，第七扫描信号S7(第九扫描信号S9)、第十扫描信号S10和第五扫描信号S5均为低电平，第八扫描信号S8为高电平。第八晶体管M8导通，驱动晶体管M0响应第一栅极G的电压而产生驱动电流。其中，驱动电流I＝K*(VGS-Vth0)2＝K*(Vdata-Vref2-Vth0)2＝K*(Vdata-Vref2-(Vref1-Vref2))2＝K*(Vdata-Vref1)2。K与驱动晶体管M0的大小和迁移率相关，由制备工艺确定；Vdata和Vref1均为设定值。
由此可见，本申请实施例提供的像素电路抑制了像素电路中驱动晶体管的阈值电压漂移，受驱动晶体管M0的阈值电压波动的影响较小；以及受第一电源电压VDD的波动的影响较小；输出的驱动电流较为稳定，从而提升了显示面板的显示画质。
在本申请的另一种实施方式中，可选地，第七扫描信号S7和第九扫描信号S9分开设置，在阈值调控阶段T1的第二子阶段T12，还可以设置第八扫描信号S8、第九扫描信号S9和第十扫描信号S10均由高电平切换为低电平，其他扫描信号保持第一子阶段T11的状态。第五晶体管M5保持断开的状态；第八晶体 管M8在第八扫描信号S8的控制下由导通状态切换为断开状态。第九晶体管M9和第十晶体管M10由导通状态切换为断开状态，驱动晶体管M0的第一栅极G和第一极(源极S)之间的电压差VGS由第一电容Cst1保持。第七晶体管M7处于导通状态，连通驱动晶体管M0的第二极(漏极)和第二栅极BG。驱动晶体管M0自导通，其第二栅极BG的电压通过驱动晶体管M0进行放电，其电压逐渐降低，直至驱动晶体管M0截止，预设阈值电压Vth0＝电压差VBS＝Vref1-Vref2。实现了调控驱动晶体管M0的阈值电压Vth为预设阈值电压Vth0。
在本申请的另一种实施方式中，可选地，与图10所示像素电路不同的是，第七扫描信号S7和第九扫描信号S9分开设置，数据写入模块300与驱动晶体管M0的第一极(源极S)电连接；数据写入模块300设置为将数据电压Vdata写入驱动晶体管M0的第一极(源极S)。相应地，在数据写入阶段，数据写入模块300将数据电压Vdata写入驱动晶体管M0的第一极(源极S)；第九晶体管M9向第一栅极G写入第一参考电压Vref1，以确保在发光阶段，电压差VGS＝Vref1-Vdata。
在上述各实施例的基础上，可选地，第一参考电压Vref1、第二参考电压Vref2、第一电源电压VDD以及第二电源电压VSS之间的大小关系与前述实施例类似，这里不再赘述。
图12为本申请实施例提供的又一种像素电路的示意图。参见图12，与图10不同的是，第二调控写入单元240包括：第十一晶体管M11和第十二晶体管M12。第十一晶体管M11的栅极接入第十一扫描信号S11，第十一晶体管M11的第一极与第一栅极G电连接，第十一晶体管M11的第二极接入第一参考电压Vref1。第十二晶体管M12的栅极接入第十二扫描信号S12，第十二晶体管M12的第一极与驱动晶体管M0的第一极(源极S)电连接，第十二晶体管M12的第二极与第十一晶体管M11的第一极电连接；其中，预设阈值电压Vth0为0。可选地，第十一扫描信号S11复用为第十二扫描信号S12，以减少信号线的数量。
下面结合驱动时序对图12所示的像素电路的驱动方法进行说明。图13为 本申请实施例提供的又一种像素电路的驱动时序的示意图。结合图12和图13，示例性地，各晶体管均为N型晶体管。该像素电路的驱动方法包括：阈值调控阶段T1、数据写入阶段T2和发光阶段T3，其中，阈值调控阶段T1包括第一子阶段T11和第二子阶段T12。
在阈值调控阶段的第一子阶段T11，第七扫描信号S7(第十一扫描信号S11/第十二扫描信号S12)和第八扫描信号S8均为高电平，第五扫描信号S5为低电平。第五晶体管M5在第五扫描信号S5的控制下断开，其他晶体管均导通，即第七晶体管M7、第八晶体管M8、第十一晶体管M11和第十二晶体管M12均导通。第十一晶体管M11将第一参考电压Vref1写入第一栅极G；第十二晶体管M12将第一参考电压Vref1写入驱动晶体管M0的第一极(源极S)；第七晶体管M7和第八晶体管M8将第一电源电压VDD写入第二栅极BG。驱动晶体管M0的第一栅极G和第一极(源极S)之间的电压差VGS＝0V，第二栅极BG和源极S之间的电压差VBS＝VDD-Vref1。
在阈值调控阶段T1的第二子阶段T12，第八扫描信号S8由高电平切换为低电平，其他扫描信号保持第一子阶段T11的状态。第五晶体管M5保持断开的状态；第八晶体管M8在第八扫描信号S8的控制下由导通状态切换为断开状态。第十一晶体管M11和第十二晶体管M12持续将第一参考电压Vref1写入第一栅极G和驱动晶体管M0的第一极(源极S)；以使驱动晶体管M0的第一栅极G和第一极(源极S)之间保持电压差VGS＝0V。第七晶体管M7处于导通状态，连通驱动晶体管M0的第二极(漏极)和第二栅极BG。驱动晶体管M0自导通，其第二栅极BG的电压通过驱动晶体管M0进行放电，其电压逐渐降低，直至驱动晶体管M0截止，预设阈值电压Vth0＝电压差VBS＝0V。实现了调控驱动晶体管M0的阈值电压Vth为预设阈值电压Vth0。
在数据写入阶段T2，第七扫描信号S7(第十一扫描信号S11/第十二扫描信号S12)和第八扫描信号S8为低电平、第五扫描信号S5均为高电平。第五晶体管M5在第五扫描信号S5的控制下导通，将数据电压Vdata写入第一栅极G， 第一栅极G的电压抬升Vdata-Vref1。与此同时，由于第一电容Cst1和发光器件D1的寄生电容Cd1的耦合作用，使得驱动晶体管M0的第一极(源极S)的电压抬升，抬升量为(Vdata-Vref1)*[Cst1/(Cst1+Cd1)]，此时驱动晶体管M0的第一栅极G和驱动晶体管M0的第一极(源极S)之间的电压差为VGS＝Vref1+(Vdata-Vref1)*[Cst1/(Cst1+Cd1)]。同样地，由于第二电容Cst2的耦合作用，第二栅极BG的电压抬升量与第一极(源极S)的电压抬升量相等，电压差VBS与上一阶段保持一致，因此，驱动晶体管M0的阈值电压与上一阶段保持一致。
在发光阶段T3，第七扫描信号S7(第十一扫描信号S11/第十二扫描信号S12)和第五扫描信号S5均为低电平，第八扫描信号S8为高电平。第八晶体管M8导通，驱动晶体管M0响应第一栅极G的电压而产生驱动电流。
其中，驱动电流I＝K*(VGS-Vth0)2
＝K*(Vdata-{Vref1+(Vdata-Vref1)*[Cst1/(Cst1+Cd1)]})2
＝K*[(Vdata-Vref1)*Cd1/(Cst1+Cd1)]2
K与驱动晶体管M0的大小和迁移率相关，由制备工艺确定；Vdata和Vref1均为设定值；Cst1和Cd1均为电容值。
由此可见，本申请实施例提供的像素电路抑制了像素电路中驱动晶体管的阈值电压漂移，受驱动晶体管M0的阈值电压波动的影响较小；以及受第一电源电压VDD的波动的影响较小；输出的驱动电流较为稳定，从而提升了显示面板的显示画质。
在本申请的另一种实施方式中，可选地，与图12所示的像素电路不同的是，第十一扫描信号S11和第十二扫描信号S12分开设置，数据写入模块300与驱动晶体管M0的第一极(源极S)电连接；数据写入模块300设置为将数据电压Vdata写入驱动晶体管M0的第一极(源极S)。在数据写入阶段，数据写入模块300将数据电压Vdata写入驱动晶体管M0的第一极(源极S)；第十一晶体管M11向第一栅极G写入第一参考电压Vref1，以确保在发光阶段，电压差 VGS＝Vref1-Vdata。
图14为本申请实施例提供的又一种像素电路的示意图。参见图14，在本申请的另一种实施方式中，可选地，与图12所示的像素电路不同的是，还包括第十五晶体管M15。第十五晶体管M15的栅极接入第五扫描信号S5，第十五晶体管M15的第一极接入第一参考电压Vref1，第十五晶体管M15的第二极与第一电容Cst1的第二极电连接，即第十五晶体管M15的第二极与驱动晶体管M0的第一极(源极S)电连接。其中，第十五晶体管M15与第五晶体管M5均由第五扫描信号S5控制，在像素电路的驱动过程中，第十五晶体管M15与第五晶体管M5同时导通。此时，第一电容Cst1的第一极写入数据电压Vdata，第一电容Cst1的第二极写入第一参考电压Vref1，能够避免第一电容Cst1第二极处于浮空状态而发生电压偏移，从而有利于数据电压Vdata的快速写入。
在上述各实施例的基础上，可选地，第一参考电压Vref1、第一电源电压VDD以及第二电源电压VSS之间的大小关系与前述实施例类似，这里不再赘述。
图15为本申请实施例提供的又一种像素电路的示意图。参见图15，在本申请的一种实施方式中，可选地，与前述各实施例不同的是，阈值电压调控模块200包括：第二调控写入单元240和第四调控写入单元260。其中，第四调控写入单元260与驱动晶体管M0的第二栅极BG电连接；第四调控写入单元260设置为向第二栅极BG写入第一固定电压V1。
阈值电压调控模块200的工作原理为：第二调控写入单元240将预设阈值电压Vth0写入驱动晶体管M0，使得驱动晶体管M0的第一栅极G和源极S之间的电压差VGS为Vth0。第四调控写入单元260将第一固定电压V1写入第二栅极BG，使得驱动晶体管M0的第二栅极BG和源极S之间的电压差VBS为V1-Vth0，其值根据第二调控写入单元240的设置方式确定。
示例性地，写入驱动晶体管M0的预设阈值电压Vth0为0V，即VGS＝Vth0＝0V；写入驱动晶体管M0的第二栅极BG和源极S之间的电压差VBS预设为4V，即VBS＝4V。结合图2，VBS＝4V对应由左向右的第一条特性曲线；且电压差VGS＝0V， 驱动晶体管M0处于导通状态。第二栅极BG通过自导通的驱动晶体管M0进行放电，电压差VBS减小，驱动晶体管M0对应的特性曲线向右移动，对应由左向右的第二条特性曲线。且电压差VGS＝0V，驱动晶体管M0仍处于导通状态，直至电压差VBS＝0V，对应由左向右的第五条特性曲线；电压差VGS＝0V使得驱动晶体管M0不再导通，第二栅极BG不再放电。因此，当驱动晶体管M0截止时，电压差VBS＝预设阈值电压Vth0。阈值电压调控模块200能够实现调控驱动晶体管M0的阈值电压Vth的功能。
需要说明的是，本申请实施例还对写入驱动晶体管M0的预设阈值电压Vth0、第一固定电压V1的取值大小进行设定，以确保在阈值电压调控阶段，虽然驱动晶体管M0的第一极(源极S)与发光模块600连接，且驱动晶体管M0处于导通状态，驱动晶体管M0的第一极(源极S)与第二电源电压VSS之间的电压差小于发光模块600的启亮电压。
继续参见图15，第一存储模块400、第二存储模块500和数据写入模块300的设置方式与前述实施例类似。示例性地，数据写入模块300的设置方式也有两种，即数据写入模块300与第一栅极G电连接，或者数据写入模块300与驱动晶体管M0的第一极(源极S)电连接。下面以数据写入模块300与第一栅极G电连接为例对图15所示的像素电路的驱动方法进行说明。
示例性地，该像素电路的驱动方法包括：阈值调控阶段、数据写入阶段和发光阶段，其中，阈值调控阶段包括第一子阶段和第二子阶段。
在阈值调控阶段的第一子阶段，第二调控写入单元240将预设阈值电压Vth0写入驱动晶体管M0；第四调控写入单元260向第二栅极BG写入第一固定电压V1。
在阈值调控阶段的第二子阶段，驱动晶体管M0自导通，以调控驱动晶体管M0的阈值电压Vth为预设阈值电压Vth0。
在数据写入阶段，数据写入模块300将数据电压Vdata写入第一栅极G。其中，数据电压Vdata的写入方式根据第二调控写入单元240的设置方式确定。
在发光阶段，驱动模块100响应第一栅极G的电压而产生驱动电流。其中，驱动电流I＝K*(VGS-Vth0)2＝K*(Vdata-VS-Vth0)2。K与驱动晶体管M0的大小和迁移率相关，由制备工艺确定；Vdata、VS和Vth0均为设定值。
由此可见，本申请实施例提供的像素电路抑制了像素电路中驱动晶体管的阈值电压漂移，受驱动晶体管M0的阈值电压波动的影响较小，输出的驱动电流较为稳定，从而提升了显示面板的显示画质。
在上述实施例中，第二调控写入单元240的设置方式与前述各实施例类似，不再赘述。
在上述各实施例的基础上，下面对第四调控写入单元260的设置方式进行说明，但不作为对本申请的限定。图16为本申请实施例提供的又一种像素电路的示意图。参见图16，在本申请的一种实施方式中，可选地，驱动晶体管M0的第二极(漏极D)接入第一电源电压VDD，第一电源电压VDD复用为第一固定电压V1，以减少信号线的数量。
继续参见图16，在本申请的一种实施方式中，可选地，第四调控写入单元260包括第十三晶体管M13，第十三晶体管M13的栅极接入第十三扫描信号S13，第十三晶体管M13的第一极与第二栅极BG电连接，第十三晶体管M13的第二极接入第一固定电压V1。
下面结合驱动时序对图16所示的像素电路的驱动方法进行说明。图17为本申请实施例提供的又一种像素电路的驱动时序的示意图。结合图16和图17，示例性地，各晶体管均为N型晶体管。该像素电路的驱动方法包括：阈值调控阶段T1、数据写入阶段T2和发光阶段T3，其中，阈值调控阶段T1包括第一子阶段T11和第二子阶段T12。
在阈值调控阶段的第一子阶段T11，第九扫描信号S9、第十扫描信号S10和第十三扫描信号S13均为高电平，第五扫描信号S5为低电平。第五晶体管M5在第五扫描信号S5的控制下断开，其他晶体管均导通，即第九晶体管M9、第十晶体管M10和第十三晶体管M13均导通。第九晶体管M9将第一参考电压 Vref1写入第一栅极G；第十晶体管M10将第二参考电压Vref2写入驱动晶体管M0的第一极(源极S)；第十三晶体管M13将第一电源电压VDD写入第二栅极BG。驱动晶体管M0的第一栅极G和第一极(源极S)之间的电压差VGS＝Vref1-Vref2，第二栅极BG和源极S之间的电压差VBS＝VDD-Vref2。
在阈值调控阶段T1的第二子阶段T12，第九扫描信号S9和第十扫描信号S10由高电平切换为低电平，其他扫描信号保持第一子阶段T11的状态。第五晶体管M5保持断开的状态；第九晶体管M9在第九扫描信号S9的控制下由导通状态切换为断开状态；第十晶体管M10在第十扫描信号S10的控制下由导通状态切换为断开状态。驱动晶体管M0的第一栅极G和第一极(源极S)之间的电压差VGS由第一电容Cst1保持。第十三晶体管M13处于导通状态，连通驱动晶体管M0的第二极(漏极)和第二栅极BG。驱动晶体管M0自导通，其第二栅极BG的电压通过驱动晶体管M0进行放电，其电压逐渐降低，直至驱动晶体管M0截止，预设阈值电压Vth0＝电压差VBS＝Vref1-Vref2。实现了调控驱动晶体管M0的阈值电压Vth为预设阈值电压Vth0。
在数据写入阶段T2，第九扫描信号S9和第十三扫描信号S13为低电平、第十扫描信号S10和第五扫描信号S5均为高电平。第五晶体管M5在第五扫描信号S5的控制下导通，将数据电压Vdata写入第一栅极G；第十晶体管M10导通，将第二参考电压Vref2写入驱动晶体管M0的第一极(源极S)。这样，以确保在发光阶段T3，电压差VGS＝Vdata-Vref2。
在发光阶段T3，第九扫描信号S9、第十扫描信号S10、第十三扫描信号S13和第五扫描信号S5均为低电平。驱动晶体管M0响应第一栅极G的电压而产生驱动电流。其中，驱动电流
I＝K*(VGS-Vth0)2＝K*(Vdata-Vref2-Vth0)2
＝K*(Vdata-Vref2-(Vref1-Vref2))2
＝K*(Vdata-Vref1)2。K与驱动晶体管M0的大小和迁移率相关，由制备工艺确定；
Vdata和Vref1均为设定值。
由此可见，本申请实施例提供的像素电路抑制了像素电路中驱动晶体管的阈值电压漂移，受驱动晶体管M0的阈值电压波动的影响较小；以及受第一电源电压VDD的波动的影响较小；输出的驱动电流较为稳定，从而提升了显示面板的显示画质。
在本申请的另一种实施方式中，可选地，与图16所示像素电路不同的是，数据写入模块300与驱动晶体管M0的第一极(源极S)电连接；数据写入模块300设置为将数据电压Vdata写入驱动晶体管M0的第一极(源极S)。相应地，在数据写入阶段，数据写入模块300将数据电压Vdata写入驱动晶体管M0的第一极(源极S)；第九晶体管M9向第一栅极G写入第一参考电压Vref1，以确保在发光阶段，电压差VGS＝Vref1-Vdata。
在上述各实施例的基础上，可选地，第一参考电压Vref1、第二参考电压Vref2、第一电源电压VDD以及第二电源电压VSS之间的大小关系与前述实施例类似，这里不再赘述。
需要说明的是，在上述各实施例中，通过设置第一参考电压Vref1、第二参考电压Vref2、第一电源电压VDD以及第二电源电压VSS之间的大小关系来避免驱动晶体管M0自导通时发生发光模块600误导通的问题。这样设置，有利于减少像素电路中晶体管的数量。
在如图18所示的其他实施例中，图18为本申请实施例提供的又一种像素电路的示意图。参见图18，在上述各实施例的基础上，可选地，像素电路还包括发光控制模块700。发光控制模块700连接于驱动晶体管M0的第一极(源极S)和发光模块600之间。发光控制模块700设置为在阈值调控阶段断开驱动晶体管M0和发光模块600之间的连接，以确保驱动晶体管M0在自导通期间，避免发光模块600误导通。
继续参见图18，在本申请的一种实施方式中，可选地，发光控制模块700包括第十四晶体管M14。第十四晶体管M14的栅极接入第十四扫描信号S14，第十四晶体管M14的第一极与驱动晶体管M0的第一极(源极S)电连接，第 十四晶体管M14的第二极与发光模块600电连接。这样设置，使得发光控制模块700的结构简单，易于实现。
下面结合驱动时序对图18所示的像素电路的驱动方法进行说明。图19为本申请实施例提供的又一种像素电路的驱动时序的示意图。结合图18和图19，与前述各实施例不同的是，在阈值调控阶段T1和数据写入阶段T2，第十四扫描信号S14为低电平，十四晶体管M14在第十四扫描信号S14的控制下断开，防止驱动晶体管M0产生的电流流入发光模块600。在发光阶段T3，第十四扫描信号S14为高电平，十四晶体管M14在第十四扫描信号S14的控制下导通，驱动晶体管M0响应第一栅极G的电压而产生驱动电流。
需要说明的是，在上述各实施例中，示例性地以驱动晶体管M0为N型晶体管为例进行说明，并非对本申请的限定。在其他实施例中，还可以设置驱动晶体管M0为P型晶体管，在实际应用中可以根据需要进行设定。
本申请实施例还提供了一种像素电路的驱动方法，该驱动方法适用于如本申请任意实施例所提供的像素电路。图20为本申请实施例提供的一种像素电路的驱动方法的流程示意图。参见图20，该驱动方法包括以下步骤：
T1、在阈值调控阶段，阈值电压调控模块将预设电压分别写入第一栅极和第二栅极，控制驱动晶体管在自导通状态下调控其阈值电压为预设阈值电压。
T2、在数据写入阶段，数据写入模块将数据电压写入驱动晶体管。
T3、在发光阶段，驱动模块响应第一栅极的电压而产生驱动电流。
由此可见，本申请实施例将阈值调控阶段和数据写入阶段分开执行，与将阈值补偿过程和数据写入过程同时执行相比，有利于缩短阈值调控阶段的时长，从而有利于提升高分辨率显示面板的刷新频率。尤其是对于采用金属氧化物的驱动晶体管，其迁移率较低，补偿过程耗时相对较长，采用本申请实施例提供的驱动方法对显示面板刷新频率的改善效果更佳。
可选地，在像素电路的各实施例中，针对不同的像素电路进行了驱动方法的说明，这些驱动方法均可以认为是本申请实施例提供的像素电路的驱动方法， 重复内容此处不再赘述。
本申请实施例还提供了一种显示面板，包括如本申请任意实施例所提供的像素电路，其技术原理类似，不再赘述。
应该理解，可以使用上面所示的各种形式的流程，重新排序、增加或删除步骤。例如，本申请中记载的各步骤可以并行地执行也可以顺序地执行也可以不同的次序执行，只要能够实现本申请的技术方案所期望的结果，本文在此不进行限制。

Claims (20)

  1. 一种像素电路，包括：
    驱动模块，包括驱动晶体管；所述驱动晶体管为双栅晶体管，包括第一栅极和第二栅极；所述驱动晶体管设置为响应所述第二栅极的电压对所述驱动晶体管的阈值电压进行调控，以及响应所述第一栅极的电压而产生驱动电流；
    阈值电压调控模块，与所述驱动模块电连接；所述阈值电压调控模块设置为将预设电压分别写入所述第一栅极和所述第二栅极，调控所述驱动晶体管的阈值电压为预设阈值电压；
    数据写入模块，与所述驱动模块电连接；所述数据写入模块设置为将数据电压写入所述驱动晶体管；
    第一存储模块，与所述驱动模块电连接；所述第一存储模块设置为存储所述第一栅极的电压；
    第二存储模块，与所述驱动模块电连接；所述第二存储模块设置为存储所述第二栅极的电压。
  2. 根据权利要求1所述的像素电路，其中，所述阈值电压调控模块包括：
    第一初始化单元，与所述驱动晶体管的第一栅极电连接；所述第一初始化单元设置为向所述第一栅极写入第一参考电压；
    第一调控写入单元，与所述驱动晶体管的第二栅极电连接；所述第一调控写入单元设置为向所述第二栅极写入第一固定电压；
    第二初始化单元，与所述驱动晶体管的第一极电连接；所述第二初始化单元设置为向所述驱动晶体管的第一极写入第二参考电压；其中，所述第一参考电压和所述第二参考电压的电压差为所述预设阈值电压。
  3. 根据权利要求2所述的像素电路，其中，所述驱动晶体管的第二极接入第一电源电压，所述第一电源电压复用为所述第一固定电压。
  4. 根据权利要求2所述的像素电路，其中，所述第二初始化单元设置于所述驱动模块和发光模块之间。
  5. 根据权利要求2所述的像素电路，其中，所述第一初始化单元包括：第 一晶体管，所述第一晶体管的栅极接入第一扫描信号，所述第一晶体管的第一极与所述第一栅极电连接，所述第一晶体管的第二极接入所述第一参考电压；
    所述第一调控写入单元包括：第二晶体管，所述第二晶体管的栅极接入第二扫描信号，所述第二晶体管的第一极与所述第二栅极电连接，所述第二晶体管的第二极接入所述第一固定电压；
    所述第二初始化单元包括：第三晶体管和第四晶体管，所述第三晶体管的栅极接入第三扫描信号，所述第三晶体管的第一极接入所述第二参考电压，所述第三晶体管的第二极与所述第四晶体管的第一极电连接，所述第四晶体管的栅极接入第四扫描信号，所述第四晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均为N型晶体管，所述第一参考电压大于或等于所述第二参考电压。
  6. 根据权利要求3所述的像素电路，其中，所述发光模块还接入第二电源电压；所述第一电源电压大于所述第二参考电压；所述第二参考电压大于所述第二电源电压；且所述第二参考电压与所述第二电源电压的差值小于所述发光模块的启亮电压。
  7. 根据权利要求1-6任一项所述的像素电路，其中，所述数据写入模块与所述驱动晶体管的第一栅极电连接；所述数据写入模块设置为将所述数据电压写入所述第一栅极。
  8. 根据权利要求7所述的像素电路，其中，所述数据写入模块包括第五晶体管，所述第五晶体管的栅极接入第五扫描信号，所述第五晶体管的第一极接入所述数据电压，所述第五晶体管的第二极与所述驱动晶体管的第一栅极电连接。
  9. 根据权利要求1-6任一项所述的像素电路，其中，所述第一存储模块连接于所述驱动晶体管的第一栅极和第一极之间；
    所述数据写入模块与所述驱动晶体管的第一极电连接，所述数据写入模块设置为将所述数据电压写入所述第一存储模块。
  10. 根据权利要求9所述的像素电路，其中，所述数据写入模块包括第六晶体管，所述第六晶体管的栅极接入第六扫描信号，所述第六晶体管的第一极接入所述数据电压，所述第六晶体管的第二极与所述驱动晶体管的第一极电连接。
  11. 根据权利要求1所述的像素电路，其中，所述阈值电压调控模块包括：
    第二调控写入单元，与所述驱动晶体管的第一栅极电连接，以及与所述驱动晶体管的第一极电连接；所述第二调控写入单元设置为向所述驱动晶体管写入预设阈值电压；
    第三调控写入单元，与所述驱动晶体管的第二栅极电连接，第三调控写入单元设置为向所述第二栅极写入第一固定电压。
  12. 根据权利要求11所述的像素电路，其中，所述第三调控写入单元还与所述驱动晶体管的第二极电连接，所述驱动晶体管的第二极接入第一电源电压，所述第一电源电压复用为所述第一固定电压。
  13. 根据权利要求12所述的像素电路，其中，所述第三调控写入单元包括第七晶体管，所述第七晶体管的栅极接入第七扫描信号，所述第七晶体管的第一极与所述第二栅极电连接，所述第七晶体管的第二极与所述第一固定电压电连接或所述第七晶体管的第二极与所述驱动晶体管的第二极电连接；
    所述第三调控写入单元还包括第八晶体管，所述第八晶体管的栅极接入第八扫描信号，所述第八晶体管的第一极与所述驱动晶体管的第二极电连接，所述第八晶体管的第二极接入所述第一电源电压。
  14. 根据权利要求11-13任一项所述的像素电路，其中，所述第二调控写入单元包括：
    第九晶体管，所述第九晶体管的栅极接入第九扫描信号，所述第九晶体管的第一极与所述第一栅极电连接，所述第九晶体管的第二极接入第一参考电压；
    第十晶体管，所述第十晶体管的栅极接入第十扫描信号，所述第十晶体管 的第一极与所述驱动晶体管的第一极电连接，所述第十晶体管的第二极接入第二参考电压；其中，所述第一参考电压和所述第二参考电压的电压差为所述预设阈值电压；
    所述驱动晶体管、所述第七晶体管、所述第八晶体管、所述第九晶体管和所述第十晶体管均为N型晶体管，所述第一参考电压大于或等于所述第二参考电压。
  15. 根据权利要求11-13任一项所述的像素电路，其中，所述第二调控写入单元包括：
    第十一晶体管，所述第十一晶体管的栅极接入第十一扫描信号，所述第十一晶体管的第一极与所述第一栅极电连接，所述第十一晶体管的第二极接入第一参考电压；
    第十二晶体管，所述第十二晶体管的栅极接入第十二扫描信号，所述第十二晶体管的第一极与所述驱动晶体管的第一极电连接，所述第十二晶体管的第二极与所述第十一晶体管的第一极电连接；其中，所述预设阈值电压为0。
  16. 根据权利要求15所述的像素电路，其中，所述第十一扫描信号复用为所述第十二扫描信号。
  17. 根据权利要求15所述的像素电路，其中，所述第二调控写入单元还包括第十五晶体管，所述第十五晶体管栅极接入第五扫描信号，所述第十五晶体管的第一极接入所述第一参考电压，所述第十五晶体管的第二极与所述驱动晶体管的第一极电连接。
  18. 根据权利要求1所述的像素电路，其中，
    所述第一存储模块包括：第一电容，所述第一电容的第一极与所述第一栅极电连接，所述第一电容的第二极与所述驱动晶体管的第一极电连接；
    所述第二存储模块包括：第二电容，所述第二电容的第一极与所述第二栅极电连接，所述第二电容的第二极与所述驱动晶体管的第一极电连接。
  19. 一种像素电路的驱动方法，采用如权利要求1-18任一项所述的像素电 路，所述驱动方法包括：
    在阈值调控阶段，所述阈值电压调控模块将预设电压分别写入所述第一栅极和所述第二栅极，控制所述驱动晶体管在自导通状态下调控其阈值电压为预设阈值电压；
    在数据写入阶段，所述数据写入模块将数据电压写入所述驱动晶体管；
    在发光阶段，所述驱动模块响应所述第一栅极的电压而产生驱动电流。
  20. 一种显示面板，包括如权利要求1-18任一项所述的像素电路。
PCT/CN2023/073676 2022-08-30 2023-01-29 像素电路及其驱动方法、显示面板 WO2024045485A1 (zh)

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