WO2024044893A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024044893A1
WO2024044893A1 PCT/CN2022/115533 CN2022115533W WO2024044893A1 WO 2024044893 A1 WO2024044893 A1 WO 2024044893A1 CN 2022115533 W CN2022115533 W CN 2022115533W WO 2024044893 A1 WO2024044893 A1 WO 2024044893A1
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WO
WIPO (PCT)
Prior art keywords
layer
touch
signal
display
area
Prior art date
Application number
PCT/CN2022/115533
Other languages
English (en)
French (fr)
Inventor
屈忆
初志文
周洋
白露
代俊秀
王欣欣
张毅
张顺
陈鑫
王裕
文平
张元其
王威
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/115533 priority Critical patent/WO2024044893A1/zh
Priority to CN202280002892.1A priority patent/CN117957516A/zh
Publication of WO2024044893A1 publication Critical patent/WO2024044893A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLED Organic Light Emitting Diode, organic electroluminescent diode
  • OLED Organic Light Emitting Diode, organic electroluminescent diode
  • advantages such as all-solid-state structure, self-illumination, fast response speed, high brightness, full viewing angle, and flexible display, so it has become a very competitive and flexible display device.
  • flexible OLED products can integrate the touch function layer on the display panel. Put forward higher requirements for the working stability and reliability of OLED products.
  • Embodiments of the present disclosure provide a display panel and a display device, which can improve the working stability and reliability of display products.
  • an embodiment of the present disclosure provides a display panel having a display area and a peripheral area located at the periphery of the display area. At least one side of the peripheral area is a bonding side connected to a bonding circuit. In the The peripheral area is provided with an isolation dam at least partially surrounding the display area;
  • the display panel includes:
  • a display function layer includes a display unit located in the display area, and a plurality of display signal traces located in at least part of the peripheral area connecting the display unit;
  • the touch functional layer includes a touch pattern located in the display area and a plurality of touch signal traces located in at least part of the peripheral area, the touch signal traces are connected to the display Different layer settings for signal routing;
  • first boundary and a second boundary arranged oppositely, and a first wiring area located between the first boundary and the second boundary, and the first boundary is larger than the the second boundary is closer to the display area;
  • the touch signal wiring is arranged along the first direction and is led out from the bonding circuit and connected to the touch signal through the isolation dam and the first wiring area in turn.
  • the display signal traces are arranged along a second direction that intersects with the first direction and there is an intersection area between the orthographic projection on the substrate and the touch signal traces;
  • the display panel also includes a signal shielding layer between the touch signal traces and the display signal traces in a direction perpendicular to the substrate, and the orthographic projection of the signal shielding layer on the substrate At least partially covering the intersection area of the touch signal trace and the display signal trace in the first trace area.
  • the signal shielding layer is provided with an opening pattern, and the touch signal traces and the orthographic projection of the opening pattern on the substrate at least partially do not overlap.
  • the touch signal traces along the first direction do not coincide with the orthographic projection of the opening pattern on the substrate.
  • the opening pattern includes a plurality of openings, and at least one opening is provided in a gap between at least two adjacent touch signal traces.
  • the display unit includes an anode layer, an organic electroluminescent layer and a cathode layer.
  • the anode layer includes an anode pattern for accessing display signals, and the signal shielding layer is in the same layer as the anode pattern.
  • the material is set, and the signal shielding layer is not connected to the anode pattern.
  • the signal shielding layer is connected to a constant low DC signal or a constant high DC signal.
  • the display panel further includes: a cathode lapping pattern arranged in the same layer and with the same material as the anode pattern, and an orthographic projection between the cathode lapping pattern and the anode pattern on the substrate do not overlap and are insulated from each other, the cathode overlap pattern and the orthographic projection of the cathode layer perpendicular to the substrate are at least partially coincident and electrically connected, and the cathode layer is connected to a constant low DC signal, the The signal shielding layer is integrated with the cathode lapping pattern; and/or
  • a constant low DC signal is connected to the cathode layer, the orthographic projection of the boundary of the cathode layer close to the isolation dam on the substrate does not exceed the first boundary, and the signal shielding layer is connected close to the isolation dam.
  • One side of the first boundary has a first overlapping area that overlaps with the cathode layer, and the first overlapping area is electrically connected to the cathode layer through a first via hole.
  • the cathode bonding pattern is at least partially located on the binding side and at a transition corner between the binding side and at least another side of the substrate adjacent to the binding side. area.
  • the display panel further includes an encapsulation layer that encapsulates the display function layer, and the touch function layer is directly disposed on a side of the encapsulation layer away from the substrate;
  • the touch function layer is a flexible multi-layer on-screen touch structure.
  • the touch pattern includes a plurality of self-capacitive touch electrodes distributed in an array.
  • the film layer structure of the touch function layer includes at least two touch electrodes. electrode layer, and an insulating layer provided between the at least two touch electrode layers, at least one of the touch electrode layers is a metal mesh layer, and at least another of the touch electrode layers is a bridge metal layer, so The metal grid layer and the bridge metal layer are connected through via holes on the insulating layer to form a self-capacitive touch electrode; or
  • the touch function layer is a flexible multi-layer on-screen touch structure
  • the touch pattern includes a plurality of mutually capacitive touch electrodes distributed in an array
  • the film layer structure of the touch function layer includes at least two touch electrode layer, and an insulating layer provided between the at least two touch electrode layers, at least one of the touch electrode layers is an emitter electrode layer, and at least another of the touch electrode layers is a sensing electrode layer, and the The emitter electrode layer and the sensing electrode layer are separated by the insulating layer to form a mutual capacitive touch electrode.
  • a plurality of peripheral sources and drains are further provided between the second boundary and the display signal trace and/or between the second boundary and the binding circuit.
  • Metal traces, a constant low DC signal or a constant high DC signal is connected to the peripheral source and drain metal traces, and the signal shielding layer has a connection with the peripheral source and drain metal traces on the side close to the second boundary.
  • a second overlapping area is overlapped, and the second overlapping area is electrically connected to the peripheral source and drain metal traces through a second via hole.
  • the display unit further includes a first source-drain metal layer, the first source-drain metal layer includes a source and drain pattern of a thin film transistor, wherein the peripheral source-drain metal wiring is connected to the first
  • the source and drain metal layers are on the same layer and set with the same material.
  • the touch function layer is a flexible multi-layer on-screen touch structure
  • the touch pattern includes a plurality of self-capacitive touch electrodes distributed in an array
  • the film layer structure of the touch function layer includes at least Two touch electrode layers, and an insulating layer provided between the at least two touch electrode layers, at least one of the touch electrode layers is a metal mesh layer, and at least another of the touch electrode layers is a bridge A metal layer, the metal mesh layer and the bridge metal layer are connected through via holes on the insulating layer to form a self-capacitive touch electrode; or
  • the touch function layer is a flexible multi-layer on-screen touch structure
  • the touch pattern includes a plurality of mutually capacitive touch electrodes distributed in an array
  • the film layer structure of the touch function layer includes at least two touch electrode layer, and an insulating layer provided between the at least two touch electrode layers, at least one of the touch electrode layers is an emitter electrode layer, and at least another of the touch electrode layers is a sensing electrode layer, and the The emitter electrode layer and the sensing electrode layer are separated by the insulating layer to form a mutual capacitance touch electrode; or
  • the touch function layer is a flexible single-layer on-screen touch structure.
  • the film structure of the touch function layer includes a touch electrode layer.
  • the touch pattern on the touch electrode layer includes a plurality of arrays distributed in the screen. Touch electrodes and touch signal lines connected to the plurality of touch electrodes.
  • At least a plurality of the touch signal traces are parallel to each other at a first position where the bonding circuit is led out and the line spacing is a first spacing, and are parallel to each other at a second position across the isolation dam. And the line spacing is a second spacing, and the first spacing is smaller than the second spacing.
  • orthogonal projections of at least a plurality of touch signal traces on the substrate are drawn out in parallel from the first position and tilted toward the same or different directions at the same or different angles and then extend in parallel to the second position. Location.
  • the touch signal traces are divided into multiple sub-regions in the second direction, and the multiple touch signal traces in each sub-region are arranged in the second direction.
  • the middle touch signal trace is symmetrically distributed with the center.
  • embodiments of the present disclosure also provide a display panel, which has a display area and a peripheral area located at the periphery of the display area. At least one side of the peripheral area is a binding side connected to a binding circuit. The peripheral area is provided with an isolation dam at least partially surrounding the display area;
  • the display panel includes:
  • a display function layer includes a display unit located in the display area, and a display signal trace connected to the display unit located in at least part of the peripheral area;
  • the touch functional layer includes a touch pattern located in the display area and a touch signal trace located in at least part of the peripheral area, the touch signal trace is connected with the display signal trace Line different layer settings;
  • the touch signal traces are arranged along the first direction and are led out from the binding circuit and connected to the touch pattern via the isolation dam, and at least a plurality of the touch signal traces are The traces are parallel to each other and the line spacing is the first spacing at the first position where the bonding circuit is led out, and they are parallel to each other and the line spacing is the second spacing at the second position across the isolation dam.
  • the first The distance is smaller than the second distance.
  • orthogonal projections of at least a plurality of touch signal traces on the substrate are drawn out in parallel from the first position and tilted toward the same or different directions at the same or different angles and then extend in parallel to the second position. Location.
  • the touch signal traces are divided into multiple sub-regions in the second direction, the second direction intersects the first direction, and the multiple touch signals in each sub-region
  • the traces are symmetrically distributed with the touch signal trace in the middle in the second direction as the center.
  • the boundary of the display area close to the isolation dam is the first boundary
  • the boundary of the isolation dam close to the display area is the second boundary.
  • the touch signal wiring is arranged along the first direction and is led out from the bonding circuit and connected to the touch signal through the isolation dam and the first wiring area in turn.
  • the display signal traces are arranged along a second direction that intersects with the first direction and there is an intersection area between the orthographic projection on the substrate and the touch signal traces;
  • the display panel also includes a signal shielding layer between the touch signal traces and the display signal traces in a direction perpendicular to the substrate, and the orthographic projection of the signal shielding layer on the substrate Cover at least the intersection area of the touch signal trace and the display signal trace in the first trace area.
  • the signal shielding layer is provided with an opening pattern, and the touch signal traces do not coincide with the orthographic projection of the opening pattern on the substrate.
  • the signal shielding layer is located between the organic insulating layer and the display signal trace. between the touch signal wiring, or the organic insulating layer and the display signal wiring.
  • the touch signal traces along the first direction do not coincide with the orthographic projection of the opening pattern on the substrate.
  • the opening pattern includes a plurality of openings, and at least one opening is provided in a gap between at least two adjacent touch signal traces.
  • the display unit includes an anode layer, an organic electroluminescent layer and a cathode layer.
  • the anode layer includes an anode pattern for accessing display signals, and the signal shielding layer is in the same layer as the anode pattern.
  • the material is set, and the signal shielding layer is not connected to the anode pattern.
  • the signal shielding layer is connected to a constant low DC signal or a constant high DC signal.
  • the display panel further includes: a cathode lapping pattern arranged in the same layer and with the same material as the anode pattern, and an orthographic projection between the cathode lapping pattern and the anode pattern on the substrate do not overlap and are insulated from each other, the cathode overlap pattern and the orthographic projection of the cathode layer perpendicular to the substrate are at least partially coincident and electrically connected, and the cathode layer is connected to a constant low DC signal, the The signal shielding layer is integrated with the cathode lapping pattern; and/or
  • a constant low DC signal is connected to the cathode layer, the orthographic projection of the boundary of the cathode layer close to the isolation dam on the substrate does not exceed the first boundary, and the signal shielding layer is connected close to the isolation dam.
  • One side of the first boundary has a first overlapping area that overlaps with the cathode layer, and the first overlapping area is electrically connected to the cathode layer through a first via hole.
  • the cathode lapping pattern is located on the binding side and in a transition corner area between the binding side and at least another side of the substrate adjacent to the binding side.
  • the display panel further includes an encapsulation layer that encapsulates the display function layer, and the touch function layer is directly disposed on a side of the encapsulation layer away from the substrate;
  • the touch function layer is a flexible multi-layer on-screen touch structure.
  • the touch pattern includes a plurality of self-capacitive touch electrodes distributed in an array.
  • the film layer structure of the touch function layer includes at least two touch electrodes. electrode layer, and an insulating layer provided between the at least two touch electrode layers, at least one of the touch electrode layers is a metal mesh layer, and at least another of the touch electrode layers is a bridge metal layer, so The metal grid layer and the bridge metal layer are connected through via holes on the insulating layer to form a self-capacitive touch electrode; or
  • the touch function layer is a flexible multi-layer on-screen touch structure
  • the touch pattern includes a plurality of mutually capacitive touch electrodes distributed in an array
  • the film layer structure of the touch function layer includes at least two touch electrode layer, and an insulating layer provided between the at least two touch electrode layers, at least one of the touch electrode layers is an emitter electrode layer, and at least another of the touch electrode layers is a sensing electrode layer, and the The emitter electrode layer and the sensing electrode layer are separated by the insulating layer to form a mutual capacitive touch electrode.
  • a plurality of peripheral sources and drains are further provided between the second boundary and the display signal trace and/or between the second boundary and the binding circuit.
  • Metal traces, a constant low DC signal or a constant high DC signal is connected to the peripheral source and drain metal traces, and the signal shielding layer has a connection with the peripheral source and drain metal traces on the side close to the second boundary.
  • a second overlapping area is overlapped, and the second overlapping area is electrically connected to the peripheral source and drain metal traces through a second via hole.
  • the display unit further includes a first source-drain metal layer, the first source-drain metal layer includes a source and drain pattern of a thin film transistor, wherein the peripheral source-drain metal wiring is connected to the first
  • the source and drain metal layers are on the same layer and set with the same material.
  • the touch function layer is a flexible multi-layer on-screen touch structure
  • the touch pattern includes a plurality of self-capacitive touch electrodes distributed in an array
  • the film layer structure of the touch function layer includes at least Two touch electrode layers, and an insulating layer provided between the at least two touch electrode layers, at least one of the touch electrode layers is a metal mesh layer, and at least another of the touch electrode layers is a bridge A metal layer, the metal mesh layer and the bridge metal layer are connected through via holes on the insulating layer to form a self-capacitive touch electrode; or
  • the touch function layer is a flexible multi-layer on-screen touch structure
  • the touch pattern includes a plurality of mutually capacitive touch electrodes distributed in an array
  • the film layer structure of the touch function layer includes at least two touch electrode layer, and an insulating layer provided between the at least two touch electrode layers, at least one of the touch electrode layers is an emitter electrode layer, and at least another of the touch electrode layers is a sensing electrode layer, and the The emitter electrode layer and the sensing electrode layer are separated by the insulating layer to form a mutual capacitance touch electrode; or
  • the touch function layer is a flexible single-layer on-screen touch structure.
  • the film structure of the touch function layer includes a touch electrode layer.
  • the touch pattern on the touch electrode layer includes a plurality of arrays distributed in the screen. Touch electrodes and touch signal lines connected to the plurality of touch electrodes.
  • an embodiment of the present disclosure provides a display device, including the display panel as described above.
  • the present disclosure provides a display device, including the display panel as described above.
  • the display panel provided in some embodiments of the present disclosure can reduce signal crosstalk between the touch signal traces and the display signal traces by adding a signal shielding layer between the touch signal traces and the display signal traces, thereby ensuring The touch function is not affected, improving the product's working stability and reliability.
  • the display panel provided in other embodiments of the present disclosure can reduce the short circuit problem of the touch signal traces caused by metal residue between the isolation dams by enlarging the line spacing of the touch signal traces across the isolation dams. It can be seen that the display panel provided by the embodiment of the present disclosure can improve the working stability and reliability of the display product.
  • Figure 1 is a partial structural diagram of a touch pattern of a touch functional layer in a display panel in the related art
  • Figure 2 is a partial enlarged view of the dotted box in Figure 1;
  • Figure 3 is a simple schematic diagram of the overall structure of a display panel in the related art
  • Figure 4 is a cross-sectional view along the E-E’ direction in Figure 3;
  • Figure 5 is a cross-sectional view along the F-F’ direction in Figure 3;
  • Figure 6 is a schematic structural diagram of the touch signal wiring crossing the isolation dam at the dotted box B1 in Figure 3;
  • Figure 7 is a front view of a display panel provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of the touch signal wiring and isolation dam at B1 in Figure 7 in some embodiments of the present disclosure
  • Figure 9 is a schematic structural diagram of the touch signal wiring and isolation dam at B2 in Figure 7 in some embodiments of the present disclosure.
  • Figure 10 is a schematic structural diagram of the touch signal wiring and isolation dam at B1 in Figure 7 in other embodiments of the present disclosure
  • FIG 11 is a schematic structural diagram of the touch signal wiring and isolation dam at B2 in Figure 7 in other embodiments of the present disclosure
  • Figure 12 is a schematic structural diagram of the touch signal wiring and isolation dam at B1 in Figure 7 in other embodiments of the present disclosure
  • Figure 13 is a schematic structural diagram of the touch signal wiring and isolation dam at B2 in Figure 7 in other embodiments of the present disclosure
  • Figure 14 is a schematic structural diagram of the touch signal wiring and isolation dam at B1 in Figure 7 in other embodiments of the present disclosure
  • Figure 15 is a schematic structural diagram of the touch signal wiring and isolation dam at B2 in Figure 7 in other embodiments of the present disclosure
  • Figure 16 is a schematic structural diagram of the touch signal wiring and isolation dam at B1 in Figure 7 in other embodiments of the present disclosure
  • Figure 17 is a schematic diagram of the touch structure of the FSLOC display panel in some embodiments of the present disclosure.
  • Figure 18 is a schematic diagram of the touch structure of the FMLOC display panel in some embodiments of the present disclosure.
  • Figure 19 is a schematic diagram of the wiring at B1 in Figure 7 in other embodiments of the present disclosure.
  • Figure 20 is a schematic diagram of the wiring at B1 in Figure 7 in other embodiments of the present disclosure.
  • Figure 21 is a schematic diagram of the wiring at B1 in Figure 7 in other embodiments of the present disclosure.
  • FIG. 22 is a schematic diagram of the film layer stack structure of the display panel provided by the present disclosure.
  • FMLOC Flexible Multi-Layer On Cell
  • FSLOC Flexible Single-Layer On Cell
  • the touch circuit structure may include peripheral touch signal traces and touch patterns in the touch area connected to the peripheral touch signal traces.
  • the touch pattern may be a metal grid structure.
  • the touch function layer realizes its touch function mainly through mutual capacitance and self-capacity.
  • the touch pattern in the touch area can be divided into signal emitter (Tx) 1, bridge (Bridge) 2, signal receiver (Rx) 3 and no signal Accessed virtual (Dummy) area 4.
  • the touch functional layer can be divided into a first metal layer (TMB) and a second metal layer (TMA).
  • the signal emitter 1, the signal receiver 3 and the virtual area 4 can all be composed of the first metal layer.
  • the bridge 2 can be formed of a second metal layer (TMA), and the bridge 2 connects the two parts of the signal emitter formed by the first metal layer through the via holes on the insulating layer between the first metal layer and the second metal layer. Or connect the signal receiving pole.
  • the touch chip When working, the touch chip (Touch IC) is based on the capacitance value Cm1 (the capacitance value before no finger loading) and Cm2 (the capacitance value after finger loading) between the signal emitter and the signal receiving electrode before and after finger loading, and the capacitance value.
  • the amount of change ⁇ Cm makes a touch response.
  • the stacked structure of the OLED display panel may include: a substrate, a display function layer located on the substrate, and an encapsulation layer 15 (IJP) that encapsulates the display function layer.
  • the isolation dam (Dam) 5 is a raised design that prevents the encapsulation layer 15 from overflowing.
  • the display panel 6 includes an effective display area (AA area) and a peripheral area located at the periphery of the effective display area.
  • the isolation dam 5 can be arranged in a circle around the effective display area (AA area). As shown in FIG.
  • the isolation dam 5 may be formed of an organic layer, and may include a substrate 52 , a gate insulating layer, an interlayer dielectric layer 54 , etc. in sequence under the organic layer of the isolation dam 5 , where the substrate 51 may include
  • the gate insulating layer may be one or more layers (for example, the gate insulating layer shown in Figure 4 includes a first gate insulating layer 531 and a second gate insulating layer 532), which may be an inorganic layer structure; the interlayer dielectric layer 54 may be an inorganic layer structure.
  • the isolation dam 5 can be designed as a single isolation dam or a double isolation dam structure, as shown in Figures 3 and 4.
  • the isolation dam is a double isolation dam structure as an example.
  • the inner ring isolation dam 5a can be called Dam1
  • the outer ring isolation dam 5b It can be called Dam2.
  • Dam1 can be formed by a pixel definition layer (PDL) 55 and a spacer pillar (PS) 56
  • Dam2 can be formed by an organic insulating layer (PLN) 57, a pixel definition layer (PDL) 55, and a spacer pillar (PS) 56, so Dam2 is comparable Dam1 high.
  • the isolation dam on the binding side will thin the thickness of the pixel definition layer 55 and the spacer pillars 56.
  • the isolation dam 5 on the binding side will remove the spacer pillars. 56, leaving only the pixel definition layer 55.
  • the touch signal needs to avoid crosstalk with the display signal, thereby affecting the touch function.
  • a variety of signal traces are usually laid out in the peripheral area of the display panel, especially on the bonding side connected to the bonding circuit.
  • the peripheral touch signal traces need to be led from the bonding circuit and then cross the isolation dam to connect to the touch pattern. , so the wiring design on the binding side needs to avoid signal crosstalk between the touch signal wiring and the display signal wiring to ensure the stability and reliability of the touch function.
  • the figure is a partial layout diagram on the binding side of the display panel provided in some embodiments of the present disclosure.
  • some embodiments of the present disclosure provide a display panel 10, which has a display area (AA area) and a peripheral area located at the periphery of the display area (AA area). At least one side of the peripheral area is a binding side. , there is a binding area C on the binding side, the binding circuit is located in the binding area C, and an isolation dam 20 is provided in the peripheral area at least partially surrounding the display area (AA area).
  • the isolation dam 20 includes an inner ring isolation dam 21 and an outer ring isolation dam 22 .
  • the display panel 10 includes: a substrate 11 , a display functional layer 12 and a touch functional layer 13 .
  • the display function layer 12 includes a display driving circuit layer 120, a display unit located in the display area (AA area), and a plurality of display signal traces connected to the display unit.
  • the display panel 10 is an OLED display.
  • the display unit may include a thin film transistor, an anode layer 122, an organic electroluminescent layer 123, and a cathode layer 124.
  • the display signal traces 121 may include peripheral display signal traces located in the peripheral area.
  • the side of the display function layer 12 away from the substrate 11 is an encapsulation layer 15 .
  • the touch function layer 13 is located on the encapsulation layer 15 and includes a touch pattern located in the display area (AA area) and a plurality of touch signal traces 131 located at least partially in the peripheral area.
  • the touch signal wiring 131 and the display signal wiring are arranged in different layers.
  • first boundary D1 and a second boundary D2 arranged opposite each other, and a first path between the first boundary D1 and the second boundary D2.
  • Line area D the first boundary D1 is closer to the display area than the second boundary D2, that is to say, on the binding side, the display area (AA area) is close to the isolation dam 20
  • the boundary on one side of the isolation dam 20 is the first boundary D1
  • the boundary on the side of the isolation dam 20 close to the display area (AA area) is the second boundary D2.
  • first wiring area between them is a first wiring area between them.
  • the touch signal wiring 131 is arranged along the first direction X and is led out from the binding circuit and connected to the first wiring area D via the isolation dam 20 in turn.
  • the display signal traces are arranged along the second direction Y that intersects the first direction X and the orthographic projection on the substrate 11 intersects with the touch signal traces 131 area.
  • FIG. 17 taking the binding side of the display panel 10 at the lower frame of the display panel 10 as an example.
  • the peripheral touch signal traces 131 will be connected from the binding side.
  • the circuit After the circuit is led out, it crosses the isolation dam 20 and extends into the display area (AA area), and then extends to the left and right border directions respectively to connect to the touch pattern in the display area (AA area).
  • the display area (AA area) of the display panel 10 includes a plurality of sub-pixels distributed in an array, each sub-pixel can correspond to an anode, and the cathode layer 122 is usually designed to cover the entire display area (AA area), as shown in FIG.
  • the first boundary D1 of the display area (AA area)
  • the first boundary D1 shown in the figure is the lower boundary of the cathode layer
  • the area between is the first wiring area D.
  • Display signal wiring 121 is also arranged in the first wiring area D, and the touch signal wiring 131 will be connected with the display signal wiring in the first wiring area D.
  • Signal traces 121 cross.
  • the touch signal wiring 131 is connected to the area of the touch pattern, that is, the first wiring area D is close to the display area (AA On one side of the area, in area A as shown in Figures 16 and 19, since there are film layers such as the cathode layer 122 or the anode layer between the touch signal trace 131 and the display signal trace 121 in the A area, A constant low DC signal (VSS) or a constant high DC signal (VDD) is connected to these film layers.
  • VSS constant low DC signal
  • VDD constant high DC signal
  • the crosstalk of the touch signal trace 131 signal can be well shielded; similarly, in the first trace area D
  • the display area (AA area) that is, the area of the dotted frame B in Figure 16 and the area of the dotted frame B' shown in Figure 19, since there is a source and drain metal layer (SD) in the B area, therefore, It can also well shield the crosstalk of the touch signal wiring 131 signal.
  • SD source and drain metal layer
  • the contacts in the first wiring area D There is no film layer such as the cathode layer 122 or the anode layer between the control signal trace 131 and the display signal trace 121. In this way, the touch signal trace 131 cannot be well shielded, so the touch signal trace 131 exists. Risk of crosstalk.
  • the display panel 10 provided in some embodiments of the present disclosure also includes vertical
  • the signal shielding layer 30 is located between the touch signal wiring 131 and the display signal wiring 121 in the direction of the substrate 11.
  • the orthographic projection of the signal shielding layer 30 on the substrate 11 at least covers all The intersection area of the touch signal trace 131 and the display signal trace 121 in the first trace area D.
  • the signal shielding layer 30 between the touch signal trace 131 and the display signal trace 121, the signal crosstalk between the touch signal trace 131 and the display signal trace 121 can be reduced, thereby ensuring that the touch signal trace 131 and the display signal trace 121 are connected.
  • the control function is not affected and the working stability and reliability of the product are improved.
  • the peripheral area is provided between the touch signal trace 131 and the display signal trace 121.
  • Insulating layer and since the touch function layer 13 is disposed on the encapsulation layer 15, the insulating layer includes at least one organic insulating layer.
  • the signal shielding layer 30 is located between the organic insulating layer and the touch signal wiring 131 , or between the organic insulating layer and the display signal wiring 121 . Since the signal shielding layer 30 needs to cover the first wiring area D, its wiring width is relatively large, and there is gas in the organic insulating layer.
  • the An opening pattern is provided on the signal shielding layer 30 , and the touch signal traces 131 and the orthographic projection of the opening pattern on the substrate 11 at least partially do not overlap.
  • the bulging phenomenon can be prevented; and the opening pattern and the orthographic projection of the touch signal trace 131 on the substrate at least partially do not overlap.
  • the touch signal traces 131 along the first direction do not coincide with the orthographic projection of the opening pattern on the substrate 11 , so that the position of the opening pattern avoids the touch signal traces 131 , which can effectively prevent the touch signal wiring 131 from interfering with the display signal wiring 121 through the opening pattern.
  • the opening pattern includes a plurality of openings 31 , and at least one of the openings 31 is provided in a gap between at least two adjacent touch signal traces 131 .
  • the opening 31 is mentioned. That is, at least part of the touch signal traces may be arranged between the openings 31 .
  • at least one opening 31 is provided in a gap between any two adjacent touch signal traces 131 .
  • the density of the openings 31 can be reasonably designed according to the number and spacing of the touch signal traces 131 to fully ensure that the signals of the touch signal traces 131 are not crosstalked.
  • the specific pattern of the opening pattern is not limited thereto.
  • the first wiring area D is located between the display area (AA area) and the isolation dam 20. There are no pixel definition layer digging holes, spacer pillars, etc. in the first wiring area D. , therefore, the pixel definition layer of the first routing area D is relatively flat, which can reduce the risk of disconnection caused by the climbing of the signal shielding layer 30 .
  • the signal shielding layer 30 can be connected to a constant low DC signal (VSS) or a constant high DC signal (VDD) to better shield interference signals.
  • VSS constant low DC signal
  • VDD constant high DC signal
  • the display unit includes an anode layer 124, an organic electroluminescent layer 123 and a cathode layer 122.
  • the anode layer includes an anode pattern for accessing display signals.
  • the signal shielding layer 30 is connected to the anode layer 124. 124 are arranged on the same layer and with the same material, and the signal shielding layer 30 and the anode pattern are not connected.
  • the signal shielding layer 30 is connected to a constant low DC signal or a constant high DC signal.
  • the pattern of the signal shielding layer 30 can be formed through the same patterning process when forming the anode pattern.
  • the structure is simple and no additional process steps are required.
  • the peripheral area of the display panel 10 is provided with a cathode overlapping pattern, and the periphery of the cathode layer is electrically connected by overlapping with the cathode overlapping pattern, wherein at least part of the cathode overlapping pattern A pattern is located on the binding side and in a transition corner region between the binding side and at least another side of the substrate adjacent the binding side.
  • a part of the cathode overlapping pattern 50 is also provided in the area E' in the figure.
  • the part of the cathode overlapping pattern 50 and the anode pattern are on the same layer and made of the same material.
  • the cathode lapping pattern 50 can be connected to a constant low DC signal, and the cathode A pattern of openings 31 can also be provided on the overlapping pattern 50 to avoid the "bulging" phenomenon.
  • the cathode bonding pattern 50 and the cathode layer 122 are at least partially coincident and electrically connected in an orthographic projection perpendicular to the substrate 11 , and the cathode layer 122 is connected to a constant low DC signal. , so that the cathode lapping pattern 50 is connected to a constant low DC signal, and the signal shielding layer 30 is connected to the cathode lapping pattern 50 as a whole. In this way, the signal shielding layer 30 can be connected to a constant low DC signal. For low DC signal purposes.
  • a constant low DC signal is connected to the cathode layer 122 , and the boundary of the cathode layer close to the isolation dam 20 is on the lining.
  • the orthographic projection on the bottom 11 does not exceed the first boundary D1
  • the signal shielding layer 30 has a first overlapping area overlapping the cathode layer 122 on the side close to the first boundary D1
  • the third An overlapping area is electrically connected to the cathode layer 122 through a first via hole.
  • the signal shielding layer 30 can directly overlap the cathode layer 122, so that the constant low DC signal is connected to both the signal shielding layer 30 and the cathode layer 122.
  • the signal shielding layer 30 may be connected to a constant low DC signal on the bonding circuit, and then the signal shielding layer 30 may be overlapped with the cathode layer to realize the cathode layer connection. The purpose of inputting a constant low DC signal.
  • the signal shielding layer 30 and the cathode layer 122 can be connected to a constant low DC signal, and the implementation methods can include the following:
  • the signal shielding layer 30 is directly connected to the cathode overlapping pattern 50 to achieve the purpose of inputting a constant low DC signal to the cathode layer 122. At this time, the signal shielding layer 30 is close to the cathode layer 122.
  • One side of the cathode layer 122 and the first boundary D1 of the cathode 122 layer may directly overlap but are not connected;
  • the signal shielding layer 30 can overlap and be electrically connected to the first boundary D1 of the cathode layer 122 on a side close to the cathode layer.
  • the signal shielding layer 30 and the cathode overlapping pattern 50 There is no connection between them;
  • the signal shielding layer 30 is not only integrated with the cathode overlap pattern 50 , but also overlaps and is electrically connected to the first boundary D1 of the cathode layer 122 on the side close to the cathode layer 122 .
  • peripheral source and drain metal traces 40 are also provided, and a constant low DC signal is connected to the peripheral source and drain metal traces 40 (at this time, the peripheral source and drain metal traces 40 may refer to the peripheral source and drain metal traces 40 located as shown in Figure 19 VSS line in area C), the signal shielding layer 30 has a second overlapping area that overlaps with the peripheral source and drain metal traces 40 on the side close to the second boundary D2, and the second overlapping area The peripheral source and drain metal traces 40 are electrically connected through the second via hole.
  • peripheral source and drain metal traces 40 can be directly connected to the constant low DC signal on the bonding circuit, and the signal shielding layer 30 is connected to the peripheral source and drain metal traces 40 and the The overlapping of the cathode layers achieves the purpose of connecting the constant low DC signal to both the cathode layer and the signal shielding layer 30 .
  • the signal shielding layer 30 is connected with a constant low DC signal.
  • the peripheral source and drain metal traces 40 A constant high DC signal may also be connected (in this case, the peripheral source and drain metal wiring 40 may refer to the VDD line located in the C area as shown in the figure), and the signal shielding layer 30 is close to the second One side of the boundary D2 has a second overlapping area that overlaps the peripheral source and drain metal traces 40 , and the second overlapping area is electrically connected to the peripheral source and drain metal traces 40 through a second via hole, so that, The purpose of accessing the VDD signal on the signal shielding layer 30 is achieved.
  • the display unit includes a first source and drain metal layer, and the first source and drain metal layer includes the source and drain patterns of the thin film transistor, wherein the peripheral source and drain metal traces 40 It is arranged in the same layer and material as the first source and drain metal layer.
  • the display unit may include a single source-drain metal layer or a double source-drain metal layer, and the first source-drain metal layer may be any source-drain metal reasonably selected according to the actual product. layer.
  • the display signal lines 121 may include, for example, scanning signal lines, light emission control signal lines, reference voltage signal lines, etc.
  • the touch function layer 13 is a flexible multi-layer on-screen touch structure (FMLOC), and the touch pattern includes a plurality of self-capacitive touch structures distributed in an array.
  • the film layer structure of the touch functional layer includes at least two touch electrode layers and an insulating layer disposed between the at least two touch electrode layers, at least one of the touch electrode layers is a metal mesh Grid layer 132, and at least another touch electrode layer is a bridge metal layer 133.
  • the metal grid layer 132 and the bridge metal layer 133 are connected through via holes on the insulating layer to form a self-capacitive touch layer. control electrode.
  • the touch pattern may also include a plurality of mutually capacitive touch electrodes distributed in an array, and the The film layer structure of the touch functional layer includes at least two touch electrode layers and an insulating layer disposed between the at least two touch electrode layers. At least one of the touch electrode layers is an emitter electrode layer, and at least the other touch electrode layer is an emitter electrode layer. One of the touch electrode layers is a sensing electrode layer, and the emitter electrode layer and the sensing electrode layer are separated by the insulating layer to form a mutually capacitive touch electrode.
  • the touch functional layer may also include a protective layer covering the side of at least two touch electrode layers facing away from the driving backplane. The protective layer may protect the touch electrode layer, and may be an organic material.
  • the touch functional layer 13 may also be a flexible single-layer on-screen touch structure (FSLOC).
  • FLOC flexible single-layer on-screen touch structure
  • the film layer structure of the touch functional layer 13 includes a touch screen.
  • Electrode layer, the touch pattern on the touch electrode layer includes a plurality of touch electrodes 132 distributed in an array and touch signal lines 131 connected to the plurality of touch electrodes.
  • Figure 19 shows a wiring scheme for an FMLOC display panel.
  • the number of touch signal wirings 131 is relatively small.
  • the touch signal wirings 131 can be led out from the binding circuit and then passed through the first wiring area.
  • D extends in the direction of the left and right borders respectively, and the signal shielding layer 30 can be provided in the first wiring area D.
  • FIG. 20 shows a schematic wiring diagram of an FSLOC display panel
  • FIG. 21 shows a schematic wiring diagram of another FSLOC display panel 10 .
  • the display panel 10 shown in FIG. 21 has more touch signal lines and a smaller lower frame.
  • the cathode layer and the source and drain metal layers can completely cover the touch signal traces 131 in areas 1 and 2 shown in Figure 20, so it can There is no need to provide the signal shielding layer 30 .
  • the signal shielding layer 30 needs to be added between the touch signal trace 131 and the display signal trace 121 at D.
  • the signal shielding layer 30 can be connected to a constant high DC signal (VDD).
  • the display panel 10 in the embodiment of the present disclosure can be applied to the FMLOC display panel 10 and can also be applied to the FSLOC display panel 10 in which the number of touch signal traces 131 is greater than a predetermined value.
  • the predetermined value may be a value obtained through experience based on actual product performance and other requirements.
  • the isolation dam 20 of the display panel 10 since it is mainly formed of an organic layer, in order to prevent the organic layer from forming a water vapor channel, a certain range outside Dam2 (for example, greater than 40 ⁇ m), between Dam1 and Dam2 (for example, equal to 40 ⁇ m), and within a certain range of Dam1 Within a certain range (for example, greater than 40um), organic layers such as the organic insulating layer and the pixel definition layer will be completely removed, so a large layer difference will be formed.
  • a certain range outside Dam2 for example, greater than 40 ⁇ m
  • between Dam1 and Dam2 for example, equal to 40 ⁇ m
  • a certain range of Dam1 Within a certain range for example, greater than 40um
  • the touch signal trace 7 needs to cross the isolation dams 5a and 5b.
  • the isolation dam 20 on the binding side will thin the pixel definition layer 55 and the spacer pillars 56.
  • the isolation dam 5 on the binding side will remove the spacer pillars 56. , leaving only the pixel definition layer 55. Due to the groove structure between Dam1 and Dam2, when the touch signal trace 1317 is patterned, metal residues are easily left after exposure and etching processes, resulting in a short circuit between two adjacent traces, as shown in Figure 6. Metal residue in the dotted frame may easily lead to short circuit.
  • end a in the figure is the end of the touch signal trace 131 led from the binding circuit
  • end b is the touch signal trace.
  • the lines extend to one end of the display area, and at least a plurality of the touch signal traces 131 are parallel to each other at the first position where the binding circuit is led out, and the line spacing is a first spacing.
  • the second positions are parallel to each other and the line spacing is a second spacing, and the first spacing is smaller than the second spacing.
  • orthogonal projections of at least a plurality of touch signal traces 131 on the substrate 11 are drawn out in parallel from the first position and tilted toward the same or different directions at the same or different angles and then extend in parallel to the Second position.
  • the touch signal traces 131 derived from the binding circuit are first routed diagonally, close to the isolation dam 20, and then routed along the direction of the vertical isolation dam 20, so that the touch signals crossing the isolation dam 20 position are routed.
  • the spacing between lines 131 is widened to reduce the risk of short circuits.
  • oblique divergence lines can be divided into fixed angles and non-fixed angles. That is, each of the touch signal traces 131 is inclined at the same angle or at different angles.
  • Figures 8 to 11 are schematic diagrams of the wiring structure when multiple touch signal traces 131 are inclined at the same angle; Figures 12 to 15 are shown as multiple touch signal traces 131 are inclined at different angles. Schematic diagram of the wiring structure.
  • the plurality of touch signal traces 131 are led out in parallel. After diagonally diverging, it crosses the isolation dam 20 in parallel in a direction perpendicular to the isolation dam 20 , and then continues to extend parallel to the display area (AA area).
  • the touch signal traces 131 led out of the binding circuit are first diagonally distributed.
  • the touch signal wiring 131 can also be implemented through winding design (for example, arc design instead of diagonal design). The line spacing is enlarged.
  • the touch signal wiring 131 may be divided into at least one sub-region in the second direction Y, and each sub-region
  • the plurality of touch signal traces 131 close to the edge of the display panel in the second direction Y are arranged in an oblique and divergent manner, while the touch signal traces 131 close to the middle position of the display panel in the second direction Y may not be Diagonal wiring can extend in a straight line.
  • the plurality of touch signal traces 131 in each sub-region are arranged in the second direction Y.
  • the middle one of the touch signal traces 131 is symmetrically distributed about the center, and the middle one of the touch signal traces 131 is not routed diagonally and can extend in a straight line.
  • the shape of the display area (AA area) of the display panel 10 provided by the embodiment of the present disclosure may be circular, rectangular or other shapes.
  • the manufacturing method of the display panel 10 may include the following steps:
  • Step S01 Make a display function layer 12 on the substrate 11 and encapsulate it to form an encapsulation layer 15.
  • the display function layer 12 includes a display unit located in the display area (AA area) and a display unit connected to the display unit.
  • Multiple display signal traces 121 are provided with an isolation dam 20 surrounding the display area (AA area) in the peripheral area.
  • the display area (AA area) is close to the isolation dam 20
  • the boundary on one side of the isolation dam 20 is the first boundary D1
  • the boundary on the side of the isolation dam 20 close to the display area (AA area) is the second boundary D2.
  • the display signal wiring 121 is arranged along the second direction Y;
  • Step S02 Form a touch functional layer 13 on the encapsulation layer 15.
  • the touch functional layer 13 includes a touch pattern located in the display area (AA area) and a plurality of touch signal traces located in the peripheral area.
  • Line 131, the touch signal wiring 131 and the display signal wiring 121 are arranged in different layers.
  • the touch signal wiring 131 is arranged along the first direction
  • the bonding circuit is led out and connected to the touch pattern via the isolation dam 20 and the first wiring area D in sequence.
  • the orthographic projection of the display signal wiring 121 on the substrate 11 is consistent with the Touch signal trace 131 crosses;
  • a signal shielding layer 30 is formed between the touch signal trace 131 and the display signal trace 121 in the direction perpendicular to the substrate 11 , and the signal shielding layer 30 is formed on the substrate.
  • the orthographic projection on 11 at least covers the first wiring area D.
  • step S01 specifically includes:
  • Step S011 Use the same patterning process to form the anode layer and the signal shielding layer 30 in the display unit.
  • the patterning process can use a conventional anode layer patterning process, including steps such as exposure, development, etching, etc.
  • steps such as exposure, development, etching, etc.
  • the specific process will not be described in detail. It is only necessary to modify the pattern of the mask plate in the conventional patterning process. For improvement, it is sufficient to add corresponding signal shielding layer 30 patterns based on the original anode pattern.
  • embodiments of the present disclosure also provide a display panel 10, which has a display area (AA area) and a peripheral area located at the periphery of the display area (AA area). At least one side of the peripheral area is connected with a binding On the binding side of the circuit, an isolation dam 20 is provided around the display area (AA area) in the peripheral area;
  • the display panel 10 includes:
  • the display function layer 12 includes a display unit located in the display area (AA area) and a display signal trace 121 connected to the display unit; and
  • the touch functional layer 13 includes a touch pattern located in the display area (AA area) and a touch signal wiring 131 located in the peripheral area.
  • the touch signal wiring 131 It is arranged on a different layer than the display signal wiring 121;
  • the touch signal trace 131 is arranged along the first direction X and is led out from the binding circuit and connected to the touch pattern via the isolation dam 20 in turn, as shown in FIG.
  • end a in the figure is the end where the touch signal trace 131 is led from the binding circuit
  • end b is the end where the touch signal trace 131 extends to the display area.
  • the lines 131 are parallel to each other at a first position where the bonding circuit is led out and the line spacing is a first spacing, and they are parallel to each other at a second position across the isolation dam 20 and the line spacing is a second spacing. A distance is smaller than the second distance.
  • orthogonal projections of at least a plurality of touch signal traces 131 on the substrate 11 are drawn out in parallel from the first position and tilted toward the same or different directions at the same or different angles and then extend in parallel to the Second position.
  • the touch signal traces 131 derived from the binding circuit are first routed diagonally, close to the isolation dam 20, and then routed along the direction of the vertical isolation dam 20, so that the touch signals crossing the isolation dam 20 position are routed.
  • the spacing between lines 131 is widened to reduce the risk of short circuits.
  • oblique divergence lines can be divided into fixed angles and non-fixed angles. That is, each of the touch signal traces 131 is inclined at the same angle or at different angles.
  • Figures 8 to 11 are schematic diagrams of the wiring structure when multiple touch signal traces 131 are inclined at the same angle; Figures 12 to 15 are shown as multiple touch signal traces 131 are inclined at different angles. Schematic diagram of the wiring structure.
  • the plurality of touch signal traces 131 are led out in parallel. And after diverging diagonally, it crosses the isolation dam 20 in parallel in a direction perpendicular to the isolation dam 20 , and then continues to extend parallel to the display area (AA area).
  • the touch signal traces 131 led out of the binding circuit are first diagonally distributed.
  • the touch signal wiring 131 can also be implemented through winding design (for example, arc design instead of diagonal design). The line spacing is enlarged.
  • the touch signal wiring 131 may be divided into at least one sub-region in the second direction Y, and each sub-region
  • the plurality of touch signal traces 131 close to the edge of the display panel in the second direction Y are arranged in an oblique and divergent manner, while the touch signal traces 131 close to the middle position of the display panel in the second direction Y may not be Diagonal wiring can extend in a straight line.
  • the plurality of touch signal traces 131 in each sub-region are arranged in the second direction Y.
  • the middle one of the touch signal traces 131 is symmetrically distributed about the center, and the middle one of the touch signal traces 131 is not routed diagonally and can extend in a straight line.
  • the shape of the display area (AA area) of the display panel 10 provided by the embodiment of the present disclosure may be circular, rectangular or other shapes.
  • the manufacturing method of the display panel 10 may include the following steps:
  • Step S01 Make a display function layer 12 on the substrate 11 and encapsulate it to form an encapsulation layer 15.
  • the display function layer 12 includes a display unit located in the display area (AA area) and a display unit connected to the display unit.
  • Multiple display signal traces 121 are provided with an isolation dam 20 surrounding the display area (AA area) in the peripheral area.
  • the display area (AA area) is close to the isolation dam 20
  • the boundary on one side of the isolation dam 20 is the first boundary D1
  • the boundary on the side of the isolation dam 20 close to the display area (AA area) is the second boundary D2.
  • the display signal wiring 121 is arranged along the second direction Y;
  • Step S02 Form a touch functional layer 13 on the encapsulation layer 15.
  • the touch functional layer 13 includes a touch pattern located in the display area (AA area) and a plurality of touch signal traces located in the peripheral area.
  • Line 131, the touch signal wiring 131 and the display signal wiring 121 are arranged in different layers.
  • the touch signal wiring 131 is arranged along the first direction
  • the bonding circuit is led out and connected to the touch pattern via the isolation dam 20 and the first wiring area D in sequence.
  • the orthographic projection of the display signal wiring 121 on the substrate 11 is consistent with the Touch signal trace 131 crosses;
  • a signal shielding layer 30 is formed between the touch signal trace 131 and the display signal trace 121 in the direction perpendicular to the substrate 11 .
  • the signal shield layer 30 is formed on the substrate.
  • the orthographic projection on 11 at least covers the first wiring area D.
  • orthogonal projections of at least a plurality of touch signal traces 131 on the substrate 11 are drawn out in parallel from the first position and tilted toward the same or different directions at the same or different angles and then extend in parallel to the Second position.
  • the touch signal traces 131 derived from the binding circuit are first routed diagonally, close to the isolation dam 20, and then routed along the direction of the vertical isolation dam 20, so that the touch signals crossing the isolation dam 20 position are routed.
  • the spacing between lines 131 is widened to reduce the risk of short circuits.
  • oblique divergence lines can be divided into fixed angles and non-fixed angles. That is, each of the touch signal traces 131 is inclined at the same angle or at different angles.
  • the figure shows a schematic diagram of the wiring structure when the plurality of touch signal traces 131 are tilted at the same angle; the figure shows a schematic diagram of the wiring structure when the plurality of touch signal traces 131 are tilted at different angles.
  • the plurality of touch signal traces 131 are led out in parallel. And after diverging diagonally, it crosses the isolation dam 20 in parallel in a direction perpendicular to the isolation dam 20 , and then continues to extend parallel to the display area (AA area).
  • the touch signal traces 131 led out of the binding circuit are first diagonally distributed.
  • the touch signal wiring 131 can also be implemented through winding design (for example, arc design instead of diagonal design). The line spacing is enlarged.
  • the touch signal traces 131 are divided into multiple sub-regions in the second direction Y, and the multiple touch signal traces 131 in each sub-region are arranged in the second direction Y.
  • the touch signal trace 131 in the middle in the direction Y is symmetrically distributed with the center.
  • the boundary of the display area (AA area) close to the isolation dam 20 is the first boundary D1
  • the side boundary of the isolation dam 20 close to the display area (AA area) ) is a second boundary D2
  • the display panel 10 also includes a signal shielding layer 30 between the touch signal traces 131 and the display signal traces 121 in a direction perpendicular to the substrate 11 .
  • the signal shielding layer 30 is on the The orthographic projection on the substrate 11 at least covers the first wiring area D.
  • the peripheral area is provided between the touch signal trace 131 and the display signal trace 121.
  • Insulating layer and since the touch function layer 13 is disposed on the encapsulation layer 15, the insulating layer includes at least one organic insulating layer.
  • the signal shielding layer 30 is located between the organic insulating layer and the touch signal trace 131, or the organic insulating layer and the display signal trace 121. Since the signal shielding layer 30 needs to cover the first wiring area D, its wiring width is relatively large, and there is gas in the organic insulating layer.
  • the An opening pattern is provided on the signal shielding layer 30 , and the orthographic projection of the touch signal wiring 131 and the opening pattern on the substrate 11 does not overlap. In this way, by opening an opening pattern on the signal shielding layer 30 , the bulging phenomenon can be prevented, and the position of the opening pattern avoids the touch signal wiring 131 , which can effectively prevent the touch signal wiring 131 from passing through the opening.
  • the pattern and the display signal trace 121 interfere with each other.
  • the opening pattern includes a plurality of openings 31 , and at least one opening is provided in the gap between any two adjacent touch signal traces 131 . 31. That is to say, the touch signal wiring 131 is disposed between the openings 31 .
  • the density of the openings 31 can be reasonably designed according to the number and spacing of the touch signal traces 131 to fully ensure that the signals of the touch signal traces 131 are not crosstalked.
  • the specific pattern of the opening pattern is not limited thereto.
  • the first wiring area D is located between the display area (AA area) and the isolation dam 20. There are no pixel definition layer digging holes, spacer pillars, etc. in the first wiring area D. , therefore, the pixel definition layer of the first routing area D is relatively flat, which can reduce the risk of disconnection caused by the climbing of the signal shielding layer 30 .
  • a virtual touch signal line 60 is also provided on the binding side as shown in the dotted box D' in FIG. The signal shielding layer.
  • the signal shielding layer 30 can be connected to a constant low DC signal (VSS) or a constant high DC signal (VDD) to better shield interference signals.
  • VSS constant low DC signal
  • VDD constant high DC signal
  • the display unit includes an anode layer, an organic electroluminescent layer and a cathode layer,
  • the anode layer includes an anode pattern for accessing display signals.
  • the signal shielding layer 30 and the anode layer 124 are on the same layer and made of the same material, and the signal shielding layer 30 and the anode pattern are not connected. , the signal shielding layer 30 is connected to a constant low DC signal or a constant high DC signal.
  • the pattern of the signal shielding layer 30 can be formed through the same patterning process when forming the anode pattern.
  • the structure is simple and no additional process steps are required.
  • the peripheral area of the display panel 10 is provided with a cathode overlapping pattern, and the periphery of the cathode layer is electrically connected by overlapping with the cathode overlapping pattern, wherein at least part of the cathode overlapping pattern A pattern is located on the binding side and in a transition corner region between the binding side and at least another side of the substrate adjacent the binding side.
  • a part of the cathode overlapping pattern 50 is also provided in the E' area in the figure.
  • This part of the cathode overlapping pattern 50 is arranged in the same layer and material as the anode pattern, and there is a gap between the cathode overlapping pattern and the anode pattern.
  • the orthographic projections on the substrate do not overlap and are insulated from each other, and the cathode overlap pattern 50 can be connected to a constant low DC signal.
  • a pattern of openings 31 can also be provided on the cathode overlap pattern 50 to avoid "bulging" Phenomenon.
  • 0 and the orthographic projection of the cathode layer 122 perpendicular to the substrate 11 at least partially overlap and are electrically connected, and the cathode layer 122 is connected to a constant low DC signal, so that the cathode A constant low DC signal is connected to the overlapping pattern 50 , and the signal shielding layer 30 is connected to the cathode overlapping pattern 50 as a whole. In this way, the signal shielding layer 30 can be connected to a constant low DC signal.
  • a constant low DC signal is connected to the cathode layer 122 , and the boundary of the cathode layer close to the isolation dam 20 is on the lining.
  • the orthographic projection on the bottom 11 does not exceed the first boundary D1
  • the signal shielding layer 30 has a first overlapping area overlapping the cathode layer 122 on the side close to the first boundary D1
  • the third An overlapping area is electrically connected to the cathode layer 122 through a first via hole.
  • the signal shielding layer 30 can directly overlap the cathode layer 122, so that the constant low DC signal is connected to both the signal shielding layer 30 and the cathode layer 122.
  • the signal shielding layer 30 may be connected to a constant low DC signal on the bonding circuit, and then the signal shielding layer 30 may be overlapped with the cathode layer to realize the cathode layer connection. The purpose of inputting a constant low DC signal.
  • the signal shielding layer 30 can be connected to the cathode layer with a constant low DC signal, and the implementation methods can include the following:
  • the signal shielding layer 30 is directly connected to the cathode overlapping pattern 50 to achieve the purpose of inputting constant low DC signals to both the cathode layer and the cathode layer. At this time, the signal shielding layer 30 is close to the cathode layer. One side of the cathode layer may directly overlap but not be connected to the first boundary of the cathode layer;
  • the signal shielding layer 30 can overlap and be electrically connected to the first boundary of the cathode layer on the side close to the cathode layer, and there is no gap between the signal shielding layer 30 and the cathode overlapping pattern 50. connect;
  • the signal shielding layer 30 is not only integrated with the cathode overlapping pattern 50, but also overlaps and is electrically connected to the first boundary of the cathode layer on the side close to the cathode layer.
  • peripheral source and drain metal traces 40 are also provided, and a constant low DC signal is connected to the peripheral source and drain metal traces 40 (in this case, the peripheral source and drain metal traces 40 may refer to the peripheral source and drain metal traces 40 located as shown in Figure 17 VSS line in area C), the signal shielding layer 30 has a second overlapping area that overlaps with the peripheral source and drain metal traces 40 on the side close to the second boundary D2, and the second overlapping area The peripheral source and drain metal traces 40 are electrically connected through the second via hole.
  • peripheral source and drain metal traces 40 can be directly connected to the constant low DC signal on the bonding circuit, and the signal shielding layer 30 is connected to the peripheral source and drain metal traces 40 and the The overlapping of the cathode layers achieves the purpose of connecting the constant low DC signal to both the cathode layer and the signal shielding layer 30 .
  • the signal shielding layer 30 is connected with a constant low DC signal.
  • the peripheral source and drain metal traces 40 A constant high DC signal may also be connected (in this case, the peripheral source and drain metal wiring 40 may refer to the VDD line located in the C area as shown in the figure), and the signal shielding layer 30 is close to the second One side of the boundary D2 has a second overlapping area that overlaps the peripheral source and drain metal traces 40 , and the second overlapping area is electrically connected to the peripheral source and drain metal traces 40 through a second via hole, so that, The purpose of accessing the VDD signal on the signal shielding layer 30 is achieved.
  • the display unit includes a first source and drain metal layer, and the first source and drain metal layer includes the source and drain patterns of the thin film transistor, wherein the peripheral source and drain metal traces 40 It is arranged in the same layer and material as the first source and drain metal layer.
  • the display unit may include a single source-drain metal layer or a double source-drain metal layer, and the first source-drain metal layer may be any source-drain metal reasonably selected according to the actual product. layer.
  • the display signal wiring 121 may include, for example, scanning signal lines, light emission control signal lines, reference voltage signal lines, etc.
  • the touch function layer is a flexible multi-layer on-screen touch structure (FMLOC)
  • the touch pattern includes a plurality of self-capacitive touch electrodes distributed in an array
  • the touch function layer The layer structure includes at least two touch electrode layers and an insulating layer disposed between the at least two touch electrode layers. At least one of the touch electrode layers is a metal mesh layer, and at least another of the touch electrode layers is a metal mesh layer.
  • the touch electrode layer is a bridge metal layer, and the metal grid layer and the bridge metal layer are connected through via holes on the insulating layer to form a self-capacitive touch electrode.
  • the touch pattern may also include a plurality of mutually capacitive touch electrodes distributed in an array, and the The film layer structure of the touch functional layer includes at least two touch electrode layers and an insulating layer disposed between the at least two touch electrode layers. At least one of the touch electrode layers is an emitter electrode layer, and at least the other touch electrode layer is an emitter electrode layer.
  • the touch functional layer may also include a protective layer covering the side of at least two touch electrode layers facing away from the driving backplane.
  • the protective layer may protect the touch electrode layer, and may be an organic material.
  • the touch function layer may also be a flexible single-layer on-screen touch structure (FSLOC).
  • FLOC flexible single-layer on-screen touch structure
  • the film layer structure of the touch function layer includes a touch electrode layer.
  • the touch pattern on the layer includes a plurality of touch electrodes distributed in an array and touch signal lines connected to the plurality of touch electrodes. The specific structure will not be described again here.
  • the number of touch signal wirings 131 is relatively small, and the touch signal wirings 131 can be led out from the binding circuit and then passed through the first
  • the wiring area D extends to the left and right border directions respectively, and the signal shielding layer 30 can be provided in the first wiring area D.
  • FIG. 18 shows a schematic wiring diagram of one FSLOC display panel 10
  • FIG. 19 shows a schematic wiring diagram of another FSLOC display panel 10 .
  • the display panel 10 shown in FIG. 19 has more touch signal lines and a smaller lower frame.
  • the cathode layer and the source and drain metal layers can completely cover the touch signal traces 131, so it can There is no need to provide the signal shielding layer 30 .
  • the signal shielding layer 30 needs to be added between the touch signal trace 131 and the display signal trace 121 at D.
  • the signal shielding layer 30 can be connected to a constant high DC signal (VDD).
  • the display panel 10 in the embodiment of the present disclosure can be applied to the FMLOC display panel 10 and can also be applied to the FSLOC display panel 10 in which the number of touch signal traces 131 is greater than a predetermined value.
  • the manufacturing method of the display panel 10 may include the following steps:
  • Step S01 Make a display function layer 12 on the substrate 11 and encapsulate it to form an encapsulation layer 15.
  • the display function layer 12 includes a display unit located in the display area (AA area) and a display unit connected to the display unit.
  • Multiple display signal traces 121 are provided with an isolation dam 20 surrounding the display area (AA area) in the peripheral area.
  • the display area (AA area) is close to the isolation dam 20
  • the boundary on one side of the isolation dam 20 is the first boundary D1
  • the boundary on the side of the isolation dam 20 close to the display area (AA area) is the second boundary D2.
  • the display signal wiring 121 is arranged along the second direction Y;
  • Step S02 Form a touch functional layer 13 on the encapsulation layer 15.
  • the touch functional layer 13 includes a touch pattern located in the display area (AA area) and a plurality of touch signal traces located in the peripheral area.
  • Line 131, the touch signal trace 131 and the display signal trace 121 are arranged in different layers.
  • the touch signal trace 131 is arranged along the first direction
  • the circuit is led out and connected to the touch pattern via the isolation dam 20 , and at least a plurality of the touch signal traces 131 are parallel to each other at the first position where the bonding circuit is led out, and the line spacing is a first spacing.
  • the line spacing is a second spacing
  • the first spacing is smaller than the second spacing.
  • step S01 specifically includes:
  • Step S011' Form a signal shielding layer 30 between the touch signal wiring 131 and the display signal wiring 121 in the direction perpendicular to the substrate 11 .
  • the signal shielding layer 30 is formed on the substrate 11
  • the orthographic projection on at least covers the first wiring area D.
  • step S011' the same patterning process can be used to form the anode layer and the signal shielding layer 30 in the display unit.
  • the patterning process can use a conventional anode layer patterning process, including steps such as exposure, development, etching, etc.
  • steps such as exposure, development, etching, etc.
  • the specific process will not be described in detail. It is only necessary to modify the pattern of the mask plate in the conventional patterning process. For improvement, it is sufficient to add corresponding signal shielding layer 30 patterns based on the original anode pattern.

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Abstract

一种显示面板(6、10)及显示装置，显示面板(6、10)的外围区设隔离坝(5、20)；显示面板(6、10)包括：显示功能层(12)，包括多根显示信号走线(121)；触控功能层(13)，包括多根触控信号走线(131)；在绑定侧，具有第一边界(D1)和第二边界(D2)、及位于第一边界(D1)和第二边界(D2)之间的第一走线区(D)，第一边界(D1)比第二边界(D2)更靠近显示区(AA区)；在第一走线区(D)，触控信号走线(131)沿第一方向(X)设置且从绑定电路引出依次经由隔离坝(5、20)和第一走线区(D)连接至触控图案，显示信号走线(121)沿第二方向(Y)设置且与触控信号走线(131)交叉；在垂直衬底方向上触控信号走线(131)与显示信号走线(121)之间设信号屏蔽层(30)，信号屏蔽层(30)在衬底(52、11)上的正投影至少覆盖第一走线区(D)内的触控信号走线(131)和显示信号走线(121)。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
OLED(Organic Light Emitting Diode，有机电致发光二极管)显示装置由于具有全固态结构、自发光、响应速度快、亮度高、全视角、可柔性显示等一系列优点，因而成为目前极具竞争力和良好发展前景的一类显示装置。在相关技术中，柔性OLED产品可将触控功能层集成于显示面板之上。对OLED产品中的工作稳定性和可靠性提出更高要求。
发明内容
本公开实施例提供了一种显示面板及显示装置，能够提高显示产品的工作稳定性和可靠性。
本公开实施例所提供的技术方案如下：
第一方面，本公开实施例提供一种显示面板，其具有显示区和位于所述显示区外围的外围区，所述外围区至少一侧为连接有绑定电路的绑定侧，在所述外围区设有至少部分围绕所述显示区设置的隔离坝；
所述显示面板包括：
衬底；
显示功能层，所述显示功能层包括位于所述显示区的显示单元、及连接所述显示单元的位于至少部分所述外围区的多根显示信号走线；及
触控功能层，所述触控功能层包括位于所述显示区的触控图案、及位于至少部分所述外围区的多根触控信号走线，所述触控信号走线与所述显示信号走线不同层设置；
其中在所述绑定侧，具有相对设置的第一边界和第二边界、及位于所述第一边界和所述第二边界之间的第一走线区，所述第一边界比所述第二边界更靠近所述显示区；
在所述第一走线区，所述触控信号走线沿第一方向设置且从所述绑定电路引出并依次经由所述隔离坝和所述第一走线区连接至所述触控图案，所述显示信号走线沿与所述第一方向相交的第二方向设置且在所述衬底上的正投影与所述触控信号走线存在交叉区域；
所述显示面板还包括在垂直所述衬底方向上处于所述触控信号走线与所述显示信号走线之间的信号屏蔽层，所述信号屏蔽层在所述衬底上的正投影至少部分覆盖所述第一走线区内的所述触控信号走线和所述显示信号走线的交叉区域。
示例性的，所述信号屏蔽层上设有开口图案，且触控信号走线与所述开口图案在所述衬底上的正投影至少部分不重合。
示例性的，沿着所述第一方向上的触控信号走线与所述开口图案在所述衬底上的正投影不重合。
示例性的，所述开口图案包括多个开孔，至少相邻的两根所述触控信号走线之间的间隙处设置有至少一个所述开孔。
示例性的，所述显示单元包括阳极层、有机电致发光层和阴极层，所述阳极层包括用于接入显示信号的阳极图案，所述信号屏蔽层与所述阳极图案同层且同材质设置，且所述信号屏蔽层与所述阳极图案之间不连接，所述信号屏蔽层接入恒低直流信号或者恒高直流信号。
示例性的，所述显示面板还包括：与所述阳极图案同层且同材质设置的阴极搭接图案，所述阴极搭接图案与所述阳极图案之间在所述衬底上的正投影不重合且彼此绝缘，所述阴极搭接图案与所述阴极层在垂直于所述衬底之上的正投影至少部分重合且电连接，且所述阴极层接入恒低直流信号，所述信号屏蔽层与所述阴极搭接图案连为一体；和/或
所述阴极层上接入恒低直流信号，所述阴极层靠近所述隔离坝的一侧边界在所述衬底上的正投影不超出所述第一边界，所述信号屏蔽层在靠近所述第一边界的一侧具有与所述阴极层重叠的第一重叠区域，且所述第一重叠区域通过第一过孔与所述阴极层电连接。
示例性的，所述阴极搭接图案至少部分位于所述绑定侧，且位于所述绑定侧和所述衬底的与所述绑定侧相邻的至少另一侧之间的过渡拐角区域。
示例性的，所述显示面板还包括封装所述显示功能层的封装层，所述触控功能层直接设置在所述封装层的远离所述衬底的一侧；
所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个自容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为金属网格层，至少另一个所述触控电极层为桥接金属层，所述金属网格层与所述桥接金属层通过所述绝缘层上的过孔连接，以形成自容式触控电极；或者
所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个互容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为发射电极层，至少另一个所述触控电极层为感应电极层，所述发射电极层与所述感应电极层之间通过所述绝缘层隔开，以形成互容式触控电极。
示例性的，在所述第一方向上，所述第二边界与所述显示信号走线之间和/或所述第二边界与所述绑定电路之间还设有多个外围源漏金属走线，所述外围源漏金属走线上接入恒低直流信号或恒高直流信号，所述信号屏蔽层在靠近所述第二边界的一侧具有与所述外围源漏金属走线重叠的第二重叠区域，且所述第二重叠区域通过第二过孔与所述外围源漏金属走线电连接。
示例性的，所述显示单元还包括第一源漏金属层，所述第一源漏金属层包括薄膜晶体管的源极和漏极图案，其中所述外围源漏金属走线与所述第一源漏金属层同层且同材质设置。
示例性的，所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个自容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为金属网格层，至少另一个所述触控电极层为桥接金属层，所述金属网格层与所述桥接金属层通过所述绝缘层上的过孔连接，以形成自容式触控电极；或者
所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个互容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极 层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为发射电极层，至少另一个所述触控电极层为感应电极层，所述发射电极层与所述感应电极层之间通过所述绝缘层隔开，以形成互容式触控电极；或者
所述触控功能层为柔性单层屏上触控结构，所述触控功能层的膜层结构包括一触控电极层，所述触控电极层上的触控图案包括阵列分布的多个触控电极及连接至所述多个触控电极上的触控信号线。
示例性的，至少多根所述触控信号走线在所述绑定电路引出的第一位置处相互平行且线间距为第一间距，在跨过所述隔离坝的第二位置处相互平行且线间距为第二间距，所述第一间距小于所述第二间距。
示例性的，至少多根所述触控信号走线在所述衬底上的正投影从所述第一位置平行引出并朝向相同或不同方向倾斜相同或不同角度后平行延伸至所述第二位置。
示例性的，所述触控信号走线在所述第二方向上分为多个子区域，每个所述子区域内的多根所述触控信号走线以在所述第二方向上处于中间的一根所述触控信号走线为中心呈对称分布。
第二方面，本公开实施例还提供了一种显示面板，其具有显示区和位于所述显示区外围的外围区，所述外围区至少一侧为连接有绑定电路的绑定侧，在所述外围区设有至少部分围绕所述显示区设置的隔离坝；
所述显示面板包括：
衬底；
显示功能层，所述显示功能层包括位于所述显示区的显示单元、及连接所述显示单元的位于至少部分所述外围区的显示信号走线；及
触控功能层，所述触控功能层包括位于所述显示区的触控图案、及位于至少部分所述外围区的触控信号走线，所述触控信号走线与所述显示信号走线不同层设置；
在所述绑定侧，所述触控信号走线沿第一方向设置且从所述绑定电路引出并经由所述隔离坝连接至所述触控图案，且至少多根所述触控信号走线在所述绑定电路引出的第一位置处相互平行且线间距为第一间距，在跨过所述 隔离坝的第二位置处相互平行且线间距为第二间距，所述第一间距小于所述第二间距。
示例性的，至少多根所述触控信号走线在所述衬底上的正投影从所述第一位置平行引出并朝向相同或不同方向倾斜相同或不同角度后平行延伸至所述第二位置。
示例性的，所述触控信号走线在第二方向上分为多个子区域，所述第二方向与所述第一方向交叉，每个所述子区域内的多根所述触控信号走线以在所述第二方向上处于中间的一根所述触控信号走线为中心呈对称分布。
示例性的，在所述绑定侧，所述显示区的靠近所述隔离坝的一侧边界为第一边界，所述隔离坝的靠近所述显示区的一侧边界为第二边界，在所述第二边界与所述第一边界之间具有第一走线区；
在所述第一走线区，所述触控信号走线沿第一方向设置且从所述绑定电路引出并依次经由所述隔离坝和所述第一走线区连接至所述触控图案，所述显示信号走线沿与所述第一方向交叉的第二方向设置且在所述衬底上的正投影与所述触控信号走线存在交叉区域；
所述显示面板还包括在垂直所述衬底方向上处于所述触控信号走线与所述显示信号走线之间的信号屏蔽层，所述信号屏蔽层在所述衬底上的正投影至少覆盖所述第一走线区内的所述触控信号走线和所述显示信号走线的交叉区域。
示例性的，所述信号屏蔽层上设有开口图案，且所述触控信号走线与所述开口图案在所述衬底上的正投影不重合。
示例性的，在垂直所述衬底方向上，所述触控信号走线与所述显示信号走线之间具有至少一层有机绝缘层，所述信号屏蔽层位于所述有机绝缘层与所述触控信号走线、或所述有机绝缘层与所述显示信号走线之间。
示例性的，沿着所述第一方向上的触控信号走线与所述开口图案在所述衬底上的正投影不重合。
示例性的，所述开口图案包括多个开孔，至少相邻的两根所述触控信号走线之间的间隙处设置有至少一个所述开孔。
示例性的，所述显示单元包括阳极层、有机电致发光层和阴极层，所述 阳极层包括用于接入显示信号的阳极图案，所述信号屏蔽层与所述阳极图案同层且同材质设置，且所述信号屏蔽层与所述阳极图案之间不连接，所述信号屏蔽层接入恒低直流信号或者恒高直流信号。
示例性的，所述显示面板还包括：与所述阳极图案同层且同材质设置的阴极搭接图案，所述阴极搭接图案与所述阳极图案之间在所述衬底上的正投影不重合且彼此绝缘，所述阴极搭接图案与所述阴极层在垂直于所述衬底之上的正投影至少部分重合且电连接，且所述阴极层接入恒低直流信号，所述信号屏蔽层与所述阴极搭接图案连为一体；和/或
所述阴极层上接入恒低直流信号，所述阴极层靠近所述隔离坝的一侧边界在所述衬底上的正投影不超出所述第一边界，所述信号屏蔽层在靠近所述第一边界的一侧具有与所述阴极层重叠的第一重叠区域，且所述第一重叠区域通过第一过孔与所述阴极层电连接。
示例性的，所述阴极搭接图案位于所述绑定侧，且位于所述绑定侧和所述衬底的与所述绑定侧相邻的至少另一侧之间的过渡拐角区域。
示例性的，所述显示面板还包括封装所述显示功能层的封装层，所述触控功能层直接设置在所述封装层的远离所述衬底的一侧；
所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个自容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为金属网格层，至少另一个所述触控电极层为桥接金属层，所述金属网格层与所述桥接金属层通过所述绝缘层上的过孔连接，以形成自容式触控电极；或者
所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个互容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为发射电极层，至少另一个所述触控电极层为感应电极层，所述发射电极层与所述感应电极层之间通过所述绝缘层隔开，以形成互容式触控电极。
示例性的，在所述第一方向上，所述第二边界与所述显示信号走线之间和/或所述第二边界与所述绑定电路之间还设有多个外围源漏金属走线，所述 外围源漏金属走线上接入恒低直流信号或恒高直流信号，所述信号屏蔽层在靠近所述第二边界的一侧具有与所述外围源漏金属走线重叠的第二重叠区域，且所述第二重叠区域通过第二过孔与所述外围源漏金属走线电连接。
示例性的，所述显示单元还包括第一源漏金属层，所述第一源漏金属层包括薄膜晶体管的源极和漏极图案，其中所述外围源漏金属走线与所述第一源漏金属层同层且同材质设置。
示例性的，所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个自容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为金属网格层，至少另一个所述触控电极层为桥接金属层，所述金属网格层与所述桥接金属层通过所述绝缘层上的过孔连接，以形成自容式触控电极；或者
所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个互容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为发射电极层，至少另一个所述触控电极层为感应电极层，所述发射电极层与所述感应电极层之间通过所述绝缘层隔开，以形成互容式触控电极；或者
所述触控功能层为柔性单层屏上触控结构，所述触控功能层的膜层结构包括一触控电极层，所述触控电极层上的触控图案包括阵列分布的多个触控电极及连接至所述多个触控电极上的触控信号线。
第三方面，本公开实施例提供了一种显示装置，包括如上所述的显示面板。
第四方面，本公开提供了一种显示装置，包括如上所述的显示面板。
本公开实施例所带来的有益效果如下：
本公开一些实施例中提供的显示面板，通过在触控信号走线与显示信号走线之间增加信号屏蔽层，可以减少触控信号走线与显示信号走线之间产生信号串扰，从而保证触控功能不受影响，提高产品的工作稳定性和可靠性。本公开另一些实施例中提供的显示面板，通过将跨过隔离坝的触控信号走线 的线间距扩大，从而可降低由于隔离坝之间的金属残留导致的触控信号走线短路问题。由此可见，本公开实施例提供的显示面板可以提高显示产品的工作稳定性和可靠性。
附图说明
图1为相关技术中显示面板中触控功能层的触控图案的局部结构示意图；
图2为图1中虚线框的局部放大图；
图3为相关技术中显示面板的整体结构简单示意图；
图4为图3中E-E’方向上剖视图；
图5为图3中F-F’方向上剖视图；
图6为图3中虚线框B1处触控信号走线跨过隔离坝的结构示意图；
图7为本公开实施例提供的显示面板的主视图；
图8为本公开一些实施例中图7中B1处触控信号走线与隔离坝的结构示意图；
图9为本公开一些实施例中图7中B2处触控信号走线与隔离坝的结构示意图；
图10为本公开另一些实施例中图7中B1处触控信号走线与隔离坝的结构示意图；
图11为本公开另一些实施例中图7中B2处触控信号走线与隔离坝的结构示意图；
图12为本公开另一些实施例中图7中B1处触控信号走线与隔离坝的结构示意图；
图13为本公开另一些实施例中图7中B2处触控信号走线与隔离坝的结构示意图；
图14为本公开另一些实施例中图7中B1处触控信号走线与隔离坝的结构示意图；
图15为本公开另一些实施例中图7中B2处触控信号走线与隔离坝的结构示意图；
图16为本公开另一些实施例中图7中B1处触控信号走线与隔离坝的结 构示意图；
图17为本公开一些实施例中FSLOC显示面板的触控结构示意图；
图18为本公开一些实施例中FMLOC显示面板的触控结构示意图；
图19为本公开另一些实施例中图7中B1处布线示意图；
图20为本公开另一些实施例中图7中B1处布线示意图；
图21为本公开另一些实施例中图7中B1处布线示意图；
图22为本公开提供的显示面板的膜层堆叠结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在对本公开实施例提供的显示面板及显示装置进行详细说明之前，有必要对于相关技术进行以下说明：
在相关技术中，FMLOC(Flexible Multi-Layer On Cell)、FSLOC(Flexible Single-Layer On Cell)技术是利用掩模版工艺在OLED显示面板的封装层15上形成触控电路结构(即触控功能层)，实现将触控功能层集成于显示面板之上。 该触控电路结构可包括外围触控信号走线、及与外围触控信号走线连接的触控区域内的触控图案。触控图案可以是金属网格结构。触控功能层实现其触控功能的方式主要是互容与自容。
如图1和图2所示，从功能上来说，触控区域内的触控图案又可分为信号发射极(Tx)1、桥(Bridge)2、信号接收极(Rx)3以及无信号接入的虚拟(Dummy)区4。从膜层上来看，触控功能层可分为第一金属层(TMB)和第二金属层(TMA)，其中信号发射极1、信号接收极3以及虚拟区4可全部由第一金属层(TMB)形成，桥2可由第二金属层(TMA)形成，桥2通过第一金属层和第二金属层之间的绝缘层上过孔将第一金属层所形成的两部分信号发射极或信号接收极连接起来。工作时，触控芯片(Touch IC)基于手指加载前后信号发射极与信号接收极之间的容值Cm1(无手指加载前的电容值)、Cm2(手指加载后的电容值)以及容值的变化量△Cm，做出触控响应。
从膜层上来看，OLED显示面板的堆叠结构可包括：衬底、位于衬底之上的显示功能层及封装显示功能层的封装层15(IJP)。隔离坝(Dam)5是一种阻止封装层15外溢的凸起设计。如图3所示，显示面板6包括有效显示区域(AA区)和位于有效显示区域外围的外围区，隔离坝5可以环绕有效显示区域(AA区)一圈设置。如图4所示，隔离坝5可以由有机层形成，且在隔离坝5的有机层下方可以依次包括衬底52、栅极绝缘层、层间介质层54等，其中衬底51可以是包括有机层和无机层在内的多层结构，栅极绝缘层可以是一层或多层(例如图4中所示的栅极绝缘层包括第一栅极绝缘层531和第二栅极绝缘层532)，其可以是无机层结构；层间介质层可54以是无机层结构。
隔离坝5可设计成单隔离坝或双隔离坝结构，如图3和图4所示，隔离坝为双隔离坝结构为例，内圈隔离坝5a可称之为Dam1，外圈隔离坝5b可称之为Dam2。通常Dam1可由像素定义层(PDL)55以及隔垫柱(PS)56形成，Dam2可由有机绝缘层(PLN)57、像素定义层(PDL)55以及隔垫柱(PS)56形成，因此Dam2可比Dam1高。如图4和图5所示，绑定侧的隔离坝会减薄像素定义层55和隔垫柱56厚度，例如，图4和图5所示，绑定侧的隔离坝5去除隔垫柱56，仅留下像素定义层55。
对于FMLOC或FSLOC OLED产品来说，触控信号需要避免与显示信号产生串扰，进而影响触控功能。在显示面板的外围区域通常会布设多种信号走线，尤其是在连接绑定电路的绑定侧，外围触控信号走线需从绑定电路引出后跨过隔离坝与触控图案进行连接，因此在绑定侧的走线布线设计上需要规避触控信号走线和显示信号走线的信号串扰，以保证触控功能的稳定性和可靠性。
图为本公开一些实施例中提供的显示面板在绑定侧的局部布线(layout)图。
请参见图7，本公开一些实施例提供的显示面板10，其具有显示区(AA区)和位于所述显示区(AA区)外围的外围区，所述外围区至少一侧为绑定侧，在绑定侧具有绑定区C，绑定电路位于绑定区C内，所述在所述外围区设有至少部分围绕所述显示区(AA区)设置的隔离坝20。一些实施例中，隔离坝20包括内圈隔离坝21和外圈隔离坝22。
请参见图22，从膜层结构上看，所述显示面板10包括：衬底11、显示功能层12和触控功能层13。
所述显示功能层12包括显示驱动电路层120、位于所述显示区(AA区)的显示单元、及连接所述显示单元的多根显示信号走线，例如以所述显示面板10为OLED显示面板10为例，所述显示单元可以包括薄膜晶体管、阳极层122、有机电致发光层123及阴极层124，所述显示信号走线121可以包括位于外围区的外围显示信号走线。
所述显示功能层12远离衬底11的一侧为封装层15。所述触控功能层13位于所述封装层15上，其包括位于所述显示区(AA区)的触控图案、及至少部分位于所述外围区的多根触控信号走线131。
所述触控信号走线131与所述显示信号走线不同层设置。
其中，如图16所示，在所述绑定侧，具有相对设置的第一边界D1和第二边界D2、及位于所述第一边界D1和所述第二边界D2之间的第一走线区D，所述第一边界D1比所述第二边界D2更靠近所述显示区,也就是说，在所述绑定侧，所述显示区(AA区)的靠近所述隔离坝20的一侧边界为第一边界D1，所述隔离坝20的靠近所述显示区(AA区)的一侧边界为第二边界D2， 在所述第二边界D2与所述第一边界D1之间具有第一走线区。在所述第一走线区D，所述触控信号走线131沿第一方向X设置且从所述绑定电路引出并依次经由所述隔离坝20和所述第一走线区D连接至所述触控图案，所述显示信号走线沿与所述第一方向X相交的第二方向Y设置且在所述衬底11上的正投影与所述触控信号走线131存在交叉区域。
为了更为清楚说明以上方案，请参见图17，以显示面板10的绑定侧位于显示面板10的下边框为例，在显示面板10的下边框，外围触控信号走线131会从绑定电路引出之后，跨过隔离坝20并延伸至显示区(AA区)域内，再分别向左、右边框方向延伸而接入显示区(AA区)域内的触控图案上。显示面板10的显示区(AA区)域包括阵列分布的多个子像素，每个子像素内可对应一个阳极，而阴极层122通常设计为整面覆盖整个显示区(AA区)域，以图17所示为例，从隔离坝20的上边界(即第二边界D2)至显示区(AA区)域的第一边界D1(图中所示第一边界D1即为阴极层的下边界)之间的区域即为所述第一走线区D，在该第一走线区D内还布设有显示信号走线121，而触控信号走线131会与第一走线区D内的显示信号走线121交叉。
发明人经研究发现，在相关技术中，在绑定侧的显示区(AA区)域，触控信号走线131接入触控图案的区域，即第一走线区D靠近显示区(AA区)域的一侧，如图16和图19中所示A区域内，由于该A区域内触控信号走线131与显示信号走线121之间存在阴极层122或阳极层等膜层，这些膜层上接入有恒低直流信号(VSS)或恒高直流信号(VDD)，因此，能够很好的屏蔽触控信号走线131信号的串扰；同样的，在第一走线区D的远离显示区(AA区)域的一侧，即图16的虚线框B区域以及图19中所示的虚线框B’区域内，由于该B区域内存在源漏金属层(SD)，因此，也能够很好的屏蔽触控信号走线131信号的串扰。但是，由于窄边框限制，一些显示面板10在进行布线设计时，阴极层122或阳极层等膜层的下边界不会超出第一边界D1，也就是说，第一走线区D内的触控信号走线131与显示信号走线121之间不存在阴极层122或阳极层等膜层，这样，就导致触控信号走线131不能被很好的屏蔽，因此触控信号走线131存在串扰的风险。
因此，为了解决上述第一走线区D内的触控信号走线131与显示信号走 线121之间的信号串扰问题，本公开一些实施例中提供的显示面板10中，还包括在垂直所述衬底11方向上处于所述触控信号走线131与所述显示信号走线121之间的信号屏蔽层30，所述信号屏蔽层30在所述衬底11上的正投影至少覆盖所述第一走线区D内的所述触控信号走线131和所述显示信号走线121的交叉区域。
在上述方案中，通过在触控信号走线131与显示信号走线121之间增加信号屏蔽层30，可以减少触控信号走线131与显示信号走线121之间产生信号串扰，从而保证触控功能不受影响，提高产品的工作稳定性和可靠性。
在一些示例性的实施例中，由于显示面板10的堆叠结构中，在垂直所述衬底11方向上，在所述外围区域会在触控信号走线131与显示信号走线121之间设置绝缘层，且由于触控功能层13设置于封装层15之上，该绝缘层至少包括一层有机绝缘层。所述信号屏蔽层30位于所述有机绝缘层与所述触控信号走线131、或所述有机绝缘层与所述显示信号走线121之间。由于所述信号屏蔽层30需覆盖所述第一走线区D，因此其走线宽度较大，而有机绝缘层中存在气体，为了避免所述信号屏蔽层30出现“鼓包”，在所述信号屏蔽层30上设开口图案，且触控信号走线131与所述开口图案在所述衬底11上的正投影至少部分不重合。这样，通过在所述信号屏蔽层30上开设开口图案，可防止鼓包现象；且所述开口图案与所述触控信号走线131在衬底上的正投影至少部分不重合，示例性的，沿着所述第一方向上的触控信号走线131与所述开口图案在所述衬底11上的正投影不重合，以使所述开口图案位置避开所述触控信号走线131，可有效避免触控信号走线131通过所述开口图案与所述显示信号走线121相互干扰。
以图16和图17所示为例，示例性的，所述开口图案包括多个开孔31，至少相邻的两根所述触控信号走线131之间的间隙处设置有至少一个所述开孔31。即，至少部分触控信号走线可布设于开孔31之间。示例性的，任意相邻的两根所述触控信号走线131之间的间隙处设置有至少一个所述开孔31。其中开孔31的密度可以根据触控信号走线131的数量及间距等进行合理设计，以充分保证触控信号走线131的信号不被串扰。当然可以理解的是，所述开口图案的具体图案不限于此。
还需要说明的是，所述第一走线区D位于显示区(AA区)域与隔离坝20之间，该第一走线区D内不存在像素定义层挖孔以及隔垫柱等设计，因此，所述第一走线区D的像素定义层相对平坦，可减缓所述信号屏蔽层30爬坡引起的断线风险。
此外，所述信号屏蔽层30可接入恒低直流信号(VSS)或者恒高直流信号(VDD)，以更好地屏蔽干扰信号。
示例性的，所述显示单元包括阳极层124、有机电致发光层123和阴极层122，所述阳极层包括用于接入显示信号的阳极图案，所述信号屏蔽层30与所述阳极层124同层且同材质设置，且所述信号屏蔽层30与所述阳极图案之间不连接，所述信号屏蔽层30接入恒低直流信号或者恒高直流信号。
采用上述方案，可以将所述阳极层进行图案化处理时，通过同一次构图工艺在形成阳极图案时，形成所述信号屏蔽层30的图案，结构简单，且不会额外增加工艺步骤。
此外，在一些实施例中，所述显示面板10的外围区设有阴极搭接图案，阴极层的四周通过与所述阴极搭接图案搭接进行电连接，其中，至少部分所述阴极搭接图案位于所述绑定侧，且位于所述绑定侧和所述衬底的与所述绑定侧相邻的至少另一侧之间的过渡拐角区域。以图17所示的实施例为例，在一些显示面板10中，在图中E’区域内还设置有部分阴极搭接图案50，该部分阴极搭接图案50与阳极图案同层且同材质设置，且所述阴极搭接图案与所述阳极图案之间在所述衬底上的正投影不重合且彼此绝缘，且该阴极搭接图案50上可接入恒低直流信号，在该阴极搭接图案50上也可设开孔31图案，以避免“鼓包”现象。
一些实施例中，所述阴极搭接图案50与所述阴极层122在垂直于所述衬底11之上的正投影至少部分重合且电连接，且所述阴极层122接入恒低直流信号，以使所述阴极搭接图案50上接入恒低直流信号，且所述信号屏蔽层30与所述阴极搭接图案50连为一体，这样，可实现所述信号屏蔽层30接入恒低直流信号的目的。
此外，在一些实施例中，以图16和图17所示为例，所述阴极层122上接入恒低直流信号，所述阴极层靠近所述隔离坝20的一侧边界在所述衬底 11上的正投影不超出所述第一边界D1，所述信号屏蔽层30在靠近所述第一边界D1的一侧具有与所述阴极层122重叠的第一重叠区域，且所述第一重叠区域通过第一过孔与所述阴极层122电连接。
在上述方案中，所述信号屏蔽层30可直接与所述阴极层122搭接，以使所述信号屏蔽层30与所述阴极层122上均接入恒低直流信号。
并且，在一些实施例中，可以是所述信号屏蔽层30接入绑定电路上的恒低直流信号，再通过所述信号屏蔽层30与所述阴极层搭接，实现所述阴极层接入恒低直流信号的目的。
需要说明的是，在上述实施例中，所述信号屏蔽层30可与所述阴极层122接入恒低直流信号，其实现方式可以包括以下几种：
一是，所述信号屏蔽层30与所述阴极搭接图案50直接连为一体，实现与所述阴极层122均输入恒低直流信号的目的，此时，所述信号屏蔽层30在靠近所述阴极层122的一侧与所述阴极122层的第一边界D1直接可以重叠但不连接；
二是，所述信号屏蔽层30可在靠近所述阴极层的一侧与所述阴极层122的第一边界D1重叠且电连接，所述信号屏蔽层30与所述阴极搭接图案50之间不连接；
三是，所述信号屏蔽层30既与所述阴极搭接图案50连为一体，又可在靠近所述阴极层122的一侧与所述阴极层122的第一边界D1重叠且电连接。
此外，如图19所示，在所述第一方向X上，所述第二边界D2与所述显示信号走线121之间和/或所述第二边界D2与所述绑定电路之间还设有多个外围源漏金属走线40，所述外围源漏金属走线40上接入恒低直流信号(此时所述外围源漏金属走线40可以是指位于图19所示的C区域内的VSS线)，所述信号屏蔽层30在靠近所述第二边界D2的一侧具有与所述外围源漏金属走线40重叠的第二重叠区域，且所述第二重叠区域通过第二过孔与所述外围源漏金属走线40电连接。
上述方案中，所述外围源漏金属走线40可直接接入所述绑定电路上的恒低直流信号，所述信号屏蔽层30通过分别与所述外围源漏金属走线40、所述阴极层搭接，实现了阴极层和信号屏蔽层30上均接入恒低直流信号的目的。
此外，上述方案中，所述信号屏蔽层30上均接入恒低直流信号，在其他实施例中，信号屏蔽层30上均接入恒高直流信号时，所述外围源漏金属走线40上也可以是接入恒高直流信号(此时所述外围源漏金属走线40可以是指位于图所示的C区域内的VDD线)，所述信号屏蔽层30在靠近所述第二边界D2的一侧具有与所述外围源漏金属走线40重叠的第二重叠区域，且所述第二重叠区域通过第二过孔与所述外围源漏金属走线40电连接，从而，实现所述信号屏蔽层30上接入VDD信号的目的。
当然可以理解的是，以上仅是示例性实施例，在实际应用中，具体地所述信号屏蔽层30、阴极层的信号接入方式不限于此。
此外，从膜层上来看，所述显示单元中包括第一源漏金属层，所述第一源漏金属层包括薄膜晶体管的源极和漏极图案，其中所述外围源漏金属走线40与所述第一源漏金属层同层且同材质设置。
需要说明的是，所述显示单元可以是包括单层源漏金属层，也可以包括双层源漏金属层，所述第一源漏金属层可以是根据实际产品合理选择的任一源漏金属层。
此外，需要说明的是，所述显示信号走线121例如可以包括扫描信号线、发光控制信号线、参考电压信号线等。
此外，如图18所示，在一些实施例中，所述触控功能层13为柔性多层屏上触控结构(FMLOC)，所述触控图案包括阵列分布的多个自容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为金属网格层132，至少另一个所述触控电极层为桥接金属层133，所述金属网格层132与所述桥接金属层133通过所述绝缘层上的过孔连接，以形成自容式触控电极。
在其他实施方式中，所述触控功能层为柔性多层屏上触控结构(FMLOC)时，还可以是，所述触控图案包括阵列分布的多个互容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为发射电极层，至少另一个所述触控电极层为感应电极层，所述发射电极层与所述感应电极层之间通过所述绝缘层隔开，以形成互容式触控电极。具体结构此处不再赘述。进一步的， 触控功能层还可以包括覆盖在至少两个触控电极层背离驱动背板一侧的保护层，保护层可以对触控电极层起到保护作用，其可以为有机材料。
在另一些实施例中，如图17所示，所述触控功能层13还可以为柔性单层屏上触控结构(FSLOC)，所述触控功能层13的膜层结构包括一触控电极层，所述触控电极层上的触控图案包括阵列分布的多个触控电极132及连接至所述多个触控电极上的触控信号线131。具体结构此处不再赘述。图19所示可以是一种FMLOC显示面板的走线方案，其触控信号走线131数量相对较少，其触控信号走线131可从绑定电路引出后经由所述第一走线区D分别向在左、右边框方向延伸，可在所述第一走线区D设置所述信号屏蔽层30。
图20所示为一种FSLOC显示面板的走线示意图，图21所示为另一种FSLOC显示面板10的走线示意图。其中图21所示的显示面板10相较于图18所示的显示面板10，触控信号线走线增加，下边框减小。
请参见图20，由于触控信号走线131数量小于预定值，在图20中所示1和2区域处，阴极层以及源漏金属层可完全覆盖所述触控信号走线131，因此可无需设置所述信号屏蔽层30。
请参见图21，当触控信号走线131数量大于预定值，且在所述第二方向Y上分为多个子区域时，且绑定侧边框减小至预定宽度，其第一走线区D处触控信号走线131与显示信号走线121之间则需增加所述信号屏蔽层30，该信号屏蔽层30可接入恒高直流信号(VDD)。
由此可见，本公开实施例中的显示面板10可适用于FMLOC显示面板10，也可以适用于触控信号走线131数量大于预定值的FSLOC显示面板10。
其中所述预定值可以是根据实际产品性能等要求，通过经验而获取的数值。
此外，针对显示面板10的隔离坝20，由于其主要由有机层形成，为了防止有机层形成水汽通道，Dam2以外一定范围(例如大于40μm)、Dam1和Dam2之间(例如等于40μm)、Dam1以内一定范围内(例如大于40um)会完全去除有机绝缘层以及像素定义层等有机层，因此会形成较大的膜层段差。
如图6所示，在绑定侧，触控信号走线7需要跨过隔离坝5a和5b，为了 防止隔离坝5a和5b的坡度角大而导致触控信号走线7断线，如图4和图5所示，绑定侧的隔离坝20会减薄像素定义层55和隔垫柱56厚度，例如，图4和图5所示，绑定侧的隔离坝5去除隔垫柱56，仅留下像素定义层55。由于Dam1和Dam2之间为凹槽结构，触控信号走线1317在图案化处理时，经过曝光及刻蚀工艺容易留下金属残留，导致相邻两条走线短路，如图6所示，虚线框处易残留金属而导致短路。
为了解决上述问题，本公开一些实施例中，如图8至图16所示，其中图中a端即为触控信号走线131从绑定电路引出的一端，b端即为触控信号走线延伸至显示区域的一端，至少多根所述触控信号走线131在所述绑定电路引出的第一位置处相互平行且线间距为第一间距，在跨过所述隔离坝20的第二位置处相互平行且线间距为第二间距，所述第一间距小于所述第二间距。
采用上述方案，通过将跨过隔离坝20的触控信号走线131的线间距扩大，从而可降低由于隔离坝20之间的金属残留导致的触控信号走线131短路问题。
示例性的，至少多根所述触控信号走线131在所述衬底11上的正投影从所述第一位置平行引出并朝向相同或不同方向倾斜相同或不同角度后平行延伸至所述第二位置。
采用上述方案，将绑定电路引出的触控信号走线131先进行斜向发散布线，在靠近隔离坝20位置再沿垂直隔离坝20方向布线，使跨过隔离坝20位置的触控信号走线131间距拉大，以降低短路风险。
其中，斜向发散布线可分为固定角度和非固定角度。即，每根所述触控信号走线131倾斜相同角度或倾斜不同角度。
如图8至图11所示为多根所述触控信号走线131倾斜相同角度时的布线结构示意图；如图12至图15所示为多根所述触控信号走线131倾斜不同角度时的布线结构示意图。
需要说明的是，在一些实施例中，无论多根所述触控信号走线131倾斜相同角度或不同角度，从所述绑定电路引出时，多根触控信号走线131为平行引出，且斜向发散后，以垂直于隔离坝20方向平行跨过隔离坝20，再继续平行延伸至显示区(AA区)域内。
此外，还需要说明的是，上述方案中，为了实现触控信号走线131跨过 隔离坝20时间距增大，通过将绑定电路引出的触控信号走线131先进行斜向发散布线的方式拉大线间距，在其他未示意出的实施例中，根据实际产品空间布线需求，也可以是触控信号走线131经过绕线设计(例如弧线设计而非斜线设计)等方式实现线间距的拉大。
此外，示例性的，如图8和图9、图12和图13所示，所述触控信号走线131可以是仅分为在第二方向Y上分为至少一个子区域，每个子区域内靠近显示面板在第二方向Y上的边缘侧的多根触控信号走线131呈斜向发散状布线，而在靠近显示面板第二方向Y上中间位置的触控信号走线131可以不斜向布线可呈直线状延伸。
如图10和图11、图14和图15所示，在另一些实施例中，每个所述子区域内的多根所述触控信号走线131以在所述第二方向Y上处于中间的一根所述触控信号走线131为中心呈对称分布，且位于中间的一根所述触控信号走线131不斜向布线可呈直线状延伸。
此外，本公开实施例提供的显示面板10其显示区(AA区)域的形状可以是圆形、矩形或者其他形状。
此外，本公开实施例提供的显示面板10的制造方法可以包括如下步骤：
步骤S01、在衬底11上制作显示功能层12，并进行封装形成封装层15，其中所述显示功能层12包括位于所述显示区(AA区)的显示单元、及连接所述显示单元的多根显示信号走线121，在外围区设围绕所述显示区(AA区)设置的隔离坝20，其中在所述绑定侧，所述显示区(AA区)的靠近所述隔离坝20的一侧边界为第一边界D1，所述隔离坝20的靠近所述显示区(AA区)的一侧边界为第二边界D2，在所述第二边界D2与所述第一边界D1之间具有第一走线区D，在所述第一走线区D，所述显示信号走线121沿第二方向Y设置；
步骤S02、在封装层15上形成触控功能层13，所述触控功能层13包括位于所述显示区(AA区)的触控图案、及位于所述外围区的多根触控信号走线131，所述触控信号走线131与所述显示信号走线121不同层设置，在所述第一走线区D，所述触控信号走线131沿第一方向X设置且从所述绑定电路引出并依次经由所述隔离坝20和所述第一走线区D连接至所述触控图案， 所述显示信号走线121在所述衬底11上的正投影与所述触控信号走线131交叉；
其中步骤S01中，在垂直所述衬底11方向上处于所述触控信号走线131与所述显示信号走线121之间形成信号屏蔽层30，所述信号屏蔽层30在所述衬底11上的正投影至少覆盖所述第一走线区D。
上述步骤S01具体包括：
步骤S011、采用同一次构图工艺形成所述显示单元中的阳极层和所述信号屏蔽层30。
其中，该构图工艺可以选用常规的阳极层图案化工艺，例如包括曝光、显影、刻蚀等步骤，对其具体工艺不再进行详述，仅需要在常规的图案化工艺中对掩模板的图案进行改进，在原有的阳极图案基础上增加相应的信号屏蔽层30图案即可。
此外，本公开实施例还提供了一种显示面板10，其具有显示区(AA区)和位于所述显示区(AA区)外围的外围区，所述外围区至少一侧为连接有绑定电路的绑定侧，在所述外围区设有围绕所述显示区(AA区)设置的隔离坝20；
所述显示面板10包括：
衬底11；
显示功能层12，所述显示功能层12包括位于所述显示区(AA区)的显示单元、及连接所述显示单元的显示信号走线121；及
触控功能层13，所述触控功能层13包括位于所述显示区(AA区)的触控图案、及位于所述外围区的触控信号走线131，所述触控信号走线131与所述显示信号走线121不同层设置；
在所述绑定侧，所述触控信号走线131沿第一方向X设置且从所述绑定电路引出并依次经由所述隔离坝20连接至所述触控图案，如图8至图16所示，其中图中a端即为触控信号走线131从绑定电路引出的一端，b端即为触控信号走线延伸至显示区域的一端，至少多根所述触控信号走线131在所述绑定电路引出的第一位置处相互平行且线间距为第一间距，在跨过所述隔离坝20的第二位置处相互平行且线间距为第二间距，所述第一间距小于所述第 二间距。
采用上述方案，通过将跨过隔离坝20的触控信号走线131的线间距扩大，从而可降低由于隔离坝20之间的金属残留导致的触控信号走线131短路问题。
示例性的，至少多根所述触控信号走线131在所述衬底11上的正投影从所述第一位置平行引出并朝向相同或不同方向倾斜相同或不同角度后平行延伸至所述第二位置。
采用上述方案，将绑定电路引出的触控信号走线131先进行斜向发散布线，在靠近隔离坝20位置再沿垂直隔离坝20方向布线，使跨过隔离坝20位置的触控信号走线131间距拉大，以降低短路风险。
其中，斜向发散布线可分为固定角度和非固定角度。即，每根所述触控信号走线131倾斜相同角度或倾斜不同角度。
如图8至图11所示为多根所述触控信号走线131倾斜相同角度时的布线结构示意图；如图12至图15所示为多根所述触控信号走线131倾斜不同角度时的布线结构示意图。
需要说明的是，在一些实施例中，无论多根所述触控信号走线131倾斜相同角度或不同角度，从所述绑定电路引出时，多根触控信号走线131为平行引出，且斜向发散后，以垂直于隔离坝20方向平行跨过隔离坝20，再继续平行延伸至显示区(AA区)域内。
此外，还需要说明的是，上述方案中，为了实现触控信号走线131跨过隔离坝20时间距增大，通过将绑定电路引出的触控信号走线131先进行斜向发散布线的方式拉大线间距，在其他未示意出的实施例中，根据实际产品空间布线需求，也可以是触控信号走线131经过绕线设计(例如弧线设计而非斜线设计)等方式实现线间距的拉大。
此外，示例性的，如图8和图9、图12和图13所示，所述触控信号走线131可以是仅分为在第二方向Y上分为至少一个子区域，每个子区域内靠近显示面板在第二方向Y上的边缘侧的多根触控信号走线131呈斜向发散状布线，而在靠近显示面板第二方向Y上中间位置的触控信号走线131可以不斜向布线可呈直线状延伸。
如图10和图11、图14和图15所示，在另一些实施例中，每个所述子 区域内的多根所述触控信号走线131以在所述第二方向Y上处于中间的一根所述触控信号走线131为中心呈对称分布，且位于中间的一根所述触控信号走线131不斜向布线可呈直线状延伸。
此外，本公开实施例提供的显示面板10其显示区(AA区)域的形状可以是圆形、矩形或者其他形状。
此外，本公开实施例提供的显示面板10的制造方法可以包括如下步骤：
步骤S01、在衬底11上制作显示功能层12，并进行封装形成封装层15，其中所述显示功能层12包括位于所述显示区(AA区)的显示单元、及连接所述显示单元的多根显示信号走线121，在外围区设围绕所述显示区(AA区)设置的隔离坝20，其中在所述绑定侧，所述显示区(AA区)的靠近所述隔离坝20的一侧边界为第一边界D1，所述隔离坝20的靠近所述显示区(AA区)的一侧边界为第二边界D2，在所述第二边界D2与所述第一边界D1之间具有第一走线区D，在所述第一走线区D，所述显示信号走线121沿第二方向Y设置；
步骤S02、在封装层15上形成触控功能层13，所述触控功能层13包括位于所述显示区(AA区)的触控图案、及位于所述外围区的多根触控信号走线131，所述触控信号走线131与所述显示信号走线121不同层设置，在所述第一走线区D，所述触控信号走线131沿第一方向X设置且从所述绑定电路引出并依次经由所述隔离坝20和所述第一走线区D连接至所述触控图案，所述显示信号走线121在所述衬底11上的正投影与所述触控信号走线131交叉；
其中步骤S01中，在垂直所述衬底11方向上处于所述触控信号走线131与所述显示信号走线121之间形成信号屏蔽层30，所述信号屏蔽层30在所述衬底11上的正投影至少覆盖所述第一走线区D。
示例性的，至少多根所述触控信号走线131在所述衬底11上的正投影从所述第一位置平行引出并朝向相同或不同方向倾斜相同或不同角度后平行延伸至所述第二位置。
采用上述方案，将绑定电路引出的触控信号走线131先进行斜向发散布线，在靠近隔离坝20位置再沿垂直隔离坝20方向布线，使跨过隔离坝20位 置的触控信号走线131间距拉大，以降低短路风险。
其中，斜向发散布线可分为固定角度和非固定角度。即，每根所述触控信号走线131倾斜相同角度或倾斜不同角度。
如图所示为多根所述触控信号走线131倾斜相同角度时的布线结构示意图；如图所示为多根所述触控信号走线131倾斜不同角度时的布线结构示意图。
需要说明的是，在一些实施例中，无论多根所述触控信号走线131倾斜相同角度或不同角度，从所述绑定电路引出时，多根触控信号走线131为平行引出，且斜向发散后，以垂直于隔离坝20方向平行跨过隔离坝20，再继续平行延伸至显示区(AA区)域内。
此外，还需要说明的是，上述方案中，为了实现触控信号走线131跨过隔离坝20时间距增大，通过将绑定电路引出的触控信号走线131先进行斜向发散布线的方式拉大线间距，在其他未示意出的实施例中，根据实际产品空间布线需求，也可以是触控信号走线131经过绕线设计(例如弧线设计而非斜线设计)等方式实现线间距的拉大。
示例性的，所述触控信号走线131在所述第二方向Y上分为多个子区域，每个所述子区域内的多根所述触控信号走线131以在所述第二方向Y上处于中间的一根所述触控信号走线131为中心呈对称分布。
示例性的，在所述绑定侧，所述显示区(AA区)的靠近所述隔离坝20的一侧边界为第一边界D1，所述隔离坝20的靠近所述显示区(AA区)的一侧边界为第二边界D2，在所述第二边界D2与所述第一边界D1之间具有第一走线区D；
所述显示面板10还包括在垂直所述衬底11方向上处于所述触控信号走线131与所述显示信号走线121之间的信号屏蔽层30，所述信号屏蔽层30在所述衬底11上的正投影至少覆盖所述第一走线区D。
在一些示例性的实施例中，由于显示面板10的堆叠结构中，在垂直所述衬底11方向上，在所述外围区域会在触控信号走线131与显示信号走线121之间设置绝缘层，且由于触控功能层13设置于封装层15之上，该绝缘层至少包括一层有机绝缘层。所述信号屏蔽层30位于所述有机绝缘层与所述触控 信号走线131、或所述有机绝缘层与所述显示信号走线121之间。由于所述信号屏蔽层30需覆盖所述第一走线区D，因此其走线宽度较大，而有机绝缘层中存在气体，为了避免所述信号屏蔽层30出现“鼓包”，在所述信号屏蔽层30上设开口图案，且所述触控信号走线131与所述开口图案在所述衬底11上的正投影不重合。这样，通过在所述信号屏蔽层30上开设开口图案，可防止鼓包现象，且所述开口图案位置避开所述触控信号走线131，可有效避免触控信号走线131通过所述开口图案与所述显示信号走线121相互干扰。
以图5所示为例，示例性的，所述开口图案包括多个开孔31，任意相邻的两根所述触控信号走线131之间的间隙处设置有至少一个所述开孔31。也就是说，将所述触控信号走线131设置于所述开孔31之间。其中开孔31的密度可以根据触控信号走线131的数量及间距等进行合理设计，以充分保证触控信号走线131的信号不被串扰。当然可以理解的是，所述开口图案的具体图案不限于此。
还需要说明的是，所述第一走线区D位于显示区(AA区)域与隔离坝20之间，该第一走线区D内不存在像素定义层挖孔以及隔垫柱等设计，因此，所述第一走线区D的像素定义层相对平坦，可减缓所述信号屏蔽层30爬坡引起的断线风险。
此外，如图16所示，在绑定侧如图16中虚线框D’所示还设有虚拟触控信号线60，该虚拟触控信号线60与显示信号走线121之间可不设置所述信号屏蔽层。
此外，所述信号屏蔽层30可接入恒低直流信号(VSS)或者恒高直流信号(VDD)，以更好地屏蔽干扰信号。
示例性的，所述显示单元包括阳极层、有机电致发光层和阴极层，
所述阳极层包括用于接入显示信号的阳极图案，所述信号屏蔽层30与所述阳极层124同层且同材质设置，且所述信号屏蔽层30与所述阳极图案之间不连接，所述信号屏蔽层30接入恒低直流信号或者恒高直流信号。
采用上述方案，可以将所述阳极层进行图案化处理时，通过同一次构图工艺在形成阳极图案时，形成所述信号屏蔽层30的图案，结构简单，且不会额外增加工艺步骤。
此外，在一些实施例中，所述显示面板10的外围区设有阴极搭接图案，阴极层的四周通过与所述阴极搭接图案搭接进行电连接，其中，至少部分所述阴极搭接图案位于所述绑定侧，且位于所述绑定侧和所述衬底的与所述绑定侧相邻的至少另一侧之间的过渡拐角区域。以图17所示的实施例为例，在一些显示面板10中，
在图中E’区域内还设置有部分阴极搭接图案50，该部分阴极搭接图案50与阳极图案同层且同材质设置，且所述阴极搭接图案与所述阳极图案之间在所述衬底上的正投影不重合且彼此绝缘，且该阴极搭接图案50上可接入恒低直流信号，在该阴极搭接图案50上也可设开孔31图案，以避免“鼓包”现象。
一些实施例中，0与所述阴极层122在垂直于所述衬底11之上的正投影至少部分重合且电连接，且所述阴极层122接入恒低直流信号，以使所述阴极搭接图案50上接入恒低直流信号，且所述信号屏蔽层30与所述阴极搭接图案50连为一体，这样，可实现所述信号屏蔽层30接入恒低直流信号的目的。
此外，在一些实施例中，以图16和图17所示为例，所述阴极层122上接入恒低直流信号，所述阴极层靠近所述隔离坝20的一侧边界在所述衬底11上的正投影不超出所述第一边界D1，所述信号屏蔽层30在靠近所述第一边界D1的一侧具有与所述阴极层122重叠的第一重叠区域，且所述第一重叠区域通过第一过孔与所述阴极层122电连接。
在上述方案中，所述信号屏蔽层30可直接与所述阴极层122搭接，以使所述信号屏蔽层30与所述阴极层122上均接入恒低直流信号。
并且，在一些实施例中，可以是所述信号屏蔽层30接入绑定电路上的恒低直流信号，再通过所述信号屏蔽层30与所述阴极层搭接，实现所述阴极层接入恒低直流信号的目的。
需要说明的是，在上述实施例中，所述信号屏蔽层30可与所述阴极层接入恒低直流信号，其实现方式可以包括以下几种：
一是，所述信号屏蔽层30与所述阴极搭接图案50直接连为一体，实现与所述阴极层均输入恒低直流信号的目的，此时，所述信号屏蔽层30在靠近 所述阴极层的一侧与所述阴极层的第一边界直接可以重叠但不连接；
二是，所述信号屏蔽层30可在靠近所述阴极层的一侧与所述阴极层的第一边界重叠且电连接，所述信号屏蔽层30与所述阴极搭接图案50之间不连接；
三是，所述信号屏蔽层30既与所述阴极搭接图案50连为一体，又可在靠近所述阴极层的一侧与所述阴极层的第一边界重叠且电连接。
此外，如图19所示，在所述第一方向X上，所述第二边界D2与所述显示信号走线121之间和/或所述第二边界D2与所述绑定电路之间还设有多个外围源漏金属走线40，所述外围源漏金属走线40上接入恒低直流信号(此时所述外围源漏金属走线40可以是指位于图17所示的C区域内的VSS线)，所述信号屏蔽层30在靠近所述第二边界D2的一侧具有与所述外围源漏金属走线40重叠的第二重叠区域，且所述第二重叠区域通过第二过孔与所述外围源漏金属走线40电连接。
上述方案中，所述外围源漏金属走线40可直接接入所述绑定电路上的恒低直流信号，所述信号屏蔽层30通过分别与所述外围源漏金属走线40、所述阴极层搭接，实现了阴极层和信号屏蔽层30上均接入恒低直流信号的目的。
此外，上述方案中，所述信号屏蔽层30上均接入恒低直流信号，在其他实施例中，信号屏蔽层30上均接入恒高直流信号时，所述外围源漏金属走线40上也可以是接入恒高直流信号(此时所述外围源漏金属走线40可以是指位于图所示的C区域内的VDD线)，所述信号屏蔽层30在靠近所述第二边界D2的一侧具有与所述外围源漏金属走线40重叠的第二重叠区域，且所述第二重叠区域通过第二过孔与所述外围源漏金属走线40电连接，从而，实现所述信号屏蔽层30上接入VDD信号的目的。
当然可以理解的是，以上仅是示例性实施例，在实际应用中，具体地所述信号屏蔽层30、阴极层的信号接入方式不限于此。
此外，从膜层上来看，所述显示单元中包括第一源漏金属层，所述第一源漏金属层包括薄膜晶体管的源极和漏极图案，其中所述外围源漏金属走线40与所述第一源漏金属层同层且同材质设置。
需要说明的是，所述显示单元可以是包括单层源漏金属层，也可以包括 双层源漏金属层，所述第一源漏金属层可以是根据实际产品合理选择的任一源漏金属层。
此外，需要说明的是，所述显示信号走线121例如可以包括扫描信号线、发光控制信号线、参考电压信号线等。此外，在一些实施例中，所述触控功能层为柔性多层屏上触控结构(FMLOC)，所述触控图案包括阵列分布的多个自容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为金属网格层，至少另一个所述触控电极层为桥接金属层，所述金属网格层与所述桥接金属层通过所述绝缘层上的过孔连接，以形成自容式触控电极。在其他实施方式中，所述触控功能层为柔性多层屏上触控结构(FMLOC)时，还可以是，所述触控图案包括阵列分布的多个互容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为发射电极层，至少另一个所述触控电极层为感应电极层，所述发射电极层与所述感应电极层之间通过所述绝缘层隔开，以形成互容式触控电极。具体结构此处不再赘述。进一步的，触控功能层还可以包括覆盖在至少两个触控电极层背离驱动背板一侧的保护层，保护层可以对触控电极层起到保护作用，其可以为有机材料。
在另一些实施例中，所述触控功能层还可以为柔性单层屏上触控结构(FSLOC)，所述触控功能层的膜层结构包括一触控电极层，所述触控电极层上的触控图案包括阵列分布的多个触控电极及连接至所述多个触控电极上的触控信号线。具体结构此处不再赘述。
此外，图17所示可以是一种FMLOC显示面板10的走线方案，其触控信号走线131数量相对较少，其触控信号走线131可从绑定电路引出后经由所述第一走线区D分别向在左、右边框方向延伸，可在所述第一走线区D设置所述信号屏蔽层30。
图18所示为一种FSLOC显示面板10的走线示意图，图19所示为另一种FSLOC显示面板10的走线示意图。其中图19所示的显示面板10相较于图18所示的显示面板10，触控信号线走线增加，下边框减小。
请参见图18，由于触控信号走线131数量小于预定值，在图18中所示1 和2区域处，阴极层以及源漏金属层可完全覆盖所述触控信号走线131，因此可无需设置所述信号屏蔽层30。
请参见图19，当触控信号走线131数量大于预定值，且在所述第二方向Y上分为多个子区域时，且绑定侧边框减小至预定宽度，其第一走线区D处触控信号走线131与显示信号走线121之间则需增加所述信号屏蔽层30，该信号屏蔽层30可接入恒高直流信号(VDD)。
由此可见，本公开实施例中的显示面板10可适用于FMLOC显示面板10，也可以适用于触控信号走线131数量大于预定值的FSLOC显示面板10。
此外，本公开实施例提供的显示面板10的制造方法可以包括如下步骤：
步骤S01、在衬底11上制作显示功能层12，并进行封装形成封装层15，其中所述显示功能层12包括位于所述显示区(AA区)的显示单元、及连接所述显示单元的多根显示信号走线121，在外围区设围绕所述显示区(AA区)设置的隔离坝20，其中在所述绑定侧，所述显示区(AA区)的靠近所述隔离坝20的一侧边界为第一边界D1，所述隔离坝20的靠近所述显示区(AA区)的一侧边界为第二边界D2，在所述第二边界D2与所述第一边界D1之间具有第一走线区D，在所述第一走线区D，所述显示信号走线121沿第二方向Y设置；
步骤S02、在封装层15上形成触控功能层13，所述触控功能层13包括位于所述显示区(AA区)的触控图案、及位于所述外围区的多根触控信号走线131，所述触控信号走线131与所述显示信号走线121不同层设置，在所述绑定侧，所述触控信号走线131沿第一方向X设置且从所述绑定电路引出并经由所述隔离坝20连接至所述触控图案，且至少多根所述触控信号走线131在所述绑定电路引出的第一位置处相互平行且线间距为第一间距，在跨过所述隔离坝20的第二位置处相互平行且线间距为第二间距，所述第一间距小于所述第二间距。
上述步骤S01具体包括：
步骤S011’、在垂直所述衬底11方向上处于所述触控信号走线131与所述显示信号走线121之间形成信号屏蔽层30，所述信号屏蔽层30在所述衬底11上的正投影至少覆盖所述第一走线区D。
其中步骤S011’中，可采用同一次构图工艺形成所述显示单元中的阳极层和所述信号屏蔽层30。
其中，该构图工艺可以选用常规的阳极层图案化工艺，例如包括曝光、显影、刻蚀等步骤，对其具体工艺不再进行详述，仅需要在常规的图案化工艺中对掩模板的图案进行改进，在原有的阳极图案基础上增加相应的信号屏蔽层30图案即可。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (30)

  1. 一种显示面板，其具有显示区和位于所述显示区外围的外围区，所述外围区至少一侧为连接有绑定电路的绑定侧，在所述外围区设有至少部分围绕所述显示区设置的隔离坝；
    所述显示面板包括：
    衬底；
    显示功能层，所述显示功能层包括位于所述显示区的显示单元、及连接所述显示单元的位于至少部分所述外围区的多根显示信号走线；及
    触控功能层，所述触控功能层包括位于所述显示区的触控图案、及位于至少部分所述外围区的多根触控信号走线，所述触控信号走线与所述显示信号走线不同层设置；
    其中在所述绑定侧，具有相对设置的第一边界和第二边界、及位于所述第一边界和所述第二边界之间的第一走线区，所述第一边界比所述第二边界更靠近所述显示区；
    在所述第一走线区，所述触控信号走线沿第一方向设置且从所述绑定电路引出并依次经由所述隔离坝和所述第一走线区连接至所述触控图案，所述显示信号走线沿与所述第一方向相交的第二方向设置且在所述衬底上的正投影与所述触控信号走线存在交叉区域；
    其特征在于，所述显示面板还包括在垂直所述衬底方向上处于所述触控信号走线与所述显示信号走线之间的信号屏蔽层，所述信号屏蔽层在所述衬底上的正投影至少部分覆盖所述第一走线区内的所述触控信号走线和所述显示信号走线的交叉区域。
  2. 根据权利要求1所述的显示面板，其特征在于，所述信号屏蔽层上设有开口图案，且触控信号走线与所述开口图案在所述衬底上的正投影至少部分不重合。
  3. 根据权利要求2所述的显示面板，其特征在于，沿着所述第一方向上的触控信号走线与所述开口图案在所述衬底上的正投影不重合。
  4. 根据权利要求3所述的显示面板，其特征在于，所述开口图案包括多个开孔，至少相邻的两根所述触控信号走线之间的间隙处设置有至少一个所 述开孔。
  5. 根据权利要求1所述的显示面板，其特征在于，所述显示单元包括阳极层、有机电致发光层和阴极层，所述阳极层包括用于接入显示信号的阳极图案，所述信号屏蔽层与所述阳极图案同层且同材质设置，且所述信号屏蔽层与所述阳极图案之间不连接，所述信号屏蔽层接入恒低直流信号或者恒高直流信号。
  6. 根据权利要求5所述的显示面板，其特征在于，
    所述显示面板还包括：与所述阳极图案同层且同材质设置的阴极搭接图案，所述阴极搭接图案与所述阳极图案之间在所述衬底上的正投影不重合且彼此绝缘，所述阴极搭接图案与所述阴极层在垂直于所述衬底之上的正投影至少部分重合且电连接，且所述阴极层接入恒低直流信号，所述信号屏蔽层与所述阴极搭接图案连为一体；和/或
    所述阴极层上接入恒低直流信号，所述阴极层靠近所述隔离坝的一侧边界在所述衬底上的正投影不超出所述第一边界，所述信号屏蔽层在靠近所述第一边界的一侧具有与所述阴极层重叠的第一重叠区域，且所述第一重叠区域通过第一过孔与所述阴极层电连接。
  7. 根据权利要求6所述的显示面板，其特征在于，
    所述阴极搭接图案至少部分位于所述绑定侧，且位于所述绑定侧和所述衬底的与所述绑定侧相邻的至少另一侧之间的过渡拐角区域。
  8. 根据权利要求5或6所述的显示面板，其特征在于，
    所述显示面板还包括封装所述显示功能层的封装层，所述触控功能层直接设置在所述封装层的远离所述衬底的一侧；
    所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个自容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为金属网格层，至少另一个所述触控电极层为桥接金属层，所述金属网格层与所述桥接金属层通过所述绝缘层上的过孔连接，以形成自容式触控电极；或者
    所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布 的多个互容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为发射电极层，至少另一个所述触控电极层为感应电极层，所述发射电极层与所述感应电极层之间通过所述绝缘层隔开，以形成互容式触控电极。
  9. 根据权利要求5所述的显示面板，其特征在于，
    在所述第一方向上，所述第二边界与所述显示信号走线之间和/或所述第二边界与所述绑定电路之间还设有多个外围源漏金属走线，所述外围源漏金属走线上接入恒低直流信号或恒高直流信号，所述信号屏蔽层在靠近所述第二边界的一侧具有与所述外围源漏金属走线重叠的第二重叠区域，且所述第二重叠区域通过第二过孔与所述外围源漏金属走线电连接。
  10. 根据权利要求9所述的显示面板，其特征在于，所述显示单元还包括第一源漏金属层，所述第一源漏金属层包括薄膜晶体管的源极和漏极图案，其中所述外围源漏金属走线与所述第一源漏金属层同层且同材质设置。
  11. 根据权利要求10所述的显示面板，其特征在于，所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个自容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为金属网格层，至少另一个所述触控电极层为桥接金属层，所述金属网格层与所述桥接金属层通过所述绝缘层上的过孔连接，以形成自容式触控电极；或者
    所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个互容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为发射电极层，至少另一个所述触控电极层为感应电极层，所述发射电极层与所述感应电极层之间通过所述绝缘层隔开，以形成互容式触控电极；或者
    所述触控功能层为柔性单层屏上触控结构，所述触控功能层的膜层结构包括一触控电极层，所述触控电极层上的触控图案包括阵列分布的多个触控电极及连接至所述多个触控电极上的触控信号线。
  12. 根据权利要求1至11任一项所述的显示面板，其特征在于，至少多 根所述触控信号走线在所述绑定电路引出的第一位置处相互平行且线间距为第一间距，在跨过所述隔离坝的第二位置处相互平行且线间距为第二间距，所述第一间距小于所述第二间距。
  13. 根据权利要求12所述的显示面板，其特征在于，至少多根所述触控信号走线在所述衬底上的正投影从所述第一位置平行引出并朝向相同或不同方向倾斜相同或不同角度后平行延伸至所述第二位置。
  14. 根据权利要求13所述的显示面板，其特征在于，所述触控信号走线在所述第二方向上分为多个子区域，每个所述子区域内的多根所述触控信号走线以在所述第二方向上处于中间的一根所述触控信号走线为中心呈对称分布。
  15. 一种显示面板，其具有显示区和位于所述显示区外围的外围区，所述外围区至少一侧为连接有绑定电路的绑定侧，在所述外围区设有至少部分围绕所述显示区设置的隔离坝；
    所述显示面板包括：
    衬底；
    显示功能层，所述显示功能层包括位于所述显示区的显示单元、及连接所述显示单元的位于至少部分所述外围区的显示信号走线；及
    触控功能层，所述触控功能层包括位于所述显示区的触控图案、及位于至少部分所述外围区的触控信号走线，所述触控信号走线与所述显示信号走线不同层设置；
    其特征在于，
    在所述绑定侧，所述触控信号走线沿第一方向设置且从所述绑定电路引出并经由所述隔离坝连接至所述触控图案，且至少多根所述触控信号走线在所述绑定电路引出的第一位置处相互平行且线间距为第一间距，在跨过所述隔离坝的第二位置处相互平行且线间距为第二间距，所述第一间距小于所述第二间距。
  16. 根据权利要求15所述的显示面板，其特征在于，至少多根所述触控信号走线在所述衬底上的正投影从所述第一位置平行引出并朝向相同或不同方向倾斜相同或不同角度后平行延伸至所述第二位置。
  17. 根据权利要求16所述的显示面板，其特征在于，所述触控信号走线在第二方向上分为多个子区域，所述第二方向与所述第一方向交叉，每个所述子区域内的多根所述触控信号走线以在所述第二方向上处于中间的一根所述触控信号走线为中心呈对称分布。
  18. 根据权利要求15至17任一项所述的显示面板，其特征在于，在所述绑定侧，所述显示区的靠近所述隔离坝的一侧边界为第一边界，所述隔离坝的靠近所述显示区的一侧边界为第二边界，在所述第二边界与所述第一边界之间具有第一走线区；
    在所述第一走线区，所述触控信号走线沿第一方向设置且从所述绑定电路引出并依次经由所述隔离坝和所述第一走线区连接至所述触控图案，所述显示信号走线沿与所述第一方向交叉的第二方向设置且在所述衬底上的正投影与所述触控信号走线存在交叉区域；
    所述显示面板还包括在垂直所述衬底方向上处于所述触控信号走线与所述显示信号走线之间的信号屏蔽层，所述信号屏蔽层在所述衬底上的正投影至少覆盖所述第一走线区内的所述触控信号走线和所述显示信号走线的交叉区域。
  19. 根据权利要求18所述的显示面板，其特征在于，所述信号屏蔽层上设有开口图案，且所述触控信号走线与所述开口图案在所述衬底上的正投影不重合。
  20. 根据权利要求19所述的显示面板，其特征在于，在垂直所述衬底方向上，所述触控信号走线与所述显示信号走线之间具有至少一层有机绝缘层，所述信号屏蔽层位于所述有机绝缘层与所述触控信号走线、或所述有机绝缘层与所述显示信号走线之间。
  21. 根据权利要求20所述的显示面板，其特征在于，沿着所述第一方向上的触控信号走线与所述开口图案在所述衬底上的正投影不重合。
  22. 根据权利要求21所述的显示面板，其特征在于，所述开口图案包括多个开孔，至少相邻的两根所述触控信号走线之间的间隙处设置有至少一个所述开孔。
  23. 根据权利要求14所述的显示面板，其特征在于，所述显示单元包括 阳极层、有机电致发光层和阴极层，所述阳极层包括用于接入显示信号的阳极图案，所述信号屏蔽层与所述阳极图案同层且同材质设置，且所述信号屏蔽层与所述阳极图案之间不连接，所述信号屏蔽层接入恒低直流信号或者恒高直流信号。
  24. 根据权利要求23所述的显示面板，其特征在于，
    所述显示面板还包括：与所述阳极图案同层且同材质设置的阴极搭接图案，所述阴极搭接图案与所述阳极图案之间在所述衬底上的正投影不重合且彼此绝缘，所述阴极搭接图案与所述阴极层在垂直于所述衬底之上的正投影至少部分重合且电连接，且所述阴极层接入恒低直流信号，所述信号屏蔽层与所述阴极搭接图案连为一体；和/或
    所述阴极层上接入恒低直流信号，所述阴极层靠近所述隔离坝的一侧边界在所述衬底上的正投影不超出所述第一边界，所述信号屏蔽层在靠近所述第一边界的一侧具有与所述阴极层重叠的第一重叠区域，且所述第一重叠区域通过第一过孔与所述阴极层电连接。
  25. 根据权利要求24所述的显示面板，其特征在于，
    所述阴极搭接图案位于所述绑定侧，且位于所述绑定侧和所述衬底的与所述绑定侧相邻的至少另一侧之间的过渡拐角区域。
  26. 根据权利要求24所述的显示面板，其特征在于，
    所述显示面板还包括封装所述显示功能层的封装层，所述触控功能层直接设置在所述封装层的远离所述衬底的一侧；
    所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个自容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为金属网格层，至少另一个所述触控电极层为桥接金属层，所述金属网格层与所述桥接金属层通过所述绝缘层上的过孔连接，以形成自容式触控电极；或者
    所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个互容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极 层为发射电极层，至少另一个所述触控电极层为感应电极层，所述发射电极层与所述感应电极层之间通过所述绝缘层隔开，以形成互容式触控电极。
  27. 根据权利要求24所述的显示面板，其特征在于，
    在所述第一方向上，所述第二边界与所述显示信号走线之间和/或所述第二边界与所述绑定电路之间还设有多个外围源漏金属走线，所述外围源漏金属走线上接入恒低直流信号或恒高直流信号，所述信号屏蔽层在靠近所述第二边界的一侧具有与所述外围源漏金属走线重叠的第二重叠区域，且所述第二重叠区域通过第二过孔与所述外围源漏金属走线电连接。
  28. 根据权利要27所述的显示面板，其特征在于，所述显示单元还包括第一源漏金属层，所述第一源漏金属层包括薄膜晶体管的源极和漏极图案，其中所述外围源漏金属走线与所述第一源漏金属层同层且同材质设置。
  29. 根据权利要求28所述的显示面板，其特征在于，所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个自容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为金属网格层，至少另一个所述触控电极层为桥接金属层，所述金属网格层与所述桥接金属层通过所述绝缘层上的过孔连接，以形成自容式触控电极；或者
    所述触控功能层为柔性多层屏上触控结构，所述触控图案包括阵列分布的多个互容式触控电极，所述触控功能层的膜层结构包括至少两个触控电极层、及设于所述至少两个触控电极层之间的绝缘层，至少一个所述触控电极层为发射电极层，至少另一个所述触控电极层为感应电极层，所述发射电极层与所述感应电极层之间通过所述绝缘层隔开，以形成互容式触控电极；或者
    所述触控功能层为柔性单层屏上触控结构，所述触控功能层的膜层结构包括一触控电极层，所述触控电极层上的触控图案包括阵列分布的多个触控电极及连接至所述多个触控电极上的触控信号线。
  30. 一种显示装置，包括如权利要求1至14任一项所述的显示面板，和/或包括如权利要求15至29任一项所述的显示面板。
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CN113672129A (zh) * 2021-07-29 2021-11-19 昆山国显光电有限公司 显示面板和显示装置
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CN114725176A (zh) * 2022-04-11 2022-07-08 京东方科技集团股份有限公司 显示面板及其制作方法、以及显示装置

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CN113296624A (zh) * 2020-02-21 2021-08-24 华为技术有限公司 一种显示面板和电子设备
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