WO2024042864A1 - Imaging device - Google Patents

Imaging device Download PDF

Info

Publication number
WO2024042864A1
WO2024042864A1 PCT/JP2023/024442 JP2023024442W WO2024042864A1 WO 2024042864 A1 WO2024042864 A1 WO 2024042864A1 JP 2023024442 W JP2023024442 W JP 2023024442W WO 2024042864 A1 WO2024042864 A1 WO 2024042864A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
column
transistor
signal line
imaging device
Prior art date
Application number
PCT/JP2023/024442
Other languages
French (fr)
Japanese (ja)
Inventor
守 佐藤
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニーセミコンダクタソリューションズ株式会社 filed Critical ソニーセミコンダクタソリューションズ株式会社
Publication of WO2024042864A1 publication Critical patent/WO2024042864A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present technology relates to an imaging device. Specifically, the present technology relates to an imaging device provided with a binning function.
  • an imaging device For surveillance cameras and cameras mounted on mobile terminals, there is a technology that allows them to operate constantly for purposes such as detecting moving objects, and reduces power consumption by lowering the spatial resolution using analog binning.
  • an imaging device for example, an imaging device has been proposed that holds one pixel signal in each of a plurality of signal holding sections and averages and outputs the pixel signals held in the plurality of signal holding sections (for example, , see Patent Document 1).
  • the first switch circuit selectively connects the pixel to each of the plurality of signal holding sections to hold one pixel signal in each of the plurality of signal holding sections, and the second switch circuit , averages and outputs pixel signals held in a plurality of signal holding units. Therefore, in the above-mentioned conventional technology, the number of switches connected to the signal line that transmits signals read from pixels in the column direction increases, which may lead to an increase in the area occupied by the switches.
  • This technology was created in view of this situation, and enables binning while suppressing the increase in the number of switches connected to the signal line that transmits signals read from pixels in the column direction.
  • the purpose is to
  • the present technology was developed to solve the above-mentioned problems, and its first aspect is that it includes a pixel array section in which pixels are arranged in a matrix in the row direction and column direction, and a pixel array section in which pixels are read out from the pixels.
  • a signal line that transmits the signal transmitted in the column direction a sample hold switch that samples and holds the signal transmitted via the signal line for each column, and a signal line that connects the signal lines of different columns to which the signal is sampled and held.
  • This is an imaging device equipped with a connection switch. This brings about the effect that binning is performed after the signals transmitted via the signal line are sampled and held for each column.
  • an AD converter that AD converts a signal transmitted via the signal line for each column, and one of the AD converters for each column connected via the connection switch.
  • the device may further include an active control unit that activates one AD conversion unit. This brings about the effect that the power consumption of the AD converter, which does not need to operate during binning processing, can be reduced in power consumption.
  • the AD conversion section may include a comparator that compares the potential of the signal line and a ramp signal, and a counter that performs a counting operation based on the comparison result of the comparator. This brings about the effect that the signal transmitted via the signal line is digitized.
  • the active control section may control the AD conversion section separately into an activated column and a deactivated column. This brings about the effect that the AD converter of at least one column among the plurality of columns is deactivated during binning.
  • the device may further include a first DC cut capacitor connected to the first input terminal of the comparator, and a second DC cut capacitor connected to the second input terminal of the comparator. This brings about the effect that the DC-cut signal is input to the comparator.
  • the active control unit connects a connection destination of a second capacitance electrode of the first DC cut capacitor whose first capacitance electrode is connected to the signal line to a first input terminal of the comparator and ground. You may further include a changeover switch for switching between. This brings about the effect that the capacitance of the first DC cut capacitor in one column is added to the signal line in another column.
  • the active control unit may control the changeover switch separately for activated columns and deactivated columns. This brings about the effect that the capacitance added to the column to be deactivated is added to the capacitance of the signal line of the column to be activated.
  • the device may further include an amplifier that amplifies the signal transmitted via the signal line for each column and inputs the amplified signal to the AD conversion section. This brings about the effect that the signal input to the AD conversion section is increased.
  • the active control section may control the amplifiers separately into activated columns and deactivated columns. This brings about the effect that the amplifier of at least one column among the plurality of columns is deactivated during binning.
  • the sample and hold switch may be a transistor provided for each of the signal lines. This brings about the effect that the signals transmitted via the signal line are sampled and held for each column.
  • the device may further include a driver that drives the transistor from both sides in the row direction. This brings about the effect that the driving force of the transistors in each column is increased based on the two drivers provided in common to the plurality of columns.
  • the device may further include a signal line reset transistor that resets the potential of the signal line, and a signal line reset level generation unit that generates a reset level of the potential of the signal line.
  • the signal line reset level generation section may include a diode-connected transistor. This brings about the effect that the potential of the signal line is raised in accordance with the forward voltage of the diode-connected transistor when the signal line is reset.
  • the capacitance used for sample and hold of the signal may be a parasitic capacitance of the signal line. This brings about the effect that capacitive load reading can be performed without adding a capacitive element to the signal line.
  • connection switch may be connected in series to a capacitor for each column used for sample and hold of the signal. This brings about the effect of making binning possible while making the number of columns to be binned variable.
  • connection switch may be connected in parallel to a capacitor for each column used for sample-holding the signal. This brings about the effect that binning can be performed while fixing the number of columns to be binned.
  • the invention further includes a constant current transistor that is electrically connectable to the signal line and that flows a constant current based on a source follower formed between the pixel and the constant current readout.
  • the constant current transistor may be turned on, and in capacitive load reading, the constant current transistor may be turned off. This brings about the effect that capacitive load readout and constant current readout can be switched.
  • the pixel includes a photodiode, a transfer transistor that transfers the charge accumulated in the photodiode to the floating diffusion, a reset transistor that resets the floating diffusion, and a potential of the floating diffusion.
  • the device may include an amplification transistor that outputs a corresponding signal, and a selection transistor connected between the amplification transistor and the signal line. This brings about the effect that a source follower is formed between the pixel and the pixel when a signal is read from the pixel.
  • the sample and hold switch may be the selection transistor. This brings about the effect that the signals transmitted via the signal line are sampled and held for each column.
  • a binning transistor may be further provided to connect floating diffusions in different rows. This brings about the effect that it is possible to binning mutually different rows.
  • FIG. 1 is a block diagram illustrating a configuration example of a camera to which the imaging device according to the first embodiment is applied.
  • 1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment.
  • FIG. 2 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing a configuration example of a pixel array section provided in the solid-state imaging device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a modification of the pixel array section provided in the solid-state imaging device according to the first embodiment.
  • FIG. 3 is a diagram showing a configuration example of a signal readout circuit for four columns according to the first embodiment.
  • FIG. 3 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the first embodiment.
  • FIG. 3 is a diagram illustrating a configuration example of a comparator applied to the signal readout circuit according to the first embodiment.
  • FIG. 7 is a diagram showing a configuration example of a signal readout circuit for four columns according to a second embodiment.
  • FIG. 7 is a diagram showing a configuration example of a signal readout circuit for four columns according to a third embodiment.
  • FIG. 7 is a diagram showing an example of the configuration of a signal readout circuit for two columns according to a fourth embodiment.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to a fifth embodiment.
  • FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for four columns according to a sixth embodiment.
  • FIG. 12 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the sixth embodiment.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to a seventh embodiment.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to an eighth embodiment.
  • FIG. 12 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the eighth embodiment.
  • FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for one column according to a ninth embodiment.
  • FIG. 12 is a perspective view showing a configuration example of an imaging device according to a tenth embodiment.
  • FIG. 1 is a block diagram showing a schematic configuration example of a vehicle control system.
  • FIG. 3 is an explanatory diagram showing an example of an installation position of an imaging unit.
  • First embodiment an example of binning based on signals sampled and held for each column in which a signal line reset transistor is connected to a vertical signal line
  • Second embodiment an example of binning based on signals sampled and held for each column in which diode-connected transistors are connected to vertical signal lines via signal line reset transistors
  • Third Embodiment (Binning is performed based on the signal sampled and held for each column in which the signal line reset transistor is connected to the vertical signal line, and connection switches are connected in parallel to the capacitance of each column used for sample and hold. Example of connection) 4.
  • Fourth embodiment (an example of binning in the row direction and column direction based on a signal sampled and held for each column in which a signal line reset transistor is connected to a vertical signal line) 5.
  • Fifth embodiment (example where each column is provided with an amplifier that amplifies the signal input to the AD conversion section) 6.
  • Sixth embodiment (example in which a driver is provided to drive a sample hold switch provided for each signal line from both sides in the row direction) 7.
  • Seventh embodiment (example of switching connection destination of DC cut capacitor between comparator input and ground) 8.
  • Eighth embodiment (example of binning based on signals sampled and held for each column in which constant current transistors are connected to vertical signal lines) 9.
  • Ninth embodiment (example in which a constant current transistor is connected in parallel to a series circuit of a signal line reset transistor and a diode-connected transistor) 10.
  • Tenth embodiment (example in which substrates on which a solid-state imaging device is formed are laminated) 11.
  • FIG. 1 is a block diagram showing a configuration example of a camera to which an imaging device according to a first embodiment is applied.
  • a camera 100 includes an optical system 101, a solid-state imaging device 102, an imaging control section 103, an image processing section 104, a storage section 105, a display section 106, and an operation section 107.
  • the imaging control section 103, the image processing section 104, the storage section 105, the display section 106, and the operation section 107 are connected to each other via a bus 108.
  • the camera 100 may be used alone, or may be incorporated into a mobile terminal such as a smartphone, or may be incorporated into an authentication device or a monitoring device.
  • the optical system 101 makes light from a subject enter the solid-state imaging device 102 and forms an image of the subject on the light-receiving surface of the solid-state imaging device 102.
  • the optical system 101 can include, for example, a focus lens, a zoom lens, an aperture, and the like.
  • Optical system 101 may include multiple lenses such as a wide-angle lens, a standard lens, and a telephoto lens.
  • the solid-state imaging device 102 converts light from a subject into an electrical signal for each pixel, digitizes the electrical signal, and outputs the digital signal.
  • the solid-state imaging device 102 may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device).
  • CMOS Complementary Metal Oxide Semiconductor
  • CCD Charge Coupled Device
  • the imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.
  • the image processing unit 104 performs image processing based on the output from the solid-state imaging device 102.
  • Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing.
  • the image processing unit 104 may include a processor that executes processing based on software.
  • the storage unit 105 stores captured images captured by the solid-state imaging device 102, and stores imaging parameters of the solid-state imaging device 102. Furthermore, the storage unit 105 can store a program for operating the camera 100 based on software.
  • the storage unit 105 may include a ROM (Read Only Memory), a RAM (Random Access Memory), and a memory card.
  • the display unit 106 displays captured images and various information that supports imaging operations.
  • the display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.
  • the operation unit 107 provides a user interface for operating the camera 100.
  • the operation unit 107 may include, for example, buttons, dials, and switches provided on the camera 100.
  • the operation unit 107 may be configured with a touch panel together with the display unit 106.
  • FIG. 2 is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment.
  • the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, a control circuit 116, drivers 117 and 118, and an active control section 119. Be prepared.
  • the pixel array section 111 includes a plurality of pixels 120.
  • the pixels 120 are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction).
  • Each pixel 120 can form a source follower with the column readout circuit 113 during signal readout.
  • Each pixel 120 is connected to a horizontal drive line 131 for each row and to a vertical signal line 132 for each column.
  • the horizontal drive line 131 drives each pixel 120 row by row when reading signals from each pixel 120.
  • the vertical signal line 132 transmits to the column signal processing unit 114 for each column a potential based on accumulated charges according to a current flowing when reading a signal from the pixel 120. Note that the vertical signal line 132 is an example of a signal line described in the claims.
  • the vertical scanning circuit 112 scans the pixels 120 to be read in the column direction.
  • the vertical scanning circuit 112 may be configured using vertical registers.
  • the column readout circuit 113 can form a source follower with each pixel 120 when reading signals from each pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120. Column readout circuit 113 can support capacitive load readout. The column readout circuit 113 may also support constant current readout.
  • the column readout circuit 113 also includes a sample and hold switch that samples and holds signals transmitted via the vertical signal line 132 for each column, and a connection switch that connects the vertical signal lines 132 of different columns on which signals are sampled and held. Equipped with. At this time, the column readout circuit 113 can sample and hold the signal transmitted via the vertical signal line 132 for each column, perform binning, and output the signal to the column signal processing section 114.
  • Each driver 117 and 118 drives a sample hold switch provided in the column readout circuit 113 from both sides in the row direction.
  • Each driver 117 and 118 can be shared by sample and hold switches provided for each column.
  • Each driver 117 and 118 may be placed on either side of column readout circuit 113.
  • the column signal processing unit 114 processes signals transmitted from each pixel 120 in the column direction. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on signals transmitted from each pixel 120 in the column direction. Further, the column signal processing unit 114 can perform AD (Analog to Digital) conversion processing based on the signals transmitted from each pixel 120 in the column direction, and output the image pickup signal Gout. At this time, the column signal processing section 114 can include an AD conversion section for each column that performs AD conversion on the signal transmitted via the vertical signal line 132.
  • CDS correlated double sampling
  • AD Analog to Digital
  • the active control unit 119 activates one AD conversion unit among the AD conversion units of each column connected via the connection switch. At this time, the active control section 119 can output a control signal CTL to each AD conversion section to control the activation timing of each AD conversion section during binning.
  • the active control unit 119 may control the AD conversion unit separately for activated columns and deactivated columns. At this time, the active control unit 119 can activate the AD conversion unit of the column to be activated and put the AD conversion unit of the column to be deactivated into a standby state.
  • the horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction.
  • the horizontal scanning circuit 115 may be configured using a horizontal register.
  • the control circuit 116 controls the vertical scanning circuit 112, column readout circuit 113, column signal processing section 114, horizontal scanning circuit 115, and drivers 117 and 118.
  • the control circuit 116 can control the scan timing in the column direction, the scan timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing section 114. Further, the control circuit 116 can control the drive timing of each driver 117 and 118 and the operation timing of the active control section 119.
  • a sample and hold switch is provided in the column readout circuit 113 in order to perform binning based on a signal sampled and held for each column.
  • a selection transistor provided in the pixel 120 may be used to sample and hold the signal read out from the pixel 120 for each column.
  • the sample and hold switch provided in the column readout circuit 113 is not required.
  • drivers 117 and 118 on both sides of column readout circuit 113 are also unnecessary.
  • binning readout it is also possible to switch between binning readout and all-pixel individual readout.
  • binning processing may be operated constantly, or when an application such as still image shooting is started, all pixels are individually read out. You may switch to
  • FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.
  • a pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion 126.
  • MOS Metal Oxide Semiconductor
  • the amplification transistor 124 and the selection transistor 125 are connected in series.
  • a cathode of the photodiode 121 is connected to a floating diffusion 126 via a transfer transistor 122.
  • the floating diffusion 126 is connected to the power supply Vdd via the reset transistor 123.
  • the power supply Vdd is connected to the vertical signal line 132 via a series circuit of an amplification transistor 124 and a selection transistor 125.
  • the gate of amplification transistor 124 is connected to floating diffusion 126 .
  • a transfer signal ⁇ TG is applied to the gate of the transfer transistor 122.
  • a pixel reset signal ⁇ PRT is applied to the gate of the reset transistor 123.
  • a selection signal ⁇ SEL is applied to the gate of the selection transistor 125.
  • the transfer signal ⁇ TG, pixel reset signal ⁇ PRT, and selection signal ⁇ SEL can be transmitted to each pixel 120 via the horizontal drive line 131 in FIG.
  • the transfer transistor 122 When the transfer transistor 122 is turned on, the charges accumulated in the photodiode 121 are transferred to the floating diffusion 126. Then, when the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion 126. The source potential of the amplification transistor 124 is applied to the vertical signal line 132 via the selection transistor 125 and transmitted via the vertical signal line 132. Furthermore, when the reset transistor 123 is turned on, the charges accumulated in the floating diffusion 126 are discharged.
  • FIG. 4 is a cross-sectional view showing an example of the configuration of a pixel array section provided in the solid-state imaging device according to the first embodiment. Note that FIG. 4 shows an example of a front-illuminated solid-state imaging device. Further, FIG. 4 shows a configuration example for three pixels.
  • a photodiode 232 is formed on a semiconductor substrate 231 for each pixel 120.
  • the material of the semiconductor substrate 231 may be Si, InGaAs, or InP.
  • a gate electrode 214 and a wiring layer 210 are formed on the semiconductor substrate 231.
  • Gate electrode 214 is formed on semiconductor substrate 231 with gate insulating film 213 interposed therebetween.
  • a sidewall 215 is formed on the sidewall of the gate electrode 214 .
  • the material of the gate electrode 214 for example, polycrystalline silicon into which impurities are introduced can be used.
  • the material of the gate insulating film 213, for example, a silicon oxide film can be used.
  • the gate electrode 214 can be used for a pixel transistor.
  • the pixel transistors include the transfer transistor 122, reset transistor 123, amplification transistor 124, and selection transistor 125 in FIG.
  • a wiring 216 is formed on the gate electrode 214.
  • FIG. 4 shows an example of three-layer wiring.
  • the wiring 216 is provided with an opening OP1 that allows light to enter the photodiode 232.
  • Gate electrode 214 and wiring 216 are insulated via insulating layer 217.
  • insulating layer 217 For example, a silicon oxide film can be used as the insulating layer 217.
  • metal such as Al or Cu can be used as the material of the wiring 216.
  • a color filter 218 is formed on the wiring layer 210 for each pixel 120.
  • a microlens 219 is formed on the color filter 218 for each pixel 120.
  • transparent resin such as acrylic or polycarbonate can be used.
  • a pigment may be added to the color filter 218 for coloring.
  • the color filter 218 can have a Bayer array, for example.
  • FIG. 5 is a cross-sectional view showing a modification of the pixel array section provided in the solid-state imaging device according to the first embodiment. Note that FIG. 5 shows an example of a back-illuminated solid-state imaging device. Further, FIG. 5 shows a configuration example for three pixels.
  • a photodiode 222 is formed in a semiconductor layer 221 for each pixel 120.
  • the material of the semiconductor layer 221 may be Si, InGaAs, or InP.
  • the semiconductor layer 221 can be formed, for example, by thinning a semiconductor substrate on which the photodiode 222 is formed from the back side.
  • a gate electrode 224 and a wiring layer 220 are formed on the semiconductor layer 221.
  • Gate electrode 224 is formed on semiconductor layer 221 with gate insulating film 223 interposed therebetween.
  • a sidewall 225 is formed on the sidewall of the gate electrode 224 .
  • the gate electrode 224 can be used for a pixel transistor.
  • the pixel transistors include the transfer transistor 122, reset transistor 123, amplification transistor 124, and selection transistor 125 in FIG.
  • a wiring 226 is formed on the gate electrode 224.
  • FIG. 5 shows an example of three-layer wiring. Gate electrode 224 and wiring 226 are insulated via insulating layer 227.
  • the semiconductor layer 221 is supported on a support substrate 230 with an insulating layer 227 interposed therebetween.
  • the support substrate 230 may be a glass substrate, a Si substrate, or a sapphire substrate.
  • a color filter 228 is formed for each pixel 120 on the back side of the semiconductor layer 221.
  • a microlens 229 is formed on the color filter 228 for each pixel 120.
  • the color filter 228 can have a Bayer array, for example.
  • FIG. 6 is a diagram showing a configuration example of a signal readout circuit for four columns according to the first embodiment.
  • pixels 120 are connected to each vertical signal line 132-1 to 132-4, respectively.
  • the amplification transistor 124 of each pixel 120 is connected to each vertical signal line 132-1 to 132-4 via a selection transistor 125, respectively.
  • a capacitor 133 is added to each vertical signal line 132-1 to 132-4.
  • This capacitor 133 can be used to sample and hold signals read out from each pixel 120 for each column.
  • This capacitance 133 may be a parasitic capacitance of each vertical signal line 132-1 to 132-4, or a capacitive element connected to each vertical signal line 132-1 to 132-4.
  • the selection transistor 125 of each pixel 120 can be used as a sample and hold switch that causes the capacitor 133 to sample and hold the signals transmitted via the vertical signal lines 132-1 to 132-4 for each column.
  • a signal line reset transistor 141 is electrically connected to each vertical signal line 132-1 to 132-4.
  • the signal line reset transistor 141 can reset the potentials VSL1 to VSL4 of the respective vertical signal lines 132-1 to 132-4.
  • a MOS transistor can be used for each signal line reset transistor 141.
  • a signal line reset signal ⁇ RT is applied to the gate of each signal line reset transistor 141.
  • the source of each signal line reset transistor 141 is connected to reset potential VR.
  • the reset potential VR may be set to a higher potential than the ground potential.
  • the signal readout circuit is provided with an AD conversion section that performs AD conversion for each column of the signals transmitted via each vertical signal line 132-1 to 132-4.
  • the AD converter is provided with a comparator 143 and a counter 146 for each column.
  • Each comparator 143 compares the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 with the reference signal RAP for each column.
  • the reference signal RAP may be a ramp signal.
  • Each counter 146 performs a counting operation for each column based on the comparison result of each comparator 143.
  • Each vertical signal line 132-1 to 132-4 is connected to an inverting input of a comparator 143 via each DC cut capacitor 144.
  • potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are applied to the inverting input of each comparator 143 via a DC cut capacitor 144, respectively. be done.
  • the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is applied to the inverting input of each comparator 143 via the DC cut capacitor 144, respectively. be done.
  • a reference signal RAP is input to a non-inverting input of each comparator 143 via a DC cut capacitor 145, respectively.
  • an auto-zero signal AZ is input to each comparator 143.
  • the autozero signal AZ activates autozero operation during the autozero period.
  • the charge accumulated in each DC cut capacitor 144 and 145 can be controlled so that the non-inverting input and the inverting input of comparator 143 are balanced.
  • connection switch 151 is provided in the signal readout circuit.
  • Connection switch 151 connects vertical signal lines 132-1 to 132-4 in different columns. At this time, the connection switch 151 is connected in series to the capacitor 133 for each column used for sampling and holding the signal read out from each pixel 120.
  • Each connection switch 151 can be provided between vertical signal lines 132-1 to 132-4 adjacent to each other in the row direction. Each connection switch 151 can be turned on/off based on open/close signals ⁇ Cn1 to ⁇ Cn4, respectively.
  • the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned on, so that each vertical signal line 132-1 to 132 -4 potentials VSL1 to VSL4 are set to potentials higher than 0V. Then, after the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned off, the selection transistor 125 of each pixel 120 is turned on, so that a signal is read out from each pixel 120. . At this time, charges corresponding to the signals read from each pixel 120 are accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4, respectively. Then, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 change based on the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4, respectively.
  • each comparator 143 connected to each vertical signal line 132-1 to 132-4, the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are compared with the reference signal RAP, and each comparison result COP1 COP4 is output from.
  • each comparator 143 can output the timing when the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 match the level of the reference signal RAP to each counter 146 as comparison results COP1 to COP4. .
  • Each counter 146 performs a counting operation based on the comparison results COP1 to COP4 of each comparator 143, and outputs a count value based on each counting operation.
  • the active control unit 119 in FIG. 2 activates one of the comparator 143 and the counter 146 that perform AD conversion for each of the vertical signal lines 132-1 to 132-4.
  • the active control unit 119 controls the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 among the comparators 143 and counter 146 provided corresponding to the vertical signal lines 132-1 to 132-4. 146 may be activated.
  • the active control unit 119 can set the control signal CTL of the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 to ACT.
  • the active control unit 119 can set the control signal CTL of the comparator 143 and counter 146 provided corresponding to each vertical signal line 132-2 to 132-4 to STB.
  • ACT can instruct activation
  • STB can instruct standby.
  • the comparator 143 connected to the vertical signal line 132-1 determines the timing at which the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 matches the level of the reference signal RAP as a comparison result COP1. It can be output to the counter 146 as follows. The counter 146 performs a counting operation based on the comparison result COP1 of the comparator 143, and outputs a count value based on the counting operation.
  • FIG. 7 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the first embodiment.
  • an example of the waveform of each part at the time of binning read-out is shown.
  • the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 and their average value are indicated by VSL.
  • pixel reset/VSL reset is performed in capacitive load readout (K11).
  • the pixel reset signal ⁇ PRT of each pixel 120 rises (t11)
  • the reset transistor 123 of each pixel 120 is turned on
  • the floating diffusion 126 of each pixel 120 is reset.
  • the reset level of the floating diffusion 126 of each pixel 120 can be set to the power supply potential Vdd.
  • the signal line reset signal ⁇ RT rises (t11), and the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned on, and each vertical signal line 132-1 to 132-4 is turned on. will be reset.
  • the reset level of each vertical signal line 132-1 to 132-4 is set to the reset potential VR via the signal line reset transistor 141 connected to each vertical signal line 132-1 to 132-4. .
  • the open/close signal ⁇ Cn* rises (t11), and a plurality of connection switches 151 among the connection switches 151 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the open/close signal ⁇ Cn* indicates a plurality of open/close signals selected from among the open/close signals ⁇ Cn1 to ⁇ Cn4.
  • the opening/closing signal ⁇ Cn* is one of the opening/closing signals ⁇ Cn1 to ⁇ Cn4.
  • the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are equalized.
  • the auto zero signal AZ rises (t11), and the auto zero operation of the comparator 143 connected to each vertical signal line 132-1 to 132-4 is activated. At this time, the charge accumulated in each DC cut capacitor 144 and 145 is controlled so that the non-inverting input and the inverting input of comparator 143 connected to each vertical signal line 132-1 to 132-4 are balanced. Then, the pixel reset signal ⁇ PRT falls, the open/close signal ⁇ Cn* falls, and the signal line reset signal ⁇ RT falls.
  • P-phase VSL settling/P-phase VSL sample hold is performed (K12).
  • the selection signal ⁇ SEL of each pixel 120 rises (t12), and the selection transistor 125 of each pixel 120 is turned on.
  • charges corresponding to the reset level of the floating diffusion 126 of each pixel 120 are applied to the capacitors 133 added to the vertical signal lines 132-1 to 132-4, respectively.
  • the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4.
  • P-phase binning/P-phase AD is performed (K13).
  • the selection signal ⁇ SEL of each pixel 120 falls (t13)
  • the open/close signal ⁇ Cn* rises and the auto-zero signal AZ falls.
  • the connection switches 151 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. .
  • the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143.
  • the comparators 143 and counters 146 provided corresponding to the vertical signal lines 132-1 to 132-4 only the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 are active. be converted into Further, the activated comparator 143 is supplied with a ramp signal as the reference signal RAP. Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the reset level is compared with the reference signal RAP.
  • the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1.
  • the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the reset levels read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted.
  • transfer/VSL reset is performed (K14).
  • the transfer signal ⁇ TG of each pixel 120 rises (t14)
  • the transfer transistor 122 of each pixel 120 is turned on, and the charge accumulated in the photodiode 121 of each pixel 120 is transferred to the floating diffusion 126 of each pixel 120.
  • Ru the signal line reset signal ⁇ RT rises (t14)
  • the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned on, and each vertical signal line 132-1 to 132-4 is turned on. will be reset.
  • the reset level of each vertical signal line 132-1 to 132-4 is set to the reset potential VR via the signal line reset transistor 141 connected to each vertical signal line 132-1 to 132-4.
  • the transfer signal ⁇ TG falls, the open/close signal ⁇ Cn* falls, and the signal line reset signal ⁇ RT falls (t15).
  • D-phase VSL settling/D-phase VSL sample and hold is performed (K15).
  • the selection signal ⁇ SEL rises (t16), and the selection transistor 125 of each pixel 120 is turned on.
  • a charge corresponding to the signal level of the floating diffusion 126 of each pixel 120 is applied to the capacitor 133 added to each vertical signal line 132-1 to 132-4.
  • the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4.
  • D-phase binning/D-phase AD is performed (K16).
  • the opening/closing signal ⁇ Cn* rises.
  • the connection switches 151 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. .
  • the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143.
  • the activated comparator 143 is supplied with a ramp signal as the reference signal RAP. Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the signal level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1. At this time, the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the signal level read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted.
  • FIG. 8 is a diagram showing a configuration example of a comparator applied to the signal readout circuit according to the first embodiment.
  • the comparator 143 includes a differential amplifier 501, a post-stage amplifier 502, an output circuit 503, and an AND circuit 504.
  • the rear stage amplifier 502 is connected to the rear stage of the differential amplifier 501, and the output circuit 503 is connected to the rear stage of the rear stage amplifier 502.
  • the AND circuit 504 is connected after the output circuit 503, and the counter 146 is connected after the AND circuit 504.
  • the differential amplifier 501 balances the comparator inputs CIN1 and CIN2 based on the auto-zero operation, and then outputs a voltage according to the difference between the comparator inputs CIN1 and CIN2.
  • Differential amplifier 501 includes PMOS transistors 511, 521, 551, 561, and 591, and NMOS transistors 531, 541, 571, and 581.
  • the PMOS transistor 511 and the NMOS transistor 531 are connected in series with each other.
  • PMOS transistor 521 and NMOS transistor 541 are connected in series with each other.
  • the sources of each PMOS transistor 511 and 521 are connected to power supply voltage VDDH, and the gate of each PMOS transistor 511 and 521 is connected to the drain of PMOS transistor 521. At this time, PMOS transistors 511 and 521 can constitute a current mirror.
  • PMOS transistor 591 is connected in parallel to PMOS transistor 511.
  • a PMOS transistor 551 is connected between the gate and drain of the NMOS transistor 531, and a PMOS transistor 561 is connected between the gate and drain of the NMOS transistor 541.
  • NMOS transistors 571 and 581 are connected in series with each other. The sources of each NMOS transistor 531 and 541 are grounded through a series circuit of NMOS transistors 571 and 581.
  • An auto-zero signal AZP is applied to the gate of each PMOS transistor 551 and 561, and a bias voltage BIAS is applied to the gate of the NMOS transistor 571.
  • NMOS transistor 571 can operate as a constant current source based on bias voltage BIAS.
  • a control signal XA is applied to the gate of the NMOS transistor 581.
  • a control signal XB is applied to the gate of the PMOS transistor 591.
  • Post-stage amplifier 502 amplifies the output of the differential amplifier 501.
  • Post-stage amplifier 502 includes a PMOS transistor 512, an NMOS transistor 522, and a switch 532.
  • the PMOS transistor 512 and the NMOS transistor 522 are connected in series with each other.
  • the source of PMOS transistor 512 is connected to power supply voltage VDDH, and the gate of PMOS transistor 512 is connected to the drain of PMOS transistor 511.
  • a switch 532 is connected between the gate and drain of the NMOS transistor 522, and the source of the NMOS transistor 522 is grounded. Switch 532 opens and closes based on auto-zero signal AZN.
  • the output circuit 503 converts the output of the subsequent stage amplifier 502 into a logical value '0' or a logical value '1'.
  • Output circuit 503 includes PMOS transistors 513 and 543 and NMOS transistors 523 and 533.
  • PMOS transistor 513 and NMOS transistor 523 are connected in series with each other, and NMOS transistors 523 and 533 are connected in series with each other.
  • the sources of PMOS transistors 513 and 543 are connected to power supply voltage VDDL, and the source of NMOS transistor 533 is grounded.
  • the drain of PMOS transistor 543 is connected to the drain of PMOS transistor 513.
  • Power supply voltage VDDL can be lower than power supply voltage VDDH.
  • the gate of the PMOS transistor 543 and the gate of the NMOS transistor 523 are connected to the drain of the PMOS transistor 512.
  • a control signal XC is applied to the gate of the PMOS transistor 513 and the gate of the NMOS transistor 533.
  • a first input terminal of the AND circuit 504 is connected to the drain of the PMOS transistor 513.
  • a control signal XD is applied to a second input terminal of the AND circuit 504.
  • Control signals XA, XB, XC, and XD are input to comparator 143 as control signal CTL in FIG.
  • control signals XA, XB, XC, and XD are set to low level.
  • NMOS transistors 533 and 581 are turned off, PMOS transistors 512 and 513 are turned on, and AND circuit 504 outputs a logic value of '0'.
  • control signals XA, XB, XC, and XD are set to high level.
  • NMOS transistors 533 and 581 are turned on, PMOS transistors 512 and 513 are turned off, and AND circuit 504 outputs a logical value '0' or '1' depending on the output from output circuit 503.
  • each PMOS transistor 551 and 561 is turned on based on the auto-zero signal AZP, and the switch 532 is closed based on the auto-zero signal AZN. Note that the timing at which each PMOS transistor 551 and 561 turns off after being turned on can be made later than the timing at which the switch 532 opens after closing. At this time, current flows through each PMOS transistor 551 and 561 based on the current mirror operation of PMOS transistors 511 and 521. Then, charges are accumulated in each of the DC cut capacitors 144 and 145 so that the non-inverting input and the inverting input of the comparator 143 are balanced.
  • the signal line reset transistor 141 performs binning based on the sampled and held signals for each column connected to each vertical signal line 132-1 to 132-4. This makes it possible to perform binning in the column direction while suppressing an increase in the area of the signal readout circuit, and to ensure linearity during binning without limiting the number of binnings.
  • AD converters that do not need to operate during binning processing can be set to a standby state, reducing power consumption. It is possible to aim for
  • the signal line reset transistor 141 performs binning based on signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4.
  • diode-connected transistors perform binning based on signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4 via a signal line reset transistor 141.
  • FIG. 9 is a diagram showing a configuration example of a signal readout circuit for four columns according to the second embodiment.
  • this signal readout circuit has a diode-connected transistor 142 added to the signal readout circuit of the first embodiment described above.
  • the other configuration of the signal readout circuit of the second embodiment is the same as that of the signal readout circuit of the first embodiment described above.
  • a diode-connected transistor 142 is connected in series to a signal line reset transistor 141 for each vertical signal line 132-1 to 132-4.
  • a MOS transistor can be used as the diode-connected transistor 142.
  • the gate of diode-connected transistor 142 is connected to the drain of diode-connected transistor 142.
  • the source of diode-connected transistor 142 is grounded.
  • the source of diode-connected transistor 142 may be connected to a potential higher than ground potential.
  • the diode-connected transistor 142 generates a voltage higher than 0V (for example, 0.5V), and changes the potential VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 to a potential higher than 0V via the signal line reset transistor 141.
  • the diode-connected transistor 142 is an example of a signal line reset level generation section described in the claims.
  • the operation of the signal readout circuit of the second embodiment during binning is similar to the operation of the signal readout circuit of the first embodiment during binning.
  • the diode-connected transistor 142 generates a signal sampled and held for each column connected to each vertical signal line 132-1 to 132-4 via the signal line reset transistor 141. Binning based on Thereby, the potential of each of the vertical signal lines 132-1 to 132-4 can be raised according to the forward voltage of the diode-connected transistor 142 when each of the vertical signal lines 132-1 to 132-4 is reset. Therefore, the potential of each vertical signal line 132-1 to 132-4 at the start of P-phase VSL settling can be made higher than 0V, and the settling time can be shortened.
  • connection switch 151 is connected in series with the capacitor 133 for each column used for sample and holding.
  • connection switches are connected in parallel to the capacitors for each column used for sample and holding.
  • FIG. 10 is a diagram showing a configuration example of a signal readout circuit for four columns according to the third embodiment.
  • this signal readout circuit includes a connection switch 152 in place of the connection switch 151 of the signal readout circuit of the first embodiment described above.
  • the other configuration of the signal readout circuit of the third embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • connection switch 152 connects the vertical signal lines 132-1 to 132-4 in different columns. At this time, the connection switch 152 is connected in parallel to the capacitor 133 for each column used for sampling and holding the signal read out from each pixel 120. Each connection switch 152 can be turned on/off based on the opening/closing signal ⁇ Cn. When using the connection switch 152, the number of binning in the column direction is fixed.
  • the operation of the signal readout circuit of the third embodiment during binning is similar to the operation of the signal readout circuit of the first embodiment during binning, except that the number of binnings in the column direction is fixed. be.
  • the signal line reset transistor 141 performs binning based on the signal sampled and held for each column connected to each vertical signal line 132-1 to 132-4. This makes it possible to perform binning in the column direction while suppressing an increase in the area of the signal readout circuit, and to ensure linearity during binning without limiting the number of binnings.
  • Fourth embodiment> In the first embodiment described above, binning is performed in the column direction based on signals sampled and held for each column. In this fourth embodiment, binning is performed in the column direction and row direction based on signals sampled and held for each column.
  • FIG. 11 is a diagram showing a configuration example of a signal readout circuit for two columns according to the fourth embodiment.
  • this signal readout circuit includes a cell 130 in place of the pixel 120 of the signal readout circuit of the first embodiment described above. Further, in this signal readout circuit, a binning line 140 is added to the signal readout circuit of the first embodiment described above.
  • the other configuration of the signal readout circuit of the fourth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the cells 130 are arranged in a matrix in the row and column directions. Cells 130 are connected to vertical signal lines 132-1 and 132-2 for each column.
  • the cell 130 includes photodiodes 121-1 to 121-4, transfer transistors 122-1 to 122-4, and a binning transistor 127 in place of the photodiode 121 and transfer transistor 122 of the first embodiment described above.
  • the other configuration of the cell 130 of the fourth embodiment is similar to the configuration of the pixel 120 of the first embodiment described above.
  • Each photodiode 121-1 to 121-4 can be arranged in two rows and two columns. Each of the photodiodes 121-1 to 121-4 is connected to the floating diffusion 126 via transfer transistors 122-1 to 122-4, respectively. Transfer signals ⁇ TG1 to ⁇ TG4 are applied to the gates of each of the transfer transistors 122-1 to 122-4. By controlling the application timing of these transfer signals ⁇ TG1 to ⁇ TG4, signals can be read out individually from each photodiode 121-1 to 121-4, or signals can be binned from each photodiode 121-1 to 121-4. You can also read it by The capacitive load readout operation for each photodiode 121-1 to 121-4 is similar to the capacitive load readout operation for the photodiode 121 of the first embodiment described above.
  • the binning transistor 127 is connected between the floating diffusion 126 and the binning line 140 for each cell 130.
  • Binning transistor 127 may be a MOS transistor.
  • a binning signal ⁇ BN is applied to the gate of the binning transistor 127 for each cell 130.
  • the binning signal ⁇ BN is set to low level and the binning transistor 127 of each cell 130 is turned off.
  • the binning signal ⁇ BN is set to a high level and the binning transistor 127 of each cell 130 is turned on.
  • the operation of the signal readout circuit of the fourth embodiment during binning in the row and column directions is similar to that of the signal readout circuit of the first embodiment, except that the binning transistor 127 of each cell 130 is turned on. The operation is similar to that during binning.
  • each photodiode 121-1 to 121-4 are added and averaged for 32 rows by 2 columns, and the signals of the cells 130 for 16 columns are added and averaged by capacitance.
  • the number of columns of the AD converter to be activated can be reduced to 1/16 of the individual readout of all pixels, and power consumption can be reduced.
  • each cell 130 is provided with a binning transistor 127 that connects cells 130 in different rows to each other.
  • binning can be performed not only in the column direction but also in the row direction, and it is possible to increase the number of binning operations while suppressing a decrease in spatial resolution in the row direction.
  • the average value of the signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4 is input to the comparator 143.
  • the average value of signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4 is inputted to a comparator 143 via an amplifier 161.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to the fifth embodiment.
  • this signal readout circuit has an amplifier 161 added to the signal readout circuit of the first embodiment described above.
  • the rest of the configuration of the signal readout circuit of the fifth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the amplifier 161 amplifies the signals transmitted to the comparator 143 via each vertical signal line 132-1 to 132-4 for each column.
  • An amplifier 161 is provided for each vertical signal line 132-1 to 132-4.
  • Each amplifier 161 is connected to an inverting input terminal of each comparator 143 via a DC cut capacitor 144, respectively.
  • a control signal CTL is input to the amplifier 161.
  • the amplifier 161 in the same column as the comparator 143 and the counter 146 can be activated.
  • the amplifier 161 in the same column as these can be set to the standby state.
  • an amplifier 161 is provided for each vertical signal line 132-1 to 132-4, and a control signal CTL is input to each amplifier 161.
  • the signal transmitted to the comparator 143 can be amplified while suppressing an increase in power consumption during binning.
  • the selection transistor 125 is used as a sample and hold switch that samples and holds the signals transmitted via each vertical signal line 132-1 to 132-4 for each column.
  • each vertical signal line 132-1 to 132-4 is provided with a sample hold switch that samples and holds signals transmitted via each vertical signal line 132-1 to 132-4 for each column. establish.
  • FIG. 13 is a diagram showing a configuration example of a signal readout circuit for four columns according to the sixth embodiment.
  • this signal readout circuit has a sample and hold switch 153 and drivers 301 and 302 added to the signal readout circuit of the third embodiment described above.
  • the rest of the configuration of the signal readout circuit of the sixth embodiment is similar to the configuration of the signal readout circuit of the third embodiment described above.
  • the sample and hold switch 153 causes each capacitor 153 to sample and hold the signals transmitted via the vertical signal lines 132-1 to 132-4 for each column.
  • a sample hold switch 153 is provided on each vertical signal line 132-1 to 132-4.
  • Each sample hold switch 153 is turned on/off based on the sample hold signal ⁇ VS.
  • Each sample hold switch 153 may be a MOS transistor.
  • Each driver 301 and 302 drives the sample hold switch 153 from both sides in the row direction.
  • Each driver 301 and 302 can be shared by a sample hold switch 153 provided for each column.
  • FIG. 14 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the sixth embodiment. In addition, in the figure, an example of the waveform of each part at the time of binning readout is shown.
  • the binning read operation of the sixth embodiment is similar to the binning read operation of the first embodiment described above, except that a sample and hold signal ⁇ VS is added.
  • the sample hold signal ⁇ VS rises (t11) at the same time as the pixel reset signal ⁇ PRT rises in the pixel reset/VSL reset (K11). Further, the sample hold signal ⁇ VS falls before the selection signal ⁇ SEL falls in P-phase VSL settling/P-phase VSL sample hold (K12).
  • sample hold signal ⁇ VS rises simultaneously with the rise of the transfer signal ⁇ TG in the transfer/VSL reset (K14) (t14). Further, the sample hold signal ⁇ VS falls before the selection signal ⁇ SEL falls in D-phase VSL settling/D-phase VSL sample hold (K15).
  • the sample and hold switch 153 is provided to sample and hold the signals transmitted via each vertical signal line 132-1 to 132-4 for each column. This makes it possible to perform binning in the column direction while ensuring linearity during binning.
  • drivers 301 and 302 are provided to drive the sample and hold switch 153 from both sides in the row direction. Thereby, the driving force of the sample and hold switches 153 in each column can be increased without providing drivers 301 and 302 for each row to drive the sample and hold switches 153. Therefore, it is possible to reduce the in-plane difference in driving force, it is possible to reduce fixed pattern noise, and it is also possible to suppress an increase in the area required for arranging the drivers 301 and 302.
  • the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are connected to the activated columns and the inactivated columns via the DC cut capacitors 144, respectively. was input to each comparator 143.
  • the connection destination of the DC cut capacitor 144 is switched from the comparator input to the ground.
  • FIG. 15 is a diagram showing a configuration example of a signal readout circuit for four columns according to the seventh embodiment.
  • this signal readout circuit has changeover switches 154 and 155 added to the signal readout circuit of the first embodiment described above.
  • the other configuration of the signal readout circuit of the seventh embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the first capacitive electrode of the DC cut capacitor 144 in each column is connected to each vertical signal line 132-1 to 132-4.
  • Changeover switches 154 and 155 are provided for each column.
  • the changeover switch 154 is connected between the second capacitance electrode of the DC cut capacitor 144 in each column and the inverting input terminal of each comparator 143.
  • the changeover switch 155 is connected between the second capacitance electrode of the DC cut capacitor 144 in each column and the ground.
  • the changeover switch 154 is turned on, and the changeover switch 155 is turned off.
  • the changeover switch 154 is turned off and the changeover switch 155 is turned on. At this time, the changeover switches 154 and 155 are controlled separately for activated columns and deactivated columns.
  • the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 are activated. shall be taken as a thing.
  • the changeover switch 154 connected to the vertical signal line 132-1 is turned on, and the changeover switch 155 is turned off.
  • the changeover switch 154 connected to each vertical signal line 132-2 to 132-4 is turned off, and the changeover switch 155 is turned on.
  • the open/close signals ⁇ Cn1 to ⁇ Cn4 are turned on. Therefore, the capacitance of the DC cut capacitor 144 connected to each vertical signal line 132-2 to 132-4 is added to the capacitance 133 of the vertical signal line 132-1.
  • the connection destination of the DC cut capacitor 144 is switched from the comparator input to the ground.
  • the capacitance added to the vertical signal line 132-1 of the activated column can be increased, and kTC noise can be reduced.
  • FIG. 16 is a diagram showing a configuration example of a signal readout circuit for four columns according to the eighth embodiment.
  • this signal readout circuit includes a current source 401 in place of the signal line reset transistor 141 of the signal readout circuit of the first embodiment described above. Further, this signal readout circuit has a connection switch 402, sample and hold switches 403 and 404, and a capacitor 405 added to the signal readout circuit of the first embodiment described above.
  • the rest of the configuration of the signal readout circuit of the eighth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the current source 401 can be provided for each column. Each current source 401 is connected to vertical signal lines 132-1 to 132-4. Current source 401 may be a MOS transistor.
  • the sample and hold switches 403 and 404 cause the capacitor 405 to sample and hold the signals transmitted via the vertical signal lines 132-1 to 132-4 for each column.
  • Sample and hold switches 403 and 404 are provided on each vertical signal line 132-1 to 132-4. At this time, each sample hold switch 403 is connected in series to the vertical signal lines 132-1 to 132-4, respectively.
  • Each sample hold switch 404 is connected between each vertical signal line 132-1 to 132-4 and a capacitor 405.
  • Each sample hold switch 403 is turned on/off based on the sample hold signal ⁇ VS.
  • Each sample hold switch 404 is turned on/off based on the sample hold signal ⁇ S.
  • Each sample and hold switch 403 and 404 may be a MOS transistor.
  • the capacity 405 can be provided for each column. Each capacitor 405 is connected to each vertical signal line 132-1 to 132-4 via a sample and hold switch 404, respectively. The capacitor 405 can be used to sample and hold signals read out from each pixel 120 for each column.
  • connection switch 402 connects the vertical signal lines 132-1 to 132-4 in different columns. At this time, the connection switch 402 is connected in parallel to the capacitor 405 for each column used to sample and hold the signal read out from each pixel 120. Each connection switch 402 may be a MOS transistor. Each connection switch 402 is turned on/off based on the opening/closing signal ⁇ Cn.
  • FIG. 17 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the eighth embodiment. In addition, in the figure, an example of the waveform of each part at the time of binning read-out is shown.
  • pixel reset is performed in constant current readout (K21).
  • the pixel reset signal ⁇ PRT of each pixel 120 rises (t21)
  • the reset transistor 123 of each pixel 120 is turned on
  • the floating diffusion 126 of each pixel 120 is reset.
  • the selection signal ⁇ SEL of each pixel 120 rises (t21)
  • the selection transistor 125 of each pixel 120 is turned on.
  • the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the source follower operation when the power supply potential Vdd is applied to the gate of the amplification transistor 124 of each pixel 120.
  • sample and hold signal ⁇ S rises (t21), and the sample and hold switches 404 connected to each of the vertical signal lines 132-1 to 132-4 are turned on. At this time, the capacitors 405 provided for each column are connected to the vertical signal lines 132-1 to 132-4 via the sample and hold switches 404, respectively.
  • sample and hold signal ⁇ VS rises (t21), and the sample and hold switches 403 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the capacitors 405 provided for each column are connected to the pixels 120 for each column via the vertical signal lines 132-1 to 132-4, respectively.
  • the auto zero signal AZ rises (t21), and the auto zero operation of the comparator 143 connected to each vertical signal line 132-1 to 132-4 is activated. At this time, the charge accumulated in each DC cut capacitor 144 and 145 is controlled so that the non-inverting input and the inverting input of comparator 143 connected to each vertical signal line 132-1 to 132-4 are balanced.
  • P-phase VSL settling/P-phase VSL sample and hold is performed (K22).
  • the pixel reset signal ⁇ PRT of each pixel 120 falls (t22), and the reset transistor 123 of each pixel 120 is turned off.
  • the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are applied. is set. Charges corresponding to the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are sampled and held in the capacitor 405 for each column. After that, the sample and hold signal ⁇ VS falls.
  • P-phase binning/P-phase AD is performed (K23).
  • the opening/closing signal ⁇ Cn rises (t23) and the auto-zero signal AZ falls.
  • the connection switches 402 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the charges accumulated in the capacitors 405 added to each vertical signal line 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are averaged. .
  • the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143.
  • the activated comparator 143 is supplied with a ramp signal as the reference signal RAP. Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the reset level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1.
  • the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the reset levels read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted. After that, the opening/closing signal ⁇ Cn falls.
  • transfer is performed (K24).
  • the transfer signal ⁇ TG of each pixel 120 rises (t24)
  • the transfer transistor 122 of each pixel 120 is turned on, and the charge accumulated in the photodiode 121 of each pixel 120 is transferred to the floating diffusion 126 of each pixel 120.
  • Ru Furthermore, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are adjusted based on the source follower operation when the cathode potential of the photodiode 121 of each pixel 120 is applied to the gate of the amplification transistor 124 of each pixel 120. is set.
  • sample and hold signal ⁇ VS rises (t24), and the sample and hold switches 403 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the capacitors 405 provided for each column are connected to the pixels 120 for each column via the vertical signal lines 132-1 to 132-4, respectively.
  • D-phase VSL settling/D-phase VSL sample and hold is performed (K25).
  • the transfer signal ⁇ TG of each pixel 120 falls (t25), and the transfer transistor 122 of each pixel 120 is turned off.
  • the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are applied. is set. Charges corresponding to the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are sampled and held in the capacitor 405 for each column. After that, the sample and hold signal ⁇ VS falls.
  • D-phase binning/P-phase AD is performed (K26).
  • the opening/closing signal ⁇ Cn rises (t26), and the connection switches 402 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the charges accumulated in the capacitors 405 added to each vertical signal line 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are averaged. .
  • the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143. Further, a ramp signal is supplied to the activated comparator 143 as the reference signal RAP (t26-t27).
  • the activated comparator 143 the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the signal level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1. At this time, the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4.
  • the average value of the signal level read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted. After that, the sample hold signal ⁇ S and the open/close signal ⁇ Cn fall, and the selection signal ⁇ SEL of each pixel 120 falls.
  • Ninth embodiment> In the second embodiment described above, binning was performed based on capacitive load reading.
  • a constant current transistor is connected in parallel to a series circuit of a signal line reset transistor 141 and a diode-connected transistor 142, so that constant current reading and capacitive load reading can be switched.
  • FIG. 18 is a block diagram showing a configuration example of a signal readout circuit for one column according to the ninth embodiment. Although the figure shows a signal readout circuit for one column, the same configuration can be applied to other columns as well.
  • this signal readout circuit has a sample and hold circuit 201 and a constant current transistor 301 added to the signal readout circuit of the second embodiment described above.
  • the other configuration of the signal readout circuit of the ninth embodiment is similar to the configuration of the signal readout circuit of the second embodiment described above.
  • the sample and hold circuit 201 samples and holds the bias voltage Vb and applies it to the gate of the constant current transistor 301.
  • Sample and hold circuit 201 includes a transistor 211 and a capacitor 212.
  • Transistor 211 may be a MOS transistor.
  • a sample and hold signal ⁇ SH is applied to the gate of the transistor 211.
  • Capacitor 212 is connected between the source of transistor 211 and ground potential.
  • the constant current transistor 301 is electrically connected to the vertical signal line 132-1.
  • Constant current transistor 301 may be a MOS transistor.
  • the gate of constant current transistor 301 is connected to the output of sample hold circuit 201.
  • bias voltage Vb is set to 0V and sample hold signal ⁇ SH is set to high level.
  • the constant current transistor 301 is turned off, and no current flows through the constant current transistor 301.
  • the operation of the signal readout circuit at this time is similar to the operation of the signal readout circuit of the first embodiment described above.
  • the transistor 211 In constant current readout, the transistor 211 is turned on and the bias voltage Vb is sampled and held in order to prevent horizontal scanning noise during AD conversion. Then, the transistor 211 is turned off, and the bias voltage Vb sampled and held by the sample and hold circuit 201 is applied to the gate of the constant current transistor 301. In this case, the constant current transistor 301 is turned on, and a constant current flows through the constant current transistor 301.
  • the operation of the signal readout circuit at this time is similar to the operation of the signal readout circuit of the eighth embodiment described above.
  • the constant current transistor 301 is connected in parallel to the series circuit of the signal line reset transistor 141 and the diode-connected transistor 142. This makes it possible to perform binning in the column direction while suppressing an increase in the area of the signal readout circuit, and to switch between constant current readout and capacitive load readout.
  • the signal line reset transistor 141 performs binning based on signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4.
  • substrates on which a solid-state imaging device including a pixel array section in which pixels 120 are arranged in a matrix are formed are laminated.
  • FIG. 19 is a perspective view showing a configuration example of an imaging device according to the tenth embodiment.
  • the solid-state imaging device 901 includes a support substrate 911 and a semiconductor substrate 912.
  • a semiconductor substrate 912 is stacked on a support substrate 911.
  • a pixel array section 913 and a peripheral circuit 914 are formed on the semiconductor substrate 912.
  • a column readout circuit 915 and a column ADC 916 are formed in the peripheral circuit 914.
  • the column readout circuit 915 and the column ADC 916 may be formed on both sides of the pixel array section 913 in the column direction.
  • pixels 120 are arranged in a matrix along the row and column directions.
  • the column readout circuit 915 can read signals from each pixel 120 individually based on capacitive load readout, or can perform binning and readout.
  • the signal line reset transistor 141 and connection switch 151 in FIG. 6 may be formed in the column readout circuit 915.
  • the column ADC 916 can AD convert signals read out via the column readout circuit 915 for each column.
  • the solid-state imaging device 901 can constitute a back-illuminated image sensor.
  • the solid-state imaging device 902 includes semiconductor substrates 921 and 922.
  • a semiconductor substrate 922 is stacked on the semiconductor substrate 921.
  • a pixel array section 923 is formed on the semiconductor substrate 922.
  • a peripheral circuit 924 is formed on the semiconductor substrate 922 .
  • a column readout circuit 925 and a column ADC 926 are formed.
  • the column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction.
  • the solid-state imaging device 902 can constitute a back-illuminated image sensor.
  • the substrates on which the solid-state imaging devices 901 and 902 are formed are laminated.
  • the semiconductor substrates 912 and 922 on which each pixel array section 913 and 923 are formed can be thinned, and a back-illuminated image sensor can be formed. can.
  • the technology according to the present disclosure (this technology) can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as a car, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, robot, etc. It's okay.
  • FIG. 20 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output section 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 includes a drive force generation device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits the drive force to wheels, and a drive force transmission mechanism that controls the steering angle of the vehicle. It functions as a control device for a steering mechanism to adjust and a braking device to generate braking force for the vehicle.
  • the body system control unit 12020 controls the operations of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a turn signal, or a fog lamp.
  • radio waves transmitted from a portable device that replaces a key or signals from various switches may be input to the body control unit 12020.
  • the body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, power window device, lamp, etc. of the vehicle.
  • the external information detection unit 12030 detects information external to the vehicle in which the vehicle control system 12000 is mounted.
  • an imaging section 12031 is connected to the outside-vehicle information detection unit 12030.
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the external information detection unit 12030 may perform object detection processing such as a person, car, obstacle, sign, or text on the road surface or distance detection processing based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electrical signal as an image or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • a driver condition detection section 12041 that detects the condition of the driver is connected to the in-vehicle information detection unit 12040.
  • the driver condition detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver condition detection unit 12041. It may be calculated, or it may be determined whether the driver is falling asleep.
  • the microcomputer 12051 calculates control target values for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and Control commands can be output to 12010.
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of autonomous driving, etc., which does not rely on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of preventing glare, such as switching from high beam to low beam. It can be carried out.
  • the audio and image output unit 12052 transmits an output signal of at least one of audio and images to an output device that can visually or audibly notify information to the occupants of the vehicle or to the outside of the vehicle.
  • an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 21 is a diagram showing an example of the installation position of the imaging section 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle 12100.
  • An imaging unit 12101 provided in the front nose and an imaging unit 12105 provided above the windshield inside the vehicle mainly acquire images in front of the vehicle 12100.
  • Imaging units 12102 and 12103 provided in the side mirrors mainly capture images of the sides of the vehicle 12100.
  • An imaging unit 12104 provided in the rear bumper or back door mainly captures images of the rear of the vehicle 12100.
  • the imaging unit 12105 provided above the windshield inside the vehicle is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 21 shows an example of the imaging range of the imaging units 12101 to 12104.
  • An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • an imaging range 12114 shows the imaging range of the imaging unit 12101 provided on the front nose.
  • the imaging range of the imaging unit 12104 provided in the rear bumper or back door is shown. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of image sensors, or may be an image sensor having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. In particular, by determining the three-dimensional object closest to the vehicle 12100 on its path and traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km/h or more), it is possible to extract the three-dimensional object as the preceding vehicle. can. Furthermore, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, cooperative control can be performed for the purpose of autonomous driving, etc., which does not rely on the driver's operation.
  • automatic brake control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 transfers three-dimensional object data to other three-dimensional objects such as two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, and utility poles based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceeds a set value and there is a possibility of a collision, the microcomputer 12051 transmits information via the audio speaker 12061 and the display unit 12062. By outputting a warning to the driver via the vehicle control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
  • the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceed
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101 to 12104.
  • pedestrian recognition involves, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and a pattern matching process is performed on a series of feature points indicating the outline of an object to determine whether it is a pedestrian or not.
  • the audio image output unit 12052 creates a rectangular outline for emphasis on the recognized pedestrian.
  • the display unit 12062 is controlled to display the .
  • the audio image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above.
  • the above-described camera 100 can be applied to the imaging unit 12031.
  • a pixel array section in which pixels are arranged in a matrix in the row direction and column direction; a signal line that transmits a signal read out from the pixel in the column direction; a sample hold switch that samples and holds the signal transmitted via the signal line for each column;
  • An imaging device comprising: a connection switch that connects signal lines of different columns in which the signals are sampled and held.
  • an AD converter that performs AD conversion for each column of signals transmitted via the signal line;
  • the AD conversion section a comparator that compares the potential of the signal line and the ramp signal;
  • the imaging device according to (2) further comprising a counter that performs a counting operation based on a comparison result of the comparator.
  • the solid-state imaging device according to (3) wherein the active control section controls the AD conversion section separately into an activated column and a deactivated column.
  • a first DC cut capacitor connected to the first input terminal of the comparator;
  • the active control unit is configured to switch a connection destination of a second capacitance electrode of the first DC cut capacitor, the first capacitance electrode of which is connected to the signal line, between a first input terminal of the comparator and ground.
  • the imaging device according to (5) above further comprising a switch.
  • the imaging device according to any one of (1) to (9), wherein the sample and hold switch is a transistor provided for each of the signal lines.
  • the imaging device (10), further comprising a driver that drives the transistor from both sides in the row direction.
  • a signal line reset transistor that resets the potential of the signal line;
  • the imaging device according to any one of (1) to (11), further comprising a signal line reset level generation unit that generates a reset level of the potential of the signal line.
  • the signal line reset level generation section includes a diode-connected transistor.
  • the imaging device according to any one of (1) to (13), wherein the capacitance used to sample and hold the signal is a parasitic capacitance of the signal line.
  • connection switch is connected in series to a capacitor for each column used for sample-holding the signal.
  • connection switch is connected in parallel to a capacitor for each column used for sample-holding the signal.
  • constant current transistor that is electrically connectable to the signal line and that flows a constant current based on a source follower formed between the pixel; For constant current readout, the constant current transistor is turned on; The imaging device according to any one of (1) to (16), wherein the constant current transistor is turned off during capacitive load reading.
  • the pixel is photodiode and a transfer transistor that transfers the charge accumulated in the photodiode to a floating diffusion; a reset transistor that resets the floating diffusion; an amplification transistor that outputs a signal according to the potential of the floating diffusion;

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The present invention enables binning while suppressing an increase in the number of switches connected to a signal line for transmitting, in a column direction, signals read out from pixels.　This imaging device comprises: a pixel array part in which pixels are arranged in a matrix shape in a row direction and a column direction; signal lines that transmit, in a column direction, signals read out from the pixels; a sample-and-hold switch for sampling and holding, for each column, a signal transmitted via the signal line; and a connection switch that connects signal lines of mutually different columns on which signals have been sampled and held. The imaging device may further comprise: an AD conversion unit that AD-converts, in each column, signals transmitted via the signal line; and an active control unit that activates one AD conversion unit among the AD conversion units of the columns connected via the connection switch.

Description

撮像装置Imaging device
　本技術は、撮像装置に関する。詳しくは、本技術は、ビニング機能が設けられた撮像装置に関する。 The present technology relates to an imaging device. Specifically, the present technology relates to an imaging device provided with a binning function.
　監視カメラや移動端末に搭載されたカメラでは、動体検出などの目的で常時動作させ、アナログビニングにて空間解像度を下げて低消費電力化する技術がある。このような撮像装置として、例えば、１つの画素信号を複数の信号保持部にそれぞれ保持し、複数の信号保持部に保持された画素信号を平均化して出力する撮像装置が提案されている（例えば、特許文献１参照）。 For surveillance cameras and cameras mounted on mobile terminals, there is a technology that allows them to operate constantly for purposes such as detecting moving objects, and reduces power consumption by lowering the spatial resolution using analog binning. As such an imaging device, for example, an imaging device has been proposed that holds one pixel signal in each of a plurality of signal holding sections and averages and outputs the pixel signals held in the plurality of signal holding sections (for example, , see Patent Document 1).
特開２０２０－９２３５３号公報JP2020-92353A
　しかしながら、上述の従来技術では、第１スイッチ回路は、画素を複数の信号保持部のそれぞれに選択的に接続して１つの画素信号を複数の信号保持部にそれぞれ保持し、第２スイッチ回路は、複数の信号保持部に保持された画素信号を平均化して出力する。このため、上述の従来技術では、画素から読出された信号をカラム方向に伝送する信号線に接続されるスイッチの個数が増大し、当該スイッチの専有面積の増大を招く恐れがあった。 However, in the above-mentioned conventional technology, the first switch circuit selectively connects the pixel to each of the plurality of signal holding sections to hold one pixel signal in each of the plurality of signal holding sections, and the second switch circuit , averages and outputs pixel signals held in a plurality of signal holding units. Therefore, in the above-mentioned conventional technology, the number of switches connected to the signal line that transmits signals read from pixels in the column direction increases, which may lead to an increase in the area occupied by the switches.
　本技術はこのような状況に鑑みて生み出されたものであり、画素から読出された信号をカラム方向に伝送する信号線に接続されるスイッチの個数の増大を抑制しつつ、ビニングを可能とすることを目的とする。 This technology was created in view of this situation, and enables binning while suppressing the increase in the number of switches connected to the signal line that transmits signals read from pixels in the column direction. The purpose is to
　本技術は、上述の問題点を解消するためになされたものであり、その第１の側面は、画素がロウ方向およびカラム方向にマトリックス状に配置された画素アレイ部と、前記画素から読出された信号を前記カラム方向に伝送する信号線と、前記信号線を介して伝送される信号をカラムごとにサンプルホールドさせるサンプルホールドスイッチと、前記信号がサンプルホールドされた互いに異なるカラムの信号線を接続する接続スイッチとを具備する撮像装置である。これにより、信号線を介して伝送される信号がカラムごとにサンプルホールドされた後、ビニングが実施されるという作用をもたらす。 The present technology was developed to solve the above-mentioned problems, and its first aspect is that it includes a pixel array section in which pixels are arranged in a matrix in the row direction and column direction, and a pixel array section in which pixels are read out from the pixels. A signal line that transmits the signal transmitted in the column direction, a sample hold switch that samples and holds the signal transmitted via the signal line for each column, and a signal line that connects the signal lines of different columns to which the signal is sampled and held. This is an imaging device equipped with a connection switch. This brings about the effect that binning is performed after the signals transmitted via the signal line are sampled and held for each column.
　また、第１の側面において、前記信号線を介して伝送される信号を前記カラムごとにＡＤ変換するＡＤ変換部と、前記接続スイッチを介して接続された各カラムのＡＤ変換部のうちの１つのＡＤ変換部をアクティブ化するアクティブ制御部とをさらに具備してもよい。これにより、ビニング処理時に動作が不要なＡＤ変換部の低消費電力化が図られるという作用をもたらす。 Further, in the first aspect, an AD converter that AD converts a signal transmitted via the signal line for each column, and one of the AD converters for each column connected via the connection switch. The device may further include an active control unit that activates one AD conversion unit. This brings about the effect that the power consumption of the AD converter, which does not need to operate during binning processing, can be reduced in power consumption.
　また、第１の側面において、前記ＡＤ変換部は、前記信号線の電位とランプ信号とを比較するコンパレータと、前記コンパレータの比較結果に基づいてカウント動作を実施するカウンタとを備えてもよい。これにより、信号線を介して伝送される信号がデジタル化されるという作用をもたらす。 Furthermore, in the first aspect, the AD conversion section may include a comparator that compares the potential of the signal line and a ramp signal, and a counter that performs a counting operation based on the comparison result of the comparator. This brings about the effect that the signal transmitted via the signal line is digitized.
　また、第１の側面において、前記アクティブ制御部は、前記ＡＤ変換部をアクティブ化されるカラムと非アクティブ化されるカラムとに分けて制御してもよい。これにより、複数のカラムのうち少なくとも１つのカラムのＡＤ変換部がビニング時に非アクティブ化されるという作用をもたらす。 Furthermore, in the first aspect, the active control section may control the AD conversion section separately into an activated column and a deactivated column. This brings about the effect that the AD converter of at least one column among the plurality of columns is deactivated during binning.
　また、第１の側面において、前記コンパレータの第１入力端子に接続された第１ＤＣカットコンデンサと、前記コンパレータの第２入力端子に接続された第２ＤＣカットコンデンサとをさらに具備してもよい。これにより、ＤＣカットされた信号がコンパレータに入力されるという作用をもたらす。 Furthermore, in the first aspect, the device may further include a first DC cut capacitor connected to the first input terminal of the comparator, and a second DC cut capacitor connected to the second input terminal of the comparator. This brings about the effect that the DC-cut signal is input to the comparator.
　また、第１の側面において、前記アクティブ制御部は、第１容量電極が前記信号線に接続される前記第１ＤＣカットコンデンサの第２容量電極の接続先を前記コンパレータの第１入力端子と接地との間で切り替える切替スイッチをさらに具備してもよい。これにより、あるカラムの第１ＤＣカットコンデンサの容量が別のカラムの信号線に付加されるという作用をもたらす。 Further, in the first aspect, the active control unit connects a connection destination of a second capacitance electrode of the first DC cut capacitor whose first capacitance electrode is connected to the signal line to a first input terminal of the comparator and ground. You may further include a changeover switch for switching between. This brings about the effect that the capacitance of the first DC cut capacitor in one column is added to the signal line in another column.
　また、第１の側面において、前記アクティブ制御部は、前記切替スイッチをアクティブ化されるカラムと非アクティブ化されるカラムとに分けて制御してもよい。これにより、非アクティブ化されるカラムに付加された容量がアクティブ化されるカラムの信号線の容量に付加されるという作用をもたらす。 Furthermore, in the first aspect, the active control unit may control the changeover switch separately for activated columns and deactivated columns. This brings about the effect that the capacitance added to the column to be deactivated is added to the capacitance of the signal line of the column to be activated.
　また、第１の側面において、前記信号線を介して伝送される信号を前記カラムごとに増幅して前記ＡＤ変換部に入力するアンプをさらに具備してもよい。これにより、ＡＤ変換部の信号入力が増大されるという作用をもたらす。 Furthermore, in the first aspect, the device may further include an amplifier that amplifies the signal transmitted via the signal line for each column and inputs the amplified signal to the AD conversion section. This brings about the effect that the signal input to the AD conversion section is increased.
　また、第１の側面において、前記アクティブ制御部は、前記アンプをアクティブ化されるカラムと非アクティブ化されるカラムとに分けて制御してもよい。これにより、複数のカラムのうち少なくとも１つのカラムのアンプがビニング時に非アクティブ化されるという作用をもたらす。 Furthermore, in the first aspect, the active control section may control the amplifiers separately into activated columns and deactivated columns. This brings about the effect that the amplifier of at least one column among the plurality of columns is deactivated during binning.
　また、第１の側面において、前記サンプルホールドスイッチは、前記信号線ごとに設けられたトランジスタでもよい。これにより、信号線を介して伝送される信号がカラムごとにサンプルホールドされるという作用をもたらす。 Furthermore, in the first aspect, the sample and hold switch may be a transistor provided for each of the signal lines. This brings about the effect that the signals transmitted via the signal line are sampled and held for each column.
　また、第１の側面において、前記トランジスタを前記ロウ方向の両側から駆動するドライバをさらに具備してもよい。これにより、複数のカラムに共通に設けられた２つのドライバに基づいて各カラムのトランジスタの駆動力が増大されるという作用をもたらす。 Furthermore, in the first aspect, the device may further include a driver that drives the transistor from both sides in the row direction. This brings about the effect that the driving force of the transistors in each column is increased based on the two drivers provided in common to the plurality of columns.
　また、第１の側面において、前記信号線の電位をリセットする信号線リセットトランジスタと、前記信号線の電位のリセットレベルを生成する信号線リセットレベル生成部とをさらに具備してもよい。これにより、０Ｖより高い電圧にリセットされた信号線の電位に基づいて、容量負荷読出しが可能となるという作用をもたらす。 Furthermore, in the first aspect, the device may further include a signal line reset transistor that resets the potential of the signal line, and a signal line reset level generation unit that generates a reset level of the potential of the signal line. This brings about the effect that capacitive load reading becomes possible based on the potential of the signal line reset to a voltage higher than 0V.
　また、第１の側面において、前記信号線リセットレベル生成部は、ダイオード接続トランジスタを備えてもよい。これにより、信号線のリセット時にダイオード接続トランジスタの順方向電圧に応じて信号線の電位が持ち上げられるという作用をもたらす。 Furthermore, in the first aspect, the signal line reset level generation section may include a diode-connected transistor. This brings about the effect that the potential of the signal line is raised in accordance with the forward voltage of the diode-connected transistor when the signal line is reset.
　また、第１の側面において、前記信号のサンプルホールドに用いられる容量は、前記信号線の寄生容量でもよい。これにより、信号線に容量素子を付加することなく、容量負荷読出しが可能となるという作用をもたらす。 Furthermore, in the first aspect, the capacitance used for sample and hold of the signal may be a parasitic capacitance of the signal line. This brings about the effect that capacitive load reading can be performed without adding a capacitive element to the signal line.
　また、第１の側面において、前記接続スイッチは、前記信号のサンプルホールドに用いられるカラムごとの容量に対して直列接続されてもよい。これにより、ビニングされるカラム数を可変としつつ、ビニングが可能となるという作用をもたらす。 Furthermore, in the first aspect, the connection switch may be connected in series to a capacitor for each column used for sample and hold of the signal. This brings about the effect of making binning possible while making the number of columns to be binned variable.
　また、第１の側面において、前記接続スイッチは、前記信号のサンプルホールドに用いられるカラムごとの容量に対して並列接続されてもよい。これにより、ビニングされるカラム数を固定しつつ、ビニングが可能となるという作用をもたらす。 Furthermore, in the first aspect, the connection switch may be connected in parallel to a capacitor for each column used for sample-holding the signal. This brings about the effect that binning can be performed while fixing the number of columns to be binned.
　また、第１の側面において、前記信号線に電気的に接続可能であり、前記画素との間に形成されるソースフォロワに基づいて定電流を流す定電流トランジスタをさらに具備し、定電流読出しでは、前記定電流トランジスタはオンされ、容量負荷読出しでは、前記定電流トランジスタはオフされてもよい。これにより、容量負荷読出しと定電流読出しとが切替可能となるという作用をもたらす。 In the first aspect, the invention further includes a constant current transistor that is electrically connectable to the signal line and that flows a constant current based on a source follower formed between the pixel and the constant current readout. , the constant current transistor may be turned on, and in capacitive load reading, the constant current transistor may be turned off. This brings about the effect that capacitive load readout and constant current readout can be switched.
　また、第１の側面において、前記画素は、フォトダイオードと、前記フォトダイオードに蓄積された電荷をフローティングディフュージョンに転送する転送トランジスタと、前記フローティングディフュージョンをリセットするリセットトランジスタと、前記フローティングディフュージョンの電位に応じた信号を出力する増幅トランジスタと、前記増幅トランジスタと前記信号線との間に接続された選択トランジスタとを備えてもよい。これにより、画素からの信号の読出し時に画素との間でソースフォロワが形成されるという作用をもたらす。 Further, in the first aspect, the pixel includes a photodiode, a transfer transistor that transfers the charge accumulated in the photodiode to the floating diffusion, a reset transistor that resets the floating diffusion, and a potential of the floating diffusion. The device may include an amplification transistor that outputs a corresponding signal, and a selection transistor connected between the amplification transistor and the signal line. This brings about the effect that a source follower is formed between the pixel and the pixel when a signal is read from the pixel.
　また、第１の側面において、前記サンプルホールドスイッチは、前記選択トランジスタでもよい。これにより、信号線を介して伝送される信号がカラムごとにサンプルホールドされるという作用をもたらす。 Furthermore, in the first aspect, the sample and hold switch may be the selection transistor. This brings about the effect that the signals transmitted via the signal line are sampled and held for each column.
　また、第１の側面において、互いに異なるロウのフローティングディフュージョンを接続するビニングトランジスタをさらに備えてもよい。これにより、互いに異なるロウのビニングが可能となるという作用をもたらす。 Furthermore, in the first aspect, a binning transistor may be further provided to connect floating diffusions in different rows. This brings about the effect that it is possible to binning mutually different rows.
第１の実施の形態に係る撮像装置が適用されるカメラの構成例を示すブロック図である。FIG. 1 is a block diagram illustrating a configuration example of a camera to which the imaging device according to the first embodiment is applied. 第１の実施の形態に係る固体撮像装置の構成例を示すブロック図である。1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment. FIG. 第１の実施の形態に係る固体撮像装置に設けられた画素の回路構成例を示すブロック図である。FIG. 2 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. 第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の構成例を示す断面図である。FIG. 3 is a cross-sectional view showing a configuration example of a pixel array section provided in the solid-state imaging device according to the first embodiment. 第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の変形例を示す断面図である。FIG. 7 is a cross-sectional view showing a modification of the pixel array section provided in the solid-state imaging device according to the first embodiment. 第１の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。FIG. 3 is a diagram showing a configuration example of a signal readout circuit for four columns according to the first embodiment. 第１の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。FIG. 3 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the first embodiment. 第１の実施の形態に係る信号読出し回路に適用されるコンパレータの構成例を示す図である。FIG. 3 is a diagram illustrating a configuration example of a comparator applied to the signal readout circuit according to the first embodiment. 第２の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。FIG. 7 is a diagram showing a configuration example of a signal readout circuit for four columns according to a second embodiment. 第３の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。FIG. 7 is a diagram showing a configuration example of a signal readout circuit for four columns according to a third embodiment. 第４の実施の形態に係る２カラム分の信号読出し回路の構成例を示す図である。FIG. 7 is a diagram showing an example of the configuration of a signal readout circuit for two columns according to a fourth embodiment. 第５の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to a fifth embodiment. 第６の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for four columns according to a sixth embodiment. 第６の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。FIG. 12 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the sixth embodiment. 第７の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to a seventh embodiment. 第８の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to an eighth embodiment. 第８の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。FIG. 12 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the eighth embodiment. 第９の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for one column according to a ninth embodiment. 第１０の実施の形態に係る撮像装置の構成例を示す斜視図である。FIG. 12 is a perspective view showing a configuration example of an imaging device according to a tenth embodiment. 車両制御システムの概略的な構成例を示すブロック図である。FIG. 1 is a block diagram showing a schematic configuration example of a vehicle control system. 撮像部の設置位置の一例を示す説明図である。FIG. 3 is an explanatory diagram showing an example of an installation position of an imaging unit.
　以下、本技術を実施するための形態（以下、実施の形態と称する）について説明する。説明は以下の順序により行う。
　１．第１の実施の形態（信号線リセットトランジスタが垂直信号線に接続されたカラムごとにサンプルホールドされた信号に基づいてビニングする例）
　２．第２の実施の形態（信号線リセットトランジスタを介してダイオード接続トランジスタが垂直信号線に接続されたカラムごとにサンプルホールドされた信号に基づいてビニングする例）
　３．第３の実施の形態（信号線リセットトランジスタが垂直信号線に接続されたカラムごとにサンプルホールドされた信号に基づいてビニングするとともに、サンプルホールドに用いられるカラムごとの容量に対して接続スイッチを並列接続した例）
　４．第４の実施の形態（信号線リセットトランジスタが垂直信号線に接続されたカラムごとにサンプルホールドされた信号に基づいて、ロウ方向およびカラム方向にビニングする例）
　５．第５の実施の形態（ＡＤ変換部に入力される信号を増幅するアンプをカラムごとに設けた例）
　６．第６の実施の形態（信号線ごとに設けられたサンプルホールドスイッチをロウ方向の両側から駆動するドライバを設けた例）
　７．第７の実施の形態（ＤＣカットコンデンサの接続先をコンパレータ入力と接地との間で切り替える例）
　８．第８の実施の形態（定電流トランジスタが垂直信号線に接続されたカラムごとにサンプルホールドされた信号に基づいてビニングする例）
　９．第９の実施の形態（信号線リセットトランジスタとダイオード接続トランジスタとの直列回路に並列に定電流トランジスタを接続した例）
　１０．第１０の実施の形態（固体撮像装置が形成される基板を積層化した例）
　１１．移動体への応用例 Hereinafter, a mode for implementing the present technology (hereinafter referred to as an embodiment) will be described. The explanation will be given in the following order.
1. First embodiment (an example of binning based on signals sampled and held for each column in which a signal line reset transistor is connected to a vertical signal line)
2. Second embodiment (an example of binning based on signals sampled and held for each column in which diode-connected transistors are connected to vertical signal lines via signal line reset transistors)
3. Third Embodiment (Binning is performed based on the signal sampled and held for each column in which the signal line reset transistor is connected to the vertical signal line, and connection switches are connected in parallel to the capacitance of each column used for sample and hold. Example of connection)
4. Fourth embodiment (an example of binning in the row direction and column direction based on a signal sampled and held for each column in which a signal line reset transistor is connected to a vertical signal line)
5. Fifth embodiment (example where each column is provided with an amplifier that amplifies the signal input to the AD conversion section)
6. Sixth embodiment (example in which a driver is provided to drive a sample hold switch provided for each signal line from both sides in the row direction)
7. Seventh embodiment (example of switching connection destination of DC cut capacitor between comparator input and ground)
8. Eighth embodiment (example of binning based on signals sampled and held for each column in which constant current transistors are connected to vertical signal lines)
9. Ninth embodiment (example in which a constant current transistor is connected in parallel to a series circuit of a signal line reset transistor and a diode-connected transistor)
10. Tenth embodiment (example in which substrates on which a solid-state imaging device is formed are laminated)
11. Example of application to mobile objects
　＜１．第１の実施の形態＞
　図１は、第１の実施の形態に係る撮像装置が適用されるカメラの構成例を示すブロック図である。 <1. First embodiment>
FIG. 1 is a block diagram showing a configuration example of a camera to which an imaging device according to a first embodiment is applied.
　同図において、カメラ１００は、光学系１０１、固体撮像装置１０２、撮像制御部１０３、画像処理部１０４、記憶部１０５、表示部１０６および操作部１０７を備える。撮像制御部１０３、画像処理部１０４、記憶部１０５、表示部１０６および操作部１０７は、バス１０８を介して互いに接続されている。なお、カメラ１００は、単体としても用いられてもよいし、スマートフォンなどの携帯端末に組み込まれてもよいし、認証装置や監視装置に組み込まれてもよい。 In the figure, a camera 100 includes an optical system 101, a solid-state imaging device 102, an imaging control section 103, an image processing section 104, a storage section 105, a display section 106, and an operation section 107. The imaging control section 103, the image processing section 104, the storage section 105, the display section 106, and the operation section 107 are connected to each other via a bus 108. Note that the camera 100 may be used alone, or may be incorporated into a mobile terminal such as a smartphone, or may be incorporated into an authentication device or a monitoring device.
　光学系１０１は、被写体からの光を固体撮像装置１０２に入射させ、被写像を固体撮像装置１０２の受光面に結像させる。光学系１０１は、例えば、フォーカスレンズ、ズームレンズおよび絞りなどを備えることができる。光学系１０１は、広角レンズ、標準レンズおよび望遠レンズなどの複数のレンズを備えてもよい。 The optical system 101 makes light from a subject enter the solid-state imaging device 102 and forms an image of the subject on the light-receiving surface of the solid-state imaging device 102. The optical system 101 can include, for example, a focus lens, a zoom lens, an aperture, and the like. Optical system 101 may include multiple lenses such as a wide-angle lens, a standard lens, and a telephoto lens.
　固体撮像装置１０２は、被写体からの光を画素ごとに電気信号に変換し、その電気信号をデジタル化して出力する。固体撮像装置１０２は、例えば、ＣＭＯＳ（Complementary Metal Oxide Semiconductor）イメージセンサでもよいし、ＣＣＤ(Charge Coupled Device)でもよい。 The solid-state imaging device 102 converts light from a subject into an electrical signal for each pixel, digitizes the electrical signal, and outputs the digital signal. The solid-state imaging device 102 may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device).
　撮像制御部１０３は、操作部１０７からの指令に基づいて固体撮像装置１０２による撮像を制御する。このとき、撮像制御部１０３は、固体撮像装置１０２の露光時間、露光量および撮像タイミングなどを制御することができる。 The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.
　画像処理部１０４は、固体撮像装置１０２からの出力に基づいて画像処理を実施する。画像処理は、例えば、ガンマ補正、ホワイトバランス処理、シャープネス処理、階調変換処理である。画像処理部１０４は、ソフトウェアに基づいて処理を実行するプロセッサを備えてもよい。 The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing. The image processing unit 104 may include a processor that executes processing based on software.
　記憶部１０５は、固体撮像装置１０２で撮像された撮像画像を記憶したり、固体撮像装置１０２の撮像パラメータなどを記憶したりする。また、記憶部１０５は、ソフトウェアに基づいてカメラ１００を動作させるプログラムを記憶することができる。記憶部１０５は、ＲＯＭ（Read Only Memory）、ＲＡＭ（Random Access Memory）およびメモリカードを含んでもよい。 The storage unit 105 stores captured images captured by the solid-state imaging device 102, and stores imaging parameters of the solid-state imaging device 102. Furthermore, the storage unit 105 can store a program for operating the camera 100 based on software. The storage unit 105 may include a ROM (Read Only Memory), a RAM (Random Access Memory), and a memory card.
　表示部１０６は、撮像画像を表示したり、撮像操作をサポートする各種情報を表示したりする。表示部１０６は、液晶ディスプレイでもよいし、有機ＥＬ（Electro Luminescence）ディスプレイでもよい。 The display unit 106 displays captured images and various information that supports imaging operations. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.
　操作部１０７は、カメラ１００を操作するユーザインターフェースを提供する。操作部１０７は、例えば、カメラ１００に設けられたボタン、ダイヤルおよびスイッチを含んでもよい。操作部１０７は、表示部１０６とともにタッチパネルで構成してもよい。 The operation unit 107 provides a user interface for operating the camera 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the camera 100. The operation unit 107 may be configured with a touch panel together with the display unit 106.
　図２は、第１の実施の形態に係る固体撮像装置の構成例を示すブロック図である。 FIG. 2 is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment.
　同図において、固体撮像装置１０２は、画素アレイ部１１１、垂直走査回路１１２、カラム読出し回路１１３、カラム信号処理部１１４、水平走査回路１１５、制御回路１１６、ドライバ１１７、１１８およびアクティブ制御部１１９を備える。 In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, a control circuit 116, drivers 117 and 118, and an active control section 119. Be prepared.
　画素アレイ部１１１は、複数の画素１２０を備える。画素１２０は、ロウ方向（水平方向とも言う）およびカラム方向（垂直方向とも言う）に沿ってマトリックス状に配列される。各画素１２０は、信号の読出し時にカラム読出し回路１１３との間でソースフォロワを構成することができる。各画素１２０は、ロウごとに水平駆動線１３１に接続され、カラムごとに垂直信号線１３２に接続される。水平駆動線１３１は、各画素１２０からの信号の読出し時に各画素１２０をロウごとに駆動する。垂直信号線１３２は、画素１２０からの信号読出し時に流れる電流に応じて蓄積された電荷に基づく電位をカラムごとにカラム信号処理部１１４に伝送する。なお、垂直信号線１３２は、特許請求の範囲に記載の信号線の一例である。 The pixel array section 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel 120 can form a source follower with the column readout circuit 113 during signal readout. Each pixel 120 is connected to a horizontal drive line 131 for each row and to a vertical signal line 132 for each column. The horizontal drive line 131 drives each pixel 120 row by row when reading signals from each pixel 120. The vertical signal line 132 transmits to the column signal processing unit 114 for each column a potential based on accumulated charges according to a current flowing when reading a signal from the pixel 120. Note that the vertical signal line 132 is an example of a signal line described in the claims.
　垂直走査回路１１２は、読出し対象となる画素１２０をカラム方向に走査する。垂直走査回路１１２は、垂直レジスタを用いて構成してもよい。 The vertical scanning circuit 112 scans the pixels 120 to be read in the column direction. The vertical scanning circuit 112 may be configured using vertical registers.
　カラム読出し回路１１３は、各画素１２０からの信号の読出し時に、各画素１２０との間でソースフォロワを構成することができる。このとき、カラム読出し回路１１３は、画素１２０に保持された電荷に基づいて垂直信号線１３２の電位を変化させることができる。カラム読出し回路１１３は、容量負荷読出しに対応することができる。カラム読出し回路１１３は、定電流読出しにも対応してもよい。 The column readout circuit 113 can form a source follower with each pixel 120 when reading signals from each pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120. Column readout circuit 113 can support capacitive load readout. The column readout circuit 113 may also support constant current readout.
　また、カラム読出し回路１１３は、垂直信号線１３２を介して伝送される信号をカラムごとにサンプルホールドさせるサンプルホールドスイッチと、信号がサンプルホールドされた互いに異なるカラムの垂直信号線１３２を接続する接続スイッチとを備える。このとき、カラム読出し回路１１３は、垂直信号線１３２を介して伝送される信号をカラムごとにサンプルホールドした後、ビニングを実施し、カラム信号処理部１１４に出力することができる。 The column readout circuit 113 also includes a sample and hold switch that samples and holds signals transmitted via the vertical signal line 132 for each column, and a connection switch that connects the vertical signal lines 132 of different columns on which signals are sampled and held. Equipped with. At this time, the column readout circuit 113 can sample and hold the signal transmitted via the vertical signal line 132 for each column, perform binning, and output the signal to the column signal processing section 114.
　各ドライバ１１７および１１８は、カラム読出し回路１１３に設けられたサンプルホールドスイッチをロウ方向の両側から駆動する。各ドライバ１１７および１１８は、カラムごとに設けられたサンプルホールドスイッチで共有することができる。各ドライバ１１７および１１８は、カラム読出し回路１１３の両側に配置してもよい。 Each driver 117 and 118 drives a sample hold switch provided in the column readout circuit 113 from both sides in the row direction. Each driver 117 and 118 can be shared by sample and hold switches provided for each column. Each driver 117 and 118 may be placed on either side of column readout circuit 113.
　カラム信号処理部１１４は、各画素１２０からカラム方向に伝送された信号を処理する。例えば、カラム信号処理部１１４は、各画素１２０からカラム方向に伝送された信号に基づいて、相関二重サンプリング（ＣＤＳ：Correlated Double Sampling）処理を実施することができる。また、カラム信号処理部１１４は、各画素１２０からカラム方向に伝送された信号に基づいて、ＡＤ（Analog to Digital）変換処理を実施し、撮像信号Ｇｏｕｔを出力することができる。このとき、カラム信号処理部１１４は、垂直信号線１３２を介して伝送される信号をＡＤ変換するＡＤ変換部をカラムごとに備えることができる。 The column signal processing unit 114 processes signals transmitted from each pixel 120 in the column direction. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on signals transmitted from each pixel 120 in the column direction. Further, the column signal processing unit 114 can perform AD (Analog to Digital) conversion processing based on the signals transmitted from each pixel 120 in the column direction, and output the image pickup signal Gout. At this time, the column signal processing section 114 can include an AD conversion section for each column that performs AD conversion on the signal transmitted via the vertical signal line 132.
　アクティブ制御部１１９は、接続スイッチを介して接続された各カラムのＡＤ変換部のうちの１つのＡＤ変換部をアクティブ化する。このとき、アクティブ制御部１１９は、ビニング時において各ＡＤ変換部のアクティブ化のタイミングを制御する制御信号ＣＴＬを各ＡＤ変換部に出力することができる。アクティブ制御部１１９は、アクティブ化されるカラムと非アクティブ化されるカラムとに分けてＡＤ変換部を制御してもよい。このとき、アクティブ制御部１１９は、アクティブ化されるカラムのＡＤ変換部をアクティブ化し、非アクティブ化されるカラムのＡＤ変換部をスタンバイ状態とすることができる。 The active control unit 119 activates one AD conversion unit among the AD conversion units of each column connected via the connection switch. At this time, the active control section 119 can output a control signal CTL to each AD conversion section to control the activation timing of each AD conversion section during binning. The active control unit 119 may control the AD conversion unit separately for activated columns and deactivated columns. At this time, the active control unit 119 can activate the AD conversion unit of the column to be activated and put the AD conversion unit of the column to be deactivated into a standby state.
　水平走査回路１１５は、読出し対象となる画素１２０をロウ方向に走査する。水平走査回路１１５は、水平レジスタを用いて構成してもよい。 The horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.
　制御回路１１６は、垂直走査回路１１２、カラム読出し回路１１３、カラム信号処理部１１４、水平走査回路１１５およびドライバ１１７および１１８を制御する。例えば、制御回路１１６は、カラム方向の走査タイミング、ロウ方向の走査タイミング、カラム読出し回路１１３の動作タイミングおよびカラム信号処理部１１４の処理タイミングを制御することができる。また、制御回路１１６は、各ドライバ１１７および１１８の駆動タイミングおよびアクティブ制御部１１９の動作タイミングを制御することができる。 The control circuit 116 controls the vertical scanning circuit 112, column readout circuit 113, column signal processing section 114, horizontal scanning circuit 115, and drivers 117 and 118. For example, the control circuit 116 can control the scan timing in the column direction, the scan timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing section 114. Further, the control circuit 116 can control the drive timing of each driver 117 and 118 and the operation timing of the active control section 119.
　なお、図２の構成例では、カラムごとにサンプルホールドされた信号に基づいてビニングするために、カラム読出し回路１１３にサンプルホールドスイッチを設けた例を示した。画素１２０から読み出された信号をカラムごとにサンプルホールドするために、画素１２０に設けられた選択トランジスタを用いてもよい。この方法では、カラム読出し回路１１３に設けられたサンプルホールドスイッチは不要である。また、カラム読出し回路１１３の両側のドライバ１１７および１１８も不要である。 Note that in the configuration example of FIG. 2, an example is shown in which a sample and hold switch is provided in the column readout circuit 113 in order to perform binning based on a signal sampled and held for each column. A selection transistor provided in the pixel 120 may be used to sample and hold the signal read out from the pixel 120 for each column. In this method, the sample and hold switch provided in the column readout circuit 113 is not required. Furthermore, drivers 117 and 118 on both sides of column readout circuit 113 are also unnecessary.
　また、カメラ１００の用途に応じてビニング読出しと全画素個別読出しとを切り替えてもよい。例えば、カメラ１００が搭載されたモバイル端末において、動体検出などのアプリケーションが起動された場合、ビニング処理を常時動作させてもよいし、静止画撮影などのアプリケーションが起動された場合、全画素個別読出しに切り替えてもよい。 Furthermore, depending on the purpose of the camera 100, it is also possible to switch between binning readout and all-pixel individual readout. For example, in a mobile terminal equipped with the camera 100, when an application such as moving object detection is started, binning processing may be operated constantly, or when an application such as still image shooting is started, all pixels are individually read out. You may switch to
　図３は、第１の実施の形態に係る固体撮像装置に設けられた画素の回路構成例を示すブロック図である。 FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.
　同図において、画素１２０は、フォトダイオード１２１、転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４、選択トランジスタ１２５およびフローティングディフュージョン１２６を備える。転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４および選択トランジスタ１２５として、ＭＯＳ（Metal Oxide Semiconductor）トランジスタを用いることができる。 In the figure, a pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion 126. MOS (Metal Oxide Semiconductor) transistors can be used as the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.
　増幅トランジスタ１２４と選択トランジスタ１２５は、直列に接続されている。フォトダイオード１２１のカソードは、転送トランジスタ１２２を介してフローティングディフュージョン１２６に接続されている。また、フローティングディフュージョン１２６は、リセットトランジスタ１２３を介して電源Ｖｄｄに接続されている。また、電源Ｖｄｄは、増幅トランジスタ１２４と選択トランジスタ１２５の直列回路を介して垂直信号線１３２に接続されている。増幅トランジスタ１２４のゲートはフローティングディフュージョン１２６に接続されている。 The amplification transistor 124 and the selection transistor 125 are connected in series. A cathode of the photodiode 121 is connected to a floating diffusion 126 via a transfer transistor 122. Furthermore, the floating diffusion 126 is connected to the power supply Vdd via the reset transistor 123. Further, the power supply Vdd is connected to the vertical signal line 132 via a series circuit of an amplification transistor 124 and a selection transistor 125. The gate of amplification transistor 124 is connected to floating diffusion 126 .
　転送トランジスタ１２２のゲートには、転送信号ΦＴＧが印加される。リセットトランジスタ１２３のゲートには、画素リセット信号ΦＰＲＴが印加される。選択トランジスタ１２５のゲートには、選択信号ΦＳＥＬが印加される。転送信号ΦＴＧ、画素リセット信号ΦＰＲＴおよび選択信号ΦＳＥＬは、図２の水平駆動線１３１を介して各画素１２０に伝送することができる。 A transfer signal ΦTG is applied to the gate of the transfer transistor 122. A pixel reset signal ΦPRT is applied to the gate of the reset transistor 123. A selection signal ΦSEL is applied to the gate of the selection transistor 125. The transfer signal ΦTG, pixel reset signal ΦPRT, and selection signal ΦSEL can be transmitted to each pixel 120 via the horizontal drive line 131 in FIG.
　転送トランジスタ１２２がオンすると、フォトダイオード１２１に蓄積された電荷がフローティングディフュージョン１２６に転送される。そして、選択トランジスタ１２５がオンすると、フローティングディフュージョン１２６の電位に応じて増幅トランジスタ１２４のソース電位が変化する。そして、増幅トランジスタ１２４のソース電位は、選択トランジスタ１２５を介して垂直信号線１３２に印加され、垂直信号線１３２を介して伝送される。また、リセットトランジスタ１２３がオンすると、フローティングディフュージョン１２６に蓄積された電荷が排出される。 When the transfer transistor 122 is turned on, the charges accumulated in the photodiode 121 are transferred to the floating diffusion 126. Then, when the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion 126. The source potential of the amplification transistor 124 is applied to the vertical signal line 132 via the selection transistor 125 and transmitted via the vertical signal line 132. Furthermore, when the reset transistor 123 is turned on, the charges accumulated in the floating diffusion 126 are discharged.
　図４は、第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の構成例を示す断面図である。なお、図４では、表面照射型固体撮像装置の例を示す。また、図４では、３画素分の構成例を示した。 FIG. 4 is a cross-sectional view showing an example of the configuration of a pixel array section provided in the solid-state imaging device according to the first embodiment. Note that FIG. 4 shows an example of a front-illuminated solid-state imaging device. Further, FIG. 4 shows a configuration example for three pixels.
　同図において、半導体基板２３１には、画素１２０ごとにフォトダイオード２３２が形成されている。半導体基板２３１の材料は、Ｓｉでもよいし、ＩｎＧａＡｓでもよいし、ＩｎＰでもよい。 In the figure, a photodiode 232 is formed on a semiconductor substrate 231 for each pixel 120. The material of the semiconductor substrate 231 may be Si, InGaAs, or InP.
　半導体基板２３１上には、ゲート電極２１４および配線層２１０が形成される。ゲート電極２１４は、ゲート絶縁膜２１３を介して半導体基板２３１上に形成される。ゲート電極２１４の側壁には、サイドウォール２１５が形成される。ゲート電極２１４の材料は、例えば、不純物が導入された多結晶シリコンを用いることができる。ゲート絶縁膜２１３の材料は、例えば、シリコン酸化膜を用いることができる。サイドウォール２１５の材料は、例えば、シリコン酸化膜またはシリコン窒化膜を用いることができる。 A gate electrode 214 and a wiring layer 210 are formed on the semiconductor substrate 231. Gate electrode 214 is formed on semiconductor substrate 231 with gate insulating film 213 interposed therebetween. A sidewall 215 is formed on the sidewall of the gate electrode 214 . As the material of the gate electrode 214, for example, polycrystalline silicon into which impurities are introduced can be used. As the material of the gate insulating film 213, for example, a silicon oxide film can be used. As the material of the sidewall 215, for example, a silicon oxide film or a silicon nitride film can be used.
　ゲート電極２１４は、画素トランジスタに用いることができる。画素トランジスタは、図３の転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４および選択トランジスタ１２５を含む。 The gate electrode 214 can be used for a pixel transistor. The pixel transistors include the transfer transistor 122, reset transistor 123, amplification transistor 124, and selection transistor 125 in FIG.
　ゲート電極２１４上には、配線２１６が形成される。図４では、３層配線の例を示した。このとき、配線２１６には、光をフォトダイオード２３２に入射させる開口部ＯＰ１が設けられる。ゲート電極２１４および配線２１６は、絶縁層２１７を介して絶縁される。絶縁層２１７は、例えば、シリコン酸化膜を用いることができる。配線２１６の材料は、例えば、ＡｌまたはＣｕなどの金属を用いることができる。 A wiring 216 is formed on the gate electrode 214. FIG. 4 shows an example of three-layer wiring. At this time, the wiring 216 is provided with an opening OP1 that allows light to enter the photodiode 232. Gate electrode 214 and wiring 216 are insulated via insulating layer 217. For example, a silicon oxide film can be used as the insulating layer 217. As the material of the wiring 216, for example, metal such as Al or Cu can be used.
　配線層２１０上には、画素１２０ごとにカラーフィルタ２１８が形成される。カラーフィルタ２１８上には、画素１２０ごとにマイクロレンズ２１９が形成されている。カラーフィルタ２１８およびマイクロレンズ２１９の材料は、例えば、アクリルまたはポリカーボネートなどの透明樹脂を用いることができる。カラーフィルタ２１８は、着色に顔料が添加されてもよい。カラーフィルタ２１８は、例えば、ベイヤ配列を構成することができる。 A color filter 218 is formed on the wiring layer 210 for each pixel 120. A microlens 219 is formed on the color filter 218 for each pixel 120. As the material of the color filter 218 and the microlens 219, for example, transparent resin such as acrylic or polycarbonate can be used. A pigment may be added to the color filter 218 for coloring. The color filter 218 can have a Bayer array, for example.
　図５は、第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の変形例を示す断面図である。なお、図５では、裏面照射型固体撮像装置の例を示す。また、図５では、３画素分の構成例を示した。 FIG. 5 is a cross-sectional view showing a modification of the pixel array section provided in the solid-state imaging device according to the first embodiment. Note that FIG. 5 shows an example of a back-illuminated solid-state imaging device. Further, FIG. 5 shows a configuration example for three pixels.
　同図において、半導体層２２１には、画素１２０ごとにフォトダイオード２２２が形成されている。半導体層２２１の材料は、Ｓｉでもよいし、ＩｎＧａＡｓでもよいし、ＩｎＰでもよい。半導体層２２１は、例えば、フォトダイオード２２２が表面側に形成された半導体基板を裏面側から薄膜化して形成することができる。 In the figure, a photodiode 222 is formed in a semiconductor layer 221 for each pixel 120. The material of the semiconductor layer 221 may be Si, InGaAs, or InP. The semiconductor layer 221 can be formed, for example, by thinning a semiconductor substrate on which the photodiode 222 is formed from the back side.
　半導体層２２１上には、ゲート電極２２４および配線層２２０が形成される。ゲート電極２２４は、ゲート絶縁膜２２３を介して半導体層２２１上に形成される。ゲート電極２２４の側壁には、サイドウォール２２５が形成される。 A gate electrode 224 and a wiring layer 220 are formed on the semiconductor layer 221. Gate electrode 224 is formed on semiconductor layer 221 with gate insulating film 223 interposed therebetween. A sidewall 225 is formed on the sidewall of the gate electrode 224 .
　ゲート電極２２４は、画素トランジスタに用いることができる。画素トランジスタは、図３の転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４および選択トランジスタ１２５を含む。 The gate electrode 224 can be used for a pixel transistor. The pixel transistors include the transfer transistor 122, reset transistor 123, amplification transistor 124, and selection transistor 125 in FIG.
　ゲート電極２２４上には、配線２２６が形成される。図５では、３層配線の例を示した。ゲート電極２２４および配線２２６は、絶縁層２２７を介して絶縁される。半導体層２２１は、絶縁層２２７を介し、支持基板２３０上に支持される。支持基板２３０は、ガラス基板でもよいし、Ｓｉ基板でもよいし、サファイア基板でもよい。 A wiring 226 is formed on the gate electrode 224. FIG. 5 shows an example of three-layer wiring. Gate electrode 224 and wiring 226 are insulated via insulating layer 227. The semiconductor layer 221 is supported on a support substrate 230 with an insulating layer 227 interposed therebetween. The support substrate 230 may be a glass substrate, a Si substrate, or a sapphire substrate.
　半導体層２２１の裏面側には、画素１２０ごとにカラーフィルタ２２８が形成される。カラーフィルタ２２８上には、画素１２０ごとにマイクロレンズ２２９が形成されている。カラーフィルタ２２８は、例えば、ベイヤ配列を構成することができる。 A color filter 228 is formed for each pixel 120 on the back side of the semiconductor layer 221. A microlens 229 is formed on the color filter 228 for each pixel 120. The color filter 228 can have a Bayer array, for example.
　図６は、第１の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。 FIG. 6 is a diagram showing a configuration example of a signal readout circuit for four columns according to the first embodiment.
　同図において、各垂直信号線１３２－１から１３２－４には、画素１２０がそれぞれ接続される。このとき、各画素１２０の増幅トランジスタ１２４は、選択トランジスタ１２５をそれぞれ介して各垂直信号線１３２－１から１３２－４に接続される。また、各垂直信号線１３２－１から１３２－４には、容量１３３が付加される。この容量１３３は、各画素１２０から読出された信号のカラムごとのサンプルホールドに用いることができる。この容量１３３は、各垂直信号線１３２－１から１３２－４の寄生容量でもよいし、各垂直信号線１３２－１から１３２－４に接続された容量素子でもよい。このとき、各画素１２０の選択トランジスタ１２５は、各垂直信号線１３２－１から１３２－４を介して伝送される信号をカラムごとに容量１３３にサンプルホールドさせるサンプルホールドスイッチとして用いることができる。 In the figure, pixels 120 are connected to each vertical signal line 132-1 to 132-4, respectively. At this time, the amplification transistor 124 of each pixel 120 is connected to each vertical signal line 132-1 to 132-4 via a selection transistor 125, respectively. Further, a capacitor 133 is added to each vertical signal line 132-1 to 132-4. This capacitor 133 can be used to sample and hold signals read out from each pixel 120 for each column. This capacitance 133 may be a parasitic capacitance of each vertical signal line 132-1 to 132-4, or a capacitive element connected to each vertical signal line 132-1 to 132-4. At this time, the selection transistor 125 of each pixel 120 can be used as a sample and hold switch that causes the capacitor 133 to sample and hold the signals transmitted via the vertical signal lines 132-1 to 132-4 for each column.
　また、各垂直信号線１３２－１から１３２－４には、信号線リセットトランジスタ１４１が電気的に接続される。信号線リセットトランジスタ１４１は、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４をリセットすることができる。各信号線リセットトランジスタ１４１は、例えば、ＭＯＳトランジスタを用いることができる。各信号線リセットトランジスタ１４１のゲートには、信号線リセット信号ΦＲＴが印加される。各信号線リセットトランジスタ１４１のソースは、リセット電位ＶＲに接続される。リセット電位ＶＲは、接地電位よりも高い電位に設定してもよい。 Further, a signal line reset transistor 141 is electrically connected to each vertical signal line 132-1 to 132-4. The signal line reset transistor 141 can reset the potentials VSL1 to VSL4 of the respective vertical signal lines 132-1 to 132-4. For each signal line reset transistor 141, for example, a MOS transistor can be used. A signal line reset signal ΦRT is applied to the gate of each signal line reset transistor 141. The source of each signal line reset transistor 141 is connected to reset potential VR. The reset potential VR may be set to a higher potential than the ground potential.
　また、信号読出し回路には、各垂直信号線１３２－１から１３２－４を介して伝送される信号をカラムごとにＡＤ変換するＡＤ変換部が設けられる。ＡＤ変換部には、コンパレータ１４３およびカウンタ１４６がカラムごとに設けられる。各コンパレータ１４３は、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４と参照信号ＲＡＰとをカラムごとに比較する。参照信号ＲＡＰはランプ信号でもよい。各カウンタ１４６は、各コンパレータ１４３の比較結果に基づいてカウント動作をカラムごとに実施する。 Further, the signal readout circuit is provided with an AD conversion section that performs AD conversion for each column of the signals transmitted via each vertical signal line 132-1 to 132-4. The AD converter is provided with a comparator 143 and a counter 146 for each column. Each comparator 143 compares the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 with the reference signal RAP for each column. The reference signal RAP may be a ramp signal. Each counter 146 performs a counting operation for each column based on the comparison result of each comparator 143.
　各垂直信号線１３２－１から１３２－４は、各ＤＣカットコンデンサ１４４を介してコンパレータ１４３の反転入力にそれぞれ接続される。ここで、各画素１２０から信号を個別に読出す場合、各コンパレータ１４３の反転入力には、ＤＣカットコンデンサ１４４をそれぞれ介して各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が印加される。異なるカラムの信号をビニングして読出す場合、各コンパレータ１４３の反転入力には、ＤＣカットコンデンサ１４４をそれぞれ介して各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が印加される。各コンパレータ１４３の非反転入力には、ＤＣカットコンデンサ１４５をそれぞれ介して参照信号ＲＡＰが入力される。 Each vertical signal line 132-1 to 132-4 is connected to an inverting input of a comparator 143 via each DC cut capacitor 144. Here, when reading signals from each pixel 120 individually, potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are applied to the inverting input of each comparator 143 via a DC cut capacitor 144, respectively. be done. When reading signals from different columns by binning, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is applied to the inverting input of each comparator 143 via the DC cut capacitor 144, respectively. be done. A reference signal RAP is input to a non-inverting input of each comparator 143 via a DC cut capacitor 145, respectively.
　また、各コンパレータ１４３には、オートゼロ信号ＡＺが入力される。オートゼロ信号ＡＺは、オートゼロ期間にオートゼロ動作をアクティブ化する。オートゼロ動作では、コンパレータ１４３の非反転入力および反転入力がバランスするように各ＤＣカットコンデンサ１４４および１４５に蓄積される電荷を制御することができる。 Furthermore, an auto-zero signal AZ is input to each comparator 143. The autozero signal AZ activates autozero operation during the autozero period. In auto-zero operation, the charge accumulated in each DC cut capacitor 144 and 145 can be controlled so that the non-inverting input and the inverting input of comparator 143 are balanced.
　また、信号読出し回路には、接続スイッチ１５１が設けられる。接続スイッチ１５１は、互いに異なるカラムの垂直信号線１３２－１から１３２－４を接続する。このとき、接続スイッチ１５１は、各画素１２０から読出された信号のサンプルホールドに用いられるカラムごとの容量１３３に対して直列接続される。各接続スイッチ１５１は、ロウ方向に互いに隣接する垂直信号線１３２－１から１３２－４の間に設けることができる。各接続スイッチ１５１は、開閉信号ΦＣｎ１からΦＣｎ４にそれぞれ基づいてオン／オフすることができる。 Additionally, a connection switch 151 is provided in the signal readout circuit. Connection switch 151 connects vertical signal lines 132-1 to 132-4 in different columns. At this time, the connection switch 151 is connected in series to the capacitor 133 for each column used for sampling and holding the signal read out from each pixel 120. Each connection switch 151 can be provided between vertical signal lines 132-1 to 132-4 adjacent to each other in the row direction. Each connection switch 151 can be turned on/off based on open/close signals ΦCn1 to ΦCn4, respectively.
　ここで、各画素１２０からの信号の読出し前に、各垂直信号線１３２－１から１３２－４に接続された信号線リセットトランジスタ１４１がそれぞれオンすることで、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が０Ｖより高い電位に設定される。そして、各垂直信号線１３２－１から１３２－４に接続された信号線リセットトランジスタ１４１がそれぞれオフした後、各画素１２０の選択トランジスタ１２５がオンすることで、各画素１２０から信号が読出される。このとき、各画素１２０から読出された信号に応じた電荷が各垂直信号線１３２－１から１３２－４にそれぞれ付加された容量１３３に蓄積される。そして、各垂直信号線１３２－１から１３２－４にそれぞれ付加された容量１３３に蓄積された電荷に基づいて各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が変化する。 Here, before reading signals from each pixel 120, the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned on, so that each vertical signal line 132-1 to 132 -4 potentials VSL1 to VSL4 are set to potentials higher than 0V. Then, after the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned off, the selection transistor 125 of each pixel 120 is turned on, so that a signal is read out from each pixel 120. . At this time, charges corresponding to the signals read from each pixel 120 are accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4, respectively. Then, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 change based on the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4, respectively.
　そして、各垂直信号線１３２－１から１３２－４に接続されたコンパレータ１４３において、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が参照信号ＲＡＰと比較され、それぞれの比較結果ＣＯＰ１からＣＯＰ４が出力される。このとき、各コンパレータ１４３は、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が参照信号ＲＡＰのレベルと一致するタイミングを比較結果ＣＯＰ１からＣＯＰ４として各カウンタ１４６に出力することができる。各カウンタ１４６は、各コンパレータ１４３の比較結果ＣＯＰ１からＣＯＰ４に基づいてカウント動作を実施し、各カウント動作に基づくカウント値を出力する。 Then, in the comparator 143 connected to each vertical signal line 132-1 to 132-4, the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are compared with the reference signal RAP, and each comparison result COP1 COP4 is output from. At this time, each comparator 143 can output the timing when the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 match the level of the reference signal RAP to each counter 146 as comparison results COP1 to COP4. . Each counter 146 performs a counting operation based on the comparison results COP1 to COP4 of each comparator 143, and outputs a count value based on each counting operation.
　一方、各画素１２０からの信号をビニングして読出す場合、各画素１２０の選択トランジスタ１２５がオフした後、開閉信号ΦＣｎ１からΦＣｎ４が立ち上がることで垂直信号線１３２－１から１３２－４が互いに接続される。このとき、各垂直信号線１３２－１から１３２－４にそれぞれ付加された容量１３３に蓄積された電荷はビニングされ、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が平均化される。そして、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が各コンパレータ１４３に入力される。 On the other hand, when the signals from each pixel 120 are binned and read out, after the selection transistor 125 of each pixel 120 is turned off, the open/close signals ΦCn1 to ΦCn4 rise, so that the vertical signal lines 132-1 to 132-4 are connected to each other. be done. At this time, the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. Ru. Then, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143.
　このとき、図２のアクティブ制御部１１９は、垂直信号線１３２－１から１３２－４ごとにＡＤ変換を実施するコンパレータ１４３およびカウンタ１４６のうちの１つをアクティブ化する。例えば、アクティブ制御部１１９は、各垂直信号線１３２－１から１３２－４に対応して設けられたコンパレータ１４３およびカウンタ１４６のうち垂直信号線１３２－１に対応して設けられたコンパレータ１４３およびカウンタ１４６をアクティブ化してもよい。このとき、アクティブ制御部１１９は、垂直信号線１３２－１に対応して設けられたコンパレータ１４３およびカウンタ１４６の制御信号ＣＴＬをＡＣＴに設定することができる。また、アクティブ制御部１１９は、各垂直信号線１３２－２から１３２－４に対応して設けられたコンパレータ１４３およびカウンタ１４６の制御信号ＣＴＬをＳＴＢに設定することができる。ＡＣＴは、アクティブ化を指示し、ＳＴＢはスタンバイ化を指示することができる。 At this time, the active control unit 119 in FIG. 2 activates one of the comparator 143 and the counter 146 that perform AD conversion for each of the vertical signal lines 132-1 to 132-4. For example, the active control unit 119 controls the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 among the comparators 143 and counter 146 provided corresponding to the vertical signal lines 132-1 to 132-4. 146 may be activated. At this time, the active control unit 119 can set the control signal CTL of the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 to ACT. Furthermore, the active control unit 119 can set the control signal CTL of the comparator 143 and counter 146 provided corresponding to each vertical signal line 132-2 to 132-4 to STB. ACT can instruct activation, and STB can instruct standby.
　そして、垂直信号線１３２－１に接続されたコンパレータ１４３において、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が参照信号ＲＡＰと比較され、その比較結果ＣＯＰ１が出力される。このとき、垂直信号線１３２－１に接続されたコンパレータ１４３は、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が参照信号ＲＡＰのレベルと一致するタイミングを比較結果ＣＯＰ１としてカウンタ１４６に出力することができる。カウンタ１４６は、コンパレータ１４３の比較結果ＣＯＰ１に基づいてカウント動作を実施し、そのカウント動作に基づくカウント値を出力する。 Then, in the comparator 143 connected to the vertical signal line 132-1, the average value of the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 is compared with the reference signal RAP, and the comparison result COP1 is output. Ru. At this time, the comparator 143 connected to the vertical signal line 132-1 determines the timing at which the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 matches the level of the reference signal RAP as a comparison result COP1. It can be output to the counter 146 as follows. The counter 146 performs a counting operation based on the comparison result COP1 of the comparator 143, and outputs a count value based on the counting operation.
　図７は、第１の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。なお、同図では、ビニング読出し時の各部の波形の一例を示した。また、同図では、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４およびそれらの平均値をＶＳＬで示した。 FIG. 7 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the first embodiment. In addition, in the figure, an example of the waveform of each part at the time of binning read-out is shown. Further, in the figure, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 and their average value are indicated by VSL.
　同図において、容量負荷読出しでは、画素リセット／ＶＳＬリセットが実施される（Ｋ１１）。このとき、各画素１２０の画素リセット信号ΦＰＲＴが立ち上がり（ｔ１１）、各画素１２０のリセットトランジスタ１２３がオンして各画素１２０のフローティングディフュージョン１２６がリセットされる。なお、各画素１２０のフローティングディフュージョン１２６のリセットレベルは、電源電位Ｖｄｄに設定することができる。また、信号線リセット信号ΦＲＴが立ち上がり（ｔ１１）、各垂直信号線１３２－１から１３２－４に接続された信号線リセットトランジスタ１４１がそれぞれオンして各垂直信号線１３２－１から１３２－４がリセットされる。このとき、各垂直信号線１３２－１から１３２－４のリセットレベルは、各垂直信号線１３２－１から１３２－４に接続された信号線リセットトランジスタ１４１をそれぞれ介してリセット電位ＶＲに設定される。 In the figure, pixel reset/VSL reset is performed in capacitive load readout (K11). At this time, the pixel reset signal ΦPRT of each pixel 120 rises (t11), the reset transistor 123 of each pixel 120 is turned on, and the floating diffusion 126 of each pixel 120 is reset. Note that the reset level of the floating diffusion 126 of each pixel 120 can be set to the power supply potential Vdd. Further, the signal line reset signal ΦRT rises (t11), and the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned on, and each vertical signal line 132-1 to 132-4 is turned on. will be reset. At this time, the reset level of each vertical signal line 132-1 to 132-4 is set to the reset potential VR via the signal line reset transistor 141 connected to each vertical signal line 132-1 to 132-4. .
　また、開閉信号ΦＣｎ＊が立ち上がり（ｔ１１）、各垂直信号線１３２－１から１３２－４に接続された接続スイッチ１５１のうちの複数の接続スイッチ１５１がオンする。なお、開閉信号ΦＣｎ＊は、開閉信号ΦＣｎ１からΦＣｎ４のうちから選択された複数の開閉信号を示す。以下の説明では、開閉信号ΦＣｎ＊が開閉信号ΦＣｎ１からΦＣｎ４である場合を例にとる。このとき、各垂直信号線１３２－１から１３２－４にそれぞれ付加された容量１３３に蓄積された電荷が均等化される。 Furthermore, the open/close signal ΦCn* rises (t11), and a plurality of connection switches 151 among the connection switches 151 connected to each of the vertical signal lines 132-1 to 132-4 are turned on. Note that the open/close signal ΦCn* indicates a plurality of open/close signals selected from among the open/close signals ΦCn1 to ΦCn4. In the following explanation, a case will be taken as an example where the opening/closing signal ΦCn* is one of the opening/closing signals ΦCn1 to ΦCn4. At this time, the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are equalized.
　また、オートゼロ信号ＡＺが立ち上がり（ｔ１１）、各垂直信号線１３２－１から１３２－４に接続されたコンパレータ１４３のオートゼロ動作がアクティブ化される。このとき、各垂直信号線１３２－１から１３２－４に接続されたコンパレータ１４３の非反転入力および反転入力がバランスするように各ＤＣカットコンデンサ１４４および１４５に蓄積される電荷が制御される。そして、画素リセット信号ΦＰＲＴが立ち下がり、開閉信号ΦＣｎ＊が立ち下がり、信号線リセット信号ΦＲＴが立ち下がる。 Furthermore, the auto zero signal AZ rises (t11), and the auto zero operation of the comparator 143 connected to each vertical signal line 132-1 to 132-4 is activated. At this time, the charge accumulated in each DC cut capacitor 144 and 145 is controlled so that the non-inverting input and the inverting input of comparator 143 connected to each vertical signal line 132-1 to 132-4 are balanced. Then, the pixel reset signal ΦPRT falls, the open/close signal ΦCn* falls, and the signal line reset signal ΦRT falls.
　次に、Ｐ相ＶＳＬセトリング／Ｐ相ＶＳＬサンプルホールドが実施される（Ｋ１２）。このとき、各画素１２０の選択信号ΦＳＥＬが立ち上がり（ｔ１２）、各画素１２０の選択トランジスタ１２５がオンする。そして、各画素１２０の増幅トランジスタ１２４のソースフォロワ動作に基づいて各画素１２０のフローティングディフュージョン１２６のリセットレベルに応じた電荷が各垂直信号線１３２－１から１３２－４に付加された容量１３３にそれぞれ蓄積される。そして、各垂直信号線１３２－１から１３２－４に付加された容量１３３に蓄積された電荷に基づいて各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が設定される。 Next, P-phase VSL settling/P-phase VSL sample hold is performed (K12). At this time, the selection signal ΦSEL of each pixel 120 rises (t12), and the selection transistor 125 of each pixel 120 is turned on. Then, based on the source follower operation of the amplification transistor 124 of each pixel 120, charges corresponding to the reset level of the floating diffusion 126 of each pixel 120 are applied to the capacitors 133 added to the vertical signal lines 132-1 to 132-4, respectively. Accumulated. Then, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4.
　次に、Ｐ相ビニング／Ｐ相ＡＤが実施される（Ｋ１３）。このとき、各画素１２０の選択信号ΦＳＥＬが立ち下がった後（ｔ１３）、開閉信号ΦＣｎ＊が立ち上がり、オートゼロ信号ＡＺが立ち下がる。開閉信号ΦＣｎ＊が立ち上がると、各垂直信号線１３２－１から１３２－４に接続された接続スイッチ１５１がオンする。そして、各垂直信号線１３２－１から１３２－４にそれぞれ付加された容量１３３に蓄積された電荷がビニングされ、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が平均化される。そして、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が各コンパレータ１４３に入力される。また、例えば、各垂直信号線１３２－１から１３２－４に対応して設けられたコンパレータ１４３およびカウンタ１４６のうち垂直信号線１３２－１に対応して設けられたコンパレータ１４３およびカウンタ１４６のみがアクティブ化される。また、アクティブ化されたコンパレータ１４３には、参照信号ＲＡＰとしてランプ信号が供給される。そして、アクティブ化されたコンパレータ１４３において、リセットレベルに応じた各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が参照信号ＲＡＰと比較される。そして、参照信号ＲＡＰのレベルが各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値と一致したときのタイミングが比較結果ＣＯＰ１として出力される。このとき、アクティブ化されたカウンタ１４６において、参照信号ＲＡＰのレベルが各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値と一致するまでカウント動作が実施される。そして、アクティブ化されたカウンタ１４６のカウント動作に基づいて、各垂直信号線１３２－１から１３２－４に接続された各画素１２０から読出されたリセットレベルの平均値がＡＤ変換される。 Next, P-phase binning/P-phase AD is performed (K13). At this time, after the selection signal ΦSEL of each pixel 120 falls (t13), the open/close signal ΦCn* rises and the auto-zero signal AZ falls. When the opening/closing signal ΦCn* rises, the connection switches 151 connected to each of the vertical signal lines 132-1 to 132-4 are turned on. Then, the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. . Then, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143. Further, for example, among the comparators 143 and counters 146 provided corresponding to the vertical signal lines 132-1 to 132-4, only the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 are active. be converted into Further, the activated comparator 143 is supplied with a ramp signal as the reference signal RAP. Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the reset level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1. At this time, the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the reset levels read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted.
　次に、転送／ＶＳＬリセットが実施される（Ｋ１４）。このとき、各画素１２０の転送信号ΦＴＧが立ち上がり（ｔ１４）、各画素１２０の転送トランジスタ１２２がオンして各画素１２０のフォトダイオード１２１に蓄積された電荷が各画素１２０のフローティングディフュージョン１２６に転送される。また、信号線リセット信号ΦＲＴが立ち上がり（ｔ１４）、各垂直信号線１３２－１から１３２－４に接続された信号線リセットトランジスタ１４１がそれぞれオンして各垂直信号線１３２－１から１３２－４がリセットされる。このとき、各垂直信号線１３２－１から１３２－４のリセットレベルは、各垂直信号線１３２－１から１３２－４に接続された信号線リセットトランジスタ１４１をそれぞれ介してリセット電位ＶＲに設定される。そして、転送信号ΦＴＧが立ち下がるとともに、開閉信号ΦＣｎ＊が立ち下がり、信号線リセット信号ΦＲＴが立ち下がる（ｔ１５）。 Next, transfer/VSL reset is performed (K14). At this time, the transfer signal ΦTG of each pixel 120 rises (t14), the transfer transistor 122 of each pixel 120 is turned on, and the charge accumulated in the photodiode 121 of each pixel 120 is transferred to the floating diffusion 126 of each pixel 120. Ru. Further, the signal line reset signal ΦRT rises (t14), and the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned on, and each vertical signal line 132-1 to 132-4 is turned on. will be reset. At this time, the reset level of each vertical signal line 132-1 to 132-4 is set to the reset potential VR via the signal line reset transistor 141 connected to each vertical signal line 132-1 to 132-4. . Then, as the transfer signal ΦTG falls, the open/close signal ΦCn* falls, and the signal line reset signal ΦRT falls (t15).
　次に、Ｄ相ＶＳＬセトリング／Ｄ相ＶＳＬサンプルホールドが実施される（Ｋ１５）。このとき、選択信号ΦＳＥＬが立ち上がり（ｔ１６）、各画素１２０の選択トランジスタ１２５がオンする。そして、各画素１２０の増幅トランジスタ１２４のソースフォロワ動作に基づいて各画素１２０のフローティングディフュージョン１２６の信号レベルに応じた電荷が各垂直信号線１３２－１から１３２－４に付加された容量１３３にそれぞれ蓄積される。そして、各垂直信号線１３２－１から１３２－４に付加された容量１３３に蓄積された電荷に基づいて各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が設定される。 Next, D-phase VSL settling/D-phase VSL sample and hold is performed (K15). At this time, the selection signal ΦSEL rises (t16), and the selection transistor 125 of each pixel 120 is turned on. Then, based on the source follower operation of the amplification transistor 124 of each pixel 120, a charge corresponding to the signal level of the floating diffusion 126 of each pixel 120 is applied to the capacitor 133 added to each vertical signal line 132-1 to 132-4. Accumulated. Then, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4.
　次に、Ｄ相ビニング／Ｄ相ＡＤが実施される（Ｋ１６）。このとき、選択信号ΦＳＥＬが立ち下がった後（ｔ１７）、開閉信号ΦＣｎ＊が立ち上がる。開閉信号ΦＣｎ＊が立ち上がると、各垂直信号線１３２－１から１３２－４に接続された接続スイッチ１５１がオンする。そして、各垂直信号線１３２－１から１３２－４にそれぞれ付加された容量１３３に蓄積された電荷がビニングされ、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が平均化される。そして、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が各コンパレータ１４３に入力される。また、アクティブ化されたコンパレータ１４３には、参照信号ＲＡＰとしてランプ信号が供給される。そして、アクティブ化されたコンパレータ１４３において、信号レベルに応じた各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が参照信号ＲＡＰと比較される。そして、参照信号ＲＡＰのレベルが各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値と一致したときのタイミングが比較結果ＣＯＰ１として出力される。このとき、アクティブ化されたカウンタ１４６において、参照信号ＲＡＰのレベルが各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値と一致するまでカウント動作が実施される。そして、アクティブ化されたカウンタ１４６のカウント動作に基づいて、各垂直信号線１３２－１から１３２－４に接続された各画素１２０から読出された信号レベルの平均値がＡＤ変換される。 Next, D-phase binning/D-phase AD is performed (K16). At this time, after the selection signal ΦSEL falls (t17), the opening/closing signal ΦCn* rises. When the opening/closing signal ΦCn* rises, the connection switches 151 connected to each of the vertical signal lines 132-1 to 132-4 are turned on. Then, the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. . Then, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143. Further, the activated comparator 143 is supplied with a ramp signal as the reference signal RAP. Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the signal level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1. At this time, the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the signal level read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted.
　図８は、第１の実施の形態に係る信号読出し回路に適用されるコンパレータの構成例を示す図である。 FIG. 8 is a diagram showing a configuration example of a comparator applied to the signal readout circuit according to the first embodiment.
　同図において、コンパレータ１４３は、差動アンプ５０１、後段アンプ５０２、出力回路５０３およびＡＮＤ回路５０４を備える。後段アンプ５０２は、差動アンプ５０１の後段に接続され、出力回路５０３は、後段アンプ５０２の後段に接続されている。ＡＮＤ回路５０４は、出力回路５０３の後段に接続され、カウンタ１４６は、ＡＮＤ回路５０４の後段に接続されている。 In the figure, the comparator 143 includes a differential amplifier 501, a post-stage amplifier 502, an output circuit 503, and an AND circuit 504. The rear stage amplifier 502 is connected to the rear stage of the differential amplifier 501, and the output circuit 503 is connected to the rear stage of the rear stage amplifier 502. The AND circuit 504 is connected after the output circuit 503, and the counter 146 is connected after the AND circuit 504.
　差動アンプ５０１は、オートゼロ動作に基づいてコンパレータ入力ＣＩＮ１およびＣＩＮ２をバランスさせた上で、コンパレータ入力ＣＩＮ１およびＣＩＮ２の差分に応じた電圧を出力する。差動アンプ５０１は、ＰＭＯＳトランジスタ５１１、５２１、５５１、５６１および５９１と、ＮＭＯＳトランジスタ５３１、５４１、５７１および５８１とを備える。 The differential amplifier 501 balances the comparator inputs CIN1 and CIN2 based on the auto-zero operation, and then outputs a voltage according to the difference between the comparator inputs CIN1 and CIN2. Differential amplifier 501 includes PMOS transistors 511, 521, 551, 561, and 591, and NMOS transistors 531, 541, 571, and 581.
　ＰＭＯＳトランジスタ５１１とＮＭＯＳトランジスタ５３１とは互いに直列に接続されている。ＰＭＯＳトランジスタ５２１とＮＭＯＳトランジスタ５４１とは互いに直列に接続されている。各ＰＭＯＳトランジスタ５１１および５２１のソースは、電源電圧ＶＤＤＨに接続され、各ＰＭＯＳトランジスタ５１１および５２１のゲートは、ＰＭＯＳトランジスタ５２１のドレインに接続されている。このとき、ＰＭＯＳトランジスタ５１１および５２１は、カレントミラーを構成することができる。ＰＭＯＳトランジスタ５９１は、ＰＭＯＳトランジスタ５１１に並列に接続されている。 The PMOS transistor 511 and the NMOS transistor 531 are connected in series with each other. PMOS transistor 521 and NMOS transistor 541 are connected in series with each other. The sources of each PMOS transistor 511 and 521 are connected to power supply voltage VDDH, and the gate of each PMOS transistor 511 and 521 is connected to the drain of PMOS transistor 521. At this time, PMOS transistors 511 and 521 can constitute a current mirror. PMOS transistor 591 is connected in parallel to PMOS transistor 511.
　ＮＭＯＳトランジスタ５３１のゲートとドレインとの間には、ＰＭＯＳトランジスタ５５１が接続され、ＮＭＯＳトランジスタ５４１のゲートとドレインとの間には、ＰＭＯＳトランジスタ５６１が接続されている。ＮＭＯＳトランジスタ５７１および５８１は互いに直列に接続されている。各ＮＭＯＳトランジスタ５３１および５４１のソースは、ＮＭＯＳトランジスタ５７１および５８１の直列回路を介して接地されている。 A PMOS transistor 551 is connected between the gate and drain of the NMOS transistor 531, and a PMOS transistor 561 is connected between the gate and drain of the NMOS transistor 541. NMOS transistors 571 and 581 are connected in series with each other. The sources of each NMOS transistor 531 and 541 are grounded through a series circuit of NMOS transistors 571 and 581.
　各ＰＭＯＳトランジスタ５５１および５６１のゲートには、オートゼロ信号ＡＺＰが印加され、ＮＭＯＳトランジスタ５７１のゲートには、バイアス電圧ＢＩＡＳが印加される。ＮＭＯＳトランジスタ５７１は、バイアス電圧ＢＩＡＳに基づいて定電流源として動作することができる。ＮＭＯＳトランジスタ５８１のゲートには、制御信号ＸＡが印加される。ＰＭＯＳトランジスタ５９１のゲートには、制御信号ＸＢが印加される。 An auto-zero signal AZP is applied to the gate of each PMOS transistor 551 and 561, and a bias voltage BIAS is applied to the gate of the NMOS transistor 571. NMOS transistor 571 can operate as a constant current source based on bias voltage BIAS. A control signal XA is applied to the gate of the NMOS transistor 581. A control signal XB is applied to the gate of the PMOS transistor 591.
　後段アンプ５０２は、差動アンプ５０１の出力を増幅する。後段アンプ５０２は、ＰＭＯＳトランジスタ５１２、ＮＭＯＳトランジスタ５２２およびスイッチ５３２を備える。 The latter stage amplifier 502 amplifies the output of the differential amplifier 501. Post-stage amplifier 502 includes a PMOS transistor 512, an NMOS transistor 522, and a switch 532.
　ＰＭＯＳトランジスタ５１２とＮＭＯＳトランジスタ５２２とは互いに直列に接続されている。ＰＭＯＳトランジスタ５１２のソースは、電源電圧ＶＤＤＨに接続され、ＰＭＯＳトランジスタ５１２のゲートは、ＰＭＯＳトランジスタ５１１のドレインに接続されている。ＮＭＯＳトランジスタ５２２のゲートとドレインとの間には、スイッチ５３２が接続され、ＮＭＯＳトランジスタ５２２のソースは、接地されている。スイッチ５３２は、オートゼロ信号ＡＺＮに基づいて開閉する。 The PMOS transistor 512 and the NMOS transistor 522 are connected in series with each other. The source of PMOS transistor 512 is connected to power supply voltage VDDH, and the gate of PMOS transistor 512 is connected to the drain of PMOS transistor 511. A switch 532 is connected between the gate and drain of the NMOS transistor 522, and the source of the NMOS transistor 522 is grounded. Switch 532 opens and closes based on auto-zero signal AZN.
　出力回路５０３は、後段アンプ５０２の出力を論理値'０'または論理値'１'に変換する。出力回路５０３は、ＰＭＯＳトランジスタ５１３および５４３と、ＮＭＯＳトランジスタ５２３および５３３とを備える。 The output circuit 503 converts the output of the subsequent stage amplifier 502 into a logical value '0' or a logical value '1'. Output circuit 503 includes PMOS transistors 513 and 543 and NMOS transistors 523 and 533.
　ＰＭＯＳトランジスタ５１３およびＮＭＯＳトランジスタ５２３は互いに直列に接続され、ＮＭＯＳトランジスタ５２３および５３３は互いに直列に接続されている。ＰＭＯＳトランジスタ５１３および５４３のソースは、電源電圧ＶＤＤＬに接続され、ＮＭＯＳトランジスタ５３３のソースは、接地されている。ＰＭＯＳトランジスタ５４３のドレインは、ＰＭＯＳトランジスタ５１３のドレインに接続されている。電源電圧ＶＤＤＬは、電源電圧ＶＤＤＨよりも低くすることができる。ＰＭＯＳトランジスタ５４３のゲートとＮＭＯＳトランジスタ５２３のゲートには、ＰＭＯＳトランジスタ５１２のドレインに接続されている。ＰＭＯＳトランジスタ５１３のゲートとＮＭＯＳトランジスタ５３３のゲートには、制御信号ＸＣが印加される。 PMOS transistor 513 and NMOS transistor 523 are connected in series with each other, and NMOS transistors 523 and 533 are connected in series with each other. The sources of PMOS transistors 513 and 543 are connected to power supply voltage VDDL, and the source of NMOS transistor 533 is grounded. The drain of PMOS transistor 543 is connected to the drain of PMOS transistor 513. Power supply voltage VDDL can be lower than power supply voltage VDDH. The gate of the PMOS transistor 543 and the gate of the NMOS transistor 523 are connected to the drain of the PMOS transistor 512. A control signal XC is applied to the gate of the PMOS transistor 513 and the gate of the NMOS transistor 533.
　ＡＮＤ回路５０４の第１入力端子は、ＰＭＯＳトランジスタ５１３のドレインに接続されている。ＡＮＤ回路５０４の第２入力端子には、制御信号ＸＤが印加される。制御信号ＸＡ、ＸＢ、ＸＣおよびＸＤは、図６の制御信号ＣＴＬとしてコンパレータ１４３に入力される。 A first input terminal of the AND circuit 504 is connected to the drain of the PMOS transistor 513. A control signal XD is applied to a second input terminal of the AND circuit 504. Control signals XA, XB, XC, and XD are input to comparator 143 as control signal CTL in FIG.
　コンパレータ１４３をスタンバイ状態に設定する場合、制御信号ＸＡ、ＸＢ、ＸＣおよびＸＤは、ロウレベルに設定される。このとき、ＮＭＯＳトランジスタ５３３および５８１はオフされ、ＰＭＯＳトランジスタ５１２および５１３はオンされ、ＡＮＤ回路５０４からは論理値'０'が出力される。 When setting the comparator 143 to the standby state, control signals XA, XB, XC, and XD are set to low level. At this time, NMOS transistors 533 and 581 are turned off, PMOS transistors 512 and 513 are turned on, and AND circuit 504 outputs a logic value of '0'.
　コンパレータ１４３をアクティブ状態に設定する場合、制御信号ＸＡ、ＸＢ、ＸＣおよびＸＤは、ハイレベルに設定される。このとき、ＮＭＯＳトランジスタ５３３および５８１はオンされ、ＰＭＯＳトランジスタ５１２および５１３はオフされ、ＡＮＤ回路５０４からは出力回路５０３からの出力に応じて論理値'０'または'１'が出力される。 When setting the comparator 143 to the active state, control signals XA, XB, XC, and XD are set to high level. At this time, NMOS transistors 533 and 581 are turned on, PMOS transistors 512 and 513 are turned off, and AND circuit 504 outputs a logical value '0' or '1' depending on the output from output circuit 503.
　このとき、オートゼロ期間において、オートゼロ信号ＡＺＰに基づいて各ＰＭＯＳトランジスタ５５１および５６１がオンし、オートゼロ信号ＡＺＮに基づいてスイッチ５３２が閉じる。なお、各ＰＭＯＳトランジスタ５５１および５６１がオンした後にオフするタイミングは、スイッチ５３２が閉じた後に開くタイミングより遅くすることができる。このとき、ＰＭＯＳトランジスタ５１１および５２１のカレントミラー動作に基づいて、各ＰＭＯＳトランジスタ５５１および５６１に電流が流れる。そして、コンパレータ１４３の非反転入力および反転入力がバランスするように各ＤＣカットコンデンサ１４４および１４５に電荷が蓄積される。 At this time, during the auto-zero period, each PMOS transistor 551 and 561 is turned on based on the auto-zero signal AZP, and the switch 532 is closed based on the auto-zero signal AZN. Note that the timing at which each PMOS transistor 551 and 561 turns off after being turned on can be made later than the timing at which the switch 532 opens after closing. At this time, current flows through each PMOS transistor 551 and 561 based on the current mirror operation of PMOS transistors 511 and 521. Then, charges are accumulated in each of the DC cut capacitors 144 and 145 so that the non-inverting input and the inverting input of the comparator 143 are balanced.
　このように、上述の第１の実施の形態では、信号線リセットトランジスタ１４１が各垂直信号線１３２－１から１３２－４に接続されたカラムごとにサンプルホールドされた信号に基づいてビニングする。これにより、信号読出し回路の面積の増大を抑制しつつ、カラム方向のビニングを実施することが可能となるとともに、ビニング数を制限することなく、ビニング時のリニアリティを確保することができる。 In this way, in the first embodiment described above, the signal line reset transistor 141 performs binning based on the sampled and held signals for each column connected to each vertical signal line 132-1 to 132-4. This makes it possible to perform binning in the column direction while suppressing an increase in the area of the signal readout circuit, and to ensure linearity during binning without limiting the number of binnings.
　また、垂直信号線１３２－１から１３２－４ごとに設けられたＡＤ変換部をアクティブ制御することにより、ビニング処理時に動作が不要なＡＤ変換部をスタンバイ状態に設定することができ、低消費電力化を図ることができる。 In addition, by actively controlling the AD converters provided for each of the vertical signal lines 132-1 to 132-4, AD converters that do not need to operate during binning processing can be set to a standby state, reducing power consumption. It is possible to aim for
　また、各画素１２０からの信号読出し時に垂直信号線１３２をリセットすることで、各画素１２０からの信号読出し時に流れる画素電流に応じた電荷を容量１３３に蓄積することができる。このため、各画素１２０から読出された信号を検出するために、各画素１２０から読出された信号に応じた定電流を各垂直信号線１３２－１から１３２－４に流す必要がなくなり、各画素１２０からの信号読出し時の消費電流を低減することができる。 Furthermore, by resetting the vertical signal line 132 when reading signals from each pixel 120, charges corresponding to the pixel current flowing when reading signals from each pixel 120 can be accumulated in the capacitor 133. Therefore, in order to detect the signal read out from each pixel 120, there is no need to flow a constant current corresponding to the signal read out from each pixel 120 through each vertical signal line 132-1 to 132-4, and each pixel Current consumption when reading signals from 120 can be reduced.
　＜２．第２の実施の形態＞
　上述の第１の実施の形態では、信号線リセットトランジスタ１４１が各垂直信号線１３２－１から１３２－４に接続されたカラムごとにサンプルホールドされた信号に基づいてビニングした。この第２の実施の形態では、信号線リセットトランジスタ１４１を介してダイオード接続トランジスタが各垂直信号線１３２－１から１３２－４に接続されたカラムごとにサンプルホールドされた信号に基づいてビニングする。 <2. Second embodiment>
In the first embodiment described above, the signal line reset transistor 141 performs binning based on signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4. In this second embodiment, diode-connected transistors perform binning based on signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4 via a signal line reset transistor 141.
　図９は、第２の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。 FIG. 9 is a diagram showing a configuration example of a signal readout circuit for four columns according to the second embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路にダイオード接続トランジスタ１４２が追加されている。第２の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit has a diode-connected transistor 142 added to the signal readout circuit of the first embodiment described above. The other configuration of the signal readout circuit of the second embodiment is the same as that of the signal readout circuit of the first embodiment described above.
　ダイオード接続トランジスタ１４２は、垂直信号線１３２－１から１３２－４ごとに信号線リセットトランジスタ１４１に直列に接続される。ダイオード接続トランジスタ１４２は、例えば、ＭＯＳトランジスタを用いることができる。このとき、ダイオード接続トランジスタ１４２のゲートは、ダイオード接続トランジスタ１４２のドレインに接続される。ダイオード接続トランジスタ１４２のソースは接地される。ダイオード接続トランジスタ１４２のソースは、接地電位よりも高い電位に接続してもよい。ダイオード接続トランジスタ１４２は、０Ｖより高い電圧（例えば、０．５Ｖ）を生成し、信号線リセットトランジスタ１４１を介して各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４を０Ｖより高い電位に設定することができる。なお、ダイオード接続トランジスタ１４２は、特許請求の範囲に記載の信号線リセットレベル生成部の一例である。この第２の実施の形態の信号読出し回路のビニング時の動作は、第１の実施の形態の信号読出し回路のビニング時の動作と同様である。 A diode-connected transistor 142 is connected in series to a signal line reset transistor 141 for each vertical signal line 132-1 to 132-4. For example, a MOS transistor can be used as the diode-connected transistor 142. At this time, the gate of diode-connected transistor 142 is connected to the drain of diode-connected transistor 142. The source of diode-connected transistor 142 is grounded. The source of diode-connected transistor 142 may be connected to a potential higher than ground potential. The diode-connected transistor 142 generates a voltage higher than 0V (for example, 0.5V), and changes the potential VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 to a potential higher than 0V via the signal line reset transistor 141. Can be set to . Note that the diode-connected transistor 142 is an example of a signal line reset level generation section described in the claims. The operation of the signal readout circuit of the second embodiment during binning is similar to the operation of the signal readout circuit of the first embodiment during binning.
　このように、上述の第２の実施の形態では、信号線リセットトランジスタ１４１を介してダイオード接続トランジスタ１４２が各垂直信号線１３２－１から１３２－４に接続されたカラムごとにサンプルホールドされた信号に基づいてビニングする。これにより、各垂直信号線１３２－１から１３２－４のリセット時にダイオード接続トランジスタ１４２の順方向電圧に応じて各垂直信号線１３２－１から１３２－４の電位を持ち上げることができる。このため、Ｐ相ＶＳＬセトリング開始時の各垂直信号線１３２－１から１３２－４の電位を０Ｖより高くすることができ、セトリング時間を短縮することができる。 In this way, in the second embodiment described above, the diode-connected transistor 142 generates a signal sampled and held for each column connected to each vertical signal line 132-1 to 132-4 via the signal line reset transistor 141. Binning based on Thereby, the potential of each of the vertical signal lines 132-1 to 132-4 can be raised according to the forward voltage of the diode-connected transistor 142 when each of the vertical signal lines 132-1 to 132-4 is reset. Therefore, the potential of each vertical signal line 132-1 to 132-4 at the start of P-phase VSL settling can be made higher than 0V, and the settling time can be shortened.
　＜３．第３の実施の形態＞
　上述の第１の実施の形態では、カラムごとにサンプルホールドされた信号に基づいてビニングするとともに、サンプルホールドに用いられるカラムごとの容量１３３に対して接続スイッチ１５１を直列接続した。この第３の実施の形態では、カラムごとにサンプルホールドされた信号に基づいてビニングするとともに、サンプルホールドに用いられるカラムごとの容量に対して接続スイッチを並列接続する。 <3. Third embodiment>
In the first embodiment described above, binning is performed based on signals sampled and held for each column, and the connection switch 151 is connected in series with the capacitor 133 for each column used for sample and holding. In this third embodiment, binning is performed based on signals sampled and held for each column, and connection switches are connected in parallel to the capacitors for each column used for sample and holding.
　図１０は、第３の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。 FIG. 10 is a diagram showing a configuration example of a signal readout circuit for four columns according to the third embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路の接続スイッチ１５１に代えて、接続スイッチ１５２を備える。第３の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit includes a connection switch 152 in place of the connection switch 151 of the signal readout circuit of the first embodiment described above. The other configuration of the signal readout circuit of the third embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　接続スイッチ１５２は、互いに異なるカラムの垂直信号線１３２－１から１３２－４を接続する。このとき、接続スイッチ１５２は、各画素１２０から読出された信号のサンプルホールドに用いられるカラムごとの容量１３３に対して並列接続される。各接続スイッチ１５２は、開閉信号ΦＣｎに基づいてオン／オフすることができる。接続スイッチ１５２を用いる場合、カラム方向のビニング数は固定される。この第３の実施の形態の信号読出し回路のビニング時の動作は、カラム方向のビニング数が固定される点を除いて、第１の実施の形態の信号読出し回路のビニング時の動作と同様である。 The connection switch 152 connects the vertical signal lines 132-1 to 132-4 in different columns. At this time, the connection switch 152 is connected in parallel to the capacitor 133 for each column used for sampling and holding the signal read out from each pixel 120. Each connection switch 152 can be turned on/off based on the opening/closing signal ΦCn. When using the connection switch 152, the number of binning in the column direction is fixed. The operation of the signal readout circuit of the third embodiment during binning is similar to the operation of the signal readout circuit of the first embodiment during binning, except that the number of binnings in the column direction is fixed. be.
　このように、上述の第３の実施の形態では、信号線リセットトランジスタ１４１が各垂直信号線１３２－１から１３２－４に接続されたカラムごとにサンプルホールドされた信号に基づいてビニングする。これにより、信号読出し回路の面積の増大を抑制しつつ、カラム方向のビニングを実施することが可能となるとともに、ビニング数を制限することなく、ビニング時のリニアリティを確保することができる。 In this way, in the third embodiment described above, the signal line reset transistor 141 performs binning based on the signal sampled and held for each column connected to each vertical signal line 132-1 to 132-4. This makes it possible to perform binning in the column direction while suppressing an increase in the area of the signal readout circuit, and to ensure linearity during binning without limiting the number of binnings.
　＜４．第４の実施の形態＞
　上述の第１の実施の形態では、カラムごとにサンプルホールドされた信号に基づいてカラム方向にビニングした。この第４の実施の形態では、カラムごとにサンプルホールドされた信号に基づいてカラム方向およびロウ方向にビニングする。 <4. Fourth embodiment>
In the first embodiment described above, binning is performed in the column direction based on signals sampled and held for each column. In this fourth embodiment, binning is performed in the column direction and row direction based on signals sampled and held for each column.
　図１１は、第４の実施の形態に係る２カラム分の信号読出し回路の構成例を示す図である。 FIG. 11 is a diagram showing a configuration example of a signal readout circuit for two columns according to the fourth embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路の画素１２０に代えて、セル１３０を備える。また、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路にビニング線１４０が追加されている。第４の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit includes a cell 130 in place of the pixel 120 of the signal readout circuit of the first embodiment described above. Further, in this signal readout circuit, a binning line 140 is added to the signal readout circuit of the first embodiment described above. The other configuration of the signal readout circuit of the fourth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　セル１３０は、ロウ方向およびカラム方向にマトリックス状に配置される。セル１３０は、カラムごとに垂直信号線１３２－１および１３２－２に接続される。セル１３０は、上述の第１の実施の形態のフォトダイオード１２１および転送トランジスタ１２２に代えて、フォトダイオード１２１－１から１２１－４、転送トランジスタ１２２－１から１２２－４およびビニングトランジスタ１２７を備える。第４の実施の形態のセル１３０のそれ以外の構成は、上述の第１の実施の形態の画素１２０の構成と同様である。 The cells 130 are arranged in a matrix in the row and column directions. Cells 130 are connected to vertical signal lines 132-1 and 132-2 for each column. The cell 130 includes photodiodes 121-1 to 121-4, transfer transistors 122-1 to 122-4, and a binning transistor 127 in place of the photodiode 121 and transfer transistor 122 of the first embodiment described above. The other configuration of the cell 130 of the fourth embodiment is similar to the configuration of the pixel 120 of the first embodiment described above.
　各フォトダイオード１２１－１から１２１－４は、２行×２列に配置することができる。各フォトダイオード１２１－１から１２１－４は、転送トランジスタ１２２－１から１２２－４をそれぞれ介し、フローティングディフュージョン１２６に接続されている。各転送トランジスタ１２２－１から１２２－４のゲートには、転送信号ΦＴＧ１～ΦＴＧ４が印加される。この転送信号ΦＴＧ１～ΦＴＧ４の印加タイミングを制御することにより、各フォトダイオード１２１－１から１２１－４より個別に信号を読み出してもよいし、各フォトダイオード１２１－１から１２１－４より信号をビニングして読み出してもよい。各フォトダイオード１２１－１から１２１－４についての容量負荷読出し動作は、上述の第１の実施の形態のフォトダイオード１２１についての容量負荷読出し動作と同様である。 Each photodiode 121-1 to 121-4 can be arranged in two rows and two columns. Each of the photodiodes 121-1 to 121-4 is connected to the floating diffusion 126 via transfer transistors 122-1 to 122-4, respectively. Transfer signals ΦTG1 to ΦTG4 are applied to the gates of each of the transfer transistors 122-1 to 122-4. By controlling the application timing of these transfer signals ΦTG1 to ΦTG4, signals can be read out individually from each photodiode 121-1 to 121-4, or signals can be binned from each photodiode 121-1 to 121-4. You can also read it by The capacitive load readout operation for each photodiode 121-1 to 121-4 is similar to the capacitive load readout operation for the photodiode 121 of the first embodiment described above.
　ビニングトランジスタ１２７は、フローティングディフュージョン１２６とビニング線１４０との間にセル１３０ごとに接続される。ビニングトランジスタ１２７は、ＭＯＳトランジスタでもよい。ビニングトランジスタ１２７のゲートには、ビニング信号ΦＢＮがセル１３０ごとに印加される。 The binning transistor 127 is connected between the floating diffusion 126 and the binning line 140 for each cell 130. Binning transistor 127 may be a MOS transistor. A binning signal ΦBN is applied to the gate of the binning transistor 127 for each cell 130.
　各セル１３０から個別に信号を読出す場合、ビニング信号ΦＢＮはロウレベルに設定され、各セル１３０のビニングトランジスタ１２７はオフされる。 When reading signals from each cell 130 individually, the binning signal ΦBN is set to low level and the binning transistor 127 of each cell 130 is turned off.
　一方、各セル１３０の信号をロウ方向にビニングして読出す場合、ビニング信号ΦＢＮはハイレベルに設定され、各セル１３０のビニングトランジスタ１２７はオンされる。この第４の実施の形態の信号読出し回路のロウ方向およびカラム方向のビニング時の動作は、各セル１３０のビニングトランジスタ１２７はオンされる点以外は、第１の実施の形態の信号読出し回路のビニング時の動作と同様である。 On the other hand, when the signal of each cell 130 is binned and read in the row direction, the binning signal ΦBN is set to a high level and the binning transistor 127 of each cell 130 is turned on. The operation of the signal readout circuit of the fourth embodiment during binning in the row and column directions is similar to that of the signal readout circuit of the first embodiment, except that the binning transistor 127 of each cell 130 is turned on. The operation is similar to that during binning.
　例えば、各フォトダイオード１２１－１から１２１－４の信号を３２行×２列分だけ加算平均するとともに、１６カラム分のセル１３０の信号を容量加算平均するものとする。このとき、アクティブ化されるＡＤ変換部のカラム数は、全画素個別読出しに対して１／１６にすることができ、低消費電力化を図ることができる。 For example, it is assumed that the signals of each photodiode 121-1 to 121-4 are added and averaged for 32 rows by 2 columns, and the signals of the cells 130 for 16 columns are added and averaged by capacitance. At this time, the number of columns of the AD converter to be activated can be reduced to 1/16 of the individual readout of all pixels, and power consumption can be reduced.
　このように、上述の第４の実施の形態では、互いに異なるロウのセル１３０を互いに接続するビニングトランジスタ１２７を各セル１３０に設ける。これにより、カラム方向だけでなくロウ方向にもビニングすることができ、ロウ方向の空間解像度の低下を抑制しつつ、ビニング数を増大させることが可能となる。 In this manner, in the fourth embodiment described above, each cell 130 is provided with a binning transistor 127 that connects cells 130 in different rows to each other. As a result, binning can be performed not only in the column direction but also in the row direction, and it is possible to increase the number of binning operations while suppressing a decrease in spatial resolution in the row direction.
　＜５．第５の実施の形態＞
　上述の第１の実施の形態では、各垂直信号線１３２－１から１３２－４に接続されたカラムごとにサンプルホールドされた信号の平均値をコンパレータ１４３に入力した。この第５の実施の形態では、各垂直信号線１３２－１から１３２－４に接続されたカラムごとにサンプルホールドされた信号の平均値を、アンプ１６１を介してコンパレータ１４３に入力する。 <5. Fifth embodiment>
In the first embodiment described above, the average value of the signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4 is input to the comparator 143. In the fifth embodiment, the average value of signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4 is inputted to a comparator 143 via an amplifier 161.
　図１２は、第５の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。 FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to the fifth embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路にアンプ１６１が追加されている。第５の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit has an amplifier 161 added to the signal readout circuit of the first embodiment described above. The rest of the configuration of the signal readout circuit of the fifth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　アンプ１６１は、各垂直信号線１３２－１から１３２－４を介してコンパレータ１４３に伝送される信号をカラムごとに増幅する。アンプ１６１は、垂直信号線１３２－１から１３２－４ごとに設けられる。各アンプ１６１は、ＤＣカットコンデンサ１４４をそれぞれ介して各コンパレータ１４３の反転入力端子に接続される。アンプ１６１には、制御信号ＣＴＬが入力される。このとき、コンパレータ１４３およびカウンタ１４６のアクティブ化に対応してそれらと同一カラムのアンプ１６１をアクティブ化することができる。また、コンパレータ１４３およびカウンタ１４６のスタンバイ状態に対応してそれらと同一カラムのアンプ１６１をスタンバイ状態に設定することができる。 The amplifier 161 amplifies the signals transmitted to the comparator 143 via each vertical signal line 132-1 to 132-4 for each column. An amplifier 161 is provided for each vertical signal line 132-1 to 132-4. Each amplifier 161 is connected to an inverting input terminal of each comparator 143 via a DC cut capacitor 144, respectively. A control signal CTL is input to the amplifier 161. At this time, in response to the activation of the comparator 143 and the counter 146, the amplifier 161 in the same column as the comparator 143 and the counter 146 can be activated. Furthermore, in response to the standby state of the comparator 143 and the counter 146, the amplifier 161 in the same column as these can be set to the standby state.
　このように、上述の第５の実施の形態では、各垂直信号線１３２－１から１３２－４ごとにアンプ１６１を設けるとともに、各アンプ１６１に制御信号ＣＴＬを入力する。これにより、ビニング時の消費電力の増大を抑制しつつ、コンパレータ１４３に伝送される信号を増幅することができる。 In this manner, in the fifth embodiment described above, an amplifier 161 is provided for each vertical signal line 132-1 to 132-4, and a control signal CTL is input to each amplifier 161. Thereby, the signal transmitted to the comparator 143 can be amplified while suppressing an increase in power consumption during binning.
　＜６．第６の実施の形態＞
　上述の第３の実施の形態では、各垂直信号線１３２－１から１３２－４を介して伝送される信号をカラムごとにサンプルホールドさせるサンプルホールドスイッチとして選択トランジスタ１２５を用いた。この第６の実施の形態では、各垂直信号線１３２－１から１３２－４を介して伝送される信号をカラムごとにサンプルホールドさせるサンプルホールドスイッチを各垂直信号線１３２－１から１３２－４に設ける。 <6. Sixth embodiment>
In the third embodiment described above, the selection transistor 125 is used as a sample and hold switch that samples and holds the signals transmitted via each vertical signal line 132-1 to 132-4 for each column. In this sixth embodiment, each vertical signal line 132-1 to 132-4 is provided with a sample hold switch that samples and holds signals transmitted via each vertical signal line 132-1 to 132-4 for each column. establish.
　図１３は、第６の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。 FIG. 13 is a diagram showing a configuration example of a signal readout circuit for four columns according to the sixth embodiment.
　同図において、この信号読出し回路は、上述の第３の実施の形態の信号読出し回路にサンプルホールドスイッチ１５３と、ドライバ３０１および３０２が追加されている。第６の実施の形態の信号読出し回路のそれ以外の構成は、上述の第３の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit has a sample and hold switch 153 and drivers 301 and 302 added to the signal readout circuit of the third embodiment described above. The rest of the configuration of the signal readout circuit of the sixth embodiment is similar to the configuration of the signal readout circuit of the third embodiment described above.
　サンプルホールドスイッチ１５３は、各垂直信号線１３２－１から１３２－４を介して伝送される信号をカラムごとに各容量１５３にサンプルホールドさせる。サンプルホールドスイッチ１５３は、各垂直信号線１３２－１から１３２－４に設けられる。各サンプルホールドスイッチ１５３は、サンプルホールド信号ΦＶＳに基づいてオン／オフされる。各サンプルホールドスイッチ１５３は、ＭＯＳトランジスタでもよい。 The sample and hold switch 153 causes each capacitor 153 to sample and hold the signals transmitted via the vertical signal lines 132-1 to 132-4 for each column. A sample hold switch 153 is provided on each vertical signal line 132-1 to 132-4. Each sample hold switch 153 is turned on/off based on the sample hold signal ΦVS. Each sample hold switch 153 may be a MOS transistor.
　各ドライバ３０１および３０２は、サンプルホールドスイッチ１５３をロウ方向の両側から駆動する。各ドライバ３０１および３０２は、カラムごとに設けられたサンプルホールドスイッチ１５３で共有することができる。 Each driver 301 and 302 drives the sample hold switch 153 from both sides in the row direction. Each driver 301 and 302 can be shared by a sample hold switch 153 provided for each column.
　図１４は、第６の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。なお、同図では、ビニング読出し時の各部の波形の一例を示した。 FIG. 14 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the sixth embodiment. In addition, in the figure, an example of the waveform of each part at the time of binning readout is shown.
　同図において、第６の実施の形態のビニング読出し時の動作は、サンプルホールド信号ΦＶＳが追加される点を除いて、上述の第１の実施の形態のビニング読出し時の動作と同様である。 In the figure, the binning read operation of the sixth embodiment is similar to the binning read operation of the first embodiment described above, except that a sample and hold signal ΦVS is added.
　サンプルホールド信号ΦＶＳは、画素リセット／ＶＳＬリセット（Ｋ１１）において、画素リセット信号ΦＰＲＴの立ち上がりと同時に立ち上がる（ｔ１１）。また、サンプルホールド信号ΦＶＳは、Ｐ相ＶＳＬセトリング／Ｐ相ＶＳＬサンプルホールド（Ｋ１２）において、選択信号ΦＳＥＬが立ち下がる前に立ち下がる。 The sample hold signal ΦVS rises (t11) at the same time as the pixel reset signal ΦPRT rises in the pixel reset/VSL reset (K11). Further, the sample hold signal ΦVS falls before the selection signal ΦSEL falls in P-phase VSL settling/P-phase VSL sample hold (K12).
　さらに、サンプルホールド信号ΦＶＳは、転送／ＶＳＬリセット（Ｋ１４）において、転送信号ΦＴＧの立ち上がりと同時に立ち上がる（ｔ１４）。また、サンプルホールド信号ΦＶＳは、Ｄ相ＶＳＬセトリング／Ｄ相ＶＳＬサンプルホールド（Ｋ１５）において、選択信号ΦＳＥＬが立ち下がる前に立ち下がる。 Furthermore, the sample hold signal ΦVS rises simultaneously with the rise of the transfer signal ΦTG in the transfer/VSL reset (K14) (t14). Further, the sample hold signal ΦVS falls before the selection signal ΦSEL falls in D-phase VSL settling/D-phase VSL sample hold (K15).
　このように、上述の第６の実施の形態では、各垂直信号線１３２－１から１３２－４を介して伝送される信号をカラムごとにサンプルホールドさせるサンプルホールドスイッチ１５３を設ける。これにより、ビニング時のリニアリティを確保しつつ、カラム方向のビニングを実施することが可能となる。 In this manner, in the sixth embodiment described above, the sample and hold switch 153 is provided to sample and hold the signals transmitted via each vertical signal line 132-1 to 132-4 for each column. This makes it possible to perform binning in the column direction while ensuring linearity during binning.
　また、サンプルホールドスイッチ１５３をロウ方向の両側から駆動するドライバ３０１および３０２を設ける。これにより、サンプルホールドスイッチ１５３を駆動するドライバ３０１および３０２をロウごとに設けることなく、各カラムのサンプルホールドスイッチ１５３の駆動力を増大させることができる。このため、駆動力の面内差を低減することが可能となり、固定パターンノイズを低減することが可能となるとともに、ドライバ３０１および３０２の配置に必要な面積の増大を抑制することができる。 Additionally, drivers 301 and 302 are provided to drive the sample and hold switch 153 from both sides in the row direction. Thereby, the driving force of the sample and hold switches 153 in each column can be increased without providing drivers 301 and 302 for each row to drive the sample and hold switches 153. Therefore, it is possible to reduce the in-plane difference in driving force, it is possible to reduce fixed pattern noise, and it is also possible to suppress an increase in the area required for arranging the drivers 301 and 302.
　＜７．第７の実施の形態＞
　上述の第１の実施の形態では、アクティブ化されたカラムおよび非アクティブ化されたカラムについて、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４を、ＤＣカットコンデンサ１４４をそれぞれ介して各コンパレータ１４３に入力した。この第７の実施の形態では、非アクティブ化されたカラムについては、ＤＣカットコンデンサ１４４の接続先をコンパレータ入力から接地に切り替える。 <7. Seventh embodiment>
In the first embodiment described above, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are connected to the activated columns and the inactivated columns via the DC cut capacitors 144, respectively. was input to each comparator 143. In this seventh embodiment, for a deactivated column, the connection destination of the DC cut capacitor 144 is switched from the comparator input to the ground.
　図１５は、第７の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。 FIG. 15 is a diagram showing a configuration example of a signal readout circuit for four columns according to the seventh embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路に切替スイッチ１５４および１５５が追加されている。第７の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit has changeover switches 154 and 155 added to the signal readout circuit of the first embodiment described above. The other configuration of the signal readout circuit of the seventh embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　各カラムのＤＣカットコンデンサ１４４の第１容量電極は、各垂直信号線１３２－１から１３２－４に接続される。切替スイッチ１５４および１５５は、カラムごとに設けられる。切替スイッチ１５４は、各カラムのＤＣカットコンデンサ１４４の第２容量電極と、各コンパレータ１４３の反転入力端子との間に接続される。切替スイッチ１５５は、各カラムのＤＣカットコンデンサ１４４の第２容量電極と、接地との間に接続される。 The first capacitive electrode of the DC cut capacitor 144 in each column is connected to each vertical signal line 132-1 to 132-4. Changeover switches 154 and 155 are provided for each column. The changeover switch 154 is connected between the second capacitance electrode of the DC cut capacitor 144 in each column and the inverting input terminal of each comparator 143. The changeover switch 155 is connected between the second capacitance electrode of the DC cut capacitor 144 in each column and the ground.
　そして、アクティブ化されたカラムについては、切替スイッチ１５４はオンされるとともに、切替スイッチ１５５はオフされる。一方、非アクティブ化されたカラムについては、切替スイッチ１５４はオフされるとともに、切替スイッチ１５５はオンされる。このとき、切替スイッチ１５４および１５５は、アクティブ化されるカラムと非アクティブ化されるカラムとに分けて制御される。 Then, for the activated column, the changeover switch 154 is turned on, and the changeover switch 155 is turned off. On the other hand, for the deactivated column, the changeover switch 154 is turned off and the changeover switch 155 is turned on. At this time, the changeover switches 154 and 155 are controlled separately for activated columns and deactivated columns.
　例えば、各垂直信号線１３２－１から１３２－４に対応して設けられたコンパレータ１４３およびカウンタ１４６のうち垂直信号線１３２－１に対応して設けられたコンパレータ１４３およびカウンタ１４６がアクティブ化されるものとする。このとき、垂直信号線１３２－１に接続された切替スイッチ１５４はオンされるとともに、切替スイッチ１５５はオフされる。一方、各垂直信号線１３２－２から１３２－４に接続された切替スイッチ１５４はオフされるとともに、切替スイッチ１５５はオンされる。また、ビニング時には、開閉信号ΦＣｎ１からΦＣｎ４はオンされる。このため、各垂直信号線１３２－２から１３２－４に接続されたＤＣカットコンデンサ１４４の容量が、垂直信号線１３２－１の容量１３３に付加される。 For example, among the comparators 143 and counters 146 provided corresponding to the vertical signal lines 132-1 to 132-4, the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 are activated. shall be taken as a thing. At this time, the changeover switch 154 connected to the vertical signal line 132-1 is turned on, and the changeover switch 155 is turned off. On the other hand, the changeover switch 154 connected to each vertical signal line 132-2 to 132-4 is turned off, and the changeover switch 155 is turned on. Furthermore, during binning, the open/close signals ΦCn1 to ΦCn4 are turned on. Therefore, the capacitance of the DC cut capacitor 144 connected to each vertical signal line 132-2 to 132-4 is added to the capacitance 133 of the vertical signal line 132-1.
　このように、上述の第７の実施の形態では、非アクティブ化されたカラムについては、ＤＣカットコンデンサ１４４の接続先をコンパレータ入力から接地に切り替える。これにより、アクティブ化されたカラムの垂直信号線１３２－１に付加される容量を増大させることができ、ｋＴＣノイズを低減することができる。 In this manner, in the seventh embodiment described above, for a deactivated column, the connection destination of the DC cut capacitor 144 is switched from the comparator input to the ground. Thereby, the capacitance added to the vertical signal line 132-1 of the activated column can be increased, and kTC noise can be reduced.
　＜８．第８の実施の形態＞
　上述の第１の実施の形態では、容量負荷読出しに基づいてビニングを実施した。この第８の実施の形態では、定電流読出しに基づいてビニングを実施する。 <8. Eighth embodiment>
In the first embodiment described above, binning was performed based on capacitive load reading. In this eighth embodiment, binning is performed based on constant current readout.
　図１６は、第８の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。 FIG. 16 is a diagram showing a configuration example of a signal readout circuit for four columns according to the eighth embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路の信号線リセットトランジスタ１４１に代えて、電流源４０１を備える。また、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路に接続スイッチ４０２と、サンプルホールドスイッチ４０３および４０４と、容量４０５とが追加されている。第８の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit includes a current source 401 in place of the signal line reset transistor 141 of the signal readout circuit of the first embodiment described above. Further, this signal readout circuit has a connection switch 402, sample and hold switches 403 and 404, and a capacitor 405 added to the signal readout circuit of the first embodiment described above. The rest of the configuration of the signal readout circuit of the eighth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　電流源４０１は、カラムごとに設けることができる。各電流源４０１は、垂直信号線１３２－１から１３２－４に接続される。電流源４０１は、ＭＯＳトランジスタでもよい。 The current source 401 can be provided for each column. Each current source 401 is connected to vertical signal lines 132-1 to 132-4. Current source 401 may be a MOS transistor.
　サンプルホールドスイッチ４０３および４０４は、各垂直信号線１３２－１から１３２－４を介して伝送される信号をカラムごとに容量４０５にサンプルホールドさせる。サンプルホールドスイッチ４０３および４０４は、各垂直信号線１３２－１から１３２－４に設けられる。このとき、各サンプルホールドスイッチ４０３は、垂直信号線１３２－１から１３２－４にそれぞれ直列に接続される。各サンプルホールドスイッチ４０４は、各垂直信号線１３２－１から１３２－４と容量４０５との間に接続される。各サンプルホールドスイッチ４０３は、サンプルホールド信号ΦＶＳに基づいてオン／オフされる。各サンプルホールドスイッチ４０４は、サンプルホールド信号ΦＳに基づいてオン／オフされる。各サンプルホールドスイッチ４０３および４０４は、ＭＯＳトランジスタでもよい。 The sample and hold switches 403 and 404 cause the capacitor 405 to sample and hold the signals transmitted via the vertical signal lines 132-1 to 132-4 for each column. Sample and hold switches 403 and 404 are provided on each vertical signal line 132-1 to 132-4. At this time, each sample hold switch 403 is connected in series to the vertical signal lines 132-1 to 132-4, respectively. Each sample hold switch 404 is connected between each vertical signal line 132-1 to 132-4 and a capacitor 405. Each sample hold switch 403 is turned on/off based on the sample hold signal ΦVS. Each sample hold switch 404 is turned on/off based on the sample hold signal ΦS. Each sample and hold switch 403 and 404 may be a MOS transistor.
　容量４０５は、カラムごとに設けることができる。各容量４０５は、サンプルホールドスイッチ４０４をそれぞれ介して各垂直信号線１３２－１から１３２－４に接続される。容量４０５は、各画素１２０から読出された信号のカラムごとのサンプルホールドに用いることができる。 The capacity 405 can be provided for each column. Each capacitor 405 is connected to each vertical signal line 132-1 to 132-4 via a sample and hold switch 404, respectively. The capacitor 405 can be used to sample and hold signals read out from each pixel 120 for each column.
　接続スイッチ４０２は、互いに異なるカラムの垂直信号線１３２－１から１３２－４を接続する。このとき、接続スイッチ４０２は、各画素１２０から読出された信号のサンプルホールドに用いられるカラムごとの容量４０５に対して並列接続される。各接続スイッチ４０２は、ＭＯＳトランジスタでもよい。各接続スイッチ４０２は、開閉信号ΦＣｎに基づいてオン／オフされる。 The connection switch 402 connects the vertical signal lines 132-1 to 132-4 in different columns. At this time, the connection switch 402 is connected in parallel to the capacitor 405 for each column used to sample and hold the signal read out from each pixel 120. Each connection switch 402 may be a MOS transistor. Each connection switch 402 is turned on/off based on the opening/closing signal ΦCn.
　図１７は、第８の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。なお、同図では、ビニング読出し時の各部の波形の一例を示した。 FIG. 17 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the eighth embodiment. In addition, in the figure, an example of the waveform of each part at the time of binning read-out is shown.
　同図において、定電流読出しでは、画素リセットが実施される（Ｋ２１）。このとき、各画素１２０の画素リセット信号ΦＰＲＴが立ち上がり（ｔ２１）、各画素１２０のリセットトランジスタ１２３がオンして各画素１２０のフローティングディフュージョン１２６がリセットされる。また、各画素１２０の選択信号ΦＳＥＬが立ち上がり（ｔ２１）、各画素１２０の選択トランジスタ１２５がオンする。このとき、電源電位Ｖｄｄが各画素１２０の増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が設定される。 In the figure, pixel reset is performed in constant current readout (K21). At this time, the pixel reset signal ΦPRT of each pixel 120 rises (t21), the reset transistor 123 of each pixel 120 is turned on, and the floating diffusion 126 of each pixel 120 is reset. Further, the selection signal ΦSEL of each pixel 120 rises (t21), and the selection transistor 125 of each pixel 120 is turned on. At this time, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the source follower operation when the power supply potential Vdd is applied to the gate of the amplification transistor 124 of each pixel 120.
　また、サンプルホールド信号ΦＳが立ち上がり（ｔ２１）、各垂直信号線１３２－１から１３２－４に接続されたサンプルホールドスイッチ４０４がそれぞれオンする。このとき、カラムごとに設けられた容量４０５は、サンプルホールドスイッチ４０４をそれぞれ介して各垂直信号線１３２－１から１３２－４に接続される。 Furthermore, the sample and hold signal ΦS rises (t21), and the sample and hold switches 404 connected to each of the vertical signal lines 132-1 to 132-4 are turned on. At this time, the capacitors 405 provided for each column are connected to the vertical signal lines 132-1 to 132-4 via the sample and hold switches 404, respectively.
　また、サンプルホールド信号ΦＶＳが立ち上がり（ｔ２１）、各垂直信号線１３２－１から１３２－４に接続されたサンプルホールドスイッチ４０３がそれぞれオンする。このとき、カラムごとに設けられた容量４０５は、垂直信号線１３２－１から１３２－４をそれぞれ介してカラムごとに画素１２０に接続される。 Furthermore, the sample and hold signal ΦVS rises (t21), and the sample and hold switches 403 connected to each of the vertical signal lines 132-1 to 132-4 are turned on. At this time, the capacitors 405 provided for each column are connected to the pixels 120 for each column via the vertical signal lines 132-1 to 132-4, respectively.
　また、オートゼロ信号ＡＺが立ち上がり（ｔ２１）、各垂直信号線１３２－１から１３２－４に接続されたコンパレータ１４３のオートゼロ動作がアクティブ化される。このとき、各垂直信号線１３２－１から１３２－４に接続されたコンパレータ１４３の非反転入力および反転入力がバランスするように各ＤＣカットコンデンサ１４４および１４５に蓄積される電荷が制御される。 Furthermore, the auto zero signal AZ rises (t21), and the auto zero operation of the comparator 143 connected to each vertical signal line 132-1 to 132-4 is activated. At this time, the charge accumulated in each DC cut capacitor 144 and 145 is controlled so that the non-inverting input and the inverting input of comparator 143 connected to each vertical signal line 132-1 to 132-4 are balanced.
　次に、Ｐ相ＶＳＬセトリング／Ｐ相ＶＳＬサンプルホールドが実施される（Ｋ２２）。このとき、各画素１２０の画素リセット信号ΦＰＲＴが立ち下がり（ｔ２２）、各画素１２０のリセットトランジスタ１２３がオフする。そして、各画素１２０のフローティングディフュージョン１２６のリセットレベルが各画素１２０の増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が設定される。そして、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４に応じた電荷がカラムごとに容量４０５にサンプルホールドされる。その後、サンプルホールド信号ΦＶＳが立ち下がる。 Next, P-phase VSL settling/P-phase VSL sample and hold is performed (K22). At this time, the pixel reset signal ΦPRT of each pixel 120 falls (t22), and the reset transistor 123 of each pixel 120 is turned off. Based on the source follower operation when the reset level of the floating diffusion 126 of each pixel 120 is applied to the gate of the amplification transistor 124 of each pixel 120, the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are applied. is set. Charges corresponding to the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are sampled and held in the capacitor 405 for each column. After that, the sample and hold signal ΦVS falls.
　次に、Ｐ相ビニング／Ｐ相ＡＤが実施される（Ｋ２３）。このとき、開閉信号ΦＣｎが立ち上がり（ｔ２３）、オートゼロ信号ＡＺが立ち下がる。開閉信号ΦＣｎが立ち上がると、各垂直信号線１３２－１から１３２－４に接続された接続スイッチ４０２がオンする。そして、各垂直信号線１３２－１から１３２－４にそれぞれ付加された容量４０５に蓄積された電荷がビニングされ、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が平均化される。そして、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が各コンパレータ１４３に入力される。また、例えば、各垂直信号線１３２－１から１３２－４に対応して設けられたコンパレータ１４３およびカウンタ１４６のうち垂直信号線１３２－１に対応して設けられたコンパレータ１４３およびカウンタ１４６のみがアクティブ化される。また、アクティブ化されたコンパレータ１４３には、参照信号ＲＡＰとしてランプ信号が供給される。そして、アクティブ化されたコンパレータ１４３において、リセットレベルに応じた各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が参照信号ＲＡＰと比較される。そして、参照信号ＲＡＰのレベルが各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値と一致したときのタイミングが比較結果ＣＯＰ１として出力される。このとき、アクティブ化されたカウンタ１４６において、参照信号ＲＡＰのレベルが各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値と一致するまでカウント動作が実施される。そして、アクティブ化されたカウンタ１４６のカウント動作に基づいて、各垂直信号線１３２－１から１３２－４に接続された各画素１２０から読出されたリセットレベルの平均値がＡＤ変換される。その後、開閉信号ΦＣｎが立ち下がる。 Next, P-phase binning/P-phase AD is performed (K23). At this time, the opening/closing signal ΦCn rises (t23) and the auto-zero signal AZ falls. When the opening/closing signal ΦCn rises, the connection switches 402 connected to each of the vertical signal lines 132-1 to 132-4 are turned on. Then, the charges accumulated in the capacitors 405 added to each vertical signal line 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are averaged. . Then, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143. Further, for example, among the comparators 143 and counters 146 provided corresponding to the vertical signal lines 132-1 to 132-4, only the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 are active. be converted into Further, the activated comparator 143 is supplied with a ramp signal as the reference signal RAP. Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the reset level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1. At this time, the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the reset levels read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted. After that, the opening/closing signal ΦCn falls.
　次に、転送が実施される（Ｋ２４）。このとき、各画素１２０の転送信号ΦＴＧが立ち上がり（ｔ２４）、各画素１２０の転送トランジスタ１２２がオンして各画素１２０のフォトダイオード１２１に蓄積された電荷が各画素１２０のフローティングディフュージョン１２６に転送される。また、各画素１２０のフォトダイオード１２１のカソード電位が各画素１２０の増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が設定される。 Next, transfer is performed (K24). At this time, the transfer signal ΦTG of each pixel 120 rises (t24), the transfer transistor 122 of each pixel 120 is turned on, and the charge accumulated in the photodiode 121 of each pixel 120 is transferred to the floating diffusion 126 of each pixel 120. Ru. Furthermore, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are adjusted based on the source follower operation when the cathode potential of the photodiode 121 of each pixel 120 is applied to the gate of the amplification transistor 124 of each pixel 120. is set.
　また、サンプルホールド信号ΦＶＳが立ち上がり（ｔ２４）、各垂直信号線１３２－１から１３２－４に接続されたサンプルホールドスイッチ４０３がそれぞれオンする。このとき、カラムごとに設けられた容量４０５は、垂直信号線１３２－１から１３２－４をそれぞれ介してカラムごとに画素１２０に接続される。 Furthermore, the sample and hold signal ΦVS rises (t24), and the sample and hold switches 403 connected to each of the vertical signal lines 132-1 to 132-4 are turned on. At this time, the capacitors 405 provided for each column are connected to the pixels 120 for each column via the vertical signal lines 132-1 to 132-4, respectively.
　次に、Ｄ相ＶＳＬセトリング／Ｄ相ＶＳＬサンプルホールドが実施される（Ｋ２５）。このとき、各画素１２０の転送信号ΦＴＧが立ち下がり（ｔ２５）、各画素１２０の転送トランジスタ１２２がオフする。そして、各画素１２０のフローティングディフュージョン１２６の信号レベルが各画素１２０の増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が設定される。そして、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４に応じた電荷がカラムごとに容量４０５にサンプルホールドされる。その後、サンプルホールド信号ΦＶＳが立ち下がる。 Next, D-phase VSL settling/D-phase VSL sample and hold is performed (K25). At this time, the transfer signal ΦTG of each pixel 120 falls (t25), and the transfer transistor 122 of each pixel 120 is turned off. Based on the source follower operation when the signal level of the floating diffusion 126 of each pixel 120 is applied to the gate of the amplification transistor 124 of each pixel 120, the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are applied. is set. Charges corresponding to the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are sampled and held in the capacitor 405 for each column. After that, the sample and hold signal ΦVS falls.
　次に、Ｄ相ビニング／Ｐ相ＡＤが実施される（Ｋ２６）。このとき、開閉信号ΦＣｎが立ち上がり（ｔ２６）、各垂直信号線１３２－１から１３２－４に接続された接続スイッチ４０２がオンする。そして、各垂直信号線１３２－１から１３２－４にそれぞれ付加された容量４０５に蓄積された電荷がビニングされ、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４が平均化される。そして、各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が各コンパレータ１４３に入力される。また、アクティブ化されたコンパレータ１４３には、参照信号ＲＡＰとしてランプ信号が供給される（ｔ２６－ｔ２７）。そして、アクティブ化されたコンパレータ１４３において、信号レベルに応じた各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値が参照信号ＲＡＰと比較される。そして、参照信号ＲＡＰのレベルが各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値と一致したときのタイミングが比較結果ＣＯＰ１として出力される。このとき、アクティブ化されたカウンタ１４６において、参照信号ＲＡＰのレベルが各垂直信号線１３２－１から１３２－４の電位ＶＳＬ１からＶＳＬ４の平均値と一致するまでカウント動作が実施される。そして、アクティブ化されたカウンタ１４６のカウント動作に基づいて、各垂直信号線１３２－１から１３２－４に接続された各画素１２０から読出された信号レベルの平均値がＡＤ変換される。その後、サンプルホールド信号ΦＳおよび開閉信号ΦＣｎが立ち下がり、各画素１２０の選択信号ΦＳＥＬが立ち下がる。 Next, D-phase binning/P-phase AD is performed (K26). At this time, the opening/closing signal ΦCn rises (t26), and the connection switches 402 connected to each of the vertical signal lines 132-1 to 132-4 are turned on. Then, the charges accumulated in the capacitors 405 added to each vertical signal line 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are averaged. . Then, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143. Further, a ramp signal is supplied to the activated comparator 143 as the reference signal RAP (t26-t27). Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the signal level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1. At this time, the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the signal level read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted. After that, the sample hold signal ΦS and the open/close signal ΦCn fall, and the selection signal ΦSEL of each pixel 120 falls.
　このように、上述の第８の実施の形態では、定電流読出しに基づいてビニングを実施する。これにより、容量負荷読出しに比べてセトリングにかかる時間を短縮することができる。 In this manner, in the eighth embodiment described above, binning is performed based on constant current readout. Thereby, the time required for settling can be reduced compared to capacitive load reading.
　＜９．第９の実施の形態＞
　上述の第２の実施の形態では、容量負荷読出しに基づいてビニングを実施した。この第９の実施の形態では、信号線リセットトランジスタ１４１とダイオード接続トランジスタ１４２との直列回路に並列に定電流トランジスタを接続し、定電流読出しと容量負荷読出しとを切替可能とする。 <9. Ninth embodiment>
In the second embodiment described above, binning was performed based on capacitive load reading. In the ninth embodiment, a constant current transistor is connected in parallel to a series circuit of a signal line reset transistor 141 and a diode-connected transistor 142, so that constant current reading and capacitive load reading can be switched.
　図１８は、第９の実施の形態に係る１カラム分の信号読出し回路の構成例を示すブロック図である。なお、同図では、１カラム分の信号読出し回路について示したが、他のカラムについても同様に構成することができる。 FIG. 18 is a block diagram showing a configuration example of a signal readout circuit for one column according to the ninth embodiment. Although the figure shows a signal readout circuit for one column, the same configuration can be applied to other columns as well.
　同図において、この信号読出し回路は、上述の第２の実施の形態の信号読出し回路にサンプルホールド回路２０１および定電流トランジスタ３０１が追加されている。第９の実施の形態の信号読出し回路のそれ以外の構成は、上述の第２の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit has a sample and hold circuit 201 and a constant current transistor 301 added to the signal readout circuit of the second embodiment described above. The other configuration of the signal readout circuit of the ninth embodiment is similar to the configuration of the signal readout circuit of the second embodiment described above.
　サンプルホールド回路２０１は、バイアス電圧Ｖｂをサンプルホールドし、定電流トランジスタ３０１のゲートに印加する。サンプルホールド回路２０１は、トランジスタ２１１およびコンデンサ２１２を備える。トランジスタ２１１は、ＭＯＳトランジスタでもよい。トランジスタ２１１のゲートには、サンプルホールド信号ΦＳＨが印加される。コンデンサ２１２は、トランジスタ２１１のソースとグランド電位との間に接続される。 The sample and hold circuit 201 samples and holds the bias voltage Vb and applies it to the gate of the constant current transistor 301. Sample and hold circuit 201 includes a transistor 211 and a capacitor 212. Transistor 211 may be a MOS transistor. A sample and hold signal ΦSH is applied to the gate of the transistor 211. Capacitor 212 is connected between the source of transistor 211 and ground potential.
　定電流トランジスタ３０１は、垂直信号線１３２－１に電気的に接続される。定電流トランジスタ３０１は、ＭＯＳトランジスタでもよい。定電流トランジスタ３０１のゲートは、サンプルホールド回路２０１の出力に接続される。 The constant current transistor 301 is electrically connected to the vertical signal line 132-1. Constant current transistor 301 may be a MOS transistor. The gate of constant current transistor 301 is connected to the output of sample hold circuit 201.
　ここで、容量負荷読出しでは、バイアス電圧Ｖｂは０Ｖに設定され、サンプルホールド信号ΦＳＨはハイレベルに設定される。この場合、定電流トランジスタ３０１はオフされ、定電流トランジスタ３０１には電流は流れない。このときの信号読出し回路の動作は、上述の第１の実施の形態の信号読出し回路の動作と同様である。 Here, in capacitive load reading, bias voltage Vb is set to 0V and sample hold signal ΦSH is set to high level. In this case, the constant current transistor 301 is turned off, and no current flows through the constant current transistor 301. The operation of the signal readout circuit at this time is similar to the operation of the signal readout circuit of the first embodiment described above.
　定電流読出しでは、ＡＤ変換時の横引きノイズを防止するため、トランジスタ２１１がオンしてバイアス電圧Ｖｂがサンプルホールドされる。そして、トランジスタ２１１がオフし、サンプルホールド回路２０１にサンプルホールドされたバイアス電圧Ｖｂが定電流トランジスタ３０１のゲートに印加される。この場合、定電流トランジスタ３０１はオンされ、定電流トランジスタ３０１には定電流が流れる。このときの信号読出し回路の動作は、上述の第８の実施の形態の信号読出し回路の動作と同様である。 In constant current readout, the transistor 211 is turned on and the bias voltage Vb is sampled and held in order to prevent horizontal scanning noise during AD conversion. Then, the transistor 211 is turned off, and the bias voltage Vb sampled and held by the sample and hold circuit 201 is applied to the gate of the constant current transistor 301. In this case, the constant current transistor 301 is turned on, and a constant current flows through the constant current transistor 301. The operation of the signal readout circuit at this time is similar to the operation of the signal readout circuit of the eighth embodiment described above.
　このように、上述の第９の実施の形態では、信号線リセットトランジスタ１４１とダイオード接続トランジスタ１４２との直列回路に並列に定電流トランジスタ３０１を接続する。これにより、信号読出し回路の面積の増大を抑制しつつ、カラム方向のビニングを実施することが可能となるとともに、定電流読出しと容量負荷読出しとを切り替えることができる。 In this way, in the ninth embodiment described above, the constant current transistor 301 is connected in parallel to the series circuit of the signal line reset transistor 141 and the diode-connected transistor 142. This makes it possible to perform binning in the column direction while suppressing an increase in the area of the signal readout circuit, and to switch between constant current readout and capacitive load readout.
　＜１０．第１０の実施の形態＞
　上述の第１の実施の形態では、信号線リセットトランジスタ１４１が各垂直信号線１３２－１から１３２－４に接続されたカラムごとにサンプルホールドされた信号に基づいてビニングした。この第１０の実施の形態では、画素１２０がマトリックス状に配列された画素アレイ部が設けられた固体撮像装置が形成される基板を積層化する。 <10. Tenth embodiment>
In the first embodiment described above, the signal line reset transistor 141 performs binning based on signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4. In the tenth embodiment, substrates on which a solid-state imaging device including a pixel array section in which pixels 120 are arranged in a matrix are formed are laminated.
　図１９は、第１０の実施の形態に係る撮像装置の構成例を示す斜視図である。 FIG. 19 is a perspective view showing a configuration example of an imaging device according to the tenth embodiment.
　同図におけるａにおいて、固体撮像装置９０１は、支持基板９１１および半導体基板９１２を備える。半導体基板９１２は、支持基板９１１上に積層されている。半導体基板９１２には、画素アレイ部９１３および周辺回路９１４が形成される。周辺回路９１４には、カラム読出し回路９１５およびカラムＡＤＣ９１６が形成される。カラム読出し回路９１５およびカラムＡＤＣ９１６は、画素アレイ部９１３のカラム方向の両側に形成してもよい。 At a in the figure, the solid-state imaging device 901 includes a support substrate 911 and a semiconductor substrate 912. A semiconductor substrate 912 is stacked on a support substrate 911. A pixel array section 913 and a peripheral circuit 914 are formed on the semiconductor substrate 912. In the peripheral circuit 914, a column readout circuit 915 and a column ADC 916 are formed. The column readout circuit 915 and the column ADC 916 may be formed on both sides of the pixel array section 913 in the column direction.
　画素アレイ部９１３には、ロウ方向およびカラム方向に沿ってマトリックス状に画素１２０が配列される。カラム読出し回路９１５は、容量負荷読出しに基づいて各画素１２０から個別に信号を読出したり、ビニングして読出したりすることができる。カラム読出し回路９１５には、例えば、図６の信号線リセットトランジスタ１４１および接続スイッチ１５１を形成してもよい。カラムＡＤＣ９１６は、カラム読出し回路９１５を介して読み出された信号をカラムごとにＡＤ変換することができる。このとき、固体撮像装置９０１は、裏面照射型イメージセンサを構成することができる。 In the pixel array section 913, pixels 120 are arranged in a matrix along the row and column directions. The column readout circuit 915 can read signals from each pixel 120 individually based on capacitive load readout, or can perform binning and readout. For example, the signal line reset transistor 141 and connection switch 151 in FIG. 6 may be formed in the column readout circuit 915. The column ADC 916 can AD convert signals read out via the column readout circuit 915 for each column. At this time, the solid-state imaging device 901 can constitute a back-illuminated image sensor.
　同図におけるｂにおいて、固体撮像装置９０２は、半導体基板９２１および９２２を備える。半導体基板９２２は、半導体基板９２１上に積層されている。半導体基板９２２には、画素アレイ部９２３が形成される。半導体基板９２２には、周辺回路９２４が形成される。周辺回路９２４には、カラム読出し回路９２５およびカラムＡＤＣ９２６が形成される。カラム読出し回路９２５およびカラムＡＤＣ９２６は、画素アレイ部９２３のカラム方向の両側の位置に対応するように形成してもよい。このとき、固体撮像装置９０２は、裏面照射型イメージセンサを構成することができる。 In b in the figure, the solid-state imaging device 902 includes semiconductor substrates 921 and 922. A semiconductor substrate 922 is stacked on the semiconductor substrate 921. A pixel array section 923 is formed on the semiconductor substrate 922. A peripheral circuit 924 is formed on the semiconductor substrate 922 . In the peripheral circuit 924, a column readout circuit 925 and a column ADC 926 are formed. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction. At this time, the solid-state imaging device 902 can constitute a back-illuminated image sensor.
　このように、上述の第１２の実施の形態では、各固体撮像装置９０１および９０２が形成される基板をそれぞれ積層化する。これにより、各画素アレイ部９１３および９２３を支持しつつ、各画素アレイ部９１３および９２３がそれぞれ形成される半導体基板９１２および９２２を薄膜化することができ、裏面照射型イメージセンサを形成することができる。 In this manner, in the twelfth embodiment described above, the substrates on which the solid- state imaging devices 901 and 902 are formed are laminated. As a result, while supporting each pixel array section 913 and 923, the semiconductor substrates 912 and 922 on which each pixel array section 913 and 923 are formed can be thinned, and a back-illuminated image sensor can be formed. can.
　＜１１．移動体への応用例＞
　本開示に係る技術（本技術）は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 <11. Example of application to mobile objects>
The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as a car, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, robot, etc. It's okay.
　図２０は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。 FIG. 20 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present disclosure can be applied.
　車両制御システム１２０００は、通信ネットワーク１２００１を介して接続された複数の電子制御ユニットを備える。図２０に示した例では、車両制御システム１２０００は、駆動系制御ユニット１２０１０、ボディ系制御ユニット１２０２０、車外情報検出ユニット１２０３０、車内情報検出ユニット１２０４０、及び統合制御ユニット１２０５０を備える。また、統合制御ユニット１２０５０の機能構成として、マイクロコンピュータ１２０５１、音声画像出力部１２０５２、及び車載ネットワークＩ／Ｆ(interface)１２０５３が図示されている。 The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 20, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. Further, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/image output section 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
　駆動系制御ユニット１２０１０は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット１２０１０は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。 The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 includes a drive force generation device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits the drive force to wheels, and a drive force transmission mechanism that controls the steering angle of the vehicle. It functions as a control device for a steering mechanism to adjust and a braking device to generate braking force for the vehicle.
　ボディ系制御ユニット１２０２０は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット１２０２０は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット１２０２０には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット１２０２０は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。 The body system control unit 12020 controls the operations of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a turn signal, or a fog lamp. In this case, radio waves transmitted from a portable device that replaces a key or signals from various switches may be input to the body control unit 12020. The body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, power window device, lamp, etc. of the vehicle.
　車外情報検出ユニット１２０３０は、車両制御システム１２０００を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット１２０３０には、撮像部１２０３１が接続される。車外情報検出ユニット１２０３０は、撮像部１２０３１に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット１２０３０は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。 The external information detection unit 12030 detects information external to the vehicle in which the vehicle control system 12000 is mounted. For example, an imaging section 12031 is connected to the outside-vehicle information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image. The external information detection unit 12030 may perform object detection processing such as a person, car, obstacle, sign, or text on the road surface or distance detection processing based on the received image.
　撮像部１２０３１は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部１２０３１は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部１２０３１が受光する光は、可視光であってもよいし、赤外線等の非可視光であってもよい。 The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. Furthermore, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared light.
　車内情報検出ユニット１２０４０は、車内の情報を検出する。車内情報検出ユニット１２０４０には、例えば、運転者の状態を検出する運転者状態検出部１２０４１が接続される。運転者状態検出部１２０４１は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット１２０４０は、運転者状態検出部１２０４１から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。 The in-vehicle information detection unit 12040 detects in-vehicle information. For example, a driver condition detection section 12041 that detects the condition of the driver is connected to the in-vehicle information detection unit 12040. The driver condition detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver condition detection unit 12041. It may be calculated, or it may be determined whether the driver is falling asleep.
　マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット１２０１０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むＡＤＡＳ(Advanced Driver Assistance System)の機能実現を目的とした協調制御を行うことができる。 The microcomputer 12051 calculates control target values for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and Control commands can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of autonomous driving, etc., which does not rely on operation.
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で取得される車外の情報に基づいて、ボディ系制御ユニット１２０２０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。 Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of preventing glare, such as switching from high beam to low beam. It can be carried out.
　音声画像出力部１２０５２は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図２０の例では、出力装置として、オーディオスピーカ１２０６１、表示部１２０６２及びインストルメントパネル１２０６３が例示されている。表示部１２０６２は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。 The audio and image output unit 12052 transmits an output signal of at least one of audio and images to an output device that can visually or audibly notify information to the occupants of the vehicle or to the outside of the vehicle. In the example of FIG. 20, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
　図２１は、撮像部１２０３１の設置位置の例を示す図である。 FIG. 21 is a diagram showing an example of the installation position of the imaging section 12031.
　図２１では、撮像部１２０３１として、撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５を有する。 In FIG. 21, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
　撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５は、例えば、車両１２１００のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部１２１０１及び車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として車両１２１００の前方の画像を取得する。サイドミラーに備えられる撮像部１２１０２，１２１０３は、主として車両１２１００の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部１２１０４は、主として車両１２１００の後方の画像を取得する。車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。 The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle 12100. An imaging unit 12101 provided in the front nose and an imaging unit 12105 provided above the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. Imaging units 12102 and 12103 provided in the side mirrors mainly capture images of the sides of the vehicle 12100. An imaging unit 12104 provided in the rear bumper or back door mainly captures images of the rear of the vehicle 12100. The imaging unit 12105 provided above the windshield inside the vehicle is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
　なお、図２１には、撮像部１２１０１ないし１２１０４の撮影範囲の一例が示されている。撮像範囲１２１１１は、フロントノーズに設けられた撮像部１２１０１の撮像範囲を示し、撮像範囲１２１１２，１２１１３は、それぞれサイドミラーに設けられた撮像部１２１０２，１２１０３の撮像範囲を示し、撮像範囲１２１１４は、リアバンパ又はバックドアに設けられた撮像部１２１０４の撮像範囲を示す。例えば、撮像部１２１０１ないし１２１０４で撮像された画像データが重ね合わせられることにより、車両１２１００を上方から見た俯瞰画像が得られる。 Note that FIG. 21 shows an example of the imaging range of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 shows the imaging range of the imaging unit 12101 provided on the front nose. The imaging range of the imaging unit 12104 provided in the rear bumper or back door is shown. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、距離情報を取得する機能を有していてもよい。例えば、撮像部１２１０１ないし１２１０４の少なくとも１つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。 At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of image sensors, or may be an image sensor having pixels for phase difference detection.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を基に、撮像範囲１２１１１ないし１２１１４内における各立体物までの距離と、この距離の時間的変化（車両１２１００に対する相対速度）を求めることにより、特に車両１２１００の進行路上にある最も近い立体物で、車両１２１００と略同じ方向に所定の速度（例えば、０ｋｍ／ｈ以上）で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ１２０５１は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御（追従停止制御も含む）や自動加速制御（追従発進制御も含む）等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 For example, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. In particular, by determining the three-dimensional object closest to the vehicle 12100 on its path and traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km/h or more), it is possible to extract the three-dimensional object as the preceding vehicle. can. Furthermore, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, cooperative control can be performed for the purpose of autonomous driving, etc., which does not rely on the driver's operation.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を元に、立体物に関する立体物データを、２輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ１２０５１は、車両１２１００の周辺の障害物を、車両１２１００のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ１２０５１は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ１２０６１や表示部１２０６２を介してドライバに警報を出力することや、駆動系制御ユニット１２０１０を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。 For example, the microcomputer 12051 transfers three-dimensional object data to other three-dimensional objects such as two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, and utility poles based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceeds a set value and there is a possibility of a collision, the microcomputer 12051 transmits information via the audio speaker 12061 and the display unit 12062. By outputting a warning to the driver via the vehicle control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部１２１０１ないし１２１０４の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ１２０５１が、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部１２０５２は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部１２０６２を制御する。また、音声画像出力部１２０５２は、歩行者を示すアイコン等を所望の位置に表示するように表示部１２０６２を制御してもよい。 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition involves, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and a pattern matching process is performed on a series of feature points indicating the outline of an object to determine whether it is a pedestrian or not. This is done by a procedure that determines the When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 creates a rectangular outline for emphasis on the recognized pedestrian. The display unit 12062 is controlled to display the . Furthermore, the audio image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
　以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、撮像部１２０３１に適用され得る。具体的には、例えば、上述のカメラ１００は、撮像部１２０３１に適用することができる。車両制御システム１２０００に本開示に係る技術を適用することにより、消費電力の増大を抑制しつつ、撮影画像を得ることが可能となる。 An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, for example, the above-described camera 100 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it becomes possible to obtain captured images while suppressing an increase in power consumption.
　なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。また、本明細書に記載された効果はあくまで例示であって、限定されるものではなく、また、他の効果があってもよい。 Note that the above-described embodiments show an example for embodying the present technology, and the matters in the embodiments and the matters specifying the invention in the claims have a corresponding relationship, respectively. Similarly, the matters specifying the invention in the claims and the matters in the embodiments of the present technology having the same names have a corresponding relationship. However, the present technology is not limited to the embodiments, and can be realized by making various modifications to the embodiments without departing from the gist thereof. Further, the effects described in this specification are merely examples, and are not limiting, and other effects may also exist.
　なお、本技術は以下のような構成もとることができる。
（１）画素がロウ方向およびカラム方向にマトリックス状に配置された画素アレイ部と、
　前記画素から読出された信号を前記カラム方向に伝送する信号線と、
　前記信号線を介して伝送される信号をカラムごとにサンプルホールドさせるサンプルホールドスイッチと、
　前記信号がサンプルホールドされた互いに異なるカラムの信号線を接続する接続スイッチと
を具備する撮像装置。
（２）前記信号線を介して伝送される信号を前記カラムごとにＡＤ変換するＡＤ変換部と、
　前記接続スイッチを介して接続された各カラムのＡＤ変換部のうちの１つのＡＤ変換部をアクティブ化するアクティブ制御部と
をさらに具備する前記（１）記載の撮像装置。
（３）前記ＡＤ変換部は、
　前記信号線の電位とランプ信号とを比較するコンパレータと、
　前記コンパレータの比較結果に基づいてカウント動作を実施するカウンタと
を備える前記（２）記載の撮像装置。
（４）前記アクティブ制御部は、前記ＡＤ変換部をアクティブ化されるカラムと非アクティブ化されるカラムとに分けて制御する前記（３）記載の固体撮像装置。
（５）前記コンパレータの第１入力端子に接続された第１ＤＣカットコンデンサと、
　前記コンパレータの第２入力端子に接続された第２ＤＣカットコンデンサと
をさらに具備する前記（３）または（４）に記載の撮像装置。
（６）前記アクティブ制御部は、第１容量電極が前記信号線に接続される前記第１ＤＣカットコンデンサの第２容量電極の接続先を前記コンパレータの第１入力端子と接地との間で切り替える切替スイッチ
をさらに具備する前記（５）記載の撮像装置。
（７）前記アクティブ制御部は、前記切替スイッチをアクティブ化されるカラムと非アクティブ化されるカラムとに分けて制御する
前記（６）記載の撮像装置。
（８）前記信号線を介して伝送される信号を前記カラムごとに増幅して前記ＡＤ変換部に入力するアンプ
をさらに具備する前記（２）から（７）のいずれかに記載の撮像装置。
（９）前記アクティブ制御部は、前記アンプをアクティブ化されるカラムと非アクティブ化されるカラムとに分けて制御する
前記（８）記載の撮像装置。
（１０）前記サンプルホールドスイッチは、前記信号線ごとに設けられたトランジスタである
前記（１）から（９）のいずれかに記載の撮像装置。
（１１）前記トランジスタを前記ロウ方向の両側から駆動するドライバ
をさらに具備する前記（１０）記載の撮像装置。
（１２）前記信号線の電位をリセットする信号線リセットトランジスタと、
　前記信号線の電位のリセットレベルを生成する信号線リセットレベル生成部と
をさらに具備する前記（１）から（１１）のいずれかに記載の撮像装置。
（１３）前記信号線リセットレベル生成部は、ダイオード接続トランジスタを備える
前記（１２）記載の撮像装置。
（１４）前記信号のサンプルホールドに用いられる容量は、前記信号線の寄生容量である
前記（１）から（１３）のいずれかに記載の撮像装置。
（１５）前記接続スイッチは、前記信号のサンプルホールドに用いられるカラムごとの容量に対して直列接続される
前記（１）から（１４）のいずれかに記載の撮像装置。
（１６）前記接続スイッチは、前記信号のサンプルホールドに用いられるカラムごとの容量に対して並列接続される
前記（１）から（１４）のいずれかに記載の撮像装置。
（１７）前記信号線に電気的に接続可能であり、前記画素との間に形成されるソースフォロワに基づいて定電流を流す定電流トランジスタをさらに具備し、
　定電流読出しでは、前記定電流トランジスタはオンされ、
　容量負荷読出しでは、前記定電流トランジスタはオフされる
前記（１）から（１６）のいずれかに記載の撮像装置。
（１８）前記画素は、
　フォトダイオードと、
　前記フォトダイオードに蓄積された電荷をフローティングディフュージョンに転送する転送トランジスタと、
　前記フローティングディフュージョンをリセットするリセットトランジスタと、
　前記フローティングディフュージョンの電位に応じた信号を出力する増幅トランジスタと、
　前記増幅トランジスタと前記信号線との間に接続された選択トランジスタと
を備える前記（１）から（１７）のいずれかに記載の撮像装置。
（１９）前記サンプルホールドスイッチは、前記選択トランジスタである
前記（１９）記載の撮像装置。
（２０）互いに異なるロウのフローティングディフュージョンを接続するビニングトランジスタをさらに備える
前記（１８）または（１９）に記載の撮像装置。 Note that the present technology can also have the following configuration.
(1) A pixel array section in which pixels are arranged in a matrix in the row direction and column direction;
a signal line that transmits a signal read out from the pixel in the column direction;
a sample hold switch that samples and holds the signal transmitted via the signal line for each column;
An imaging device comprising: a connection switch that connects signal lines of different columns in which the signals are sampled and held.
(2) an AD converter that performs AD conversion for each column of signals transmitted via the signal line;
The imaging device according to (1), further comprising an active control section that activates one AD conversion section among the AD conversion sections of each column connected via the connection switch.
(3) The AD conversion section
a comparator that compares the potential of the signal line and the ramp signal;
The imaging device according to (2), further comprising a counter that performs a counting operation based on a comparison result of the comparator.
(4) The solid-state imaging device according to (3), wherein the active control section controls the AD conversion section separately into an activated column and a deactivated column.
(5) a first DC cut capacitor connected to the first input terminal of the comparator;
The imaging device according to (3) or (4), further comprising a second DC cut capacitor connected to a second input terminal of the comparator.
(6) The active control unit is configured to switch a connection destination of a second capacitance electrode of the first DC cut capacitor, the first capacitance electrode of which is connected to the signal line, between a first input terminal of the comparator and ground. The imaging device according to (5) above, further comprising a switch.
(7) The imaging device according to (6), wherein the active control unit controls the changeover switch separately for activated columns and deactivated columns.
(8) The imaging device according to any one of (2) to (7), further comprising an amplifier that amplifies a signal transmitted via the signal line for each column and inputs the amplified signal to the AD conversion section.
(9) The imaging device according to (8), wherein the active control unit controls the amplifiers separately for an activated column and a deactivated column.
(10) The imaging device according to any one of (1) to (9), wherein the sample and hold switch is a transistor provided for each of the signal lines.
(11) The imaging device according to (10), further comprising a driver that drives the transistor from both sides in the row direction.
(12) a signal line reset transistor that resets the potential of the signal line;
The imaging device according to any one of (1) to (11), further comprising a signal line reset level generation unit that generates a reset level of the potential of the signal line.
(13) The imaging device according to (12), wherein the signal line reset level generation section includes a diode-connected transistor.
(14) The imaging device according to any one of (1) to (13), wherein the capacitance used to sample and hold the signal is a parasitic capacitance of the signal line.
(15) The imaging device according to any one of (1) to (14), wherein the connection switch is connected in series to a capacitor for each column used for sample-holding the signal.
(16) The imaging device according to any one of (1) to (14), wherein the connection switch is connected in parallel to a capacitor for each column used for sample-holding the signal.
(17) further comprising a constant current transistor that is electrically connectable to the signal line and that flows a constant current based on a source follower formed between the pixel;
For constant current readout, the constant current transistor is turned on;
The imaging device according to any one of (1) to (16), wherein the constant current transistor is turned off during capacitive load reading.
(18) The pixel is
photodiode and
a transfer transistor that transfers the charge accumulated in the photodiode to a floating diffusion;
a reset transistor that resets the floating diffusion;
an amplification transistor that outputs a signal according to the potential of the floating diffusion;
The imaging device according to any one of (1) to (17), including a selection transistor connected between the amplification transistor and the signal line.
(19) The imaging device according to (19), wherein the sample hold switch is the selection transistor.
(20) The imaging device according to (18) or (19), further including a binning transistor that connects floating diffusions of different rows.
　１００　カメラ
　１０１　光学系
　１０２　固体撮像装置
　１０３　撮像制御部
　１０４　画像処理部
　１０５　記憶部
　１０６　表示部
　１０７　操作部
　１０８　バス
　１１１　画素アレイ部
　１１２　垂直走査回路
　１１３　カラム読出し回路
　１１４　カラム信号処理部
　１１５　水平走査回路
　１１６　制御回路
　１１７、１１８　ドライバ
　１１９　アクティブ制御部
　１２１　フォトダイオード
　１２２　転送トランジスタ
　１２３　リセットトランジスタ
　１２４　増幅トランジスタ
　１２５　選択トランジスタ
　１２６　フローティングディフュージョン
　１３１　水平駆動線
　１３２　垂直信号線
　１３３　容量
　１４１　信号線リセットトランジスタ
　１４２　ダイオード接続トランジスタ
　１４３　コンパレータ
　１４４、１４５　ＤＣカットコンデンサ
　１４６　カウンタ
　１５１　接続スイッチ 100 Camera 101 Optical system 102 Solid-state imaging device 103 Imaging control section 104 Image processing section 105 Storage section 106 Display section 107 Operation section 108 Bus 111 Pixel array section 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing section 115 Horizontal scanning circuit 116 Control circuit 117, 118 Driver 119 Active control unit 121 Photodiode 122 Transfer transistor 123 Reset transistor 124 Amplification transistor 125 Selection transistor 126 Floating diffusion 131 Horizontal drive line 132 Vertical signal line 133 Capacitor 141 Signal line reset transistor 142 Diode-connected transistor 143 Comparator 144 , 145 DC cut capacitor 146 Counter 151 Connection switch

Claims (20)

  1. 　画素がロウ方向およびカラム方向にマトリックス状に配置された画素アレイ部と、
    　前記画素から読出された信号を前記カラム方向に伝送する信号線と、
    　前記信号線を介して伝送される信号をカラムごとにサンプルホールドさせるサンプルホールドスイッチと、
    　前記信号がサンプルホールドされた互いに異なるカラムの信号線を接続する接続スイッチと
    を具備する撮像装置。     a pixel array section in which pixels are arranged in a matrix in a row direction and a column direction;
    a signal line that transmits a signal read out from the pixel in the column direction;
    a sample hold switch that samples and holds the signal transmitted via the signal line for each column;
    An imaging device comprising: a connection switch that connects signal lines of different columns in which the signals are sampled and held.
  2. 　前記信号線を介して伝送される信号を前記カラムごとにＡＤ変換するＡＤ変換部と、
    　前記接続スイッチを介して接続された各カラムのＡＤ変換部のうちの１つのＡＤ変換部をアクティブ化するアクティブ制御部と
    をさらに具備する請求項１記載の撮像装置。     an AD conversion unit that performs AD conversion for each column of the signal transmitted via the signal line;
    The imaging device according to claim 1, further comprising an active control section that activates one AD conversion section among the AD conversion sections of each column connected via the connection switch.
  3. 　前記ＡＤ変換部は、
    　前記信号線の電位とランプ信号とを比較するコンパレータと、
    　前記コンパレータの比較結果に基づいてカウント動作を実施するカウンタと
    を備える請求項２記載の撮像装置。     The AD converter includes:
    a comparator that compares the potential of the signal line and the ramp signal;
    The imaging device according to claim 2, further comprising a counter that performs a counting operation based on a comparison result of the comparator.
  4. 　前記アクティブ制御部は、前記ＡＤ変換部をアクティブ化されるカラムと非アクティブ化されるカラムとに分けて制御する
    請求項２記載の撮像装置。     The imaging device according to claim 2, wherein the active control section controls the AD conversion section separately into an activated column and a deactivated column.
  5. 　前記コンパレータの第１入力端子に接続された第１ＤＣカットコンデンサと、
    　前記コンパレータの第２入力端子に接続された第２ＤＣカットコンデンサと
    をさらに具備する請求項３記載の撮像装置。     a first DC cut capacitor connected to a first input terminal of the comparator;
    The imaging device according to claim 3, further comprising a second DC cut capacitor connected to a second input terminal of the comparator.
  6. 　第１容量電極が前記信号線に接続される前記第１ＤＣカットコンデンサの第２容量電極の接続先を前記コンパレータの第１入力端子と接地との間で切り替える切替スイッチ
    をさらに具備する請求項５記載の撮像装置。     6. A changeover switch according to claim 5, further comprising a changeover switch for switching a connection destination of a second capacitance electrode of the first DC cut capacitor, the first capacitance electrode of which is connected to the signal line, between a first input terminal of the comparator and ground. imaging device.
  7. 　前記アクティブ制御部は、前記切替スイッチをアクティブ化されるカラムと非アクティブ化されるカラムとに分けて制御する
    請求項６記載の撮像装置。     7. The imaging apparatus according to claim 6, wherein the active control unit controls the changeover switch separately for an activated column and a deactivated column.
  8. 　前記信号線を介して伝送される信号を前記カラムごとに増幅して前記ＡＤ変換部に入力するアンプ
    をさらに具備する請求項２記載の撮像装置。     The imaging device according to claim 2, further comprising an amplifier that amplifies the signal transmitted via the signal line for each column and inputs the amplified signal to the AD conversion section.
  9. 　前記アクティブ制御部は、前記アンプをアクティブ化されるカラムと非アクティブ化されるカラムとに分けて制御する
    請求項８記載の撮像装置。     The imaging device according to claim 8, wherein the active control unit controls the amplifiers separately into activated columns and deactivated columns.
  10. 　前記サンプルホールドスイッチは、前記信号線ごとに設けられたトランジスタである
    請求項１記載の撮像装置。     The imaging device according to claim 1, wherein the sample and hold switch is a transistor provided for each of the signal lines.
  11. 　前記トランジスタを前記ロウ方向の両側から駆動するドライバ
    をさらに具備する請求項１０記載の撮像装置。     The imaging device according to claim 10, further comprising a driver that drives the transistor from both sides in the row direction.
  12. 　前記信号線の電位をリセットする信号線リセットトランジスタと、
    　前記信号線の電位のリセットレベルを生成する信号線リセットレベル生成部と
    をさらに具備する請求項１記載の撮像装置。     a signal line reset transistor that resets the potential of the signal line;
    The imaging device according to claim 1, further comprising a signal line reset level generation section that generates a reset level of the potential of the signal line.
  13. 　前記信号線リセットレベル生成部は、ダイオード接続トランジスタを備える
    請求項４記載の撮像装置。     The imaging device according to claim 4, wherein the signal line reset level generation section includes a diode-connected transistor.
  14. 　前記信号のサンプルホールドに用いられる容量は、前記信号線の寄生容量である
    請求項１記載の撮像装置。     2. The imaging device according to claim 1, wherein the capacitance used to sample and hold the signal is a parasitic capacitance of the signal line.
  15. 　前記接続スイッチは、前記信号のサンプルホールドに用いられるカラムごとの容量に対して直列接続される
    請求項１記載の撮像装置。     The imaging device according to claim 1, wherein the connection switch is connected in series to a capacitor for each column used for sample-holding the signal.
  16. 　前記接続スイッチは、前記信号のサンプルホールドに用いられるカラムごとの容量に対して並列接続される
    請求項１記載の撮像装置。     The imaging device according to claim 1, wherein the connection switch is connected in parallel to a capacitor for each column used for sample-holding the signal.
  17. 　前記信号線に電気的に接続可能であり、前記画素との間に形成されるソースフォロワに基づいて定電流を流す定電流トランジスタをさらに具備し、
    　定電流読出しでは、前記定電流トランジスタはオンされ、
    　容量負荷読出しでは、前記定電流トランジスタはオフされる
    請求項１記載の撮像装置。     further comprising a constant current transistor that is electrically connectable to the signal line and that flows a constant current based on a source follower formed between the pixel and the pixel;
    For constant current readout, the constant current transistor is turned on;
    The imaging device according to claim 1, wherein the constant current transistor is turned off during capacitive load readout.
  18. 　前記画素は、
    　フォトダイオードと、
    　前記フォトダイオードに蓄積された電荷をフローティングディフュージョンに転送する転送トランジスタと、
    　前記フローティングディフュージョンをリセットするリセットトランジスタと、
    　前記フローティングディフュージョンの電位に応じた信号を出力する増幅トランジスタと、
    　前記増幅トランジスタと前記信号線との間に接続された選択トランジスタと
    を備える請求項１記載の撮像装置。     The pixel is
    photodiode and
    a transfer transistor that transfers the charge accumulated in the photodiode to a floating diffusion;
    a reset transistor that resets the floating diffusion;
    an amplification transistor that outputs a signal according to the potential of the floating diffusion;
    The imaging device according to claim 1, further comprising a selection transistor connected between the amplification transistor and the signal line.
  19. 　前記サンプルホールドスイッチは、前記選択トランジスタである
    請求項１８記載の撮像装置。     The imaging device according to claim 18, wherein the sample and hold switch is the selection transistor.
  20. 　互いに異なるロウのフローティングディフュージョンを接続するビニングトランジスタをさらに備える
    請求項１８記載の撮像装置。     The imaging device according to claim 18, further comprising a binning transistor connecting floating diffusions of different rows.
PCT/JP2023/024442 2022-08-25 2023-06-30 Imaging device WO2024042864A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022134128 2022-08-25
JP2022-134128 2022-08-25

Publications (1)

Publication Number Publication Date
WO2024042864A1 true WO2024042864A1 (en) 2024-02-29

Family

ID=90012878

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/024442 WO2024042864A1 (en) 2022-08-25 2023-06-30 Imaging device

Country Status (1)

Country Link
WO (1) WO2024042864A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010245951A (en) * 2009-04-08 2010-10-28 Nikon Corp Imaging element, and imaging device
JP2016052055A (en) * 2014-09-01 2016-04-11 キヤノン株式会社 Imaging device
JP2018139374A (en) * 2017-02-24 2018-09-06 キヤノン株式会社 Imaging apparatus and imaging system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010245951A (en) * 2009-04-08 2010-10-28 Nikon Corp Imaging element, and imaging device
JP2016052055A (en) * 2014-09-01 2016-04-11 キヤノン株式会社 Imaging device
JP2018139374A (en) * 2017-02-24 2018-09-06 キヤノン株式会社 Imaging apparatus and imaging system

Similar Documents

Publication Publication Date Title
US11418749B2 (en) Solid-state image pick-up device and electronic device
EP3301907B1 (en) Solid-state imaging device, method of driving solid-state imaging device, and imaging system
US11323648B2 (en) Solid-state image sensor and electronic apparatus
WO2020090460A1 (en) Sensor and control method
CN111615824B (en) Imaging device and electronic apparatus
CN115398885A (en) Solid-state image pickup element
WO2020059553A1 (en) Solid-state imaging device and electronic apparatus
US11381764B2 (en) Sensor element and electronic device
WO2020085085A1 (en) Solid-state imaging device
WO2019193801A1 (en) Solid-state imaging element, electronic apparatus, and method for controlling solid-state imaging element
WO2020121699A1 (en) Imaging device
US20230326940A1 (en) Imaging device and electronic apparatus
WO2024042864A1 (en) Imaging device
US11671728B2 (en) Sensing device, electronic apparatus, and method for controlling sensing device
WO2024042862A1 (en) Imaging device
JP7309713B2 (en) Comparator and imager
WO2024042863A1 (en) Imaging device
US11438534B2 (en) Solid-state imaging device and electronic apparatus
WO2024095630A1 (en) Imaging device
WO2023100547A1 (en) Imaging device and electronic apparatus
WO2024004377A1 (en) Solid-state imaging element, imaging device, and method for controlling solid-state imaging element
WO2023026576A1 (en) Imaging device and electronic apparatus
WO2023067961A1 (en) Solid-state imaging element, imaging device, and method for controlling solid-state imaging element
WO2024042946A1 (en) Photodetector element
WO2024135091A1 (en) Imaging device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23856981

Country of ref document: EP

Kind code of ref document: A1