WO2024042864A1 - Dispositif d'imagerie - Google Patents

Dispositif d'imagerie Download PDF

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Publication number
WO2024042864A1
WO2024042864A1 PCT/JP2023/024442 JP2023024442W WO2024042864A1 WO 2024042864 A1 WO2024042864 A1 WO 2024042864A1 JP 2023024442 W JP2023024442 W JP 2023024442W WO 2024042864 A1 WO2024042864 A1 WO 2024042864A1
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Prior art keywords
signal
column
transistor
signal line
imaging device
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PCT/JP2023/024442
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English (en)
Japanese (ja)
Inventor
守 佐藤
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2024042864A1 publication Critical patent/WO2024042864A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present technology relates to an imaging device. Specifically, the present technology relates to an imaging device provided with a binning function.
  • an imaging device For surveillance cameras and cameras mounted on mobile terminals, there is a technology that allows them to operate constantly for purposes such as detecting moving objects, and reduces power consumption by lowering the spatial resolution using analog binning.
  • an imaging device for example, an imaging device has been proposed that holds one pixel signal in each of a plurality of signal holding sections and averages and outputs the pixel signals held in the plurality of signal holding sections (for example, , see Patent Document 1).
  • the first switch circuit selectively connects the pixel to each of the plurality of signal holding sections to hold one pixel signal in each of the plurality of signal holding sections, and the second switch circuit , averages and outputs pixel signals held in a plurality of signal holding units. Therefore, in the above-mentioned conventional technology, the number of switches connected to the signal line that transmits signals read from pixels in the column direction increases, which may lead to an increase in the area occupied by the switches.
  • This technology was created in view of this situation, and enables binning while suppressing the increase in the number of switches connected to the signal line that transmits signals read from pixels in the column direction.
  • the purpose is to
  • the present technology was developed to solve the above-mentioned problems, and its first aspect is that it includes a pixel array section in which pixels are arranged in a matrix in the row direction and column direction, and a pixel array section in which pixels are read out from the pixels.
  • a signal line that transmits the signal transmitted in the column direction a sample hold switch that samples and holds the signal transmitted via the signal line for each column, and a signal line that connects the signal lines of different columns to which the signal is sampled and held.
  • This is an imaging device equipped with a connection switch. This brings about the effect that binning is performed after the signals transmitted via the signal line are sampled and held for each column.
  • an AD converter that AD converts a signal transmitted via the signal line for each column, and one of the AD converters for each column connected via the connection switch.
  • the device may further include an active control unit that activates one AD conversion unit. This brings about the effect that the power consumption of the AD converter, which does not need to operate during binning processing, can be reduced in power consumption.
  • the AD conversion section may include a comparator that compares the potential of the signal line and a ramp signal, and a counter that performs a counting operation based on the comparison result of the comparator. This brings about the effect that the signal transmitted via the signal line is digitized.
  • the active control section may control the AD conversion section separately into an activated column and a deactivated column. This brings about the effect that the AD converter of at least one column among the plurality of columns is deactivated during binning.
  • the device may further include a first DC cut capacitor connected to the first input terminal of the comparator, and a second DC cut capacitor connected to the second input terminal of the comparator. This brings about the effect that the DC-cut signal is input to the comparator.
  • the active control unit connects a connection destination of a second capacitance electrode of the first DC cut capacitor whose first capacitance electrode is connected to the signal line to a first input terminal of the comparator and ground. You may further include a changeover switch for switching between. This brings about the effect that the capacitance of the first DC cut capacitor in one column is added to the signal line in another column.
  • the active control unit may control the changeover switch separately for activated columns and deactivated columns. This brings about the effect that the capacitance added to the column to be deactivated is added to the capacitance of the signal line of the column to be activated.
  • the device may further include an amplifier that amplifies the signal transmitted via the signal line for each column and inputs the amplified signal to the AD conversion section. This brings about the effect that the signal input to the AD conversion section is increased.
  • the active control section may control the amplifiers separately into activated columns and deactivated columns. This brings about the effect that the amplifier of at least one column among the plurality of columns is deactivated during binning.
  • the sample and hold switch may be a transistor provided for each of the signal lines. This brings about the effect that the signals transmitted via the signal line are sampled and held for each column.
  • the device may further include a driver that drives the transistor from both sides in the row direction. This brings about the effect that the driving force of the transistors in each column is increased based on the two drivers provided in common to the plurality of columns.
  • the device may further include a signal line reset transistor that resets the potential of the signal line, and a signal line reset level generation unit that generates a reset level of the potential of the signal line.
  • the signal line reset level generation section may include a diode-connected transistor. This brings about the effect that the potential of the signal line is raised in accordance with the forward voltage of the diode-connected transistor when the signal line is reset.
  • the capacitance used for sample and hold of the signal may be a parasitic capacitance of the signal line. This brings about the effect that capacitive load reading can be performed without adding a capacitive element to the signal line.
  • connection switch may be connected in series to a capacitor for each column used for sample and hold of the signal. This brings about the effect of making binning possible while making the number of columns to be binned variable.
  • connection switch may be connected in parallel to a capacitor for each column used for sample-holding the signal. This brings about the effect that binning can be performed while fixing the number of columns to be binned.
  • the invention further includes a constant current transistor that is electrically connectable to the signal line and that flows a constant current based on a source follower formed between the pixel and the constant current readout.
  • the constant current transistor may be turned on, and in capacitive load reading, the constant current transistor may be turned off. This brings about the effect that capacitive load readout and constant current readout can be switched.
  • the pixel includes a photodiode, a transfer transistor that transfers the charge accumulated in the photodiode to the floating diffusion, a reset transistor that resets the floating diffusion, and a potential of the floating diffusion.
  • the device may include an amplification transistor that outputs a corresponding signal, and a selection transistor connected between the amplification transistor and the signal line. This brings about the effect that a source follower is formed between the pixel and the pixel when a signal is read from the pixel.
  • the sample and hold switch may be the selection transistor. This brings about the effect that the signals transmitted via the signal line are sampled and held for each column.
  • a binning transistor may be further provided to connect floating diffusions in different rows. This brings about the effect that it is possible to binning mutually different rows.
  • FIG. 1 is a block diagram illustrating a configuration example of a camera to which the imaging device according to the first embodiment is applied.
  • 1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment.
  • FIG. 2 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing a configuration example of a pixel array section provided in the solid-state imaging device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a modification of the pixel array section provided in the solid-state imaging device according to the first embodiment.
  • FIG. 3 is a diagram showing a configuration example of a signal readout circuit for four columns according to the first embodiment.
  • FIG. 3 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the first embodiment.
  • FIG. 3 is a diagram illustrating a configuration example of a comparator applied to the signal readout circuit according to the first embodiment.
  • FIG. 7 is a diagram showing a configuration example of a signal readout circuit for four columns according to a second embodiment.
  • FIG. 7 is a diagram showing a configuration example of a signal readout circuit for four columns according to a third embodiment.
  • FIG. 7 is a diagram showing an example of the configuration of a signal readout circuit for two columns according to a fourth embodiment.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to a fifth embodiment.
  • FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for four columns according to a sixth embodiment.
  • FIG. 12 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the sixth embodiment.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to a seventh embodiment.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to an eighth embodiment.
  • FIG. 12 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the eighth embodiment.
  • FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for one column according to a ninth embodiment.
  • FIG. 12 is a perspective view showing a configuration example of an imaging device according to a tenth embodiment.
  • FIG. 1 is a block diagram showing a schematic configuration example of a vehicle control system.
  • FIG. 3 is an explanatory diagram showing an example of an installation position of an imaging unit.
  • First embodiment an example of binning based on signals sampled and held for each column in which a signal line reset transistor is connected to a vertical signal line
  • Second embodiment an example of binning based on signals sampled and held for each column in which diode-connected transistors are connected to vertical signal lines via signal line reset transistors
  • Third Embodiment (Binning is performed based on the signal sampled and held for each column in which the signal line reset transistor is connected to the vertical signal line, and connection switches are connected in parallel to the capacitance of each column used for sample and hold. Example of connection) 4.
  • Fourth embodiment (an example of binning in the row direction and column direction based on a signal sampled and held for each column in which a signal line reset transistor is connected to a vertical signal line) 5.
  • Fifth embodiment (example where each column is provided with an amplifier that amplifies the signal input to the AD conversion section) 6.
  • Sixth embodiment (example in which a driver is provided to drive a sample hold switch provided for each signal line from both sides in the row direction) 7.
  • Seventh embodiment (example of switching connection destination of DC cut capacitor between comparator input and ground) 8.
  • Eighth embodiment (example of binning based on signals sampled and held for each column in which constant current transistors are connected to vertical signal lines) 9.
  • Ninth embodiment (example in which a constant current transistor is connected in parallel to a series circuit of a signal line reset transistor and a diode-connected transistor) 10.
  • Tenth embodiment (example in which substrates on which a solid-state imaging device is formed are laminated) 11.
  • FIG. 1 is a block diagram showing a configuration example of a camera to which an imaging device according to a first embodiment is applied.
  • a camera 100 includes an optical system 101, a solid-state imaging device 102, an imaging control section 103, an image processing section 104, a storage section 105, a display section 106, and an operation section 107.
  • the imaging control section 103, the image processing section 104, the storage section 105, the display section 106, and the operation section 107 are connected to each other via a bus 108.
  • the camera 100 may be used alone, or may be incorporated into a mobile terminal such as a smartphone, or may be incorporated into an authentication device or a monitoring device.
  • the optical system 101 makes light from a subject enter the solid-state imaging device 102 and forms an image of the subject on the light-receiving surface of the solid-state imaging device 102.
  • the optical system 101 can include, for example, a focus lens, a zoom lens, an aperture, and the like.
  • Optical system 101 may include multiple lenses such as a wide-angle lens, a standard lens, and a telephoto lens.
  • the solid-state imaging device 102 converts light from a subject into an electrical signal for each pixel, digitizes the electrical signal, and outputs the digital signal.
  • the solid-state imaging device 102 may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device).
  • CMOS Complementary Metal Oxide Semiconductor
  • CCD Charge Coupled Device
  • the imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.
  • the image processing unit 104 performs image processing based on the output from the solid-state imaging device 102.
  • Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing.
  • the image processing unit 104 may include a processor that executes processing based on software.
  • the storage unit 105 stores captured images captured by the solid-state imaging device 102, and stores imaging parameters of the solid-state imaging device 102. Furthermore, the storage unit 105 can store a program for operating the camera 100 based on software.
  • the storage unit 105 may include a ROM (Read Only Memory), a RAM (Random Access Memory), and a memory card.
  • the display unit 106 displays captured images and various information that supports imaging operations.
  • the display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.
  • the operation unit 107 provides a user interface for operating the camera 100.
  • the operation unit 107 may include, for example, buttons, dials, and switches provided on the camera 100.
  • the operation unit 107 may be configured with a touch panel together with the display unit 106.
  • FIG. 2 is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment.
  • the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, a control circuit 116, drivers 117 and 118, and an active control section 119. Be prepared.
  • the pixel array section 111 includes a plurality of pixels 120.
  • the pixels 120 are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction).
  • Each pixel 120 can form a source follower with the column readout circuit 113 during signal readout.
  • Each pixel 120 is connected to a horizontal drive line 131 for each row and to a vertical signal line 132 for each column.
  • the horizontal drive line 131 drives each pixel 120 row by row when reading signals from each pixel 120.
  • the vertical signal line 132 transmits to the column signal processing unit 114 for each column a potential based on accumulated charges according to a current flowing when reading a signal from the pixel 120. Note that the vertical signal line 132 is an example of a signal line described in the claims.
  • the vertical scanning circuit 112 scans the pixels 120 to be read in the column direction.
  • the vertical scanning circuit 112 may be configured using vertical registers.
  • the column readout circuit 113 can form a source follower with each pixel 120 when reading signals from each pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120. Column readout circuit 113 can support capacitive load readout. The column readout circuit 113 may also support constant current readout.
  • the column readout circuit 113 also includes a sample and hold switch that samples and holds signals transmitted via the vertical signal line 132 for each column, and a connection switch that connects the vertical signal lines 132 of different columns on which signals are sampled and held. Equipped with. At this time, the column readout circuit 113 can sample and hold the signal transmitted via the vertical signal line 132 for each column, perform binning, and output the signal to the column signal processing section 114.
  • Each driver 117 and 118 drives a sample hold switch provided in the column readout circuit 113 from both sides in the row direction.
  • Each driver 117 and 118 can be shared by sample and hold switches provided for each column.
  • Each driver 117 and 118 may be placed on either side of column readout circuit 113.
  • the column signal processing unit 114 processes signals transmitted from each pixel 120 in the column direction. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on signals transmitted from each pixel 120 in the column direction. Further, the column signal processing unit 114 can perform AD (Analog to Digital) conversion processing based on the signals transmitted from each pixel 120 in the column direction, and output the image pickup signal Gout. At this time, the column signal processing section 114 can include an AD conversion section for each column that performs AD conversion on the signal transmitted via the vertical signal line 132.
  • CDS correlated double sampling
  • AD Analog to Digital
  • the active control unit 119 activates one AD conversion unit among the AD conversion units of each column connected via the connection switch. At this time, the active control section 119 can output a control signal CTL to each AD conversion section to control the activation timing of each AD conversion section during binning.
  • the active control unit 119 may control the AD conversion unit separately for activated columns and deactivated columns. At this time, the active control unit 119 can activate the AD conversion unit of the column to be activated and put the AD conversion unit of the column to be deactivated into a standby state.
  • the horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction.
  • the horizontal scanning circuit 115 may be configured using a horizontal register.
  • the control circuit 116 controls the vertical scanning circuit 112, column readout circuit 113, column signal processing section 114, horizontal scanning circuit 115, and drivers 117 and 118.
  • the control circuit 116 can control the scan timing in the column direction, the scan timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing section 114. Further, the control circuit 116 can control the drive timing of each driver 117 and 118 and the operation timing of the active control section 119.
  • a sample and hold switch is provided in the column readout circuit 113 in order to perform binning based on a signal sampled and held for each column.
  • a selection transistor provided in the pixel 120 may be used to sample and hold the signal read out from the pixel 120 for each column.
  • the sample and hold switch provided in the column readout circuit 113 is not required.
  • drivers 117 and 118 on both sides of column readout circuit 113 are also unnecessary.
  • binning readout it is also possible to switch between binning readout and all-pixel individual readout.
  • binning processing may be operated constantly, or when an application such as still image shooting is started, all pixels are individually read out. You may switch to
  • FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.
  • a pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion 126.
  • MOS Metal Oxide Semiconductor
  • the amplification transistor 124 and the selection transistor 125 are connected in series.
  • a cathode of the photodiode 121 is connected to a floating diffusion 126 via a transfer transistor 122.
  • the floating diffusion 126 is connected to the power supply Vdd via the reset transistor 123.
  • the power supply Vdd is connected to the vertical signal line 132 via a series circuit of an amplification transistor 124 and a selection transistor 125.
  • the gate of amplification transistor 124 is connected to floating diffusion 126 .
  • a transfer signal ⁇ TG is applied to the gate of the transfer transistor 122.
  • a pixel reset signal ⁇ PRT is applied to the gate of the reset transistor 123.
  • a selection signal ⁇ SEL is applied to the gate of the selection transistor 125.
  • the transfer signal ⁇ TG, pixel reset signal ⁇ PRT, and selection signal ⁇ SEL can be transmitted to each pixel 120 via the horizontal drive line 131 in FIG.
  • the transfer transistor 122 When the transfer transistor 122 is turned on, the charges accumulated in the photodiode 121 are transferred to the floating diffusion 126. Then, when the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion 126. The source potential of the amplification transistor 124 is applied to the vertical signal line 132 via the selection transistor 125 and transmitted via the vertical signal line 132. Furthermore, when the reset transistor 123 is turned on, the charges accumulated in the floating diffusion 126 are discharged.
  • FIG. 4 is a cross-sectional view showing an example of the configuration of a pixel array section provided in the solid-state imaging device according to the first embodiment. Note that FIG. 4 shows an example of a front-illuminated solid-state imaging device. Further, FIG. 4 shows a configuration example for three pixels.
  • a photodiode 232 is formed on a semiconductor substrate 231 for each pixel 120.
  • the material of the semiconductor substrate 231 may be Si, InGaAs, or InP.
  • a gate electrode 214 and a wiring layer 210 are formed on the semiconductor substrate 231.
  • Gate electrode 214 is formed on semiconductor substrate 231 with gate insulating film 213 interposed therebetween.
  • a sidewall 215 is formed on the sidewall of the gate electrode 214 .
  • the material of the gate electrode 214 for example, polycrystalline silicon into which impurities are introduced can be used.
  • the material of the gate insulating film 213, for example, a silicon oxide film can be used.
  • the gate electrode 214 can be used for a pixel transistor.
  • the pixel transistors include the transfer transistor 122, reset transistor 123, amplification transistor 124, and selection transistor 125 in FIG.
  • a wiring 216 is formed on the gate electrode 214.
  • FIG. 4 shows an example of three-layer wiring.
  • the wiring 216 is provided with an opening OP1 that allows light to enter the photodiode 232.
  • Gate electrode 214 and wiring 216 are insulated via insulating layer 217.
  • insulating layer 217 For example, a silicon oxide film can be used as the insulating layer 217.
  • metal such as Al or Cu can be used as the material of the wiring 216.
  • a color filter 218 is formed on the wiring layer 210 for each pixel 120.
  • a microlens 219 is formed on the color filter 218 for each pixel 120.
  • transparent resin such as acrylic or polycarbonate can be used.
  • a pigment may be added to the color filter 218 for coloring.
  • the color filter 218 can have a Bayer array, for example.
  • FIG. 5 is a cross-sectional view showing a modification of the pixel array section provided in the solid-state imaging device according to the first embodiment. Note that FIG. 5 shows an example of a back-illuminated solid-state imaging device. Further, FIG. 5 shows a configuration example for three pixels.
  • a photodiode 222 is formed in a semiconductor layer 221 for each pixel 120.
  • the material of the semiconductor layer 221 may be Si, InGaAs, or InP.
  • the semiconductor layer 221 can be formed, for example, by thinning a semiconductor substrate on which the photodiode 222 is formed from the back side.
  • a gate electrode 224 and a wiring layer 220 are formed on the semiconductor layer 221.
  • Gate electrode 224 is formed on semiconductor layer 221 with gate insulating film 223 interposed therebetween.
  • a sidewall 225 is formed on the sidewall of the gate electrode 224 .
  • the gate electrode 224 can be used for a pixel transistor.
  • the pixel transistors include the transfer transistor 122, reset transistor 123, amplification transistor 124, and selection transistor 125 in FIG.
  • a wiring 226 is formed on the gate electrode 224.
  • FIG. 5 shows an example of three-layer wiring. Gate electrode 224 and wiring 226 are insulated via insulating layer 227.
  • the semiconductor layer 221 is supported on a support substrate 230 with an insulating layer 227 interposed therebetween.
  • the support substrate 230 may be a glass substrate, a Si substrate, or a sapphire substrate.
  • a color filter 228 is formed for each pixel 120 on the back side of the semiconductor layer 221.
  • a microlens 229 is formed on the color filter 228 for each pixel 120.
  • the color filter 228 can have a Bayer array, for example.
  • FIG. 6 is a diagram showing a configuration example of a signal readout circuit for four columns according to the first embodiment.
  • pixels 120 are connected to each vertical signal line 132-1 to 132-4, respectively.
  • the amplification transistor 124 of each pixel 120 is connected to each vertical signal line 132-1 to 132-4 via a selection transistor 125, respectively.
  • a capacitor 133 is added to each vertical signal line 132-1 to 132-4.
  • This capacitor 133 can be used to sample and hold signals read out from each pixel 120 for each column.
  • This capacitance 133 may be a parasitic capacitance of each vertical signal line 132-1 to 132-4, or a capacitive element connected to each vertical signal line 132-1 to 132-4.
  • the selection transistor 125 of each pixel 120 can be used as a sample and hold switch that causes the capacitor 133 to sample and hold the signals transmitted via the vertical signal lines 132-1 to 132-4 for each column.
  • a signal line reset transistor 141 is electrically connected to each vertical signal line 132-1 to 132-4.
  • the signal line reset transistor 141 can reset the potentials VSL1 to VSL4 of the respective vertical signal lines 132-1 to 132-4.
  • a MOS transistor can be used for each signal line reset transistor 141.
  • a signal line reset signal ⁇ RT is applied to the gate of each signal line reset transistor 141.
  • the source of each signal line reset transistor 141 is connected to reset potential VR.
  • the reset potential VR may be set to a higher potential than the ground potential.
  • the signal readout circuit is provided with an AD conversion section that performs AD conversion for each column of the signals transmitted via each vertical signal line 132-1 to 132-4.
  • the AD converter is provided with a comparator 143 and a counter 146 for each column.
  • Each comparator 143 compares the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 with the reference signal RAP for each column.
  • the reference signal RAP may be a ramp signal.
  • Each counter 146 performs a counting operation for each column based on the comparison result of each comparator 143.
  • Each vertical signal line 132-1 to 132-4 is connected to an inverting input of a comparator 143 via each DC cut capacitor 144.
  • potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are applied to the inverting input of each comparator 143 via a DC cut capacitor 144, respectively. be done.
  • the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is applied to the inverting input of each comparator 143 via the DC cut capacitor 144, respectively. be done.
  • a reference signal RAP is input to a non-inverting input of each comparator 143 via a DC cut capacitor 145, respectively.
  • an auto-zero signal AZ is input to each comparator 143.
  • the autozero signal AZ activates autozero operation during the autozero period.
  • the charge accumulated in each DC cut capacitor 144 and 145 can be controlled so that the non-inverting input and the inverting input of comparator 143 are balanced.
  • connection switch 151 is provided in the signal readout circuit.
  • Connection switch 151 connects vertical signal lines 132-1 to 132-4 in different columns. At this time, the connection switch 151 is connected in series to the capacitor 133 for each column used for sampling and holding the signal read out from each pixel 120.
  • Each connection switch 151 can be provided between vertical signal lines 132-1 to 132-4 adjacent to each other in the row direction. Each connection switch 151 can be turned on/off based on open/close signals ⁇ Cn1 to ⁇ Cn4, respectively.
  • the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned on, so that each vertical signal line 132-1 to 132 -4 potentials VSL1 to VSL4 are set to potentials higher than 0V. Then, after the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned off, the selection transistor 125 of each pixel 120 is turned on, so that a signal is read out from each pixel 120. . At this time, charges corresponding to the signals read from each pixel 120 are accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4, respectively. Then, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 change based on the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4, respectively.
  • each comparator 143 connected to each vertical signal line 132-1 to 132-4, the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are compared with the reference signal RAP, and each comparison result COP1 COP4 is output from.
  • each comparator 143 can output the timing when the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 match the level of the reference signal RAP to each counter 146 as comparison results COP1 to COP4. .
  • Each counter 146 performs a counting operation based on the comparison results COP1 to COP4 of each comparator 143, and outputs a count value based on each counting operation.
  • the active control unit 119 in FIG. 2 activates one of the comparator 143 and the counter 146 that perform AD conversion for each of the vertical signal lines 132-1 to 132-4.
  • the active control unit 119 controls the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 among the comparators 143 and counter 146 provided corresponding to the vertical signal lines 132-1 to 132-4. 146 may be activated.
  • the active control unit 119 can set the control signal CTL of the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 to ACT.
  • the active control unit 119 can set the control signal CTL of the comparator 143 and counter 146 provided corresponding to each vertical signal line 132-2 to 132-4 to STB.
  • ACT can instruct activation
  • STB can instruct standby.
  • the comparator 143 connected to the vertical signal line 132-1 determines the timing at which the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 matches the level of the reference signal RAP as a comparison result COP1. It can be output to the counter 146 as follows. The counter 146 performs a counting operation based on the comparison result COP1 of the comparator 143, and outputs a count value based on the counting operation.
  • FIG. 7 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the first embodiment.
  • an example of the waveform of each part at the time of binning read-out is shown.
  • the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 and their average value are indicated by VSL.
  • pixel reset/VSL reset is performed in capacitive load readout (K11).
  • the pixel reset signal ⁇ PRT of each pixel 120 rises (t11)
  • the reset transistor 123 of each pixel 120 is turned on
  • the floating diffusion 126 of each pixel 120 is reset.
  • the reset level of the floating diffusion 126 of each pixel 120 can be set to the power supply potential Vdd.
  • the signal line reset signal ⁇ RT rises (t11), and the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned on, and each vertical signal line 132-1 to 132-4 is turned on. will be reset.
  • the reset level of each vertical signal line 132-1 to 132-4 is set to the reset potential VR via the signal line reset transistor 141 connected to each vertical signal line 132-1 to 132-4. .
  • the open/close signal ⁇ Cn* rises (t11), and a plurality of connection switches 151 among the connection switches 151 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the open/close signal ⁇ Cn* indicates a plurality of open/close signals selected from among the open/close signals ⁇ Cn1 to ⁇ Cn4.
  • the opening/closing signal ⁇ Cn* is one of the opening/closing signals ⁇ Cn1 to ⁇ Cn4.
  • the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are equalized.
  • the auto zero signal AZ rises (t11), and the auto zero operation of the comparator 143 connected to each vertical signal line 132-1 to 132-4 is activated. At this time, the charge accumulated in each DC cut capacitor 144 and 145 is controlled so that the non-inverting input and the inverting input of comparator 143 connected to each vertical signal line 132-1 to 132-4 are balanced. Then, the pixel reset signal ⁇ PRT falls, the open/close signal ⁇ Cn* falls, and the signal line reset signal ⁇ RT falls.
  • P-phase VSL settling/P-phase VSL sample hold is performed (K12).
  • the selection signal ⁇ SEL of each pixel 120 rises (t12), and the selection transistor 125 of each pixel 120 is turned on.
  • charges corresponding to the reset level of the floating diffusion 126 of each pixel 120 are applied to the capacitors 133 added to the vertical signal lines 132-1 to 132-4, respectively.
  • the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4.
  • P-phase binning/P-phase AD is performed (K13).
  • the selection signal ⁇ SEL of each pixel 120 falls (t13)
  • the open/close signal ⁇ Cn* rises and the auto-zero signal AZ falls.
  • the connection switches 151 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. .
  • the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143.
  • the comparators 143 and counters 146 provided corresponding to the vertical signal lines 132-1 to 132-4 only the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 are active. be converted into Further, the activated comparator 143 is supplied with a ramp signal as the reference signal RAP. Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the reset level is compared with the reference signal RAP.
  • the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1.
  • the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the reset levels read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted.
  • transfer/VSL reset is performed (K14).
  • the transfer signal ⁇ TG of each pixel 120 rises (t14)
  • the transfer transistor 122 of each pixel 120 is turned on, and the charge accumulated in the photodiode 121 of each pixel 120 is transferred to the floating diffusion 126 of each pixel 120.
  • Ru the signal line reset signal ⁇ RT rises (t14)
  • the signal line reset transistors 141 connected to each vertical signal line 132-1 to 132-4 are turned on, and each vertical signal line 132-1 to 132-4 is turned on. will be reset.
  • the reset level of each vertical signal line 132-1 to 132-4 is set to the reset potential VR via the signal line reset transistor 141 connected to each vertical signal line 132-1 to 132-4.
  • the transfer signal ⁇ TG falls, the open/close signal ⁇ Cn* falls, and the signal line reset signal ⁇ RT falls (t15).
  • D-phase VSL settling/D-phase VSL sample and hold is performed (K15).
  • the selection signal ⁇ SEL rises (t16), and the selection transistor 125 of each pixel 120 is turned on.
  • a charge corresponding to the signal level of the floating diffusion 126 of each pixel 120 is applied to the capacitor 133 added to each vertical signal line 132-1 to 132-4.
  • the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4.
  • D-phase binning/D-phase AD is performed (K16).
  • the opening/closing signal ⁇ Cn* rises.
  • the connection switches 151 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the charges accumulated in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. .
  • the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143.
  • the activated comparator 143 is supplied with a ramp signal as the reference signal RAP. Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the signal level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1. At this time, the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the signal level read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted.
  • FIG. 8 is a diagram showing a configuration example of a comparator applied to the signal readout circuit according to the first embodiment.
  • the comparator 143 includes a differential amplifier 501, a post-stage amplifier 502, an output circuit 503, and an AND circuit 504.
  • the rear stage amplifier 502 is connected to the rear stage of the differential amplifier 501, and the output circuit 503 is connected to the rear stage of the rear stage amplifier 502.
  • the AND circuit 504 is connected after the output circuit 503, and the counter 146 is connected after the AND circuit 504.
  • the differential amplifier 501 balances the comparator inputs CIN1 and CIN2 based on the auto-zero operation, and then outputs a voltage according to the difference between the comparator inputs CIN1 and CIN2.
  • Differential amplifier 501 includes PMOS transistors 511, 521, 551, 561, and 591, and NMOS transistors 531, 541, 571, and 581.
  • the PMOS transistor 511 and the NMOS transistor 531 are connected in series with each other.
  • PMOS transistor 521 and NMOS transistor 541 are connected in series with each other.
  • the sources of each PMOS transistor 511 and 521 are connected to power supply voltage VDDH, and the gate of each PMOS transistor 511 and 521 is connected to the drain of PMOS transistor 521. At this time, PMOS transistors 511 and 521 can constitute a current mirror.
  • PMOS transistor 591 is connected in parallel to PMOS transistor 511.
  • a PMOS transistor 551 is connected between the gate and drain of the NMOS transistor 531, and a PMOS transistor 561 is connected between the gate and drain of the NMOS transistor 541.
  • NMOS transistors 571 and 581 are connected in series with each other. The sources of each NMOS transistor 531 and 541 are grounded through a series circuit of NMOS transistors 571 and 581.
  • An auto-zero signal AZP is applied to the gate of each PMOS transistor 551 and 561, and a bias voltage BIAS is applied to the gate of the NMOS transistor 571.
  • NMOS transistor 571 can operate as a constant current source based on bias voltage BIAS.
  • a control signal XA is applied to the gate of the NMOS transistor 581.
  • a control signal XB is applied to the gate of the PMOS transistor 591.
  • Post-stage amplifier 502 amplifies the output of the differential amplifier 501.
  • Post-stage amplifier 502 includes a PMOS transistor 512, an NMOS transistor 522, and a switch 532.
  • the PMOS transistor 512 and the NMOS transistor 522 are connected in series with each other.
  • the source of PMOS transistor 512 is connected to power supply voltage VDDH, and the gate of PMOS transistor 512 is connected to the drain of PMOS transistor 511.
  • a switch 532 is connected between the gate and drain of the NMOS transistor 522, and the source of the NMOS transistor 522 is grounded. Switch 532 opens and closes based on auto-zero signal AZN.
  • the output circuit 503 converts the output of the subsequent stage amplifier 502 into a logical value '0' or a logical value '1'.
  • Output circuit 503 includes PMOS transistors 513 and 543 and NMOS transistors 523 and 533.
  • PMOS transistor 513 and NMOS transistor 523 are connected in series with each other, and NMOS transistors 523 and 533 are connected in series with each other.
  • the sources of PMOS transistors 513 and 543 are connected to power supply voltage VDDL, and the source of NMOS transistor 533 is grounded.
  • the drain of PMOS transistor 543 is connected to the drain of PMOS transistor 513.
  • Power supply voltage VDDL can be lower than power supply voltage VDDH.
  • the gate of the PMOS transistor 543 and the gate of the NMOS transistor 523 are connected to the drain of the PMOS transistor 512.
  • a control signal XC is applied to the gate of the PMOS transistor 513 and the gate of the NMOS transistor 533.
  • a first input terminal of the AND circuit 504 is connected to the drain of the PMOS transistor 513.
  • a control signal XD is applied to a second input terminal of the AND circuit 504.
  • Control signals XA, XB, XC, and XD are input to comparator 143 as control signal CTL in FIG.
  • control signals XA, XB, XC, and XD are set to low level.
  • NMOS transistors 533 and 581 are turned off, PMOS transistors 512 and 513 are turned on, and AND circuit 504 outputs a logic value of '0'.
  • control signals XA, XB, XC, and XD are set to high level.
  • NMOS transistors 533 and 581 are turned on, PMOS transistors 512 and 513 are turned off, and AND circuit 504 outputs a logical value '0' or '1' depending on the output from output circuit 503.
  • each PMOS transistor 551 and 561 is turned on based on the auto-zero signal AZP, and the switch 532 is closed based on the auto-zero signal AZN. Note that the timing at which each PMOS transistor 551 and 561 turns off after being turned on can be made later than the timing at which the switch 532 opens after closing. At this time, current flows through each PMOS transistor 551 and 561 based on the current mirror operation of PMOS transistors 511 and 521. Then, charges are accumulated in each of the DC cut capacitors 144 and 145 so that the non-inverting input and the inverting input of the comparator 143 are balanced.
  • the signal line reset transistor 141 performs binning based on the sampled and held signals for each column connected to each vertical signal line 132-1 to 132-4. This makes it possible to perform binning in the column direction while suppressing an increase in the area of the signal readout circuit, and to ensure linearity during binning without limiting the number of binnings.
  • AD converters that do not need to operate during binning processing can be set to a standby state, reducing power consumption. It is possible to aim for
  • the signal line reset transistor 141 performs binning based on signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4.
  • diode-connected transistors perform binning based on signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4 via a signal line reset transistor 141.
  • FIG. 9 is a diagram showing a configuration example of a signal readout circuit for four columns according to the second embodiment.
  • this signal readout circuit has a diode-connected transistor 142 added to the signal readout circuit of the first embodiment described above.
  • the other configuration of the signal readout circuit of the second embodiment is the same as that of the signal readout circuit of the first embodiment described above.
  • a diode-connected transistor 142 is connected in series to a signal line reset transistor 141 for each vertical signal line 132-1 to 132-4.
  • a MOS transistor can be used as the diode-connected transistor 142.
  • the gate of diode-connected transistor 142 is connected to the drain of diode-connected transistor 142.
  • the source of diode-connected transistor 142 is grounded.
  • the source of diode-connected transistor 142 may be connected to a potential higher than ground potential.
  • the diode-connected transistor 142 generates a voltage higher than 0V (for example, 0.5V), and changes the potential VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 to a potential higher than 0V via the signal line reset transistor 141.
  • the diode-connected transistor 142 is an example of a signal line reset level generation section described in the claims.
  • the operation of the signal readout circuit of the second embodiment during binning is similar to the operation of the signal readout circuit of the first embodiment during binning.
  • the diode-connected transistor 142 generates a signal sampled and held for each column connected to each vertical signal line 132-1 to 132-4 via the signal line reset transistor 141. Binning based on Thereby, the potential of each of the vertical signal lines 132-1 to 132-4 can be raised according to the forward voltage of the diode-connected transistor 142 when each of the vertical signal lines 132-1 to 132-4 is reset. Therefore, the potential of each vertical signal line 132-1 to 132-4 at the start of P-phase VSL settling can be made higher than 0V, and the settling time can be shortened.
  • connection switch 151 is connected in series with the capacitor 133 for each column used for sample and holding.
  • connection switches are connected in parallel to the capacitors for each column used for sample and holding.
  • FIG. 10 is a diagram showing a configuration example of a signal readout circuit for four columns according to the third embodiment.
  • this signal readout circuit includes a connection switch 152 in place of the connection switch 151 of the signal readout circuit of the first embodiment described above.
  • the other configuration of the signal readout circuit of the third embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • connection switch 152 connects the vertical signal lines 132-1 to 132-4 in different columns. At this time, the connection switch 152 is connected in parallel to the capacitor 133 for each column used for sampling and holding the signal read out from each pixel 120. Each connection switch 152 can be turned on/off based on the opening/closing signal ⁇ Cn. When using the connection switch 152, the number of binning in the column direction is fixed.
  • the operation of the signal readout circuit of the third embodiment during binning is similar to the operation of the signal readout circuit of the first embodiment during binning, except that the number of binnings in the column direction is fixed. be.
  • the signal line reset transistor 141 performs binning based on the signal sampled and held for each column connected to each vertical signal line 132-1 to 132-4. This makes it possible to perform binning in the column direction while suppressing an increase in the area of the signal readout circuit, and to ensure linearity during binning without limiting the number of binnings.
  • Fourth embodiment> In the first embodiment described above, binning is performed in the column direction based on signals sampled and held for each column. In this fourth embodiment, binning is performed in the column direction and row direction based on signals sampled and held for each column.
  • FIG. 11 is a diagram showing a configuration example of a signal readout circuit for two columns according to the fourth embodiment.
  • this signal readout circuit includes a cell 130 in place of the pixel 120 of the signal readout circuit of the first embodiment described above. Further, in this signal readout circuit, a binning line 140 is added to the signal readout circuit of the first embodiment described above.
  • the other configuration of the signal readout circuit of the fourth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the cells 130 are arranged in a matrix in the row and column directions. Cells 130 are connected to vertical signal lines 132-1 and 132-2 for each column.
  • the cell 130 includes photodiodes 121-1 to 121-4, transfer transistors 122-1 to 122-4, and a binning transistor 127 in place of the photodiode 121 and transfer transistor 122 of the first embodiment described above.
  • the other configuration of the cell 130 of the fourth embodiment is similar to the configuration of the pixel 120 of the first embodiment described above.
  • Each photodiode 121-1 to 121-4 can be arranged in two rows and two columns. Each of the photodiodes 121-1 to 121-4 is connected to the floating diffusion 126 via transfer transistors 122-1 to 122-4, respectively. Transfer signals ⁇ TG1 to ⁇ TG4 are applied to the gates of each of the transfer transistors 122-1 to 122-4. By controlling the application timing of these transfer signals ⁇ TG1 to ⁇ TG4, signals can be read out individually from each photodiode 121-1 to 121-4, or signals can be binned from each photodiode 121-1 to 121-4. You can also read it by The capacitive load readout operation for each photodiode 121-1 to 121-4 is similar to the capacitive load readout operation for the photodiode 121 of the first embodiment described above.
  • the binning transistor 127 is connected between the floating diffusion 126 and the binning line 140 for each cell 130.
  • Binning transistor 127 may be a MOS transistor.
  • a binning signal ⁇ BN is applied to the gate of the binning transistor 127 for each cell 130.
  • the binning signal ⁇ BN is set to low level and the binning transistor 127 of each cell 130 is turned off.
  • the binning signal ⁇ BN is set to a high level and the binning transistor 127 of each cell 130 is turned on.
  • the operation of the signal readout circuit of the fourth embodiment during binning in the row and column directions is similar to that of the signal readout circuit of the first embodiment, except that the binning transistor 127 of each cell 130 is turned on. The operation is similar to that during binning.
  • each photodiode 121-1 to 121-4 are added and averaged for 32 rows by 2 columns, and the signals of the cells 130 for 16 columns are added and averaged by capacitance.
  • the number of columns of the AD converter to be activated can be reduced to 1/16 of the individual readout of all pixels, and power consumption can be reduced.
  • each cell 130 is provided with a binning transistor 127 that connects cells 130 in different rows to each other.
  • binning can be performed not only in the column direction but also in the row direction, and it is possible to increase the number of binning operations while suppressing a decrease in spatial resolution in the row direction.
  • the average value of the signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4 is input to the comparator 143.
  • the average value of signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4 is inputted to a comparator 143 via an amplifier 161.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for four columns according to the fifth embodiment.
  • this signal readout circuit has an amplifier 161 added to the signal readout circuit of the first embodiment described above.
  • the rest of the configuration of the signal readout circuit of the fifth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the amplifier 161 amplifies the signals transmitted to the comparator 143 via each vertical signal line 132-1 to 132-4 for each column.
  • An amplifier 161 is provided for each vertical signal line 132-1 to 132-4.
  • Each amplifier 161 is connected to an inverting input terminal of each comparator 143 via a DC cut capacitor 144, respectively.
  • a control signal CTL is input to the amplifier 161.
  • the amplifier 161 in the same column as the comparator 143 and the counter 146 can be activated.
  • the amplifier 161 in the same column as these can be set to the standby state.
  • an amplifier 161 is provided for each vertical signal line 132-1 to 132-4, and a control signal CTL is input to each amplifier 161.
  • the signal transmitted to the comparator 143 can be amplified while suppressing an increase in power consumption during binning.
  • the selection transistor 125 is used as a sample and hold switch that samples and holds the signals transmitted via each vertical signal line 132-1 to 132-4 for each column.
  • each vertical signal line 132-1 to 132-4 is provided with a sample hold switch that samples and holds signals transmitted via each vertical signal line 132-1 to 132-4 for each column. establish.
  • FIG. 13 is a diagram showing a configuration example of a signal readout circuit for four columns according to the sixth embodiment.
  • this signal readout circuit has a sample and hold switch 153 and drivers 301 and 302 added to the signal readout circuit of the third embodiment described above.
  • the rest of the configuration of the signal readout circuit of the sixth embodiment is similar to the configuration of the signal readout circuit of the third embodiment described above.
  • the sample and hold switch 153 causes each capacitor 153 to sample and hold the signals transmitted via the vertical signal lines 132-1 to 132-4 for each column.
  • a sample hold switch 153 is provided on each vertical signal line 132-1 to 132-4.
  • Each sample hold switch 153 is turned on/off based on the sample hold signal ⁇ VS.
  • Each sample hold switch 153 may be a MOS transistor.
  • Each driver 301 and 302 drives the sample hold switch 153 from both sides in the row direction.
  • Each driver 301 and 302 can be shared by a sample hold switch 153 provided for each column.
  • FIG. 14 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the sixth embodiment. In addition, in the figure, an example of the waveform of each part at the time of binning readout is shown.
  • the binning read operation of the sixth embodiment is similar to the binning read operation of the first embodiment described above, except that a sample and hold signal ⁇ VS is added.
  • the sample hold signal ⁇ VS rises (t11) at the same time as the pixel reset signal ⁇ PRT rises in the pixel reset/VSL reset (K11). Further, the sample hold signal ⁇ VS falls before the selection signal ⁇ SEL falls in P-phase VSL settling/P-phase VSL sample hold (K12).
  • sample hold signal ⁇ VS rises simultaneously with the rise of the transfer signal ⁇ TG in the transfer/VSL reset (K14) (t14). Further, the sample hold signal ⁇ VS falls before the selection signal ⁇ SEL falls in D-phase VSL settling/D-phase VSL sample hold (K15).
  • the sample and hold switch 153 is provided to sample and hold the signals transmitted via each vertical signal line 132-1 to 132-4 for each column. This makes it possible to perform binning in the column direction while ensuring linearity during binning.
  • drivers 301 and 302 are provided to drive the sample and hold switch 153 from both sides in the row direction. Thereby, the driving force of the sample and hold switches 153 in each column can be increased without providing drivers 301 and 302 for each row to drive the sample and hold switches 153. Therefore, it is possible to reduce the in-plane difference in driving force, it is possible to reduce fixed pattern noise, and it is also possible to suppress an increase in the area required for arranging the drivers 301 and 302.
  • the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are connected to the activated columns and the inactivated columns via the DC cut capacitors 144, respectively. was input to each comparator 143.
  • the connection destination of the DC cut capacitor 144 is switched from the comparator input to the ground.
  • FIG. 15 is a diagram showing a configuration example of a signal readout circuit for four columns according to the seventh embodiment.
  • this signal readout circuit has changeover switches 154 and 155 added to the signal readout circuit of the first embodiment described above.
  • the other configuration of the signal readout circuit of the seventh embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the first capacitive electrode of the DC cut capacitor 144 in each column is connected to each vertical signal line 132-1 to 132-4.
  • Changeover switches 154 and 155 are provided for each column.
  • the changeover switch 154 is connected between the second capacitance electrode of the DC cut capacitor 144 in each column and the inverting input terminal of each comparator 143.
  • the changeover switch 155 is connected between the second capacitance electrode of the DC cut capacitor 144 in each column and the ground.
  • the changeover switch 154 is turned on, and the changeover switch 155 is turned off.
  • the changeover switch 154 is turned off and the changeover switch 155 is turned on. At this time, the changeover switches 154 and 155 are controlled separately for activated columns and deactivated columns.
  • the comparator 143 and counter 146 provided corresponding to the vertical signal line 132-1 are activated. shall be taken as a thing.
  • the changeover switch 154 connected to the vertical signal line 132-1 is turned on, and the changeover switch 155 is turned off.
  • the changeover switch 154 connected to each vertical signal line 132-2 to 132-4 is turned off, and the changeover switch 155 is turned on.
  • the open/close signals ⁇ Cn1 to ⁇ Cn4 are turned on. Therefore, the capacitance of the DC cut capacitor 144 connected to each vertical signal line 132-2 to 132-4 is added to the capacitance 133 of the vertical signal line 132-1.
  • the connection destination of the DC cut capacitor 144 is switched from the comparator input to the ground.
  • the capacitance added to the vertical signal line 132-1 of the activated column can be increased, and kTC noise can be reduced.
  • FIG. 16 is a diagram showing a configuration example of a signal readout circuit for four columns according to the eighth embodiment.
  • this signal readout circuit includes a current source 401 in place of the signal line reset transistor 141 of the signal readout circuit of the first embodiment described above. Further, this signal readout circuit has a connection switch 402, sample and hold switches 403 and 404, and a capacitor 405 added to the signal readout circuit of the first embodiment described above.
  • the rest of the configuration of the signal readout circuit of the eighth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the current source 401 can be provided for each column. Each current source 401 is connected to vertical signal lines 132-1 to 132-4. Current source 401 may be a MOS transistor.
  • the sample and hold switches 403 and 404 cause the capacitor 405 to sample and hold the signals transmitted via the vertical signal lines 132-1 to 132-4 for each column.
  • Sample and hold switches 403 and 404 are provided on each vertical signal line 132-1 to 132-4. At this time, each sample hold switch 403 is connected in series to the vertical signal lines 132-1 to 132-4, respectively.
  • Each sample hold switch 404 is connected between each vertical signal line 132-1 to 132-4 and a capacitor 405.
  • Each sample hold switch 403 is turned on/off based on the sample hold signal ⁇ VS.
  • Each sample hold switch 404 is turned on/off based on the sample hold signal ⁇ S.
  • Each sample and hold switch 403 and 404 may be a MOS transistor.
  • the capacity 405 can be provided for each column. Each capacitor 405 is connected to each vertical signal line 132-1 to 132-4 via a sample and hold switch 404, respectively. The capacitor 405 can be used to sample and hold signals read out from each pixel 120 for each column.
  • connection switch 402 connects the vertical signal lines 132-1 to 132-4 in different columns. At this time, the connection switch 402 is connected in parallel to the capacitor 405 for each column used to sample and hold the signal read out from each pixel 120. Each connection switch 402 may be a MOS transistor. Each connection switch 402 is turned on/off based on the opening/closing signal ⁇ Cn.
  • FIG. 17 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the eighth embodiment. In addition, in the figure, an example of the waveform of each part at the time of binning read-out is shown.
  • pixel reset is performed in constant current readout (K21).
  • the pixel reset signal ⁇ PRT of each pixel 120 rises (t21)
  • the reset transistor 123 of each pixel 120 is turned on
  • the floating diffusion 126 of each pixel 120 is reset.
  • the selection signal ⁇ SEL of each pixel 120 rises (t21)
  • the selection transistor 125 of each pixel 120 is turned on.
  • the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the source follower operation when the power supply potential Vdd is applied to the gate of the amplification transistor 124 of each pixel 120.
  • sample and hold signal ⁇ S rises (t21), and the sample and hold switches 404 connected to each of the vertical signal lines 132-1 to 132-4 are turned on. At this time, the capacitors 405 provided for each column are connected to the vertical signal lines 132-1 to 132-4 via the sample and hold switches 404, respectively.
  • sample and hold signal ⁇ VS rises (t21), and the sample and hold switches 403 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the capacitors 405 provided for each column are connected to the pixels 120 for each column via the vertical signal lines 132-1 to 132-4, respectively.
  • the auto zero signal AZ rises (t21), and the auto zero operation of the comparator 143 connected to each vertical signal line 132-1 to 132-4 is activated. At this time, the charge accumulated in each DC cut capacitor 144 and 145 is controlled so that the non-inverting input and the inverting input of comparator 143 connected to each vertical signal line 132-1 to 132-4 are balanced.
  • P-phase VSL settling/P-phase VSL sample and hold is performed (K22).
  • the pixel reset signal ⁇ PRT of each pixel 120 falls (t22), and the reset transistor 123 of each pixel 120 is turned off.
  • the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are applied. is set. Charges corresponding to the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are sampled and held in the capacitor 405 for each column. After that, the sample and hold signal ⁇ VS falls.
  • P-phase binning/P-phase AD is performed (K23).
  • the opening/closing signal ⁇ Cn rises (t23) and the auto-zero signal AZ falls.
  • the connection switches 402 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the charges accumulated in the capacitors 405 added to each vertical signal line 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are averaged. .
  • the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143.
  • the activated comparator 143 is supplied with a ramp signal as the reference signal RAP. Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the reset level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1.
  • the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the reset levels read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted. After that, the opening/closing signal ⁇ Cn falls.
  • transfer is performed (K24).
  • the transfer signal ⁇ TG of each pixel 120 rises (t24)
  • the transfer transistor 122 of each pixel 120 is turned on, and the charge accumulated in the photodiode 121 of each pixel 120 is transferred to the floating diffusion 126 of each pixel 120.
  • Ru Furthermore, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are adjusted based on the source follower operation when the cathode potential of the photodiode 121 of each pixel 120 is applied to the gate of the amplification transistor 124 of each pixel 120. is set.
  • sample and hold signal ⁇ VS rises (t24), and the sample and hold switches 403 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the capacitors 405 provided for each column are connected to the pixels 120 for each column via the vertical signal lines 132-1 to 132-4, respectively.
  • D-phase VSL settling/D-phase VSL sample and hold is performed (K25).
  • the transfer signal ⁇ TG of each pixel 120 falls (t25), and the transfer transistor 122 of each pixel 120 is turned off.
  • the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are applied. is set. Charges corresponding to the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are sampled and held in the capacitor 405 for each column. After that, the sample and hold signal ⁇ VS falls.
  • D-phase binning/P-phase AD is performed (K26).
  • the opening/closing signal ⁇ Cn rises (t26), and the connection switches 402 connected to each of the vertical signal lines 132-1 to 132-4 are turned on.
  • the charges accumulated in the capacitors 405 added to each vertical signal line 132-1 to 132-4 are binned, and the potentials VSL1 to VSL4 of each vertical signal line 132-1 to 132-4 are averaged. .
  • the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143. Further, a ramp signal is supplied to the activated comparator 143 as the reference signal RAP (t26-t27).
  • the activated comparator 143 the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 according to the signal level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1. At this time, the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4.
  • the average value of the signal level read from each pixel 120 connected to each vertical signal line 132-1 to 132-4 is AD converted. After that, the sample hold signal ⁇ S and the open/close signal ⁇ Cn fall, and the selection signal ⁇ SEL of each pixel 120 falls.
  • Ninth embodiment> In the second embodiment described above, binning was performed based on capacitive load reading.
  • a constant current transistor is connected in parallel to a series circuit of a signal line reset transistor 141 and a diode-connected transistor 142, so that constant current reading and capacitive load reading can be switched.
  • FIG. 18 is a block diagram showing a configuration example of a signal readout circuit for one column according to the ninth embodiment. Although the figure shows a signal readout circuit for one column, the same configuration can be applied to other columns as well.
  • this signal readout circuit has a sample and hold circuit 201 and a constant current transistor 301 added to the signal readout circuit of the second embodiment described above.
  • the other configuration of the signal readout circuit of the ninth embodiment is similar to the configuration of the signal readout circuit of the second embodiment described above.
  • the sample and hold circuit 201 samples and holds the bias voltage Vb and applies it to the gate of the constant current transistor 301.
  • Sample and hold circuit 201 includes a transistor 211 and a capacitor 212.
  • Transistor 211 may be a MOS transistor.
  • a sample and hold signal ⁇ SH is applied to the gate of the transistor 211.
  • Capacitor 212 is connected between the source of transistor 211 and ground potential.
  • the constant current transistor 301 is electrically connected to the vertical signal line 132-1.
  • Constant current transistor 301 may be a MOS transistor.
  • the gate of constant current transistor 301 is connected to the output of sample hold circuit 201.
  • bias voltage Vb is set to 0V and sample hold signal ⁇ SH is set to high level.
  • the constant current transistor 301 is turned off, and no current flows through the constant current transistor 301.
  • the operation of the signal readout circuit at this time is similar to the operation of the signal readout circuit of the first embodiment described above.
  • the transistor 211 In constant current readout, the transistor 211 is turned on and the bias voltage Vb is sampled and held in order to prevent horizontal scanning noise during AD conversion. Then, the transistor 211 is turned off, and the bias voltage Vb sampled and held by the sample and hold circuit 201 is applied to the gate of the constant current transistor 301. In this case, the constant current transistor 301 is turned on, and a constant current flows through the constant current transistor 301.
  • the operation of the signal readout circuit at this time is similar to the operation of the signal readout circuit of the eighth embodiment described above.
  • the constant current transistor 301 is connected in parallel to the series circuit of the signal line reset transistor 141 and the diode-connected transistor 142. This makes it possible to perform binning in the column direction while suppressing an increase in the area of the signal readout circuit, and to switch between constant current readout and capacitive load readout.
  • the signal line reset transistor 141 performs binning based on signals sampled and held for each column connected to each vertical signal line 132-1 to 132-4.
  • substrates on which a solid-state imaging device including a pixel array section in which pixels 120 are arranged in a matrix are formed are laminated.
  • FIG. 19 is a perspective view showing a configuration example of an imaging device according to the tenth embodiment.
  • the solid-state imaging device 901 includes a support substrate 911 and a semiconductor substrate 912.
  • a semiconductor substrate 912 is stacked on a support substrate 911.
  • a pixel array section 913 and a peripheral circuit 914 are formed on the semiconductor substrate 912.
  • a column readout circuit 915 and a column ADC 916 are formed in the peripheral circuit 914.
  • the column readout circuit 915 and the column ADC 916 may be formed on both sides of the pixel array section 913 in the column direction.
  • pixels 120 are arranged in a matrix along the row and column directions.
  • the column readout circuit 915 can read signals from each pixel 120 individually based on capacitive load readout, or can perform binning and readout.
  • the signal line reset transistor 141 and connection switch 151 in FIG. 6 may be formed in the column readout circuit 915.
  • the column ADC 916 can AD convert signals read out via the column readout circuit 915 for each column.
  • the solid-state imaging device 901 can constitute a back-illuminated image sensor.
  • the solid-state imaging device 902 includes semiconductor substrates 921 and 922.
  • a semiconductor substrate 922 is stacked on the semiconductor substrate 921.
  • a pixel array section 923 is formed on the semiconductor substrate 922.
  • a peripheral circuit 924 is formed on the semiconductor substrate 922 .
  • a column readout circuit 925 and a column ADC 926 are formed.
  • the column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction.
  • the solid-state imaging device 902 can constitute a back-illuminated image sensor.
  • the substrates on which the solid-state imaging devices 901 and 902 are formed are laminated.
  • the semiconductor substrates 912 and 922 on which each pixel array section 913 and 923 are formed can be thinned, and a back-illuminated image sensor can be formed. can.
  • the technology according to the present disclosure (this technology) can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as a car, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, robot, etc. It's okay.
  • FIG. 20 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output section 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 includes a drive force generation device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits the drive force to wheels, and a drive force transmission mechanism that controls the steering angle of the vehicle. It functions as a control device for a steering mechanism to adjust and a braking device to generate braking force for the vehicle.
  • the body system control unit 12020 controls the operations of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a turn signal, or a fog lamp.
  • radio waves transmitted from a portable device that replaces a key or signals from various switches may be input to the body control unit 12020.
  • the body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, power window device, lamp, etc. of the vehicle.
  • the external information detection unit 12030 detects information external to the vehicle in which the vehicle control system 12000 is mounted.
  • an imaging section 12031 is connected to the outside-vehicle information detection unit 12030.
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the external information detection unit 12030 may perform object detection processing such as a person, car, obstacle, sign, or text on the road surface or distance detection processing based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electrical signal as an image or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • a driver condition detection section 12041 that detects the condition of the driver is connected to the in-vehicle information detection unit 12040.
  • the driver condition detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver condition detection unit 12041. It may be calculated, or it may be determined whether the driver is falling asleep.
  • the microcomputer 12051 calculates control target values for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and Control commands can be output to 12010.
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of autonomous driving, etc., which does not rely on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of preventing glare, such as switching from high beam to low beam. It can be carried out.
  • the audio and image output unit 12052 transmits an output signal of at least one of audio and images to an output device that can visually or audibly notify information to the occupants of the vehicle or to the outside of the vehicle.
  • an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 21 is a diagram showing an example of the installation position of the imaging section 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle 12100.
  • An imaging unit 12101 provided in the front nose and an imaging unit 12105 provided above the windshield inside the vehicle mainly acquire images in front of the vehicle 12100.
  • Imaging units 12102 and 12103 provided in the side mirrors mainly capture images of the sides of the vehicle 12100.
  • An imaging unit 12104 provided in the rear bumper or back door mainly captures images of the rear of the vehicle 12100.
  • the imaging unit 12105 provided above the windshield inside the vehicle is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 21 shows an example of the imaging range of the imaging units 12101 to 12104.
  • An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • an imaging range 12114 shows the imaging range of the imaging unit 12101 provided on the front nose.
  • the imaging range of the imaging unit 12104 provided in the rear bumper or back door is shown. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of image sensors, or may be an image sensor having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. In particular, by determining the three-dimensional object closest to the vehicle 12100 on its path and traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km/h or more), it is possible to extract the three-dimensional object as the preceding vehicle. can. Furthermore, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, cooperative control can be performed for the purpose of autonomous driving, etc., which does not rely on the driver's operation.
  • automatic brake control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 transfers three-dimensional object data to other three-dimensional objects such as two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, and utility poles based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceeds a set value and there is a possibility of a collision, the microcomputer 12051 transmits information via the audio speaker 12061 and the display unit 12062. By outputting a warning to the driver via the vehicle control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
  • the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceed
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101 to 12104.
  • pedestrian recognition involves, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and a pattern matching process is performed on a series of feature points indicating the outline of an object to determine whether it is a pedestrian or not.
  • the audio image output unit 12052 creates a rectangular outline for emphasis on the recognized pedestrian.
  • the display unit 12062 is controlled to display the .
  • the audio image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above.
  • the above-described camera 100 can be applied to the imaging unit 12031.
  • a pixel array section in which pixels are arranged in a matrix in the row direction and column direction; a signal line that transmits a signal read out from the pixel in the column direction; a sample hold switch that samples and holds the signal transmitted via the signal line for each column;
  • An imaging device comprising: a connection switch that connects signal lines of different columns in which the signals are sampled and held.
  • an AD converter that performs AD conversion for each column of signals transmitted via the signal line;
  • the AD conversion section a comparator that compares the potential of the signal line and the ramp signal;
  • the imaging device according to (2) further comprising a counter that performs a counting operation based on a comparison result of the comparator.
  • the solid-state imaging device according to (3) wherein the active control section controls the AD conversion section separately into an activated column and a deactivated column.
  • a first DC cut capacitor connected to the first input terminal of the comparator;
  • the active control unit is configured to switch a connection destination of a second capacitance electrode of the first DC cut capacitor, the first capacitance electrode of which is connected to the signal line, between a first input terminal of the comparator and ground.
  • the imaging device according to (5) above further comprising a switch.
  • the imaging device according to any one of (1) to (9), wherein the sample and hold switch is a transistor provided for each of the signal lines.
  • the imaging device (10), further comprising a driver that drives the transistor from both sides in the row direction.
  • a signal line reset transistor that resets the potential of the signal line;
  • the imaging device according to any one of (1) to (11), further comprising a signal line reset level generation unit that generates a reset level of the potential of the signal line.
  • the signal line reset level generation section includes a diode-connected transistor.
  • the imaging device according to any one of (1) to (13), wherein the capacitance used to sample and hold the signal is a parasitic capacitance of the signal line.
  • connection switch is connected in series to a capacitor for each column used for sample-holding the signal.
  • connection switch is connected in parallel to a capacitor for each column used for sample-holding the signal.
  • constant current transistor that is electrically connectable to the signal line and that flows a constant current based on a source follower formed between the pixel; For constant current readout, the constant current transistor is turned on; The imaging device according to any one of (1) to (16), wherein the constant current transistor is turned off during capacitive load reading.
  • the pixel is photodiode and a transfer transistor that transfers the charge accumulated in the photodiode to a floating diffusion; a reset transistor that resets the floating diffusion; an amplification transistor that outputs a signal according to the potential of the floating diffusion;

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Abstract

La présente invention permet un compartimentage tout en supprimant une augmentation du nombre de commutateurs connectés à une ligne de signal pour transmettre, dans une direction de colonne, des signaux lus à partir de pixels.　Ce dispositif d'imagerie comprend : une partie de réseau de pixels dans laquelle des pixels sont agencés selon une forme de matrice dans une direction de rangée et une direction de colonne; des lignes de signal qui transmettent, dans une direction de colonne, des signaux lus à partir des pixels; un commutateur d'échantillonnage et de maintien pour échantillonner et maintenir, pour chaque colonne, un signal transmis par le biais de la ligne de signal; et un commutateur de connexion qui connecte des lignes de signal de colonnes mutuellement différentes sur lesquelles des signaux ont été échantillonnés et maintenus. Le dispositif d'imagerie peut en outre comprendre : une unité de conversion A/N qui convertit A/N, dans chaque colonne, des signaux transmis par le biais de la ligne de signal; et une unité de commande active qui active une unité de conversion A/N parmi les unités de conversion A/N des colonnes connectées par le biais du commutateur de connexion.
PCT/JP2023/024442 2022-08-25 2023-06-30 Dispositif d'imagerie WO2024042864A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010245951A (ja) * 2009-04-08 2010-10-28 Nikon Corp 撮像素子及び撮像装置
JP2016052055A (ja) * 2014-09-01 2016-04-11 キヤノン株式会社 撮像装置
JP2018139374A (ja) * 2017-02-24 2018-09-06 キヤノン株式会社 撮像装置および撮像システム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010245951A (ja) * 2009-04-08 2010-10-28 Nikon Corp 撮像素子及び撮像装置
JP2016052055A (ja) * 2014-09-01 2016-04-11 キヤノン株式会社 撮像装置
JP2018139374A (ja) * 2017-02-24 2018-09-06 キヤノン株式会社 撮像装置および撮像システム

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