WO2024135091A1 - Imaging device - Google Patents

Imaging device Download PDF

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Publication number
WO2024135091A1
WO2024135091A1 PCT/JP2023/038719 JP2023038719W WO2024135091A1 WO 2024135091 A1 WO2024135091 A1 WO 2024135091A1 JP 2023038719 W JP2023038719 W JP 2023038719W WO 2024135091 A1 WO2024135091 A1 WO 2024135091A1
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Prior art keywords
signal
pixel
pixels
unit
imaging device
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PCT/JP2023/038719
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French (fr)
Japanese (ja)
Inventor
守 佐藤
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2024135091A1 publication Critical patent/WO2024135091A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/703—SSIS architectures incorporating pixels for producing signals other than image signals
    • H04N25/708—Pixels for edge detection

Definitions

  • This technology relates to an imaging device. More specifically, this technology relates to an imaging device capable of detecting edges in an image.
  • Some imaging devices detect edges based on the results of comparing the brightness of adjacent pixels.
  • a solid-state imaging device has been proposed that generates an edge signal by including a circuit that compares electrical signals from adjacent rows transferred at different times onto a vertical readout line (see, for example, Patent Document 1).
  • This technology was developed in light of these circumstances, and aims to make it possible to use pixel signals that are not used to generate edge signals as gradation signals.
  • a first aspect of the technology is an imaging device that includes a readout circuit that reads out pixel signals from pixels in units of kernels that are subjected to convolution processing, and a signal processing unit that performs processing to generate an edge signal based on pixel signals of some of the pixels read out in units of kernels, and performs processing to generate a gradation signal based on pixel signals that include at least pixels that are not used to generate the edge signal among the pixels read out in units of kernels.
  • the signal processing unit may generate the edge signal and then generate the gradation signal within the same frame. This provides the effect of generating the edge signal and the gradation signal based on pixel signals within the same frame.
  • the readout circuit may non-destructively read out from the pixel the pixel signal used to generate the edge signal, and then non-destructively read out from the pixel the pixel signal used to generate the gradation signal. This provides the effect of generating a gradation signal including the pixel signal used to generate the edge signal.
  • the pixels used to generate the edge signal may be selected so that their rows and columns are different from each other. This has the effect of preventing an increase in the number of signal lines used to read out the pixel signals used to generate the edge signal, while making it possible to read out the pixel signals used to generate the edge signal in bulk on a kernel basis.
  • the gradation signal may be generated based on the binning values of the pixel signals of all pixels read out on a kernel-by-kernel basis. This brings about the effect that the AD conversion unit used to generate the edge signal and the gradation signal can be shared on a kernel-by-kernel basis.
  • an edge signal may be generated based on AD conversion of the signal level, and for all pixels read out in units of kernels, after an auto-zero operation based on the binning value of the signal level, a gradation signal may be generated based on AD conversion of the binning value of the reset level. This provides the effect of non-destructively reading out the pixel signals used to generate the edge signal and the pixel signals used to generate the gradation signal from the pixels.
  • the gradation signal may be generated based on a binning value of pixel signals that do not include pixels used to generate the edge signal among the pixels read out on a kernel basis. This has the effect of enabling CDS (Correlated Double Sampling) to generate the gradation signal while sharing the AD conversion unit used to generate the edge signal and the gradation signal on a kernel basis.
  • CDS Correlated Double Sampling
  • an edge signal may be generated based on AD conversion of a signal level, and for pixels read out in units of kernels that do not include the pixel used to generate the edge signal, a gradation signal may be generated based on AD conversion of a binning value of a signal level after an auto-zero operation based on a binning value of a reset level. This provides the effect of generating a gradation signal based on a CDS after the edge signal is generated.
  • the size of the kernel unit may be equal when the edge signal is generated and when the gradation signal is generated. This provides the effect that the edge signal and the gradation signal are generated based on the same kernel unit.
  • the size of the kernel unit may be different when the edge signal is generated and when the gradation signal is generated. This provides the effect that the edge signal and the gradation signal are generated based on kernel units that are different from each other.
  • the signal processing unit may include an AD conversion unit used to generate the edge signal and the gradation signal
  • the readout circuit may include a multiplexer that switches the connection between the AD conversion unit and a signal line that transmits the pixel signal in the column direction for generating the edge signal and the gradation signal.
  • the AD conversion unit may include at least one of a flash AD converter and a single-slope AD converter. This provides the effect of performing AD conversion based on the result of comparison with a level signal or a ramp signal.
  • a reference signal generating unit may be further provided that generates a reference signal to be input to the AD conversion unit. This provides the effect of AD-converting the pixel signal based on the comparison result with the reference signal.
  • the reference signal generating unit may include a first reference signal generating unit that generates a plurality of level signals, a second reference signal generating unit that generates a ramp signal, and a reference signal switching unit that switches between the output of the level signal and the output of the ramp signal. This provides the effect of generating low gradation signals and high gradation signals while sharing the AD conversion unit.
  • the AD conversion unit may include a comparator shared between generating the edge signal and generating the gradation signal, and the multiplexer may switch the connection between the signal line and the AD conversion unit so that pixel signals from two pixels are input to the comparator when generating the edge signal, and may switch the connection between the signal line and the AD conversion unit so that the pixel signal read out on a kernel basis and a reference signal to be compared with the pixel signal are input to the comparator when generating the gradation signal.
  • This provides the effect of generating edge signals and gradation signals while sharing a comparator.
  • the AD conversion unit may be shared between generating the edge signal and generating the gradation signal, and also used to generate an image signal on a pixel-by-pixel basis
  • the multiplexer may switch the connection between the signal line and the AD conversion unit so that pixel signals from two pixels are input to the comparator when generating the edge signal, switch the connection between the signal line and the AD conversion unit so that the pixel signal read out on a kernel-by-kernel basis and a reference signal to be compared with the pixel signal are input to the comparator when generating the gradation signal, and switch the connection between the signal line and the AD conversion unit so that the pixel signal read out on a pixel-by-pixel basis and a reference signal to be compared with the pixel signal are input to the comparator when generating the image signal.
  • a transfer control driver that controls the transfer of the charge accumulated in the pixel
  • a selection control driver that controls the selection of the pixel from which the pixel signal is read
  • a reset control driver that controls the resetting of the charge accumulated in the pixel
  • a binning control driver that controls the binning of the charge accumulated in the pixel
  • the pixel may include a binning transistor that connects the floating diffusion of the pixel to the floating diffusion of another pixel. This provides the effect of generating binned pixel signals for each of the different rows and columns.
  • connection switch may be provided that connects the signal lines that transmit the pixel signals in the column direction between different columns. This provides the effect of generating binned pixel signals for different columns.
  • an exposure control unit may be further provided that performs exposure control based on the gradation signal. This provides the effect of optimizing the level of the pixel signal used to generate the edge signal.
  • FIG. 1 is a block diagram showing an example of the configuration of a camera to which an imaging device according to a first embodiment is applied; 1 is a block diagram illustrating an example of a configuration of a solid-state imaging device according to a first embodiment.
  • 2 is a circuit diagram showing a configuration example of a pixel provided in the solid-state imaging device according to the first embodiment; 2 is a cross-sectional view showing a configuration example of a pixel array section provided in the solid-state imaging device according to the first embodiment; 10 is a cross-sectional view showing a modified example of a pixel array portion provided in the solid-state imaging device according to the first embodiment.
  • FIG. 3 is a block diagram showing a readout method of the solid-state imaging device according to the first embodiment; FIG.
  • FIG. 4 is a block diagram showing an example of switching of signal paths when an edge image is generated by the solid-state imaging device according to the first embodiment
  • FIG. 4 is a block diagram showing an example of switching of signal paths when a low gradation image is generated by the solid-state imaging device according to the first embodiment
  • FIG. 5 is a timing chart showing an example of waveforms of various parts when an edge image and a low gradation image are generated by the solid-state imaging device according to the first embodiment.
  • 5A and 5B are diagrams illustrating a relationship between a gradation signal of a low gradation image and a reference signal by the solid-state imaging device according to the first embodiment.
  • FIG. 4 is a block diagram showing an example of switching of signal paths when a high-gradation image is generated by the solid-state imaging device according to the first embodiment
  • FIG. 5 is a timing chart showing an example of waveforms at various parts when a high-gradation image is generated by the solid-state imaging device according to the first embodiment.
  • 2A to 2C are diagrams illustrating an example of an image generated by the solid-state imaging device according to the first embodiment.
  • 2 is a circuit diagram showing a configuration example of a pixel array section of a solid-state imaging device according to a first embodiment
  • 4 is a diagram illustrating an example of a configuration of a comparator applied to the signal readout circuit according to the first embodiment;
  • FIG. 4 is a flowchart illustrating an example of an exposure control method for the solid-state imaging device according to the first embodiment.
  • 13 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to a second embodiment generates a low-tone image.
  • FIG. 10 is a timing chart showing an example of waveforms of various parts when an edge image and a low gradation image are generated by a solid-state imaging device according to a second embodiment.
  • 13 is a circuit diagram illustrating an example of a level signal generating unit of a solid-state imaging device according to a second embodiment.
  • FIG. 13 is a block diagram showing a readout method of a solid-state imaging device according to a third embodiment.
  • FIG. 13 is a circuit diagram showing a configuration example of a pixel array section of a solid-state imaging device according to a third embodiment.
  • FIG. 13 is a block diagram showing a readout method of a solid-state imaging device according to a fourth embodiment.
  • FIG. 13 is a circuit diagram showing a configuration example of a pixel array section of a solid-state imaging device according to a fourth embodiment.
  • 13A to 13C are diagrams illustrating a readout method of a solid-state imaging device according to a fifth embodiment.
  • 13 is a timing chart showing an example of waveforms of various parts when an edge image and a low gradation image are generated by a solid-state imaging device according to a fifth embodiment.
  • FIG. 13 is a circuit diagram showing a configuration example of a pixel array section of a solid-state imaging device according to a third embodiment.
  • FIG. 13 is a block diagram showing a readout method of a solid-state imaging device according to a fourth embodiment.
  • FIG. 23 is a block diagram showing an example of switching of signal paths when an edge image is generated by a solid-state imaging device according to a sixth embodiment.
  • FIG. 23 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to a sixth embodiment generates a low-tone image.
  • 23 is a timing chart showing an example of waveforms of various parts when an edge image and a low gradation image are generated by a solid-state imaging device according to a sixth embodiment.
  • FIG. 13 is a circuit diagram showing a configuration example of a pixel array section of a solid-state imaging device according to a sixth embodiment.
  • FIG. 23 is a block diagram showing an example of switching of signal paths when a gradation image is generated by a solid-state imaging device according to a seventh embodiment.
  • 23 is a timing chart showing an example of waveforms of various parts when an edge image and a gradation image are generated by a solid-state imaging device according to a seventh embodiment.
  • FIG. 23 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to an eighth embodiment generates a low-tone image.
  • FIG. 23 is a circuit diagram showing a configuration example of a gain section of a solid-state imaging device according to an eighth embodiment.
  • FIG. 23 is a circuit diagram showing an example of the configuration of a pixel provided in a solid-state imaging device according to a ninth embodiment.
  • FIG. 23 is a circuit diagram showing a configuration example of a pixel array section of a solid-state imaging device according to a ninth embodiment.
  • FIG. 23 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to a tenth embodiment generates a low-tone image.
  • 23 is a timing chart showing an example of waveforms of various parts when an edge image and a low gradation image are generated by a solid-state imaging device according to a tenth embodiment.
  • FIG. 23 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to an eleventh embodiment generates a low-tone image.
  • FIG. 23 is a timing chart showing an example of waveforms at various parts when an edge image and a low gradation image are generated by a solid-state imaging device according to an eleventh embodiment.
  • FIG. 23 is a block diagram illustrating an example of the configuration of a solid-state imaging device according to a twelfth embodiment.
  • FIG. 23 is a block diagram showing an example of switching of signal paths when an edge image is generated by a solid-state imaging device according to a twelfth embodiment.
  • FIG. 23 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to a twelfth embodiment generates a low-tone image.
  • FIG. 23 is a timing chart showing an example of waveforms at various parts when an edge image and a low gradation image are generated by a solid-state imaging device according to an eleventh embodiment.
  • FIG. 23 is a block diagram illustrating an example of the configuration of a solid-state imaging device according to a twelfth
  • FIG. 23 is a block diagram illustrating an example of the configuration of a solid-state imaging device according to a thirteenth embodiment.
  • FIG. 23 is a perspective view showing an example of the configuration of an imaging device according to a fourteenth embodiment.
  • 1 is a block diagram showing a schematic configuration example of a vehicle control system;
  • FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit.
  • First embodiment an example of generating an edge image and a low-tone image based on a kernel unit of 4 ⁇ 4 pixels
  • Second embodiment an example in which an edge image and a low-tone image are generated based on a kernel unit of 4 ⁇ 4 pixels, and the gradation of the low-tone image is expanded
  • Third embodiment an example of generating an edge image and a low-tone image based on a kernel unit of 2 ⁇ 2 pixels
  • Fourth embodiment an example of generating an edge image and a low-tone image based on a kernel unit of 3 ⁇ 3 pixels.
  • Tenth embodiment (example of connecting vertical signal lines between different columns during binning) 11. Eleventh embodiment (example of sampling and holding pixel signals for each column during binning) 12. Twelfth embodiment (example in which AD conversion units are separated for generating edge images and generating low gradation images) 13. Thirteenth embodiment (an example in which the AD conversion unit is divided into an edge image generation unit and a low gradation image generation unit, and the AD conversion unit used for generating the low gradation image is a successive approximation type AD conversion unit) 14. Fourteenth embodiment (an example in which substrates on which solid-state imaging devices are formed are stacked) 15. Examples of applications to moving objects
  • FIG. 1 is a block diagram showing an example of the configuration of a camera to which an imaging device according to a first embodiment is applied.
  • the camera 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a memory unit 105, a display unit 106, and an operation unit 107.
  • the imaging control unit 103, the image processing unit 104, the memory unit 105, the display unit 106, and the operation unit 107 are connected to each other via a bus 108.
  • the camera 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, or may be incorporated into an authentication device or a monitoring device.
  • the optical system 101 allows light from a subject to be incident on the solid-state imaging device 102, and forms an image of the subject on the light receiving surface of the solid-state imaging device 102.
  • the optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture.
  • the optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.
  • the solid-state imaging device 102 converts the light from the subject into an electrical signal for each pixel, and then digitizes and outputs the electrical signal.
  • the solid-state imaging device 102 may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device).
  • the solid-state imaging device 102 may be a back-illuminated solid-state imaging device.
  • the light received by the solid-state imaging device 102 may be visible light, near infrared light (NIR: Near InfraRed), short wave infrared light (SWIR: Short Wavelength InfraRed), ultraviolet light, X-rays, or the like.
  • NIR Near InfraRed
  • SWIR Short Wavelength InfraRed
  • ultraviolet light X-rays, or the like.
  • the imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.
  • the image processing unit 104 performs image processing based on the output from the solid-state imaging device 102.
  • the image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing.
  • the image processing unit 104 may include a processor that executes processing based on software.
  • the storage unit 105 stores images captured by the solid-state imaging device 102, and stores imaging parameters of the solid-state imaging device 102.
  • the storage unit 105 can also store programs that operate the camera 100 based on software.
  • the storage unit 105 may include a ROM (Read Only Memory), a RAM (Random Access Memory), and a memory card.
  • the display unit 106 displays captured images and various information that supports the imaging operation.
  • the display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.
  • the operation unit 107 provides a user interface for operating the camera 100.
  • the operation unit 107 may include, for example, buttons, dials, and switches provided on the camera 100.
  • the operation unit 107 may be configured as a touch panel together with the display unit 106.
  • FIG. 2 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment.
  • the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.
  • the pixel array section 111 includes a plurality of pixels 120.
  • the pixels 120 are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction).
  • Each pixel 120 can form a source follower with the column readout circuit 113 when reading out a signal.
  • Each pixel 120 is connected to a horizontal drive line 131 for each row, and to a vertical signal line 132 for each column.
  • the horizontal drive line 131 drives each pixel 120 for each row when reading out a signal from each pixel 120.
  • the vertical signal line 132 transmits the pixel signal read out from the pixel 120 to the column signal processing section 114 for each column.
  • the vertical scanning circuit 112 scans the pixels 120 to be read in the column direction.
  • the vertical scanning circuit 112 may be configured using vertical registers.
  • the vertical scanning circuit 112 includes a transfer control driver 141, a selection control driver 142, a reset control driver 143, and a binning control driver 144.
  • the transfer control driver 141 controls the transfer of the charge accumulated in the pixel 120.
  • the selection control driver 142 controls the selection of the pixel 120 from which the pixel signal is read out.
  • the reset control driver 143 controls the reset of the charge accumulated in the pixel 120.
  • the binning control driver 144 controls the binning of the charge accumulated in the pixel 120.
  • the transfer control driver 141, the selection control driver 142, the reset control driver 143, and the binning control driver 144 can control the pixel 120 via the horizontal drive line 131.
  • the column readout circuit 113 can read out pixel signals from each pixel 120 in units of kernels to be convolved.
  • the convolution process may be a differential process of pixel signals, a weighted differential process of pixel signals, or a filtering process.
  • the kernel unit may be a 2x2 pixel unit, a 3x3 pixel unit, a 4x4 pixel unit, or any other pixel unit.
  • the column readout circuit 113 may form a source follower with each pixel 120 when reading out a signal from each pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120.
  • the column readout circuit 113 may also support constant current readout or capacitive load readout.
  • the column signal processing unit 114 processes signals transmitted in the column direction from each pixel 120.
  • the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 120.
  • the column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 120, and output an edge signal G1, a low gradation signal G2, and a high gradation signal G3.
  • the edge signal G1 can be generated based on a comparison result of pixel signals read out from pixels 120 in different rows or columns.
  • the low gradation signal G2 can be generated based on a binning value of the pixel signal of each pixel 120.
  • the high gradation signal G3 can be generated based on individual reading of the pixel signal of each pixel 120.
  • the column signal processing unit 114 may include an AD conversion unit 145 that is shared for generating the edge signal G1, the low gradation signal G2, and the high gradation signal G3.
  • the column signal processing unit 114 can perform the generation process of the edge signal G1 based on the pixel signals of some of the pixels 120 read out in kernel units. Also, the column signal processing unit 114 can perform the generation process of the low gradation signal G2 based on pixel signals read out including at least the pixels not used to generate the edge signal G1 among the pixels 120 read out in kernel units.
  • the size of the kernel unit may be the same when generating the edge signal G1 and when generating the low gradation signal G2, or may be different from each other.
  • the column signal processing unit 114 may generate the edge signal G1 and then generate the low gradation signal G2 within the same frame. Also, the column signal processing unit 114 may non-destructively read out the pixel signal used to generate the edge signal G1 from the pixel 120, and then non-destructively read out the pixel signal used to generate the low gradation signal G2 from the pixel 120.
  • the pixels 120 used to generate the edge signal G1 may be selected such that their rows and columns are different from each other.
  • the horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction.
  • the horizontal scanning circuit 115 may be configured using a horizontal register.
  • the control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115.
  • the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114.
  • the control circuit 116 can also control the generation timing of the edge signal G1, the generation timing of the low gradation signal G2, and the generation timing of the high gradation signal G3.
  • the control circuit 116 includes a reference signal generating unit 151 and an exposure control unit 152.
  • the reference signal generating unit 151 can generate a level signal that is compared with the pixel signal when the low gradation signal G2 is generated, and a ramp signal that is compared with the pixel signal when the high gradation signal G3 is generated.
  • the exposure control unit 152 can perform exposure control based on the low gradation signal G2.
  • FIG. 3 is a block diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to the first embodiment.
  • pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, a binning transistor 127, and a floating diffusion 126.
  • MOS Metal Oxide Semiconductor
  • the amplification transistor 124 and the selection transistor 125 are connected in series.
  • the cathode of the photodiode 121 is connected to the floating diffusion 126 via the transfer transistor 122.
  • the floating diffusion 126 is connected to the power supply Vdd via the reset transistor 123.
  • the power supply Vdd is connected to the vertical signal line 132 via the series circuit of the amplification transistor 124 and the selection transistor 125.
  • the gate of the amplification transistor 124 is connected to the floating diffusion 126.
  • the binning transistor 127 is connected between the floating diffusion 126 and the binning line 133.
  • the binning line 133 can connect the pixels 120 to be binned together. In this case, the binning line 133 may connect the pixels 120 to each other in the row direction and the column direction.
  • a transfer signal TRG is applied to the gate of the transfer transistor 122 from the transfer control driver 141.
  • a reset signal RST is applied to the gate of the reset transistor 123 from the reset control driver 143.
  • a selection signal SEL is applied to the gate of the selection transistor 125 from the selection control driver 142.
  • a binning signal BNE is applied to the gate of the binning transistor 127 from the binning control driver 144.
  • the transfer transistor 122 When the transfer transistor 122 is turned on, the charge accumulated in the photodiode 121 is transferred to the floating diffusion 126.
  • the selection transistor 125 When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion 126.
  • the source potential of the amplification transistor 124 is applied to the vertical signal line 132 via the selection transistor 125 and transmitted via the vertical signal line 132.
  • the reset transistor 123 When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion 126 is discharged.
  • the binning transistor 127 When the binning transistor 127 is turned on, the floating diffusions 126 of multiple pixels 120 are connected in kernel units via the binning line 133.
  • FIG. 4 is a cross-sectional view showing an example of the configuration of a pixel array section provided in a solid-state imaging device according to the first embodiment. Note that FIG. 4 shows an example of a front-illuminated solid-state imaging device. FIG. 4 also shows an example of the configuration for three pixels.
  • a photodiode 232 is formed for each pixel 120 on a semiconductor substrate 231.
  • the material of the semiconductor substrate 231 may be Si, InGaAs, or InP.
  • a gate electrode 214 and a wiring layer 210 are formed on a semiconductor substrate 231.
  • the gate electrode 214 is formed on the semiconductor substrate 231 via a gate insulating film 213.
  • a sidewall 215 is formed on the sidewall of the gate electrode 214.
  • the material of the gate electrode 214 may be, for example, polycrystalline silicon doped with impurities.
  • the material of the gate insulating film 213 may be, for example, a silicon oxide film.
  • the material of the sidewall 215 may be, for example, a silicon oxide film or a silicon nitride film.
  • the gate electrode 214 can be used for pixel transistors.
  • the pixel transistors include the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 in FIG. 3.
  • a wiring 216 is formed on the gate electrode 214.
  • FIG. 4 shows an example of a three-layer wiring.
  • an opening OP1 is provided in the wiring 216 to allow light to enter the photodiode 232.
  • the gate electrode 214 and the wiring 216 are insulated via an insulating layer 217.
  • the insulating layer 217 may be, for example, a silicon oxide film.
  • the material of the wiring 216 may be, for example, a metal such as Al or Cu.
  • a color filter 218 is formed on the wiring layer 210 for each pixel 120.
  • a microlens 219 is formed on the color filter 218 for each pixel 120.
  • the material of the color filter 218 and the microlens 219 may be a transparent resin such as acrylic or polycarbonate.
  • a pigment may be added to the color filter 218 for coloring.
  • the color filter 218 may form, for example, a Bayer array or a quad Bayer array.
  • the color filter 218 may include an RGB filter, a complementary color filter, or a white filter.
  • FIG. 5 is a cross-sectional view showing a modified example of a pixel array section provided in a solid-state imaging device according to the first embodiment. Note that FIG. 5 shows an example of a back-illuminated solid-state imaging device. Also, FIG. 5 shows an example of a configuration for three pixels.
  • a photodiode 222 is formed in the semiconductor layer 221 for each pixel 120.
  • the material of the semiconductor layer 221 may be Si, InGaAs, or InP.
  • the semiconductor layer 221 can be formed, for example, by thinning a semiconductor substrate, on the front side of which the photodiode 222 is formed, from the back side.
  • a gate electrode 224 and a wiring layer 220 are formed on the semiconductor layer 221.
  • the gate electrode 224 is formed on the semiconductor layer 221 via a gate insulating film 223.
  • a sidewall 225 is formed on the side wall of the gate electrode 224.
  • the gate electrode 224 can be used for pixel transistors.
  • the pixel transistors include the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 in FIG. 3.
  • Wiring 226 is formed on the gate electrode 224.
  • FIG. 5 shows an example of three-layer wiring.
  • the gate electrode 224 and wiring 226 are insulated via an insulating layer 227.
  • the semiconductor layer 221 is supported on a support substrate 230 via the insulating layer 227.
  • the support substrate 230 may be a glass substrate, a Si substrate, or a sapphire substrate.
  • a color filter 228 is formed for each pixel 120 on the back side of the semiconductor layer 221.
  • a microlens 229 is formed for each pixel 120 on the color filter 228.
  • the color filter 228 may, for example, configure a Bayer array or a quad Bayer array.
  • the color filter 228 may include an RGB filter, a complementary color filter, or a white filter.
  • FIG. 6 is a block diagram showing a readout method of the solid-state imaging device according to the first embodiment. Note that in the figure, “a” shows an example of switching the comparator input when pixel signals are read out from the pixels 120 in units of kernels when generating edge signals. “b” in the figure shows an example of switching the comparator input when pixel signals are read out from the pixels 120 in units of kernels when generating low gradation signals.
  • the kernel unit is set to 4x4 pixels (pixels from row n (n is a multiple of 4) to row n+3 and row m (m is a multiple of 4) to row m+3).
  • four comparators 171-1 to 171-4 are provided in each kernel unit to detect vertical and horizontal edges.
  • a multiplexer 161 is provided to switch the input to each comparator 171-1 to 171-4 when generating an edge signal and when generating a low gradation signal.
  • the multiplexer 161 can switch the comparator input so that the pixel signals read out from each of the pixels 120-1 and 120-2 are input to both of the comparators 171-1 and 171-2.
  • the multiplexer 161 can also switch the comparator input so that the pixel signals read out from each of the pixels 120-3 and 120-4 are input to both of the comparators 171-3 and 171-4.
  • the pixel signals read out from the pixels 120-1 and 120-2 are input to the comparators 171-1 and 171-2 so that their polarities are reversed.
  • the pixel signals read out from the pixels 120-3 and 120-4 are input to the comparators 171-3 and 171-4 so that their polarities are reversed.
  • 16 pixels 120 included in the kernel unit are selected to generate a low gradation signal.
  • the multiplexer 161 can switch the comparator input so that the binning values of the pixel signals read out from each pixel 120 are input to the comparators 171-1 to 171-4.
  • level signals VF1 to VF4 are input to each of the comparators 171-1 to 171-4.
  • the level signals VF1 to VF4 can be set to different voltage levels.
  • the comparators 171-1 to 171-4 can operate as flash AD converters and can generate a 5-gradation low gradation signal.
  • FIG. 7 is a block diagram showing an example of switching of signal paths when an edge image is generated by a solid-state imaging device according to the first embodiment.
  • each pixel 120 includes an amplification transistor 124, a selection transistor 125, a binning transistor 127, and a pixel block 128.
  • Each pixel block 128 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, and a floating diffusion 126.
  • the pixel array section 111 has two vertical signal lines 132-1 and 132-2 for each column as the vertical signal lines 132. At this time, in each kernel unit, the selection transistors 125 of the pixels 120 in the n+3th and n+1th rows are connected to the vertical signal line 132-2, and the selection transistors 125 of the pixels 120 in the n+2th and nth rows are connected to the vertical signal line 132-1.
  • the column read circuit 113 includes a multiplexer 161, current sources 251-1 to 251-4, switches 261-1 to 261-4, and selectors 271-1 to 271-4.
  • the multiplexer 161 includes switches 161-1 to 161-4.
  • Each current source 251-1 to 251-4 can be used for constant current readout of pixel signals from each pixel 120. At this time, each current source 251-1 to 251-4 forms a source follower for each column with the amplification transistor 124 of each pixel 120, and can charge the vertical signal lines 132-1 and 132-2 according to the charge accumulated in each pixel 120.
  • the multiplexer 161 switches the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 on a kernel basis when generating an edge signal, a low gradation signal, or a high gradation signal. At this time, the multiplexer 161 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 so that pixel signals from two pixels are input to each of the comparators 171-1 to 171-4 in different combinations when generating an edge signal.
  • the multiplexer 161 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 so that pixel signals read out on a kernel basis and level signals VF1 to VF4 are input to each of the comparators 171-1 to 171-4 when generating a low gradation signal.
  • the multiplexer 161 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 so that the pixel signal read out on a pixel-by-pixel basis and the ramp signal RAP are input to each of the comparators 171-1 to 171-4.
  • Each switch 161-1 to 161-4 is provided for each column.
  • the input terminals of each switch 161-1 to 161-4 are provided for each vertical signal line 132-1, 132-2.
  • the output terminals of each switch 161-1 to 161-4 are connected to the inverting input terminals of each comparator 171-1 to 171-4.
  • Switch 261-1 to 261-4 is provided for each column.
  • Switch 261-1 is used to connect switch 161-1 to selector 271-3.
  • Switch 261-2 is used to connect switch 161-2 to selector 271-4.
  • Switch 261-3 is used to connect switch 161-3 to selector 271-1.
  • Switch 261-4 is used to connect switch 161-4 to selector 271-2.
  • Selectors 271-1 to 271-4 are provided for each column. Selector 271-1 selects either the output of reference signal generation unit 151 or the pixel signal output via switch 261-3 and inputs it to gain unit 281-1. Selector 271-2 selects either the output of reference signal generation unit 151 or the pixel signal output via switch 261-4 and inputs it to gain unit 281-2. Selector 271-3 selects either the output of reference signal generation unit 151 or the pixel signal output via switch 261-1 and inputs it to gain unit 281-3. Selector 271-4 selects either the output of reference signal generation unit 151 or the pixel signal output via switch 261-2 and inputs it to gain unit 281-4.
  • the column signal processing unit 114 includes gain units 281-1 to 281-4, comparators 171-1 to 171-4, inverters 181-1 to 181-4, and NAND circuits 191-1 to 191-4.
  • Gain units 281-1 to 281-4 are provided for each of comparators 171-1 to 171-4.
  • Gain unit 281-1 multiplies the output of selector 271-1 with gain G and outputs the result to the non-inverting input terminal of comparator 171-1.
  • Gain unit 281-2 multiplies the output of selector 271-2 with gain G and outputs the result to the non-inverting input terminal of comparator 171-2.
  • Gain unit 281-3 multiplies the output of selector 271-3 with gain G and outputs the result to the non-inverting input terminal of comparator 171-3.
  • Gain unit 281-4 multiplies the output of selector 271-4 with gain G and outputs the result to the non-inverting input terminal of comparator 171-4.
  • Comparators 171-1 to 171-4 are provided for each column. Comparator 171-1 compares the output of gain unit 281-1 with the pixel signal output via switch 161-1. Comparator 171-2 compares the output of gain unit 281-2 with the pixel signal output via switch 161-2. Comparator 171-3 compares the output of gain unit 281-3 with the pixel signal output via switch 161-3. Comparator 171-4 compares the output of gain unit 281-4 with the pixel signal output via switch 161-4.
  • an auto-zero signal AZ is input to each of the comparators 171-1 to 171-4.
  • the auto-zero signal AZ activates the auto-zero operation during the auto-zero period.
  • a DC cut capacitor 291 is connected to the non-inverting input terminal
  • a DC cut capacitor 292 is connected to the inverting input terminal.
  • the charge stored in each of the DC cut capacitors 291, 292 is controlled so that the non-inverting input and the inverting input of each of the comparators 171-1 to 171-4 are balanced.
  • Inverter 181-1 inverts the output of comparator 171-1 and inputs it to NAND circuit 191-1.
  • Inverter 181-2 inverts the output of comparator 171-2 and inputs it to NAND circuit 191-2.
  • Inverter 181-3 inverts the output of comparator 171-3 and inputs it to NAND circuit 191-3.
  • Inverter 181-4 inverts the output of comparator 171-4 and inputs it to NAND circuit 191-4.
  • NAND circuit 191-1 calculates the NAND of the output of inverter 181-1 and the output enable signal VOE.
  • NAND circuit 191-2 calculates the NAND of the output of inverter 181-2 and the output enable signal VOE.
  • NAND circuit 191-3 calculates the NAND of the output of inverter 181-3 and the output enable signal VOE.
  • NAND circuit 191-4 calculates the NAND of the output of inverter 181-4 and the output enable signal VOE.
  • the output enable signal VOE enables the output of each of comparators 171-1 to 171-4.
  • the reference signal generating unit 151 includes a ramp signal generating unit 153, a level signal generating unit 154, and a reference signal switching unit 155.
  • the ramp signal generating unit 153 generates a ramp signal RAP.
  • the level signal generating unit 154 generates level signals VF1 to VF4.
  • the reference signal switching unit 155 inputs the level signal VF1 to the selector 271-1, the level signal VF2 to the selector 271-2, the level signal VF3 to the selector 271-3, and the level signal VF4 to the selector 271-4.
  • the reference signal switching unit 155 inputs the ramp signal RAP to each of the selectors 271-1 to 271-4.
  • the solid-state imaging device generates an edge image.
  • the selection transistor 125 is turned on and the binning transistor 127 is turned off.
  • the selection transistor 125 and the binning transistor 127 are turned off.
  • the vertical signal line 132-1 to which pixel 120-1 is connected is connected to comparator 171-1 via switch 161-1.
  • the vertical signal line 132-1 to which pixel 120-4 is connected is connected to comparator 171-2 via switch 161-2.
  • the vertical signal line 132-2 to which pixel 120-3 is connected is connected to comparator 171-4 via switch 161-4.
  • the vertical signal line 132-2 to which pixel 120-4 is connected is connected to comparator 171-3 via switch 161-3.
  • the vertical signal line 132-1 to which the pixel 120-1 is connected is connected to the gain section 281-3 via the switch 161-1, the switch 261-1, and the selector 271-3.
  • the vertical signal line 132-1 to which the pixel 120-4 is connected is connected to the gain section 281-3 via the switch 161-2, the switch 261-2, and the selector 271-4.
  • the vertical signal line 132-2 to which the pixel 120-3 is connected is connected to the gain section 281-2 via the switch 161-4, the switch 261-4, and the selector 271-2.
  • the vertical signal line 132-2 to which the pixel 120-2 is connected is connected to the gain section 281-1 via the switch 161-3, the switch 261-3, and the selector 271-1.
  • FIG. 8 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the first embodiment.
  • the solid-state imaging device generates a low-tone image.
  • the selection transistors 125 and binning transistors 127 are turned on in the 16 pixels 120 included in the kernel unit.
  • the vertical signal lines 132-1 and 132-2 to which the pixels 120 in the mth column included in the kernel unit are connected are connected to the comparator 171-1 via the switch 161-1.
  • the vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+1th column included in the kernel unit are connected are connected to the comparator 171-2 via the switch 161-2.
  • the vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+2th column included in the kernel unit are connected are connected to the comparator 171-3 via the switch 161-3.
  • the vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+3th column included in the kernel unit are connected are connected to the comparator 171-4 via the switch 161-4. At this time, the switches 261-1 to 261-4 are turned off.
  • the level signal VF1 generated by the level signal generating unit 154 is input to the gain unit 281-1 via the reference signal switching unit 155 and the selector 271-1.
  • the level signal VF2 generated by the level signal generating unit 154 is input to the gain unit 281-2 via the reference signal switching unit 155 and the selector 271-2.
  • the level signal VF3 generated by the level signal generating unit 154 is input to the gain unit 281-3 via the reference signal switching unit 155 and the selector 271-3.
  • the level signal VF4 generated by the level signal generating unit 154 is input to the gain unit 281-4 via the reference signal switching unit 155 and the selector 271-4. At this time, the gain of each of the gain units 281-1 to 281-4 is set to 1.
  • FIG. 9 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by the solid-state imaging device according to the first embodiment.
  • the selection control driver 142 generates selection signals SEL1 and SEL2 as the selection signal SEL.
  • the selection signal SEL1 is applied to the selection transistors 125 of each pixel 120 in the mth and m+2th columns
  • the selection signal SEL2 is applied to the selection transistors 125 of each pixel 120 in the m+1th and m+3th columns.
  • an edge signal is generated based on non-destructive readout (P11), and then a low gradation signal is generated (P12).
  • a P-phase readout is performed for each pixel 120-1 to 120-4 (K11), and then a D-phase readout is performed (K12).
  • an edge signal is generated based on AD conversion of the signal level.
  • a D-phase readout is performed for each pixel 120 (K13), and then a P-phase readout is performed (K14).
  • an auto-zero operation based on the binning value of the signal level is performed, and then a gradation signal is generated based on AD conversion of the binning value of the reset level.
  • the switching signal RSW is set to a low level.
  • the input of the selector 271-1 is switched to the switch 261-3 side
  • the input of the selector 271-2 is switched to the switch 261-4 side
  • the input of the selector 271-3 is switched to the switch 261-1 side
  • the input of the selector 271-4 is switched to the switch 261-2 side.
  • each of the switches 261-1 to 261-4 is turned on.
  • the switch 161-1 is connected to the vertical signal line 132-1 to which the pixel 120-1 is connected.
  • the switch 161-2 is connected to the vertical signal line 132-1 to which the pixel 120-4 is connected.
  • the switch 161-3 is connected to the vertical signal line 132-2 to which the pixel 120-3 is connected.
  • the switch 161-4 is connected to the vertical signal line 132-2 to which the pixel 120-2 is connected.
  • the reset signal RST[n+3]-[n] rises (t11), turning on the reset transistor 123 of the pixel 120 included in the kernel unit and resetting the floating diffusion 126.
  • the auto-zero signal AZ rises (t11), activating the auto-zero operation of each of the comparators 171-1 to 171-4.
  • the charge stored in the DC-cut capacitors 291 and 292 is controlled so that the non-inverting input and the inverting input of each of the comparators 171-1 to 171-4 are balanced.
  • the selection signals SEL1[n+2], [n+3] and SEL2[n], [n+1] rise (t11).
  • the selection transistors 125 of the pixels 120 in the n+2th and n+3th rows are turned on, and in the m+1th and m+3th columns, the selection transistors 125 of the pixels 120 in the nth and n+1th rows are turned on.
  • the pixels 120 in the same column are connected to different vertical signal lines 132-1, 132-2 via the selection transistors 125, preventing collision of pixel signals read out from the pixels 120 in the same column.
  • the potential VLc1 of the vertical signal line 132-1 to which the pixel 120-1 is connected is set and input to the comparator 171-1. Also, based on the source follower operation when the power supply potential Vdd is applied to the gate of the amplification transistor 124 of the pixel 120-4, the potential VLc2 of the vertical signal line 132-1 to which the pixel 120-4 is connected is set and input to the comparator 171-2.
  • the potential VLc3 of the vertical signal line 132-2 to which the pixel 120-3 is connected is set and input to the comparator 171-4.
  • the potential VLc4 of the vertical signal line 132-2 to which the pixel 120-2 is connected is set and input to the comparator 171-3. Note that VLc* indicates VLc1 to VLc4.
  • the reset signal RST[n+3]-[n] falls (t12), and the reset transistor 123 of the pixel 120 included in the kernel unit is turned off.
  • the potential VLc1 of the vertical signal line 132-1 to which pixel 120-1 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-1 is applied to the gate of the amplification transistor 124.
  • the potential VLc2 of the vertical signal line 132-1 to which pixel 120-4 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-4 is applied to the gate of the amplification transistor 124.
  • the potential VLc3 of the vertical signal line 132-2 to which pixel 120-3 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-3 is applied to the gate of the amplification transistor 124.
  • the potential VLc4 of the vertical signal line 132-2 to which the pixel 120-2 is connected is set based on the source follower action when the reset level of the floating diffusion 126 of the pixel 120-2 is applied to the gate of the amplification transistor 124.
  • the transfer signal TRG[n+3]-[n] rises (t14).
  • the transfer transistor 122 of the pixel 120 included in the kernel unit turns on, and the charge accumulated in the photodiode 121 is transferred to the floating diffusion 126.
  • the potential VLc1 of the vertical signal line 132-1 to which pixel 120-1 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-1 is applied to the gate of the amplification transistor 124.
  • the potential VLc2 of the vertical signal line 132-1 to which pixel 120-4 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-4 is applied to the gate of the amplification transistor 124.
  • the potential VLc3 of the vertical signal line 132-2 to which pixel 120-3 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-3 is applied to the gate of the amplification transistor 124.
  • the potential VLc4 of the vertical signal line 132-2 to which the pixel 120-2 is connected is set based on the source follower action when the cathode potential of the photodiode 121 of the pixel 120-2 is applied to the gate of the amplification transistor 124.
  • the transfer signal TRG[n+3]-[n] falls, and the transfer transistor 122 of the pixel 120 included in the kernel unit is turned off.
  • the potential VLc1 of the vertical signal line 132-1 to which pixel 120-1 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-1 is applied to the gate of the amplification transistor 124.
  • the potential VLc2 of the vertical signal line 132-1 to which pixel 120-4 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-4 is applied to the gate of the amplification transistor 124.
  • the potential VLc3 of the vertical signal line 132-2 to which pixel 120-3 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-3 is applied to the gate of the amplification transistor 124.
  • the potential VLc4 of the vertical signal line 132-2 to which the pixel 120-2 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of the pixel 120-2 is applied to the gate of the amplification transistor 124.
  • the potential VLc1 of the vertical signal line 132-1 to which the pixel 120-1 is connected is compared with the potential VLc2 of the vertical signal line 132-1 to which the pixel 120-4 is connected.
  • the potential VLc3 of the vertical signal line 132-2 to which the pixel 120-3 is connected is compared with the potential VLc4 of the vertical signal line 132-2 to which the pixel 120-2 is connected.
  • the potentials VLc1 to VLc4 input to the non-inverting input terminals of the comparators 171-1 to 171-4 may be multiplied by a gain G.
  • the outputs of the comparators 171-1 to 171-4 are then input to the NAND circuits 191-1 to 191-4 via the inverters 181-1 to 181-4, respectively.
  • the output enable signal VOE rises (t15).
  • the comparison results VO1 to VO4 of the comparators 171-1 to 171-4 are output as edge signals via the inverters 181-1 to 181-4 and the NAND circuits 191-1 to 191-4, respectively.
  • the switching signal RSW is set to a high level.
  • the input of the selector 271-1 is switched to the level signal VF1
  • the input of the selector 271-2 is switched to the level signal VF2
  • the input of the selector 271-3 is switched to the level signal VF3
  • the input of the selector 271-4 is switched to the level signal VF4.
  • each of the switches 261-1 to 261-4 is turned off.
  • the switch 161-1 is connected to each of the vertical signal lines 132-1 and 132-2 of the mth column.
  • the switch 161-2 is connected to each of the vertical signal lines 132-1 and 132-2 of the m+1th column.
  • the switch 161-3 is connected to each of the vertical signal lines 132-1 and 132-2 of the m+2th column.
  • the switch 161-4 is connected to each of the vertical signal lines 132-1 and 132-2 of the m+3th column.
  • the output enable signal VOE also falls (t16).
  • the auto-zero signal AZ also rises (t16), activating the auto-zero operation of each of the comparators 171-1 to 171-4.
  • the binning signal BNE also rises, turning on the binning transistors 127 of the 16 pixels 120 included in the kernel unit. With the selection signals SEL1[n+2], [n+3] and SEL2[n], [n+1] still rising, the selection signals SEL1[n], [n+1] and SEL2[n+2], [n+3] also rise (t16). At this time, the selection transistors 125 of the 16 pixels 120 included in the kernel unit are turned on.
  • the potential VLc of the vertical signal lines 132-1, 132-2 of the mth to m+3th columns of the kernel unit is set based on the source follower operation when the binning values of the signal levels of the 16 pixels 120 included in the kernel unit are applied to the gates of the amplification transistors 124.
  • the potential VLc of the vertical signal lines 132-1, 132-2 of the mth to m+3th columns of the kernel unit is applied to the inverting input terminals of the comparators 171-1 to 171-4 via the DC cut capacitor 292
  • the charges accumulated in the DC cut capacitors 291, 292 connected to each of the comparators 171-1 to 171-4 reflect the binning values of the signal levels of the 16 pixels 120 included in the kernel unit.
  • the auto-zero signal AZ falls (t17), deactivating the auto-zero operation of each of the comparators 171-1 to 171-4. Then, the reset signal RST[n+3]-[n] rises, turning on the reset transistor 123 of the pixel 120 included in the kernel unit and resetting the floating diffusion 126.
  • the reset signal RST[n+3]-[n] falls (t18), and the reset transistors 123 of the pixels 120 included in the kernel unit are turned off.
  • the potential VLc of the vertical signal lines 132-1 and 132-2 of the mth to (m+3)th columns of the kernel unit is set based on the source follower operation when the binning values of the reset levels of the 16 pixels 120 included in the kernel unit are applied to the gates of the amplification transistors 124.
  • each of the comparators 171-1 to 171-4 the potential VLc of the vertical signal lines 132-1 and 132-2 is compared with the level signals VF1 to VF4, respectively, with electric charge stored in each of the DC cut capacitors 291 and 292 so that the binning value of the signal level of each kernel is reflected.
  • the outputs of the comparators 171-1 to 171-4 are input to the NAND circuits 191-1 to 191-4 via the inverters 181-1 to 181-4, respectively.
  • the output enable signal VOE rises (t19).
  • the comparison results VO1 to VO4 of the comparators 171-1 to 171-4 are output as low-gradation signals via the inverters 181-1 to 181-4 and the NAND circuits 191-1 to 191-4, respectively.
  • FIG. 10 is a diagram showing the relationship between the gradation signal of a low-gradation image and the reference signal obtained by the solid-state imaging device according to the first embodiment.
  • five low-level gradation signals can be obtained by using four level signals VF1 to VF4 as reference signals for each comparator 171-1 to 171-4.
  • FIG. 11 is a block diagram showing an example of signal path switching when a high-gradation image is generated by a solid-state imaging device according to the first embodiment.
  • the solid-state imaging device generates a high-tone image.
  • the gradation of the high-tone image may be set to, for example, 8 bits to 14 bits.
  • pixel signals may be read out individually from each of the 16 pixels 120 included in the kernel unit.
  • the selection transistors 125 are turned on row by row.
  • the binning transistors 127 are turned off. For example, when reading out from the pixels 120-4 to 120-7 in the nth row included in the kernel unit, the selection transistors 125 of those pixels 120-4 to 120-7 are turned on. Also, the selection transistors 125 of the pixels 120 in the n+1th to n+3th rows included in the kernel unit are turned off.
  • the vertical signal line 132-1 is connected to the comparators 171-1 to 171-4 via the switches 161-1 to 161-4, respectively.
  • the vertical signal line 132-2 is connected to the comparators 171-1 to 171-4 via the switches 161-1 to 161-4, respectively. At this time, the switches 261-1 to 261-4 are turned off.
  • the ramp signal RAP generated by the ramp signal generating unit 153 is input to the gain units 281-1 to 281-4 via the reference signal switching unit 155 and the selectors 271-1 to 271-4, respectively.
  • FIG. 12 is a timing chart showing an example of waveforms at various parts when a high-gradation image is generated by the solid-state imaging device according to the first embodiment.
  • the switching signal RSW is set to a high level (t21).
  • the input of each of the selectors 271-1 to 271-4 is switched to the ramp signal RAP.
  • each of the switches 261-1 to 261-4 is turned off.
  • the binning signal BNE[n] is set to a low level (t21), and the binning transistor 127 is turned off.
  • the auto-zero signal AZ also rises (t21), activating the auto-zero operation of each of the comparators 171-1 to 171-4.
  • the reset signal RST[n] also rises, turning on the reset transistor 123 of the pixel 120 included in the kernel unit and resetting the floating diffusion 126.
  • the selection signals SEL1[n] and SEL2[n] also rise (t21). At this time, the selection transistor 125 of the pixel 120 in the nth row included in the kernel unit is turned on.
  • the reset transistor 123 of each pixel 120 in the nth row included in the kernel unit is turned off.
  • the potential VLc of the vertical signal line 132-1 or 132-2 to which the pixel 120 in the nth row is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of each pixel 120 in the nth row is applied to the gate of the amplification transistor 124.
  • the output enable signal VOE rises and the ramp signal RAP is supplied as a reference signal to each of the comparators 171-1 to 171-4 (t23). Then, in each of the comparators 171-1 to 171-4, the potential VLc of the vertical signal line 132-1 or 132-2 corresponding to the reset level is compared with the ramp signal RAP, and the timing when the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132-1 or 132-2 is output as the comparison results VO1 to VO4 (t24). At this time, the reset level read out from the pixel 120 in the nth row is AD converted based on the counting operation until the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132-1 or 132-2.
  • the transfer signal TRG[n] rises (t25). Then, the transfer transistor 122 of each pixel 120 in the nth row included in the kernel unit turns on, and the charge accumulated in the photodiode 121 is transferred to the floating diffusion 126. At this time, the potential VLc of the vertical signal line 132-1 or vertical signal line 132-2 to which the pixel 120 in the nth row is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of each pixel 120 in the nth row is applied to the gate of the amplification transistor 124.
  • the ramp signal RAP is supplied to each of the comparators 171-1 to 171-4 as a reference signal (t26). Then, in each of the comparators 171-1 to 171-4, the potential VLc of the vertical signal line 132-1 or vertical signal line 132-2 corresponding to the signal level is compared with the ramp signal RAP, and the timing when the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132-1 or vertical signal line 132-2 is output as the comparison results VO1 to VO4 (t27). At this time, the signal level read out from the pixel 120 in the nth row is AD converted based on the counting operation until the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132-1 or vertical signal line 132-2.
  • FIG. 13 is a diagram showing an example of image generation by the solid-state imaging device according to the first embodiment.
  • a captured image is generated based on a high-tone signal.
  • the high-tone signal can be generated based on pixel signals read out individually from each pixel 120.
  • an edge image is generated based on the edge signal.
  • the edge signal can be generated based on a convolution process of pixel signals read out from pixels 120 on a kernel-by-kernel basis.
  • a low-tone image is generated based on a low-tone signal.
  • the low-tone signal can be generated based on the binning value of the pixel signal read out from the pixel 120 in kernel units.
  • FIG. 14 is a circuit diagram showing an example of the configuration of a pixel array section of a solid-state imaging device according to the first embodiment.
  • 4 x 4 pixels 120 are arranged in kernel units in the pixel array section 111.
  • the pixels 120 are connected so that the pixel signals read out from the pixels 120 do not collide when generating an edge signal.
  • the selection transistors 125 of the pixels 120 in the n+3th and n+1th rows are connected to the vertical signal line 132-2, and the selection transistors 125 of the pixels 120 in the n+2th and nth rows are connected to the vertical signal line 132-1.
  • the selection signal SEL1 is applied to the selection transistors 125 of each pixel 120 in the mth and m+2th columns, and the selection signal SEL2 is applied to the selection transistors 125 of each pixel 120 in the m+1th and m+3th columns.
  • FIG. 15 is a diagram showing an example of the configuration of a comparator applied to the signal readout circuit according to the first embodiment.
  • the configuration of the comparator 171-1 in FIG. 17 is taken as an example, but each of the comparators 171-2 to 171-4 can be configured in the same way.
  • the comparator 171-1 includes a differential amplifier 501 and a rear-stage amplifier 502.
  • An inverter 181-1 is connected to the rear stage of the comparator 171-1.
  • the rear-stage amplifier 502 is connected to the rear stage of the differential amplifier 501, and the inverter 181-1 is connected to the rear stage of the rear-stage amplifier 502.
  • Differential amplifier 501 balances comparator inputs DVSL1 and DVSL2 based on the auto-zero operation, and outputs a voltage according to the difference between comparator inputs DVSL1 and DVSL2.
  • Differential amplifier 501 includes PMOS transistors 511, 521, 551, and 561, and NMOS transistors 531, 541, and 571.
  • PMOS transistor 511 and NMOS transistor 531 are connected in series to each other.
  • PMOS transistor 521 and NMOS transistor 541 are connected in series to each other.
  • the sources of each of PMOS transistors 511 and 521 are connected to power supply voltage VDDH, and the gates of each of PMOS transistors 511 and 521 are connected to the drain of PMOS transistor 521. At this time, PMOS transistors 511 and 521 can form a current mirror.
  • a PMOS transistor 551 is connected between the gate and drain of the NMOS transistor 531, and a PMOS transistor 561 is connected between the gate and drain of the NMOS transistor 541.
  • the sources of the NMOS transistors 531 and 541 are grounded via an NMOS transistor 571.
  • An auto-zero signal AZP is applied to the gate of each of the PMOS transistors 551 and 561, and a bias voltage BIAS is applied to the gate of the NMOS transistor 571.
  • the NMOS transistor 571 can operate as a constant current source based on the bias voltage BIAS.
  • the rear amplifier 502 amplifies the output of the differential amplifier 501.
  • the rear amplifier 502 includes a PMOS transistor 512, an NMOS transistor 522, and a switch 532.
  • PMOS transistor 512 and NMOS transistor 522 are connected in series with each other.
  • the source of PMOS transistor 512 is connected to power supply voltage VDDH, and the gate of PMOS transistor 512 is connected to the drain of PMOS transistor 511.
  • Switch 532 is connected between the gate and drain of NMOS transistor 522, and the source of NMOS transistor 522 is grounded. Switch 532 opens and closes based on auto-zero signal AZN. Auto-zero signals AZP and AZN are signals of opposite polarity.
  • Inverter 181-1 converts the output of rear-stage amplifier 502 to a logical value of '0' or '1'.
  • Inverter 181-1 includes a PMOS transistor 513 and an NMOS transistor 523.
  • the PMOS transistor 513 and the NMOS transistor 523 are connected in series to each other.
  • the source of the PMOS transistor 513 is connected to the power supply voltage VDDL, and the source of the NMOS transistor 523 is grounded.
  • the power supply voltage VDDL can be lower than the power supply voltage VDDH.
  • the gates of the PMOS transistor 513 and the NMOS transistor 523 are connected to the drain of the PMOS transistor 512.
  • the PMOS transistors 551 and 561 turn on based on the auto-zero signal AZP, and the switch 532 closes based on the auto-zero signal AZN.
  • the timing at which the PMOS transistors 551 and 561 turn on and then off can be delayed compared to the timing at which the switch 532 opens after closing.
  • FIG. 16 is a flowchart showing an example of an exposure control method for a solid-state imaging device according to the first embodiment.
  • the solid-state imaging device when the solid-state imaging device starts exposure of the current frame, it acquires an edge image (S101) and acquires a low-tone image (S102).
  • the solid-state imaging device determines whether the average output value Dout of any pixel region of the low gradation image is within a predetermined range (S103). Whether or not it is within the predetermined range may be determined based on the relationship VTL ⁇ Dout ⁇ VTH. If the average output value Dout of the any pixel region is within the predetermined range, exposure of the current frame is started. On the other hand, if the average output value Dout of the any pixel region is outside the predetermined range, the solid-state imaging device changes the exposure time (S104) and returns to S101.
  • the solid-state imaging device When changing the exposure time, if Dout ⁇ VTL, the solid-state imaging device lengthens the exposure time in any time step. If VTH ⁇ Dout, the solid-state imaging device shortens the exposure time in any time step.
  • the solid-state imaging device generates a low-tone image based on pixel signals that are not used to generate edge signals in 4x4 pixel kernel units. This makes it possible to generate edge images while suppressing a decrease in frame rate, and improves the controllability of imaging control using pixel signals, thereby improving the image quality of the edge images. For example, by generating an edge image while performing exposure control based on a low-tone image, it is possible to prevent highlight blowout and black crush in the edge image.
  • Second embodiment In the first embodiment described above, five low gradation signals are generated based on the results of comparing the pixel signal with the level signals VF1 to VF4.
  • the number of levels of the level signal compared with the pixel signal is increased, and the comparison between the pixel signal and the level signal is performed in a time series manner, thereby increasing the number of gradations of the low gradation signals without increasing the number of comparators.
  • FIG. 17 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the second embodiment.
  • this solid-state imaging device has a reference signal generating unit 251 instead of the reference signal generating unit 151 of the first embodiment described above.
  • the rest of the configuration of the solid-state imaging device of the second embodiment is the same as the configuration of the solid-state imaging device of the first embodiment described above.
  • the reference signal generating unit 251 includes a level signal generating unit 254 instead of the level signal generating unit 154 of the first embodiment described above.
  • the rest of the configuration of the reference signal generating unit 251 of the second embodiment is the same as the configuration of the reference signal generating unit 151 of the first embodiment described above.
  • the level signal generating unit 254 generates level signals VF5 to VF8 in addition to level signals VF1 to VF4.
  • the level signals VF1 to VF4 are set to a different level than the level signals VF5 to VF8.
  • the level signal generating unit 254 can switch between the output of the level signals VF1 to VF4 and the level signals VF5 to VF8 based on the switching signal VFC.
  • FIG. 18 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by a solid-state imaging device according to the second embodiment.
  • an edge signal is generated based on non-destructive readout (P11), a first low gradation signal is generated (P12), and then a second low gradation signal is generated (P13).
  • P11 non-destructive readout
  • P12 first low gradation signal
  • P13 second low gradation signal
  • level signals VF1 to VF4 are used in generating the first low gradation signal.
  • level signals VF5 to VF8 are used.
  • the first low gradation signal and the second low gradation signal are generated so that the brightness of the low gradation images is different from each other.
  • a P-phase readout is performed for each pixel 120-1 to 120-4 (K11), and then a D-phase readout is performed (K12).
  • a D-phase readout is performed for each pixel 120 (K13), and then a first P-phase readout is performed (K14), and then a second P-phase readout is performed (K15).
  • the switching signal RSW is set to a high level (t16).
  • the input of the selector 271-1 is switched to the level signal VF5
  • the input of the selector 271-2 is switched to the level signal VF6
  • the input of the selector 271-3 is switched to the level signal VF7
  • the input of the selector 271-4 is switched to the level signal VF8.
  • each of the switches 261-1 to 261-4 is turned off.
  • the switch 161-1 is connected to each of the vertical signal lines 132-1 and 132-2 of the mth column.
  • the switch 161-2 is connected to each of the vertical signal lines 132-1 and 132-2 of the m+1th column.
  • the switch 161-3 is connected to each of the vertical signal lines 132-1 and 132-2 of the m+2th column.
  • Switch 161-4 is connected to each of the vertical signal lines 132-1 and 132-2 in the (m+3)th column.
  • each of the comparators 171-1 to 171-4 the potential VLc of the vertical signal lines 132-1 and 132-2 is compared with the level signals VF5 to VF8, respectively, with electric charge stored in each of the DC cut capacitors 291 and 292 so that the binning value of the signal level of each kernel is reflected.
  • the outputs of the comparators 171-1 to 171-4 are input to the NAND circuits 191-1 to 191-4 via the inverters 181-1 to 181-4, respectively.
  • the output enable signal VOE rises (t21).
  • the comparison results VO1 to VO4 of the comparators 171-1 to 171-4 are output as the second low gradation signal via the inverters 181-1 to 181-4 and the NAND circuits 191-1 to 191-4, respectively.
  • FIG. 19 is a circuit diagram showing an example of a level signal generating unit of a solid-state imaging device according to the second embodiment.
  • the level signal generating unit 254 includes resistors 150-1 to 150-9 and switches 241-1 to 241-4.
  • the resistors 150-1 to 150-9 are connected in series between the power supply voltage VDD and the ground voltage VSS.
  • the level signal generating unit 254 can generate level signals VF1 to VF8 based on the resistor voltage division.
  • a level signal VF1 is generated at the connection point of the resistors 150-1 and 150-2.
  • a level signal VF2 is generated.
  • a level signal VF3 is generated.
  • a level signal VF4 is generated.
  • a level signal VF5 is generated.
  • a level signal VF6 is generated at the connection point of resistors 150-6 and 150-7.
  • a level signal VF7 is generated at the connection point of resistors 150-7 and 150-8.
  • a level signal VF8 is generated at the connection point of resistors 150-8 and 150-9.
  • Switch 241-1 switches between the outputs of level signals VF1 and VF5 based on the switching signal VFC.
  • Switch 241-2 switches between the outputs of level signals VF2 and VF6 based on the switching signal VFC.
  • Switch 241-3 switches between the outputs of level signals VF3 and VF7 based on the switching signal VFC.
  • Switch 241-4 switches between the outputs of level signals VF4 and VF8 based on the switching signal VFC. This allows the level signal generating unit 254 to set eight levels for the reference signal based on resistor division.
  • the level signal generating unit 254 switches between the output of the level signals VF1 to VF4 and the output of the level signals VF5 to VF8 based on the switching signal VFC. This makes it possible to increase the number of gradations of the low gradation signals in each kernel unit without increasing the number of comparators 171-1 to 171-4.
  • an edge image and a low gradation image are generated based on a kernel unit of 4 ⁇ 4 pixels.
  • an edge image and a low gradation image are generated based on a kernel unit of 2 ⁇ 2 pixels.
  • FIG. 20 is a block diagram showing a readout method for a solid-state imaging device according to a third embodiment.
  • “a” shows an example of comparator input switching when pixel signals are read out from pixels 120 in kernel units when edge signals are generated.
  • “b” in the figure shows an example of comparator input switching when pixel signals are read out from pixels 120 in kernel units when low gradation signals are generated.
  • the kernel unit is set to 2x2 pixels (pixels from row n (n is a multiple of 2) to row n+1 and row m (m is a multiple of 2) to row m+1).
  • the kernel unit in each kernel unit, four comparators 171-1 to 171-4 are provided to detect vertical and horizontal edges.
  • a multiplexer 162 is provided to switch the input to each of the comparators 171-1 to 171-4 when generating an edge signal and when generating a low gradation signal.
  • pixels 120-11 to 120-14 are selected from the four pixels 120 included in the kernel unit. Pixels 120-11 and 120-12 can be used to detect edges in the horizontal direction, and pixels 120-13 and 120-14 can be used to detect edges in the vertical direction.
  • multiplexer 162 can switch the comparator input so that pixel signals read out from each of pixels 120-11 and 120-12 are input to both comparators 171-1 and 171-2. Additionally, multiplexer 162 can switch the comparator input so that pixel signals read out from each of pixels 120-13 and 120-14 are input to both comparators 171-3 and 171-4.
  • the pixel signals read out from each of the pixels 120-11 and 120-12 are input to the comparators 171-1 and 171-2 so that their polarities are reversed.
  • the pixel signals read out from each of the pixels 120-13 and 120-14 are input to the comparators 171-3 and 171-4 so that their polarities are reversed.
  • the multiplexer 162 can switch the comparator input so that the binning values of the pixel signals read out from each pixel 120 are input to the comparators 171-1 to 171-4.
  • level signals VF1 to VF4 are input to each of the comparators 171-1 to 171-4.
  • the comparators 171-1 to 171-4 can operate as flash AD converters and can generate a five-level low gradation signal.
  • FIG. 21 is a circuit diagram showing an example of the configuration of a pixel array section of a solid-state imaging device according to the third embodiment.
  • 2 x 2 pixels 120 are arranged in kernel units in the pixel array section 111.
  • the pixels 120 are connected so that the pixel signals read out from the pixels 120 do not collide when generating an edge signal.
  • the selection transistor 125 of the pixel 120 in the n+1th row is connected to the vertical signal line 132-2, and the selection transistor 125 of the pixel 120 in the nth row is connected to the vertical signal line 132-1.
  • the selection signal SEL1 is applied to the selection transistor 125 of the pixel 120 in the mth column
  • the selection signal SEL2 is applied to the selection transistor 125 of the pixel 120 in the m+1th column.
  • edge images and low-tone images are generated based on a kernel unit of 2x2 pixels. This makes it possible to improve the resolution compared to a method in which edge images and low-tone images are generated based on a kernel unit of 4x4 pixels.
  • an edge image and a low gradation image are generated based on a kernel unit of 4 ⁇ 4 pixels.
  • an edge image and a low gradation image are generated based on a kernel unit of 3 ⁇ 3 pixels.
  • FIG. 22 is a block diagram showing a readout method of a solid-state imaging device according to the fourth embodiment.
  • a shows an example of comparator input switching when pixel signals are read out from pixels 120 in kernel units when edge signals are generated.
  • b shows an example of comparator input switching when pixel signals are read out from pixels 120 in kernel units when low gradation signals are generated.
  • the kernel unit is set to 3x3 pixels (pixels from row n (n is a multiple of 3) to row n+1 and row m (m is a multiple of 3) to row m+1).
  • the kernel unit in each kernel unit, four comparators 171-1 to 171-4 are provided to detect vertical and horizontal edges.
  • a multiplexer 163 is provided to switch the input to each of the comparators 171-1 to 171-4 when generating an edge signal and when generating a low gradation signal.
  • pixels 120-21 to 120-24 are selected from the nine pixels 120 included in the kernel unit. Pixels 120-21 and 120-22 can be used to detect edges in the horizontal direction, and pixels 120-23 and 120-24 can be used to detect edges in the vertical direction.
  • multiplexer 163 can switch the comparator input so that pixel signals read out from each of pixels 120-21 and 120-22 are input to both comparators 171-1 and 171-2. Additionally, multiplexer 163 can switch the comparator input so that pixel signals read out from each of pixels 120-23 and 120-24 are input to both comparators 171-3 and 171-4.
  • the pixel signals read out from each of the pixels 120-21 and 120-22 are input to the comparators 171-1 and 171-2 so that their polarities are reversed.
  • the pixel signals read out from each of the pixels 120-23 and 120-24 are input to the comparators 171-3 and 171-4 so that their polarities are reversed.
  • the multiplexer 163 can switch the comparator input so that the binning values of the pixel signals read out from each pixel 120 are input to the comparators 171-1 to 171-4.
  • level signals VF1 to VF4 are input to each of the comparators 171-1 to 171-4.
  • the comparators 171-1 to 171-4 can operate as flash AD converters and can generate a five-level low gradation signal.
  • FIG. 23 is a circuit diagram showing an example of the configuration of a pixel array section of a solid-state imaging device according to the fourth embodiment.
  • 3 x 3 pixels 120 are arranged in kernel units in the pixel array section 111.
  • the pixels 120 are connected so that the pixel signals read out from the pixels 120 do not collide when generating an edge signal.
  • a vertical signal line 132-3 is added to the pixel array section 111 for each column.
  • the selection control driver 142 generates a selection signal SEL3 in addition to selection signals SEL1 and SEL2.
  • the selection transistor 125 of the pixel 120 in the n+2th row is connected to the vertical signal line 132-1, and the selection transistor 125 of the pixel 120 in the n+1th row is connected to the vertical signal line 132-2.
  • the selection transistor 125 of the pixel 120 in the nth row is connected to the vertical signal line 132-3.
  • the selection signal SEL1 is applied to the selection transistor 125 of the pixel 120 in the mth column
  • the selection signal SEL2 is applied to the selection transistor 125 of the pixel 120 in the m+1th column
  • the selection signal SEL3 is applied to the selection transistor 125 of the pixel 120 in the m+2th column.
  • edge images and low-tone images are generated based on kernel units of 3x3 pixels. This makes it possible to improve the resolution compared to a method in which edge images and low-tone images are generated based on kernel units of 4x4 pixels.
  • an edge image and a low gradation image are generated based on a kernel unit of 4 ⁇ 4 pixels.
  • an edge image is generated based on a kernel unit of 4 ⁇ 4 pixels, and a low gradation image is generated based on a kernel unit of 8 ⁇ 8 pixels.
  • FIG. 24 shows a readout method for a solid-state imaging device according to the fifth embodiment.
  • the kernel unit when generating an edge image, is set to 4x4 pixels. At this time, after edge signals are generated in kernel units for rows n to n+3, edge signals are generated in kernel units for rows n+4 to n+7 as shown in the figure, at b.
  • the kernel unit when generating a low-tone image, the kernel unit is set to 8 x 8 pixels. At this time, a low-tone image is generated based on the binning values of pixel signals read out from 64 pixels 120 included in the kernel unit of 8 x 8 pixels.
  • FIG. 25 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by a solid-state imaging device according to the fifth embodiment.
  • an edge signal is generated for the kernel unit from the nth row to the n+3th row based on non-destructive readout (P21), and then an edge signal is generated for the kernel unit from the nth row+4th row to the n+7th row (P22). Then, after an edge signal is generated for the kernel unit from the nth row to the n+7th row, a low gradation signal is generated for the kernel unit from the nth row to the n+7th row (P23).
  • edge signals for the kernel units from the nth row to the n+3th row (P21) and the generation of edge signals for the kernel units from the nth row to the n+7th row (P22) are the same as the generation of edge signals in FIG. 9 (P11).
  • the generation of low gradation signals for the kernel units from the nth row to the n+7th row (P23) is the same as the generation of low gradation signals in FIG. 9 (P12).
  • the binning signal BNE[n+3]-[n] rises, whereas in the generation of the low gradation signal for the kernel unit from row n to row n+7 (P23), the binning signal BNE[n+7]-[n] rises. Also, in the generation of the low gradation signal (P12) in FIG. 9, the selection signals SEL1[n]-[n+3] and SEL2[n]-[n+3] are set to high level.
  • the selection signals SEL1[n]-[n+7] and SEL2[n]-[n+7] are set to high level.
  • a P-phase readout is performed (K31) for each pixel 120-1 to 120-4 of the kernel unit from the nth row to the n+3th row, followed by a D-phase readout (K32).
  • a P-phase readout is performed (K33) for each pixel 120-1 to 120-4 of the kernel unit from the nth row to the n+7th row, followed by a D-phase readout (K34).
  • a D-phase readout is performed (K35) for each pixel 120 of the kernel unit from the nth row to the n+7th row, followed by a P-phase readout (K36).
  • the size of the kernel unit is made different when generating the edge signal and when generating the gradation signal. This makes it possible to reduce the time required to generate a low gradation image while preventing a decrease in the resolution of the edge image in each frame.
  • the kernel unit when generating a low-tone image is an integer multiple of the kernel unit when generating an edge signal.
  • a low gradation image is generated based on the binning values of pixel signals read from all pixels 120 included in the kernel unit.
  • a low gradation image is generated based on the binning values of pixel signals read from the pixels 120 included in the kernel unit, excluding the pixels 120-1 to 120-4 used in generating the edge signals.
  • FIG. 26 is a block diagram showing an example of switching of signal paths when an edge image is generated by a solid-state imaging device according to the sixth embodiment.
  • a vertical signal line 132 is provided instead of the vertical signal lines 132-1 and 132-2 of the first embodiment described above.
  • the selection transistor 125 of each pixel 120 is connected to the vertical signal line 132.
  • the pixel signals are read out at separate times for the pixels 120-1 to 120-4 used to generate the edge signal and the other pixels 120. Therefore, when signals are read out from the pixels 120-1 to 120-4 in the same column, they do not collide with signals read out from other pixels 120, and one vertical signal line 132 can be provided for each column.
  • this solid-state imaging device is provided with a multiplexer 163 instead of the multiplexer 161 of the first embodiment described above.
  • the rest of the configuration of the solid-state imaging device of the sixth embodiment is the same as the configuration of the solid-state imaging device of the first embodiment described above.
  • the multiplexer 163 switches the input to each of the comparators 171-1 to 171-4 when an edge signal is generated and when a low gradation signal is generated. At this time, the multiplexer 163 can switch the connection between the vertical signal line 132 and the input of each of the comparators 171-1 to 171-4 so that pixel signals from two pixels are input to each of the comparators 171-1 to 171-4 in different combinations when an edge signal is generated. In addition, the multiplexer 163 can switch the connection between the vertical signal line 132 and the input of each of the comparators 171-1 to 171-4 so that pixel signals read out on a kernel basis and level signals VF1 to VF4 are input to each of the comparators 171-1 to 171-4 when a low gradation signal is generated.
  • the multiplexer 163 can switch the connection between each vertical signal line 132 and the input of each comparator 171-1 to 171-4 so that the pixel signal read out on a pixel-by-pixel basis and the ramp signal RAP are input to each comparator 171-1 to 171-4.
  • the multiplexer 161 includes switches 163-1 to 163-4. Each switch 163-1 to 163-4 is provided for each column. The input terminals of each switch 163-1 to 163-4 are provided for each vertical signal line 132. The output terminals of each switch 163-1 to 163-4 are connected to the inverting input terminals of each comparator 171-1 to 171-4.
  • the solid-state imaging device generates an edge image.
  • the selection transistor 125 is turned on and the binning transistor 127 is turned off.
  • the selection transistor 125 and the binning transistor 127 are turned off.
  • the vertical signal line 132 to which pixel 120-1 is connected is connected to comparator 171-1 via switch 163-1.
  • the vertical signal line 132 to which pixel 120-4 is connected is connected to comparator 171-2 via switch 163-2.
  • the vertical signal line 132 to which pixel 120-3 is connected is connected to comparator 171-4 via switch 163-4.
  • the vertical signal line 132 to which pixel 120-4 is connected is connected to comparator 171-3 via switch 163-3.
  • the vertical signal line 132 to which pixel 120-1 is connected is connected to the gain section 281-3 via switch 163-1, switch 261-1, and selector 271-3.
  • the vertical signal line 132 to which pixel 120-4 is connected is connected to the gain section 281-4 via switch 163-2, switch 261-2, and selector 271-4.
  • the vertical signal line 132 to which pixel 120-3 is connected is connected to the gain section 281-2 via switch 163-4, switch 261-4, and selector 271-2.
  • the vertical signal line 132 to which pixel 120-2 is connected is connected to the gain section 281-1 via switch 163-3, switch 261-3, and selector 271-1.
  • FIG. 27 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the sixth embodiment.
  • the solid-state imaging device generates a low-tone image.
  • the selection transistors 125 and binning transistors 127 are turned on in the 16 pixels 120 included in the kernel unit, excluding the pixels 120-1 to 120-4 used to generate the edge signal.
  • the vertical signal line 132 to which the pixel 120 in the mth column included in the kernel unit is connected is connected to the comparator 171-1 via the switch 163-1.
  • the vertical signal line 132 to which the pixel 120 in the m+1th column included in the kernel unit is connected is connected to the comparator 171-2 via the switch 163-2.
  • the vertical signal line 132 to which the pixel 120 in the m+2th column included in the kernel unit is connected is connected to the comparator 171-3 via the switch 163-3.
  • the vertical signal line 132 to which the pixel 120 in the m+3th column included in the kernel unit is connected is connected to the comparator 171-4 via the switch 163-4. At this time, the switches 261-1 to 261-4 are turned off.
  • the level signal VF1 generated by the level signal generating unit 154 is input to the gain unit 281-1 via the reference signal switching unit 155 and the selector 271-1.
  • the level signal VF2 generated by the level signal generating unit 154 is input to the gain unit 281-2 via the reference signal switching unit 155 and the selector 271-2.
  • the level signal VF3 generated by the level signal generating unit 154 is input to the gain unit 281-3 via the reference signal switching unit 155 and the selector 271-3.
  • the level signal VF4 generated by the level signal generating unit 154 is input to the gain unit 281-4 via the reference signal switching unit 155 and the selector 271-4. At this time, the gain of each of the gain units 281-1 to 281-4 is set to 1.
  • FIG. 28 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by a solid-state imaging device according to the sixth embodiment.
  • the selection control driver 142 generates selection signals SEL, SELE, transfer signals TRG, TRGE, and binning signals BNE, BNEE.
  • the selection signal SELE is applied to the selection transistors 125 of the pixels 120-1 to 120-4 used to generate the edge signal.
  • the selection signal SEL is applied to the selection transistors 125 of the pixels 120 not used to generate the edge signal.
  • the transfer signal TRGE is applied to the transfer transistors 122 of the pixels 120-1 to 120-4 used to generate the edge signal.
  • the transfer signal TRG is applied to the transfer transistors 122 of the pixels 120 not used to generate the edge signal.
  • the binning signal BNEE is applied to the binning transistors 127 of the pixels 120-1 to 120-4 used to generate the edge signal.
  • the binning signal BNE is applied to the binning transistors 127 of the pixels 120 that are not used to generate the edge signal.
  • an edge signal is generated based on non-destructive readout (P41), and then a low gradation signal is generated (P42).
  • a P-phase readout is performed for each pixel 120-1 to 120-4 (K41), and then a D-phase readout is performed (K42).
  • an edge signal is generated based on AD conversion of the signal level.
  • a P-phase readout is performed for each pixel 120 except for the pixels 120-1 to 120-4 used in generating the edge signal (K43), and then a D-phase readout is performed (K44).
  • a gradation signal is generated based on AD conversion of the binning value of the signal level after an auto-zero operation based on the binning value of the reset level.
  • CDS can be performed.
  • the switching signal RSW is set to a low level.
  • the input of the selector 271-1 is switched to the switch 261-3 side
  • the input of the selector 271-2 is switched to the switch 261-4 side
  • the input of the selector 271-3 is switched to the switch 261-1 side
  • the input of the selector 271-4 is switched to the switch 261-2 side.
  • each of the switches 261-1 to 261-4 is turned on.
  • the switch 161-1 is connected to the vertical signal line 132 to which the pixel 120-1 is connected.
  • the switch 161-2 is connected to the vertical signal line 132 to which the pixel 120-4 is connected.
  • the switch 161-3 is connected to the vertical signal line 132 to which the pixel 120-3 is connected.
  • the switch 161-4 is connected to the vertical signal line 132 to which the pixel 120-2 is connected.
  • the reset signal RST[n+3]-[n] rises (t41), turning on the reset transistor 123 of the pixel 120 included in the kernel unit and resetting the floating diffusion 126.
  • the auto-zero signal AZ rises (t41), activating the auto-zero operation of each of the comparators 171-1 to 171-4.
  • the charge stored in the DC-cut capacitors 291 and 292 is controlled so that the non-inverting input and the inverting input of each of the comparators 171-1 to 171-4 are balanced.
  • the selection signal SELE[n+3]-[n] is set to a high level, and the selection signal SEL[n+3]-[n] is set to a low level (t41).
  • the selection transistors 125 of the pixels 120-1 to 120-4 are turned on, and the selection transistors 125 of the other pixels 120 are turned off.
  • the reset signal RST[n+3]-[n] falls (t42), and the reset transistor 123 of the pixel 120 included in the kernel unit is turned off.
  • the potential VLc1 of the vertical signal line 132 to which pixel 120-1 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-1 is applied to the gate of the amplification transistor 124.
  • the potential VLc2 of the vertical signal line 132 to which pixel 120-4 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-4 is applied to the gate of the amplification transistor 124.
  • the potential VLc3 of the vertical signal line 132 to which pixel 120-3 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-3 is applied to the gate of the amplification transistor 124.
  • the potential VLc4 of the vertical signal line 132 to which pixel 120-2 is connected is set based on the source follower action when the reset level of the floating diffusion 126 of pixel 120-2 is applied to the gate of the amplification transistor 124.
  • the transfer signal TRGE[n+3]-[n] rises (t44).
  • the transfer transistors 122 of the pixels 120-1 to 120-4 are turned on, and the charge accumulated in the photodiodes 121 is transferred to the floating diffusion 126.
  • the potential VLc1 of the vertical signal line 132 to which pixel 120-1 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-1 is applied to the gate of the amplification transistor 124. Furthermore, the potential VLc2 of the vertical signal line 132 to which pixel 120-4 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-4 is applied to the gate of the amplification transistor 124.
  • the potential VLc3 of the vertical signal line 132 to which pixel 120-3 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-3 is applied to the gate of the amplification transistor 124.
  • the potential VLc4 of the vertical signal line 132 to which pixel 120-2 is connected is set based on the source follower action when the cathode potential of the photodiode 121 of pixel 120-2 is applied to the gate of the amplification transistor 124.
  • the transfer signal TRG[n+3]-[n] falls, and the transfer transistor 122 of the pixel 120 included in the kernel unit is turned off.
  • the potential VLc1 of the vertical signal line 132 to which pixel 120-1 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-1 is applied to the gate of the amplification transistor 124.
  • the potential VLc2 of the vertical signal line 132 to which pixel 120-4 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-4 is applied to the gate of the amplification transistor 124.
  • the potential VLc3 of the vertical signal line 132 to which pixel 120-3 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-3 is applied to the gate of the amplification transistor 124.
  • the potential VLc4 of the vertical signal line 132 to which pixel 120-2 is connected is set based on the source follower action when the signal level of the floating diffusion 126 of pixel 120-2 is applied to the gate of the amplification transistor 124.
  • the potential VLc1 of the vertical signal line 132 to which the pixel 120-1 is connected is compared with the potential VLc2 of the vertical signal line 132 to which the pixel 120-4 is connected.
  • the potential VLc3 of the vertical signal line 132 to which the pixel 120-3 is connected is compared with the potential VLc4 of the vertical signal line 132 to which the pixel 120-2 is connected.
  • the potentials VLc1 to VLc4 input to the non-inverting input terminals of each of the comparators 171-1 to 171-4 may be multiplied by a gain G.
  • the outputs of each of the comparators 171-1 to 171-4 are input to the NAND circuits 191-1 to 191-4 via the inverters 181-1 to 181-4, respectively.
  • the output enable signal VOE rises (t45).
  • the comparison results VO1 to VO4 of the comparators 171-1 to 171-4 are output as edge signals via the inverters 181-1 to 181-4 and the NAND circuits 191-1 to 191-4, respectively.
  • the switching signal RSW is set to a high level.
  • the input of the selector 271-1 is switched to the level signal VF1
  • the input of the selector 271-2 is switched to the level signal VF2
  • the input of the selector 271-3 is switched to the level signal VF3
  • the input of the selector 271-4 is switched to the level signal VF4.
  • each of the switches 261-1 to 261-4 is turned off.
  • the switch 161-1 is connected to the vertical signal line 132 of the mth column.
  • the switch 161-2 is connected to the vertical signal line 132 of the m+1th column.
  • the switch 161-3 is connected to the vertical signal line 132 of the m+2th column.
  • the switch 161-4 is connected to the vertical signal line 132 of the m+3th column.
  • the output enable signal VOE also falls (t46).
  • the reset signal RST[n+3]-[n] also rises (t46), turning on the reset transistor 123 of the pixel 120 included in the kernel unit and resetting the floating diffusion 126.
  • the auto-zero signal AZ also rises (t46), activating the auto-zero operation of each of the comparators 171-1 to 171-4.
  • the binning signal BNE[n+3]-[n] also rises, turning on the binning transistors 127 of the pixels 120 other than the pixels 120-1 to 120-4.
  • the selection signal SELE[n+3]-[n] also falls, and the selection signal SEL[n+3]-[n] also rises (t46). At this time, the selection transistors 125 of the pixels 120-1 to 120-4 are turned off, and the selection transistors 125 of the other pixels 120 are turned on.
  • the reset signal RST[n+3]-[n] falls, turning off the reset transistor 123 of the pixel 120 included in the kernel unit.
  • the potential VLc of the vertical signal line 132 of the mth to m+3th columns of the kernel unit is set based on the source follower operation when the binning value of the reset level of the pixels 120 other than the pixels 120-1 to 120-4 is applied to the gate of the amplification transistor 124 (t47).
  • the potential VLc of the vertical signal line 132 of the mth to m+3th columns of the kernel unit is applied to the inverting input terminal of each of the comparators 171-1 to 171-4 via the DC cut capacitor 292
  • charge is accumulated in each of the DC cut capacitors 291, 292 so that the non-inverting input and the inverting input of each of the comparators 171-1 to 171-4 are balanced.
  • the charge accumulated in the DC cut capacitors 291, 292 connected to each of the comparators 171-1 to 171-4 reflects the binning value of the reset level of the 16 pixels 120 included in the kernel unit.
  • the transfer signal TRG[n+3]-[n] rises (t48).
  • the transfer transistors 122 of the pixels 120 other than pixels 120-1 to 120-4 are turned on, and the charge accumulated in the photodiodes 121 is transferred to the floating diffusion 126.
  • the transfer signal TRG[n+3]-[n] falls, and the transfer transistors 122 of the pixels 120 other than pixels 120-1 to 120-4 are turned off.
  • the potential VLc of the vertical signal line 132 of the mth to (m+3)th columns of the kernel unit is set based on the source follower operation when the binning values of the signal levels of the pixels 120 other than the pixels 120-1 to 120-4 are applied to the gates of the amplification transistors 124.
  • the potential VLc of the vertical signal line 132 is compared with the level signals VF1 to VF4 in a state in which charge is stored in each of the DC cut capacitors 291, 292 so that the binning values of the reset levels of the pixels 120 other than the pixels 120-1 to 120-4 are reflected.
  • a low gradation signal can be generated based on the analog CDS.
  • the outputs of the comparators 171-1 to 171-4 are input to the NAND circuits 191-1 to 191-4 via the inverters 181-1 to 181-4, respectively.
  • the output enable signal VOE rises (t49).
  • the comparison results VO1 to VO4 of the comparators 171-1 to 171-4 are output as low gradation signals via the inverters 181-1 to 181-4 and the NAND circuits 191-1 to 191-4, respectively.
  • FIG. 29 is a circuit diagram showing an example of the configuration of a pixel array section of a solid-state imaging device according to the sixth embodiment.
  • 4 x 4 pixels 120 are arranged in kernel units in the pixel array section 111.
  • the pixels 120 are connected so that reading from the pixels 120-1 to 120-4 used to generate edge signals and reading from the other pixels 120 can be performed separately.
  • the selection signal SELE is applied to the selection transistors 125 of each of the pixels 120-1 to 120-4, and the selection signal SEL is applied to the selection transistors 125 of the other pixels 120.
  • the transfer signal TRGE is applied to the transfer transistors 122 of each of the pixels 120-1 to 120-4, and the transfer signal TRG is applied to the transfer transistors 122 of the other pixels 120.
  • the binning signal BNEE is applied to the binning transistors 127 of each of the pixels 120-1 to 120-4, and the binning signal BNE is applied to the binning transistors 127 of the other pixels 120.
  • a low-tone image is generated based on the binning values of pixel signals read from the pixels 120 included in the kernel unit, excluding the pixels 120-1 to 120-4 used to generate the edge signals. This makes it possible to generate a low-tone image based on the CDS, thereby improving the image quality of the low-tone image.
  • a low gradation image is generated based on a comparison result between the binning value of the pixel signals read from the pixels 120 excluding the pixels 120-1 to 120-4 used to generate the edge signal and each of the level signals VF1 to VF4.
  • a low gradation image is generated based on a comparison result between the binning value of the pixel signals read from the pixels 120 excluding the pixels 120-1 to 120-4 used to generate the edge signal and the ramp signal RAP.
  • FIG. 30 is a block diagram showing an example of signal path switching when a gradation image is generated by a solid-state imaging device according to the seventh embodiment.
  • this solid-state imaging device has comparators 172-1 to 172-4 instead of comparators 171-1 to 171-4 of the sixth embodiment described above.
  • the rest of the configuration of the solid-state imaging device of the seventh embodiment is the same as the configuration of the solid-state imaging device of the sixth embodiment described above.
  • An active control signal CTL is input to each of the comparators 172-1 to 172-4.
  • the timing of activation of the AD conversion of each of the comparators 172-1 to 172-4 is controlled based on the active control signal CTL.
  • the timing of the AD conversion of each of the comparators 172-1 to 172-4 may be controlled separately for columns to be activated and columns to be deactivated. At this time, in the columns to be activated, each of the comparators 172-1 to 172-4 may be activated, and in the columns to be deactivated, each of the comparators 172-1 to 172-4 may be set to a standby state.
  • the solid-state imaging device generates a low-tone image.
  • the selection transistors 125 and binning transistors 127 are turned on in the 16 pixels 120 included in the kernel unit, excluding the pixels 120-1 to 120-4 used to generate the edge signal.
  • the vertical signal line 132 to which the pixel 120 in the mth column included in the kernel unit is connected is connected to the comparator 171-1 via the switch 163-1.
  • the vertical signal line 132 to which the pixel 120 in the m+1th column included in the kernel unit is connected is connected to the comparator 171-2 via the switch 163-2.
  • the vertical signal line 132 to which the pixel 120 in the m+2th column included in the kernel unit is connected is connected to the comparator 171-3 via the switch 163-3.
  • the vertical signal line 132 to which the pixel 120 in the m+3th column included in the kernel unit is connected is connected to the comparator 171-4 via the switch 163-4. At this time, the switches 261-1 to 261-4 are turned off.
  • the ramp signal RAP is input to the gain units 281-1 to 281-4 via the selectors 271-1 to 271-4, respectively. At this time, the gain of each of the gain units 281-1 to 281-4 is set to 1.
  • FIG. 31 is a timing chart showing an example of waveforms at various parts when an edge image and a gradation image are generated by a solid-state imaging device according to the seventh embodiment.
  • an edge signal is generated based on non-destructive readout (P41), and then a low gradation signal is generated (P52).
  • a P-phase readout is performed for each of the pixels 120-1 to 120-4 (K41), and then a D-phase readout is performed (K42).
  • a P-phase readout is performed for each pixel 120 except for the pixels 120-1 to 120-4 used in generating the edge signal (K53), and then a D-phase readout is performed (K54).
  • CDS can be performed.
  • the generation of the edge signal (t51 to t56) is similar to the generation of the edge signal (t41 to t46) in the sixth embodiment described above.
  • the switching signal RSW When generating a low gradation signal, the switching signal RSW is set to a high level. At this time, the input of each of the selectors 271-1 to 271-4 is switched to the ramp signal RAP. Also, each of the switches 261-1 to 261-4 is turned off. Furthermore, the switch 161-1 is connected to the vertical signal line 132 of the mth column. The switch 161-2 is connected to the vertical signal line 132 of the m+1th column. The switch 161-3 is connected to the vertical signal line 132 of the m+2th column. The switch 161-4 is connected to the vertical signal line 132 of the m+3th column.
  • the reset signal RST[n+3]-[n] falls, and the reset transistor 123 of the pixel 120 included in the kernel unit is turned off.
  • the potential VLc of the vertical signal line 132 of the mth to (m+3)th columns of the kernel unit is set based on the source follower operation when the binning values of the reset levels of the pixels 120 other than the pixels 120-1 to 120-4 are applied to the gates of the amplification transistors 124 (t57).
  • the ramp signal RAP is supplied to each of the comparators 171-1 to 171-4 as a reference signal, and the output enable signal VOE rises.
  • the comparator 171-1 may be activated, and each of the comparators 171-2 to 171-4 may be set to a standby state.
  • the potential VLc of the vertical signal line 132 corresponding to the reset level is compared with the ramp signal RAP, and the timing when the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132 is output as the comparison result VO1 (t58).
  • the binning values of the reset levels read out from the pixels 120 other than the pixels 120-1 to 120-4 are AD converted.
  • the output enable signal VOE falls and the transfer signal TRG[n+3]-[n] rises.
  • the transfer transistors 122 of the pixels 120 other than pixels 120-1 to 120-4 turn on, and the charge accumulated in the photodiodes 121 is transferred to the floating diffusion 126.
  • the transfer signal TRG[n+3]-[n] falls, and the transfer transistors 122 of the pixels 120 other than pixels 120-1 to 120-4 are turned off.
  • the potential VLc of the vertical signal line 132 of the mth to (m+3)th columns of the kernel unit is set based on the source follower operation when the binning values of the signal levels of the pixels 120 other than the pixels 120-1 to 120-4 are applied to the gates of the amplification transistors 124.
  • the ramp signal RAP is supplied to each of the comparators 171-1 to 171-4 as a reference signal, and the output enable signal VOE rises.
  • the comparator 171-1 the potential VLc of the vertical signal line 132 corresponding to the signal level is compared with the ramp signal RAP, and the timing when the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132 is output as the comparison result VO1 (t59).
  • the binning values of the signal levels read out from the pixels 120 other than the pixels 120-1 to 120-4 are AD converted based on the counting operation until the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132.
  • a low-tone image is generated based on the result of comparing the binning values of the pixel signals read from the pixels 120 excluding the pixels 120-1 to 120-4 used to generate the edge signal with the ramp signal RAP. This makes it possible to generate a low-tone image based on the CDS, and to increase the number of gradations of the low-tone image without increasing the number of comparators 171-1 to 171-4.
  • the level signals VF1 to VF4 are supplied to the selectors 271-1 to 271-4, respectively, in order to supply the reference signals used in generating low gradation images to the comparators 171-1 to 171-4.
  • the level signals supplied to the selectors 271-1 to 271-4 are multiplied by a gain and supplied to the comparators 171-1 to 171-4.
  • FIG. 32 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the eighth embodiment.
  • this solid-state imaging device includes gain units 282-1 to 282-4 instead of the gain units 281-1 to 281-4 of the first embodiment described above. Also, in this solid-state imaging device, the level signal generation unit 154 generates a level signal VF instead of level signals VF1 to VF4, and supplies it to each of the selectors 271-1 to 271-4.
  • the rest of the configuration of the solid-state imaging device of the eighth embodiment is the same as the configuration of the solid-state imaging device of the first embodiment described above.
  • Each of the gain units 282-1 to 282-4 applies a different gain G1 to G4 to the level signal VF and supplies the result to each of the comparators 171-1 to 171-4.
  • the gain unit 282-1 can multiply the level signal VF by the gain G1 to generate the level signal VF1.
  • the gain unit 282-2 can multiply the level signal VF by the gain G2 to generate the level signal VF2.
  • the gain unit 282-3 can multiply the level signal VF by the gain G3 to generate the level signal VF3.
  • the gain unit 282-4 can multiply the level signal VF by the gain G4 to generate the level signal VF4.
  • FIG. 33 is a circuit diagram showing an example of the configuration of a gain section of a solid-state imaging device according to the eighth embodiment.
  • each of the gain sections 282-1 to 282-4 includes capacitances 301 to 304 and switches 311 to 314.
  • Each of the capacitances 301 to 304 and each of the switches 311 to 314 are connected in series, and the series circuits of each of the capacitances 301 to 304 and each of the switches 311 to 314 are connected in parallel.
  • the capacitance value of the capacitance 301 is C
  • the capacitance value of the capacitance 302 can be set to 0.75C
  • the capacitance value of the capacitance 304 to 0.25C.
  • Each of the switches 311 to 314 switches between the ground potential and the level signal VF and inputs it to each of the capacitances 301 to 304. At this time, the gain can be changed by switching each of the switches 311 to 314.
  • the gain can be set to 1 by switching each switch 311 to 314 to input the level signal VF.
  • the gain can be set to 0.75 by switching each switch 311, 312 to input the level signal VF.
  • the gain can be set to 0.5 by switching each switch 311 to input the level signal VF.
  • the gain can be set to 0.25 by switching each switch 313, 314 to the input of the level signal VF.
  • the level signal VF supplied to the selectors 271-1 to 271-4 is multiplied by a gain and supplied as a reference signal to each of the comparators 171-1 to 171-4. This allows the wiring that supplies the level signal VF to the selectors 271-1 to 271-4 to be common, eliminating the need to provide wiring that supplies the level signals VF1 to VF4 for each of the selectors 271-1 to 271-4.
  • the reset transistor 123, the amplification transistor 124, the selection transistor 125, and the binning transistor 127 are provided for each pixel 120.
  • the reset transistor 123, the amplification transistor 124, the selection transistor 125, and the binning transistor 127 are shared by a plurality of pixels.
  • FIG. 34 is a circuit diagram showing an example of the configuration of a pixel provided in a solid-state imaging device according to the ninth embodiment.
  • cell 620 includes photodiodes 121-1 to 121-4 and transfer transistors 122-1 to 122-4 instead of photodiode 121 and transfer transistor 122 of the first embodiment described above.
  • the rest of the configuration of cell 620 of the ninth embodiment is the same as the configuration of pixel 120 of the first embodiment described above.
  • the photodiodes 121-1 to 121-4 can be arranged in 2 rows and 2 columns. In this case, each of the photodiodes 121-1 to 121-4 can form a pixel. Each of the photodiodes 121-1 to 121-4 is connected to the floating diffusion 126 via a transfer transistor 122-1 to 122-4, respectively. Transfer signals TRG1 to TRG4 are applied to the gates of the transfer transistors 122-1 to 122-4. By controlling the application timing of the transfer signals TRG1 to TRG4, signals can be read out individually from each of the photodiodes 121-1 to 121-4, or signals can be binned and read out from each of the photodiodes 121-1 to 121-4.
  • the binning signal BNE When reading out signals individually from cells 620, the binning signal BNE is set to a low level, and the binning transistor 127 of the cell 620 is turned off. On the other hand, when reading out signals by binning from the cell 620, the binning signal BNE is set to a high level, and the binning transistor 127 of the cell 620 is turned on.
  • FIG. 35 is a circuit diagram showing an example of the configuration of a pixel array section of a solid-state imaging device according to the ninth embodiment.
  • the cells 620 are arranged in a matrix in the row and column directions.
  • the kernel unit may be set with the cell 620 as a unit, or the kernel unit may be set with each of the photodiodes 121-1 to 121-4 as a unit.
  • an edge signal may be generated based on pixel signals read out individually from each of photodiodes 121-1 to 121-4, and a low gradation signal may be generated based on pixel signals read out by binning from cell 620.
  • an edge signal may be generated based on pixel signals read out by binning from cell 620, and a low gradation signal may be generated based on pixel signals read out by binning from cell 620.
  • the reset transistor 123, the amplification transistor 124, the selection transistor 125, and the binning transistor 127 are shared by multiple pixels. This makes it possible to improve the resolution of edge images and gradation images while suppressing an increase in pixel area.
  • the binning lines 133 are provided to connect the pixels 120 to each other in the row and column directions.
  • vertical signal lines that transmit pixel signals for each column are connected to each other, thereby binning pixel signals read out from the pixels 120 in different columns.
  • FIG. 36 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the tenth embodiment.
  • this solid-state imaging device has binning lines 133-1 and 133-2 instead of the binning line 133 of the first embodiment described above.
  • This solid-state imaging device also has connection switches 611-1 and 611-2 and a horizontal connection line 601 added to the solid-state imaging device of the first embodiment described above.
  • This solid-state imaging device also has cells 620 arranged in a matrix in the row and column directions instead of the pixels 120 of the first embodiment described above.
  • the rest of the configuration of the solid-state imaging device of the tenth embodiment is the same as the configuration of the solid-state imaging device of the first embodiment described above.
  • Each binning line 133-1, 133-2 is provided for each column.
  • Each binning line 133-1, 133-2 bins pixel signals read from pixels 120 in different rows.
  • connection switches 611-1 and 611-2 connect the vertical signal lines 132-1 and 132-2 of different columns.
  • the connection switch 611-1 is connected between the vertical signal line 132-1 and the horizontal connection line 601
  • the connection switch 611-2 is connected between the vertical signal line 132-2 and the horizontal connection line 601.
  • Each of the connection switches 611-1 and 611-2 can be turned on/off based on the opening/closing signal ⁇ Cn.
  • FIG. 37 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by a solid-state imaging device according to the tenth embodiment.
  • an edge signal is generated based on a non-destructive readout (P61), and then a low gradation signal is generated (P62).
  • P61 a non-destructive readout
  • K62 a D-phase readout
  • K63 a D-phase readout is performed for each cell 620, and then a P-phase readout is performed (K64).
  • pixel signals may be binned and read out from the four photodiodes 121-1 to 121-4 included in cell 620.
  • a transfer signal TRG is commonly applied to the gates of transfer transistors 122-1 to 122-4 of cell 620 as transfer signals TRG1 to TRG4.
  • an edge signal is generated when the opening/closing signal ⁇ Cn is at a low level (P61), and a low gradation signal is generated when the opening/closing signal ⁇ Cn is at a high level (P62). Except for this point, the generation of the edge signal (P11) and the generation of the low gradation signal (P12) in the first embodiment described above are the same.
  • the binning signal BNE rises, turning on the binning transistor 127. At this time, pixel signals read out from pixels 120 in different rows are binned via the binning lines 133-1 and 133-2. Also, in generating the low gradation signal (P62), the opening/closing signal ⁇ Cn rises, turning on the connection switches 611-1 and 611-2. At this time, pixel signals read out from pixels 120 in different columns are binned via the horizontal connection line 601.
  • the vertical signal lines 132-1, 132-2 that transmit pixel signals for each column are connected together, and pixel signals read from pixels 120 in different columns are binned. This eliminates the need to connect pixels 120 in different columns together via binning lines 133, and the wiring area for the binning lines 133 in the pixel array section 111 can be reduced.
  • the vertical signal lines 132-1 and 132-2 that transmit pixel signals for each column are connected to each other, thereby binning pixel signals read from pixels 120 in different columns.
  • the pixel signals read from pixels 120 in different columns are binned by sampling and holding the pixel signals read to the vertical signal lines 132-1 and 132-2.
  • FIG. 38 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the eleventh embodiment.
  • this solid-state imaging device is the same as the solid-state imaging device of the tenth embodiment described above, except that sample-and-hold switches 621-1 and 621-2 and capacitors 631-1 and 631-2 have been added.
  • the rest of the configuration of the solid-state imaging device of the eleventh embodiment is the same as the configuration of the solid-state imaging device of the first embodiment described above.
  • the sample and hold switch 621-1 and the capacitor 631-1 sample and hold the pixel signal read out to the vertical signal line 132-1.
  • the sample and hold switch 621-2 and the capacitor 631-2 sample and hold the pixel signal read out to the vertical signal line 132-2.
  • the sample and hold switch 621-1 is connected between the capacitor 631-1 and the vertical signal line 132-1, and the sample and hold switch 621-2 is connected between the capacitor 631-2 and the vertical signal line 132-2.
  • Each of the sample and hold switches 621-1 and 621-2 can be turned on/off based on the sample and hold signal SHE.
  • the connection switch 611-1 is connected between the sample and hold switch 621-1 and the horizontal connection line 601, and the connection switch 611-2 is connected between the sample and hold switch 621-2 and the horizontal connection line 601.
  • FIG. 39 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by a solid-state imaging device according to the eleventh embodiment.
  • an edge signal is generated based on a non-destructive readout (P71), and then a low gradation signal is generated (P72).
  • a P-phase readout is performed (K71) for the cell 620 used to generate the edge signal, and then a D-phase readout is performed (K72).
  • a D-phase readout is performed (K73) for each cell 620, and then a P-phase readout is performed (K74).
  • pixel signals may be binned and read out from the four photodiodes 121-1 to 121-4 included in cell 620.
  • a transfer signal TRG is commonly applied to the gates of transfer transistors 122-1 to 122-4 of cell 620 as transfer signals TRG1 to TRG4.
  • the binning signal BNE rises, turning on the binning transistor 127. At this time, pixel signals read out from pixels 120 in different rows are binned via the binning lines 133-1 and 133-2.
  • the sample and hold signal SHE rises (t16), turning on the sample and hold switches 621-1 and 621-2. At this time, the pixel signals of the signal levels read out to the vertical signal lines 132-1 and 132-2 are sampled and held in the capacitors 631-1 and 631-2, respectively.
  • the open/close signal ⁇ Cn rises, turning on the connection switches 611-1 and 611-2.
  • the pixel signals with the signal levels sampled and held in the capacitors 631-1 and 631-2 are binned via the horizontal connection line 601, and the pixel signals with the signal levels read out from the pixels 120 in different columns are binned (t17).
  • the reset signal RST rises (t18), turning on the reset transistor 123 and resetting the floating diffusion 126.
  • the sample and hold signal SHE rises (t18), turning on the sample and hold switches 621-1 and 621-2.
  • the reset level pixel signals read out to the vertical signal lines 132-1 and 132-2 are sampled and held in the capacitors 631-1 and 631-2, respectively.
  • the sample and hold signal SHE falls.
  • the open/close signal ⁇ Cn rises, turning on the connection switches 611-1 and 611-2.
  • the reset level pixel signals sampled and held in the capacitors 631-1 and 631-2 are binned via the horizontal connection line 601, and the reset level pixel signals read out from the pixels 120 in different columns are binned (t19).
  • the generation of the edge signal (P71) and the generation of the low gradation image (P72) in the eleventh embodiment are similar to the generation of the edge signal (P11) and the generation of the low gradation signal (P12) in the first embodiment described above.
  • pixel signals read out from pixels 120 in different columns are binned by sampling and holding the pixel signals read out to the vertical signal lines 132-1 and 132-2. This eliminates the need to connect pixels 120 in different columns via binning lines 133, and the wiring area for the binning lines 133 in the pixel array section 111 can be reduced.
  • the AD conversion unit 145 is shared between edge image generation and low gradation image generation, and the AD conversion unit operates as an edge ADC when generating edge images and as a flash ADC when generating low gradation images.
  • the AD conversion unit is divided between edge image generation and low gradation image generation.
  • FIG. 40 is a block diagram showing an example of the configuration of a solid-state imaging device according to the twelfth embodiment.
  • this solid-state imaging device 702 has a column readout circuit 713, a column signal processing unit 714, and a control circuit 716 instead of the column readout circuit 113, the column signal processing unit 114, and the control circuit 116 of the solid-state imaging device 102 of the first embodiment described above.
  • the rest of the configuration of the solid-state imaging device 702 of the 12th embodiment is the same as the configuration of the solid-state imaging device 102 of the first embodiment described above.
  • the column readout circuit 713 can read out pixel signals from the pixels in units of kernels to be convolved.
  • the column readout circuit 713 may configure a source follower between each pixel 120 when reading out a signal from each pixel 120.
  • the column signal processing unit 714 processes signals transmitted in the column direction from each pixel 120. At this time, the column signal processing unit 714 performs AD conversion processing based on the signals transmitted in the column direction from each pixel 120, and can output an edge signal G1, a low gradation signal G2, and a high gradation signal G3.
  • the column signal processing unit 714 includes AD conversion units 717 and 718.
  • the AD conversion unit 717 is used to generate the edge image G1.
  • the AD conversion unit 718 is used to generate the low gradation image G2 and the high gradation image G3.
  • the control circuit 716 controls the vertical scanning circuit 112, the column readout circuit 713, the column signal processing unit 714, and the horizontal scanning circuit 115.
  • the control circuit 716 controls so that a pixel signal is input to the AD conversion unit 717 when the edge image G1 is generated, and so that a pixel signal is input to the AD conversion unit 718 when the low gradation image G2 and the high gradation image G3 are generated.
  • the control of the control circuit 716 is similar to the control of the control circuit 116 in the first embodiment described above.
  • FIG. 41 is a block diagram showing an example of switching of signal paths when an edge image is generated by a solid-state imaging device according to the twelfth embodiment.
  • the column read circuit 713 has a multiplexer 761 instead of the multiplexer 161 of the column read circuit 113 of the first embodiment described above.
  • the column read circuit 713 omits the selectors 271-1 to 271-4 from the column read circuit 113 of the first embodiment described above.
  • the rest of the configuration of the column read circuit 713 of the twelfth embodiment is the same as the configuration of the column read circuit 113 of the first embodiment described above.
  • the multiplexer 761 When generating an edge signal, the multiplexer 761 switches the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 on a kernel-by-kernel basis. In addition, when generating a low gradation signal and a high gradation signal, the multiplexer 761 switches the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 771-1 to 771-4 on a kernel-by-kernel basis.
  • the multiplexer 761 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 so that pixel signals from two pixels are input to each of the comparators 171-1 to 171-4 in different combinations when generating an edge signal.
  • the multiplexer 761 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 771-1 to 771-4 so that the pixel signal read out on a kernel-by-kernel basis and the level signals VF1 to VF4 are input to each of the comparators 771-1 to 771-4.
  • the multiplexer 761 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 771-1 to 771-4 so that the pixel signal read out on a pixel-by-pixel basis and the ramp signal RAP are input to each of the comparators 771-1 to 771-4.
  • the multiplexer 761 includes switches 761-1 to 761-4. Each of the switches 761-1 to 761-4 is provided for each column. The input terminals of each of the switches 761-1 to 761-4 are provided for each of the vertical signal lines 132-1 and 132-2. The first output terminals of each of the switches 761-1 to 761-4 are connected to the inverting input terminals of each of the comparators 171-1 to 171-4. The second output terminals of each of the switches 761-1 to 761-4 are connected to the inverting input terminals of each of the comparators 771-1 to 771-4.
  • the rest of the configuration of the column readout circuit 713 of the twelfth embodiment is the same as the configuration of the column readout circuit 113 of the first embodiment described above.
  • the column signal processing unit 714 is obtained by adding comparators 771-1 to 771-4, inverters 781-1 to 781-4, and NAND circuits 791-1 to 791-4 to the column signal processing unit 114 of the first embodiment described above.
  • the rest of the configuration of the column signal processing unit 714 of the 12th embodiment is the same as the configuration of the column signal processing unit 114 of the first embodiment described above.
  • Comparators 771-1 to 771-4 are provided for each column. Comparator 771-1 compares level signal VF1 with the pixel signal output via switch 761-1. Comparator 771-2 compares level signal VF2 with the pixel signal output via switch 761-2. Comparator 771-3 compares level signal VF3 with the pixel signal output via switch 761-3. Comparator 771-4 compares level signal VF4 with the pixel signal output via switch 761-4.
  • Inverter 781-1 inverts the output of comparator 771-1 and inputs it to NAND circuit 791-1.
  • Inverter 781-2 inverts the output of comparator 771-2 and inputs it to NAND circuit 791-2.
  • Inverter 781-3 inverts the output of comparator 771-3 and inputs it to NAND circuit 791-3.
  • Inverter 781-4 inverts the output of comparator 771-4 and inputs it to NAND circuit 791-4.
  • NAND circuit 791-1 calculates the NAND of the output of inverter 781-1 and the output enable signal VOE.
  • NAND circuit 791-2 calculates the NAND of the output of inverter 781-2 and the output enable signal VOE.
  • NAND circuit 791-3 calculates the NAND of the output of inverter 781-3 and the output enable signal VOE.
  • NAND circuit 791-4 calculates the NAND of the output of inverter 781-4 and the output enable signal VOE.
  • the solid-state imaging device generates an edge image.
  • the selection transistor 125 is turned on and the binning transistor 127 is turned off.
  • the selection transistor 125 and the binning transistor 127 are turned off.
  • the vertical signal line 132-1 to which the pixel 120-1 is connected is connected to the comparator 171-1 via the switch 761-1.
  • the vertical signal line 132-1 to which the pixel 120-4 is connected is connected to the comparator 171-2 via the switch 761-2.
  • the vertical signal line 132-2 to which the pixel 120-3 is connected is connected to the comparator 171-4 via the switch 761-4.
  • the vertical signal line 732-2 to which the pixel 120-4 is connected is connected to the comparator 171-3 via the switch 161-3.
  • the vertical signal line 132-1 to which the pixel 120-1 is connected is connected to the gain section 281-3 via switches 761-1 and 261-1.
  • the vertical signal line 132-1 to which the pixel 120-4 is connected is connected to the gain section 281-4 via switches 761-2 and 261-2.
  • the vertical signal line 132-2 to which the pixel 120-3 is connected is connected to the gain section 281-2 via switches 761-4 and 261-4.
  • the vertical signal line 132-2 to which the pixel 120-2 is connected is connected to the gain section 281-1 via switches 761-3 and 261-3.
  • FIG. 42 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the twelfth embodiment.
  • the solid-state imaging device generates a low-tone image.
  • the selection transistors 125 and binning transistors 127 are turned on in the 16 pixels 120 included in the kernel unit.
  • the vertical signal lines 132-1 and 132-2 to which the pixels 120 in the mth column included in the kernel unit are connected are connected to the comparator 771-1 via the switch 761-1.
  • the vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+1th column included in the kernel unit are connected are connected to the comparator 771-2 via the switch 761-2.
  • the vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+2th column included in the kernel unit are connected are connected to the comparator 771-3 via the switch 761-3.
  • the vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+3th column included in the kernel unit are connected are connected to the comparator 771-4 via the switch 761-4.
  • each of the level signals VF1 to VF4 is input to the inverting input terminal of each of the comparators 771-1 to 771-4.
  • the comparison results VOB1 to VOB4 of each of the comparators 771-1 to 771-4 are output as low gradation signals via each of the inverters 781-1 to 781-4 and the NAND circuits 791-1 to 791-4.
  • an AD conversion unit 717 is provided for generating the edge image G1
  • an AD conversion unit 718 is provided for generating the low gradation image G2 and the high gradation image G3. This makes it possible to eliminate the need for the selectors 271-1 to 271-4 that switch the inputs to the comparators 171-1 to 171-4.
  • the AD conversion unit is shared between edge image generation and low gradation image generation, and the AD conversion unit operates as an edge ADC when generating edge images and operates as a flash ADC when generating low gradation images.
  • the AD conversion unit is divided between edge image generation and low gradation image generation, and the AD conversion unit used for low gradation image generation is a successive approximation type AD conversion unit.
  • FIG. 43 is a block diagram showing an example of the configuration of a solid-state imaging device according to the thirteenth embodiment.
  • this solid-state imaging device 802 has a column readout circuit 813, a column signal processing unit 814, and a control circuit 816 instead of the column readout circuit 113, the column signal processing unit 114, and the control circuit 116 of the solid-state imaging device 102 of the first embodiment described above.
  • the solid-state imaging device 802 has a multiplexer 817 and an AD conversion unit 818 added to the solid-state imaging device 102 of the first embodiment described above.
  • the rest of the configuration of the solid-state imaging device 802 of the thirteenth embodiment is the same as the configuration of the solid-state imaging device 102 of the first embodiment described above.
  • the column readout circuit 813 can read out pixel signals from the pixels in units of kernels to be convolved.
  • the column readout circuit 813 may configure a source follower between each pixel 120 when reading out a signal from each pixel 120.
  • the column signal processing unit 814 processes signals transmitted in the column direction from each pixel 120. At this time, the column signal processing unit 814 performs AD conversion processing based on the signals transmitted in the column direction from each pixel 120, and can output an edge signal G1 and a high gradation signal G3.
  • the column signal processing unit 814 includes an AD conversion unit 815.
  • the AD conversion unit 815 is used to generate the edge image G1 and the high gradation image G3.
  • the control circuit 816 controls the vertical scanning circuit 112, the column readout circuit 713, the column signal processing unit 714, the horizontal scanning circuit 115, the multiplexer 817, and the AD conversion unit 818.
  • the control circuit 816 controls so that pixel signals are input to the AD conversion unit 815 when the edge image G1 and the high gradation image G3 are generated, and so that pixel signals are input to the AD conversion unit 818 when the low gradation image G2 is generated.
  • the control of the control circuit 816 is similar to the control of the control circuit 116 in the first embodiment described above.
  • the multiplexer 817 inputs the pixel signals read out from each pixel 120 to the vertical signal line 132 to the AD conversion unit 818. At this time, the multiplexer 817 can switch the connection between the AD conversion unit 818 and the vertical signal line 132 on a kernel-by-kernel basis.
  • the AD conversion unit 818 is used to generate the low gradation image G2.
  • the AD conversion unit 818 may be a successive approximation type AD conversion unit.
  • the AD conversion unit 818 can AD convert the pixel signal output from the multiplexer 817 on a kernel-by-kernel basis and output it to the control circuit 816.
  • the exposure control unit 152 can perform exposure control based on the low gradation signal G2 output from the AD conversion unit 818.
  • the AD conversion unit is divided into one for generating edge images and one for generating low gradation images, and the AD conversion unit used for generating low gradation images is a successive approximation type AD conversion unit. This makes it possible to eliminate the need for selectors 271-1 to 271-4 that switch the inputs to each of comparators 171-1 to 171-4, and also reduces the number of comparators used for generating low gradation images.
  • an edge image and a low gradation image are generated based on a kernel unit of 4 ⁇ 4 pixels.
  • substrates on which a solid-state imaging device is formed the solid-state imaging device including a pixel array section 111 in which pixels 120 are arranged in a matrix, are laminated.
  • FIG. 44 is a perspective view showing an example configuration of an imaging device according to the fourteenth embodiment.
  • the solid-state imaging device 901 includes a support substrate 911 and a semiconductor substrate 912.
  • the semiconductor substrate 912 is stacked on the support substrate 911.
  • a pixel array section 913 and a peripheral circuit 914 are formed on the semiconductor substrate 912.
  • a column readout circuit 915 and a column ADC 916 are formed on the peripheral circuit 914.
  • the column readout circuit 915 and the column ADC 916 may be formed on both sides of the pixel array section 913 in the column direction.
  • the pixels 120 are arranged in a matrix in the row and column directions in the pixel array section 913.
  • the column readout circuit 915 can read out signals from each pixel 120 individually based on constant current readout, or can read out signals by binning.
  • the column ADC 916 can perform AD conversion on the signals read out via the column readout circuit 915 for each column.
  • the solid-state imaging device 901 can constitute a back-illuminated image sensor.
  • the solid-state imaging device 902 includes semiconductor substrates 921 and 922.
  • the semiconductor substrate 922 is stacked on the semiconductor substrate 921.
  • a pixel array section 923 is formed on the semiconductor substrate 922.
  • a peripheral circuit 924 is formed on the semiconductor substrate 922.
  • a column readout circuit 925 and a column ADC 926 are formed on the peripheral circuit 924.
  • the column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction.
  • the solid-state imaging device 902 can constitute a back-illuminated image sensor.
  • the substrates on which the solid-state imaging devices 901 and 902 are formed are stacked. This makes it possible to thin the semiconductor substrates 912 and 922 on which the pixel array sections 913 and 923 are formed while supporting the pixel array sections 913 and 923, respectively, and to form a back-illuminated image sensor.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.
  • FIG. 45 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
  • the body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps.
  • radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020.
  • the body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
  • the outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030.
  • the outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images.
  • the outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface based on the received images.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received.
  • the imaging unit 12031 can output the electrical signal as an image, or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects information inside the vehicle.
  • a driver state detection unit 12041 that detects the state of the driver is connected.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
  • the microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010.
  • the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 can also control the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby performing cooperative control aimed at automatic driving, which allows the vehicle to travel autonomously without relying on the driver's operation.
  • the microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching high beams to low beams.
  • the audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 46 shows an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 12100.
  • the imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100.
  • the imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100.
  • the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
  • FIG. 46 shows an example of the imaging ranges of the imaging units 12101 to 12104.
  • Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door.
  • an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for detecting phase differences.
  • the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles.
  • the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering the vehicle to avoid a collision via the drive system control unit 12010.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian.
  • the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian.
  • the audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology disclosed herein can be applied to the imaging unit 12031.
  • the camera 100 described above can be applied to the imaging unit 12031.
  • the above-described embodiment shows an example for realizing the present technology, and there is a corresponding relationship between the matters in the embodiment and the matters specifying the invention in the claims. Similarly, there is a corresponding relationship between the matters specifying the invention in the claims and the matters in the embodiment of the present technology that have the same name.
  • the present technology is not limited to the embodiment, and can be realized by making various modifications to the embodiment without departing from the gist of the technology.
  • the effects described in this specification are merely examples and are not limiting, and other effects may also be present.
  • the present technology can also be configured as follows.
  • a readout circuit that reads out pixel signals from pixels in units of kernels to be convolved; an imaging device comprising: a signal processing unit that performs an edge signal generation process based on pixel signals of a portion of pixels read out on a kernel basis, and performs a gradation signal generation process based on pixel signals read out including at least pixels among the pixels read out on a kernel basis that are not used to generate the edge signal.
  • the signal processing unit generates the edge signal and then generates the gradation signal within the same frame.
  • the imaging device described in (7) generates a gradation signal based on AD conversion of the binning value of the signal level after an auto-zero operation based on the binning value of the reset level for pixels among the pixels read out on a kernel basis that do not include pixels used to generate the edge signal.
  • the signal processing unit includes an AD conversion unit used to generate the edge signal and the gradation signal,
  • the AD conversion unit includes at least one of a flash AD converter and a single-slope AD converter.
  • the reference signal generation unit a first reference signal generating unit that generates a plurality of level signals; A second reference signal generating unit that generates a ramp signal; The imaging device according to (13), further comprising a reference signal switching unit that switches between an output of the level signal and an output of the ramp signal.
  • the AD conversion unit includes a comparator shared between generating the edge signal and generating the gradation signal
  • the multiplexer includes: when generating the edge signal, switching a connection between the signal line and the AD conversion unit so that pixel signals from two pixels are input to the comparator;
  • the imaging device according to any one of (11) to (14), wherein, when the gradation signal is generated, the connection between the signal line and the AD conversion unit is switched so that a pixel signal read out on a kernel basis and a reference signal to be compared with the pixel signal are input to the comparator.
  • the AD conversion unit is used in common for generating the edge signal and the gradation signal, and is also used in common for generating an imaging signal on a pixel-by-pixel basis
  • the multiplexer includes: when generating the edge signal, switching a connection between the signal line and the AD conversion unit so that pixel signals from two pixels are input to the comparator; When generating the gradation signal, a connection between the signal line and the AD conversion unit is switched so that a pixel signal read out on a kernel-by-kernel basis and a reference signal to be compared with the pixel signal are input to the comparator;
  • the imaging device according to any one of (11) to (15), wherein, when the imaging signal is generated, the connection between the signal line and the AD conversion unit is switched so that a pixel signal read out on a pixel-by-pixel basis and a reference signal to be compared with the pixel signal are input to the comparator.
  • a transfer control driver that controls transfer of the charge stored in the pixel; a selection control driver for controlling selection of a pixel from which the pixel signal is to be read; A reset control driver that controls resetting of charges accumulated in the pixels;
  • REFERENCE SIGNS LIST 100 camera 101 optical system 102 solid-state imaging device 103 imaging control unit 104 image processing unit 105 memory unit 106 display unit 107 operation unit 108 bus 111 pixel array unit 112 vertical scanning circuit 113 column readout circuit 114 column signal processing unit 115 horizontal scanning circuit 116 control circuit 120 pixel 121 photodiode 122 transfer transistor 123 reset transistor 124 amplifying transistor 125 selection transistor 126 floating diffusion 131 horizontal drive line 132 vertical signal line 141 transfer control driver 142 selection control driver 143 reset control driver 144 binning control driver 145 AD conversion unit 151 reference signal generation unit 152 exposure control unit 153 ramp signal generation unit 154 Level signal generating section 155 Reference signal switching section 161 Multiplexers 161-1 to 161-4, 261-1 to 261-4 Switches 171-1 to 171-4 Comparators 181-1 to 181-4 Inverters 191-1 to 191-4 NAND circuits 251-1 to 251-4 Current sources 271-1 to 271-4 Selectors 281-1 to 281-4 Gain sections 291, 292 DC

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Abstract

The present invention makes it possible to utilize, as a gradation signal, a pixel signal not used for generating an edge signal.　This imaging device comprises: a readout circuit that reads out pixel signals from pixels on a per-kernel basis, the kernel being subjected to convolution processing; and a signal processing unit that performs processing for generating an edge signal on the basis of pixel signals of some of the pixels read out on a per-kernel basis, and performs processing for generating a gradation signal on the basis of read-out pixel signals including at least a pixel not used for generating the edge signal among the pixels read out on a per-kernel basis. The signal processing unit may generate the gradation signal after generating the edge signal in the same frame.

Description

撮像装置Imaging device
　本技術は、撮像装置に関する。詳しくは、本技術は、画像のエッジを検出可能な撮像装置に関する。 This technology relates to an imaging device. More specifically, this technology relates to an imaging device capable of detecting edges in an image.
　撮像装置では、隣接画素間の輝度の比較結果に基づいてエッジを検出するものがある。例えば、垂直読み出し線上に別々のタイミングで転送される隣接行の電気信号を比較する回路を備えて、エッジ信号を生成する固体撮像装置が提案されている（例えば、特許文献１参照）。 Some imaging devices detect edges based on the results of comparing the brightness of adjacent pixels. For example, a solid-state imaging device has been proposed that generates an edge signal by including a circuit that compares electrical signals from adjacent rows transferred at different times onto a vertical readout line (see, for example, Patent Document 1).
特開平１１－２２５２８９号公報Japanese Patent Application Laid-Open No. 11-225289
　しかしながら、上述の従来技術では、エッジ信号の生成に用いられない画素信号は無駄になるため、画素信号を用いた撮像制御の制御性の低下を招くおそれがあった。 However, in the conventional technology described above, pixel signals that are not used to generate edge signals are wasted, which may lead to a decrease in controllability of imaging control using pixel signals.
　本技術はこのような状況に鑑みて生み出されたものであり、エッジ信号の生成に用いられない画素信号を階調信号として利用可能とすることを目的とする。 This technology was developed in light of these circumstances, and aims to make it possible to use pixel signals that are not used to generate edge signals as gradation signals.
　本技術は、上述の問題点を解消するためになされたものであり、その第１の側面は、畳み込み処理されるカーネル単位で画素から画素信号を読出す読出回路と、前記カーネル単位で読出された一部の画素の画素信号に基づいてエッジ信号の生成処理を実施するとともに、前記カーネル単位で読出された画素のうち前記エッジ信号の生成に用いられない画素を少なくとも含んで読出された画素信号に基づいて階調信号の生成処理を実施する信号処理部とを備える撮像装置である。これにより、エッジ信号の生成に用いられない画素信号が階調信号の生成に利用されるという作用をもたらす。 The present technology has been made to solve the above-mentioned problems, and a first aspect of the technology is an imaging device that includes a readout circuit that reads out pixel signals from pixels in units of kernels that are subjected to convolution processing, and a signal processing unit that performs processing to generate an edge signal based on pixel signals of some of the pixels read out in units of kernels, and performs processing to generate a gradation signal based on pixel signals that include at least pixels that are not used to generate the edge signal among the pixels read out in units of kernels. This brings about the effect that pixel signals that are not used to generate the edge signal are used to generate the gradation signal.
　また、第１の側面において、前記信号処理部は、同一フレーム内において、前記エッジ信号を生成した後、前記階調信号を生成してもよい。これにより、同一フレーム内の画素信号に基づいて、エッジ信号および階調信号が生成されるという作用をもたらす。 In addition, in the first aspect, the signal processing unit may generate the edge signal and then generate the gradation signal within the same frame. This provides the effect of generating the edge signal and the gradation signal based on pixel signals within the same frame.
　また、第１の側面において、前記読出回路は、前記エッジ信号の生成に用いられる前記画素信号を前記画素から非破壊で読出した後、前記階調信号の生成に用いられる前記画素信号を前記画素から非破壊で読出してもよい。これにより、エッジ信号の生成に用いられた画素信号を含んで階調信号が生成されるという作用をもたらす。 In addition, in the first aspect, the readout circuit may non-destructively read out from the pixel the pixel signal used to generate the edge signal, and then non-destructively read out from the pixel the pixel signal used to generate the gradation signal. This provides the effect of generating a gradation signal including the pixel signal used to generate the edge signal.
　また、第１の側面において、前記エッジ信号の生成に用いられる画素は、行および列がそれぞれ互い異なるように選択されてもよい。これにより、エッジ信号の生成に用いられる画素信号の読出しに用いられる信号線の増大を抑止しつつ、エッジ信号の生成に用いられる画素信号をカーネル単位で一括読出し可能となるという作用をもたらす。 In addition, in the first aspect, the pixels used to generate the edge signal may be selected so that their rows and columns are different from each other. This has the effect of preventing an increase in the number of signal lines used to read out the pixel signals used to generate the edge signal, while making it possible to read out the pixel signals used to generate the edge signal in bulk on a kernel basis.
　また、第１の側面において、前記階調信号は、前記カーネル単位で読み出された全ての画素の画素信号のビニング値に基づいて生成されてもよい。これにより、エッジ信号の生成および階調信号の生成に用いられるＡＤ変換部がカーネル単位で共用可能になるという作用をもたらす。 In addition, in the first aspect, the gradation signal may be generated based on the binning values of the pixel signals of all pixels read out on a kernel-by-kernel basis. This brings about the effect that the AD conversion unit used to generate the edge signal and the gradation signal can be shared on a kernel-by-kernel basis.
　また、第１の側面において、リセットレベルに基づくオートゼロ動作後に、信号レベルのＡＤ変換に基づいてエッジ信号を生成し、前記カーネル単位で読み出された全ての画素について、信号レベルのビニング値に基づくオートゼロ動作後に、リセットレベルのビニング値のＡＤ変換に基づいて諧調信号を生成してもよい。これにより、エッジ信号の生成に用いられる画素信号および階調信号の生成に用いられる画素信号が画素から非破壊で読み出されるという作用をもたらす。 In addition, in the first aspect, after an auto-zero operation based on the reset level, an edge signal may be generated based on AD conversion of the signal level, and for all pixels read out in units of kernels, after an auto-zero operation based on the binning value of the signal level, a gradation signal may be generated based on AD conversion of the binning value of the reset level. This provides the effect of non-destructively reading out the pixel signals used to generate the edge signal and the pixel signals used to generate the gradation signal from the pixels.
　また、第１の側面において、前記階調信号は、前記カーネル単位で読み出された画素のうち前記エッジ信号の生成に用いられた画素を含まない画素信号のビニング値に基づいて生成されてもよい。これにより、エッジ信号の生成および階調信号の生成に用いられるＡＤ変換部をカーネル単位で共用しつつ、階調信号の生成にＣＤＳ（Correlated Double Sampling）が可能となるという作用をもたらす。 In addition, in the first aspect, the gradation signal may be generated based on a binning value of pixel signals that do not include pixels used to generate the edge signal among the pixels read out on a kernel basis. This has the effect of enabling CDS (Correlated Double Sampling) to generate the gradation signal while sharing the AD conversion unit used to generate the edge signal and the gradation signal on a kernel basis.
　また、第１の側面において、リセットレベルに基づくオートゼロ動作後に、信号レベルのＡＤ変換に基づいてエッジ信号を生成し、前記カーネル単位で読み出された画素のうち前記エッジ信号の生成に用いられた画素を含まない画素について、リセットレベルのビニング値に基づくオートゼロ動作後に、信号レベルのビニング値のＡＤ変換に基づいて諧調信号を生成してもよい。これにより、エッジ信号の生成後、ＣＤＳに基づいて階調信号が生成されるという作用をもたらす。 In addition, in the first aspect, after an auto-zero operation based on a reset level, an edge signal may be generated based on AD conversion of a signal level, and for pixels read out in units of kernels that do not include the pixel used to generate the edge signal, a gradation signal may be generated based on AD conversion of a binning value of a signal level after an auto-zero operation based on a binning value of a reset level. This provides the effect of generating a gradation signal based on a CDS after the edge signal is generated.
　また、第１の側面において、前記カーネル単位のサイズは、前記エッジ信号の生成時と前記階調信号の生成時とで互いに等しくてもよい。これにより、同一のカーネル単位に基づいて、エッジ信号および階調信号が生成されるという作用をもたらす。 In addition, in the first aspect, the size of the kernel unit may be equal when the edge signal is generated and when the gradation signal is generated. This provides the effect that the edge signal and the gradation signal are generated based on the same kernel unit.
　また、第１の側面において、前記カーネル単位のサイズは、前記エッジ信号の生成時と前記階調信号の生成時とで互いに異なってもよい。これにより、互いに異なるカーネル単位に基づいて、エッジ信号および階調信号が生成されるという作用をもたらす。 In addition, in the first aspect, the size of the kernel unit may be different when the edge signal is generated and when the gradation signal is generated. This provides the effect that the edge signal and the gradation signal are generated based on kernel units that are different from each other.
　また、第１の側面において、前記信号処理部は、前記エッジ信号の生成と前記階調信号の生成とに用いられるＡＤ変換部を備え、前記読出回路は、前記エッジ信号の生成と前記階調信号の生成とで前記画素信号をカラム方向に伝送する信号線と前記ＡＤ変換部との接続を切り替えるマルチプレクサを備えてもよい。これにより、エッジ信号の生成および階調信号の生成に用いられるＡＤ変換部がカーネル単位で共用可能になるという作用をもたらす。 In addition, in the first aspect, the signal processing unit may include an AD conversion unit used to generate the edge signal and the gradation signal, and the readout circuit may include a multiplexer that switches the connection between the AD conversion unit and a signal line that transmits the pixel signal in the column direction for generating the edge signal and the gradation signal. This brings about the effect that the AD conversion unit used to generate the edge signal and the gradation signal can be shared on a kernel basis.
　また、第１の側面において、前記ＡＤ変換部は、フラッシュＡＤ変換器およびシングルスロープＡＤ変換器の少なくともいずれか１つを備えてもよい。これにより、レベル信号またはランプ信号との比較結果に基づいてＡＤ変換されるという作用をもたらす。 In addition, in the first aspect, the AD conversion unit may include at least one of a flash AD converter and a single-slope AD converter. This provides the effect of performing AD conversion based on the result of comparison with a level signal or a ramp signal.
　また、第１の側面において、前記ＡＤ変換部に入力される参照信号を生成する参照信号生成部をさらに備えてもよい。これにより、参照信号との比較結果に基づいて画素信号がＡＤ変換されるという作用をもたらす。 In addition, in the first aspect, a reference signal generating unit may be further provided that generates a reference signal to be input to the AD conversion unit. This provides the effect of AD-converting the pixel signal based on the comparison result with the reference signal.
　また、第１の側面において、前記参照信号生成部は、複数のレベル信号を生成する第１参照信号生成部と、ランプ信号を生成する第２参照信号生成部と、前記レベル信号の出力と前記ランプ信号の出力とを切り替える参照信号切替部とを備えてもよい。これにより、ＡＤ変換部を共用しつつ、低階調信号および高階調信号が生成されるという作用をもたらす。 In addition, in the first aspect, the reference signal generating unit may include a first reference signal generating unit that generates a plurality of level signals, a second reference signal generating unit that generates a ramp signal, and a reference signal switching unit that switches between the output of the level signal and the output of the ramp signal. This provides the effect of generating low gradation signals and high gradation signals while sharing the AD conversion unit.
　また、第１の側面において、前記ＡＤ変換部は、前記エッジ信号の生成と前記階調信号の生成とで共用されるコンパレータを備え、前記マルチプレクサは、前記エッジ信号の生成時には、２つの画素からの画素信号が前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替え、前記階調信号の生成時には、前記カーネル単位で読出された画素信号と、前記画素信号と比較される参照信号とが前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替えてもよい。これにより、コンパレータを共用しつつ、エッジ信号および階調信号が生成されるという作用をもたらす。 In addition, in the first aspect, the AD conversion unit may include a comparator shared between generating the edge signal and generating the gradation signal, and the multiplexer may switch the connection between the signal line and the AD conversion unit so that pixel signals from two pixels are input to the comparator when generating the edge signal, and may switch the connection between the signal line and the AD conversion unit so that the pixel signal read out on a kernel basis and a reference signal to be compared with the pixel signal are input to the comparator when generating the gradation signal. This provides the effect of generating edge signals and gradation signals while sharing a comparator.
　また、第１の側面において、前記ＡＤ変換部は、前記エッジ信号の生成と前記階調信号の生成とで共用されるとともに、画素単位の撮像信号の生成にも共用され、前記マルチプレクサは、前記エッジ信号の生成時には、２つの画素からの画素信号が前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替え、前記階調信号の生成時には、前記カーネル単位で読出された画素信号と、前記画素信号と比較される参照信号とが前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替え、前記撮像信号の生成時には、前記画素単位で読出された画素信号と、前記画素信号と比較される参照信号とが前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替えてもよい。これにより、コンパレータを共用しつつ、エッジ信号、低階調信号および高階調信号が生成されるという作用をもたらす。 In addition, in the first aspect, the AD conversion unit may be shared between generating the edge signal and generating the gradation signal, and also used to generate an image signal on a pixel-by-pixel basis, and the multiplexer may switch the connection between the signal line and the AD conversion unit so that pixel signals from two pixels are input to the comparator when generating the edge signal, switch the connection between the signal line and the AD conversion unit so that the pixel signal read out on a kernel-by-kernel basis and a reference signal to be compared with the pixel signal are input to the comparator when generating the gradation signal, and switch the connection between the signal line and the AD conversion unit so that the pixel signal read out on a pixel-by-pixel basis and a reference signal to be compared with the pixel signal are input to the comparator when generating the image signal. This provides the effect of generating edge signals, low gradation signals, and high gradation signals while sharing the comparator.
　また、第１の側面において、前記画素に蓄積された電荷の転送を制御する転送制御ドライバと、前記画素信号が読出される画素の選択を制御する選択制御ドライバと、前記画素に蓄積された電荷のリセットを制御するリセット制御ドライバと、前記画素に蓄積された電荷のビニングを制御するビニング制御ドライバとを備えてもよい。これにより、エッジ信号および階調信号の生成に用いられる画素信号の読出しが制御されるという作用をもたらす。 In addition, in the first aspect, a transfer control driver that controls the transfer of the charge accumulated in the pixel, a selection control driver that controls the selection of the pixel from which the pixel signal is read, a reset control driver that controls the resetting of the charge accumulated in the pixel, and a binning control driver that controls the binning of the charge accumulated in the pixel may be provided. This provides the effect of controlling the reading of the pixel signal used to generate the edge signal and the gradation signal.
　また、第１の側面において、前記画素は、前記画素のフローティングディフュージョンを他の画素のフローティングディフュージョンと接続するビニングトランジスタを備えてもよい。これにより、互いに異なる行および列のそれぞれについてビニングされた画素信号が生成されるという作用をもたらす。 In addition, in the first aspect, the pixel may include a binning transistor that connects the floating diffusion of the pixel to the floating diffusion of another pixel. This provides the effect of generating binned pixel signals for each of the different rows and columns.
　また、第１の側面において、前記画素信号をカラム方向に伝送する信号線を互いに異なるカラム間で接続する接続スイッチをさらに備えてもよい。これにより、互いに異なる列についてビニングされた画素信号が生成されるという作用をもたらす。 In addition, in the first aspect, a connection switch may be provided that connects the signal lines that transmit the pixel signals in the column direction between different columns. This provides the effect of generating binned pixel signals for different columns.
　また、第１の側面において、前記階調信号に基づいて露光制御を実施する露光制御部をさらに備えてもよい。これにより、エッジ信号の生成に用いられる画素信号のレベルが適正化されるという作用をもたらす。 In the first aspect, an exposure control unit may be further provided that performs exposure control based on the gradation signal. This provides the effect of optimizing the level of the pixel signal used to generate the edge signal.
第１の実施の形態に係る撮像装置が適用されるカメラの構成例を示すブロック図である。1 is a block diagram showing an example of the configuration of a camera to which an imaging device according to a first embodiment is applied; 第１の実施の形態に係る固体撮像装置の構成例を示すブロック図である。1 is a block diagram illustrating an example of a configuration of a solid-state imaging device according to a first embodiment. 第１の実施の形態に係る固体撮像装置に設けられた画素の構成例を示す回路図である。2 is a circuit diagram showing a configuration example of a pixel provided in the solid-state imaging device according to the first embodiment; 第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の構成例を示す断面図である。2 is a cross-sectional view showing a configuration example of a pixel array section provided in the solid-state imaging device according to the first embodiment; 第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の変形例を示す断面図である。10 is a cross-sectional view showing a modified example of a pixel array portion provided in the solid-state imaging device according to the first embodiment. FIG. 第１の実施の形態に係る固体撮像装置の読出し方法を示すブロック図である。3 is a block diagram showing a readout method of the solid-state imaging device according to the first embodiment; FIG. 第１の実施の形態に係る固体撮像装置によるエッジ画像の生成時の信号経路の切替例を示すブロック図である。4 is a block diagram showing an example of switching of signal paths when an edge image is generated by the solid-state imaging device according to the first embodiment; FIG. 第１の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。4 is a block diagram showing an example of switching of signal paths when a low gradation image is generated by the solid-state imaging device according to the first embodiment; FIG. 第１の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。5 is a timing chart showing an example of waveforms of various parts when an edge image and a low gradation image are generated by the solid-state imaging device according to the first embodiment. 第１の実施の形態に係る固体撮像装置による低階調画像の階調信号と参照信号との関係を示す図である。5A and 5B are diagrams illustrating a relationship between a gradation signal of a low gradation image and a reference signal by the solid-state imaging device according to the first embodiment. 第１の実施の形態に係る固体撮像装置による高階調画像の生成時の信号経路の切替例を示すブロック図である。4 is a block diagram showing an example of switching of signal paths when a high-gradation image is generated by the solid-state imaging device according to the first embodiment; FIG. 第１の実施の形態に係る固体撮像装置による高階調画像の生成時の各部の波形の一例を示すタイミングチャートである。5 is a timing chart showing an example of waveforms at various parts when a high-gradation image is generated by the solid-state imaging device according to the first embodiment. 第１の実施の形態に係る固体撮像装置による画像の生成例を示す図である。2A to 2C are diagrams illustrating an example of an image generated by the solid-state imaging device according to the first embodiment. 第１の実施の形態に係る固体撮像装置の画素アレイ部の構成例を示す回路図である。2 is a circuit diagram showing a configuration example of a pixel array section of a solid-state imaging device according to a first embodiment; 第１の実施の形態に係る信号読出し回路に適用されるコンパレータの構成例を示す図である。4 is a diagram illustrating an example of a configuration of a comparator applied to the signal readout circuit according to the first embodiment; FIG. 第１の実施の形態に係る固体撮像装置の露光制御方法の一例を示すフローチャートである。4 is a flowchart illustrating an example of an exposure control method for the solid-state imaging device according to the first embodiment. 第２の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。13 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to a second embodiment generates a low-tone image. FIG. 第２の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。10 is a timing chart showing an example of waveforms of various parts when an edge image and a low gradation image are generated by a solid-state imaging device according to a second embodiment. 第２の実施の形態に係る固体撮像装置のレベル信号生成部の一例を示す回路図である。13 is a circuit diagram illustrating an example of a level signal generating unit of a solid-state imaging device according to a second embodiment. 第３の実施の形態に係る固体撮像装置の読出し方法を示すブロック図である。FIG. 13 is a block diagram showing a readout method of a solid-state imaging device according to a third embodiment. 第３の実施の形態に係る固体撮像装置の画素アレイ部の構成例を示す回路図である。FIG. 13 is a circuit diagram showing a configuration example of a pixel array section of a solid-state imaging device according to a third embodiment. 第４の実施の形態に係る固体撮像装置の読出し方法を示すブロック図である。FIG. 13 is a block diagram showing a readout method of a solid-state imaging device according to a fourth embodiment. 第４の実施の形態に係る固体撮像装置の画素アレイ部の構成例を示す回路図である。FIG. 13 is a circuit diagram showing a configuration example of a pixel array section of a solid-state imaging device according to a fourth embodiment. 第５の実施の形態に係る固体撮像装置の読出し方法を示す図である。13A to 13C are diagrams illustrating a readout method of a solid-state imaging device according to a fifth embodiment. 第５の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。13 is a timing chart showing an example of waveforms of various parts when an edge image and a low gradation image are generated by a solid-state imaging device according to a fifth embodiment. 第６の実施の形態に係る固体撮像装置によるエッジ画像の生成時の信号経路の切替例を示すブロック図である。FIG. 23 is a block diagram showing an example of switching of signal paths when an edge image is generated by a solid-state imaging device according to a sixth embodiment. 第６の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。FIG. 23 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to a sixth embodiment generates a low-tone image. 第６の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。23 is a timing chart showing an example of waveforms of various parts when an edge image and a low gradation image are generated by a solid-state imaging device according to a sixth embodiment. 第６の実施の形態に係る固体撮像装置の画素アレイ部の構成例を示す回路図である。FIG. 13 is a circuit diagram showing a configuration example of a pixel array section of a solid-state imaging device according to a sixth embodiment. 第７の実施の形態に係る固体撮像装置による階調画像の生成時の信号経路の切替例を示すブロック図である。FIG. 23 is a block diagram showing an example of switching of signal paths when a gradation image is generated by a solid-state imaging device according to a seventh embodiment. 第７の実施の形態に係る固体撮像装置によるエッジ画像および階調画像の生成時の各部の波形の一例を示すタイミングチャートである。23 is a timing chart showing an example of waveforms of various parts when an edge image and a gradation image are generated by a solid-state imaging device according to a seventh embodiment. 第８の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。FIG. 23 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to an eighth embodiment generates a low-tone image. 第８の実施の形態に係る固体撮像装置のゲイン部の構成例を示す回路図である。FIG. 23 is a circuit diagram showing a configuration example of a gain section of a solid-state imaging device according to an eighth embodiment. 第９の実施の形態に係る固体撮像装置に設けられた画素の構成例を示す回路図である。FIG. 23 is a circuit diagram showing an example of the configuration of a pixel provided in a solid-state imaging device according to a ninth embodiment. 第９の実施の形態に係る固体撮像装置の画素アレイ部の構成例を示す回路図である。FIG. 23 is a circuit diagram showing a configuration example of a pixel array section of a solid-state imaging device according to a ninth embodiment. 第１０の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。FIG. 23 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to a tenth embodiment generates a low-tone image. 第１０の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。23 is a timing chart showing an example of waveforms of various parts when an edge image and a low gradation image are generated by a solid-state imaging device according to a tenth embodiment. 第１１の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。FIG. 23 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to an eleventh embodiment generates a low-tone image. 第１１の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。23 is a timing chart showing an example of waveforms at various parts when an edge image and a low gradation image are generated by a solid-state imaging device according to an eleventh embodiment. 第１２の実施の形態に係る固体撮像装置の構成例を示すブロック図である。FIG. 23 is a block diagram illustrating an example of the configuration of a solid-state imaging device according to a twelfth embodiment. 第１２の実施の形態に係る固体撮像装置によるエッジ画像の生成時の信号経路の切替例を示すブロック図である。FIG. 23 is a block diagram showing an example of switching of signal paths when an edge image is generated by a solid-state imaging device according to a twelfth embodiment. 第１２の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。FIG. 23 is a block diagram showing an example of switching of signal paths when a solid-state imaging device according to a twelfth embodiment generates a low-tone image. 第１３の実施の形態に係る固体撮像装置の構成例を示すブロック図である。FIG. 23 is a block diagram illustrating an example of the configuration of a solid-state imaging device according to a thirteenth embodiment. 第１４の実施の形態に係る撮像装置の構成例を示す斜視図である。FIG. 23 is a perspective view showing an example of the configuration of an imaging device according to a fourteenth embodiment. 車両制御システムの概略的な構成例を示すブロック図である。1 is a block diagram showing a schematic configuration example of a vehicle control system; 撮像部の設置位置の一例を示す説明図である。FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit.
　以下、本技術を実施するための形態（以下、実施の形態と称する）について説明する。説明は以下の順序により行う。
　１．第１の実施の形態（４×４画素のカーネル単位に基づいてエッジ画像および低階調画像を生成する例）
　２．第２の実施の形態（４×４画素のカーネル単位に基づいてエッジ画像および低階調画像を生成するとともに、低階調画像の階調を拡大した例）
　３．第３の実施の形態（２×２画素のカーネル単位に基づいてエッジ画像および低階調画像を生成する例）
　４．第４の実施の形態（３×３画素のカーネル単位に基づいてエッジ画像および低階調画像を生成する例）
　５．第５の実施の形態（エッジ画像の生成時のカーネル単位と低階調画像の生成時のカーネル単位とが互いに異なる例）
　６．第６の実施の形態（４×４画素のカーネル単位においてエッジ画像の生成に用いた画素を低階調画像の生成時に使用しない例）
　７．第７の実施の形態（画素信号とランプ信号との比較結果に基づいて階調画像を生成する例）
　８．第８の実施の形態（レベル信号のゲイン制御に基づいて低階調画像を生成する例）
　９．第９の実施の形態（画素トランジスタが複数の画素で共有される時のカーネル単位に基づいてエッジ画像および低階調画像を生成する例）
　１０．第１０の実施の形態（ビニング時に互いに異なるカラム間で垂直信号線を接続する例）
　１１．第１１の実施の形態（ビニング時にカラムごとに画素信号をサンプルホールドする例）
　１２．第１２の実施の形態（エッジ画像の生成と低階調画像の生成とでＡＤ変換部を分けた例）
　１３．第１３の実施の形態（エッジ画像の生成と低階調画像の生成とでＡＤ変換部を分けた上で、低階調画像の生成に用いられるＡＤ変換部を逐次比較型ＡＤ変換部とした例）
　１４．第１４の実施の形態（固体撮像装置が形成される基板を積層化した例）
　１５．移動体への応用例 Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described in the following order.
1. First embodiment (an example of generating an edge image and a low-tone image based on a kernel unit of 4×4 pixels)
2. Second embodiment (an example in which an edge image and a low-tone image are generated based on a kernel unit of 4×4 pixels, and the gradation of the low-tone image is expanded)
3. Third embodiment (an example of generating an edge image and a low-tone image based on a kernel unit of 2×2 pixels)
4. Fourth embodiment (an example of generating an edge image and a low-tone image based on a kernel unit of 3×3 pixels)
5. Fifth embodiment (an example in which the kernel unit when generating an edge image and the kernel unit when generating a low gradation image are different from each other)
6. Sixth embodiment (an example in which pixels used in generating an edge image in a 4×4 pixel kernel unit are not used in generating a low gradation image)
7. Seventh embodiment (example of generating a grayscale image based on a comparison result between a pixel signal and a ramp signal)
8. Eighth embodiment (an example of generating a low-gradation image based on gain control of a level signal)
9. Ninth embodiment (an example of generating an edge image and a low-tone image based on a kernel unit when a pixel transistor is shared by multiple pixels)
10. Tenth embodiment (example of connecting vertical signal lines between different columns during binning)
11. Eleventh embodiment (example of sampling and holding pixel signals for each column during binning)
12. Twelfth embodiment (example in which AD conversion units are separated for generating edge images and generating low gradation images)
13. Thirteenth embodiment (an example in which the AD conversion unit is divided into an edge image generation unit and a low gradation image generation unit, and the AD conversion unit used for generating the low gradation image is a successive approximation type AD conversion unit)
14. Fourteenth embodiment (an example in which substrates on which solid-state imaging devices are formed are stacked)
15. Examples of applications to moving objects
　＜１．第１の実施の形態＞
　図１は、第１の実施の形態に係る撮像装置が適用されるカメラの構成例を示すブロック図である。 1. First embodiment
FIG. 1 is a block diagram showing an example of the configuration of a camera to which an imaging device according to a first embodiment is applied.
　同図において、カメラ１００は、光学系１０１、固体撮像装置１０２、撮像制御部１０３、画像処理部１０４、記憶部１０５、表示部１０６および操作部１０７を備える。撮像制御部１０３、画像処理部１０４、記憶部１０５、表示部１０６および操作部１０７は、バス１０８を介して互いに接続されている。なお、カメラ１００は、単体としても用いられてもよいし、スマートフォンなどの携帯端末に組み込まれてもよいし、認証装置や監視装置に組み込まれてもよい。 In the figure, the camera 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a memory unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the memory unit 105, the display unit 106, and the operation unit 107 are connected to each other via a bus 108. The camera 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, or may be incorporated into an authentication device or a monitoring device.
　光学系１０１は、被写体からの光を固体撮像装置１０２に入射させ、被写像を固体撮像装置１０２の受光面に結像させる。光学系１０１は、例えば、フォーカスレンズ、ズームレンズおよび絞りなどを備えることができる。光学系１０１は、広角レンズ、標準レンズおよび望遠レンズなどの複数のレンズを備えてもよい。 The optical system 101 allows light from a subject to be incident on the solid-state imaging device 102, and forms an image of the subject on the light receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.
　固体撮像装置１０２は、被写体からの光を画素ごとに電気信号に変換し、その電気信号をデジタル化して出力する。固体撮像装置１０２は、例えば、ＣＭＯＳ（Complementary Metal Oxide Semiconductor）イメージセンサでもよいし、ＣＣＤ(Charge Coupled Device)でもよい。 The solid-state imaging device 102 converts the light from the subject into an electrical signal for each pixel, and then digitizes and outputs the electrical signal. The solid-state imaging device 102 may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device).
　固体撮像装置１０２は、裏面照射型固体撮像装置でもよい。固体撮像装置１０２で受光される光は、可視光であってもよいし、近赤外光（ＮＩＲ：Near InfraRed）、短波赤外光（ＳＷＩＲ：Short Wavelength InfraRed）、紫外光またはＸ線などでもよい。 The solid-state imaging device 102 may be a back-illuminated solid-state imaging device. The light received by the solid-state imaging device 102 may be visible light, near infrared light (NIR: Near InfraRed), short wave infrared light (SWIR: Short Wavelength InfraRed), ultraviolet light, X-rays, or the like.
　撮像制御部１０３は、操作部１０７からの指令に基づいて固体撮像装置１０２による撮像を制御する。このとき、撮像制御部１０３は、固体撮像装置１０２の露光時間、露光量および撮像タイミングなどを制御することができる。 The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.
　画像処理部１０４は、固体撮像装置１０２からの出力に基づいて画像処理を実施する。画像処理は、例えば、ガンマ補正、ホワイトバランス処理、シャープネス処理、階調変換処理である。画像処理部１０４は、ソフトウェアに基づいて処理を実行するプロセッサを備えてもよい。 The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.
　記憶部１０５は、固体撮像装置１０２で撮像された撮像画像を記憶したり、固体撮像装置１０２の撮像パラメータなどを記憶したりする。また、記憶部１０５は、ソフトウェアに基づいてカメラ１００を動作させるプログラムを記憶することができる。記憶部１０５は、ＲＯＭ（Read Only Memory）、ＲＡＭ（Random Access Memory）およびメモリカードを含んでもよい。 The storage unit 105 stores images captured by the solid-state imaging device 102, and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store programs that operate the camera 100 based on software. The storage unit 105 may include a ROM (Read Only Memory), a RAM (Random Access Memory), and a memory card.
　表示部１０６は、撮像画像を表示したり、撮像操作をサポートする各種情報を表示したりする。表示部１０６は、液晶ディスプレイでもよいし、有機ＥＬ（Electro Luminescence）ディスプレイでもよい。 The display unit 106 displays captured images and various information that supports the imaging operation. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.
　操作部１０７は、カメラ１００を操作するユーザインターフェースを提供する。操作部１０７は、例えば、カメラ１００に設けられたボタン、ダイヤルおよびスイッチを含んでもよい。操作部１０７は、表示部１０６とともにタッチパネルで構成してもよい。 The operation unit 107 provides a user interface for operating the camera 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the camera 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.
　図２は、第１の実施の形態に係る固体撮像装置の構成例を示すブロック図である。 FIG. 2 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment.
　同図において、固体撮像装置１０２は、画素アレイ部１１１、垂直走査回路１１２、カラム読出し回路１１３、カラム信号処理部１１４、水平走査回路１１５および制御回路１１６を備える。 In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.
　画素アレイ部１１１は、複数の画素１２０を備える。画素１２０は、ロウ方向（水平方向とも言う）およびカラム方向（垂直方向とも言う）に沿ってマトリックス状に配列される。各画素１２０は、信号の読出し時にカラム読出し回路１１３との間でソースフォロワを構成することができる。各画素１２０は、ロウごとに水平駆動線１３１に接続され、カラムごとに垂直信号線１３２に接続される。水平駆動線１３１は、各画素１２０からの信号の読出し時に各画素１２０をロウごとに駆動する。垂直信号線１３２は、画素１２０からの読出された画素信号をカラムごとにカラム信号処理部１１４に伝送する。 The pixel array section 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). Each pixel 120 can form a source follower with the column readout circuit 113 when reading out a signal. Each pixel 120 is connected to a horizontal drive line 131 for each row, and to a vertical signal line 132 for each column. The horizontal drive line 131 drives each pixel 120 for each row when reading out a signal from each pixel 120. The vertical signal line 132 transmits the pixel signal read out from the pixel 120 to the column signal processing section 114 for each column.
　垂直走査回路１１２は、読出し対象となる画素１２０をカラム方向に走査する。垂直走査回路１１２は、垂直レジスタを用いて構成してもよい。垂直走査回路１１２は、転送制御ドライバ１４１、選択制御ドライバ１４２、リセット制御ドライバ１４３およびビニング制御ドライバ１４４を備える。 The vertical scanning circuit 112 scans the pixels 120 to be read in the column direction. The vertical scanning circuit 112 may be configured using vertical registers. The vertical scanning circuit 112 includes a transfer control driver 141, a selection control driver 142, a reset control driver 143, and a binning control driver 144.
　転送制御ドライバ１４１は、画素１２０に蓄積された電荷の転送を制御する。選択制御ドライバ１４２は、画素信号が読出される画素１２０の選択を制御する。リセット制御ドライバ１４３は、画素１２０に蓄積された電荷のリセットを制御する。ビニング制御ドライバ１４４は、画素１２０に蓄積された電荷のビニングを制御する。転送制御ドライバ１４１、選択制御ドライバ１４２、リセット制御ドライバ１４３およびビニング制御ドライバ１４４は、水平駆動線１３１を介して画素１２０を制御することができる。 The transfer control driver 141 controls the transfer of the charge accumulated in the pixel 120. The selection control driver 142 controls the selection of the pixel 120 from which the pixel signal is read out. The reset control driver 143 controls the reset of the charge accumulated in the pixel 120. The binning control driver 144 controls the binning of the charge accumulated in the pixel 120. The transfer control driver 141, the selection control driver 142, the reset control driver 143, and the binning control driver 144 can control the pixel 120 via the horizontal drive line 131.
　カラム読出し回路１１３は、畳み込み処理されるカーネル単位で各画素１２０から画素信号を読出すことができる。なお、畳み込み処理は、画素信号の差分処理であってもよいし、画素信号の重み付き差分処理であってもよいし、フィルタリング処理であってもよい。カーネル単位は、２×２画素単位であってもよいし、３×３画素単位であってもよいし、４×４画素単位であってもよいし、それ以外の画素単位であってもよい。 The column readout circuit 113 can read out pixel signals from each pixel 120 in units of kernels to be convolved. The convolution process may be a differential process of pixel signals, a weighted differential process of pixel signals, or a filtering process. The kernel unit may be a 2x2 pixel unit, a 3x3 pixel unit, a 4x4 pixel unit, or any other pixel unit.
　ここで、カラム読出し回路１１３は、各画素１２０からの信号の読出し時に、各画素１２０との間でソースフォロワを構成してもよい。このとき、カラム読出し回路１１３は、画素１２０に保持された電荷に基づいて垂直信号線１３２の電位を変化させることができる。カラム読出し回路１１３は、定電流読出しにも対応してもよいし、容量負荷読出しに対応してもよい。 Here, the column readout circuit 113 may form a source follower with each pixel 120 when reading out a signal from each pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120. The column readout circuit 113 may also support constant current readout or capacitive load readout.
　カラム信号処理部１１４は、各画素１２０からカラム方向に伝送された信号を処理する。例えば、カラム信号処理部１１４は、各画素１２０からカラム方向に伝送された信号に基づいて、相関二重サンプリング（ＣＤＳ：Correlated Double Sampling）処理を実施することができる。また、カラム信号処理部１１４は、各画素１２０からカラム方向に伝送された信号に基づいて、ＡＤ（Analog to Digital）変換処理を実施し、エッジ信号Ｇ１、低階調信号Ｇ２および高階調信号Ｇ３を出力することができる。エッジ信号Ｇ１は、ロウまたはカラムが異なる画素１２０から読出された画素信号に比較結果に基づいて生成することができる。低階調信号Ｇ２は、各画素１２０の画素信号のビニング値に基づいて生成することができる。高階調信号Ｇ３は、各画素１２０の画素信号の個別読出しに基づいて生成することができる。このとき、カラム信号処理部１１４は、エッジ信号Ｇ１の生成、低階調信号Ｇ２の生成および高階調信号Ｇ３の生成で共用されるＡＤ変換部１４５を備えてもよい。 The column signal processing unit 114 processes signals transmitted in the column direction from each pixel 120. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 120. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 120, and output an edge signal G1, a low gradation signal G2, and a high gradation signal G3. The edge signal G1 can be generated based on a comparison result of pixel signals read out from pixels 120 in different rows or columns. The low gradation signal G2 can be generated based on a binning value of the pixel signal of each pixel 120. The high gradation signal G3 can be generated based on individual reading of the pixel signal of each pixel 120. In this case, the column signal processing unit 114 may include an AD conversion unit 145 that is shared for generating the edge signal G1, the low gradation signal G2, and the high gradation signal G3.
　ここで、カラム信号処理部１１４は、カーネル単位で読出された一部の画素１２０の画素信号に基づいてエッジ信号Ｇ１の生成処理を実施することができる。また、カラム信号処理部１１４は、カーネル単位で読出された画素１２０のうちエッジ信号Ｇ１の生成に用いられない画素を少なくとも含んで読出された画素信号に基づいて低階調信号Ｇ２の生成処理を実施することができる。カーネル単位のサイズは、エッジ信号Ｇ１の生成時と低階調信号Ｇ２の生成時とで互いに等しくてもよいし、互いに異なってもよい。 Here, the column signal processing unit 114 can perform the generation process of the edge signal G1 based on the pixel signals of some of the pixels 120 read out in kernel units. Also, the column signal processing unit 114 can perform the generation process of the low gradation signal G2 based on pixel signals read out including at least the pixels not used to generate the edge signal G1 among the pixels 120 read out in kernel units. The size of the kernel unit may be the same when generating the edge signal G1 and when generating the low gradation signal G2, or may be different from each other.
　ここで、カラム信号処理部１１４は、同一フレーム内において、エッジ信号Ｇ１を生成した後、低階調信号Ｇ２を生成してもよい。また、カラム信号処理部１１４は、エッジ信号Ｇ１の生成に用いられる画素信号を画素１２０から非破壊で読出した後、低階調信号Ｇ２の生成に用いられる画素信号を画素１２０から非破壊で読出してもよい。エッジ信号Ｇ１の生成に用いられる画素１２０は、行および列がそれぞれ互い異なるように選択されてもよい。 Here, the column signal processing unit 114 may generate the edge signal G1 and then generate the low gradation signal G2 within the same frame. Also, the column signal processing unit 114 may non-destructively read out the pixel signal used to generate the edge signal G1 from the pixel 120, and then non-destructively read out the pixel signal used to generate the low gradation signal G2 from the pixel 120. The pixels 120 used to generate the edge signal G1 may be selected such that their rows and columns are different from each other.
　水平走査回路１１５は、読出し対象となる画素１２０をロウ方向に走査する。水平走査回路１１５は、水平レジスタを用いて構成してもよい。 The horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.
　制御回路１１６は、垂直走査回路１１２、カラム読出し回路１１３、カラム信号処理部１１４および水平走査回路１１５を制御する。例えば、制御回路１１６は、カラム方向の走査タイミング、ロウ方向の走査タイミング、カラム読出し回路１１３の動作タイミングおよびカラム信号処理部１１４の処理タイミングを制御することができる。また、制御回路１１６は、エッジ信号Ｇ１の生成タイミング、低階調信号Ｇ２の生成タイミングおよび高階調信号Ｇ３の生成タイミングを制御することができる。 The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. The control circuit 116 can also control the generation timing of the edge signal G1, the generation timing of the low gradation signal G2, and the generation timing of the high gradation signal G3.
　制御回路１１６は、参照信号生成部１５１および露光制御部１５２を備える。参照信号生成部１５１は、低階調信号Ｇ２の生成時に画素信号と比較されるレベル信号および高階調信号Ｇ３の生成時に画素信号と比較されるランプ信号を生成することができる。露光制御部１５２は、低階調信号Ｇ２に基づいて露光制御を実施することができる。 The control circuit 116 includes a reference signal generating unit 151 and an exposure control unit 152. The reference signal generating unit 151 can generate a level signal that is compared with the pixel signal when the low gradation signal G2 is generated, and a ramp signal that is compared with the pixel signal when the high gradation signal G3 is generated. The exposure control unit 152 can perform exposure control based on the low gradation signal G2.
　図３は、第１の実施の形態に係る固体撮像装置に設けられた画素の回路構成例を示すブロック図である。 FIG. 3 is a block diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to the first embodiment.
　同図において、画素１２０は、フォトダイオード１２１、転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４、選択トランジスタ１２５、ビニングトランジスタ１２７およびフローティングディフュージョン１２６を備える。転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４、選択トランジスタ１２５およびビニングトランジスタ１２７として、ＭＯＳ（Metal Oxide Semiconductor）トランジスタを用いることができる。 In the figure, pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, a binning transistor 127, and a floating diffusion 126. MOS (Metal Oxide Semiconductor) transistors can be used as the transfer transistor 122, the reset transistor 123, the amplification transistor 124, the selection transistor 125, and the binning transistor 127.
　増幅トランジスタ１２４と選択トランジスタ１２５は、直列に接続されている。フォトダイオード１２１のカソードは、転送トランジスタ１２２を介してフローティングディフュージョン１２６に接続されている。また、フローティングディフュージョン１２６は、リセットトランジスタ１２３を介して電源Ｖｄｄに接続されている。また、電源Ｖｄｄは、増幅トランジスタ１２４と選択トランジスタ１２５の直列回路を介して垂直信号線１３２に接続されている。増幅トランジスタ１２４のゲートはフローティングディフュージョン１２６に接続されている。ビニングトランジスタ１２７は、フローティングディフュージョン１２６とビニング線１３３との間に接続される。ビニング線１３３は、ビニングされる画素１２０同士を接続することができる。このとき、ビニング線１３３は、ロウ方向およびカラム方向に画素１２０同士を接続してもよい。 The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode 121 is connected to the floating diffusion 126 via the transfer transistor 122. The floating diffusion 126 is connected to the power supply Vdd via the reset transistor 123. The power supply Vdd is connected to the vertical signal line 132 via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion 126. The binning transistor 127 is connected between the floating diffusion 126 and the binning line 133. The binning line 133 can connect the pixels 120 to be binned together. In this case, the binning line 133 may connect the pixels 120 to each other in the row direction and the column direction.
　転送トランジスタ１２２のゲートには、転送制御ドライバ１４１から転送信号ＴＲＧが印加される。リセットトランジスタ１２３のゲートには、リセット制御ドライバ１４３からリセット信号ＲＳＴが印加される。選択トランジスタ１２５のゲートには、選択制御ドライバ１４２から選択信号ＳＥＬが印加される。ビニングトランジスタ１２７のゲートには、ビニング制御ドライバ１４４からビニング信号ＢＮＥが印加される。 A transfer signal TRG is applied to the gate of the transfer transistor 122 from the transfer control driver 141. A reset signal RST is applied to the gate of the reset transistor 123 from the reset control driver 143. A selection signal SEL is applied to the gate of the selection transistor 125 from the selection control driver 142. A binning signal BNE is applied to the gate of the binning transistor 127 from the binning control driver 144.
　転送トランジスタ１２２がオンすると、フォトダイオード１２１に蓄積された電荷がフローティングディフュージョン１２６に転送される。そして、選択トランジスタ１２５がオンすると、フローティングディフュージョン１２６の電位に応じて増幅トランジスタ１２４のソース電位が変化する。そして、増幅トランジスタ１２４のソース電位は、選択トランジスタ１２５を介して垂直信号線１３２に印加され、垂直信号線１３２を介して伝送される。また、リセットトランジスタ１２３がオンすると、フローティングディフュージョン１２６に蓄積された電荷が排出される。また、ビニングトランジスタ１２７がオンされると、ビニング線１３３を介して複数の画素１２０のフローティングディフュージョン１２６がカーネル単位で接続される。 When the transfer transistor 122 is turned on, the charge accumulated in the photodiode 121 is transferred to the floating diffusion 126. When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion 126. The source potential of the amplification transistor 124 is applied to the vertical signal line 132 via the selection transistor 125 and transmitted via the vertical signal line 132. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion 126 is discharged. When the binning transistor 127 is turned on, the floating diffusions 126 of multiple pixels 120 are connected in kernel units via the binning line 133.
　図４は、第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の構成例を示す断面図である。なお、図４では、表面照射型固体撮像装置の例を示す。また、図４では、３画素分の構成例を示した。 FIG. 4 is a cross-sectional view showing an example of the configuration of a pixel array section provided in a solid-state imaging device according to the first embodiment. Note that FIG. 4 shows an example of a front-illuminated solid-state imaging device. FIG. 4 also shows an example of the configuration for three pixels.
　同図において、半導体基板２３１には、画素１２０ごとにフォトダイオード２３２が形成されている。半導体基板２３１の材料は、Ｓｉでもよいし、ＩｎＧａＡｓでもよいし、ＩｎＰでもよい。 In the figure, a photodiode 232 is formed for each pixel 120 on a semiconductor substrate 231. The material of the semiconductor substrate 231 may be Si, InGaAs, or InP.
　半導体基板２３１上には、ゲート電極２１４および配線層２１０が形成される。ゲート電極２１４は、ゲート絶縁膜２１３を介して半導体基板２３１上に形成される。ゲート電極２１４の側壁には、サイドウォール２１５が形成される。ゲート電極２１４の材料は、例えば、不純物が導入された多結晶シリコンを用いることができる。ゲート絶縁膜２１３の材料は、例えば、シリコン酸化膜を用いることができる。サイドウォール２１５の材料は、例えば、シリコン酸化膜またはシリコン窒化膜を用いることができる。 A gate electrode 214 and a wiring layer 210 are formed on a semiconductor substrate 231. The gate electrode 214 is formed on the semiconductor substrate 231 via a gate insulating film 213. A sidewall 215 is formed on the sidewall of the gate electrode 214. The material of the gate electrode 214 may be, for example, polycrystalline silicon doped with impurities. The material of the gate insulating film 213 may be, for example, a silicon oxide film. The material of the sidewall 215 may be, for example, a silicon oxide film or a silicon nitride film.
　ゲート電極２１４は、画素トランジスタに用いることができる。画素トランジスタは、図３の転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４および選択トランジスタ１２５を含む。 The gate electrode 214 can be used for pixel transistors. The pixel transistors include the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 in FIG. 3.
　ゲート電極２１４上には、配線２１６が形成される。図４では、３層配線の例を示した。このとき、配線２１６には、光をフォトダイオード２３２に入射させる開口部ＯＰ１が設けられる。ゲート電極２１４および配線２１６は、絶縁層２１７を介して絶縁される。絶縁層２１７は、例えば、シリコン酸化膜を用いることができる。配線２１６の材料は、例えば、ＡｌまたはＣｕなどの金属を用いることができる。 A wiring 216 is formed on the gate electrode 214. FIG. 4 shows an example of a three-layer wiring. In this case, an opening OP1 is provided in the wiring 216 to allow light to enter the photodiode 232. The gate electrode 214 and the wiring 216 are insulated via an insulating layer 217. The insulating layer 217 may be, for example, a silicon oxide film. The material of the wiring 216 may be, for example, a metal such as Al or Cu.
　配線層２１０上には、画素１２０ごとにカラーフィルタ２１８が形成される。カラーフィルタ２１８上には、画素１２０ごとにマイクロレンズ２１９が形成されている。カラーフィルタ２１８およびマイクロレンズ２１９の材料は、例えば、アクリルまたはポリカーボネートなどの透明樹脂を用いることができる。カラーフィルタ２１８は、着色に顔料が添加されてもよい。カラーフィルタ２１８は、例えば、ベイヤ配列を構成してもよいし、クワッドベイヤ配列を構成してもよい。カラーフィルタ２１８は、ＲＧＢフィルタを含んでもよいし、補色フィルタを含んでもよいし、白色フィルタを含んでもよい。 A color filter 218 is formed on the wiring layer 210 for each pixel 120. A microlens 219 is formed on the color filter 218 for each pixel 120. The material of the color filter 218 and the microlens 219 may be a transparent resin such as acrylic or polycarbonate. A pigment may be added to the color filter 218 for coloring. The color filter 218 may form, for example, a Bayer array or a quad Bayer array. The color filter 218 may include an RGB filter, a complementary color filter, or a white filter.
　図５は、第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の変形例を示す断面図である。なお、図５では、裏面照射型固体撮像装置の例を示す。また、図５では、３画素分の構成例を示した。 FIG. 5 is a cross-sectional view showing a modified example of a pixel array section provided in a solid-state imaging device according to the first embodiment. Note that FIG. 5 shows an example of a back-illuminated solid-state imaging device. Also, FIG. 5 shows an example of a configuration for three pixels.
　同図において、半導体層２２１には、画素１２０ごとにフォトダイオード２２２が形成されている。半導体層２２１の材料は、Ｓｉでもよいし、ＩｎＧａＡｓでもよいし、ＩｎＰでもよい。半導体層２２１は、例えば、フォトダイオード２２２が表面側に形成された半導体基板を裏面側から薄膜化して形成することができる。 In the figure, a photodiode 222 is formed in the semiconductor layer 221 for each pixel 120. The material of the semiconductor layer 221 may be Si, InGaAs, or InP. The semiconductor layer 221 can be formed, for example, by thinning a semiconductor substrate, on the front side of which the photodiode 222 is formed, from the back side.
　半導体層２２１上には、ゲート電極２２４および配線層２２０が形成される。ゲート電極２２４は、ゲート絶縁膜２２３を介して半導体層２２１上に形成される。ゲート電極２２４の側壁には、サイドウォール２２５が形成される。 A gate electrode 224 and a wiring layer 220 are formed on the semiconductor layer 221. The gate electrode 224 is formed on the semiconductor layer 221 via a gate insulating film 223. A sidewall 225 is formed on the side wall of the gate electrode 224.
　ゲート電極２２４は、画素トランジスタに用いることができる。画素トランジスタは、図３の転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４および選択トランジスタ１２５を含む。 The gate electrode 224 can be used for pixel transistors. The pixel transistors include the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 in FIG. 3.
　ゲート電極２２４上には、配線２２６が形成される。図５では、３層配線の例を示した。ゲート電極２２４および配線２２６は、絶縁層２２７を介して絶縁される。半導体層２２１は、絶縁層２２７を介し、支持基板２３０上に支持される。支持基板２３０は、ガラス基板でもよいし、Ｓｉ基板でもよいし、サファイア基板でもよい。 Wiring 226 is formed on the gate electrode 224. FIG. 5 shows an example of three-layer wiring. The gate electrode 224 and wiring 226 are insulated via an insulating layer 227. The semiconductor layer 221 is supported on a support substrate 230 via the insulating layer 227. The support substrate 230 may be a glass substrate, a Si substrate, or a sapphire substrate.
　半導体層２２１の裏面側には、画素１２０ごとにカラーフィルタ２２８が形成される。カラーフィルタ２２８上には、画素１２０ごとにマイクロレンズ２２９が形成されている。カラーフィルタ２２８は、例えば、ベイヤ配列を構成してもよいし、クワッドベイヤ配列を構成してもよい。カラーフィルタ２２８は、ＲＧＢフィルタを含んでもよいし、補色フィルタを含んでもよいし、白色フィルタを含んでもよい。 A color filter 228 is formed for each pixel 120 on the back side of the semiconductor layer 221. A microlens 229 is formed for each pixel 120 on the color filter 228. The color filter 228 may, for example, configure a Bayer array or a quad Bayer array. The color filter 228 may include an RGB filter, a complementary color filter, or a white filter.
　図６は、第１の実施の形態に係る固体撮像装置の読出し方法を示すブロック図である。なお、同図におけるａは、エッジ信号の生成時にカーネル単位で画素１２０から画素信号を読出す時のコンパレータ入力の切替例を示す。同図におけるｂは、低階調信号の生成時にカーネル単位で画素１２０から画素信号を読出す時のコンパレータ入力の切替例を示す。 FIG. 6 is a block diagram showing a readout method of the solid-state imaging device according to the first embodiment. Note that in the figure, "a" shows an example of switching the comparator input when pixel signals are read out from the pixels 120 in units of kernels when generating edge signals. "b" in the figure shows an example of switching the comparator input when pixel signals are read out from the pixels 120 in units of kernels when generating low gradation signals.
　同図におけるａにおいて、カーネル単位は、４×４画素（ｎ（ｎは４の倍数）行目からｎ＋３行目およびｍ（ｍは４の倍数）行目からｍ＋３行目の画素）に設定される。このとき、各カーネル単位において、縦方向のエッジおよび横方向のエッジを検出するために、４個のコンパレータ１７１－１から１７１－４が設けられる。また、エッジ信号の生成時と低階調信号の生成時とで各コンパレータ１７１－１から１７１－４への入力を切り替えるために、マルチプレクサ１６１が設けられる。 In a in the figure, the kernel unit is set to 4x4 pixels (pixels from row n (n is a multiple of 4) to row n+3 and row m (m is a multiple of 4) to row m+3). In this case, four comparators 171-1 to 171-4 are provided in each kernel unit to detect vertical and horizontal edges. Also, a multiplexer 161 is provided to switch the input to each comparator 171-1 to 171-4 when generating an edge signal and when generating a low gradation signal.
　ここで、エッジ信号の生成には、カーネル単位に含まれる１６個の画素１２０のうち、４個の画素１２０－１から１２０－４が選択される。画素１２０－１から１２０－４は、行および列がそれぞれ互い異なるように選択することができる。画素１２０－１、１２０－２は、横方向のエッジの検出に用いることができ、画素１２０－３、１２０－４は、縦方向のエッジの検出に用いることができる。このとき、マルチプレクサ１６１は、各画素１２０－１、１２０－２から読出された画素信号がコンパレータ１７１－１、１７１－２の両方に入力されるようにコンパレータ入力を切り替えることができる。また、マルチプレクサ１６１は、各画素１２０－３、１２０－４から読出された画素信号がコンパレータ１７１－３、１７１－４の両方に入力されるようにコンパレータ入力を切り替えることができる。ここで、各画素１２０－１、１２０－２から読出された画素信号は、コンパレータ１７１－１、１７１－２間で極性が逆になるように入力される。各画素１２０－３、１２０－４から読出された画素信号は、コンパレータ１７１－３、１７１－４間で極性が逆になるように入力される。 Here, to generate an edge signal, four pixels 120-1 to 120-4 are selected from the 16 pixels 120 included in the kernel unit. The pixels 120-1 to 120-4 can be selected so that the rows and columns are different from each other. The pixels 120-1 and 120-2 can be used to detect edges in the horizontal direction, and the pixels 120-3 and 120-4 can be used to detect edges in the vertical direction. At this time, the multiplexer 161 can switch the comparator input so that the pixel signals read out from each of the pixels 120-1 and 120-2 are input to both of the comparators 171-1 and 171-2. The multiplexer 161 can also switch the comparator input so that the pixel signals read out from each of the pixels 120-3 and 120-4 are input to both of the comparators 171-3 and 171-4. Here, the pixel signals read out from the pixels 120-1 and 120-2 are input to the comparators 171-1 and 171-2 so that their polarities are reversed. The pixel signals read out from the pixels 120-3 and 120-4 are input to the comparators 171-3 and 171-4 so that their polarities are reversed.
　一方、同図におけるｂにおいて、低階調信号の生成には、カーネル単位に含まれる１６個の画素１２０が選択される。このとき、マルチプレクサ１６１は、各画素１２０から読出された画素信号のビニング値がコンパレータ１７１－１から１７１－４に入力されるようにコンパレータ入力を切り替えることができる。また、各コンパレータ１７１－１から１７１－４には、レベル信号ＶＦ１からＶＦ４が入力される。レベル信号ＶＦ１からＶＦ４は、互いに異なる電圧レベルに設定することができる。このとき、コンパレータ１７１－１から１７１－４は、フラッシュＡＤ変換器として動作することができ、５階調の低階調信号を生成することができる。 On the other hand, in FIG. 3B, 16 pixels 120 included in the kernel unit are selected to generate a low gradation signal. At this time, the multiplexer 161 can switch the comparator input so that the binning values of the pixel signals read out from each pixel 120 are input to the comparators 171-1 to 171-4. Also, level signals VF1 to VF4 are input to each of the comparators 171-1 to 171-4. The level signals VF1 to VF4 can be set to different voltage levels. At this time, the comparators 171-1 to 171-4 can operate as flash AD converters and can generate a 5-gradation low gradation signal.
　図７は、第１の実施の形態に係る固体撮像装置によるエッジ画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 7 is a block diagram showing an example of switching of signal paths when an edge image is generated by a solid-state imaging device according to the first embodiment.
　同図において、各画素１２０は、増幅トランジスタ１２４、選択トランジスタ１２５、ビニングトランジスタ１２７および画素ブロック１２８を備える。各画素ブロック１２８は、フォトダイオード１２１、転送トランジスタ１２２、リセットトランジスタ１２３およびフローティングディフュージョン１２６を備える。 In the figure, each pixel 120 includes an amplification transistor 124, a selection transistor 125, a binning transistor 127, and a pixel block 128. Each pixel block 128 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, and a floating diffusion 126.
　画素アレイ部１１１は、垂直信号線１３２としてカラムごとに２本の垂直信号線１３２－１、１３２－２を備える。このとき、各カーネル単位において、ｎ＋３行目およびｎ＋１行目の画素１２０の選択トランジスタ１２５は垂直信号線１３２－２に接続され、ｎ＋２行目およびｎ行目の画素１２０の選択トランジスタ１２５は垂直信号線１３２－１に接続される。 The pixel array section 111 has two vertical signal lines 132-1 and 132-2 for each column as the vertical signal lines 132. At this time, in each kernel unit, the selection transistors 125 of the pixels 120 in the n+3th and n+1th rows are connected to the vertical signal line 132-2, and the selection transistors 125 of the pixels 120 in the n+2th and nth rows are connected to the vertical signal line 132-1.
　カラム読出し回路１１３は、マルチプレクサ１６１、電流源２５１－１から２５１－４、スイッチ２６１－１から２６１－４およびセレクタ２７１－１から２７１－４を備える。マルチプレクサ１６１は、スイッチ１６１－１から１６１－４を備える。 The column read circuit 113 includes a multiplexer 161, current sources 251-1 to 251-4, switches 261-1 to 261-4, and selectors 271-1 to 271-4. The multiplexer 161 includes switches 161-1 to 161-4.
　各電流源２５１－１から２５１－４は、各画素１２０からの画素信号の定電流読出しに用いることができる。このとき、各電流源２５１－１から２５１－４は、各画素１２０の増幅トランジスタ１２４とカラムごとにソースフォロワを構成し、各画素１２０に蓄積された電荷に応じて垂直信号線１３２－１、１３２－２を充電することができる。 Each current source 251-1 to 251-4 can be used for constant current readout of pixel signals from each pixel 120. At this time, each current source 251-1 to 251-4 forms a source follower for each column with the amplification transistor 124 of each pixel 120, and can charge the vertical signal lines 132-1 and 132-2 according to the charge accumulated in each pixel 120.
　マルチプレクサ１６１は、エッジ信号の生成と低階調信号の生成と高階調信号の生成とにおいて、各垂直信号線１３２－１、１３２－２と各コンパレータ１７１－１から１７１－４の入力との接続をカーネル単位で切り替える。このとき、マルチプレクサ１６１は、エッジ信号の生成時には、２つの画素からの画素信号が互いに異なる組み合わせで各コンパレータ１７１－１から１７１－４に入力されるように各垂直信号線１３２－１、１３２－２と各コンパレータ１７１－１から１７１－４の入力との接続を切り替えることができる。また、マルチプレクサ１６１は、低階調信号の生成時には、カーネル単位で読出された画素信号と、レベル信号ＶＦ１からＶＦ４とが各コンパレータ１７１－１から１７１－４に入力されるように各垂直信号線１３２－１、１３２－２と各コンパレータ１７１－１から１７１－４の入力との接続を切り替えることができる。また、マルチプレクサ１６１は、高階調信号の生成時には、画素単位で読出された画素信号と、ランプ信号ＲＡＰとが各コンパレータ１７１－１から１７１－４に入力されるように各垂直信号線１３２－１、１３２－２と各コンパレータ１７１－１から１７１－４の入力との接続を切り替えることができる。 The multiplexer 161 switches the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 on a kernel basis when generating an edge signal, a low gradation signal, or a high gradation signal. At this time, the multiplexer 161 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 so that pixel signals from two pixels are input to each of the comparators 171-1 to 171-4 in different combinations when generating an edge signal. In addition, the multiplexer 161 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 so that pixel signals read out on a kernel basis and level signals VF1 to VF4 are input to each of the comparators 171-1 to 171-4 when generating a low gradation signal. In addition, when generating a high-gradation signal, the multiplexer 161 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 so that the pixel signal read out on a pixel-by-pixel basis and the ramp signal RAP are input to each of the comparators 171-1 to 171-4.
　各スイッチ１６１－１から１６１－４は、カラムごとに設けられる。各スイッチ１６１－１から１６１－４の入力端子は、垂直信号線１３２－１、１３２－２ごとに設けられる。各スイッチ１６１－１から１６１－４の出力端子は、各コンパレータ１７１－１から１７１－４の反転入力端子に接続される。 Each switch 161-1 to 161-4 is provided for each column. The input terminals of each switch 161-1 to 161-4 are provided for each vertical signal line 132-1, 132-2. The output terminals of each switch 161-1 to 161-4 are connected to the inverting input terminals of each comparator 171-1 to 171-4.
　各スイッチ２６１－１から２６１－４は、カラムごとに設けられる。スイッチ２６１－１は、スイッチ１６１－１とセレクタ２７１－３との接続に用いられる。スイッチ２６１－２は、スイッチ１６１－２とセレクタ２７１－４との接続に用いられる。スイッチ２６１－３は、スイッチ１６１－３とセレクタ２７１－１との接続に用いられる。スイッチ２６１－４は、スイッチ１６１－４とセレクタ２７１－２との接続に用いられる。 Each switch 261-1 to 261-4 is provided for each column. Switch 261-1 is used to connect switch 161-1 to selector 271-3. Switch 261-2 is used to connect switch 161-2 to selector 271-4. Switch 261-3 is used to connect switch 161-3 to selector 271-1. Switch 261-4 is used to connect switch 161-4 to selector 271-2.
　セレクタ２７１－１から２７１－４は、カラムごとに設けられる。セレクタ２７１－１は、参照信号生成部１５１の出力およびスイッチ２６１－３を介して出力される画素信号のいずれかを選択してゲイン部２８１－１に入力する。セレクタ２７１－２は、参照信号生成部１５１の出力およびスイッチ２６１－４を介して出力される画素信号のいずれかを選択してゲイン部２８１－２に入力する。セレクタ２７１－３は、参照信号生成部１５１の出力およびスイッチ２６１－１を介して出力される画素信号のいずれかを選択してゲイン部２８１－３に入力する。セレクタ２７１－４は、参照信号生成部１５１の出力およびスイッチ２６１－２を介して出力される画素信号のいずれかを選択してゲイン部２８１－４に入力する。 Selectors 271-1 to 271-4 are provided for each column. Selector 271-1 selects either the output of reference signal generation unit 151 or the pixel signal output via switch 261-3 and inputs it to gain unit 281-1. Selector 271-2 selects either the output of reference signal generation unit 151 or the pixel signal output via switch 261-4 and inputs it to gain unit 281-2. Selector 271-3 selects either the output of reference signal generation unit 151 or the pixel signal output via switch 261-1 and inputs it to gain unit 281-3. Selector 271-4 selects either the output of reference signal generation unit 151 or the pixel signal output via switch 261-2 and inputs it to gain unit 281-4.
　カラム信号処理部１１４は、ゲイン部２８１－１から２８１－４、コンパレータ１７１－１から１７１－４、インバータ１８１－１から１８１－４およびＮＡＮＤ回路１９１－１から１９１－４を備える。 The column signal processing unit 114 includes gain units 281-1 to 281-4, comparators 171-1 to 171-4, inverters 181-1 to 181-4, and NAND circuits 191-1 to 191-4.
　ゲイン部２８１－１から２８１－４は、コンパレータ１７１－１から１７１－４ごとに設けられる。ゲイン部２８１－１は、セレクタ２７１－１の出力にゲインＧをかけてコンパレータ１７１－１の非反転入力端子に出力する。ゲイン部２８１－２は、セレクタ２７１－２の出力にゲインＧをかけてコンパレータ１７１－２の非反転入力端子に出力する。ゲイン部２８１－３は、セレクタ２７１－３の出力にゲインＧをかけてコンパレータ１７１－３の非反転入力端子に出力する。ゲイン部２８１－４は、セレクタ２７１－４の出力にゲインＧをかけてコンパレータ１７１－４の非反転入力端子に出力する。 Gain units 281-1 to 281-4 are provided for each of comparators 171-1 to 171-4. Gain unit 281-1 multiplies the output of selector 271-1 with gain G and outputs the result to the non-inverting input terminal of comparator 171-1. Gain unit 281-2 multiplies the output of selector 271-2 with gain G and outputs the result to the non-inverting input terminal of comparator 171-2. Gain unit 281-3 multiplies the output of selector 271-3 with gain G and outputs the result to the non-inverting input terminal of comparator 171-3. Gain unit 281-4 multiplies the output of selector 271-4 with gain G and outputs the result to the non-inverting input terminal of comparator 171-4.
　コンパレータ１７１－１から１７１－４は、カラムごとに設けられる。コンパレータ１７１－１は、ゲイン部２８１－１の出力とスイッチ１６１－１を介して出力される画素信号とを比較する。コンパレータ１７１－２は、ゲイン部２８１－２の出力とスイッチ１６１－２を介して出力される画素信号とを比較する。コンパレータ１７１－３は、ゲイン部２８１－３の出力とスイッチ１６１－３を介して出力される画素信号とを比較する。コンパレータ１７１－４は、ゲイン部２８１－４の出力とスイッチ１６１－４を介して出力される画素信号とを比較する。 Comparators 171-1 to 171-4 are provided for each column. Comparator 171-1 compares the output of gain unit 281-1 with the pixel signal output via switch 161-1. Comparator 171-2 compares the output of gain unit 281-2 with the pixel signal output via switch 161-2. Comparator 171-3 compares the output of gain unit 281-3 with the pixel signal output via switch 161-3. Comparator 171-4 compares the output of gain unit 281-4 with the pixel signal output via switch 161-4.
　また、各コンパレータ１７１－１から１７１－４には、オートゼロ信号ＡＺが入力される。オートゼロ信号ＡＺは、オートゼロ期間にオートゼロ動作をアクティブ化する。このとき、各コンパレータ１７１－１から１７１－４において、非反転入力端子には、ＤＣカットコンデンサ２９１が接続され、反転入力端子には、ＤＣカットコンデンサ２９２が接続される。そして、オートゼロ動作では、各コンパレータ１７１－１から１７１－４の非反転入力および反転入力がバランスするように各ＤＣカットコンデンサ２９１、２９２に蓄積される電荷が制御される。 In addition, an auto-zero signal AZ is input to each of the comparators 171-1 to 171-4. The auto-zero signal AZ activates the auto-zero operation during the auto-zero period. At this time, in each of the comparators 171-1 to 171-4, a DC cut capacitor 291 is connected to the non-inverting input terminal, and a DC cut capacitor 292 is connected to the inverting input terminal. In the auto-zero operation, the charge stored in each of the DC cut capacitors 291, 292 is controlled so that the non-inverting input and the inverting input of each of the comparators 171-1 to 171-4 are balanced.
　インバータ１８１－１は、コンパレータ１７１－１の出力を反転してＮＡＮＤ回路１９１－１に入力する。インバータ１８１－２は、コンパレータ１７１－２の出力を反転してＮＡＮＤ回路１９１－２に入力する。インバータ１８１－３は、コンパレータ１７１－３の出力を反転してＮＡＮＤ回路１９１－３に入力する。インバータ１８１－４は、コンパレータ１７１－４の出力を反転してＮＡＮＤ回路１９１－４に入力する。 Inverter 181-1 inverts the output of comparator 171-1 and inputs it to NAND circuit 191-1. Inverter 181-2 inverts the output of comparator 171-2 and inputs it to NAND circuit 191-2. Inverter 181-3 inverts the output of comparator 171-3 and inputs it to NAND circuit 191-3. Inverter 181-4 inverts the output of comparator 171-4 and inputs it to NAND circuit 191-4.
　ＮＡＮＤ回路１９１－１は、インバータ１８１－１の出力と出力イネーブル信号ＶＯＥとの否定論理積を演算する。ＮＡＮＤ回路１９１－２は、インバータ１８１－２の出力と出力イネーブル信号ＶＯＥとの否定論理積を演算する。ＮＡＮＤ回路１９１－３は、インバータ１８１－３の出力と出力イネーブル信号ＶＯＥとの否定論理積を演算する。ＮＡＮＤ回路１９１－４は、インバータ１８１－４の出力と出力イネーブル信号ＶＯＥとの否定論理積を演算する。出力イネーブル信号ＶＯＥは、各コンパレータ１７１－１から１７１－４の出力を有効化する。 NAND circuit 191-1 calculates the NAND of the output of inverter 181-1 and the output enable signal VOE. NAND circuit 191-2 calculates the NAND of the output of inverter 181-2 and the output enable signal VOE. NAND circuit 191-3 calculates the NAND of the output of inverter 181-3 and the output enable signal VOE. NAND circuit 191-4 calculates the NAND of the output of inverter 181-4 and the output enable signal VOE. The output enable signal VOE enables the output of each of comparators 171-1 to 171-4.
　参照信号生成部１５１は、ランプ信号生成部１５３、レベル信号生成部１５４および参照信号切替部１５５を備える。 The reference signal generating unit 151 includes a ramp signal generating unit 153, a level signal generating unit 154, and a reference signal switching unit 155.
　ランプ信号生成部１５３は、ランプ信号ＲＡＰを生成する。レベル信号生成部１５４は、レベル信号ＶＦ１からＶＦ４を生成する。参照信号切替部１５５は、低階調信号の生成時には、レベル信号ＶＦ１をセレクタ２７１－１に入力し、レベル信号ＶＦ２をセレクタ２７１－２に入力し、レベル信号ＶＦ３をセレクタ２７１－３に入力し、レベル信号ＶＦ４をセレクタ２７１－４に入力する。参照信号切替部１５５は、高階調信号の生成時には、ランプ信号ＲＡＰを各セレクタ２７１－１から２７１－４に入力する。 The ramp signal generating unit 153 generates a ramp signal RAP. The level signal generating unit 154 generates level signals VF1 to VF4. When generating a low gradation signal, the reference signal switching unit 155 inputs the level signal VF1 to the selector 271-1, the level signal VF2 to the selector 271-2, the level signal VF3 to the selector 271-3, and the level signal VF4 to the selector 271-4. When generating a high gradation signal, the reference signal switching unit 155 inputs the ramp signal RAP to each of the selectors 271-1 to 271-4.
　ここで、固体撮像装置は、エッジ画像を生成するものとする。このとき、カーネル単位に含まれる１６個の画素１２０のうち４個の各画素１２０－１から１２０－４において、選択トランジスタ１２５がオンされ、ビニングトランジスタ１２７はオフされる。カーネル単位に含まれる４個の各画素１２０－１から１２０－４以外の１２個の画素１２０において、選択トランジスタ１２５およびビニングトランジスタ１２７はオフされる。 Here, the solid-state imaging device generates an edge image. At this time, in each of four pixels 120-1 to 120-4 out of the 16 pixels 120 included in the kernel unit, the selection transistor 125 is turned on and the binning transistor 127 is turned off. In the remaining 12 pixels 120 other than the four pixels 120-1 to 120-4 included in the kernel unit, the selection transistor 125 and the binning transistor 127 are turned off.
　また、画素１２０－１が接続された垂直信号線１３２－１は、スイッチ１６１－１を介してコンパレータ１７１－１に接続される。画素１２０－４が接続された垂直信号線１３２－１は、スイッチ１６１－２を介してコンパレータ１７１－２に接続される。画素１２０－３が接続された垂直信号線１３２－２は、スイッチ１６１－４を介してコンパレータ１７１－４に接続される。画素１２０－４が接続された垂直信号線１３２－２は、スイッチ１６１－３を介してコンパレータ１７１－３に接続される。 Also, the vertical signal line 132-1 to which pixel 120-1 is connected is connected to comparator 171-1 via switch 161-1. The vertical signal line 132-1 to which pixel 120-4 is connected is connected to comparator 171-2 via switch 161-2. The vertical signal line 132-2 to which pixel 120-3 is connected is connected to comparator 171-4 via switch 161-4. The vertical signal line 132-2 to which pixel 120-4 is connected is connected to comparator 171-3 via switch 161-3.
　さらに、画素１２０－１が接続された垂直信号線１３２－１は、スイッチ１６１－１、スイッチ２６１－１およびセレクタ２７１－３を介してゲイン部２８１－３に接続される。画素１２０－４が接続された垂直信号線１３２－１は、スイッチ１６１－２、スイッチ２６１－２およびセレクタ２７１－４を介してゲイン部２８１－３に接続される。画素１２０－３が接続された垂直信号線１３２－２は、スイッチ１６１－４、スイッチ２６１－４およびセレクタ２７１－２を介してゲイン部２８１－２に接続される。画素１２０－２が接続された垂直信号線１３２－２は、スイッチ１６１－３、スイッチ２６１－３およびセレクタ２７１－１を介してゲイン部２８１－１に接続される。 Furthermore, the vertical signal line 132-1 to which the pixel 120-1 is connected is connected to the gain section 281-3 via the switch 161-1, the switch 261-1, and the selector 271-3. The vertical signal line 132-1 to which the pixel 120-4 is connected is connected to the gain section 281-3 via the switch 161-2, the switch 261-2, and the selector 271-4. The vertical signal line 132-2 to which the pixel 120-3 is connected is connected to the gain section 281-2 via the switch 161-4, the switch 261-4, and the selector 271-2. The vertical signal line 132-2 to which the pixel 120-2 is connected is connected to the gain section 281-1 via the switch 161-3, the switch 261-3, and the selector 271-1.
　図８は、第１の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 8 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the first embodiment.
　同図において、固体撮像装置は、低階調画像を生成するものとする。このとき、カーネル単位に含まれる１６個の画素１２０において、選択トランジスタ１２５およびビニングトランジスタ１２７はオンされる。 In the figure, the solid-state imaging device generates a low-tone image. At this time, the selection transistors 125 and binning transistors 127 are turned on in the 16 pixels 120 included in the kernel unit.
　また、カーネル単位に含まれるｍ列目の画素１２０が接続された垂直信号線１３２－１、１３２－２は、スイッチ１６１－１を介してコンパレータ１７１－１に接続される。カーネル単位に含まれるｍ＋１列目の画素１２０が接続された垂直信号線１３２－１、１３２－２は、スイッチ１６１－２を介してコンパレータ１７１－２に接続される。カーネル単位に含まれるｍ＋２列目の画素１２０が接続された垂直信号線１３２－１、１３２－２は、スイッチ１６１－３を介してコンパレータ１７１－３に接続される。カーネル単位に含まれるｍ＋３列目の画素１２０が接続された垂直信号線１３２－１、１３２－２は、スイッチ１６１－４を介してコンパレータ１７１－４に接続される。このとき、スイッチ２６１－１から２６１－４はオフされる。 Also, the vertical signal lines 132-1 and 132-2 to which the pixels 120 in the mth column included in the kernel unit are connected are connected to the comparator 171-1 via the switch 161-1. The vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+1th column included in the kernel unit are connected are connected to the comparator 171-2 via the switch 161-2. The vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+2th column included in the kernel unit are connected are connected to the comparator 171-3 via the switch 161-3. The vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+3th column included in the kernel unit are connected are connected to the comparator 171-4 via the switch 161-4. At this time, the switches 261-1 to 261-4 are turned off.
　さらに、レベル信号生成部１５４で生成されたレベル信号ＶＦ１は、参照信号切替部１５５およびセレクタ２７１－１を介してゲイン部２８１－１に入力される。レベル信号生成部１５４で生成されたレベル信号ＶＦ２は、参照信号切替部１５５およびセレクタ２７１－２を介してゲイン部２８１－２に入力される。レベル信号生成部１５４で生成されたレベル信号ＶＦ３は、参照信号切替部１５５およびセレクタ２７１－３を介してゲイン部２８１－３に入力される。レベル信号生成部１５４で生成されたレベル信号ＶＦ４は、参照信号切替部１５５およびセレクタ２７１－４を介してゲイン部２８１－４に入力される。このとき、各ゲイン部２８１－１から２８１－４のゲインは１に設定される。 Furthermore, the level signal VF1 generated by the level signal generating unit 154 is input to the gain unit 281-1 via the reference signal switching unit 155 and the selector 271-1. The level signal VF2 generated by the level signal generating unit 154 is input to the gain unit 281-2 via the reference signal switching unit 155 and the selector 271-2. The level signal VF3 generated by the level signal generating unit 154 is input to the gain unit 281-3 via the reference signal switching unit 155 and the selector 271-3. The level signal VF4 generated by the level signal generating unit 154 is input to the gain unit 281-4 via the reference signal switching unit 155 and the selector 271-4. At this time, the gain of each of the gain units 281-1 to 281-4 is set to 1.
　図９は、第１の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。 FIG. 9 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by the solid-state imaging device according to the first embodiment.
　同図において、選択制御ドライバ１４２は、選択信号ＳＥＬとして選択信号ＳＥＬ１、ＳＥＬ２を生成する。各カーネル単位において、選択信号ＳＥＬ１は、ｍ列目およびｍ＋２列目の各画素１２０の選択トランジスタ１２５に印加され、選択信号ＳＥＬ２は、ｍ＋１列目およびｍ＋３列目の各画素１２０の選択トランジスタ１２５に印加される。 In the figure, the selection control driver 142 generates selection signals SEL1 and SEL2 as the selection signal SEL. In each kernel unit, the selection signal SEL1 is applied to the selection transistors 125 of each pixel 120 in the mth and m+2th columns, and the selection signal SEL2 is applied to the selection transistors 125 of each pixel 120 in the m+1th and m+3th columns.
　第１の実施の形態のエッジ画像および低階調画像の生成では、非破壊読出しに基づいて、エッジ信号が生成された後（Ｐ１１）、低階調信号が生成される（Ｐ１２）。エッジ信号の生成では、各画素１２０－１から１２０－４について、Ｐ相読出しが実施された後（Ｋ１１）、Ｄ相読出しが実施される（Ｋ１２）。このとき、リセットレベルに基づくオートゼロ動作後に、信号レベルのＡＤ変換に基づいてエッジ信号が生成される。低階調信号の生成では、各画素１２０について、Ｄ相読出しが実施された後（Ｋ１３）、Ｐ相読出しが実施される（Ｋ１４）。このとき、カーネル単位で読み出された全ての画素１２０について、信号レベルのビニング値に基づくオートゼロ動作後に、リセットレベルのビニング値のＡＤ変換に基づいて諧調信号が生成される。 In the generation of edge images and low gradation images in the first embodiment, an edge signal is generated based on non-destructive readout (P11), and then a low gradation signal is generated (P12). In the generation of edge signals, a P-phase readout is performed for each pixel 120-1 to 120-4 (K11), and then a D-phase readout is performed (K12). At this time, after an auto-zero operation based on the reset level, an edge signal is generated based on AD conversion of the signal level. In the generation of low gradation signals, a D-phase readout is performed for each pixel 120 (K13), and then a P-phase readout is performed (K14). At this time, for all pixels 120 read out in kernel units, an auto-zero operation based on the binning value of the signal level is performed, and then a gradation signal is generated based on AD conversion of the binning value of the reset level.
　エッジ信号の生成では、切替信号ＲＳＷがロウレベルに設定される。このとき、セレクタ２７１－１の入力はスイッチ２６１－３側に切り替えられ、セレクタ２７１－２の入力はスイッチ２６１－４側に切り替えられ、セレクタ２７１－３の入力はスイッチ２６１－１側に切り替えられ、セレクタ２７１－４の入力はスイッチ２６１－２側に切り替えられる。また、各スイッチ２６１－１から２６１－４はオンされる。さらに、スイッチ１６１－１は、画素１２０－１が接続された垂直信号線１３２－１に接続される。スイッチ１６１－２は、画素１２０－４が接続された垂直信号線１３２－１に接続される。スイッチ１６１－３は、画素１２０－３が接続された垂直信号線１３２－２に接続される。スイッチ１６１－４は、画素１２０－２が接続された垂直信号線１３２－２に接続される。 When generating an edge signal, the switching signal RSW is set to a low level. At this time, the input of the selector 271-1 is switched to the switch 261-3 side, the input of the selector 271-2 is switched to the switch 261-4 side, the input of the selector 271-3 is switched to the switch 261-1 side, and the input of the selector 271-4 is switched to the switch 261-2 side. In addition, each of the switches 261-1 to 261-4 is turned on. Furthermore, the switch 161-1 is connected to the vertical signal line 132-1 to which the pixel 120-1 is connected. The switch 161-2 is connected to the vertical signal line 132-1 to which the pixel 120-4 is connected. The switch 161-3 is connected to the vertical signal line 132-2 to which the pixel 120-3 is connected. The switch 161-4 is connected to the vertical signal line 132-2 to which the pixel 120-2 is connected.
　また、リセット信号ＲＳＴ[ｎ＋３]－[ｎ]が立ち上がり（ｔ１１）、カーネル単位に含まれる画素１２０のリセットトランジスタ１２３がオンしてフローティングディフュージョン１２６がリセットされる。 In addition, the reset signal RST[n+3]-[n] rises (t11), turning on the reset transistor 123 of the pixel 120 included in the kernel unit and resetting the floating diffusion 126.
　また、オートゼロ信号ＡＺが立ち上がり（ｔ１１）、各コンパレータ１７１－１から１７１－４のオートゼロ動作がアクティブ化される。このとき、各コンパレータ１７１－１から１７１－４の非反転入力および反転入力がバランスするように、ＤＣカットコンデンサ２９１、２９２に蓄積される電荷が制御される。 Also, the auto-zero signal AZ rises (t11), activating the auto-zero operation of each of the comparators 171-1 to 171-4. At this time, the charge stored in the DC- cut capacitors 291 and 292 is controlled so that the non-inverting input and the inverting input of each of the comparators 171-1 to 171-4 are balanced.
　また、選択信号ＳＥＬ１[ｎ＋２]、[ｎ＋３]およびＳＥＬ２[ｎ]、[ｎ＋１]が立ち上がる（ｔ１１）。このとき、ｍ列目およびｍ＋２列目では、ｎ＋２行目およびｎ＋３行目の画素１２０の選択トランジスタ１２５がオンし、ｍ＋１列目およびｍ＋３列目では、ｎ行目およびｎ＋１行目の画素１２０の選択トランジスタ１２５がオンする。これにより、同一カラムの画素１２０は、選択トランジスタ１２５を介して互いに異なる垂直信号線１３２－１、１３２－２に接続され、同一カラムの画素１２０から読み出された画素信号の衝突が防止される。 Furthermore, the selection signals SEL1[n+2], [n+3] and SEL2[n], [n+1] rise (t11). At this time, in the mth and m+2th columns, the selection transistors 125 of the pixels 120 in the n+2th and n+3th rows are turned on, and in the m+1th and m+3th columns, the selection transistors 125 of the pixels 120 in the nth and n+1th rows are turned on. As a result, the pixels 120 in the same column are connected to different vertical signal lines 132-1, 132-2 via the selection transistors 125, preventing collision of pixel signals read out from the pixels 120 in the same column.
　このとき、画素１２０－１の増幅トランジスタ１２４のゲートに電源電位Ｖｄｄが印加された時のソースフォロワ動作に基づいて、画素１２０－１が接続された垂直信号線１３２－１の電位ＶＬｃ１が設定され、コンパレータ１７１－１に入力される。また、画素１２０－４の増幅トランジスタ１２４のゲートに電源電位Ｖｄｄが印加された時のソースフォロワ動作に基づいて、画素１２０－４が接続された垂直信号線１３２－１の電位ＶＬｃ２が設定され、コンパレータ１７１－２に入力される。また、画素１２０－３の増幅トランジスタ１２４のゲートに電源電位Ｖｄｄが印加された時のソースフォロワ動作に基づいて、画素１２０－３が接続された垂直信号線１３２－２の電位ＶＬｃ３が設定され、コンパレータ１７１－４に入力される。また、画素１２０－２の増幅トランジスタ１２４のゲートに電源電位Ｖｄｄが印加された時のソースフォロワ動作に基づいて、画素１２０－２が接続された垂直信号線１３２－２の電位ＶＬｃ４が設定され、コンパレータ１７１－３に入力される。なお、ＶＬｃ＊は、ＶＬｃ１からＶＬｃ４を示す。 At this time, based on the source follower operation when the power supply potential Vdd is applied to the gate of the amplification transistor 124 of the pixel 120-1, the potential VLc1 of the vertical signal line 132-1 to which the pixel 120-1 is connected is set and input to the comparator 171-1. Also, based on the source follower operation when the power supply potential Vdd is applied to the gate of the amplification transistor 124 of the pixel 120-4, the potential VLc2 of the vertical signal line 132-1 to which the pixel 120-4 is connected is set and input to the comparator 171-2. Also, based on the source follower operation when the power supply potential Vdd is applied to the gate of the amplification transistor 124 of the pixel 120-3, the potential VLc3 of the vertical signal line 132-2 to which the pixel 120-3 is connected is set and input to the comparator 171-4. In addition, based on the source follower operation when the power supply potential Vdd is applied to the gate of the amplification transistor 124 of the pixel 120-2, the potential VLc4 of the vertical signal line 132-2 to which the pixel 120-2 is connected is set and input to the comparator 171-3. Note that VLc* indicates VLc1 to VLc4.
　次に、リセット信号ＲＳＴ[ｎ＋３]－[ｎ]が立ち下がり（ｔ１２）、カーネル単位に含まれる画素１２０のリセットトランジスタ１２３がオフする。 Next, the reset signal RST[n+3]-[n] falls (t12), and the reset transistor 123 of the pixel 120 included in the kernel unit is turned off.
　このとき、画素１２０－１のフローティングディフュージョン１２６のリセットレベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－１が接続された垂直信号線１３２－１の電位ＶＬｃ１が設定される。また、画素１２０－４のフローティングディフュージョン１２６のリセットレベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－４が接続された垂直信号線１３２－１の電位ＶＬｃ２が設定される。また、画素１２０－３のフローティングディフュージョン１２６のリセットレベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－３が接続された垂直信号線１３２－２の電位ＶＬｃ３が設定される。また、画素１２０－２のフローティングディフュージョン１２６のリセットレベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－２が接続された垂直信号線１３２－２の電位ＶＬｃ４が設定される。 At this time, the potential VLc1 of the vertical signal line 132-1 to which pixel 120-1 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-1 is applied to the gate of the amplification transistor 124. Also, the potential VLc2 of the vertical signal line 132-1 to which pixel 120-4 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-4 is applied to the gate of the amplification transistor 124. Also, the potential VLc3 of the vertical signal line 132-2 to which pixel 120-3 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-3 is applied to the gate of the amplification transistor 124. In addition, the potential VLc4 of the vertical signal line 132-2 to which the pixel 120-2 is connected is set based on the source follower action when the reset level of the floating diffusion 126 of the pixel 120-2 is applied to the gate of the amplification transistor 124.
　次に、オートゼロ信号ＡＺが立ち下がった後（ｔ１３）、転送信号ＴＲＧ[ｎ＋３]－[ｎ]が立ち上がる（ｔ１４）。このとき、カーネル単位に含まれる画素１２０の転送トランジスタ１２２がオンしてフォトダイオード１２１に蓄積された電荷がフローティングディフュージョン１２６に転送される。 Next, after the auto-zero signal AZ falls (t13), the transfer signal TRG[n+3]-[n] rises (t14). At this time, the transfer transistor 122 of the pixel 120 included in the kernel unit turns on, and the charge accumulated in the photodiode 121 is transferred to the floating diffusion 126.
　そして、画素１２０－１のフォトダイオード１２１のカソード電位が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－１が接続された垂直信号線１３２－１の電位ＶＬｃ１が設定される。また、画素１２０－４のフォトダイオード１２１のカソード電位が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－４が接続された垂直信号線１３２－１の電位ＶＬｃ２が設定される。また、画素１２０－３のフォトダイオード１２１のカソード電位が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－３が接続された垂直信号線１３２－２の電位ＶＬｃ３が設定される。また、画素１２０－２のフォトダイオード１２１のカソード電位が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－２が接続された垂直信号線１３２－２の電位ＶＬｃ４が設定される。 Then, the potential VLc1 of the vertical signal line 132-1 to which pixel 120-1 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-1 is applied to the gate of the amplification transistor 124. Also, the potential VLc2 of the vertical signal line 132-1 to which pixel 120-4 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-4 is applied to the gate of the amplification transistor 124. Also, the potential VLc3 of the vertical signal line 132-2 to which pixel 120-3 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-3 is applied to the gate of the amplification transistor 124. In addition, the potential VLc4 of the vertical signal line 132-2 to which the pixel 120-2 is connected is set based on the source follower action when the cathode potential of the photodiode 121 of the pixel 120-2 is applied to the gate of the amplification transistor 124.
　次に、転送信号ＴＲＧ[ｎ＋３]－[ｎ]が立ち下がり、カーネル単位に含まれる画素１２０の転送トランジスタ１２２がオフする。 Next, the transfer signal TRG[n+3]-[n] falls, and the transfer transistor 122 of the pixel 120 included in the kernel unit is turned off.
　このとき、画素１２０－１のフローティングディフュージョン１２６の信号レベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－１が接続された垂直信号線１３２－１の電位ＶＬｃ１が設定される。また、画素１２０－４のフローティングディフュージョン１２６の信号レベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－４が接続された垂直信号線１３２－１の電位ＶＬｃ２が設定される。また、画素１２０－３のフローティングディフュージョン１２６の信号レベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－３が接続された垂直信号線１３２－２の電位ＶＬｃ３が設定される。また、画素１２０－２のフローティングディフュージョン１２６の信号レベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－２が接続された垂直信号線１３２－２の電位ＶＬｃ４が設定される。 At this time, the potential VLc1 of the vertical signal line 132-1 to which pixel 120-1 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-1 is applied to the gate of the amplification transistor 124. Also, the potential VLc2 of the vertical signal line 132-1 to which pixel 120-4 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-4 is applied to the gate of the amplification transistor 124. Also, the potential VLc3 of the vertical signal line 132-2 to which pixel 120-3 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-3 is applied to the gate of the amplification transistor 124. In addition, the potential VLc4 of the vertical signal line 132-2 to which the pixel 120-2 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of the pixel 120-2 is applied to the gate of the amplification transistor 124.
　そして、各コンパレータ１７１－１、１７１－２において、画素１２０－１が接続された垂直信号線１３２－１の電位ＶＬｃ１と、画素１２０－４が接続された垂直信号線１３２－１の電位ＶＬｃ２とが比較される。また、各コンパレータ１７１－３、１７１－４において、画素１２０－３が接続された垂直信号線１３２－２の電位ＶＬｃ３と、画素１２０－２が接続された垂直信号線１３２－２の電位ＶＬｃ４とが比較される。このとき、各コンパレータ１７１－１から１７１－４の非反転入力端子にそれぞれ入力される電位ＶＬｃ１からＶＬｃ４は、ゲインＧがかけられてもよい。そして、各コンパレータ１７１－１から１７１－４の出力は、インバータ１８１－１から１８１－４をそれぞれ介してＮＡＮＤ回路１９１－１から１９１－４に入力される。 Then, in each of the comparators 171-1 and 171-2, the potential VLc1 of the vertical signal line 132-1 to which the pixel 120-1 is connected is compared with the potential VLc2 of the vertical signal line 132-1 to which the pixel 120-4 is connected. Also, in each of the comparators 171-3 and 171-4, the potential VLc3 of the vertical signal line 132-2 to which the pixel 120-3 is connected is compared with the potential VLc4 of the vertical signal line 132-2 to which the pixel 120-2 is connected. At this time, the potentials VLc1 to VLc4 input to the non-inverting input terminals of the comparators 171-1 to 171-4 may be multiplied by a gain G. The outputs of the comparators 171-1 to 171-4 are then input to the NAND circuits 191-1 to 191-4 via the inverters 181-1 to 181-4, respectively.
　そして、出力イネーブル信号ＶＯＥが立ち上がる（ｔ１５）。このとき、各コンパレータ１７１－１から１７１－４の比較結果ＶＯ１からＶＯ４は、各インバータ１８１－１から１８１－４およびＮＡＮＤ回路１９１－１から１９１－４をそれぞれ介してエッジ信号として出力される。 Then, the output enable signal VOE rises (t15). At this time, the comparison results VO1 to VO4 of the comparators 171-1 to 171-4 are output as edge signals via the inverters 181-1 to 181-4 and the NAND circuits 191-1 to 191-4, respectively.
　低階調信号の生成では、切替信号ＲＳＷがハイレベルに設定される。このとき、セレクタ２７１－１の入力はレベル信号ＶＦ１に切り替えられ、セレクタ２７１－２の入力はレベル信号ＶＦ２に切り替えられ、セレクタ２７１－３の入力はレベル信号ＶＦ３に切り替えられ、セレクタ２７１－４の入力はレベル信号ＶＦ４に切り替えられる。また、各スイッチ２６１－１から２６１－４はオフされる。さらに、スイッチ１６１－１は、ｍ列目のカラムの各垂直信号線１３２－１、１３２－２に接続される。スイッチ１６１－２は、ｍ＋１列目のカラムの各垂直信号線１３２－１、１３２－２に接続される。スイッチ１６１－３は、ｍ＋２列目のカラムの各垂直信号線１３２－１、１３２－２に接続される。スイッチ１６１－４は、ｍ＋３列目のカラムの各垂直信号線１３２－１、１３２－２に接続される。 When generating a low gradation signal, the switching signal RSW is set to a high level. At this time, the input of the selector 271-1 is switched to the level signal VF1, the input of the selector 271-2 is switched to the level signal VF2, the input of the selector 271-3 is switched to the level signal VF3, and the input of the selector 271-4 is switched to the level signal VF4. In addition, each of the switches 261-1 to 261-4 is turned off. Furthermore, the switch 161-1 is connected to each of the vertical signal lines 132-1 and 132-2 of the mth column. The switch 161-2 is connected to each of the vertical signal lines 132-1 and 132-2 of the m+1th column. The switch 161-3 is connected to each of the vertical signal lines 132-1 and 132-2 of the m+2th column. The switch 161-4 is connected to each of the vertical signal lines 132-1 and 132-2 of the m+3th column.
　また、出力イネーブル信号ＶＯＥが立ち下がる（ｔ１６）。また、オートゼロ信号ＡＺが立ち上がり（ｔ１６）、各コンパレータ１７１－１から１７１－４のオートゼロ動作がアクティブ化される。また、ビニング信号ＢＮＥが立ち上がり、カーネル単位に含まれる１６個の画素１２０のビニングトランジスタ１２７がオンされる。また、選択信号ＳＥＬ１[ｎ＋２]、[ｎ＋３]およびＳＥＬ２[ｎ]、[ｎ＋１]が立ち上がったままの状態で、選択信号ＳＥＬ１[ｎ]、[ｎ＋１]およびＳＥＬ２[ｎ＋２]、[ｎ＋３]が立ち上がる（ｔ１６）。このとき、カーネル単位に含まれる１６個の画素１２０の選択トランジスタ１２５がオンされる。 The output enable signal VOE also falls (t16). The auto-zero signal AZ also rises (t16), activating the auto-zero operation of each of the comparators 171-1 to 171-4. The binning signal BNE also rises, turning on the binning transistors 127 of the 16 pixels 120 included in the kernel unit. With the selection signals SEL1[n+2], [n+3] and SEL2[n], [n+1] still rising, the selection signals SEL1[n], [n+1] and SEL2[n+2], [n+3] also rise (t16). At this time, the selection transistors 125 of the 16 pixels 120 included in the kernel unit are turned on.
　そして、カーネル単位に含まれる１６個の画素１２０の信号レベルのビニング値が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、カーネル単位のｍ列目からｍ＋３列目のカラムの垂直信号線１３２－１、１３２－２の電位ＶＬｃが設定される。ここで、カーネル単位のｍ列目からｍ＋３列目のカラムの垂直信号線１３２－１、１３２－２の電位ＶＬｃがＤＣカットコンデンサ２９２を介して各コンパレータ１７１－１から１７１－４の反転入力端子に印加されているときに各コンパレータ１７１－１から１７１－４の非反転入力および反転入力がバランスするように各ＤＣカットコンデンサ２９１、２９２に電荷が蓄積される。各コンパレータ１７１－１から１７１－４にそれぞれ接続されたＤＣカットコンデンサ２９１、２９２に蓄積される電荷は、カーネル単位に含まれる１６個の画素１２０の信号レベルのビニング値が反映される。 Then, the potential VLc of the vertical signal lines 132-1, 132-2 of the mth to m+3th columns of the kernel unit is set based on the source follower operation when the binning values of the signal levels of the 16 pixels 120 included in the kernel unit are applied to the gates of the amplification transistors 124. Here, when the potential VLc of the vertical signal lines 132-1, 132-2 of the mth to m+3th columns of the kernel unit is applied to the inverting input terminals of the comparators 171-1 to 171-4 via the DC cut capacitor 292, charges are accumulated in the DC cut capacitors 291, 292 so that the non-inverting input and the inverting input of each of the comparators 171-1 to 171-4 are balanced. The charges accumulated in the DC cut capacitors 291, 292 connected to each of the comparators 171-1 to 171-4 reflect the binning values of the signal levels of the 16 pixels 120 included in the kernel unit.
　次に、オートゼロ信号ＡＺが立ち下がり（ｔ１７）、各コンパレータ１７１－１から１７１－４のオートゼロ動作が非アクティブ化される。そして、リセット信号ＲＳＴ[ｎ＋３]－[ｎ]が立ち上がり、カーネル単位に含まれる画素１２０のリセットトランジスタ１２３がオンしてフローティングディフュージョン１２６がリセットされる。 Next, the auto-zero signal AZ falls (t17), deactivating the auto-zero operation of each of the comparators 171-1 to 171-4. Then, the reset signal RST[n+3]-[n] rises, turning on the reset transistor 123 of the pixel 120 included in the kernel unit and resetting the floating diffusion 126.
　次に、リセット信号ＲＳＴ[ｎ＋３]－[ｎ]が立ち下がり（ｔ１８）、カーネル単位に含まれる画素１２０のリセットトランジスタ１２３がオフする。このとき、カーネル単位に含まれる１６個の画素１２０のリセットレベルのビニング値が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、カーネル単位のｍ列目からｍ＋３列目のカラムの垂直信号線１３２－１、１３２－２の電位ＶＬｃが設定される。 Next, the reset signal RST[n+3]-[n] falls (t18), and the reset transistors 123 of the pixels 120 included in the kernel unit are turned off. At this time, the potential VLc of the vertical signal lines 132-1 and 132-2 of the mth to (m+3)th columns of the kernel unit is set based on the source follower operation when the binning values of the reset levels of the 16 pixels 120 included in the kernel unit are applied to the gates of the amplification transistors 124.
　そして、各コンパレータ１７１－１から１７１－４において、カーネル単位の信号レベルのビニング値が反映されるように各ＤＣカットコンデンサ２９１、２９２に電荷が蓄積された状態で、垂直信号線１３２－１、１３２－２の電位ＶＬｃとレベル信号ＶＦ１からＶＦ４とがそれぞれ比較される。そして、各コンパレータ１７１－１から１７１－４の出力は、インバータ１８１－１から１８１－４をそれぞれ介してＮＡＮＤ回路１９１－１から１９１－４に入力される。 Then, in each of the comparators 171-1 to 171-4, the potential VLc of the vertical signal lines 132-1 and 132-2 is compared with the level signals VF1 to VF4, respectively, with electric charge stored in each of the DC cut capacitors 291 and 292 so that the binning value of the signal level of each kernel is reflected. The outputs of the comparators 171-1 to 171-4 are input to the NAND circuits 191-1 to 191-4 via the inverters 181-1 to 181-4, respectively.
　そして、出力イネーブル信号ＶＯＥが立ち上がる（ｔ１９）。このとき、各コンパレータ１７１－１から１７１－４の比較結果ＶＯ１からＶＯ４は、各インバータ１８１－１から１８１－４およびＮＡＮＤ回路１９１－１から１９１－４をそれぞれ介して低階調信号として出力される。 Then, the output enable signal VOE rises (t19). At this time, the comparison results VO1 to VO4 of the comparators 171-1 to 171-4 are output as low-gradation signals via the inverters 181-1 to 181-4 and the NAND circuits 191-1 to 191-4, respectively.
　図１０は、第１の実施の形態に係る固体撮像装置による低階調画像の階調信号と参照信号との関係を示す図である。 FIG. 10 is a diagram showing the relationship between the gradation signal of a low-gradation image and the reference signal obtained by the solid-state imaging device according to the first embodiment.
　同図において、各コンパレータ１７１－１から１７１－４の参照信号として、４個のレベル信号ＶＦ１からＶＦ４を用いることにより、５階調分の低階調信号を得ることができる。 In the figure, five low-level gradation signals can be obtained by using four level signals VF1 to VF4 as reference signals for each comparator 171-1 to 171-4.
　図１１は、第１の実施の形態に係る固体撮像装置による高階調画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 11 is a block diagram showing an example of signal path switching when a high-gradation image is generated by a solid-state imaging device according to the first embodiment.
　同図において、固体撮像装置は、高階調画像を生成するものとする。高階調画像の階調は、例えば、８ビットから１４ビットに設定してもよい。高階調画像の生成では、カーネル単位に含まれる１６個の画素１２０において、各画素１２０から画素信号を個別に読出してもよい。このとき、選択トランジスタ１２５は行単位でオンされる。また、ビニングトランジスタ１２７はオフされる。例えば、カーネル単位に含まれるｎ行目の画素１２０－４から１２０－７からの読出しでは、それらの画素１２０－４から１２０－７の選択トランジスタ１２５がオンされる。また、カーネル単位に含まれるｎ＋１行目からｎ＋３行目の画素１２０の選択トランジスタ１２５はオフされる。 In the figure, the solid-state imaging device generates a high-tone image. The gradation of the high-tone image may be set to, for example, 8 bits to 14 bits. In generating the high-tone image, pixel signals may be read out individually from each of the 16 pixels 120 included in the kernel unit. At this time, the selection transistors 125 are turned on row by row. Also, the binning transistors 127 are turned off. For example, when reading out from the pixels 120-4 to 120-7 in the nth row included in the kernel unit, the selection transistors 125 of those pixels 120-4 to 120-7 are turned on. Also, the selection transistors 125 of the pixels 120 in the n+1th to n+3th rows included in the kernel unit are turned off.
　また、カーネル単位に含まれるｎ行目およびｎ＋２行目の画素１２０からの読出しでは、垂直信号線１３２－１は、各スイッチ１６１－１から１６１－４を介してコンパレータ１７１－１から１７１－４にそれぞれ接続される。カーネル単位に含まれるｎ＋１行目およびｎ＋３行目の画素１２０からの読出しでは、垂直信号線１３２－２は、各スイッチ１６１－１から１６１－４を介してコンパレータ１７１－１から１７１－４にそれぞれ接続される。このとき、スイッチ２６１－１から２６１－４はオフされる。 Furthermore, when reading out the pixels 120 in the nth and n+2th rows included in the kernel unit, the vertical signal line 132-1 is connected to the comparators 171-1 to 171-4 via the switches 161-1 to 161-4, respectively. When reading out the pixels 120 in the n+1th and n+3th rows included in the kernel unit, the vertical signal line 132-2 is connected to the comparators 171-1 to 171-4 via the switches 161-1 to 161-4, respectively. At this time, the switches 261-1 to 261-4 are turned off.
　さらに、ランプ信号生成部１５３で生成されたランプ信号ＲＡＰは、参照信号切替部１５５およびセレクタ２７１－１から２７１－４をそれぞれ介してゲイン部２８１－１から２８１－４に入力される。 Furthermore, the ramp signal RAP generated by the ramp signal generating unit 153 is input to the gain units 281-1 to 281-4 via the reference signal switching unit 155 and the selectors 271-1 to 271-4, respectively.
　図１２は、第１の実施の形態に係る固体撮像装置による高階調画像の生成時の各部の波形の一例を示すタイミングチャートである。 FIG. 12 is a timing chart showing an example of waveforms at various parts when a high-gradation image is generated by the solid-state imaging device according to the first embodiment.
　同図において、第１の実施の形態の高階調画像の生成では、Ｐ相ＡＤが実施された後（Ｋ２１）、Ｄ相ＡＤが実施される（Ｋ２２）。この高階調信号の生成では、ＣＤＳを実施することができる。 In the figure, in the generation of a high-gradation image in the first embodiment, P-phase AD is performed (K21), and then D-phase AD is performed (K22). In generating this high-gradation signal, CDS can be performed.
　高階調画像の生成では、切替信号ＲＳＷはハイレベルに設定される（ｔ２１）。このとき、各セレクタ２７１－１から２７１－４の入力はランプ信号ＲＡＰに切り替えられる。また、各スイッチ２６１－１から２６１－４はオフされる。さらに、ビニング信号ＢＮＥ[ｎ]はロウレベルに設定され（ｔ２１）、ビニングトランジスタ１２７はオフされる。 When generating a high-tone image, the switching signal RSW is set to a high level (t21). At this time, the input of each of the selectors 271-1 to 271-4 is switched to the ramp signal RAP. Also, each of the switches 261-1 to 261-4 is turned off. Furthermore, the binning signal BNE[n] is set to a low level (t21), and the binning transistor 127 is turned off.
　また、オートゼロ信号ＡＺが立ち上がり（ｔ２１）、各コンパレータ１７１－１から１７１－４のオートゼロ動作がアクティブ化される。また、リセット信号ＲＳＴ[ｎ]が立ち上がり、カーネル単位に含まれる画素１２０のリセットトランジスタ１２３がオンしてフローティングディフュージョン１２６がリセットされる。また、選択信号ＳＥＬ１[ｎ]およびＳＥＬ２[ｎ]が立ち上がる（ｔ２１）。このとき、カーネル単位に含まれるｎ行目の画素１２０の選択トランジスタ１２５がオンされる。 The auto-zero signal AZ also rises (t21), activating the auto-zero operation of each of the comparators 171-1 to 171-4. The reset signal RST[n] also rises, turning on the reset transistor 123 of the pixel 120 included in the kernel unit and resetting the floating diffusion 126. The selection signals SEL1[n] and SEL2[n] also rise (t21). At this time, the selection transistor 125 of the pixel 120 in the nth row included in the kernel unit is turned on.
　そして、リセット信号ＲＳＴ[ｎ]が立ち下がると（ｔ２２）、カーネル単位に含まれるｎ行目の各画素１２０のリセットトランジスタ１２３がオフする。このとき、ｎ行目の各画素１２０のフローティングディフュージョン１２６のリセットレベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、ｎ行目の画素１２０が接続された垂直信号線１３２－１または垂直信号線１３２－２の電位ＶＬｃが設定される。 Then, when the reset signal RST[n] falls (t22), the reset transistor 123 of each pixel 120 in the nth row included in the kernel unit is turned off. At this time, the potential VLc of the vertical signal line 132-1 or 132-2 to which the pixel 120 in the nth row is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of each pixel 120 in the nth row is applied to the gate of the amplification transistor 124.
　そして、オートゼロ信号ＡＺが立ち下がった後、出力イネーブル信号ＶＯＥが立ち上がるとともに、参照信号としてランプ信号ＲＡＰが各コンパレータ１７１－１から１７１－４に供給される（ｔ２３）。そして、各コンパレータ１７１－１から１７１－４において、リセットレベルに応じた垂直信号線１３２－１または垂直信号線１３２－２の電位ＶＬｃがランプ信号ＲＡＰと比較され、ランプ信号ＲＡＰのレベルが垂直信号線１３２－１または垂直信号線１３２－２の電位ＶＬｃと一致したときのタイミングが比較結果ＶＯ１からＶＯ４として出力される（ｔ２４）。このとき、ランプ信号ＲＡＰのレベルが垂直信号線１３２－１または垂直信号線１３２－２の電位ＶＬｃと一致するまでのカウント動作に基づいて、ｎ行目の画素１２０から読み出されたリセットレベルがＡＤ変換される。 After the auto-zero signal AZ falls, the output enable signal VOE rises and the ramp signal RAP is supplied as a reference signal to each of the comparators 171-1 to 171-4 (t23). Then, in each of the comparators 171-1 to 171-4, the potential VLc of the vertical signal line 132-1 or 132-2 corresponding to the reset level is compared with the ramp signal RAP, and the timing when the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132-1 or 132-2 is output as the comparison results VO1 to VO4 (t24). At this time, the reset level read out from the pixel 120 in the nth row is AD converted based on the counting operation until the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132-1 or 132-2.
　次に、出力イネーブル信号ＶＯＥが立ち下がった後、転送信号ＴＲＧ[ｎ]が立ち上がる（ｔ２５）。そして、カーネル単位に含まれるｎ行目の各画素１２０の転送トランジスタ１２２がオンしてフォトダイオード１２１に蓄積された電荷がフローティングディフュージョン１２６に転送される。このとき、ｎ行目の各画素１２０のフローティングディフュージョン１２６の信号レベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、ｎ行目の画素１２０が接続された垂直信号線１３２－１または垂直信号線１３２－２の電位ＶＬｃが設定される。 Next, after the output enable signal VOE falls, the transfer signal TRG[n] rises (t25). Then, the transfer transistor 122 of each pixel 120 in the nth row included in the kernel unit turns on, and the charge accumulated in the photodiode 121 is transferred to the floating diffusion 126. At this time, the potential VLc of the vertical signal line 132-1 or vertical signal line 132-2 to which the pixel 120 in the nth row is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of each pixel 120 in the nth row is applied to the gate of the amplification transistor 124.
　そして、出力イネーブル信号ＶＯＥが立ち上がるとともに、参照信号としてランプ信号ＲＡＰが各コンパレータ１７１－１から１７１－４に供給される（ｔ２６）。そして、各コンパレータ１７１－１から１７１－４において、信号レベルに応じた垂直信号線１３２－１または垂直信号線１３２－２の電位ＶＬｃがランプ信号ＲＡＰと比較され、ランプ信号ＲＡＰのレベルが垂直信号線１３２－１または垂直信号線１３２－２の電位ＶＬｃと一致したときのタイミングが比較結果ＶＯ１からＶＯ４として出力される（ｔ２７）。このとき、ランプ信号ＲＡＰのレベルが垂直信号線１３２－１または垂直信号線１３２－２の電位ＶＬｃと一致するまでのカウント動作に基づいて、ｎ行目の画素１２０から読み出された信号レベルがＡＤ変換される。 Then, as the output enable signal VOE rises, the ramp signal RAP is supplied to each of the comparators 171-1 to 171-4 as a reference signal (t26). Then, in each of the comparators 171-1 to 171-4, the potential VLc of the vertical signal line 132-1 or vertical signal line 132-2 corresponding to the signal level is compared with the ramp signal RAP, and the timing when the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132-1 or vertical signal line 132-2 is output as the comparison results VO1 to VO4 (t27). At this time, the signal level read out from the pixel 120 in the nth row is AD converted based on the counting operation until the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132-1 or vertical signal line 132-2.
　図１３は、第１の実施の形態に係る固体撮像装置による画像の生成例を示す図である。 FIG. 13 is a diagram showing an example of image generation by the solid-state imaging device according to the first embodiment.
　同図におけるａにおいて、高階調信号に基づいて撮像画像が生成される。高階調信号は、各画素１２０から個別に読み出された画素信号に基づいて生成することができる。 In FIG. 1A, a captured image is generated based on a high-tone signal. The high-tone signal can be generated based on pixel signals read out individually from each pixel 120.
　同図におけるｂにおいて、エッジ信号に基づいてエッジ画像が生成される。エッジ信号は、カーネル単位で画素１２０から読み出された画素信号の畳み込み処理に基づいて生成することができる。 In b of the same figure, an edge image is generated based on the edge signal. The edge signal can be generated based on a convolution process of pixel signals read out from pixels 120 on a kernel-by-kernel basis.
　同図におけるｃにおいて、低階調信号に基づいて低階調画像が生成される。低階調信号は、カーネル単位で画素１２０から読み出された画素信号のビニング値に基づいて生成することができる。 In c in the figure, a low-tone image is generated based on a low-tone signal. The low-tone signal can be generated based on the binning value of the pixel signal read out from the pixel 120 in kernel units.
　図１４は、第１の実施の形態に係る固体撮像装置の画素アレイ部の構成例を示す回路図である。 FIG. 14 is a circuit diagram showing an example of the configuration of a pixel array section of a solid-state imaging device according to the first embodiment.
　同図において、画素アレイ部１１１には、カーネル単位で４×４個の画素１２０が配置される。各カーネル単位において、エッジ信号の生成時に画素１２０から読み出された画素信号が衝突しないように画素１２０が接続される。 In the figure, 4 x 4 pixels 120 are arranged in kernel units in the pixel array section 111. In each kernel unit, the pixels 120 are connected so that the pixel signals read out from the pixels 120 do not collide when generating an edge signal.
　このとき、各カーネル単位において、ｎ＋３行目およびｎ＋１行目の画素１２０の選択トランジスタ１２５は垂直信号線１３２－２に接続され、ｎ＋２行目およびｎ行目の画素１２０の選択トランジスタ１２５は垂直信号線１３２－１に接続される。選択信号ＳＥＬ１は、ｍ列目およびｍ＋２列目の各画素１２０の選択トランジスタ１２５に印加され、選択信号ＳＥＬ２は、ｍ＋１列目およびｍ＋３列目の各画素１２０の選択トランジスタ１２５に印加される。 At this time, in each kernel unit, the selection transistors 125 of the pixels 120 in the n+3th and n+1th rows are connected to the vertical signal line 132-2, and the selection transistors 125 of the pixels 120 in the n+2th and nth rows are connected to the vertical signal line 132-1. The selection signal SEL1 is applied to the selection transistors 125 of each pixel 120 in the mth and m+2th columns, and the selection signal SEL2 is applied to the selection transistors 125 of each pixel 120 in the m+1th and m+3th columns.
　図１５は、第１の実施の形態に係る信号読出し回路に適用されるコンパレータの構成例を示す図である。なお、以下の説明では、図１７のコンパレータ１７１－１の構成を例にとるが、各コンパレータ１７１－２から１７１－４についても同様に構成することができる。 FIG. 15 is a diagram showing an example of the configuration of a comparator applied to the signal readout circuit according to the first embodiment. In the following explanation, the configuration of the comparator 171-1 in FIG. 17 is taken as an example, but each of the comparators 171-2 to 171-4 can be configured in the same way.
　同図において、コンパレータ１７１－１は、差動アンプ５０１および後段アンプ５０２を備える。コンパレータ１７１－１の後段には、インバータ１８１－１が接続される。後段アンプ５０２は、差動アンプ５０１の後段に接続され、インバータ１８１－１は、後段アンプ５０２の後段に接続される。 In the figure, the comparator 171-1 includes a differential amplifier 501 and a rear-stage amplifier 502. An inverter 181-1 is connected to the rear stage of the comparator 171-1. The rear-stage amplifier 502 is connected to the rear stage of the differential amplifier 501, and the inverter 181-1 is connected to the rear stage of the rear-stage amplifier 502.
　差動アンプ５０１は、オートゼロ動作に基づいてコンパレータ入力ＤＶＳＬ１およびＤＶＳＬ２をバランスさせた上で、コンパレータ入力ＤＶＳＬ１およびＤＶＳＬ２の差分に応じた電圧を出力する。差動アンプ５０１は、ＰＭＯＳトランジスタ５１１、５２１、５５１および５６１と、ＮＭＯＳトランジスタ５３１、５４１および５７１とを備える。 Differential amplifier 501 balances comparator inputs DVSL1 and DVSL2 based on the auto-zero operation, and outputs a voltage according to the difference between comparator inputs DVSL1 and DVSL2. Differential amplifier 501 includes PMOS transistors 511, 521, 551, and 561, and NMOS transistors 531, 541, and 571.
　ＰＭＯＳトランジスタ５１１とＮＭＯＳトランジスタ５３１とは互いに直列に接続されている。ＰＭＯＳトランジスタ５２１とＮＭＯＳトランジスタ５４１とは互いに直列に接続されている。各ＰＭＯＳトランジスタ５１１および５２１のソースは、電源電圧ＶＤＤＨに接続され、各ＰＭＯＳトランジスタ５１１および５２１のゲートは、ＰＭＯＳトランジスタ５２１のドレインに接続されている。このとき、ＰＭＯＳトランジスタ５１１および５２１は、カレントミラーを構成することができる。 PMOS transistor 511 and NMOS transistor 531 are connected in series to each other. PMOS transistor 521 and NMOS transistor 541 are connected in series to each other. The sources of each of PMOS transistors 511 and 521 are connected to power supply voltage VDDH, and the gates of each of PMOS transistors 511 and 521 are connected to the drain of PMOS transistor 521. At this time, PMOS transistors 511 and 521 can form a current mirror.
　ＮＭＯＳトランジスタ５３１のゲートとドレインとの間には、ＰＭＯＳトランジスタ５５１が接続され、ＮＭＯＳトランジスタ５４１のゲートとドレインとの間には、ＰＭＯＳトランジスタ５６１が接続されている。各ＮＭＯＳトランジスタ５３１および５４１のソースは、ＮＭＯＳトランジスタ５７１を介して接地されている。 A PMOS transistor 551 is connected between the gate and drain of the NMOS transistor 531, and a PMOS transistor 561 is connected between the gate and drain of the NMOS transistor 541. The sources of the NMOS transistors 531 and 541 are grounded via an NMOS transistor 571.
　各ＰＭＯＳトランジスタ５５１および５６１のゲートには、オートゼロ信号ＡＺＰが印加され、ＮＭＯＳトランジスタ５７１のゲートには、バイアス電圧ＢＩＡＳが印加される。ＮＭＯＳトランジスタ５７１は、バイアス電圧ＢＩＡＳに基づいて定電流源として動作することができる。 An auto-zero signal AZP is applied to the gate of each of the PMOS transistors 551 and 561, and a bias voltage BIAS is applied to the gate of the NMOS transistor 571. The NMOS transistor 571 can operate as a constant current source based on the bias voltage BIAS.
　後段アンプ５０２は、差動アンプ５０１の出力を増幅する。後段アンプ５０２は、ＰＭＯＳトランジスタ５１２、ＮＭＯＳトランジスタ５２２およびスイッチ５３２を備える。 The rear amplifier 502 amplifies the output of the differential amplifier 501. The rear amplifier 502 includes a PMOS transistor 512, an NMOS transistor 522, and a switch 532.
　ＰＭＯＳトランジスタ５１２とＮＭＯＳトランジスタ５２２とは互いに直列に接続されている。ＰＭＯＳトランジスタ５１２のソースは、電源電圧ＶＤＤＨに接続され、ＰＭＯＳトランジスタ５１２のゲートは、ＰＭＯＳトランジスタ５１１のドレインに接続されている。ＮＭＯＳトランジスタ５２２のゲートとドレインとの間には、スイッチ５３２が接続され、ＮＭＯＳトランジスタ５２２のソースは、接地されている。スイッチ５３２は、オートゼロ信号ＡＺＮに基づいて開閉する。オートゼロ信号ＡＺＰ、ＡＺＮは、極性が互いに逆の信号である。 PMOS transistor 512 and NMOS transistor 522 are connected in series with each other. The source of PMOS transistor 512 is connected to power supply voltage VDDH, and the gate of PMOS transistor 512 is connected to the drain of PMOS transistor 511. Switch 532 is connected between the gate and drain of NMOS transistor 522, and the source of NMOS transistor 522 is grounded. Switch 532 opens and closes based on auto-zero signal AZN. Auto-zero signals AZP and AZN are signals of opposite polarity.
　インバータ１８１－１は、後段アンプ５０２の出力を論理値'０'または論理値'１'に変換する。インバータ１８１－１は、ＰＭＯＳトランジスタ５１３およびＮＭＯＳトランジスタ５２３を備える。 Inverter 181-1 converts the output of rear-stage amplifier 502 to a logical value of '0' or '1'. Inverter 181-1 includes a PMOS transistor 513 and an NMOS transistor 523.
　ＰＭＯＳトランジスタ５１３とＮＭＯＳトランジスタ５２３とは互いに直列に接続されている。ＰＭＯＳトランジスタ５１３のソースは、電源電圧ＶＤＤＬに接続され、ＮＭＯＳトランジスタ５２３のソースは、接地されている。電源電圧ＶＤＤＬは、電源電圧ＶＤＤＨよりも低くすることができる。ＰＭＯＳトランジスタ５１３のゲートとＮＭＯＳトランジスタ５２３のゲートとは、ＰＭＯＳトランジスタ５１２のドレインに接続されている。 The PMOS transistor 513 and the NMOS transistor 523 are connected in series to each other. The source of the PMOS transistor 513 is connected to the power supply voltage VDDL, and the source of the NMOS transistor 523 is grounded. The power supply voltage VDDL can be lower than the power supply voltage VDDH. The gates of the PMOS transistor 513 and the NMOS transistor 523 are connected to the drain of the PMOS transistor 512.
　オートゼロ期間において、オートゼロ信号ＡＺＰに基づいて各ＰＭＯＳトランジスタ５５１および５６１がオンし、オートゼロ信号ＡＺＮに基づいてスイッチ５３２が閉じる。なお、各ＰＭＯＳトランジスタ５５１および５６１がオンした後にオフするタイミングは、スイッチ５３２が閉じた後に開くタイミングより遅くすることができる。このとき、ＰＭＯＳトランジスタ５１１および５２１のカレントミラー動作に基づいて、各ＰＭＯＳトランジスタ５５１および５６１に電流が流れる。そして、コンパレータ１７１－１の非反転入力および反転入力がバランスするように各ＤＣカットコンデンサ２９１および２９２に電荷が蓄積される。 During the auto-zero period, the PMOS transistors 551 and 561 turn on based on the auto-zero signal AZP, and the switch 532 closes based on the auto-zero signal AZN. The timing at which the PMOS transistors 551 and 561 turn on and then off can be delayed compared to the timing at which the switch 532 opens after closing. At this time, current flows through the PMOS transistors 551 and 561 based on the current mirror operation of the PMOS transistors 511 and 521. Then, charge is accumulated in the DC cut capacitors 291 and 292 so that the non-inverting input and inverting input of the comparator 171-1 are balanced.
　図１６は、第１の実施の形態に係る固体撮像装置の露光制御方法の一例を示すフローチャートである。 FIG. 16 is a flowchart showing an example of an exposure control method for a solid-state imaging device according to the first embodiment.
　同図において、固体撮像装置は、現フレームの露光を開始すると、エッジ画像を取得し（Ｓ１０１）、低階調画像を取得する（Ｓ１０２）。 In the figure, when the solid-state imaging device starts exposure of the current frame, it acquires an edge image (S101) and acquires a low-tone image (S102).
　次に、固体撮像装置は、低階調画像の任意の画素領域の出力平均値Ｄｏｕｔが所定範囲内かどうかを判断する（Ｓ１０３）。所定範囲内かどうかは、ＶＴＬ＜Ｄｏｕｔ＜ＶＴＨという関係に基づいて判断してもよい。任意の画素領域の出力平均値Ｄｏｕｔが所定範囲内の場合、現フレームの露光を開始する。一方、任意の画素領域の出力平均値Ｄｏｕｔが所定範囲外の場合、固体撮像装置は、露光時間を変更し（Ｓ１０４）、Ｓ１０１に戻る。 Next, the solid-state imaging device determines whether the average output value Dout of any pixel region of the low gradation image is within a predetermined range (S103). Whether or not it is within the predetermined range may be determined based on the relationship VTL<Dout<VTH. If the average output value Dout of the any pixel region is within the predetermined range, exposure of the current frame is started. On the other hand, if the average output value Dout of the any pixel region is outside the predetermined range, the solid-state imaging device changes the exposure time (S104) and returns to S101.
　露光時間の変更では、Ｄｏｕｔ＜ＶＴＬの場合、固体撮像装置は、任意の時間ステップで露光時間を長くする。ＶＴＨ＜Ｄｏｕｔの場合、固体撮像装置は、任意の時間ステップで露光時間を短くする。 When changing the exposure time, if Dout<VTL, the solid-state imaging device lengthens the exposure time in any time step. If VTH<Dout, the solid-state imaging device shortens the exposure time in any time step.
　このように、上述の第１の実施の形態では、固体撮像装置は、４×４画素のカーネル単位において、エッジ信号の生成に用いられない画素信号に基づいて、低階調画像を生成する。これにより、フレームレートの低下を抑制しつつ、エッジ画像を生成することが可能となるとともに、画素信号を用いた撮像制御の制御性を向上させることができ、エッジ画像の画質を向上させることができる。例えば、低階調画像に基づいて露光制御を実施しつつ、エッジ画像を生成することにより、エッジ画像の白飛びや黒つぶれなどを防止することができる。 In this way, in the first embodiment described above, the solid-state imaging device generates a low-tone image based on pixel signals that are not used to generate edge signals in 4x4 pixel kernel units. This makes it possible to generate edge images while suppressing a decrease in frame rate, and improves the controllability of imaging control using pixel signals, thereby improving the image quality of the edge images. For example, by generating an edge image while performing exposure control based on a low-tone image, it is possible to prevent highlight blowout and black crush in the edge image.
　＜２．第２の実施の形態＞
　上述の第１の実施の形態では、画素信号とレベル信号ＶＦ１からＶＦ４との比較結果に基づいて５階調分の低階調信号を生成した。この第２の実施の形態では、画素信号と比較されるレベル信号のレベル数を増大させ、画素信号とレベル信号との比較を時系列的に実施することにより、コンパレータの個数を増大させることなく、低階調信号の階調数を増大させる。 2. Second embodiment
In the first embodiment described above, five low gradation signals are generated based on the results of comparing the pixel signal with the level signals VF1 to VF4. In the second embodiment, the number of levels of the level signal compared with the pixel signal is increased, and the comparison between the pixel signal and the level signal is performed in a time series manner, thereby increasing the number of gradations of the low gradation signals without increasing the number of comparators.
　図１７は、第２の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 17 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the second embodiment.
　同図において、この固体撮像装置は、上述の第１の実施の形態の参照信号生成部１５１に代えて、参照信号生成部２５１を備える。第２の実施の形態の固体撮像装置のそれ以外の構成は、上述の第１の実施の形態の固体撮像装置の構成と同様である。 In the figure, this solid-state imaging device has a reference signal generating unit 251 instead of the reference signal generating unit 151 of the first embodiment described above. The rest of the configuration of the solid-state imaging device of the second embodiment is the same as the configuration of the solid-state imaging device of the first embodiment described above.
　参照信号生成部２５１は、上述の第１の実施の形態のレベル信号生成部１５４に代えて、レベル信号生成部２５４を備える。第２の実施の形態の参照信号生成部２５１のそれ以外の構成は、上述の第１の実施の形態の参照信号生成部１５１の構成と同様である。 The reference signal generating unit 251 includes a level signal generating unit 254 instead of the level signal generating unit 154 of the first embodiment described above. The rest of the configuration of the reference signal generating unit 251 of the second embodiment is the same as the configuration of the reference signal generating unit 151 of the first embodiment described above.
　レベル信号生成部２５４は、レベル信号ＶＦ１からＶＦ４に加えて、レベル信号ＶＦ５からＶＦ８を生成する。レベル信号ＶＦ１からＶＦ４は、レベル信号ＶＦ５からＶＦ８と異なるレベルに設定される。このとき、レベル信号生成部２５４は、切替信号ＶＦＣに基づいて、レベル信号ＶＦ１からＶＦ４の出力と、レベル信号ＶＦ５からＶＦ８とを切り替えることができる。 The level signal generating unit 254 generates level signals VF5 to VF8 in addition to level signals VF1 to VF4. The level signals VF1 to VF4 are set to a different level than the level signals VF5 to VF8. At this time, the level signal generating unit 254 can switch between the output of the level signals VF1 to VF4 and the level signals VF5 to VF8 based on the switching signal VFC.
　図１８は、第２の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。 FIG. 18 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by a solid-state imaging device according to the second embodiment.
　同図において、第２の実施の形態のエッジ画像および低階調画像の生成では、非破壊読出しに基づいて、エッジ信号が生成された後（Ｐ１１）、第１低階調信号が生成され（Ｐ１２）、その後に第２低階調信号が生成される（Ｐ１３）。第１低階調信号の生成では、レベル信号ＶＦ１からＶＦ４が用いられる。第２低階調信号の生成では、レベル信号ＶＦ５からＶＦ８が用いられる。第１低階調信号および第２低階調信号は、低階調画像の明るさが互いに異なるように生成される。 In the figure, in generating an edge image and a low gradation image in the second embodiment, an edge signal is generated based on non-destructive readout (P11), a first low gradation signal is generated (P12), and then a second low gradation signal is generated (P13). In generating the first low gradation signal, level signals VF1 to VF4 are used. In generating the second low gradation signal, level signals VF5 to VF8 are used. The first low gradation signal and the second low gradation signal are generated so that the brightness of the low gradation images is different from each other.
　エッジ信号の生成では、各画素１２０－１から１２０－４について、Ｐ相読出しが実施された後（Ｋ１１）、Ｄ相読出しが実施される（Ｋ１２）。低階調信号の生成では、各画素１２０について、Ｄ相読出しが実施された後（Ｋ１３）、第１Ｐ相読出しが実施され（Ｋ１４）、その後に第２Ｐ相読出しが実施される（Ｋ１５）。 In generating the edge signal, a P-phase readout is performed for each pixel 120-1 to 120-4 (K11), and then a D-phase readout is performed (K12). In generating the low gradation signal, a D-phase readout is performed for each pixel 120 (K13), and then a first P-phase readout is performed (K14), and then a second P-phase readout is performed (K15).
　第２低階調信号の生成では、出力イネーブル信号ＶＯＥが立ち下がった後、切替信号ＲＳＷがハイレベルに設定される（ｔ１６）。このとき、セレクタ２７１－１の入力はレベル信号ＶＦ５に切り替えられ、セレクタ２７１－２の入力はレベル信号ＶＦ６に切り替えられ、セレクタ２７１－３の入力はレベル信号ＶＦ７に切り替えられ、セレクタ２７１－４の入力はレベル信号ＶＦ８に切り替えられる。また、各スイッチ２６１－１から２６１－４はオフされる。さらに、スイッチ１６１－１は、ｍ列目のカラムの各垂直信号線１３２－１、１３２－２に接続される。スイッチ１６１－２は、ｍ＋１列目のカラムの各垂直信号線１３２－１、１３２－２に接続される。スイッチ１６１－３は、ｍ＋２列目のカラムの各垂直信号線１３２－１、１３２－２に接続される。スイッチ１６１－４は、ｍ＋３列目のカラムの各垂直信号線１３２－１、１３２－２に接続される。 In generating the second low gradation signal, after the output enable signal VOE falls, the switching signal RSW is set to a high level (t16). At this time, the input of the selector 271-1 is switched to the level signal VF5, the input of the selector 271-2 is switched to the level signal VF6, the input of the selector 271-3 is switched to the level signal VF7, and the input of the selector 271-4 is switched to the level signal VF8. In addition, each of the switches 261-1 to 261-4 is turned off. Furthermore, the switch 161-1 is connected to each of the vertical signal lines 132-1 and 132-2 of the mth column. The switch 161-2 is connected to each of the vertical signal lines 132-1 and 132-2 of the m+1th column. The switch 161-3 is connected to each of the vertical signal lines 132-1 and 132-2 of the m+2th column. Switch 161-4 is connected to each of the vertical signal lines 132-1 and 132-2 in the (m+3)th column.
　そして、各コンパレータ１７１－１から１７１－４において、カーネル単位の信号レベルのビニング値が反映されるように各ＤＣカットコンデンサ２９１、２９２に電荷が蓄積された状態で、垂直信号線１３２－１、１３２－２の電位ＶＬｃとレベル信号ＶＦ５からＶＦ８とがそれぞれ比較される。そして、各コンパレータ１７１－１から１７１－４の出力は、インバータ１８１－１から１８１－４をそれぞれ介してＮＡＮＤ回路１９１－１から１９１－４に入力される。 Then, in each of the comparators 171-1 to 171-4, the potential VLc of the vertical signal lines 132-1 and 132-2 is compared with the level signals VF5 to VF8, respectively, with electric charge stored in each of the DC cut capacitors 291 and 292 so that the binning value of the signal level of each kernel is reflected. The outputs of the comparators 171-1 to 171-4 are input to the NAND circuits 191-1 to 191-4 via the inverters 181-1 to 181-4, respectively.
　そして、出力イネーブル信号ＶＯＥが立ち上がる（ｔ２１）。このとき、各コンパレータ１７１－１から１７１－４の比較結果ＶＯ１からＶＯ４は、各インバータ１８１－１から１８１－４およびＮＡＮＤ回路１９１－１から１９１－４をそれぞれ介して第２低階調信号として出力される。 Then, the output enable signal VOE rises (t21). At this time, the comparison results VO1 to VO4 of the comparators 171-1 to 171-4 are output as the second low gradation signal via the inverters 181-1 to 181-4 and the NAND circuits 191-1 to 191-4, respectively.
　図１９は、第２の実施の形態に係る固体撮像装置のレベル信号生成部の一例を示す回路図である。 FIG. 19 is a circuit diagram showing an example of a level signal generating unit of a solid-state imaging device according to the second embodiment.
　同図において、レベル信号生成部２５４は、抵抗１５０－１から１５０－９およびスイッチ２４１－１から２４１－４を備える。抵抗１５０－１から１５０－９は、電源電圧ＶＤＤと接地電圧ＶＳＳとの間に直列に接続される。このとき、レベル信号生成部２５４は、抵抗分圧に基づいてレベル信号ＶＦ１からＶＦ８を生成することができる。ここで、抵抗１５０－１、１５０－２の接続点では、レベル信号ＶＦ１が生成される。抵抗１５０－２、１５０－３の接続点では、レベル信号ＶＦ２が生成される。抵抗１５０－３、１５０－４の接続点では、レベル信号ＶＦ３が生成される。抵抗１５０－４、１５０－５の接続点では、レベル信号ＶＦ４が生成される。抵抗１５０－５、１５０－６の接続点では、レベル信号ＶＦ５が生成される。抵抗１５０－６、１５０－７の接続点では、レベル信号ＶＦ６が生成される。抵抗１５０－７、１５０－８の接続点では、レベル信号ＶＦ７が生成される。抵抗１５０－８、１５０－９の接続点では、レベル信号ＶＦ８が生成される。 In the figure, the level signal generating unit 254 includes resistors 150-1 to 150-9 and switches 241-1 to 241-4. The resistors 150-1 to 150-9 are connected in series between the power supply voltage VDD and the ground voltage VSS. At this time, the level signal generating unit 254 can generate level signals VF1 to VF8 based on the resistor voltage division. Here, at the connection point of the resistors 150-1 and 150-2, a level signal VF1 is generated. At the connection point of the resistors 150-2 and 150-3, a level signal VF2 is generated. At the connection point of the resistors 150-3 and 150-4, a level signal VF3 is generated. At the connection point of the resistors 150-4 and 150-5, a level signal VF4 is generated. At the connection point of the resistors 150-5 and 150-6, a level signal VF5 is generated. A level signal VF6 is generated at the connection point of resistors 150-6 and 150-7. A level signal VF7 is generated at the connection point of resistors 150-7 and 150-8. A level signal VF8 is generated at the connection point of resistors 150-8 and 150-9.
　スイッチ２４１－１は、切替信号ＶＦＣに基づいて、レベル信号ＶＦ１、ＶＦ５の出力を切り替える。スイッチ２４１－２は、切替信号ＶＦＣに基づいて、レベル信号ＶＦ２、ＶＦ６の出力を切り替える。スイッチ２４１－３は、切替信号ＶＦＣに基づいて、レベル信号ＶＦ３、ＶＦ７の出力を切り替える。スイッチ２４１－４は、切替信号ＶＦＣに基づいて、レベル信号ＶＦ４、ＶＦ８の出力を切り替える。これにより、レベル信号生成部２５４は、抵抗分圧に基づいて、参照信号に８段階のレベルを設定することができる。 Switch 241-1 switches between the outputs of level signals VF1 and VF5 based on the switching signal VFC. Switch 241-2 switches between the outputs of level signals VF2 and VF6 based on the switching signal VFC. Switch 241-3 switches between the outputs of level signals VF3 and VF7 based on the switching signal VFC. Switch 241-4 switches between the outputs of level signals VF4 and VF8 based on the switching signal VFC. This allows the level signal generating unit 254 to set eight levels for the reference signal based on resistor division.
　このように、上述の第２の実施の形態では、レベル信号生成部２５４は、切替信号ＶＦＣに基づいて、レベル信号ＶＦ１からＶＦ４の出力と、レベル信号ＶＦ５からＶＦ８の出力とを切り替える。これにより、各カーネル単位において、コンパレータ１７１－１から１７１－４の個数を増大させることなく、低階調信号の階調数を増大させることができる。 In this way, in the second embodiment described above, the level signal generating unit 254 switches between the output of the level signals VF1 to VF4 and the output of the level signals VF5 to VF8 based on the switching signal VFC. This makes it possible to increase the number of gradations of the low gradation signals in each kernel unit without increasing the number of comparators 171-1 to 171-4.
　＜３．第３の実施の形態＞
　上述の第１の実施の形態では、４×４画素のカーネル単位に基づいてエッジ画像および低階調画像を生成した。この第３の実施の形態では、２×２画素のカーネル単位に基づいてエッジ画像および低階調画像を生成する。 3. Third embodiment
In the above-described first embodiment, an edge image and a low gradation image are generated based on a kernel unit of 4×4 pixels. In this third embodiment, an edge image and a low gradation image are generated based on a kernel unit of 2×2 pixels.
　図２０は、第３の実施の形態に係る固体撮像装置の読出し方法を示すブロック図である。なお、同図におけるａは、エッジ信号の生成時にカーネル単位で画素１２０から画素信号を読出す時のコンパレータ入力の切替例を示す。同図におけるｂは、低階調信号の生成時にカーネル単位で画素１２０から画素信号を読出す時のコンパレータ入力の切替例を示す。 FIG. 20 is a block diagram showing a readout method for a solid-state imaging device according to a third embodiment. Note that in the figure, "a" shows an example of comparator input switching when pixel signals are read out from pixels 120 in kernel units when edge signals are generated. "b" in the figure shows an example of comparator input switching when pixel signals are read out from pixels 120 in kernel units when low gradation signals are generated.
　同図におけるａにおいて、カーネル単位は、２×２画素（ｎ（ｎは２の倍数）行目からｎ＋１行目およびｍ（ｍは２の倍数）行目からｍ＋１行目の画素）に設定される。このとき、各カーネル単位において、縦方向のエッジおよび横方向のエッジを検出するために、４個のコンパレータ１７１－１から１７１－４が設けられる。また、エッジ信号の生成時と低階調信号の生成時とで各コンパレータ１７１－１から１７１－４への入力を切り替えるために、マルチプレクサ１６２が設けられる。 In the figure, at a, the kernel unit is set to 2x2 pixels (pixels from row n (n is a multiple of 2) to row n+1 and row m (m is a multiple of 2) to row m+1). In this case, in each kernel unit, four comparators 171-1 to 171-4 are provided to detect vertical and horizontal edges. Also, a multiplexer 162 is provided to switch the input to each of the comparators 171-1 to 171-4 when generating an edge signal and when generating a low gradation signal.
　ここで、エッジ信号の生成には、カーネル単位に含まれる４個の画素１２０のうち、４個の画素１２０－１１から１２０－１４が選択される。画素１２０－１１、１２０－１２は、横方向のエッジの検出に用いることができ、画素１２０－１３、１２０－１４は、縦方向のエッジの検出に用いることができる。このとき、マルチプレクサ１６２は、各画素１２０－１１、１２０－１２から読出された画素信号がコンパレータ１７１－１、１７１－２の両方に入力されるようにコンパレータ入力を切り替えることができる。また、マルチプレクサ１６２は、各画素１２０－１３、１２０－１４から読出された画素信号がコンパレータ１７１－３、１７１－４の両方に入力されるようにコンパレータ入力を切り替えることができる。ここで、各画素１２０－１１、１２０－１２から読出された画素信号は、コンパレータ１７１－１、１７１－２間で極性が逆になるように入力される。各画素１２０－１３、１２０－１４から読出された画素信号は、コンパレータ１７１－３、１７１－４間で極性が逆になるように入力される。 Here, to generate an edge signal, four pixels 120-11 to 120-14 are selected from the four pixels 120 included in the kernel unit. Pixels 120-11 and 120-12 can be used to detect edges in the horizontal direction, and pixels 120-13 and 120-14 can be used to detect edges in the vertical direction. At this time, multiplexer 162 can switch the comparator input so that pixel signals read out from each of pixels 120-11 and 120-12 are input to both comparators 171-1 and 171-2. Additionally, multiplexer 162 can switch the comparator input so that pixel signals read out from each of pixels 120-13 and 120-14 are input to both comparators 171-3 and 171-4. Here, the pixel signals read out from each of the pixels 120-11 and 120-12 are input to the comparators 171-1 and 171-2 so that their polarities are reversed. The pixel signals read out from each of the pixels 120-13 and 120-14 are input to the comparators 171-3 and 171-4 so that their polarities are reversed.
　一方、同図におけるｂにおいて、低階調信号の生成には、カーネル単位に含まれる４個の画素１２０が選択される。このとき、マルチプレクサ１６２は、各画素１２０から読出された画素信号のビニング値がコンパレータ１７１－１から１７１－４に入力されるようにコンパレータ入力を切り替えることができる。また、各コンパレータ１７１－１から１７１－４には、レベル信号ＶＦ１からＶＦ４が入力される。このとき、コンパレータ１７１－１から１７１－４は、フラッシュＡＤ変換器として動作することができ、５階調の低階調信号を生成することができる。 On the other hand, in b in the same figure, four pixels 120 included in the kernel unit are selected to generate a low gradation signal. At this time, the multiplexer 162 can switch the comparator input so that the binning values of the pixel signals read out from each pixel 120 are input to the comparators 171-1 to 171-4. In addition, level signals VF1 to VF4 are input to each of the comparators 171-1 to 171-4. At this time, the comparators 171-1 to 171-4 can operate as flash AD converters and can generate a five-level low gradation signal.
　図２１は、第３の実施の形態に係る固体撮像装置の画素アレイ部の構成例を示す回路図である。 FIG. 21 is a circuit diagram showing an example of the configuration of a pixel array section of a solid-state imaging device according to the third embodiment.
　同図において、画素アレイ部１１１には、カーネル単位で２×２個の画素１２０が配置される。各カーネル単位において、エッジ信号の生成時に画素１２０から読み出された画素信号が衝突しないように画素１２０が接続される。 In the figure, 2 x 2 pixels 120 are arranged in kernel units in the pixel array section 111. In each kernel unit, the pixels 120 are connected so that the pixel signals read out from the pixels 120 do not collide when generating an edge signal.
　このとき、各カーネル単位において、ｎ＋１行目の画素１２０の選択トランジスタ１２５は垂直信号線１３２－２に接続され、ｎ行目の画素１２０の選択トランジスタ１２５は垂直信号線１３２－１に接続される。選択信号ＳＥＬ１は、ｍ列目の画素１２０の選択トランジスタ１２５に印加され、選択信号ＳＥＬ２は、ｍ＋１列目の画素１２０の選択トランジスタ１２５に印加される。 At this time, in each kernel unit, the selection transistor 125 of the pixel 120 in the n+1th row is connected to the vertical signal line 132-2, and the selection transistor 125 of the pixel 120 in the nth row is connected to the vertical signal line 132-1. The selection signal SEL1 is applied to the selection transistor 125 of the pixel 120 in the mth column, and the selection signal SEL2 is applied to the selection transistor 125 of the pixel 120 in the m+1th column.
　このように、上述の第３の実施の形態では、２×２画素のカーネル単位に基づいてエッジ画像および低階調画像を生成する。これにより、４×４画素のカーネル単位に基づいてエッジ画像および低階調画像を生成する方法に比べて解像度を向上させることが可能となる。 In this way, in the third embodiment described above, edge images and low-tone images are generated based on a kernel unit of 2x2 pixels. This makes it possible to improve the resolution compared to a method in which edge images and low-tone images are generated based on a kernel unit of 4x4 pixels.
　＜４．第４の実施の形態＞
　上述の第１の実施の形態では、４×４画素のカーネル単位に基づいてエッジ画像および低階調画像を生成した。この第４の実施の形態では、３×３画素のカーネル単位に基づいてエッジ画像および低階調画像を生成する。 4. Fourth embodiment
In the above-described first embodiment, an edge image and a low gradation image are generated based on a kernel unit of 4×4 pixels. In this fourth embodiment, an edge image and a low gradation image are generated based on a kernel unit of 3×3 pixels.
　図２２は、第４の実施の形態に係る固体撮像装置の読出し方法を示すブロック図である。なお、同図におけるａは、エッジ信号の生成時にカーネル単位で画素１２０から画素信号を読出す時のコンパレータ入力の切替例を示す。同図におけるｂは、低階調信号の生成時にカーネル単位で画素１２０から画素信号を読出す時のコンパレータ入力の切替例を示す。 FIG. 22 is a block diagram showing a readout method of a solid-state imaging device according to the fourth embodiment. Note that in the figure, a shows an example of comparator input switching when pixel signals are read out from pixels 120 in kernel units when edge signals are generated. In the figure, b shows an example of comparator input switching when pixel signals are read out from pixels 120 in kernel units when low gradation signals are generated.
　同図におけるａにおいて、カーネル単位は、３×３画素（ｎ（ｎは３の倍数）行目からｎ＋１行目およびｍ（ｍは３の倍数）行目からｍ＋１行目の画素）に設定される。このとき、各カーネル単位において、縦方向のエッジおよび横方向のエッジを検出するために、４個のコンパレータ１７１－１から１７１－４が設けられる。また、エッジ信号の生成時と低階調信号の生成時とで各コンパレータ１７１－１から１７１－４への入力を切り替えるために、マルチプレクサ１６３が設けられる。 In the figure, at a, the kernel unit is set to 3x3 pixels (pixels from row n (n is a multiple of 3) to row n+1 and row m (m is a multiple of 3) to row m+1). In this case, in each kernel unit, four comparators 171-1 to 171-4 are provided to detect vertical and horizontal edges. Also, a multiplexer 163 is provided to switch the input to each of the comparators 171-1 to 171-4 when generating an edge signal and when generating a low gradation signal.
　ここで、エッジ信号の生成には、カーネル単位に含まれる９個の画素１２０のうち、４個の画素１２０－２１から１２０－２４が選択される。画素１２０－２１、１２０－２２は、横方向のエッジの検出に用いることができ、画素１２０－２３、１２０－２４は、縦方向のエッジの検出に用いることができる。このとき、マルチプレクサ１６３は、各画素１２０－２１、１２０－２２から読出された画素信号がコンパレータ１７１－１、１７１－２の両方に入力されるようにコンパレータ入力を切り替えることができる。また、マルチプレクサ１６３は、各画素１２０－２３、１２０－２４から読出された画素信号がコンパレータ１７１－３、１７１－４の両方に入力されるようにコンパレータ入力を切り替えることができる。ここで、各画素１２０－２１、１２０－２２から読出された画素信号は、コンパレータ１７１－１、１７１－２間で極性が逆になるように入力される。各画素１２０－２３、１２０－２４から読出された画素信号は、コンパレータ１７１－３、１７１－４間で極性が逆になるように入力される。 Here, to generate an edge signal, four pixels 120-21 to 120-24 are selected from the nine pixels 120 included in the kernel unit. Pixels 120-21 and 120-22 can be used to detect edges in the horizontal direction, and pixels 120-23 and 120-24 can be used to detect edges in the vertical direction. At this time, multiplexer 163 can switch the comparator input so that pixel signals read out from each of pixels 120-21 and 120-22 are input to both comparators 171-1 and 171-2. Additionally, multiplexer 163 can switch the comparator input so that pixel signals read out from each of pixels 120-23 and 120-24 are input to both comparators 171-3 and 171-4. Here, the pixel signals read out from each of the pixels 120-21 and 120-22 are input to the comparators 171-1 and 171-2 so that their polarities are reversed. The pixel signals read out from each of the pixels 120-23 and 120-24 are input to the comparators 171-3 and 171-4 so that their polarities are reversed.
　一方、同図におけるｂにおいて、低階調信号の生成には、カーネル単位に含まれる９個の画素１２０が選択される。このとき、マルチプレクサ１６３は、各画素１２０から読出された画素信号のビニング値がコンパレータ１７１－１から１７１－４に入力されるようにコンパレータ入力を切り替えることができる。また、各コンパレータ１７１－１から１７１－４には、レベル信号ＶＦ１からＶＦ４が入力される。このとき、コンパレータ１７１－１から１７１－４は、フラッシュＡＤ変換器として動作することができ、５階調の低階調信号を生成することができる。 On the other hand, in b in the same figure, nine pixels 120 included in the kernel unit are selected to generate a low gradation signal. At this time, the multiplexer 163 can switch the comparator input so that the binning values of the pixel signals read out from each pixel 120 are input to the comparators 171-1 to 171-4. In addition, level signals VF1 to VF4 are input to each of the comparators 171-1 to 171-4. At this time, the comparators 171-1 to 171-4 can operate as flash AD converters and can generate a five-level low gradation signal.
　図２３は、第４の実施の形態に係る固体撮像装置の画素アレイ部の構成例を示す回路図である。 FIG. 23 is a circuit diagram showing an example of the configuration of a pixel array section of a solid-state imaging device according to the fourth embodiment.
　同図において、画素アレイ部１１１には、カーネル単位で３×３個の画素１２０が配置される。各カーネル単位において、エッジ信号の生成時に画素１２０から読み出された画素信号が衝突しないように画素１２０が接続される。このとき、画素アレイ部１１１には、垂直信号線１３２－１、１３２－２に加えて、垂直信号線１３２－３がカラムごとに追加される。また、選択制御ドライバ１４２は、選択信号ＳＥＬ１，ＳＥＬ２に加えて、選択信号ＳＥＬ３を生成する。 In the figure, 3 x 3 pixels 120 are arranged in kernel units in the pixel array section 111. In each kernel unit, the pixels 120 are connected so that the pixel signals read out from the pixels 120 do not collide when generating an edge signal. At this time, in addition to vertical signal lines 132-1 and 132-2, a vertical signal line 132-3 is added to the pixel array section 111 for each column. Furthermore, the selection control driver 142 generates a selection signal SEL3 in addition to selection signals SEL1 and SEL2.
　ここで、各カーネル単位において、ｎ＋２行目の画素１２０の選択トランジスタ１２５は垂直信号線１３２－１に接続され、ｎ＋１行目の画素１２０の選択トランジスタ１２５は垂直信号線１３２－２に接続される。ｎ行目の画素１２０の選択トランジスタ１２５は垂直信号線１３２－３に接続される。選択信号ＳＥＬ１は、ｍ列目の画素１２０の選択トランジスタ１２５に印加され、選択信号ＳＥＬ２は、ｍ＋１列目の画素１２０の選択トランジスタ１２５に印加され、選択信号ＳＥＬ３は、ｍ＋２列目の画素１２０の選択トランジスタ１２５に印加される。 Here, in each kernel unit, the selection transistor 125 of the pixel 120 in the n+2th row is connected to the vertical signal line 132-1, and the selection transistor 125 of the pixel 120 in the n+1th row is connected to the vertical signal line 132-2. The selection transistor 125 of the pixel 120 in the nth row is connected to the vertical signal line 132-3. The selection signal SEL1 is applied to the selection transistor 125 of the pixel 120 in the mth column, the selection signal SEL2 is applied to the selection transistor 125 of the pixel 120 in the m+1th column, and the selection signal SEL3 is applied to the selection transistor 125 of the pixel 120 in the m+2th column.
　このように、上述の第４の実施の形態では、３×３画素のカーネル単位に基づいてエッジ画像および低階調画像を生成する。これにより、４×４画素のカーネル単位に基づいてエッジ画像および低階調画像を生成する方法に比べて解像度を向上させることが可能となる。 In this way, in the fourth embodiment described above, edge images and low-tone images are generated based on kernel units of 3x3 pixels. This makes it possible to improve the resolution compared to a method in which edge images and low-tone images are generated based on kernel units of 4x4 pixels.
　＜５．第５の実施の形態＞
　上述の第１の実施の形態では、４×４画素のカーネル単位に基づいてエッジ画像および低階調画像を生成した。この第５の実施の形態では、４×４画素のカーネル単位に基づいてエッジ画像を生成し、８×８画素のカーネル単位に基づいて低階調画像を生成する。 <5. Fifth embodiment>
In the first embodiment described above, an edge image and a low gradation image are generated based on a kernel unit of 4×4 pixels. In this fifth embodiment, an edge image is generated based on a kernel unit of 4×4 pixels, and a low gradation image is generated based on a kernel unit of 8×8 pixels.
　図２４は、第５の実施の形態に係る固体撮像装置の読出し方法を示す図である。 FIG. 24 shows a readout method for a solid-state imaging device according to the fifth embodiment.
　同図におけるａにおいて、エッジ画像の生成時には、カーネル単位が４×４画素に設定される。このとき、ｎ行目からｎ＋３行目について、カーネル単位でエッジ信号を生成した後、同図におけるｂに示すように、ｎ＋４行目からｎ＋７行目について、カーネル単位でエッジ信号を生成する。 In the figure, at a, when generating an edge image, the kernel unit is set to 4x4 pixels. At this time, after edge signals are generated in kernel units for rows n to n+3, edge signals are generated in kernel units for rows n+4 to n+7 as shown in the figure, at b.
　次に、同図におけるｃに示すように、低階調画像の生成時には、カーネル単位が８×８画素に設定される。このとき、８×８画素のカーネル単位に含まれる６４個の画素１２０から読み出された画素信号のビニング値に基づいて、低階調画像が生成される。 Next, as shown in c in the figure, when generating a low-tone image, the kernel unit is set to 8 x 8 pixels. At this time, a low-tone image is generated based on the binning values of pixel signals read out from 64 pixels 120 included in the kernel unit of 8 x 8 pixels.
　図２５は、第５の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。 FIG. 25 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by a solid-state imaging device according to the fifth embodiment.
　同図において、第５の実施の形態に係る固体撮像装置では、非破壊読出しに基づいて、ｎ行目からｎ＋３行目のカーネル単位についてエッジ信号が生成された後（Ｐ２１）、ｎ行目＋４行目からｎ＋７行目のカーネル単位についてエッジ信号が生成される（Ｐ２２）。そして、ｎ行目からｎ＋７行目のカーネル単位についてエッジ信号が生成された後、ｎ行目からｎ＋７行目のカーネル単位について低階調信号が生成される（Ｐ２３）。 In the figure, in the solid-state imaging device according to the fifth embodiment, an edge signal is generated for the kernel unit from the nth row to the n+3th row based on non-destructive readout (P21), and then an edge signal is generated for the kernel unit from the nth row+4th row to the n+7th row (P22). Then, after an edge signal is generated for the kernel unit from the nth row to the n+7th row, a low gradation signal is generated for the kernel unit from the nth row to the n+7th row (P23).
　ｎ行目からｎ＋３行目のカーネル単位についてのエッジ信号の生成（Ｐ２１）およびｎ＋４行目からｎ＋７行目のカーネル単位についてのエッジ信号の生成（Ｐ２２）は、図９のエッジ信号の生成（Ｐ１１）と同様である。ｎ行目からｎ＋７行目のカーネル単位について低階調信号の生成（Ｐ２３）は、図９の低階調信号の生成（Ｐ１２）と同様である。 The generation of edge signals for the kernel units from the nth row to the n+3th row (P21) and the generation of edge signals for the kernel units from the nth row to the n+7th row (P22) are the same as the generation of edge signals in FIG. 9 (P11). The generation of low gradation signals for the kernel units from the nth row to the n+7th row (P23) is the same as the generation of low gradation signals in FIG. 9 (P12).
　ただし、図９の低階調信号の生成（Ｐ１２）では、ビニング信号ＢＮＥ[ｎ＋３]－[ｎ]が立ち上がるのに対し、ｎ行目からｎ＋７行目のカーネル単位について低階調信号の生成（Ｐ２３）では、ビニング信号ＢＮＥ[ｎ＋７]－[ｎ]が立ち上がる。また、図９の低階調信号の生成（Ｐ１２）では、選択信号ＳＥＬ１[ｎ]－[ｎ＋３]およびＳＥＬ２[ｎ]－[ｎ＋３]がハイレベルに設定される。これに対して、ｎ行目からｎ＋７行目のカーネル単位について低階調信号の生成（Ｐ２３）では、選択信号ＳＥＬ１[ｎ]－[ｎ＋７]およびＳＥＬ２[ｎ]－[ｎ＋７]がハイレベルに設定される。 However, in the generation of the low gradation signal (P12) in FIG. 9, the binning signal BNE[n+3]-[n] rises, whereas in the generation of the low gradation signal for the kernel unit from row n to row n+7 (P23), the binning signal BNE[n+7]-[n] rises. Also, in the generation of the low gradation signal (P12) in FIG. 9, the selection signals SEL1[n]-[n+3] and SEL2[n]-[n+3] are set to high level. In contrast, in the generation of the low gradation signal for the kernel unit from row n to row n+7 (P23), the selection signals SEL1[n]-[n+7] and SEL2[n]-[n+7] are set to high level.
　ｎ行目からｎ＋３行目のカーネル単位についてのエッジ信号の生成では、ｎ行目からｎ＋３行目のカーネル単位の各画素１２０－１から１２０－４について、Ｐ相読出しが実施された後（Ｋ３１）、Ｄ相読出しが実施される（Ｋ３２）。ｎ＋４行目からｎ＋７行目のカーネル単位についてのエッジ信号の生成では、ｎ＋４行目からｎ＋７行目のカーネル単位の各画素１２０－１から１２０－４について、Ｐ相読出しが実施された後（Ｋ３３）、Ｄ相読出しが実施される（Ｋ３４）。ｎ行目からｎ＋７行目のカーネル単位についての低階調信号の生成では、ｎ行目からｎ＋７行目のカーネル単位の各画素１２０について、Ｄ相読出しが実施された後（Ｋ３５）、Ｐ相読出しが実施される（Ｋ３６）。 In generating edge signals for the kernel unit from the nth row to the n+3th row, a P-phase readout is performed (K31) for each pixel 120-1 to 120-4 of the kernel unit from the nth row to the n+3th row, followed by a D-phase readout (K32). In generating edge signals for the kernel unit from the nth row to the n+7th row, a P-phase readout is performed (K33) for each pixel 120-1 to 120-4 of the kernel unit from the nth row to the n+7th row, followed by a D-phase readout (K34). In generating low gradation signals for the kernel unit from the nth row to the n+7th row, a D-phase readout is performed (K35) for each pixel 120 of the kernel unit from the nth row to the n+7th row, followed by a P-phase readout (K36).
　このように、上述の第５の実施の形態では、エッジ信号の生成時と階調信号の生成時とでカーネル単位のサイズを互いに異ならせる。これにより、各フレームにおけるエッジ画像の解像度の低下を防止しつつ、低階調画像の生成にかかる時間を短縮することができる。 In this way, in the fifth embodiment described above, the size of the kernel unit is made different when generating the edge signal and when generating the gradation signal. This makes it possible to reduce the time required to generate a low gradation image while preventing a decrease in the resolution of the edge image in each frame.
　なお、低階調画像の生成時のカーネル単位は、エッジ信号の生成時のカーネル単位の整数倍とするのが好ましい。 In addition, it is preferable that the kernel unit when generating a low-tone image is an integer multiple of the kernel unit when generating an edge signal.
　＜６．第６の実施の形態＞
　上述の第１の実施の形態では、カーネル単位に含まれる全ての画素１２０から読出された画素信号のビニング値に基づいて、低階調画像を生成した。この第６の実施の形態では、カーネル単位に含まれる画素１２０のうち、エッジ信号の生成に用いられた画素１２０－１から１２０－４を除外した画素１２０から読出された画素信号のビニング値に基づいて、低階調画像を生成する。 6. Sixth embodiment
In the first embodiment described above, a low gradation image is generated based on the binning values of pixel signals read from all pixels 120 included in the kernel unit. In this sixth embodiment, a low gradation image is generated based on the binning values of pixel signals read from the pixels 120 included in the kernel unit, excluding the pixels 120-1 to 120-4 used in generating the edge signals.
　図２６は、第６の実施の形態に係る固体撮像装置によるエッジ画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 26 is a block diagram showing an example of switching of signal paths when an edge image is generated by a solid-state imaging device according to the sixth embodiment.
　同図において、画素アレイ部１１１では、上述の第１の実施の形態の垂直信号線１３２－１、１３２－２に代えて、垂直信号線１３２が設けられる。このとき、各カーネル単位において、各画素１２０の選択トランジスタ１２５は垂直信号線１３２に接続される。 In the figure, in the pixel array section 111, a vertical signal line 132 is provided instead of the vertical signal lines 132-1 and 132-2 of the first embodiment described above. At this time, in each kernel unit, the selection transistor 125 of each pixel 120 is connected to the vertical signal line 132.
　エッジ信号の生成に用いられた画素１２０－１から１２０－４を除外して低階調画像を生成する方法では、エッジ信号の生成に用いられた画素１２０－１から１２０－４と、それ以外の画素１２０とでは、別個のタイミングで画素信号が読出される。このため、同一のカラムにおいて、画素１２０－１から１２０－４からの信号読出し時に他の画素１２０から読出された信号と衝突することはなく、１本の垂直信号線１３２をカラムごとに設ければよい。 In the method of generating a low-tone image by excluding the pixels 120-1 to 120-4 used to generate the edge signal, the pixel signals are read out at separate times for the pixels 120-1 to 120-4 used to generate the edge signal and the other pixels 120. Therefore, when signals are read out from the pixels 120-1 to 120-4 in the same column, they do not collide with signals read out from other pixels 120, and one vertical signal line 132 can be provided for each column.
　また、この固体撮像装置は、上述の第１の実施の形態のマルチプレクサ１６１に代えて、マルチプレクサ１６３が設けられる。第６の実施の形態の固体撮像装置のそれ以外の構成は、上述の第１の実施の形態の固体撮像装置の構成と同様である。 In addition, this solid-state imaging device is provided with a multiplexer 163 instead of the multiplexer 161 of the first embodiment described above. The rest of the configuration of the solid-state imaging device of the sixth embodiment is the same as the configuration of the solid-state imaging device of the first embodiment described above.
　マルチプレクサ１６３は、エッジ信号の生成時と低階調信号の生成時とで各コンパレータ１７１－１から１７１－４への入力を切り替える。このとき、マルチプレクサ１６３は、エッジ信号の生成時には、２つの画素からの画素信号が互いに異なる組み合わせで各コンパレータ１７１－１から１７１－４に入力されるように垂直信号線１３２と各コンパレータ１７１－１から１７１－４の入力との接続を切り替えることができる。また、マルチプレクサ１６３は、低階調信号の生成時には、カーネル単位で読出された画素信号と、レベル信号ＶＦ１からＶＦ４とが各コンパレータ１７１－１から１７１－４に入力されるように垂直信号線１３２と各コンパレータ１７１－１から１７１－４の入力との接続を切り替えることができる。また、マルチプレクサ１６３は、高階調信号の生成時には、画素単位で読出された画素信号と、ランプ信号ＲＡＰとが各コンパレータ１７１－１から１７１－４に入力されるように各垂直信号線１３２と各コンパレータ１７１－１から１７１－４の入力との接続を切り替えることができる。 The multiplexer 163 switches the input to each of the comparators 171-1 to 171-4 when an edge signal is generated and when a low gradation signal is generated. At this time, the multiplexer 163 can switch the connection between the vertical signal line 132 and the input of each of the comparators 171-1 to 171-4 so that pixel signals from two pixels are input to each of the comparators 171-1 to 171-4 in different combinations when an edge signal is generated. In addition, the multiplexer 163 can switch the connection between the vertical signal line 132 and the input of each of the comparators 171-1 to 171-4 so that pixel signals read out on a kernel basis and level signals VF1 to VF4 are input to each of the comparators 171-1 to 171-4 when a low gradation signal is generated. In addition, when generating a high-gradation signal, the multiplexer 163 can switch the connection between each vertical signal line 132 and the input of each comparator 171-1 to 171-4 so that the pixel signal read out on a pixel-by-pixel basis and the ramp signal RAP are input to each comparator 171-1 to 171-4.
　マルチプレクサ１６１は、スイッチ１６３－１から１６３－４を備える。各スイッチ１６３－１から１６３－４は、カラムごとに設けられる。各スイッチ１６３－１から１６３－４の入力端子は、垂直信号線１３２ごとに設けられる。各スイッチ１６３－１から１６３－４の出力端子は、各コンパレータ１７１－１から１７１－４の反転入力端子に接続される。 The multiplexer 161 includes switches 163-1 to 163-4. Each switch 163-1 to 163-4 is provided for each column. The input terminals of each switch 163-1 to 163-4 are provided for each vertical signal line 132. The output terminals of each switch 163-1 to 163-4 are connected to the inverting input terminals of each comparator 171-1 to 171-4.
　ここで、固体撮像装置は、エッジ画像を生成するものとする。このとき、カーネル単位に含まれる１６個の画素１２０のうち４個の各画素１２０－１から１２０－４において、選択トランジスタ１２５がオンされ、ビニングトランジスタ１２７はオフされる。カーネル単位に含まれる４個の各画素１２０－１から１２０－４以外の１２個の画素１２０において、選択トランジスタ１２５およびビニングトランジスタ１２７はオフされる。 Here, the solid-state imaging device generates an edge image. At this time, in each of four pixels 120-1 to 120-4 out of the 16 pixels 120 included in the kernel unit, the selection transistor 125 is turned on and the binning transistor 127 is turned off. In the remaining 12 pixels 120 other than the four pixels 120-1 to 120-4 included in the kernel unit, the selection transistor 125 and the binning transistor 127 are turned off.
　また、画素１２０－１が接続された垂直信号線１３２は、スイッチ１６３－１を介してコンパレータ１７１－１に接続される。画素１２０－４が接続された垂直信号線１３２は、スイッチ１６３－２を介してコンパレータ１７１－２に接続される。画素１２０－３が接続された垂直信号線１３２は、スイッチ１６３－４を介してコンパレータ１７１－４に接続される。画素１２０－４が接続された垂直信号線１３２は、スイッチ１６３－３を介してコンパレータ１７１－３に接続される。 The vertical signal line 132 to which pixel 120-1 is connected is connected to comparator 171-1 via switch 163-1. The vertical signal line 132 to which pixel 120-4 is connected is connected to comparator 171-2 via switch 163-2. The vertical signal line 132 to which pixel 120-3 is connected is connected to comparator 171-4 via switch 163-4. The vertical signal line 132 to which pixel 120-4 is connected is connected to comparator 171-3 via switch 163-3.
　さらに、画素１２０－１が接続された垂直信号線１３２は、スイッチ１６３－１、スイッチ２６１－１およびセレクタ２７１－３を介してゲイン部２８１－３に接続される。画素１２０－４が接続された垂直信号線１３２は、スイッチ１６３－２、スイッチ２６１－２およびセレクタ２７１－４を介してゲイン部２８１－４に接続される。画素１２０－３が接続された垂直信号線１３２は、スイッチ１６３－４、スイッチ２６１－４およびセレクタ２７１－２を介してゲイン部２８１－２に接続される。画素１２０－２が接続された垂直信号線１３２は、スイッチ１６３－３、スイッチ２６１－３およびセレクタ２７１－１を介してゲイン部２８１－１に接続される。 Furthermore, the vertical signal line 132 to which pixel 120-1 is connected is connected to the gain section 281-3 via switch 163-1, switch 261-1, and selector 271-3. The vertical signal line 132 to which pixel 120-4 is connected is connected to the gain section 281-4 via switch 163-2, switch 261-2, and selector 271-4. The vertical signal line 132 to which pixel 120-3 is connected is connected to the gain section 281-2 via switch 163-4, switch 261-4, and selector 271-2. The vertical signal line 132 to which pixel 120-2 is connected is connected to the gain section 281-1 via switch 163-3, switch 261-3, and selector 271-1.
　図２７は、第６の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 27 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the sixth embodiment.
　同図において、固体撮像装置は、低階調画像を生成するものとする。このとき、カーネル単位に含まれる１６個の画素１２０のうち、エッジ信号の生成に用いられた画素１２０－１から１２０－４を除く画素１２０において、選択トランジスタ１２５およびビニングトランジスタ１２７はオンされる。 In the figure, the solid-state imaging device generates a low-tone image. At this time, the selection transistors 125 and binning transistors 127 are turned on in the 16 pixels 120 included in the kernel unit, excluding the pixels 120-1 to 120-4 used to generate the edge signal.
　また、カーネル単位に含まれるｍ列目の画素１２０が接続された垂直信号線１３２は、スイッチ１６３－１を介してコンパレータ１７１－１に接続される。カーネル単位に含まれるｍ＋１列目の画素１２０が接続された垂直信号線１３２は、スイッチ１６３－２を介してコンパレータ１７１－２に接続される。カーネル単位に含まれるｍ＋２列目の画素１２０が接続された垂直信号線１３２は、スイッチ１６３－３を介してコンパレータ１７１－３に接続される。カーネル単位に含まれるｍ＋３列目の画素１２０が接続された垂直信号線１３２は、スイッチ１６３－４を介してコンパレータ１７１－４に接続される。このとき、スイッチ２６１－１から２６１－４はオフされる。 The vertical signal line 132 to which the pixel 120 in the mth column included in the kernel unit is connected is connected to the comparator 171-1 via the switch 163-1. The vertical signal line 132 to which the pixel 120 in the m+1th column included in the kernel unit is connected is connected to the comparator 171-2 via the switch 163-2. The vertical signal line 132 to which the pixel 120 in the m+2th column included in the kernel unit is connected is connected to the comparator 171-3 via the switch 163-3. The vertical signal line 132 to which the pixel 120 in the m+3th column included in the kernel unit is connected is connected to the comparator 171-4 via the switch 163-4. At this time, the switches 261-1 to 261-4 are turned off.
　さらに、レベル信号生成部１５４で生成されたレベル信号ＶＦ１は、参照信号切替部１５５およびセレクタ２７１－１を介してゲイン部２８１－１に入力される。レベル信号生成部１５４で生成されたレベル信号ＶＦ２は、参照信号切替部１５５およびセレクタ２７１－２を介してゲイン部２８１－２に入力される。レベル信号生成部１５４で生成されたレベル信号ＶＦ３は、参照信号切替部１５５およびセレクタ２７１－３を介してゲイン部２８１－３に入力される。レベル信号生成部１５４で生成されたレベル信号ＶＦ４は、参照信号切替部１５５およびセレクタ２７１－４を介してゲイン部２８１－４に入力される。このとき、各ゲイン部２８１－１から２８１－４のゲインは１に設定される。 Furthermore, the level signal VF1 generated by the level signal generating unit 154 is input to the gain unit 281-1 via the reference signal switching unit 155 and the selector 271-1. The level signal VF2 generated by the level signal generating unit 154 is input to the gain unit 281-2 via the reference signal switching unit 155 and the selector 271-2. The level signal VF3 generated by the level signal generating unit 154 is input to the gain unit 281-3 via the reference signal switching unit 155 and the selector 271-3. The level signal VF4 generated by the level signal generating unit 154 is input to the gain unit 281-4 via the reference signal switching unit 155 and the selector 271-4. At this time, the gain of each of the gain units 281-1 to 281-4 is set to 1.
　図２８は、第６の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。 FIG. 28 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by a solid-state imaging device according to the sixth embodiment.
　同図において、選択制御ドライバ１４２は、選択信号ＳＥＬ、ＳＥＬＥ、転送信号ＴＲＧ、ＴＲＧＥおよびビニング信号ＢＮＥ、ＢＮＥＥを生成する。各カーネル単位において、選択信号ＳＥＬＥは、エッジ信号の生成に用いられた画素１２０－１から１２０－４の選択トランジスタ１２５に印加される。各カーネル単位において、選択信号ＳＥＬは、エッジ信号の生成に用いられない画素１２０の選択トランジスタ１２５に印加される。各カーネル単位において、転送信号ＴＲＧＥは、エッジ信号の生成に用いられた画素１２０－１から１２０－４の転送トランジスタ１２２に印加される。各カーネル単位において、転送信号ＴＲＧは、エッジ信号の生成に用いられない画素１２０の転送トランジスタ１２２に印加される。各カーネル単位において、ビニング信号ＢＮＥＥは、エッジ信号の生成に用いられた画素１２０－１から１２０－４のビニングトランジスタ１２７に印加される。各カーネル単位において、ビニング信号ＢＮＥは、エッジ信号の生成に用いられない画素１２０のビニングトランジスタ１２７に印加される。 In the figure, the selection control driver 142 generates selection signals SEL, SELE, transfer signals TRG, TRGE, and binning signals BNE, BNEE. In each kernel unit, the selection signal SELE is applied to the selection transistors 125 of the pixels 120-1 to 120-4 used to generate the edge signal. In each kernel unit, the selection signal SEL is applied to the selection transistors 125 of the pixels 120 not used to generate the edge signal. In each kernel unit, the transfer signal TRGE is applied to the transfer transistors 122 of the pixels 120-1 to 120-4 used to generate the edge signal. In each kernel unit, the transfer signal TRG is applied to the transfer transistors 122 of the pixels 120 not used to generate the edge signal. In each kernel unit, the binning signal BNEE is applied to the binning transistors 127 of the pixels 120-1 to 120-4 used to generate the edge signal. In each kernel unit, the binning signal BNE is applied to the binning transistors 127 of the pixels 120 that are not used to generate the edge signal.
　第６の実施の形態のエッジ画像および低階調画像の生成では、非破壊読出しに基づいて、エッジ信号が生成された後（Ｐ４１）、低階調信号が生成される（Ｐ４２）。エッジ信号の生成では、各画素１２０－１から１２０－４について、Ｐ相読出しが実施された後（Ｋ４１）、Ｄ相読出しが実施される（Ｋ４２）。このとき、リセットレベルに基づくオートゼロ動作後に、信号レベルのＡＤ変換に基づいてエッジ信号が生成される。低階調信号の生成では、エッジ信号の生成に用いられた画素１２０－１から１２０－４を除いた各画素１２０について、Ｐ相読出しが実施された後（Ｋ４３）、Ｄ相読出しが実施される（Ｋ４４）。このとき、カーネル単位で読み出された画素１２０のうちエッジ信号の生成に用いられた画素１２０－１から１２０－４を含まない画素１２０について、リセットレベルのビニング値に基づくオートゼロ動作後に、信号レベルのビニング値のＡＤ変換に基づいて諧調信号が生成される。この低階調信号の生成では、ＣＤＳを実施することができる。 In the generation of the edge image and the low gradation image of the sixth embodiment, an edge signal is generated based on non-destructive readout (P41), and then a low gradation signal is generated (P42). In the generation of the edge signal, a P-phase readout is performed for each pixel 120-1 to 120-4 (K41), and then a D-phase readout is performed (K42). At this time, after an auto-zero operation based on the reset level, an edge signal is generated based on AD conversion of the signal level. In the generation of the low gradation signal, a P-phase readout is performed for each pixel 120 except for the pixels 120-1 to 120-4 used in generating the edge signal (K43), and then a D-phase readout is performed (K44). At this time, for the pixels 120 read out in kernel units that do not include the pixels 120-1 to 120-4 used in generating the edge signal, a gradation signal is generated based on AD conversion of the binning value of the signal level after an auto-zero operation based on the binning value of the reset level. In the generation of this low gradation signal, CDS can be performed.
　エッジ信号の生成では、切替信号ＲＳＷがロウレベルに設定される。このとき、セレクタ２７１－１の入力はスイッチ２６１－３側に切り替えられ、セレクタ２７１－２の入力はスイッチ２６１－４側に切り替えられ、セレクタ２７１－３の入力はスイッチ２６１－１側に切り替えられ、セレクタ２７１－４の入力はスイッチ２６１－２側に切り替えられる。また、各スイッチ２６１－１から２６１－４はオンされる。さらに、スイッチ１６１－１は、画素１２０－１が接続された垂直信号線１３２に接続される。スイッチ１６１－２は、画素１２０－４が接続された垂直信号線１３２に接続される。スイッチ１６１－３は、画素１２０－３が接続された垂直信号線１３２に接続される。スイッチ１６１－４は、画素１２０－２が接続された垂直信号線１３２に接続される。 When generating an edge signal, the switching signal RSW is set to a low level. At this time, the input of the selector 271-1 is switched to the switch 261-3 side, the input of the selector 271-2 is switched to the switch 261-4 side, the input of the selector 271-3 is switched to the switch 261-1 side, and the input of the selector 271-4 is switched to the switch 261-2 side. In addition, each of the switches 261-1 to 261-4 is turned on. Furthermore, the switch 161-1 is connected to the vertical signal line 132 to which the pixel 120-1 is connected. The switch 161-2 is connected to the vertical signal line 132 to which the pixel 120-4 is connected. The switch 161-3 is connected to the vertical signal line 132 to which the pixel 120-3 is connected. The switch 161-4 is connected to the vertical signal line 132 to which the pixel 120-2 is connected.
　また、リセット信号ＲＳＴ[ｎ＋３]－[ｎ]が立ち上がり（ｔ４１）、カーネル単位に含まれる画素１２０のリセットトランジスタ１２３がオンしてフローティングディフュージョン１２６がリセットされる。 In addition, the reset signal RST[n+3]-[n] rises (t41), turning on the reset transistor 123 of the pixel 120 included in the kernel unit and resetting the floating diffusion 126.
　また、オートゼロ信号ＡＺが立ち上がり（ｔ４１）、各コンパレータ１７１－１から１７１－４のオートゼロ動作がアクティブ化される。このとき、各コンパレータ１７１－１から１７１－４の非反転入力および反転入力がバランスするように、ＤＣカットコンデンサ２９１、２９２に蓄積される電荷が制御される。 Also, the auto-zero signal AZ rises (t41), activating the auto-zero operation of each of the comparators 171-1 to 171-4. At this time, the charge stored in the DC- cut capacitors 291 and 292 is controlled so that the non-inverting input and the inverting input of each of the comparators 171-1 to 171-4 are balanced.
　また、選択信号ＳＥＬＥ[ｎ＋３]－ [ｎ]がハイレベル、選択信号ＳＥＬ[ｎ＋３]－ [ｎ]がロウレベルに設定される（ｔ４１）。このとき、各画素１２０－１から１２０－４の選択トランジスタ１２５はオンし、それ以外の画素１２０の選択トランジスタ１２５はオフする。 Furthermore, the selection signal SELE[n+3]-[n] is set to a high level, and the selection signal SEL[n+3]-[n] is set to a low level (t41). At this time, the selection transistors 125 of the pixels 120-1 to 120-4 are turned on, and the selection transistors 125 of the other pixels 120 are turned off.
　次に、リセット信号ＲＳＴ[ｎ＋３]－[ｎ]が立ち下がり（ｔ４２）、カーネル単位に含まれる画素１２０のリセットトランジスタ１２３がオフする。 Next, the reset signal RST[n+3]-[n] falls (t42), and the reset transistor 123 of the pixel 120 included in the kernel unit is turned off.
　このとき、画素１２０－１のフローティングディフュージョン１２６のリセットレベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－１が接続された垂直信号線１３２の電位ＶＬｃ１が設定される。また、画素１２０－４のフローティングディフュージョン１２６のリセットレベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－４が接続された垂直信号線１３２の電位ＶＬｃ２が設定される。また、画素１２０－３のフローティングディフュージョン１２６のリセットレベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－３が接続された垂直信号線１３２の電位ＶＬｃ３が設定される。また、画素１２０－２のフローティングディフュージョン１２６のリセットレベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－２が接続された垂直信号線１３２の電位ＶＬｃ４が設定される。 At this time, the potential VLc1 of the vertical signal line 132 to which pixel 120-1 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-1 is applied to the gate of the amplification transistor 124. Also, the potential VLc2 of the vertical signal line 132 to which pixel 120-4 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-4 is applied to the gate of the amplification transistor 124. Also, the potential VLc3 of the vertical signal line 132 to which pixel 120-3 is connected is set based on the source follower operation when the reset level of the floating diffusion 126 of pixel 120-3 is applied to the gate of the amplification transistor 124. In addition, the potential VLc4 of the vertical signal line 132 to which pixel 120-2 is connected is set based on the source follower action when the reset level of the floating diffusion 126 of pixel 120-2 is applied to the gate of the amplification transistor 124.
　次に、オートゼロ信号ＡＺが立ち下がった後（ｔ４３）、転送信号ＴＲＧＥ[ｎ＋３]－[ｎ]が立ち上がる（ｔ４４）。このとき、画素１２０－１から１２０－４の転送トランジスタ１２２がオンしてフォトダイオード１２１に蓄積された電荷がフローティングディフュージョン１２６に転送される。 Next, after the auto-zero signal AZ falls (t43), the transfer signal TRGE[n+3]-[n] rises (t44). At this time, the transfer transistors 122 of the pixels 120-1 to 120-4 are turned on, and the charge accumulated in the photodiodes 121 is transferred to the floating diffusion 126.
　そして、画素１２０－１のフォトダイオード１２１のカソード電位が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－１が接続された垂直信号線１３２の電位ＶＬｃ１が設定される。また、画素１２０－４のフォトダイオード１２１のカソード電位が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－４が接続された垂直信号線１３２の電位ＶＬｃ２が設定される。また、画素１２０－３のフォトダイオード１２１のカソード電位が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－３が接続された垂直信号線１３２の電位ＶＬｃ３が設定される。また、画素１２０－２のフォトダイオード１２１のカソード電位が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－２が接続された垂直信号線１３２の電位ＶＬｃ４が設定される。 Then, the potential VLc1 of the vertical signal line 132 to which pixel 120-1 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-1 is applied to the gate of the amplification transistor 124. Furthermore, the potential VLc2 of the vertical signal line 132 to which pixel 120-4 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-4 is applied to the gate of the amplification transistor 124. Furthermore, the potential VLc3 of the vertical signal line 132 to which pixel 120-3 is connected is set based on the source follower operation when the cathode potential of the photodiode 121 of pixel 120-3 is applied to the gate of the amplification transistor 124. In addition, the potential VLc4 of the vertical signal line 132 to which pixel 120-2 is connected is set based on the source follower action when the cathode potential of the photodiode 121 of pixel 120-2 is applied to the gate of the amplification transistor 124.
　次に、転送信号ＴＲＧ[ｎ＋３]－[ｎ]が立ち下がり、カーネル単位に含まれる画素１２０の転送トランジスタ１２２がオフする。 Next, the transfer signal TRG[n+3]-[n] falls, and the transfer transistor 122 of the pixel 120 included in the kernel unit is turned off.
　このとき、画素１２０－１のフローティングディフュージョン１２６の信号レベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－１が接続された垂直信号線１３２の電位ＶＬｃ１が設定される。また、画素１２０－４のフローティングディフュージョン１２６の信号レベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－４が接続された垂直信号線１３２の電位ＶＬｃ２が設定される。また、画素１２０－３のフローティングディフュージョン１２６の信号レベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－３が接続された垂直信号線１３２の電位ＶＬｃ３が設定される。また、画素１２０－２のフローティングディフュージョン１２６の信号レベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、画素１２０－２が接続された垂直信号線１３２の電位ＶＬｃ４が設定される。 At this time, the potential VLc1 of the vertical signal line 132 to which pixel 120-1 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-1 is applied to the gate of the amplification transistor 124. Also, the potential VLc2 of the vertical signal line 132 to which pixel 120-4 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-4 is applied to the gate of the amplification transistor 124. Also, the potential VLc3 of the vertical signal line 132 to which pixel 120-3 is connected is set based on the source follower operation when the signal level of the floating diffusion 126 of pixel 120-3 is applied to the gate of the amplification transistor 124. In addition, the potential VLc4 of the vertical signal line 132 to which pixel 120-2 is connected is set based on the source follower action when the signal level of the floating diffusion 126 of pixel 120-2 is applied to the gate of the amplification transistor 124.
　そして、各コンパレータ１７１－１、１７１－２において、画素１２０－１が接続された垂直信号線１３２の電位ＶＬｃ１と、画素１２０－４が接続された垂直信号線１３２の電位ＶＬｃ２とが比較される。また、各コンパレータ１７１－３、１７１－４において、画素１２０－３が接続された垂直信号線１３２の電位ＶＬｃ３と、画素１２０－２が接続された垂直信号線１３２の電位ＶＬｃ４とが比較される。このとき、各コンパレータ１７１－１から１７１－４の非反転入力端子にそれぞれ入力される電位ＶＬｃ１からＶＬｃ４は、ゲインＧがかけられてもよい。そして、各コンパレータ１７１－１から１７１－４の出力は、インバータ１８１－１から１８１－４をそれぞれ介してＮＡＮＤ回路１９１－１から１９１－４に入力される。 Then, in each of the comparators 171-1 and 171-2, the potential VLc1 of the vertical signal line 132 to which the pixel 120-1 is connected is compared with the potential VLc2 of the vertical signal line 132 to which the pixel 120-4 is connected. In addition, in each of the comparators 171-3 and 171-4, the potential VLc3 of the vertical signal line 132 to which the pixel 120-3 is connected is compared with the potential VLc4 of the vertical signal line 132 to which the pixel 120-2 is connected. At this time, the potentials VLc1 to VLc4 input to the non-inverting input terminals of each of the comparators 171-1 to 171-4 may be multiplied by a gain G. Then, the outputs of each of the comparators 171-1 to 171-4 are input to the NAND circuits 191-1 to 191-4 via the inverters 181-1 to 181-4, respectively.
　そして、出力イネーブル信号ＶＯＥが立ち上がる（ｔ４５）。このとき、各コンパレータ１７１－１から１７１－４の比較結果ＶＯ１からＶＯ４は、各インバータ１８１－１から１８１－４およびＮＡＮＤ回路１９１－１から１９１－４をそれぞれ介してエッジ信号として出力される。 Then, the output enable signal VOE rises (t45). At this time, the comparison results VO1 to VO4 of the comparators 171-1 to 171-4 are output as edge signals via the inverters 181-1 to 181-4 and the NAND circuits 191-1 to 191-4, respectively.
　低階調信号の生成では、切替信号ＲＳＷがハイレベルに設定される。このとき、セレクタ２７１－１の入力はレベル信号ＶＦ１に切り替えられ、セレクタ２７１－２の入力はレベル信号ＶＦ２に切り替えられ、セレクタ２７１－３の入力はレベル信号ＶＦ３に切り替えられ、セレクタ２７１－４の入力はレベル信号ＶＦ４に切り替えられる。また、各スイッチ２６１－１から２６１－４はオフされる。さらに、スイッチ１６１－１は、ｍ列目のカラムの垂直信号線１３２に接続される。スイッチ１６１－２は、ｍ＋１列目のカラムの垂直信号線１３２に接続される。スイッチ１６１－３は、ｍ＋２列目のカラムの垂直信号線１３２に接続される。スイッチ１６１－４は、ｍ＋３列目のカラムの垂直信号線１３２に接続される。 When generating a low gradation signal, the switching signal RSW is set to a high level. At this time, the input of the selector 271-1 is switched to the level signal VF1, the input of the selector 271-2 is switched to the level signal VF2, the input of the selector 271-3 is switched to the level signal VF3, and the input of the selector 271-4 is switched to the level signal VF4. In addition, each of the switches 261-1 to 261-4 is turned off. Furthermore, the switch 161-1 is connected to the vertical signal line 132 of the mth column. The switch 161-2 is connected to the vertical signal line 132 of the m+1th column. The switch 161-3 is connected to the vertical signal line 132 of the m+2th column. The switch 161-4 is connected to the vertical signal line 132 of the m+3th column.
　また、出力イネーブル信号ＶＯＥが立ち下がる（ｔ４６）。また、リセット信号ＲＳＴ[ｎ＋３]－[ｎ]が立ち上がり（ｔ４６）、カーネル単位に含まれる画素１２０のリセットトランジスタ１２３がオンしてフローティングディフュージョン１２６がリセットされる。また、オートゼロ信号ＡＺが立ち上がり（ｔ４６）、各コンパレータ１７１－１から１７１－４のオートゼロ動作がアクティブ化される。また、ビニング信号ＢＮＥ[ｎ＋３]－[ｎ]が立ち上がり、画素１２０－１から１２０－４以外の画素１２０のビニングトランジスタ１２７がオンされる。また、選択信号ＳＥＬＥ[ｎ＋３]－[ｎ]が立ち下がるとともに、選択信号ＳＥＬ[ｎ＋３]－[ｎ]が立ち上がる（ｔ４６）。このとき、画素１２０－１から１２０－４の選択トランジスタ１２５がオフされるとともに、それ以外の画素１２０の選択トランジスタ１２５がオンされる。 The output enable signal VOE also falls (t46). The reset signal RST[n+3]-[n] also rises (t46), turning on the reset transistor 123 of the pixel 120 included in the kernel unit and resetting the floating diffusion 126. The auto-zero signal AZ also rises (t46), activating the auto-zero operation of each of the comparators 171-1 to 171-4. The binning signal BNE[n+3]-[n] also rises, turning on the binning transistors 127 of the pixels 120 other than the pixels 120-1 to 120-4. The selection signal SELE[n+3]-[n] also falls, and the selection signal SEL[n+3]-[n] also rises (t46). At this time, the selection transistors 125 of the pixels 120-1 to 120-4 are turned off, and the selection transistors 125 of the other pixels 120 are turned on.
　次に、リセット信号ＲＳＴ[ｎ＋３]－[ｎ]が立ち下がり、カーネル単位に含まれる画素１２０のリセットトランジスタ１２３がオフする。 Next, the reset signal RST[n+3]-[n] falls, turning off the reset transistor 123 of the pixel 120 included in the kernel unit.
　このとき、画素１２０－１から１２０－４以外の画素１２０のリセットレベルのビニング値が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、カーネル単位のｍ列目からｍ＋３列目のカラムの垂直信号線１３２の電位ＶＬｃが設定される（ｔ４７）。ここで、カーネル単位のｍ列目からｍ＋３列目のカラムの垂直信号線１３２の電位ＶＬｃがＤＣカットコンデンサ２９２を介して各コンパレータ１７１－１から１７１－４の反転入力端子に印加されているときに各コンパレータ１７１－１から１７１－４の非反転入力および反転入力がバランスするように各ＤＣカットコンデンサ２９１、２９２に電荷が蓄積される。各コンパレータ１７１－１から１７１－４にそれぞれ接続されたＤＣカットコンデンサ２９１、２９２に蓄積される電荷は、カーネル単位に含まれる１６個の画素１２０のリセットレベルのビニング値が反映される。 At this time, the potential VLc of the vertical signal line 132 of the mth to m+3th columns of the kernel unit is set based on the source follower operation when the binning value of the reset level of the pixels 120 other than the pixels 120-1 to 120-4 is applied to the gate of the amplification transistor 124 (t47). Here, when the potential VLc of the vertical signal line 132 of the mth to m+3th columns of the kernel unit is applied to the inverting input terminal of each of the comparators 171-1 to 171-4 via the DC cut capacitor 292, charge is accumulated in each of the DC cut capacitors 291, 292 so that the non-inverting input and the inverting input of each of the comparators 171-1 to 171-4 are balanced. The charge accumulated in the DC cut capacitors 291, 292 connected to each of the comparators 171-1 to 171-4 reflects the binning value of the reset level of the 16 pixels 120 included in the kernel unit.
　次に、オートゼロ信号ＡＺが立ち下がった後、転送信号ＴＲＧ[ｎ＋３]－[ｎ]が立ち上がる（ｔ４８）。このとき、画素１２０－１から１２０－４以外の画素１２０の転送トランジスタ１２２がオンしてフォトダイオード１２１に蓄積された電荷がフローティングディフュージョン１２６に転送される。 Next, after the auto-zero signal AZ falls, the transfer signal TRG[n+3]-[n] rises (t48). At this time, the transfer transistors 122 of the pixels 120 other than pixels 120-1 to 120-4 are turned on, and the charge accumulated in the photodiodes 121 is transferred to the floating diffusion 126.
　次に、転送信号ＴＲＧ[ｎ＋３]－[ｎ]が立ち下がり、画素１２０－１から１２０－４以外の画素１２０の転送トランジスタ１２２がオフする。 Next, the transfer signal TRG[n+3]-[n] falls, and the transfer transistors 122 of the pixels 120 other than pixels 120-1 to 120-4 are turned off.
　このとき、画素１２０－１から１２０－４以外の画素１２０の信号レベルのビニング値が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、カーネル単位のｍ列目からｍ＋３列目のカラムの垂直信号線１３２の電位ＶＬｃが設定される。 At this time, the potential VLc of the vertical signal line 132 of the mth to (m+3)th columns of the kernel unit is set based on the source follower operation when the binning values of the signal levels of the pixels 120 other than the pixels 120-1 to 120-4 are applied to the gates of the amplification transistors 124.
　そして、各コンパレータ１７１－１から１７１－４において、画素１２０－１から１２０－４以外の画素１２０のリセットレベルのビニング値が反映されるように各ＤＣカットコンデンサ２９１、２９２に電荷が蓄積された状態で、垂直信号線１３２の電位ＶＬｃとレベル信号ＶＦ１からＶＦ４とがそれぞれ比較される。このとき、アナログＣＤＳに基づいて、低階調信号を生成することができる。そして、各コンパレータ１７１－１から１７１－４の出力は、インバータ１８１－１から１８１－４をそれぞれ介してＮＡＮＤ回路１９１－１から１９１－４に入力される。 Then, in each of the comparators 171-1 to 171-4, the potential VLc of the vertical signal line 132 is compared with the level signals VF1 to VF4 in a state in which charge is stored in each of the DC cut capacitors 291, 292 so that the binning values of the reset levels of the pixels 120 other than the pixels 120-1 to 120-4 are reflected. At this time, a low gradation signal can be generated based on the analog CDS. The outputs of the comparators 171-1 to 171-4 are input to the NAND circuits 191-1 to 191-4 via the inverters 181-1 to 181-4, respectively.
　そして、出力イネーブル信号ＶＯＥが立ち上がる（ｔ４９）。このとき、各コンパレータ１７１－１から１７１－４の比較結果ＶＯ１からＶＯ４は、各インバータ１８１－１から１８１－４およびＮＡＮＤ回路１９１－１から１９１－４をそれぞれ介して低階調信号として出力される。 Then, the output enable signal VOE rises (t49). At this time, the comparison results VO1 to VO4 of the comparators 171-1 to 171-4 are output as low gradation signals via the inverters 181-1 to 181-4 and the NAND circuits 191-1 to 191-4, respectively.
　図２９は、第６の実施の形態に係る固体撮像装置の画素アレイ部の構成例を示す回路図である。 FIG. 29 is a circuit diagram showing an example of the configuration of a pixel array section of a solid-state imaging device according to the sixth embodiment.
　同図において、画素アレイ部１１１には、カーネル単位で４×４個の画素１２０が配置される。各カーネル単位において、エッジ信号の生成に用いられる画素１２０－１から１２０－４からの読出しと、それ以外の画素１２０からの読出しが別個に実施可能となるように、画素１２０が接続される。 In the figure, 4 x 4 pixels 120 are arranged in kernel units in the pixel array section 111. In each kernel unit, the pixels 120 are connected so that reading from the pixels 120-1 to 120-4 used to generate edge signals and reading from the other pixels 120 can be performed separately.
　このとき、選択信号ＳＥＬＥは、各画素１２０－１から１２０－４の選択トランジスタ１２５に印加され、選択信号ＳＥＬは、それ以外の画素１２０の選択トランジスタ１２５に印加される。転送信号ＴＲＧＥは、各画素１２０－１から１２０－４の転送トランジスタ１２２に印加され、転送信号ＴＲＧは、それ以外の画素１２０の転送トランジスタ１２２に印加される。ビニング信号ＢＮＥＥは、各画素１２０－１から１２０－４のビニングトランジスタ１２７に印加され、ビニング信号ＢＮＥは、それ以外の画素１２０のビニングトランジスタ１２７に印加される。 At this time, the selection signal SELE is applied to the selection transistors 125 of each of the pixels 120-1 to 120-4, and the selection signal SEL is applied to the selection transistors 125 of the other pixels 120. The transfer signal TRGE is applied to the transfer transistors 122 of each of the pixels 120-1 to 120-4, and the transfer signal TRG is applied to the transfer transistors 122 of the other pixels 120. The binning signal BNEE is applied to the binning transistors 127 of each of the pixels 120-1 to 120-4, and the binning signal BNE is applied to the binning transistors 127 of the other pixels 120.
　このように、上述の第６の実施の形態では、カーネル単位に含まれる画素１２０のうち、エッジ信号の生成に用いられた画素１２０－１から１２０－４を除外した画素１２０から読出された画素信号のビニング値に基づいて、低階調画像を生成する。これにより、ＣＤＳに基づいて低階調画像を生成することができ、低階調画像の画質を向上させることができる。 In this way, in the sixth embodiment described above, a low-tone image is generated based on the binning values of pixel signals read from the pixels 120 included in the kernel unit, excluding the pixels 120-1 to 120-4 used to generate the edge signals. This makes it possible to generate a low-tone image based on the CDS, thereby improving the image quality of the low-tone image.
　＜７．第７の実施の形態＞
　上述の第６の実施の形態では、エッジ信号の生成に用いられた画素１２０－１から１２０－４を除外した画素１２０から読出された画素信号のビニング値と、各レベル信号ＶＦ１からＶＦ４との比較結果に基づいて、低階調画像を生成した。この第７の実施の形態では、エッジ信号の生成に用いられた画素１２０－１から１２０－４を除外した画素１２０から読出された画素信号のビニング値と、ランプ信号ＲＡＰとの比較結果に基づいて、低階調画像を生成する。 7. Seventh embodiment
In the sixth embodiment described above, a low gradation image is generated based on a comparison result between the binning value of the pixel signals read from the pixels 120 excluding the pixels 120-1 to 120-4 used to generate the edge signal and each of the level signals VF1 to VF4. In the seventh embodiment, a low gradation image is generated based on a comparison result between the binning value of the pixel signals read from the pixels 120 excluding the pixels 120-1 to 120-4 used to generate the edge signal and the ramp signal RAP.
　図３０は、第７の実施の形態に係る固体撮像装置による階調画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 30 is a block diagram showing an example of signal path switching when a gradation image is generated by a solid-state imaging device according to the seventh embodiment.
　同図において、この固体撮像装置は、上述の第６の実施の形態のコンパレータ１７１－１から１７１－４に代えて、コンパレータ１７２－１から１７２－４を備える。第７の実施の形態の固体撮像装置のそれ以外の構成は、上述の第６の実施の形態の固体撮像装置の構成と同様である。 In the figure, this solid-state imaging device has comparators 172-1 to 172-4 instead of comparators 171-1 to 171-4 of the sixth embodiment described above. The rest of the configuration of the solid-state imaging device of the seventh embodiment is the same as the configuration of the solid-state imaging device of the sixth embodiment described above.
　各コンパレータ１７２－１から１７２－４には、アクティブ制御信号ＣＴＬが入力される。各コンパレータ１７２－１から１７２－４は、アクティブ制御信号ＣＴＬに基づいて、ＡＤ変換のアクティブ化のタイミングが制御される。各コンパレータ１７２－１から１７２－４は、アクティブ化されるカラムと非アクティブ化されるカラムとに分けてＡＤ変換のタイミングが制御されてもよい。このとき、アクティブ化されるカラムでは、各コンパレータ１７２－１から１７２－４がアクティブ化され、非アクティブ化されるカラムでは、各コンパレータ１７２－１から１７２－４がスタンバイ状態に設定されてもよい。 An active control signal CTL is input to each of the comparators 172-1 to 172-4. The timing of activation of the AD conversion of each of the comparators 172-1 to 172-4 is controlled based on the active control signal CTL. The timing of the AD conversion of each of the comparators 172-1 to 172-4 may be controlled separately for columns to be activated and columns to be deactivated. At this time, in the columns to be activated, each of the comparators 172-1 to 172-4 may be activated, and in the columns to be deactivated, each of the comparators 172-1 to 172-4 may be set to a standby state.
　固体撮像装置は、低階調画像を生成するものとする。このとき、カーネル単位に含まれる１６個の画素１２０のうち、エッジ信号の生成に用いられた画素１２０－１から１２０－４を除く画素１２０において、選択トランジスタ１２５およびビニングトランジスタ１２７はオンされる。 The solid-state imaging device generates a low-tone image. At this time, the selection transistors 125 and binning transistors 127 are turned on in the 16 pixels 120 included in the kernel unit, excluding the pixels 120-1 to 120-4 used to generate the edge signal.
　また、カーネル単位に含まれるｍ列目の画素１２０が接続された垂直信号線１３２は、スイッチ１６３－１を介してコンパレータ１７１－１に接続される。カーネル単位に含まれるｍ＋１列目の画素１２０が接続された垂直信号線１３２は、スイッチ１６３－２を介してコンパレータ１７１－２に接続される。カーネル単位に含まれるｍ＋２列目の画素１２０が接続された垂直信号線１３２は、スイッチ１６３－３を介してコンパレータ１７１－３に接続される。カーネル単位に含まれるｍ＋３列目の画素１２０が接続された垂直信号線１３２は、スイッチ１６３－４を介してコンパレータ１７１－４に接続される。このとき、スイッチ２６１－１から２６１－４はオフされる。 The vertical signal line 132 to which the pixel 120 in the mth column included in the kernel unit is connected is connected to the comparator 171-1 via the switch 163-1. The vertical signal line 132 to which the pixel 120 in the m+1th column included in the kernel unit is connected is connected to the comparator 171-2 via the switch 163-2. The vertical signal line 132 to which the pixel 120 in the m+2th column included in the kernel unit is connected is connected to the comparator 171-3 via the switch 163-3. The vertical signal line 132 to which the pixel 120 in the m+3th column included in the kernel unit is connected is connected to the comparator 171-4 via the switch 163-4. At this time, the switches 261-1 to 261-4 are turned off.
　さらに、ランプ信号ＲＡＰは、セレクタ２７１－１から２７１－４をそれぞれ介してゲイン部２８１－１から２８１－４に入力される。このとき、各ゲイン部２８１－１から２８１－４のゲインは１に設定される。 Furthermore, the ramp signal RAP is input to the gain units 281-1 to 281-4 via the selectors 271-1 to 271-4, respectively. At this time, the gain of each of the gain units 281-1 to 281-4 is set to 1.
　図３１は、第７の実施の形態に係る固体撮像装置によるエッジ画像および階調画像の生成時の各部の波形の一例を示すタイミングチャートである。 FIG. 31 is a timing chart showing an example of waveforms at various parts when an edge image and a gradation image are generated by a solid-state imaging device according to the seventh embodiment.
　同図において、第７の実施の形態のエッジ画像および低階調画像の生成では、非破壊読出しに基づいて、エッジ信号が生成された後（Ｐ４１）、低階調信号が生成される（Ｐ５２）。エッジ信号の生成では、各画素１２０－１から１２０－４について、Ｐ相読出しが実施された後（Ｋ４１）、Ｄ相読出しが実施される（Ｋ４２）。低階調信号の生成では、エッジ信号の生成に用いられた画素１２０－１から１２０－４を除いた各画素１２０について、Ｐ相読出しが実施された後（Ｋ５３）、Ｄ相読出しが実施される（Ｋ５４）。この低階調信号の生成では、ＣＤＳを実施することができる。 In the figure, in generating an edge image and a low gradation image in the seventh embodiment, an edge signal is generated based on non-destructive readout (P41), and then a low gradation signal is generated (P52). In generating an edge signal, a P-phase readout is performed for each of the pixels 120-1 to 120-4 (K41), and then a D-phase readout is performed (K42). In generating a low gradation signal, a P-phase readout is performed for each pixel 120 except for the pixels 120-1 to 120-4 used in generating the edge signal (K53), and then a D-phase readout is performed (K54). In generating this low gradation signal, CDS can be performed.
　エッジ信号の生成（ｔ５１からｔ５６）は、上述の第６の実施の形態のエッジ信号の生成（ｔ４１からｔ４６）と同様である。 The generation of the edge signal (t51 to t56) is similar to the generation of the edge signal (t41 to t46) in the sixth embodiment described above.
　低階調信号の生成では、切替信号ＲＳＷがハイレベルに設定される。このとき、各セレクタ２７１－１から２７１－４の入力はランプ信号ＲＡＰに切り替えられる。また、各スイッチ２６１－１から２６１－４はオフされる。さらに、スイッチ１６１－１は、ｍ列目のカラムの垂直信号線１３２に接続される。スイッチ１６１－２は、ｍ＋１列目のカラムの垂直信号線１３２に接続される。スイッチ１６１－３は、ｍ＋２列目のカラムの垂直信号線１３２に接続される。スイッチ１６１－４は、ｍ＋３列目のカラムの垂直信号線１３２に接続される。 When generating a low gradation signal, the switching signal RSW is set to a high level. At this time, the input of each of the selectors 271-1 to 271-4 is switched to the ramp signal RAP. Also, each of the switches 261-1 to 261-4 is turned off. Furthermore, the switch 161-1 is connected to the vertical signal line 132 of the mth column. The switch 161-2 is connected to the vertical signal line 132 of the m+1th column. The switch 161-3 is connected to the vertical signal line 132 of the m+2th column. The switch 161-4 is connected to the vertical signal line 132 of the m+3th column.
　そして、切替信号ＲＳＷがハイレベルに設定された後、リセット信号ＲＳＴ[ｎ＋３]－[ｎ]が立ち下がり、カーネル単位に含まれる画素１２０のリセットトランジスタ１２３がオフする。 Then, after the switching signal RSW is set to a high level, the reset signal RST[n+3]-[n] falls, and the reset transistor 123 of the pixel 120 included in the kernel unit is turned off.
　このとき、画素１２０－１から１２０－４以外の画素１２０のリセットレベルのビニング値が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、カーネル単位のｍ列目からｍ＋３列目のカラムの垂直信号線１３２の電位ＶＬｃが設定される（ｔ５７）。 At this time, the potential VLc of the vertical signal line 132 of the mth to (m+3)th columns of the kernel unit is set based on the source follower operation when the binning values of the reset levels of the pixels 120 other than the pixels 120-1 to 120-4 are applied to the gates of the amplification transistors 124 (t57).
　そして、オートゼロ信号ＡＺが立ち下がった後、参照信号としてランプ信号ＲＡＰが各コンパレータ１７１－１から１７１－４に供給されるとともに、出力イネーブル信号ＶＯＥが立ち上がる。ここで、コンパレータ１７１－１をアクティブ化し、各コンパレータ１７１－２から１７１－４をスタンバイ状態に設定してもよい。このとき、コンパレータ１７１－１において、リセットレベルに応じた垂直信号線１３２の電位ＶＬｃがランプ信号ＲＡＰと比較され、ランプ信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＬｃと一致したときのタイミングが比較結果ＶＯ１として出力される（ｔ５８）。そして、ランプ信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＬｃと一致するまでのカウント動作に基づいて、画素１２０－１から１２０－４以外の画素１２０から読み出されたリセットレベルのビニング値がＡＤ変換される。 After the auto-zero signal AZ falls, the ramp signal RAP is supplied to each of the comparators 171-1 to 171-4 as a reference signal, and the output enable signal VOE rises. Here, the comparator 171-1 may be activated, and each of the comparators 171-2 to 171-4 may be set to a standby state. At this time, in the comparator 171-1, the potential VLc of the vertical signal line 132 corresponding to the reset level is compared with the ramp signal RAP, and the timing when the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132 is output as the comparison result VO1 (t58). Then, based on the counting operation until the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132, the binning values of the reset levels read out from the pixels 120 other than the pixels 120-1 to 120-4 are AD converted.
　次に、出力イネーブル信号ＶＯＥが立ち下がるとともに、転送信号ＴＲＧ[ｎ＋３]－[ｎ]が立ち上がる。このとき、画素１２０－１から１２０－４以外の画素１２０の転送トランジスタ１２２がオンしてフォトダイオード１２１に蓄積された電荷がフローティングディフュージョン１２６に転送される。 Next, the output enable signal VOE falls and the transfer signal TRG[n+3]-[n] rises. At this time, the transfer transistors 122 of the pixels 120 other than pixels 120-1 to 120-4 turn on, and the charge accumulated in the photodiodes 121 is transferred to the floating diffusion 126.
　次に、転送信号ＴＲＧ[ｎ＋３]－[ｎ]が立ち下がり、画素１２０－１から１２０－４以外の画素１２０の転送トランジスタ１２２がオフする。 Next, the transfer signal TRG[n+3]-[n] falls, and the transfer transistors 122 of the pixels 120 other than pixels 120-1 to 120-4 are turned off.
　このとき、画素１２０－１から１２０－４以外の画素１２０の信号レベルのビニング値が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて、カーネル単位のｍ列目からｍ＋３列目のカラムの垂直信号線１３２の電位ＶＬｃが設定される。 At this time, the potential VLc of the vertical signal line 132 of the mth to (m+3)th columns of the kernel unit is set based on the source follower operation when the binning values of the signal levels of the pixels 120 other than the pixels 120-1 to 120-4 are applied to the gates of the amplification transistors 124.
　そして、参照信号としてランプ信号ＲＡＰが各コンパレータ１７１－１から１７１－４に供給されるとともに、出力イネーブル信号ＶＯＥが立ち上がる。そして、コンパレータ１７１－１において、信号レベルに応じた垂直信号線１３２の電位ＶＬｃがランプ信号ＲＡＰと比較され、ランプ信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＬｃと一致したときのタイミングが比較結果ＶＯ１として出力される（ｔ５９）。このとき、ランプ信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＬｃと一致するまでのカウント動作に基づいて、画素１２０－１から１２０－４以外の画素１２０から読み出された信号レベルのビニング値がＡＤ変換される。 Then, the ramp signal RAP is supplied to each of the comparators 171-1 to 171-4 as a reference signal, and the output enable signal VOE rises. Then, in the comparator 171-1, the potential VLc of the vertical signal line 132 corresponding to the signal level is compared with the ramp signal RAP, and the timing when the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132 is output as the comparison result VO1 (t59). At this time, the binning values of the signal levels read out from the pixels 120 other than the pixels 120-1 to 120-4 are AD converted based on the counting operation until the level of the ramp signal RAP matches the potential VLc of the vertical signal line 132.
　このように、上述の第７の実施の形態では、エッジ信号の生成に用いられた画素１２０－１から１２０－４を除外した画素１２０から読出された画素信号のビニング値と、ランプ信号ＲＡＰとの比較結果に基づいて、低階調画像を生成する。これにより、ＣＤＳに基づいて低階調画像を生成することが可能となるとともに、コンパレータ１７１－１から１７１－４の個数を増大させることなく、低階調画像の階調数を増大させることが可能となる。 In this way, in the seventh embodiment described above, a low-tone image is generated based on the result of comparing the binning values of the pixel signals read from the pixels 120 excluding the pixels 120-1 to 120-4 used to generate the edge signal with the ramp signal RAP. This makes it possible to generate a low-tone image based on the CDS, and to increase the number of gradations of the low-tone image without increasing the number of comparators 171-1 to 171-4.
　＜８．第８の実施の形態＞
　上述の第１の実施の形態では、低階調画像の生成に用いられる参照信号を各コンパレータ１７１－１から１７１－４に供給するために、レベル信号ＶＦ１からＶＦ４をセレクタ２７１－１から２７１－４にそれぞれ供給した。この第８の実施の形態では、低階調画像の生成に用いられる参照信号を各コンパレータ１７１－１から１７１－４に供給するために、各セレクタ２７１－１から２７１－４に供給されたレベル信号にゲインを掛けて各コンパレータ１７１－１から１７１－４に供給する。 8. Eighth embodiment
In the first embodiment described above, the level signals VF1 to VF4 are supplied to the selectors 271-1 to 271-4, respectively, in order to supply the reference signals used in generating low gradation images to the comparators 171-1 to 171-4. In this eighth embodiment, in order to supply the reference signals used in generating low gradation images to the comparators 171-1 to 171-4, the level signals supplied to the selectors 271-1 to 271-4 are multiplied by a gain and supplied to the comparators 171-1 to 171-4.
　図３２は、第８の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 32 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the eighth embodiment.
　同図において、この固体撮像装置は、上述の第１の実施の形態のゲイン部２８１－１から２８１－４に代えて、ゲイン部２８２－１から２８２－４を備える。また、この固体撮像装置では、レベル信号生成部１５４は、レベル信号ＶＦ１からＶＦ４に代えて、レベル信号ＶＦを生成し、各セレクタ２７１－１から２７１－４に供給する。第８の実施の形態の固体撮像装置のそれ以外の構成は、上述の第１の実施の形態の固体撮像装置の構成と同様である。 In the figure, this solid-state imaging device includes gain units 282-1 to 282-4 instead of the gain units 281-1 to 281-4 of the first embodiment described above. Also, in this solid-state imaging device, the level signal generation unit 154 generates a level signal VF instead of level signals VF1 to VF4, and supplies it to each of the selectors 271-1 to 271-4. The rest of the configuration of the solid-state imaging device of the eighth embodiment is the same as the configuration of the solid-state imaging device of the first embodiment described above.
　各ゲイン部２８２－１から２８２－４は、互いに異なるゲインＧ１からＧ４をレベル信号ＶＦにかけて各コンパレータ１７１－１から１７１－４に供給する。このとき、ゲイン部２８２－１は、レベル信号ＶＦにゲインＧ１をかけてレベル信号ＶＦ１を生成することができる。ゲイン部２８２－２は、レベル信号ＶＦにゲインＧ２かけてレベル信号ＶＦ２を生成することができる。ゲイン部２８２－３は、レベル信号ＶＦにゲインＧ３かけてレベル信号ＶＦ３を生成することができる。ゲイン部２８２－４は、レベル信号ＶＦにゲインＧ４かけてレベル信号ＶＦ４を生成することができる。 Each of the gain units 282-1 to 282-4 applies a different gain G1 to G4 to the level signal VF and supplies the result to each of the comparators 171-1 to 171-4. At this time, the gain unit 282-1 can multiply the level signal VF by the gain G1 to generate the level signal VF1. The gain unit 282-2 can multiply the level signal VF by the gain G2 to generate the level signal VF2. The gain unit 282-3 can multiply the level signal VF by the gain G3 to generate the level signal VF3. The gain unit 282-4 can multiply the level signal VF by the gain G4 to generate the level signal VF4.
　図３３は、第８の実施の形態に係る固体撮像装置のゲイン部の構成例を示す回路図である。 FIG. 33 is a circuit diagram showing an example of the configuration of a gain section of a solid-state imaging device according to the eighth embodiment.
　同図において、各ゲイン部２８２－１から２８２－４は、容量３０１から３０４およびスイッチ３１１から３１４を備える。各容量３０１から３０４と各スイッチ３１１から３１４は、直列に接続されるとともに、各容量３０１から３０４と各スイッチ３１１から３１４との直列回路は、並列に接続される。ここで、容量３０１の容量値をＣとすると、容量３０２の容量値は０．７５Ｃ、容量３０３の容量値は０．５Ｃ、容量３０４の容量値は０．２５Ｃに設定することができる。各スイッチ３１１から３１４は、接地電位とレベル信号ＶＦとを切り替えて、各容量３０１から３０４に入力する。このとき、各スイッチ３１１から３１４を切り替えることにより、ゲインを変更することができる。 In the figure, each of the gain sections 282-1 to 282-4 includes capacitances 301 to 304 and switches 311 to 314. Each of the capacitances 301 to 304 and each of the switches 311 to 314 are connected in series, and the series circuits of each of the capacitances 301 to 304 and each of the switches 311 to 314 are connected in parallel. Here, if the capacitance value of the capacitance 301 is C, the capacitance value of the capacitance 302 can be set to 0.75C, the capacitance value of the capacitance 303 to 0.5C, and the capacitance value of the capacitance 304 to 0.25C. Each of the switches 311 to 314 switches between the ground potential and the level signal VF and inputs it to each of the capacitances 301 to 304. At this time, the gain can be changed by switching each of the switches 311 to 314.
　例えば、同図におけるａに示すように、各スイッチ３１１から３１４をレベル信号ＶＦの入力に切り替えることにより、ゲインを１に設定することができる。 For example, as shown in FIG. 1A, the gain can be set to 1 by switching each switch 311 to 314 to input the level signal VF.
　同図におけるｂに示すように、各スイッチ３１１、３１２をレベル信号ＶＦの入力に切り替えることにより、ゲインを０．７５に設定することができる。 As shown in FIG. 3B, the gain can be set to 0.75 by switching each switch 311, 312 to input the level signal VF.
　同図におけるｃに示すように、各スイッチ３１１をレベル信号ＶＦの入力に切り替えることにより、ゲインを０．５に設定することができる。 As shown in Fig. 3c, the gain can be set to 0.5 by switching each switch 311 to input the level signal VF.
　同図におけるｄに示すように、各スイッチ３１３、３１４をレベル信号ＶＦの入力に切り替えることにより、ゲインを０．２５に設定することができる。 As shown in d of the same figure, the gain can be set to 0.25 by switching each switch 313, 314 to the input of the level signal VF.
　このように、上述の第８の実施の形態では、低階調画像の生成時において、セレクタ２７１－１から２７１－４に供給されたレベル信号ＶＦにゲインを掛けて参照信号として各コンパレータ１７１－１から１７１－４に供給する。これにより、セレクタ２７１－１から２７１－４にレベル信号ＶＦを供給する配線を共通化することができ、レベル信号ＶＦ１からＶＦ４を供給する配線をセレクタ２７１－１から２７１－４ごとに設ける必要がなくなる。 In this way, in the eighth embodiment described above, when generating a low gradation image, the level signal VF supplied to the selectors 271-1 to 271-4 is multiplied by a gain and supplied as a reference signal to each of the comparators 171-1 to 171-4. This allows the wiring that supplies the level signal VF to the selectors 271-1 to 271-4 to be common, eliminating the need to provide wiring that supplies the level signals VF1 to VF4 for each of the selectors 271-1 to 271-4.
　＜９．第９の実施の形態＞
　上述の第１の実施の形態では、リセットトランジスタ１２３、増幅トランジスタ１２４、選択トランジスタ１２５およびビニングトランジスタ１２７を画素１２０ごとに設けた。この第９の実施の形態では、リセットトランジスタ１２３、増幅トランジスタ１２４、選択トランジスタ１２５およびビニングトランジスタ１２７を複数の画素で共有する。 9. Ninth embodiment
In the above-described first embodiment, the reset transistor 123, the amplification transistor 124, the selection transistor 125, and the binning transistor 127 are provided for each pixel 120. In the ninth embodiment, the reset transistor 123, the amplification transistor 124, the selection transistor 125, and the binning transistor 127 are shared by a plurality of pixels.
　図３４は、第９の実施の形態に係る固体撮像装置に設けられた画素の構成例を示す回路図である。 FIG. 34 is a circuit diagram showing an example of the configuration of a pixel provided in a solid-state imaging device according to the ninth embodiment.
　同図において、セル６２０は、上述の第１の実施の形態のフォトダイオード１２１および転送トランジスタ１２２に代えて、フォトダイオード１２１－１から１２１－４および転送トランジスタ１２２－１から１２２－４を備える。第９の実施の形態のセル６２０のそれ以外の構成は、上述の第１の実施の形態の画素１２０の構成と同様である。 In the figure, cell 620 includes photodiodes 121-1 to 121-4 and transfer transistors 122-1 to 122-4 instead of photodiode 121 and transfer transistor 122 of the first embodiment described above. The rest of the configuration of cell 620 of the ninth embodiment is the same as the configuration of pixel 120 of the first embodiment described above.
　各フォトダイオード１２１－１から１２１－４は、２行×２列に配置することができる。このとき、各フォトダイオード１２１－１から１２１－４は、画素を構成することができる。各フォトダイオード１２１－１から１２１－４は、転送トランジスタ１２２－１から１２２－４をそれぞれ介し、フローティングディフュージョン１２６に接続されている。各転送トランジスタ１２２－１から１２２－４のゲートには、転送信号ＴＲＧ１～ＴＲＧ４が印加される。この転送信号ＴＲＧ１～ＴＲＧ４の印加タイミングを制御することにより、各フォトダイオード１２１－１から１２１－４より個別に信号を読み出してもよいし、各フォトダイオード１２１－１から１２１－４より信号をビニングして読み出してもよい。 The photodiodes 121-1 to 121-4 can be arranged in 2 rows and 2 columns. In this case, each of the photodiodes 121-1 to 121-4 can form a pixel. Each of the photodiodes 121-1 to 121-4 is connected to the floating diffusion 126 via a transfer transistor 122-1 to 122-4, respectively. Transfer signals TRG1 to TRG4 are applied to the gates of the transfer transistors 122-1 to 122-4. By controlling the application timing of the transfer signals TRG1 to TRG4, signals can be read out individually from each of the photodiodes 121-1 to 121-4, or signals can be binned and read out from each of the photodiodes 121-1 to 121-4.
　セル６２０から個別に信号を読出す場合、ビニング信号ＢＮＥはロウレベルに設定され、セル６２０のビニングトランジスタ１２７はオフされる。一方、セル６２０からビニングして信号を読出す場合、ビニング信号ＢＮＥはハイレベルに設定され、セル６２０のビニングトランジスタ１２７はオンされる。 When reading out signals individually from cells 620, the binning signal BNE is set to a low level, and the binning transistor 127 of the cell 620 is turned off. On the other hand, when reading out signals by binning from the cell 620, the binning signal BNE is set to a high level, and the binning transistor 127 of the cell 620 is turned on.
　図３５は、第９の実施の形態に係る固体撮像装置の画素アレイ部の構成例を示す回路図である。 FIG. 35 is a circuit diagram showing an example of the configuration of a pixel array section of a solid-state imaging device according to the ninth embodiment.
　同図において、セル６２０は、ロウ方向およびカラム方向にマトリックス状に配置される。このとき、セル６２０を単位としてカーネル単位を設定してもよいし、各フォトダイオード１２１－１から１２１－４を単位としてカーネル単位を設定してもよい。 In the figure, the cells 620 are arranged in a matrix in the row and column directions. At this time, the kernel unit may be set with the cell 620 as a unit, or the kernel unit may be set with each of the photodiodes 121-1 to 121-4 as a unit.
　例えば、各カーネル単位において、各フォトダイオード１２１－１から１２１－４より個別に読出された画素信号に基づいてエッジ信号を生成し、セル６２０からビニングして読出された画素信号に基づいて低階調信号を生成してもよい。あるいは、各カーネル単位において、セル６２０からビニングして読出された画素信号に基づいてエッジ信号を生成し、セル６２０からビニングして読出された画素信号に基づいて低階調信号を生成してもよい。 For example, in each kernel unit, an edge signal may be generated based on pixel signals read out individually from each of photodiodes 121-1 to 121-4, and a low gradation signal may be generated based on pixel signals read out by binning from cell 620. Alternatively, in each kernel unit, an edge signal may be generated based on pixel signals read out by binning from cell 620, and a low gradation signal may be generated based on pixel signals read out by binning from cell 620.
　このように、上述の第９の実施の形態では、リセットトランジスタ１２３、増幅トランジスタ１２４、選択トランジスタ１２５およびビニングトランジスタ１２７を複数の画素で共有する。これにより、画素面積の増大を抑制しつつ、エッジ画像および階調画像の解像度を向上させることができる。 In this way, in the above-mentioned ninth embodiment, the reset transistor 123, the amplification transistor 124, the selection transistor 125, and the binning transistor 127 are shared by multiple pixels. This makes it possible to improve the resolution of edge images and gradation images while suppressing an increase in pixel area.
　＜１０．第１０の実施の形態＞
　上述の第１の実施の形態では、ロウ方向およびカラム方向に画素１２０同士を接続するビニング線１３３を設けた。この第１０の実施の形態では、画素信号をカラムごとに伝送する垂直信号線同士を接続することにより、カラムが互いに異なる画素１２０から読出された画素信号をビニングする。 <10. Tenth embodiment>
In the first embodiment described above, the binning lines 133 are provided to connect the pixels 120 to each other in the row and column directions. In the tenth embodiment, vertical signal lines that transmit pixel signals for each column are connected to each other, thereby binning pixel signals read out from the pixels 120 in different columns.
　図３６は、第１０の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 36 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the tenth embodiment.
　同図において、この固体撮像装置は、上述の第１の実施の形態のビニング線１３３に代えて、ビニング線１３３－１、１３３－２が設けられている。また、この固体撮像装置は、上述の第１の実施の形態の固体撮像装置に接続スイッチ６１１－１、６１１－２および水平接続線６０１が追加されている。また、この固体撮像装置は、上述の第１の実施の形態の画素１２０に代えて、セル６２０がロウ方向およびカラム方向にマトリックス状に配置されている。第１０の実施の形態の固体撮像装置のそれ以外の構成は、上述の第１の実施の形態の固体撮像装置の構成と同様である。 In the figure, this solid-state imaging device has binning lines 133-1 and 133-2 instead of the binning line 133 of the first embodiment described above. This solid-state imaging device also has connection switches 611-1 and 611-2 and a horizontal connection line 601 added to the solid-state imaging device of the first embodiment described above. This solid-state imaging device also has cells 620 arranged in a matrix in the row and column directions instead of the pixels 120 of the first embodiment described above. The rest of the configuration of the solid-state imaging device of the tenth embodiment is the same as the configuration of the solid-state imaging device of the first embodiment described above.
　各ビニング線１３３－１、１３３－２は、カラムごとに設けられる。各ビニング線１３３－１、１３３－２は、ロウが互いに異なる画素１２０から読出された画素信号をビニングする。 Each binning line 133-1, 133-2 is provided for each column. Each binning line 133-1, 133-2 bins pixel signals read from pixels 120 in different rows.
　接続スイッチ６１１－１、６１１－２は、互いに異なるカラムの垂直信号線１３２－１、１３２－２を接続する。接続スイッチ６１１－１は、垂直信号線１３２－１と水平接続線６０１との間に接続され、接続スイッチ６１１－２は、垂直信号線１３２－２と水平接続線６０１との間に接続される。各接続スイッチ６１１－１、６１１－２は、開閉信号ΦＣｎに基づいてオン／オフすることができる。 The connection switches 611-1 and 611-2 connect the vertical signal lines 132-1 and 132-2 of different columns. The connection switch 611-1 is connected between the vertical signal line 132-1 and the horizontal connection line 601, and the connection switch 611-2 is connected between the vertical signal line 132-2 and the horizontal connection line 601. Each of the connection switches 611-1 and 611-2 can be turned on/off based on the opening/closing signal ΦCn.
　図３７は、第１０の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。 FIG. 37 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by a solid-state imaging device according to the tenth embodiment.
　同図において、第１０の実施の形態のエッジ画像および低階調画像の生成では、非破壊読出しに基づいて、エッジ信号が生成された後（Ｐ６１）、低階調信号が生成される（Ｐ６２）。エッジ信号の生成では、エッジ信号の生成に用いられるセル６２０について、Ｐ相読出しが実施された後（Ｋ６１）、Ｄ相読出しが実施される（Ｋ６２）。低階調信号の生成では、各セル６２０について、Ｄ相読出しが実施された後（Ｋ６３）、Ｐ相読出しが実施される（Ｋ６４）。 In the figure, in generating an edge image and a low gradation image in the tenth embodiment, an edge signal is generated based on a non-destructive readout (P61), and then a low gradation signal is generated (P62). In generating an edge signal, a P-phase readout is performed (K61) for the cell 620 used to generate the edge signal, and then a D-phase readout is performed (K62). In generating a low gradation signal, a D-phase readout is performed (K63) for each cell 620, and then a P-phase readout is performed (K64).
　ここで、セル６２０に含まれる４個のフォトダイオード１２１－１から１２１－４から画素信号をビニングして読出されてもよい。このとき、セル６２０の転送トランジスタ１２２－１から１２２－４のゲートには、転送信号ＴＲＧ１～ＴＲＧ４として転送信号ＴＲＧが共通に印加される。 Here, pixel signals may be binned and read out from the four photodiodes 121-1 to 121-4 included in cell 620. At this time, a transfer signal TRG is commonly applied to the gates of transfer transistors 122-1 to 122-4 of cell 620 as transfer signals TRG1 to TRG4.
　第１０の実施の形態のエッジ画像および低階調画像の生成では、開閉信号ΦＣｎがロウレベルの時にエッジ信号が生成され（Ｐ６１）、開閉信号ΦＣｎがハイレベルの時に低階調信号が生成される（Ｐ６２）。この点を除いては、上述の第１の実施の形態のエッジ信号の生成（Ｐ１１）および低階調信号の生成（Ｐ１２）と同様である。 In the generation of edge images and low gradation images in the tenth embodiment, an edge signal is generated when the opening/closing signal ΦCn is at a low level (P61), and a low gradation signal is generated when the opening/closing signal ΦCn is at a high level (P62). Except for this point, the generation of the edge signal (P11) and the generation of the low gradation signal (P12) in the first embodiment described above are the same.
　ここで、低階調信号の生成（Ｐ６２）において、ビニング信号ＢＮＥが立ち上がることで、ビニングトランジスタ１２７はオンする。このとき、ロウが互いに異なる画素１２０から読出された画素信号が各ビニング線１３３－１、１３３－２を介してビニングされる。また、低階調信号の生成（Ｐ６２）において、開閉信号ΦＣｎが立ち上がることで、接続スイッチ６１１－１、６１１－２はオンする。このとき、カラムが互いに異なる画素１２０から読出された画素信号が水平接続線６０１を介してビニングされる。 Here, in generating the low gradation signal (P62), the binning signal BNE rises, turning on the binning transistor 127. At this time, pixel signals read out from pixels 120 in different rows are binned via the binning lines 133-1 and 133-2. Also, in generating the low gradation signal (P62), the opening/closing signal ΦCn rises, turning on the connection switches 611-1 and 611-2. At this time, pixel signals read out from pixels 120 in different columns are binned via the horizontal connection line 601.
　このように、上述の第１０の実施の形態では、画素信号をカラムごとに伝送する垂直信号線１３２－１、１３２－２同士を接続することにより、カラムが互いに異なる画素１２０から読出された画素信号をビニングする。これにより、カラムが互いに異なる画素１２０同士をビニング線１３３を介して接続する必要がなくなり、画素アレイ部１１１におけるビニング線１３３の配線領域を削減することができる。 In this way, in the above-mentioned tenth embodiment, the vertical signal lines 132-1, 132-2 that transmit pixel signals for each column are connected together, and pixel signals read from pixels 120 in different columns are binned. This eliminates the need to connect pixels 120 in different columns together via binning lines 133, and the wiring area for the binning lines 133 in the pixel array section 111 can be reduced.
　＜１１．第１１の実施の形態＞
　上述の第１０の実施の形態では、画素信号をカラムごとに伝送する垂直信号線１３２－１、１３２－２同士を接続することにより、カラムが互いに異なる画素１２０から読出された画素信号をビニングした。この第１１の実施の形態では、垂直信号線１３２－１、１３２－２に読出された画素信号をサンプルホールドしてビニングすることにより、カラムが互いに異なる画素１２０から読出された画素信号をビニングする。 11. Eleventh embodiment
In the above-described tenth embodiment, the vertical signal lines 132-1 and 132-2 that transmit pixel signals for each column are connected to each other, thereby binning pixel signals read from pixels 120 in different columns. In the eleventh embodiment, the pixel signals read from pixels 120 in different columns are binned by sampling and holding the pixel signals read to the vertical signal lines 132-1 and 132-2.
　図３８は、第１１の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 38 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the eleventh embodiment.
　同図において、この固体撮像装置は、上述の第１０の実施の形態の固体撮像装置にサンプルホールドスイッチ６２１－１、６２１－２および容量６３１－１、６３１－２が追加されている。第１１の実施の形態の固体撮像装置のそれ以外の構成は、上述の第１の実施の形態の固体撮像装置の構成と同様である。 In the figure, this solid-state imaging device is the same as the solid-state imaging device of the tenth embodiment described above, except that sample-and-hold switches 621-1 and 621-2 and capacitors 631-1 and 631-2 have been added. The rest of the configuration of the solid-state imaging device of the eleventh embodiment is the same as the configuration of the solid-state imaging device of the first embodiment described above.
　サンプルホールドスイッチ６２１－１および容量６３１－１は、垂直信号線１３２－１に読出された画素信号をサンプルホールドする。サンプルホールドスイッチ６２１－２および容量６３１－２は、垂直信号線１３２－２に読出された画素信号をサンプルホールドする。サンプルホールドスイッチ６２１－１は、容量６３１－１と、垂直信号線１３２－１との間に接続され、サンプルホールドスイッチ６２１－２は、容量６３１－２と、垂直信号線１３２－２との間に接続される。各サンプルホールドスイッチ６２１－１、６２１－２は、サンプルホールド信号ＳＨＥに基づいてオン／オフすることができる。接続スイッチ６１１－１は、サンプルホールドスイッチ６２１－１と水平接続線６０１との間に接続され、接続スイッチ６１１－２は、サンプルホールドスイッチ６２１－２と水平接続線６０１との間に接続される。 The sample and hold switch 621-1 and the capacitor 631-1 sample and hold the pixel signal read out to the vertical signal line 132-1. The sample and hold switch 621-2 and the capacitor 631-2 sample and hold the pixel signal read out to the vertical signal line 132-2. The sample and hold switch 621-1 is connected between the capacitor 631-1 and the vertical signal line 132-1, and the sample and hold switch 621-2 is connected between the capacitor 631-2 and the vertical signal line 132-2. Each of the sample and hold switches 621-1 and 621-2 can be turned on/off based on the sample and hold signal SHE. The connection switch 611-1 is connected between the sample and hold switch 621-1 and the horizontal connection line 601, and the connection switch 611-2 is connected between the sample and hold switch 621-2 and the horizontal connection line 601.
　図３９は、第１１の実施の形態に係る固体撮像装置によるエッジ画像および低階調画像の生成時の各部の波形の一例を示すタイミングチャートである。 FIG. 39 is a timing chart showing an example of waveforms at various parts when an edge image and a low-tone image are generated by a solid-state imaging device according to the eleventh embodiment.
　同図において、第１１の実施の形態のエッジ画像および低階調画像の生成では、非破壊読出しに基づいて、エッジ信号が生成された後（Ｐ７１）、低階調信号が生成される（Ｐ７２）。エッジ信号の生成では、エッジ信号の生成に用いられるセル６２０について、Ｐ相読出しが実施された後（Ｋ７１）、Ｄ相読出しが実施される（Ｋ７２）。低階調信号の生成では、各セル６２０について、Ｄ相読出しが実施された後（Ｋ７３）、Ｐ相読出しが実施される（Ｋ７４）。 In the figure, in generating an edge image and a low gradation image in the eleventh embodiment, an edge signal is generated based on a non-destructive readout (P71), and then a low gradation signal is generated (P72). In generating an edge signal, a P-phase readout is performed (K71) for the cell 620 used to generate the edge signal, and then a D-phase readout is performed (K72). In generating a low gradation signal, a D-phase readout is performed (K73) for each cell 620, and then a P-phase readout is performed (K74).
　ここで、セル６２０に含まれる４個のフォトダイオード１２１－１から１２１－４から画素信号をビニングして読出されてもよい。このとき、セル６２０の転送トランジスタ１２２－１から１２２－４のゲートには、転送信号ＴＲＧ１～ＴＲＧ４として転送信号ＴＲＧが共通に印加される。 Here, pixel signals may be binned and read out from the four photodiodes 121-1 to 121-4 included in cell 620. At this time, a transfer signal TRG is commonly applied to the gates of transfer transistors 122-1 to 122-4 of cell 620 as transfer signals TRG1 to TRG4.
　第１１の実施の形態の低階調画像の生成（Ｐ７２）では、ビニング信号ＢＮＥが立ち上がることで、ビニングトランジスタ１２７はオンする。このとき、ロウが互いに異なる画素１２０から読出された画素信号が各ビニング線１３３－１、１３３－２を介してビニングされる。また、リセット信号ＲＳＴが立ち上がる前に、サンプルホールド信号ＳＨＥが立ち上がることにより（ｔ１６）、サンプルホールドスイッチ６２１－１、６２１－２がオンされる。このとき、各垂直信号線１３２－１、１３２－２に読出された信号レベルの画素信号が容量６３１－１、６３１－２にそれぞれサンプルホールドされる。そして、サンプルホールド信号ＳＨＥが立ち下がった後、開閉信号ΦＣｎが立ち上がり、接続スイッチ６１１－１、６１１－２はオンする。このとき、容量６３１－１、６３１－２にそれぞれサンプルホールドされた信号レベルの画素信号が水平接続線６０１を介してビニングされることで、カラムが互いに異なる画素１２０から読出された信号レベルの画素信号がビニングされる（ｔ１７）。 In the generation of a low-tone image (P72) in the eleventh embodiment, the binning signal BNE rises, turning on the binning transistor 127. At this time, pixel signals read out from pixels 120 in different rows are binned via the binning lines 133-1 and 133-2. In addition, before the reset signal RST rises, the sample and hold signal SHE rises (t16), turning on the sample and hold switches 621-1 and 621-2. At this time, the pixel signals of the signal levels read out to the vertical signal lines 132-1 and 132-2 are sampled and held in the capacitors 631-1 and 631-2, respectively. Then, after the sample and hold signal SHE falls, the open/close signal ΦCn rises, turning on the connection switches 611-1 and 611-2. At this time, the pixel signals with the signal levels sampled and held in the capacitors 631-1 and 631-2 are binned via the horizontal connection line 601, and the pixel signals with the signal levels read out from the pixels 120 in different columns are binned (t17).
　次に、リセット信号ＲＳＴが立ち上がることにより（ｔ１８）、リセットトランジスタ１２３がオンしてフローティングディフュージョン１２６がリセットされる。このとき、サンプルホールド信号ＳＨＥが立ち上がることにより（ｔ１８）、サンプルホールドスイッチ６２１－１、６２１－２がオンされる。そして、各垂直信号線１３２－１、１３２－２に読出されたリセットレベルの画素信号が容量６３１－１、６３１－２にそれぞれサンプルホールドされる。そして、リセット信号ＲＳＴが立ち下がった後、サンプルホールド信号ＳＨＥが立ち下がる。そして、開閉信号ΦＣｎが立ち上がり、接続スイッチ６１１－１、６１１－２はオンする。このとき、容量６３１－１、６３１－２にそれぞれサンプルホールドされたリセットレベルの画素信号が水平接続線６０１を介してビニングされることで、カラムが互いに異なる画素１２０から読出されたリセットレベルの画素信号がビニングされる（ｔ１９）。 Next, the reset signal RST rises (t18), turning on the reset transistor 123 and resetting the floating diffusion 126. At this time, the sample and hold signal SHE rises (t18), turning on the sample and hold switches 621-1 and 621-2. The reset level pixel signals read out to the vertical signal lines 132-1 and 132-2 are sampled and held in the capacitors 631-1 and 631-2, respectively. After the reset signal RST falls, the sample and hold signal SHE falls. Then, the open/close signal ΦCn rises, turning on the connection switches 611-1 and 611-2. At this time, the reset level pixel signals sampled and held in the capacitors 631-1 and 631-2 are binned via the horizontal connection line 601, and the reset level pixel signals read out from the pixels 120 in different columns are binned (t19).
　以上の点を除いては、第１１の実施の形態のエッジ信号の生成（Ｐ７１）および低階調画像の生成（Ｐ７２）は、上述の第１の実施の形態のエッジ信号の生成（Ｐ１１）および低階調信号の生成（Ｐ１２）と同様である。 Apart from the above, the generation of the edge signal (P71) and the generation of the low gradation image (P72) in the eleventh embodiment are similar to the generation of the edge signal (P11) and the generation of the low gradation signal (P12) in the first embodiment described above.
　このように、上述の第１１の実施の形態では、垂直信号線１３２－１、１３２－２に読出された画素信号をサンプルホールドしてビニングすることにより、カラムが互いに異なる画素１２０から読出された画素信号をビニングする。これにより、カラムが互いに異なる画素１２０同士を、ビニング線１３３を介して接続する必要がなくなり、画素アレイ部１１１におけるビニング線１３３の配線領域を削減することができる。 In this way, in the above-described eleventh embodiment, pixel signals read out from pixels 120 in different columns are binned by sampling and holding the pixel signals read out to the vertical signal lines 132-1 and 132-2. This eliminates the need to connect pixels 120 in different columns via binning lines 133, and the wiring area for the binning lines 133 in the pixel array section 111 can be reduced.
　＜１２．第１２の実施の形態＞
　上述の第１の実施の形態では、エッジ画像の生成と低階調画像の生成とでＡＤ変換部１４５を共有し、エッジ画像の生成時にはＡＤ変換部をエッジＡＤＣとして動作させ、低階調画像の生成時にはＡＤ変換部をフラッシュＡＤＣとして動作させた。この第１２の実施の形態では、エッジ画像の生成と低階調画像の生成とでＡＤ変換部を分ける。 <12. Twelfth embodiment>
In the first embodiment described above, the AD conversion unit 145 is shared between edge image generation and low gradation image generation, and the AD conversion unit operates as an edge ADC when generating edge images and as a flash ADC when generating low gradation images. In this twelfth embodiment, the AD conversion unit is divided between edge image generation and low gradation image generation.
　図４０は、第１２の実施の形態に係る固体撮像装置の構成例を示すブロック図である。 FIG. 40 is a block diagram showing an example of the configuration of a solid-state imaging device according to the twelfth embodiment.
　同図において、この固体撮像装置７０２は、上述の第１の実施の形態の固体撮像装置１０２のカラム読出し回路１１３、カラム信号処理部１１４および制御回路１１６に代えて、カラム読出し回路７１３、カラム信号処理部７１４および制御回路７１６を備える。第１２の実施の形態の固体撮像装置７０２のそれ以外の構成は、上述の第１の実施の形態の固体撮像装置１０２の構成と同様である。 In the figure, this solid-state imaging device 702 has a column readout circuit 713, a column signal processing unit 714, and a control circuit 716 instead of the column readout circuit 113, the column signal processing unit 114, and the control circuit 116 of the solid-state imaging device 102 of the first embodiment described above. The rest of the configuration of the solid-state imaging device 702 of the 12th embodiment is the same as the configuration of the solid-state imaging device 102 of the first embodiment described above.
　カラム読出し回路７１３は、畳み込み処理されるカーネル単位で画素から画素信号を読出すことができる。カラム読出し回路７１３は、各画素１２０からの信号の読出し時に、各画素１２０との間でソースフォロワを構成してもよい。 The column readout circuit 713 can read out pixel signals from the pixels in units of kernels to be convolved. The column readout circuit 713 may configure a source follower between each pixel 120 when reading out a signal from each pixel 120.
　カラム信号処理部７１４は、各画素１２０からカラム方向に伝送された信号を処理する。このとき、カラム信号処理部７１４は、各画素１２０からカラム方向に伝送された信号に基づいて、ＡＤ変換処理を実施し、エッジ信号Ｇ１、低階調信号Ｇ２および高階調信号Ｇ３を出力することができる。カラム信号処理部７１４は、ＡＤ変換部７１７、７１８を備える。ＡＤ変換部７１７は、エッジ画像Ｇ１の生成に用いられる。ＡＤ変換部７１８は、低階調画像Ｇ２および高階調画像Ｇ３の生成に用いられる。 The column signal processing unit 714 processes signals transmitted in the column direction from each pixel 120. At this time, the column signal processing unit 714 performs AD conversion processing based on the signals transmitted in the column direction from each pixel 120, and can output an edge signal G1, a low gradation signal G2, and a high gradation signal G3. The column signal processing unit 714 includes AD conversion units 717 and 718. The AD conversion unit 717 is used to generate the edge image G1. The AD conversion unit 718 is used to generate the low gradation image G2 and the high gradation image G3.
　制御回路７１６は、垂直走査回路１１２、カラム読出し回路７１３、カラム信号処理部７１４および水平走査回路１１５を制御する。制御回路７１６は、エッジ画像Ｇ１の生成時にＡＤ変換部７１７に画素信号が入力され、低階調画像Ｇ２および高階調画像Ｇ３の生成時にＡＤ変換部７１８に画素信号が入力されるように制御する。これ以外の制御回路７１６の制御は、上述の第１の実施の形態の制御回路１１６の制御と同様である。 The control circuit 716 controls the vertical scanning circuit 112, the column readout circuit 713, the column signal processing unit 714, and the horizontal scanning circuit 115. The control circuit 716 controls so that a pixel signal is input to the AD conversion unit 717 when the edge image G1 is generated, and so that a pixel signal is input to the AD conversion unit 718 when the low gradation image G2 and the high gradation image G3 are generated. Other than this, the control of the control circuit 716 is similar to the control of the control circuit 116 in the first embodiment described above.
　図４１は、第１２の実施の形態に係る固体撮像装置によるエッジ画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 41 is a block diagram showing an example of switching of signal paths when an edge image is generated by a solid-state imaging device according to the twelfth embodiment.
　同図において、カラム読出し回路７１３は、上述の第１の実施の形態のカラム読出し回路１１３のマルチプレクサ１６１に代えて、マルチプレクサ７６１を備える。また、カラム読出し回路７１３は、上述の第１の実施の形態のカラム読出し回路１１３から、セレクタ２７１－１から２７１－４が省略されている。第１２の実施の形態のカラム読出し回路７１３のそれ以外の構成は、上述の第１の実施の形態のカラム読出し回路１１３の構成と同様である。 In the figure, the column read circuit 713 has a multiplexer 761 instead of the multiplexer 161 of the column read circuit 113 of the first embodiment described above. In addition, the column read circuit 713 omits the selectors 271-1 to 271-4 from the column read circuit 113 of the first embodiment described above. The rest of the configuration of the column read circuit 713 of the twelfth embodiment is the same as the configuration of the column read circuit 113 of the first embodiment described above.
　マルチプレクサ７６１は、エッジ信号の生成において、各垂直信号線１３２－１、１３２－２と各コンパレータ１７１－１から１７１－４の入力との接続をカーネル単位で切り替える。また、マルチプレクサ７６１は、低階調信号の生成と高階調信号の生成とにおいて、各垂直信号線１３２－１、１３２－２と各コンパレータ７７１－１から７７１－４の入力との接続をカーネル単位で切り替える。このとき、マルチプレクサ７６１は、エッジ信号の生成時には、２つの画素からの画素信号が互いに異なる組み合わせで各コンパレータ１７１－１から１７１－４に入力されるように各垂直信号線１３２－１、１３２－２と各コンパレータ１７１－１から１７１－４の入力との接続を切り替えることができる。また、マルチプレクサ７６１は、低階調信号の生成時には、カーネル単位で読出された画素信号と、レベル信号ＶＦ１からＶＦ４とが各コンパレータ７７１－１から７７１－４に入力されるように各垂直信号線１３２－１、１３２－２と各コンパレータ７７１－１から７７１－４の入力との接続を切り替えることができる。また、マルチプレクサ７６１は、高階調信号の生成時には、画素単位で読出された画素信号と、ランプ信号ＲＡＰとが各コンパレータ７７１－１から７７１－４に入力されるように各垂直信号線１３２－１、１３２－２と各コンパレータ７７１－１から７７１－４の入力との接続を切り替えることができる。 When generating an edge signal, the multiplexer 761 switches the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 on a kernel-by-kernel basis. In addition, when generating a low gradation signal and a high gradation signal, the multiplexer 761 switches the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 771-1 to 771-4 on a kernel-by-kernel basis. At this time, the multiplexer 761 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 171-1 to 171-4 so that pixel signals from two pixels are input to each of the comparators 171-1 to 171-4 in different combinations when generating an edge signal. In addition, when generating a low gradation signal, the multiplexer 761 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 771-1 to 771-4 so that the pixel signal read out on a kernel-by-kernel basis and the level signals VF1 to VF4 are input to each of the comparators 771-1 to 771-4. In addition, when generating a high gradation signal, the multiplexer 761 can switch the connection between each of the vertical signal lines 132-1, 132-2 and the inputs of each of the comparators 771-1 to 771-4 so that the pixel signal read out on a pixel-by-pixel basis and the ramp signal RAP are input to each of the comparators 771-1 to 771-4.
　マルチプレクサ７６１は、スイッチ７６１－１から７６１－４を備える。各スイッチ７６１－１から７６１－４は、カラムごとに設けられる。各スイッチ７６１－１から７６１－４の入力端子は、垂直信号線１３２－１、１３２－２ごとに設けられる。各スイッチ７６１－１から７６１－４の第１出力端子は、各コンパレータ１７１－１から１７１－４の反転入力端子に接続される。各スイッチ７６１－１から７６１－４の第２出力端子は、各コンパレータ７７１－１から７７１－４の反転入力端子に接続される。第１２の実施の形態のカラム読出し回路７１３のそれ以外の構成は、上述の第１の実施の形態のカラム読出し回路１１３の構成と同様である。 The multiplexer 761 includes switches 761-1 to 761-4. Each of the switches 761-1 to 761-4 is provided for each column. The input terminals of each of the switches 761-1 to 761-4 are provided for each of the vertical signal lines 132-1 and 132-2. The first output terminals of each of the switches 761-1 to 761-4 are connected to the inverting input terminals of each of the comparators 171-1 to 171-4. The second output terminals of each of the switches 761-1 to 761-4 are connected to the inverting input terminals of each of the comparators 771-1 to 771-4. The rest of the configuration of the column readout circuit 713 of the twelfth embodiment is the same as the configuration of the column readout circuit 113 of the first embodiment described above.
　カラム信号処理部７１４は、上述の第１の実施の形態のカラム信号処理部１１４にコンパレータ７７１－１から７７１－４、インバータ７８１－１から７８１－４およびＮＡＮＤ回路７９１－１から７９１－４が追加されている。第１２の実施の形態のカラム信号処理部７１４のそれ以外の構成は、上述の第１の実施の形態のカラム信号処理部１１４の構成と同様である。 The column signal processing unit 714 is obtained by adding comparators 771-1 to 771-4, inverters 781-1 to 781-4, and NAND circuits 791-1 to 791-4 to the column signal processing unit 114 of the first embodiment described above. The rest of the configuration of the column signal processing unit 714 of the 12th embodiment is the same as the configuration of the column signal processing unit 114 of the first embodiment described above.
　コンパレータ７７１－１から７７１－４は、カラムごとに設けられる。コンパレータ７７１－１は、レベル信号ＶＦ１とスイッチ７６１－１を介して出力される画素信号とを比較する。コンパレータ７７１－２は、レベル信号ＶＦ２とスイッチ７６１－２を介して出力される画素信号とを比較する。コンパレータ７７１－３は、レベル信号ＶＦ３とスイッチ７６１－３を介して出力される画素信号とを比較する。コンパレータ７７１－４は、レベル信号ＶＦ４とスイッチ７６１－４を介して出力される画素信号とを比較する。 Comparators 771-1 to 771-4 are provided for each column. Comparator 771-1 compares level signal VF1 with the pixel signal output via switch 761-1. Comparator 771-2 compares level signal VF2 with the pixel signal output via switch 761-2. Comparator 771-3 compares level signal VF3 with the pixel signal output via switch 761-3. Comparator 771-4 compares level signal VF4 with the pixel signal output via switch 761-4.
　インバータ７８１－１は、コンパレータ７７１－１の出力を反転してＮＡＮＤ回路７９１－１に入力する。インバータ７８１－２は、コンパレータ７７１－２の出力を反転してＮＡＮＤ回路７９１－２に入力する。インバータ７８１－３は、コンパレータ７７１－３の出力を反転してＮＡＮＤ回路７９１－３に入力する。インバータ７８１－４は、コンパレータ７７１－４の出力を反転してＮＡＮＤ回路７９１－４に入力する。 Inverter 781-1 inverts the output of comparator 771-1 and inputs it to NAND circuit 791-1. Inverter 781-2 inverts the output of comparator 771-2 and inputs it to NAND circuit 791-2. Inverter 781-3 inverts the output of comparator 771-3 and inputs it to NAND circuit 791-3. Inverter 781-4 inverts the output of comparator 771-4 and inputs it to NAND circuit 791-4.
　ＮＡＮＤ回路７９１－１は、インバータ７８１－１の出力と出力イネーブル信号ＶＯＥとの否定論理積を演算する。ＮＡＮＤ回路７９１－２は、インバータ７８１－２の出力と出力イネーブル信号ＶＯＥとの否定論理積を演算する。ＮＡＮＤ回路７９１－３は、インバータ７８１－３の出力と出力イネーブル信号ＶＯＥとの否定論理積を演算する。ＮＡＮＤ回路７９１－４は、インバータ７８１－４の出力と出力イネーブル信号ＶＯＥとの否定論理積を演算する。 NAND circuit 791-1 calculates the NAND of the output of inverter 781-1 and the output enable signal VOE. NAND circuit 791-2 calculates the NAND of the output of inverter 781-2 and the output enable signal VOE. NAND circuit 791-3 calculates the NAND of the output of inverter 781-3 and the output enable signal VOE. NAND circuit 791-4 calculates the NAND of the output of inverter 781-4 and the output enable signal VOE.
　なお、図４１の例では、各コンパレータ１７１－１から１７１－４および７７１－１から７７１－４に接続されるＤＣカットコンデンサは省略して示した。 Note that in the example of Figure 41, the DC blocking capacitors connected to each of the comparators 171-1 to 171-4 and 771-1 to 771-4 are omitted.
　ここで、固体撮像装置は、エッジ画像を生成するものとする。このとき、カーネル単位に含まれる１６個の画素１２０のうち４個の各画素１２０－１から１２０－４において、選択トランジスタ１２５がオンされ、ビニングトランジスタ１２７はオフされる。カーネル単位に含まれる４個の各画素１２０－１から１２０－４以外の１２個の画素１２０において、選択トランジスタ１２５およびビニングトランジスタ１２７はオフされる。 Here, the solid-state imaging device generates an edge image. At this time, in each of four pixels 120-1 to 120-4 out of the 16 pixels 120 included in the kernel unit, the selection transistor 125 is turned on and the binning transistor 127 is turned off. In the remaining 12 pixels 120 other than the four pixels 120-1 to 120-4 included in the kernel unit, the selection transistor 125 and the binning transistor 127 are turned off.
　また、画素１２０－１が接続された垂直信号線１３２－１は、スイッチ７６１－１を介してコンパレータ１７１－１に接続される。画素１２０－４が接続された垂直信号線１３２－１は、スイッチ７６１－２を介してコンパレータ１７１－２に接続される。画素１２０－３が接続された垂直信号線１３２－２は、スイッチ７６１－４を介してコンパレータ１７１－４に接続される。画素１２０－４が接続された垂直信号線７３２－２は、スイッチ１６１－３を介してコンパレータ１７１－３に接続される。 Also, the vertical signal line 132-1 to which the pixel 120-1 is connected is connected to the comparator 171-1 via the switch 761-1. The vertical signal line 132-1 to which the pixel 120-4 is connected is connected to the comparator 171-2 via the switch 761-2. The vertical signal line 132-2 to which the pixel 120-3 is connected is connected to the comparator 171-4 via the switch 761-4. The vertical signal line 732-2 to which the pixel 120-4 is connected is connected to the comparator 171-3 via the switch 161-3.
　さらに、画素１２０－１が接続された垂直信号線１３２－１は、スイッチ７６１－１、２６１－１を介してゲイン部２８１－３に接続される。画素１２０－４が接続された垂直信号線１３２－１は、スイッチ７６１－２、２６１－２を介してゲイン部２８１－４に接続される。画素１２０－３が接続された垂直信号線１３２－２は、スイッチ７６１－４、２６１－４を介してゲイン部２８１－２に接続される。画素１２０－２が接続された垂直信号線１３２－２は、スイッチ７６１－３、２６１－３を介してゲイン部２８１－１に接続される。 Furthermore, the vertical signal line 132-1 to which the pixel 120-1 is connected is connected to the gain section 281-3 via switches 761-1 and 261-1. The vertical signal line 132-1 to which the pixel 120-4 is connected is connected to the gain section 281-4 via switches 761-2 and 261-2. The vertical signal line 132-2 to which the pixel 120-3 is connected is connected to the gain section 281-2 via switches 761-4 and 261-4. The vertical signal line 132-2 to which the pixel 120-2 is connected is connected to the gain section 281-1 via switches 761-3 and 261-3.
　図４２は、第１２の実施の形態に係る固体撮像装置による低階調画像の生成時の信号経路の切替例を示すブロック図である。 FIG. 42 is a block diagram showing an example of signal path switching when a low-tone image is generated by a solid-state imaging device according to the twelfth embodiment.
　同図において、固体撮像装置は、低階調画像を生成するものとする。このとき、カーネル単位に含まれる１６個の画素１２０において、選択トランジスタ１２５およびビニングトランジスタ１２７はオンされる。 In the figure, the solid-state imaging device generates a low-tone image. At this time, the selection transistors 125 and binning transistors 127 are turned on in the 16 pixels 120 included in the kernel unit.
　また、カーネル単位に含まれるｍ列目の画素１２０が接続された垂直信号線１３２－１、１３２－２は、スイッチ７６１－１を介してコンパレータ７７１－１に接続される。カーネル単位に含まれるｍ＋１列目の画素１２０が接続された垂直信号線１３２－１、１３２－２は、スイッチ７６１－２を介してコンパレータ７７１－２に接続される。カーネル単位に含まれるｍ＋２列目の画素１２０が接続された垂直信号線１３２－１、１３２－２は、スイッチ７６１－３を介してコンパレータ７７１－３に接続される。カーネル単位に含まれるｍ＋３列目の画素１２０が接続された垂直信号線１３２－１、１３２－２は、スイッチ７６１－４を介してコンパレータ７７１－４に接続される。 The vertical signal lines 132-1 and 132-2 to which the pixels 120 in the mth column included in the kernel unit are connected are connected to the comparator 771-1 via the switch 761-1. The vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+1th column included in the kernel unit are connected are connected to the comparator 771-2 via the switch 761-2. The vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+2th column included in the kernel unit are connected are connected to the comparator 771-3 via the switch 761-3. The vertical signal lines 132-1 and 132-2 to which the pixels 120 in the m+3th column included in the kernel unit are connected are connected to the comparator 771-4 via the switch 761-4.
　さらに、各レベル信号ＶＦ１からＶＦ４は、コンパレータ７７１－１から７７１－４の反転入力端子にそれぞれ入力される。このとき、各コンパレータ７７１－１から７７１－４の比較結果ＶＯＢ１からＶＯＢ４は、各インバータ７８１－１から７８１－４およびＮＡＮＤ回路７９１－１から７９１－４をそれぞれ介して低階調信号として出力される。 Furthermore, each of the level signals VF1 to VF4 is input to the inverting input terminal of each of the comparators 771-1 to 771-4. At this time, the comparison results VOB1 to VOB4 of each of the comparators 771-1 to 771-4 are output as low gradation signals via each of the inverters 781-1 to 781-4 and the NAND circuits 791-1 to 791-4.
　このように、上述の第１２の実施の形態では、エッジ画像Ｇ１の生成に用いられるＡＤ変換部７１７と、低階調画像Ｇ２および高階調画像Ｇ３の生成に用いられるＡＤ変換部７１８とを設ける。これにより、各コンパレータ１７１－１から１７１－４への入力を切り替えるセレクタ２７１－１から２７１－４を不要とすることができる。 In this way, in the above-mentioned twelfth embodiment, an AD conversion unit 717 is provided for generating the edge image G1, and an AD conversion unit 718 is provided for generating the low gradation image G2 and the high gradation image G3. This makes it possible to eliminate the need for the selectors 271-1 to 271-4 that switch the inputs to the comparators 171-1 to 171-4.
　＜１３．第１３の実施の形態＞
　上述の第１の実施の形態では、エッジ画像の生成と低階調画像の生成とでＡＤ変換部を共有し、エッジ画像の生成時にはＡＤ変換部をエッジＡＤＣとして動作させ、低階調画像の生成時にはＡＤ変換部をフラッシュＡＤＣとして動作させた。この第１３の実施の形態では、エッジ画像の生成と低階調画像の生成とでＡＤ変換部を分けた上で、低階調画像の生成に用いられるＡＤ変換部を逐次比較型ＡＤ変換部とする。 <13. Thirteenth embodiment>
In the first embodiment described above, the AD conversion unit is shared between edge image generation and low gradation image generation, and the AD conversion unit operates as an edge ADC when generating edge images and operates as a flash ADC when generating low gradation images. In this thirteenth embodiment, the AD conversion unit is divided between edge image generation and low gradation image generation, and the AD conversion unit used for low gradation image generation is a successive approximation type AD conversion unit.
　図４３は、第１３の実施の形態に係る固体撮像装置の構成例を示すブロック図である。 FIG. 43 is a block diagram showing an example of the configuration of a solid-state imaging device according to the thirteenth embodiment.
　同図において、この固体撮像装置８０２は、上述の第１の実施の形態の固体撮像装置１０２のカラム読出し回路１１３、カラム信号処理部１１４および制御回路１１６に代えて、カラム読出し回路８１３、カラム信号処理部８１４および制御回路８１６を備える。また、固体撮像装置８０２は、上述の第１の実施の形態の固体撮像装置１０２にマルチプレクサ８１７およびＡＤ変換部８１８が追加されている。第１３の実施の形態の固体撮像装置８０２のそれ以外の構成は、上述の第１の実施の形態の固体撮像装置１０２の構成と同様である。 In the figure, this solid-state imaging device 802 has a column readout circuit 813, a column signal processing unit 814, and a control circuit 816 instead of the column readout circuit 113, the column signal processing unit 114, and the control circuit 116 of the solid-state imaging device 102 of the first embodiment described above. In addition, the solid-state imaging device 802 has a multiplexer 817 and an AD conversion unit 818 added to the solid-state imaging device 102 of the first embodiment described above. The rest of the configuration of the solid-state imaging device 802 of the thirteenth embodiment is the same as the configuration of the solid-state imaging device 102 of the first embodiment described above.
　カラム読出し回路８１３は、畳み込み処理されるカーネル単位で画素から画素信号を読出すことができる。カラム読出し回路８１３は、各画素１２０からの信号の読出し時に、各画素１２０との間でソースフォロワを構成してもよい。 The column readout circuit 813 can read out pixel signals from the pixels in units of kernels to be convolved. The column readout circuit 813 may configure a source follower between each pixel 120 when reading out a signal from each pixel 120.
　カラム信号処理部８１４は、各画素１２０からカラム方向に伝送された信号を処理する。このとき、カラム信号処理部８１４は、各画素１２０からカラム方向に伝送された信号に基づいて、ＡＤ変換処理を実施し、エッジ信号Ｇ１および高階調信号Ｇ３を出力することができる。カラム信号処理部８１４は、ＡＤ変換部８１５を備える。ＡＤ変換部８１５は、エッジ画像Ｇ１および高階調画像Ｇ３の生成に用いられる。 The column signal processing unit 814 processes signals transmitted in the column direction from each pixel 120. At this time, the column signal processing unit 814 performs AD conversion processing based on the signals transmitted in the column direction from each pixel 120, and can output an edge signal G1 and a high gradation signal G3. The column signal processing unit 814 includes an AD conversion unit 815. The AD conversion unit 815 is used to generate the edge image G1 and the high gradation image G3.
　制御回路８１６は、垂直走査回路１１２、カラム読出し回路７１３、カラム信号処理部７１４、水平走査回路１１５、マルチプレクサ８１７およびＡＤ変換部８１８を制御する。制御回路８１６は、エッジ画像Ｇ１および高階調画像Ｇ３の生成時にＡＤ変換部８１５に画素信号が入力され、低階調画像Ｇ２の生成時にＡＤ変換部８１８に画素信号が入力されるように制御する。これ以外の制御回路８１６の制御は、上述の第１の実施の形態の制御回路１１６の制御と同様である。 The control circuit 816 controls the vertical scanning circuit 112, the column readout circuit 713, the column signal processing unit 714, the horizontal scanning circuit 115, the multiplexer 817, and the AD conversion unit 818. The control circuit 816 controls so that pixel signals are input to the AD conversion unit 815 when the edge image G1 and the high gradation image G3 are generated, and so that pixel signals are input to the AD conversion unit 818 when the low gradation image G2 is generated. Other than this, the control of the control circuit 816 is similar to the control of the control circuit 116 in the first embodiment described above.
　マルチプレクサ８１７は、各画素１２０から垂直信号線１３２に読み出された画素信号をＡＤ変換部８１８に入力する。このとき、マルチプレクサ８１７は、ＡＤ変換部８１８と垂直信号線１３２との接続をカーネル単位で切り替えることができる。 The multiplexer 817 inputs the pixel signals read out from each pixel 120 to the vertical signal line 132 to the AD conversion unit 818. At this time, the multiplexer 817 can switch the connection between the AD conversion unit 818 and the vertical signal line 132 on a kernel-by-kernel basis.
　ＡＤ変換部８１８は、低階調画像Ｇ２の生成に用いられる。ＡＤ変換部８１８は、逐次比較型ＡＤ変換部でもよい。このとき、ＡＤ変換部８１８は、マルチプレクサ８１７からカーネル単位で出力された画素信号をＡＤ変換し、制御回路８１６に出力することができる。このとき、露光制御部１５２は、ＡＤ変換部８１８から出力された低階調信号Ｇ２に基づいて、露光制御を実施することができる。 The AD conversion unit 818 is used to generate the low gradation image G2. The AD conversion unit 818 may be a successive approximation type AD conversion unit. At this time, the AD conversion unit 818 can AD convert the pixel signal output from the multiplexer 817 on a kernel-by-kernel basis and output it to the control circuit 816. At this time, the exposure control unit 152 can perform exposure control based on the low gradation signal G2 output from the AD conversion unit 818.
　このように、上述の第１３の実施の形態では、エッジ画像の生成と低階調画像の生成とでＡＤ変換部を分けた上で、低階調画像の生成に用いられるＡＤ変換部を逐次比較型ＡＤ変換部とする。これにより、各コンパレータ１７１－１から１７１－４への入力を切り替えるセレクタ２７１－１から２７１－４を不要とすることが可能となるとともに、低階調画像の生成に用いられるコンパレータの個数を削減することができる。 In this way, in the thirteenth embodiment described above, the AD conversion unit is divided into one for generating edge images and one for generating low gradation images, and the AD conversion unit used for generating low gradation images is a successive approximation type AD conversion unit. This makes it possible to eliminate the need for selectors 271-1 to 271-4 that switch the inputs to each of comparators 171-1 to 171-4, and also reduces the number of comparators used for generating low gradation images.
　＜１４．第１４の実施の形態＞
　上述の第１の実施の形態では、４×４画素のカーネル単位に基づいてエッジ画像および低階調画像を生成した。この第１４の実施の形態では、画素１２０がマトリックス状に配列された画素アレイ部１１１が設けられた固体撮像装置が形成される基板を積層化する。 <14. Fourteenth embodiment>
In the first embodiment described above, an edge image and a low gradation image are generated based on a kernel unit of 4 × 4 pixels. In this fourteenth embodiment, substrates on which a solid-state imaging device is formed, the solid-state imaging device including a pixel array section 111 in which pixels 120 are arranged in a matrix, are laminated.
　図４４は、第１４の実施の形態に係る撮像装置の構成例を示す斜視図である。 FIG. 44 is a perspective view showing an example configuration of an imaging device according to the fourteenth embodiment.
　同図におけるａにおいて、固体撮像装置９０１は、支持基板９１１および半導体基板９１２を備える。半導体基板９１２は、支持基板９１１上に積層されている。半導体基板９１２には、画素アレイ部９１３および周辺回路９１４が形成される。周辺回路９１４には、カラム読出し回路９１５およびカラムＡＤＣ９１６が形成される。カラム読出し回路９１５およびカラムＡＤＣ９１６は、画素アレイ部９１３のカラム方向の両側に形成してもよい。 In FIG. 9A, the solid-state imaging device 901 includes a support substrate 911 and a semiconductor substrate 912. The semiconductor substrate 912 is stacked on the support substrate 911. A pixel array section 913 and a peripheral circuit 914 are formed on the semiconductor substrate 912. A column readout circuit 915 and a column ADC 916 are formed on the peripheral circuit 914. The column readout circuit 915 and the column ADC 916 may be formed on both sides of the pixel array section 913 in the column direction.
　画素アレイ部９１３には、ロウ方向およびカラム方向に沿ってマトリックス状に画素１２０が配列される。カラム読出し回路９１５は、定電流読出しに基づいて各画素１２０から個別に信号を読出したり、ビニングして読出したりすることができる。カラムＡＤＣ９１６は、カラム読出し回路９１５を介して読み出された信号をカラムごとにＡＤ変換することができる。このとき、固体撮像装置９０１は、裏面照射型イメージセンサを構成することができる。 The pixels 120 are arranged in a matrix in the row and column directions in the pixel array section 913. The column readout circuit 915 can read out signals from each pixel 120 individually based on constant current readout, or can read out signals by binning. The column ADC 916 can perform AD conversion on the signals read out via the column readout circuit 915 for each column. In this case, the solid-state imaging device 901 can constitute a back-illuminated image sensor.
　同図におけるｂにおいて、固体撮像装置９０２は、半導体基板９２１および９２２を備える。半導体基板９２２は、半導体基板９２１上に積層されている。半導体基板９２２には、画素アレイ部９２３が形成される。半導体基板９２２には、周辺回路９２４が形成される。周辺回路９２４には、カラム読出し回路９２５およびカラムＡＤＣ９２６が形成される。カラム読出し回路９２５およびカラムＡＤＣ９２６は、画素アレイ部９２３のカラム方向の両側の位置に対応するように形成してもよい。このとき、固体撮像装置９０２は、裏面照射型イメージセンサを構成することができる。 In FIG. 9B, the solid-state imaging device 902 includes semiconductor substrates 921 and 922. The semiconductor substrate 922 is stacked on the semiconductor substrate 921. A pixel array section 923 is formed on the semiconductor substrate 922. A peripheral circuit 924 is formed on the semiconductor substrate 922. A column readout circuit 925 and a column ADC 926 are formed on the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction. In this case, the solid-state imaging device 902 can constitute a back-illuminated image sensor.
　このように、上述の第１４の実施の形態では、各固体撮像装置９０１および９０２が形成される基板をそれぞれ積層化する。これにより、各画素アレイ部９１３および９２３を支持しつつ、各画素アレイ部９１３および９２３がそれぞれ形成される半導体基板９１２および９２２を薄膜化することができ、裏面照射型イメージセンサを形成することができる。 In this way, in the above-mentioned 14th embodiment, the substrates on which the solid- state imaging devices 901 and 902 are formed are stacked. This makes it possible to thin the semiconductor substrates 912 and 922 on which the pixel array sections 913 and 923 are formed while supporting the pixel array sections 913 and 923, respectively, and to form a back-illuminated image sensor.
　＜１１．移動体への応用例＞
　本開示に係る技術（本技術）は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 <11. Examples of applications to moving objects>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.
　図４５は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。 FIG. 45 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
　車両制御システム１２０００は、通信ネットワーク１２００１を介して接続された複数の電子制御ユニットを備える。図４５に示した例では、車両制御システム１２０００は、駆動系制御ユニット１２０１０、ボディ系制御ユニット１２０２０、車外情報検出ユニット１２０３０、車内情報検出ユニット１２０４０、及び統合制御ユニット１２０５０を備える。また、統合制御ユニット１２０５０の機能構成として、マイクロコンピュータ１２０５１、音声画像出力部１２０５２、及び車載ネットワークＩ／Ｆ(interface)１２０５３が図示されている。 The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 45, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
　駆動系制御ユニット１２０１０は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット１２０１０は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。 The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
　ボディ系制御ユニット１２０２０は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット１２０２０は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット１２０２０には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット１２０２０は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。 The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020. The body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
　車外情報検出ユニット１２０３０は、車両制御システム１２０００を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット１２０３０には、撮像部１２０３１が接続される。車外情報検出ユニット１２０３０は、撮像部１２０３１に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット１２０３０は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。 The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface based on the received images.
　撮像部１２０３１は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部１２０３１は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部１２０３１が受光する光は、可視光であってもよいし、赤外線等の非可視光であってもよい。 The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
　車内情報検出ユニット１２０４０は、車内の情報を検出する。車内情報検出ユニット１２０４０には、例えば、運転者の状態を検出する運転者状態検出部１２０４１が接続される。運転者状態検出部１２０４１は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット１２０４０は、運転者状態検出部１２０４１から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。 The in-vehicle information detection unit 12040 detects information inside the vehicle. To the in-vehicle information detection unit 12040, for example, a driver state detection unit 12041 that detects the state of the driver is connected. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
　マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット１２０１０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むＡＤＡＳ(Advanced Driver Assistance System)の機能実現を目的とした協調制御を行うことができる。 The microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 The microcomputer 12051 can also control the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby performing cooperative control aimed at automatic driving, which allows the vehicle to travel autonomously without relying on the driver's operation.
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で取得される車外の情報に基づいて、ボディ系制御ユニット１２０２０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。 The microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching high beams to low beams.
　音声画像出力部１２０５２は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図４５の例では、出力装置として、オーディオスピーカ１２０６１、表示部１２０６２及びインストルメントパネル１２０６３が例示されている。表示部１２０６２は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。 The audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information. In the example of FIG. 45, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
　図４６は、撮像部１２０３１の設置位置の例を示す図である。 FIG. 46 shows an example of the installation position of the imaging unit 12031.
　図４６では、撮像部１２０３１として、撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５を有する。 In FIG. 46, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
　撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５は、例えば、車両１２１００のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部１２１０１及び車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として車両１２１００の前方の画像を取得する。サイドミラーに備えられる撮像部１２１０２，１２１０３は、主として車両１２１００の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部１２１０４は、主として車両１２１００の後方の画像を取得する。車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。 The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
　なお、図４６には、撮像部１２１０１ないし１２１０４の撮影範囲の一例が示されている。撮像範囲１２１１１は、フロントノーズに設けられた撮像部１２１０１の撮像範囲を示し、撮像範囲１２１１２，１２１１３は、それぞれサイドミラーに設けられた撮像部１２１０２，１２１０３の撮像範囲を示し、撮像範囲１２１１４は、リアバンパ又はバックドアに設けられた撮像部１２１０４の撮像範囲を示す。例えば、撮像部１２１０１ないし１２１０４で撮像された画像データが重ね合わせられることにより、車両１２１００を上方から見た俯瞰画像が得られる。 Note that FIG. 46 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、距離情報を取得する機能を有していてもよい。例えば、撮像部１２１０１ないし１２１０４の少なくとも１つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。 At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for detecting phase differences.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を基に、撮像範囲１２１１１ないし１２１１４内における各立体物までの距離と、この距離の時間的変化（車両１２１００に対する相対速度）を求めることにより、特に車両１２１００の進行路上にある最も近い立体物で、車両１２１００と略同じ方向に所定の速度（例えば、０ｋｍ／ｈ以上）で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ１２０５１は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御（追従停止制御も含む）や自動加速制御（追従発進制御も含む）等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 For example, the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を元に、立体物に関する立体物データを、２輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ１２０５１は、車両１２１００の周辺の障害物を、車両１２１００のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ１２０５１は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ１２０６１や表示部１２０６２を介してドライバに警報を出力することや、駆動系制御ユニット１２０１０を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。 For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering the vehicle to avoid a collision via the drive system control unit 12010.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部１２１０１ないし１２１０４の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ１２０５１が、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部１２０５２は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部１２０６２を制御する。また、音声画像出力部１２０５２は、歩行者を示すアイコン等を所望の位置に表示するように表示部１２０６２を制御してもよい。 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured image of the imaging units 12101 to 12104 and recognizes a pedestrian, the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
　以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、撮像部１２０３１に適用され得る。具体的には、例えば、上述のカメラ１００は、撮像部１２０３１に適用することができる。車両制御システム１２０００に本開示に係る技術を適用することにより、エッジ画像の画質を向上させることが可能となる。 Above, an example of a vehicle control system to which the technology disclosed herein can be applied has been described. Of the configurations described above, the technology disclosed herein can be applied to the imaging unit 12031. Specifically, for example, the camera 100 described above can be applied to the imaging unit 12031. By applying the technology disclosed herein to the vehicle control system 12000, it is possible to improve the image quality of edge images.
　なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。また、本明細書に記載された効果はあくまで例示であって、限定されるものではなく、また、他の効果があってもよい。 Note that the above-described embodiment shows an example for realizing the present technology, and there is a corresponding relationship between the matters in the embodiment and the matters specifying the invention in the claims. Similarly, there is a corresponding relationship between the matters specifying the invention in the claims and the matters in the embodiment of the present technology that have the same name. However, the present technology is not limited to the embodiment, and can be realized by making various modifications to the embodiment without departing from the gist of the technology. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.
　なお、本技術は以下のような構成もとることができる。
（１）畳み込み処理されるカーネル単位で画素から画素信号を読出す読出回路と、
　前記カーネル単位で読出された一部の画素の画素信号に基づいてエッジ信号の生成処理を実施するとともに、前記カーネル単位で読出された画素のうち前記エッジ信号の生成に用いられない画素を少なくとも含んで読出された画素信号に基づいて階調信号の生成処理を実施する信号処理部と
を備える撮像装置。
（２）前記信号処理部は、同一フレーム内において、前記エッジ信号を生成した後、前記階調信号を生成する
前記（１）記載の撮像装置。
（３）前記読出回路は、前記エッジ信号の生成に用いられる前記画素信号を前記画素から非破壊で読出した後、前記階調信号の生成に用いられる前記画素信号を前記画素から非破壊で読出す
前記（１）または（２）に記載の撮像装置。
（４）前記エッジ信号の生成に用いられる画素は、行および列がそれぞれ互い異なるように選択される
前記（１）から（３）のいずれかに記載の撮像装置。
（５）前記階調信号は、前記カーネル単位で読み出された全ての画素の画素信号のビニング値に基づいて生成される
前記（１）から（４）のいずれかに記載の撮像装置。
（６）リセットレベルに基づくオートゼロ動作後に、信号レベルのＡＤ変換に基づいてエッジ信号を生成し、
　前記カーネル単位で読み出された全ての画素について、信号レベルのビニング値に基づくオートゼロ動作後に、リセットレベルのビニング値のＡＤ変換に基づいて諧調信号を生成する
前記（５）に記載の撮像装置。
（７）前記階調信号は、前記カーネル単位で読み出された画素のうち前記エッジ信号の生成に用いられた画素を含まない画素信号のビニング値に基づいて生成される
前記（１）から（４）のいずれかに記載の撮像装置。
（８）リセットレベルに基づくオートゼロ動作後に、信号レベルのＡＤ変換に基づいてエッジ信号を生成し、
　前記カーネル単位で読み出された画素のうち前記エッジ信号の生成に用いられた画素を含まない画素について、リセットレベルのビニング値に基づくオートゼロ動作後に、信号レベルのビニング値のＡＤ変換に基づいて諧調信号を生成する
前記（７）に記載の撮像装置。
（９）前記カーネル単位のサイズは、前記エッジ信号の生成時と前記階調信号の生成時とで互いに等しい
前記（１）から（８）のいずれかに記載の撮像装置。
（１０）前記カーネル単位のサイズは、前記エッジ信号の生成時と前記階調信号の生成時とで互いに異なる
前記（１）から（８）のいずれかに記載の撮像装置。
（１１）前記信号処理部は、前記エッジ信号の生成と前記階調信号の生成とに用いられるＡＤ変換部を備え、
　前記読出回路は、前記エッジ信号の生成と前記階調信号の生成とで前記画素信号をカラム方向に伝送する信号線と前記ＡＤ変換部との接続を切り替えるマルチプレクサ
を備える前記（１）から（１０）のいずれかに記載の撮像装置。
（１２）前記ＡＤ変換部は、フラッシュＡＤ変換器およびシングルスロープＡＤ変換器の少なくともいずれか１つを備える前記（１１）に記載の撮像装置。
（１３）前記ＡＤ変換部に入力される参照信号を生成する参照信号生成部
をさらに備える前記（１１）または（１２）に記載の撮像装置。
（１４）前記参照信号生成部は、
　複数のレベル信号を生成する第１参照信号生成部と、
　ランプ信号を生成する第２参照信号生成部と、
　前記レベル信号の出力と前記ランプ信号の出力とを切り替える参照信号切替部と
を備える前記（１３）に記載の撮像装置。
（１５）前記ＡＤ変換部は、前記エッジ信号の生成と前記階調信号の生成とで共用されるコンパレータを備え、
　前記マルチプレクサは、
　前記エッジ信号の生成時には、２つの画素からの画素信号が前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替え、
　前記階調信号の生成時には、前記カーネル単位で読出された画素信号と、前記画素信号と比較される参照信号とが前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替える
前記（１１）から（１４）のいずれかに記載の撮像装置。
（１６）前記ＡＤ変換部は、前記エッジ信号の生成と前記階調信号の生成とで共用されるとともに、画素単位の撮像信号の生成にも共用され、
　前記マルチプレクサは、
　前記エッジ信号の生成時には、２つの画素からの画素信号が前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替え、
　前記階調信号の生成時には、前記カーネル単位で読出された画素信号と、前記画素信号と比較される参照信号とが前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替え、
　前記撮像信号の生成時には、前記画素単位で読出された画素信号と、前記画素信号と比較される参照信号とが前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替える
前記（１１）から（１５）のいずれかに記載の撮像装置。
（１７）前記画素に蓄積された電荷の転送を制御する転送制御ドライバと、
　前記画素信号が読出される画素の選択を制御する選択制御ドライバと、
　前記画素に蓄積された電荷のリセットを制御するリセット制御ドライバと、
　前記画素に蓄積された電荷のビニングを制御するビニング制御ドライバと
を備える前記（１）から（１６）のいずれかに記載の撮像装置。
（１８）前記画素は、前記画素のフローティングディフュージョンを他の画素のフローティングディフュージョンと接続するビニングトランジスタ
を備える前記（１）から（１７）のいずれかに記載の撮像装置。
（１９）前記画素信号をカラム方向に伝送する信号線を互いに異なるカラム間で接続する接続スイッチ
をさらに備える前記（１）から（１８）のいずれかに記載の撮像装置。
（２０）前記階調信号に基づいて露光制御を実施する露光制御部
をさらに備える前記（１）から（１９）のいずれかに記載の撮像装置。 The present technology can also be configured as follows.
(1) a readout circuit that reads out pixel signals from pixels in units of kernels to be convolved;
an imaging device comprising: a signal processing unit that performs an edge signal generation process based on pixel signals of a portion of pixels read out on a kernel basis, and performs a gradation signal generation process based on pixel signals read out including at least pixels among the pixels read out on a kernel basis that are not used to generate the edge signal.
(2) The imaging device according to (1), wherein the signal processing unit generates the edge signal and then generates the gradation signal within the same frame.
(3) An imaging device described in (1) or (2), wherein the readout circuit non-destructively reads out from the pixel the pixel signal used to generate the edge signal, and then non-destructively reads out from the pixel the pixel signal used to generate the gradation signal.
(4) The imaging device according to any one of (1) to (3), wherein the pixels used to generate the edge signal are selected so that their rows and columns are different from each other.
(5) The imaging device according to any one of (1) to (4), wherein the gradation signal is generated based on a binning value of pixel signals of all pixels read out in units of kernels.
(6) generating an edge signal based on AD conversion of the signal level after an auto-zero operation based on the reset level;
The imaging device according to (5), wherein after an auto-zero operation based on a binning value of a signal level is performed for all pixels read out on a kernel-by-kernel basis, a gradation signal is generated based on AD conversion of a binning value of a reset level.
(7) An imaging device described in any one of (1) to (4), in which the gradation signal is generated based on a binning value of pixel signals that do not include pixels used to generate the edge signal among the pixels read out on a kernel basis.
(8) generating an edge signal based on AD conversion of the signal level after an auto-zero operation based on the reset level;
The imaging device described in (7) generates a gradation signal based on AD conversion of the binning value of the signal level after an auto-zero operation based on the binning value of the reset level for pixels among the pixels read out on a kernel basis that do not include pixels used to generate the edge signal.
(9) The imaging device according to any one of (1) to (8), wherein the size of the kernel unit is equal when the edge signal is generated and when the gradation signal is generated.
(10) The imaging device according to any one of (1) to (8), wherein the size of the kernel unit is different between when the edge signal is generated and when the gradation signal is generated.
(11) The signal processing unit includes an AD conversion unit used to generate the edge signal and the gradation signal,
The imaging device described in any one of (1) to (10), wherein the readout circuit is provided with a multiplexer that switches a connection between a signal line that transmits the pixel signal in a column direction and the AD conversion unit depending on whether the edge signal is generated or the gradation signal is generated.
(12) The imaging device according to (11), wherein the AD conversion unit includes at least one of a flash AD converter and a single-slope AD converter.
(13) The imaging device according to (11) or (12), further comprising a reference signal generating unit that generates a reference signal to be input to the AD conversion unit.
(14) The reference signal generation unit
a first reference signal generating unit that generates a plurality of level signals;
A second reference signal generating unit that generates a ramp signal;
The imaging device according to (13), further comprising a reference signal switching unit that switches between an output of the level signal and an output of the ramp signal.
(15) The AD conversion unit includes a comparator shared between generating the edge signal and generating the gradation signal,
The multiplexer includes:
when generating the edge signal, switching a connection between the signal line and the AD conversion unit so that pixel signals from two pixels are input to the comparator;
The imaging device according to any one of (11) to (14), wherein, when the gradation signal is generated, the connection between the signal line and the AD conversion unit is switched so that a pixel signal read out on a kernel basis and a reference signal to be compared with the pixel signal are input to the comparator.
(16) The AD conversion unit is used in common for generating the edge signal and the gradation signal, and is also used in common for generating an imaging signal on a pixel-by-pixel basis,
The multiplexer includes:
when generating the edge signal, switching a connection between the signal line and the AD conversion unit so that pixel signals from two pixels are input to the comparator;
When generating the gradation signal, a connection between the signal line and the AD conversion unit is switched so that a pixel signal read out on a kernel-by-kernel basis and a reference signal to be compared with the pixel signal are input to the comparator;
The imaging device according to any one of (11) to (15), wherein, when the imaging signal is generated, the connection between the signal line and the AD conversion unit is switched so that a pixel signal read out on a pixel-by-pixel basis and a reference signal to be compared with the pixel signal are input to the comparator.
(17) A transfer control driver that controls transfer of the charge stored in the pixel;
a selection control driver for controlling selection of a pixel from which the pixel signal is to be read;
A reset control driver that controls resetting of charges accumulated in the pixels;
The imaging device according to any one of (1) to (16), further comprising: a binning control driver that controls binning of the electric charges accumulated in the pixels.
(18) The imaging device according to any one of (1) to (17), wherein the pixel includes a binning transistor that connects the floating diffusion of the pixel to the floating diffusion of another pixel.
(19) The imaging device according to any one of (1) to (18), further comprising a connection switch that connects signal lines that transmit the pixel signals in a column direction between different columns.
(20) The imaging device according to any one of (1) to (19), further comprising an exposure control unit that performs exposure control based on the gradation signal.
　１００　カメラ
　１０１　光学系
　１０２　固体撮像装置
　１０３　撮像制御部
　１０４　画像処理部
　１０５　記憶部
　１０６　表示部
　１０７　操作部
　１０８　バス
　１１１　画素アレイ部
　１１２　垂直走査回路
　１１３　カラム読出し回路
　１１４　カラム信号処理部
　１１５　水平走査回路
　１１６　制御回路
　１２０　画素
　１２１　フォトダイオード
　１２２　転送トランジスタ
　１２３　リセットトランジスタ
　１２４　増幅トランジスタ
　１２５　選択トランジスタ
　１２６　フローティングディフュージョン
　１３１　水平駆動線
　１３２　垂直信号線
　１４１　転送制御ドライバ
　１４２　選択制御ドライバ
　１４３　リセット制御ドライバ
　１４４　ビニング制御ドライバ
　１４５　ＡＤ変換部
　１５１　参照信号生成部
　１５２　露光制御部
　１５３　ランプ信号生成部
　１５４　レベル信号生成部
　１５５　参照信号切替部
　１６１　マルチプレクサ
　１６１－１から１６１－４、２６１－１から２６１－４　スイッチ
　１７１－１から１７１－４　コンパレータ
　１８１－１から１８１－４　インバータ
　１９１－１から１９１－４　ＮＡＮＤ回路
　２５１－１から２５１－４　電流源
　２７１－１から２７１－４　セレクタ
　２８１－１から２８１－４　ゲイン部
　２９１、２９２　ＤＣカットコンデンサ REFERENCE SIGNS LIST 100 camera 101 optical system 102 solid-state imaging device 103 imaging control unit 104 image processing unit 105 memory unit 106 display unit 107 operation unit 108 bus 111 pixel array unit 112 vertical scanning circuit 113 column readout circuit 114 column signal processing unit 115 horizontal scanning circuit 116 control circuit 120 pixel 121 photodiode 122 transfer transistor 123 reset transistor 124 amplifying transistor 125 selection transistor 126 floating diffusion 131 horizontal drive line 132 vertical signal line 141 transfer control driver 142 selection control driver 143 reset control driver 144 binning control driver 145 AD conversion unit 151 reference signal generation unit 152 exposure control unit 153 ramp signal generation unit 154 Level signal generating section 155 Reference signal switching section 161 Multiplexers 161-1 to 161-4, 261-1 to 261-4 Switches 171-1 to 171-4 Comparators 181-1 to 181-4 Inverters 191-1 to 191-4 NAND circuits 251-1 to 251-4 Current sources 271-1 to 271-4 Selectors 281-1 to 281-4 Gain sections 291, 292 DC cut capacitors

Claims (20)

  1. 　畳み込み処理されるカーネル単位で画素から画素信号を読出す読出回路と、
    　前記カーネル単位で読出された一部の画素の画素信号に基づいてエッジ信号の生成処理を実施するとともに、前記カーネル単位で読出された画素のうち前記エッジ信号の生成に用いられない画素を少なくとも含んで読出された画素信号に基づいて階調信号の生成処理を実施する信号処理部と
    を備える撮像装置。     A readout circuit that reads out pixel signals from pixels in units of kernels to be convolved;
    an imaging device comprising: a signal processing unit that performs an edge signal generation process based on pixel signals of a portion of pixels read out on a kernel basis, and performs a gradation signal generation process based on pixel signals read out including at least pixels among the pixels read out on a kernel basis that are not used to generate the edge signal.
  2. 　前記信号処理部は、同一フレーム内において、前記エッジ信号を生成した後、前記階調信号を生成する
    請求項１に記載の撮像装置。     The imaging device according to claim 1 , wherein the signal processing unit generates the edge signal and then generates the gradation signal within the same frame.
  3. 　前記読出回路は、前記エッジ信号の生成に用いられる前記画素信号を前記画素から非破壊で読出した後、前記階調信号の生成に用いられる前記画素信号を前記画素から非破壊で読出す
    請求項１に記載の撮像装置。     2. The imaging device according to claim 1, wherein the readout circuit non-destructively reads out from the pixels the pixel signals used to generate the edge signals, and then non-destructively reads out from the pixels the pixel signals used to generate the gradation signals.
  4. 　前記エッジ信号の生成に用いられる画素は、行および列がそれぞれ互い異なるように選択される
    請求項１に記載の撮像装置。     The imaging device according to claim 1 , wherein the pixels used to generate the edge signal are selected so that their rows and columns are different from each other.
  5. 　前記階調信号は、前記カーネル単位で読み出された全ての画素の画素信号のビニング値に基づいて生成される
    請求項１に記載の撮像装置。     The imaging device according to claim 1 , wherein the gradation signal is generated based on a binning value of pixel signals of all pixels read out in units of kernels.
  6. 　リセットレベルに基づくオートゼロ動作後に、信号レベルのＡＤ変換に基づいてエッジ信号を生成し、
    　前記カーネル単位で読み出された全ての画素について、信号レベルのビニング値に基づくオートゼロ動作後に、リセットレベルのビニング値のＡＤ変換に基づいて諧調信号を生成する
    請求項５に記載の撮像装置。     After an auto-zero operation based on a reset level, an edge signal is generated based on an AD conversion of the signal level;
    The imaging device according to claim 5 , wherein after an auto-zero operation based on a binning value of a signal level is performed for all pixels read out in units of kernels, a gradation signal is generated based on AD conversion of a binning value of a reset level.
  7. 　前記階調信号は、前記カーネル単位で読み出された画素のうち前記エッジ信号の生成に用いられた画素を含まない画素信号のビニング値に基づいて生成される
    請求項１に記載の撮像装置。     The imaging device according to claim 1 , wherein the gradation signal is generated based on a binning value of pixel signals that do not include pixels used in generating the edge signal among the pixels read out in units of the kernel.
  8. 　リセットレベルに基づくオートゼロ動作後に、信号レベルのＡＤ変換に基づいてエッジ信号を生成し、
    　前記カーネル単位で読み出された画素のうち前記エッジ信号の生成に用いられた画素を含まない画素について、リセットレベルのビニング値に基づくオートゼロ動作後に、信号レベルのビニング値のＡＤ変換に基づいて諧調信号を生成する
    請求項７に記載の撮像装置。     After an auto-zero operation based on a reset level, an edge signal is generated based on an AD conversion of the signal level;
    8. The imaging device according to claim 7, wherein for pixels among the pixels read out on a kernel basis that do not include pixels used in generating the edge signal, after an auto-zero operation based on a binning value of a reset level, a gradation signal is generated based on AD conversion of a binning value of a signal level.
  9. 　前記カーネル単位のサイズは、前記エッジ信号の生成時と前記階調信号の生成時とで互いに等しい
    請求項１に記載の撮像装置。     The imaging device according to claim 1 , wherein the size of the kernel unit is equal when the edge signal is generated and when the gradation signal is generated.
  10. 　前記カーネル単位のサイズは、前記エッジ信号の生成時と前記階調信号の生成時とで互いに異なる
    請求項１に記載の撮像装置。     The imaging device according to claim 1 , wherein a size of the kernel unit is different between when the edge signal is generated and when the gradation signal is generated.
  11. 　前記信号処理部は、前記エッジ信号の生成と前記階調信号の生成とに用いられるＡＤ変換部を備え、
    　前記読出回路は、前記エッジ信号の生成と前記階調信号の生成とで前記画素信号をカラム方向に伝送する信号線と前記ＡＤ変換部との接続を切り替えるマルチプレクサ
    を備える請求項１に記載の撮像装置。     the signal processing unit includes an AD conversion unit used for generating the edge signal and the gradation signal,
    2 . The imaging device according to claim 1 , wherein the readout circuit includes a multiplexer that switches a connection between the AD conversion unit and a signal line that transmits the pixel signal in the column direction depending on whether the edge signal is generated or the gradation signal is generated.
  12. 　前記ＡＤ変換部は、フラッシュＡＤ変換器およびシングルスロープＡＤ変換器の少なくともいずれか１つを備える請求項１１に記載の撮像装置。 The imaging device according to claim 11, wherein the AD conversion unit includes at least one of a flash AD converter and a single-slope AD converter.
  13. 　前記ＡＤ変換部に入力される参照信号を生成する参照信号生成部
    をさらに備える請求項１１に記載の撮像装置。     The imaging device according to claim 11 , further comprising a reference signal generating unit that generates a reference signal to be input to the AD conversion unit.
  14. 　前記参照信号生成部は、
    　複数のレベル信号を生成する第１参照信号生成部と、
    　ランプ信号を生成する第２参照信号生成部と、
    　前記レベル信号の出力と前記ランプ信号の出力とを切り替える参照信号切替部と
    を備える請求項１３に記載の撮像装置。     The reference signal generation unit
    a first reference signal generating unit that generates a plurality of level signals;
    A second reference signal generating unit that generates a ramp signal;
    The imaging device according to claim 13 , further comprising a reference signal switching unit that switches between an output of the level signal and an output of the ramp signal.
  15. 　前記ＡＤ変換部は、前記エッジ信号の生成と前記階調信号の生成とで共用されるコンパレータを備え、
    　前記マルチプレクサは、
    　前記エッジ信号の生成時には、２つの画素からの画素信号が前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替え、
    　前記階調信号の生成時には、前記カーネル単位で読出された画素信号と、前記画素信号と比較される参照信号とが前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替える
    請求項１１に記載の撮像装置。     the AD conversion unit includes a comparator shared between generating the edge signal and generating the gradation signal,
    The multiplexer includes:
    when generating the edge signal, switching a connection between the signal line and the AD conversion unit so that pixel signals from two pixels are input to the comparator;
    The imaging device described in claim 11, wherein when the gradation signal is generated, the connection between the signal line and the AD conversion unit is switched so that a pixel signal read out on a kernel basis and a reference signal to be compared with the pixel signal are input to the comparator.
  16. 　前記ＡＤ変換部は、前記エッジ信号の生成と前記階調信号の生成とで共用されるとともに、画素単位の撮像信号の生成にも共用され、
    　前記マルチプレクサは、
    　前記エッジ信号の生成時には、２つの画素からの画素信号が前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替え、
    　前記階調信号の生成時には、前記カーネル単位で読出された画素信号と、前記画素信号と比較される参照信号とが前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替え、
    　前記撮像信号の生成時には、前記画素単位で読出された画素信号と、前記画素信号と比較される参照信号とが前記コンパレータに入力されるように前記信号線と前記ＡＤ変換部との接続を切り替える
    請求項１１に記載の撮像装置。     the AD conversion unit is used in common for generating the edge signal and the gradation signal, and is also used in common for generating an imaging signal in pixel units;
    The multiplexer includes:
    when generating the edge signal, switching a connection between the signal line and the AD conversion unit so that pixel signals from two pixels are input to the comparator;
    When generating the gradation signal, a connection between the signal line and the AD conversion unit is switched so that a pixel signal read out on a kernel-by-kernel basis and a reference signal to be compared with the pixel signal are input to the comparator;
    The imaging device according to claim 11, wherein when the imaging signal is generated, the connection between the signal line and the AD conversion unit is switched so that a pixel signal read out on a pixel-by-pixel basis and a reference signal to be compared with the pixel signal are input to the comparator.
  17. 　前記画素に蓄積された電荷の転送を制御する転送制御ドライバと、
    　前記画素信号が読出される画素の選択を制御する選択制御ドライバと、
    　前記画素に蓄積された電荷のリセットを制御するリセット制御ドライバと、
    　前記画素に蓄積された電荷のビニングを制御するビニング制御ドライバと
    を備える請求項１に記載の撮像装置。     a transfer control driver for controlling the transfer of the electric charge stored in the pixel;
    a selection control driver for controlling selection of a pixel from which the pixel signal is to be read;
    A reset control driver that controls resetting of charges accumulated in the pixels;
    The imaging device according to claim 1 , further comprising a binning control driver that controls binning of the charges stored in the pixels.
  18. 　前記画素は、前記画素のフローティングディフュージョンを他の画素のフローティングディフュージョンと接続するビニングトランジスタ
    を備える請求項１に記載の撮像装置。     The imaging device according to claim 1 , wherein the pixel comprises a binning transistor that connects the floating diffusion of the pixel to the floating diffusion of another pixel.
  19. 　前記画素信号をカラム方向に伝送する信号線を互いに異なるカラム間で接続する接続スイッチ
    をさらに備える請求項１に記載の撮像装置。     The imaging device according to claim 1 , further comprising a connection switch that connects signal lines that transmit the pixel signals in a column direction between different columns.
  20. 　前記階調信号に基づいて露光制御を実施する露光制御部
    をさらに備える請求項１に記載の撮像装置。     The imaging apparatus according to claim 1 , further comprising an exposure control unit that performs exposure control based on the gradation signal.
PCT/JP2023/038719 2022-12-21 2023-10-26 Imaging device WO2024135091A1 (en)

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JP2018125842A (en) * 2017-02-03 2018-08-09 パナソニックＩｐマネジメント株式会社 Imaging apparatus and camera system
WO2021090538A1 (en) * 2019-11-07 2021-05-14 ソニーセミコンダクタソリューションズ株式会社 Sensing device, electronic apparatus, and method for controlling sensing device
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JP2018125842A (en) * 2017-02-03 2018-08-09 パナソニックＩｐマネジメント株式会社 Imaging apparatus and camera system
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