WO2024042862A1 - Imaging device - Google Patents

Imaging device Download PDF

Info

Publication number
WO2024042862A1
WO2024042862A1 PCT/JP2023/024422 JP2023024422W WO2024042862A1 WO 2024042862 A1 WO2024042862 A1 WO 2024042862A1 JP 2023024422 W JP2023024422 W JP 2023024422W WO 2024042862 A1 WO2024042862 A1 WO 2024042862A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
signal line
imaging device
signal
pixel
Prior art date
Application number
PCT/JP2023/024422
Other languages
French (fr)
Japanese (ja)
Inventor
守 佐藤
克彦 半澤
達也 石川
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニーセミコンダクタソリューションズ株式会社 filed Critical ソニーセミコンダクタソリューションズ株式会社
Publication of WO2024042862A1 publication Critical patent/WO2024042862A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present technology relates to an imaging device. Specifically, the present technology relates to an imaging device capable of capacitive load reading.
  • a capacitive load readout method is known in which a capacitor is used as the load of a source follower when reading signals from a pixel.
  • a capacitive load readout method for example, an imaging device has been proposed in which a reset unit resets the voltage of the output line, and then a constant current source causes a constant current to flow through the output line, and the source of the amplification transistor is connected to the output line. (For example, see Patent Document 1).
  • an output line reset voltage generation circuit that generates an output line reset voltage is provided in order to reset the voltage of the output line by the reset section, which may increase current consumption.
  • the output line reset voltage generation circuit is omitted and the output line reset voltage is set to the ground voltage, there is a risk that the settling time will increase.
  • the present technology was created in view of this situation, and its purpose is to enable capacitive load reading while suppressing increases in current consumption and settling time.
  • the imaging device includes: a signal line transistor electrically connected to the signal line; and a voltage generation section connected in series to the signal line transistor and capable of generating a voltage higher than 0V. This brings about the effect that the signal line is set to a voltage higher than 0V when the signal line is reset.
  • the potential of the signal line may be a potential of a parasitic capacitance of the signal line. This brings about the effect that capacitive load reading can be performed without adding a capacitive element to the signal line.
  • the pixel includes a photodiode, a transfer transistor that transfers the charge accumulated in the photodiode to the floating diffusion, a reset transistor that resets the floating diffusion, and a potential of the floating diffusion.
  • the device may include an amplification transistor that outputs a corresponding signal, and a selection transistor connected between the amplification transistor and the signal line. This brings about the effect that a source follower is formed between the pixel and the pixel when a signal is read from the pixel.
  • the voltage generation section may include a diode-connected transistor. This brings about the effect that the potential of the signal line is raised in accordance with the forward voltage of the diode-connected transistor when the signal line is reset.
  • the voltage generation section may include a plurality of diode-connected transistors having different numbers of series connections. This brings about the effect that the voltage of the signal line at the time of resetting the signal line can be switched.
  • the voltage generation unit sets the reset level of the signal line when the reset level is read from the pixel to be equal to or higher than the reset level of the signal line when the signal level is read from the pixel. Good too. This brings about the effect of shortening the settling time when the reset level is read from the pixel.
  • the device may further include a comparator that compares the potential of the signal line and the ramp signal. This brings about the effect that the signal read from the pixel can be detected based on the potential of the signal line.
  • a comparator may be further provided to compare the potentials of the signal lines provided in different columns. This brings about the effect that the edge of the object is detected based on the capacitive load readout.
  • the device may further include a constant current transistor that is electrically connectable to the signal line and that flows a constant current based on a source follower formed between the pixel and the pixel. This brings about the effect that constant current reading is possible when capacitive load reading is not performed.
  • the constant current transistor may be turned on in constant current readout using the constant current transistor, and the constant current transistor may be turned off in capacitive load readout using the voltage generation section. . This brings about the effect that capacitive load readout and constant current readout can be switched.
  • the device further includes a sample hold circuit that operates the signal line transistor as a constant current transistor, and a switch that switches a connection destination of the signal line transistor between the voltage generation section and a ground potential. It's okay. This brings about the effect that the signal line transistor is shared for constant current reading and capacitive load reading.
  • the connection destination of the signal line transistor in constant current readout, the connection destination of the signal line transistor is switched to the ground potential and the signal line transistor is turned on, and in the capacitive load readout, the connection destination of the signal line transistor is switched to the ground potential, and the signal line transistor is turned on.
  • the signal line transistor may be turned off after being switched to the voltage generating section and the signal line being reset. This brings about the effect that capacitive load readout and constant current readout can be switched.
  • the voltage generation section may include a series transistor connected in series to the signal line transistor, and an opening/closing transistor that opens and closes between a gate and a drain of the series transistor. This brings about the effect that the series transistor is shared for constant current reading and capacitive load reading.
  • the switching transistor may be turned off in constant current reading, and the switching transistor may be turned on in capacitive load reading. This brings about the effect that capacitive load readout and constant current readout can be switched.
  • the first side surface may include a chip on which the pixel is formed, and the signal line transistor may be formed on the chip. This brings about the effect that variations in the characteristics of the signal line transistor and the characteristics of the pixel transistor are reduced.
  • the voltage generation section may be formed on the chip. This brings about the effect that variations in the characteristics of the voltage generation section and the characteristics of the pixel transistor are reduced.
  • the first side surface further includes a pixel array section in which the pixels are arranged in a matrix in the row direction and the column direction, and a plurality of the signal lines are provided in the row direction so as to be wired in the column direction.
  • the signal line transistor may be provided for each of the signal lines. This brings about the effect that the potential of the signal line is reset for each signal line.
  • the voltage generation section may be provided in each of the signal lines having different columns. This brings about the effect that the potential of the signal line is set for each signal line.
  • the voltage generation section may be shared by a plurality of signal lines having different columns. This brings about the effect that the number of voltage generating sections is reduced relative to the number of columns.
  • each column may include a shorting line that shorts the voltage generation sections provided in each of the plurality of signal lines different from each other. This brings about the effect that variations in the potential of the signal line from column to column are reduced.
  • FIG. 1 is a block diagram illustrating a configuration example of a camera to which the imaging device according to the first embodiment is applied.
  • 1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment.
  • FIG. 2 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing a configuration example of a pixel array section provided in the solid-state imaging device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a modification of the pixel array section provided in the solid-state imaging device according to the first embodiment.
  • FIG. 3 is a diagram illustrating a configuration example of a signal readout circuit for one column according to the first embodiment.
  • FIG. 3 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the first embodiment.
  • FIG. 3 is a diagram illustrating an example of a circuit configuration of a voltage generation section connected to a vertical signal line of the imaging device according to the first embodiment.
  • FIG. 7 is a block diagram showing an example of switching when reading a capacitive load of a signal reading circuit for one column according to a second embodiment.
  • FIG. 7 is a block diagram showing an example of switching during constant current readout of the signal readout circuit for one column according to the second embodiment.
  • FIG. 7 is a diagram showing an example of waveforms of various parts during constant current readout of the signal readout circuit according to the second embodiment.
  • FIG. 7 is a diagram showing a configuration example of a signal readout circuit for one column according to a third embodiment.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for one column according to a fourth embodiment.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for two columns according to a fifth embodiment.
  • FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for four columns according to a sixth embodiment.
  • FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for one column according to a seventh embodiment.
  • FIG. 12 is a diagram showing an example of waveforms of various parts during constant current readout of the signal readout circuit according to the second embodiment.
  • FIG. 7 is a diagram showing a configuration example of a signal readout circuit for one column according to
  • FIG. 12 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the seventh embodiment.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for one column according to an eighth embodiment.
  • FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for one column according to a ninth embodiment.
  • 10 is a diagram showing an example of the configuration of a signal readout circuit for one column according to a tenth embodiment.
  • FIG. FIG. 12 is a diagram showing a configuration example of a signal readout circuit for two columns according to an eleventh embodiment.
  • FIG. 12 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the eleventh embodiment.
  • FIG. 12 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the eleventh embodiment.
  • FIG. 12 is a perspective view showing a configuration example of an imaging device according to a twelfth embodiment.
  • FIG. 1 is a block diagram showing a schematic configuration example of a vehicle control system.
  • FIG. 3 is an explanatory diagram showing an example of an installation position of an imaging unit.
  • First embodiment (example in which a diode-connected transistor is connected via a signal line transistor electrically connected to a vertical signal line) 2.
  • Second embodiment (example in which a signal line transistor electrically connected to a vertical signal line is switched to operate as a constant current transistor or switched to be connected to a diode-connected transistor) 3.
  • Third embodiment (example in which a constant current transistor is connected in parallel to a series circuit of a signal line transistor and a diode-connected transistor) 4.
  • Fourth embodiment (example in which a series transistor connected in series to a signal line transistor electrically connected to a vertical signal line operates as a diode-connected transistor or as a constant current transistor) 5.
  • Fifth embodiment (example where diode-connected transistors are shared by multiple columns) 6.
  • Sixth embodiment (example where drains of diode-connected transistors are shorted between multiple columns) 7.
  • Seventh embodiment (an example in which the number of series diode-connected transistors connected via a signal line transistor electrically connected to a vertical signal line can be switched) 8.
  • Eighth embodiment (an example in which a signal line transistor and a diode-connected transistor are provided in an upper layer chip where pixels are provided, and a constant current transistor is provided in a lower layer chip) 9.
  • Ninth embodiment (example in which capacitive load readout using a series circuit of a signal line transistor and a diode-connected transistor is applied to a cell in which an amplification transistor is shared by four photodiodes) 10.
  • Tenth embodiment (example where capacitive load readout using a series circuit of a signal line transistor and a diode-connected transistor is applied to binning readout) 11.
  • Eleventh embodiment (example in which capacitive load readout using a series circuit of a signal line transistor and a diode-connected transistor is applied to edge detection) 12.
  • Twelfth embodiment (example in which substrates on which a solid-state imaging device is formed are laminated) 13.
  • FIG. 1 is a block diagram showing a configuration example of a camera to which an imaging device according to a first embodiment is applied.
  • a camera 100 includes an optical system 101, a solid-state imaging device 102, an imaging control section 103, an image processing section 104, a storage section 105, a display section 106, and an operation section 107.
  • the imaging control section 103, the image processing section 104, the storage section 105, the display section 106, and the operation section 107 are connected to each other via a bus 108.
  • the camera 100 may be used alone, or may be incorporated into a mobile terminal such as a smartphone, or may be incorporated into an authentication device or a monitoring device.
  • the optical system 101 makes light from a subject enter the solid-state imaging device 102 and forms an image of the subject on the light-receiving surface of the solid-state imaging device 102.
  • the optical system 101 can include, for example, a focus lens, a zoom lens, an aperture, and the like.
  • Optical system 101 may include multiple lenses such as a wide-angle lens, a standard lens, and a telephoto lens.
  • the solid-state imaging device 102 converts light from a subject into an electrical signal for each pixel, digitizes the electrical signal, and outputs the digital signal.
  • the solid-state imaging device 102 may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device).
  • CMOS Complementary Metal Oxide Semiconductor
  • CCD Charge Coupled Device
  • the imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.
  • the image processing unit 104 performs image processing based on the output from the solid-state imaging device 102.
  • Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing.
  • the image processing unit 104 may include a processor that executes processing based on software.
  • the storage unit 105 stores captured images captured by the solid-state imaging device 102, and stores imaging parameters of the solid-state imaging device 102. Furthermore, the storage unit 105 can store a program for operating the camera 100 based on software.
  • the storage unit 105 may include a ROM (Read Only Memory), a RAM (Random Access Memory), and a memory card.
  • the display unit 106 displays captured images and various information that supports imaging operations.
  • the display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.
  • the operation unit 107 provides a user interface for operating the camera 100.
  • the operation unit 107 may include, for example, buttons, dials, and switches provided on the camera 100.
  • the operation unit 107 may be configured with a touch panel together with the display unit 106.
  • FIG. 2 is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment.
  • the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.
  • the pixel array section 111 includes a plurality of pixels 120.
  • the pixels 120 are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction).
  • Each pixel 120 can form a source follower with the column readout circuit 113 during signal readout.
  • Each pixel 120 is connected to a horizontal drive line 131 for each row and to a vertical signal line 132 for each column.
  • the horizontal drive line 131 drives each pixel 120 row by row when reading signals from each pixel 120.
  • the vertical signal line 132 transmits a potential based on accumulated charges according to a current flowing when reading a signal from the pixel 120 to the column signal processing unit 114 for each column. Note that the vertical signal line 132 is an example of a signal line described in the claims.
  • the vertical scanning circuit 112 scans the pixels 120 to be read in the column direction.
  • the vertical scanning circuit 112 may be configured using vertical registers.
  • the column readout circuit 113 can form a source follower with each pixel 120 when reading signals from each pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120. Column readout circuit 113 can support capacitive load readout. The column readout circuit 113 may also support constant current readout.
  • the column signal processing unit 114 processes signals transmitted from each pixel 120 in the column direction. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on signals transmitted from each pixel 120 in the column direction. Further, the column signal processing unit 114 can perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 120, and output the image pickup signal Gout.
  • CDS correlated double sampling
  • AD Analog to Digital
  • the horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction.
  • the horizontal scanning circuit 115 may be configured using a horizontal register.
  • the control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing section 114, and the horizontal scanning circuit 115.
  • the control circuit 116 can control the scan timing in the column direction, the scan timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing section 114.
  • FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.
  • a pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion 126.
  • MOS Metal Oxide Semiconductor
  • the amplification transistor 124 and the selection transistor 125 are connected in series.
  • a cathode of the photodiode 121 is connected to a floating diffusion 126 via a transfer transistor 122.
  • the floating diffusion 126 is connected to the power supply Vdd via the reset transistor 123.
  • the power supply Vdd is connected to the vertical signal line 132 via a series circuit of an amplification transistor 124 and a selection transistor 125.
  • the gate of amplification transistor 124 is connected to floating diffusion 126 .
  • a transfer signal ⁇ TG is applied to the gate of the transfer transistor 122.
  • a pixel reset signal ⁇ PRT is applied to the gate of the reset transistor 123.
  • a selection signal ⁇ SEL is applied to the gate of the selection transistor 125.
  • the transfer signal ⁇ TG, pixel reset signal ⁇ PRT, and selection signal ⁇ SEL can be transmitted to each pixel 120 via the horizontal drive line 131 in FIG.
  • the transfer transistor 122 When the transfer transistor 122 is turned on, the charges accumulated in the photodiode 121 are transferred to the floating diffusion 126. Then, when the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion 126. The source potential of the amplification transistor 124 is applied to the vertical signal line 132 via the selection transistor 125 and transmitted via the vertical signal line 132. Furthermore, when the reset transistor 123 is turned on, the charges accumulated in the floating diffusion 126 are discharged.
  • FIG. 4 is a cross-sectional view showing an example of the configuration of a pixel array section provided in the solid-state imaging device according to the first embodiment. Note that FIG. 4 shows an example of a front-illuminated solid-state imaging device. Further, FIG. 4 shows a configuration example for three pixels.
  • a photodiode 232 is formed on a semiconductor substrate 231 for each pixel 120.
  • the material of the semiconductor substrate 231 may be Si, InGaAs, or InP.
  • a gate electrode 214 and a wiring layer 210 are formed on the semiconductor substrate 231.
  • Gate electrode 214 is formed on semiconductor substrate 231 with gate insulating film 213 interposed therebetween.
  • a sidewall 215 is formed on the sidewall of the gate electrode 214 .
  • the material of the gate electrode 214 for example, polycrystalline silicon into which impurities are introduced can be used.
  • the material of the gate insulating film 213, for example, a silicon oxide film can be used.
  • the gate electrode 214 can be used for a pixel transistor.
  • the pixel transistors include the transfer transistor 122, reset transistor 123, amplification transistor 124, and selection transistor 125 in FIG.
  • a wiring 216 is formed on the gate electrode 214.
  • FIG. 4 shows an example of three-layer wiring.
  • the wiring 216 is provided with an opening OP1 that allows light to enter the photodiode 232.
  • Gate electrode 214 and wiring 216 are insulated via insulating layer 217.
  • insulating layer 217 For example, a silicon oxide film can be used as the insulating layer 217.
  • metal such as Al or Cu can be used as the material of the wiring 216.
  • a color filter 218 is formed on the wiring layer 210 for each pixel 120.
  • a microlens 219 is formed on the color filter 218 for each pixel 120.
  • transparent resin such as acrylic or polycarbonate can be used.
  • a pigment may be added to the color filter 218 for coloring.
  • the color filter 218 can have a Bayer array, for example.
  • FIG. 5 is a cross-sectional view showing a modification of the pixel array section provided in the solid-state imaging device according to the first embodiment. Note that FIG. 5 shows an example of a back-illuminated solid-state imaging device. Further, FIG. 5 shows a configuration example for three pixels.
  • a photodiode 222 is formed in a semiconductor layer 221 for each pixel 120.
  • the material of the semiconductor layer 221 may be Si, InGaAs, or InP.
  • the semiconductor layer 221 can be formed, for example, by thinning a semiconductor substrate on which the photodiode 222 is formed from the back side.
  • a gate electrode 224 and a wiring layer 220 are formed on the semiconductor layer 221.
  • Gate electrode 224 is formed on semiconductor layer 221 with gate insulating film 223 interposed therebetween.
  • a sidewall 225 is formed on the sidewall of the gate electrode 224 .
  • the gate electrode 224 can be used for a pixel transistor.
  • the pixel transistors include the transfer transistor 122, reset transistor 123, amplification transistor 124, and selection transistor 125 in FIG.
  • a wiring 226 is formed on the gate electrode 224.
  • FIG. 5 shows an example of three-layer wiring. Gate electrode 224 and wiring 226 are insulated via insulating layer 227.
  • the semiconductor layer 221 is supported on a support substrate 230 with an insulating layer 227 interposed therebetween.
  • the support substrate 230 may be a glass substrate, a Si substrate, or a sapphire substrate.
  • a color filter 228 is formed for each pixel 120 on the back side of the semiconductor layer 221.
  • a microlens 229 is formed on the color filter 228 for each pixel 120.
  • the color filter 228 can have a Bayer array, for example.
  • FIG. 6 is a diagram showing a configuration example of a signal readout circuit for one column according to the first embodiment.
  • an amplification transistor 124 is connected to a vertical signal line 132 via a selection transistor 125. Further, a capacitor 133 is added to the vertical signal line 132. This capacitance 133 may be a parasitic capacitance of the vertical signal line 132 or a capacitive element connected to the vertical signal line 132.
  • a signal line transistor 141 is electrically connected to the vertical signal line 132.
  • the signal line transistor 141 can reset the potential VSL of the vertical signal line 132.
  • a MOS transistor can be used as the signal line transistor 141.
  • a signal line reset signal ⁇ RT is applied to the gate of the signal line transistor 141.
  • a diode-connected transistor 142 is connected in series to the signal line transistor 141.
  • a MOS transistor can be used as the diode-connected transistor 142.
  • the gate of diode-connected transistor 142 is connected to the drain of diode-connected transistor 142.
  • the source of diode-connected transistor 142 is grounded.
  • the source of diode-connected transistor 142 may be connected to a potential higher than ground potential.
  • the diode-connected transistor 142 can generate a voltage higher than 0V (for example, 0.5V), and can set the potential VSL of the vertical signal line 132 to a potential higher than 0V via the signal line transistor 141.
  • the diode-connected transistor 142 is an example of a voltage generating section described in the claims.
  • the vertical signal line 132 is connected to an inverting input of a comparator 143 via a DC cut capacitor 144. At this time, the potential VSL of the vertical signal line 132 is applied to the inverting input of the comparator 143 via the DC cut capacitor 144.
  • a reference signal RAP is input to a non-inverting input of the comparator 143 via a DC cut capacitor 145. Reference signal RAP is, for example, a ramp signal.
  • the potential VSL of the vertical signal line 132 is set to a potential higher than 0V. Then, after the signal line transistor 141 is turned off, the selection transistor 125 is turned on, so that a signal is read out from the pixel 120, and the pixel current IPX flows to the vertical signal line 132 via the selection transistor 125. At this time, charges corresponding to the pixel current IPX are accumulated in the capacitor 133, and the potential VSL of the vertical signal line 132 changes based on the charges accumulated in the capacitor 133. Then, the comparator 143 compares the potential VSL of the vertical signal line 132 with the reference signal RAP, and outputs the comparison result COP.
  • FIG. 7 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the first embodiment.
  • pixel reset/VSL reset is performed in capacitive load readout (K11).
  • the pixel reset signal ⁇ PRT rises (t11)
  • the reset transistor 123 is turned on
  • the floating diffusion 126 is reset.
  • the reset level of the floating diffusion 126 can be set to the power supply potential Vdd.
  • the signal line reset signal ⁇ RT rises (t11)
  • the signal line transistor 141 is turned on
  • the vertical signal line 132 is reset.
  • the reset level of the vertical signal line 132 is set to a potential higher than 0V (for example, 0.5V) by the forward voltage VR1 of the diode-connected transistor 142.
  • 0V for example, 0.5V
  • the rising timing of the pixel reset signal ⁇ PRT and the rising timing of the signal line reset signal ⁇ RT do not necessarily have to be simultaneous, and may be shifted from each other.
  • the fall timing of the signal line reset signal ⁇ RT does not need to be later than the fall timing of the pixel reset signal ⁇ PRT, and is not particularly limited as long as it is before the rise of the selection signal ⁇ SEL.
  • P-phase VSL settling is performed (K12).
  • the signal line reset signal ⁇ RT falls, the selection signal ⁇ SEL rises (t12), and the selection transistor 125 is turned on.
  • a pixel current IPX corresponding to the reset level of the floating diffusion 126 flows to the vertical signal line 132 via the selection transistor 125.
  • charges corresponding to the pixel current IPX are accumulated in the capacitor 133, and the potential VSL of the vertical signal line 132 is set based on the charges accumulated in the capacitor 133.
  • P-phase AD is performed (K13).
  • the ramp signal is supplied to the comparator 143 as the reference signal RAP.
  • the potential VSL of the vertical signal line 132 according to the reset level is compared with the reference signal RAP, and the timing when the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 is determined as the comparison result COP.
  • the reset level read from the pixel 120 is AD converted based on a counting operation until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132.
  • transfer/VSL reset is performed (K14).
  • the transfer signal ⁇ TG rises (t14)
  • the transfer transistor 122 is turned on, and the charges accumulated in the photodiode 121 are transferred to the floating diffusion 126.
  • the signal line reset signal ⁇ RT rises (t14)
  • the signal line transistor 141 is turned on, and the vertical signal line 132 is reset.
  • the reset level of the vertical signal line 132 is set to a potential higher than 0V (for example, 0.5V) by the forward voltage VR1 of the diode-connected transistor 142.
  • the rising timing of the transfer signal ⁇ TG and the rising timing of the signal line reset signal ⁇ RT do not necessarily have to be simultaneous, and may be shifted from each other. Further, the fall timing of the signal line reset signal ⁇ RT does not need to be later than the fall timing of the transfer signal ⁇ TG, and is not particularly limited as long as it is before the rise of the selection signal ⁇ SEL.
  • D-phase VSL settling is performed (K15).
  • the signal line reset signal ⁇ RT falls, the selection signal ⁇ SEL rises (t15), and the selection transistor 125 is turned on.
  • a pixel current IPX corresponding to the signal level of the floating diffusion 126 flows to the vertical signal line 132 via the selection transistor 125.
  • charges corresponding to the pixel current IPX are accumulated in the capacitor 133, and the potential VSL of the vertical signal line 132 is set based on the charges accumulated in the capacitor 133.
  • D-phase AD is performed (K16).
  • the selection signal ⁇ SEL falls (t16), and the ramp signal is supplied to the comparator 143 as the reference signal RAP (t16-t17).
  • the comparator 143 the potential VSL of the vertical signal line 132 according to the signal level is compared with the reference signal RAP, and the timing when the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 is determined as the comparison result COP.
  • the signal level read from the pixel 120 is AD converted based on a counting operation until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132.
  • FIG. 8 is a diagram illustrating an example of a circuit configuration of a voltage generation section connected to a vertical signal line of the imaging device according to the first embodiment.
  • the voltage generation section connected to the vertical signal line 132 may include a signal line transistor 141 and a diode-connected transistor 142.
  • the diode-connected transistor 142 may be an NMOS transistor.
  • the signal line transistor 141 may be connected to the drain side of the diode-connected transistor 142.
  • the voltage generation section connected to the vertical signal line 132 may include a signal line transistor 141 and a diode-connected transistor 142. At this time, the signal line transistor 141 may be connected to the source side of the diode-connected transistor 142.
  • the voltage generation section connected to the vertical signal line 132 may include a signal line transistor 141 and a diode-connected transistor 146.
  • the diode-connected transistor 146 may be a PMOS transistor.
  • the signal line transistor 141 may be connected to the drain side of the diode-connected transistor 146, or the signal line transistor 141 may be connected to the source side of the diode-connected transistor 146.
  • the voltage generation section connected to the vertical signal line 132 may include a signal line transistor 141 and a PN junction diode 147.
  • the signal line transistor 141 may be connected to the anode side of the PN junction diode 147, or the signal line transistor 141 may be connected to the cathode side of the PN junction diode 147.
  • the voltage generation section connected to the vertical signal line 132 may include a signal line transistor 141 and voltage dividing resistors 148 and 149. Voltage dividing resistors 148 and 149 are connected in series with each other. Further, the source of the signal line transistor 141 is connected to a connection point between voltage dividing resistors 148 and 149.
  • the resistance values of the voltage dividing resistors 148 and 149 may be increased.
  • the potential of the vertical signal line 132 can be raised according to the forward voltage VR1 of the diode-connected transistor 142 when the vertical signal line 132 is reset. Therefore, the potential of the vertical signal line 132 at the start of P-phase VSL settling can be made higher than 0V, and the settling time can be shortened.
  • the diode-connected transistor 142 is connected via the signal line transistor 141 electrically connected to the vertical signal line 132.
  • the signal line transistor 141 electrically connected to the vertical signal line 132 is switched to operate as a constant current transistor or switched to be connected to the diode-connected transistor 142.
  • FIG. 9 is a block diagram illustrating an example of switching during capacitive load reading of the signal readout circuit for one column according to the second embodiment.
  • this signal readout circuit has a sample and hold circuit 201 and switches 202 and 203 added to the signal readout circuit of the first embodiment described above.
  • the other configuration of the signal readout circuit of the second embodiment is the same as that of the signal readout circuit of the first embodiment described above.
  • the sample and hold circuit 201 samples and holds the bias voltage Vb that causes the signal line transistor 141 to operate as a constant current transistor, and applies it to the gate of the signal line transistor 141.
  • Sample and hold circuit 201 includes a transistor 211 and a capacitor 212.
  • Transistor 211 may be a MOS transistor.
  • a sample and hold signal ⁇ SH is applied to the gate of the transistor 211.
  • Capacitor 212 is connected between the source of transistor 211 and ground potential.
  • the switch 202 switches the gate input of the signal line transistor 141 between the signal line reset signal ⁇ RT and the output of the sample and hold circuit 201.
  • the switch 203 switches the connection destination of the signal line transistor 141 between the ground potential and the diode-connected transistor 142.
  • the switch 202 switches the gate input of the signal line transistor 141 to the signal line reset signal ⁇ RT. Further, the switch 203 switches the connection destination of the signal line transistor 141 to the diode-connected transistor 142. At this time, the operation of the signal readout circuit is similar to that in FIG.
  • FIG. 10 is a block diagram showing an example of switching during constant current readout of the signal readout circuit for one column according to the second embodiment.
  • a switch 202 switches the gate input of the signal line transistor 141 to the output of the sample and hold circuit 201.
  • the bias voltage Vb is set so that the signal line transistor 141 is turned on.
  • the switch 203 switches the connection destination of the signal line transistor 141 to the ground potential.
  • FIG. 11 is a diagram showing an example of waveforms of various parts during constant current readout of the signal readout circuit according to the second embodiment.
  • the transistor 211 in constant current readout, the transistor 211 is turned on and the bias voltage Vb is sampled and held in order to prevent horizontal scanning noise during AD conversion. Then, the transistor 211 is turned off and the bias voltage Vb sampled and held by the sample and hold circuit 201 is applied to the gate of the signal line transistor 141, so that the signal line transistor 141 operates as a constant current transistor.
  • pixel reset is performed (K21).
  • the pixel reset signal ⁇ PRT rises (t21)
  • the reset transistor 123 is turned on
  • the floating diffusion 126 is reset.
  • the selection signal ⁇ SEL rises (t21)
  • the selection transistor 125 is turned on.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the power supply potential Vdd is applied to the gate of the amplification transistor 124.
  • P-phase AD is performed (K23).
  • the ramp signal is supplied to the comparator 143 as the reference signal RAP.
  • the potential VSL of the vertical signal line 132 according to the reset level is compared with the reference signal RAP, and the timing when the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 is determined as the comparison result COP.
  • the reset level read from the pixel 120 is AD converted based on a counting operation until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132.
  • transfer is performed (K24).
  • the transfer signal ⁇ TG rises (t24)
  • the transfer transistor 122 is turned on, and the charges accumulated in the photodiode 121 are transferred to the floating diffusion 126.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the cathode potential of the photodiode 121 is applied to the gate of the amplification transistor 124.
  • D-phase VSL settling is performed (K25).
  • the transfer signal ⁇ TG falls (t25) and the transfer transistor 122 is turned off.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the signal level of the floating diffusion 126 is applied to the gate of the amplification transistor 124.
  • P-phase AD is performed (K26).
  • the ramp signal is supplied to the comparator 143 as the reference signal RAP (t26-t27).
  • the potential VSL of the vertical signal line 132 according to the signal level is compared with the reference signal RAP, and the timing when the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 is determined as the comparison result COP.
  • the signal level read from the pixel 120 is AD converted based on a counting operation until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132.
  • the signal line transistor 141 can be used to reset the vertical signal line 132, or the signal line transistor 141 can be used as a constant current transistor. This makes it possible to switch between capacitive load readout and constant current readout, and it is possible to operate the imaging device with low power consumption or at high speed depending on how the imaging device is used.
  • Third embodiment In the second embodiment described above, it is possible to switch between constant current readout and capacitive load readout based on the switching operations of switches 202 and 203.
  • a constant current transistor is connected in parallel to a series circuit of a signal line transistor 141 and a diode-connected transistor 142 in order to enable switching between constant current readout and capacitive load readout.
  • FIG. 12 is a diagram showing a configuration example of a signal readout circuit for one column according to the third embodiment.
  • this signal readout circuit has a sample hold circuit 201 and a constant current transistor 301 added to the signal readout circuit of the first embodiment described above.
  • the other configuration of the signal readout circuit of the third embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the constant current transistor 301 is electrically connected to the vertical signal line 132.
  • Constant current transistor 301 may be a MOS transistor.
  • the output of sample hold circuit 201 is connected to the gate of constant current transistor 301.
  • bias voltage Vb is set to 0V and sample hold signal ⁇ SH is set to high level.
  • the constant current transistor 301 is turned off, and no current flows through the constant current transistor 301.
  • the operation of the signal readout circuit at this time is similar to that in FIG.
  • the transistor 211 In constant current reading, the transistor 211 is turned on and the bias voltage Vb is sampled and held. Then, the transistor 211 is turned off, and the bias voltage Vb sampled and held by the sample and hold circuit 201 is applied to the gate of the constant current transistor 301. In this case, the constant current transistor 301 is turned on, and a constant current flows through the constant current transistor 301.
  • the operation of the signal readout circuit at this time is similar to that in FIG.
  • the constant current transistor 301 is connected in parallel to the series circuit of the signal line transistor 141 and the diode-connected transistor 142. This makes it possible to switch between constant current readout and capacitive load readout without providing switches 202 and 203, and to shorten the settling time during capacitive load readout.
  • the constant current transistor 301 is connected in parallel to the series circuit of the signal line transistor 141 and the diode-connected transistor 142 in order to enable switching between constant current reading and capacitive load reading.
  • the gate of a series transistor connected in series to a signal line transistor 141 electrically connected to a vertical signal line 132 is used.
  • a switching transistor is connected between the and the drain.
  • FIG. 13 is a diagram showing a configuration example of a signal readout circuit for one column according to the fourth embodiment.
  • this signal readout circuit is provided with a series transistor 402 in place of the diode-connected transistor 142 of the signal readout circuit of the first embodiment described above. Further, this signal readout circuit has a sample hold circuit 201 and an open/close transistor 401 added to the signal readout circuit of the first embodiment described above.
  • the other configuration of the signal readout circuit of the fourth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the series transistor 402 is connected in series to the signal line transistor 141.
  • a switching transistor 401 is connected between the gate and drain of the series transistor 402.
  • a switching signal DSF is applied to the gate of the switching transistor 401.
  • the series transistor 402 and the switching transistor 401 may be MOS transistors.
  • the switching signal DSF is set to a high level, and the switching transistor 401 is turned on.
  • the gate and drain of the series transistor 402 are short-circuited, and the series transistor 402 operates as a diode-connected transistor.
  • the sample hold signal ⁇ SH is set to low level, and the transistor 211 is turned off. The operation of the signal readout circuit at this time is similar to that in FIG.
  • the switching signal DSF is set to low level, and the switching transistor 401 is turned off. Further, the transistor 211 is turned on and the bias voltage Vb is sampled and held. Then, the transistor 211 is turned off, and the bias voltage Vb sampled and held by the sample and hold circuit 201 is applied to the gate of the series transistor 402. In this case, the series transistor 402 is turned on and a constant current flows through the series transistor 402.
  • the operation of the signal readout circuit at this time is similar to that in FIG.
  • the series transistor 402 is connected in series to the signal line transistor 141, and the opening/closing transistor 401 is connected between the gate and drain of the series transistor 402. This makes it possible to switch between constant current readout and capacitive load readout without providing switches 202 and 203, and to shorten the settling time during capacitive load readout.
  • diode-connected transistors 142 are provided for each column.
  • a diode-connected transistor 142 is shared by a plurality of columns.
  • FIG. 14 is a diagram showing a configuration example of a signal readout circuit for two columns according to the fifth embodiment.
  • this signal readout circuit is provided with a plurality of vertical signal lines 132-1 and 132-2, and switches 501 and 502 are added to the signal readout circuit of the above-described first embodiment.
  • the rest of the configuration of the signal readout circuit of the fifth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the pixels 120 are connected to the vertical signal lines 132-1 and 132-2, and a comparator 143 is provided for each of the vertical signal lines 132-1 and 132-2. Further, a signal line transistor 141 is connected to each vertical signal line 132-1 and 132-2, and switches 501 and 502 are provided for each vertical signal line 132-1 and 132-2.
  • the switch 501 switches the connection destination of the signal line transistor 141 connected to the vertical signal line 132-1 between the ground potential and the diode-connected transistor 142.
  • the switch 502 switches the connection destination of the signal line transistor 141 connected to the vertical signal line 132-2 between the ground potential and the diode-connected transistor 142.
  • the diode-connected transistor 142 can be shared by a plurality of columns. I can do it.
  • the comparator 143 connected to the vertical signal line 132-1 compares the potential VSL1 of the vertical signal line 132-1 with the reference signal RAP, and outputs the comparison result COP1.
  • a comparator 143 connected to the vertical signal line 132-2 compares the potential VSL2 of the vertical signal line 132-2 with the reference signal RAP, and outputs the comparison result COP2.
  • the diode-connected transistor 142 is shared by a plurality of columns. This makes it possible to increase the number of columns while suppressing an increase in the number of diode-connected transistors 142.
  • the reset level of the vertical signal line 132 is set for each column.
  • the reset level of the vertical signal line 132 is set commonly for a plurality of columns.
  • FIG. 15 is a diagram showing a configuration example of a signal readout circuit for four columns according to the sixth embodiment.
  • this signal readout circuit is provided with a plurality of vertical signal lines 132-1 to 132-4, and a shorting line 601 is added to the signal readout circuit of the first embodiment described above.
  • the rest of the configuration of the signal readout circuit of the sixth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • a pixel 120 is connected to each vertical signal line 132-1 to 132-4, and a comparator 143 is provided for each vertical signal line 132-1 to 132-4. Further, a diode-connected transistor 142 is connected to each of the vertical signal lines 132-1 to 132-4 via a signal line transistor 141, respectively. Furthermore, the drains of the diode-connected transistors 142 provided for each of the vertical signal lines 132-1 to 132-4 are connected to each other via a shorting line 601.
  • the comparator 143 connected to the vertical signal line 132-1 compares the potential VSL1 of the vertical signal line 132-1 with the reference signal RAP, and outputs the comparison result COP1.
  • a comparator 143 connected to the vertical signal line 132-2 compares the potential VSL2 of the vertical signal line 132-2 with the reference signal RAP, and outputs the comparison result COP2.
  • a comparator 143 connected to the vertical signal line 132-3 compares the potential VSL3 of the vertical signal line 132-3 with the reference signal RAP, and outputs the comparison result COP3.
  • a comparator 143 connected to the vertical signal line 132-4 compares the potential VSL4 of the vertical signal line 132-4 with the reference signal RAP, and outputs the comparison result COP4.
  • the drains of diode-connected transistors 142 in different columns are connected to each other via the shorting line 601.
  • capacitive load reading can be performed for each column while reducing variations in the reset level of the vertical signal line 132 from column to column.
  • the reset level of the vertical signal line 132 is fixed to one value for P-phase VSL settling and D-phase VSL settling.
  • the reset level of the vertical signal line 132 can be switched between P-phase VSL settling and D-phase VSL settling.
  • FIG. 16 is a diagram showing a configuration example of a signal readout circuit for one column according to the seventh embodiment.
  • this signal readout circuit has a switch 701 and diode-connected transistors 702 and 703 added to the signal readout circuit of the first embodiment described above.
  • the rest of the configuration of the signal readout circuit of the seventh embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • Diode-connected transistors 702 and 703 are connected in series with each other.
  • Switch 701 switches the connection destination of signal line transistor 141 between diode-connected transistor 142 and a series circuit of diode-connected transistors 702 and 703.
  • the reset level of the vertical signal line 132 can be raised by the forward voltage VR1 of the diode-connected transistor 142.
  • the reset level of vertical signal line 132 can be raised by the sum VR2 of the forward voltages of each diode-connected transistor 702 and 703.
  • FIG. 17 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the seventh embodiment.
  • the capacitive load read operation is the same as in FIG. 7.
  • the signal line transistor 141 is connected to the series circuit of diode-connected transistors 702 and 703.
  • the reset level of the vertical signal line 132 is set to the sum VR2 of the forward voltages of the respective diode-connected transistors 702 and 703.
  • the transfer/VSL reset (K14) before the D-phase AD (K16) the signal line transistor 141 is connected to the diode-connected transistor 142.
  • the reset level of the vertical signal line 132 is set to the forward voltage VR1 of the diode-connected transistor 142.
  • the reset level of the vertical signal line 132 during P-phase VSL settling is set higher than the reset level of the vertical signal line 132 during D-phase VSL settling. This makes it possible to shorten the settling time before P-phase AD (K13) in capacitive load reading. Further, the potential VSL of the vertical signal line 132 when a large amount of light is incident can be clipped by the sum VR2 of the forward voltages of the respective diode-connected transistors 702 and 703, and the sunspot phenomenon can be prevented. .
  • a series circuit of diode-connected transistors 702 and 703 is provided in order to make it possible to switch the reset level of the vertical signal line 132.
  • a series circuit of three or more stages of diode-connected transistors may be provided.
  • the configuration in which the reset level of the vertical signal line 132 can be switched may be applied to any of the configurations of the second to sixth embodiments described above.
  • the diode-connected transistor 142 is connected via the signal line transistor 141 that is electrically connected to the vertical signal line 132 that transmits the signal read out from the pixel 120.
  • a signal line transistor 141 and a diode-connected transistor 142 are provided in the upper layer chip in which the pixel 120 is provided, and a constant current transistor 301 is provided in the lower layer chip.
  • FIG. 18 is a diagram showing a configuration example of a signal readout circuit for one column according to the eighth embodiment.
  • this signal readout circuit is similar to the circuit configuration of the signal readout circuit in FIG. However, this signal readout circuit is formed on a stacked chip.
  • This stacked chip includes an upper layer chip 801 and a lower layer chip 802. Upper layer chip 801 is stacked on lower layer chip 802 .
  • a pixel 120, a vertical signal line 132, a signal line transistor 141, and a diode-connected transistor 142 are formed on the upper layer chip 801.
  • the size and threshold of the signal line transistor 141 can be set similarly to the size and threshold of the selection transistor 125.
  • the size and threshold of diode-connected transistor 142 can be set similarly to the size and threshold of reset transistor 123.
  • a sample and hold circuit 201, a constant current transistor 301, and a comparator 143 are formed in the lower chip 802. At this time, the vertical signal line 132 can be wired from the upper layer chip 801 to the lower layer chip 802.
  • the signal line transistor 141 and the diode-connected transistor 142 are formed in the upper layer chip 801 on which the pixel 120 is formed. Thereby, variations in the characteristics of the pixel transistor provided in the pixel 120 can be made equal to variations in the characteristics of the signal line transistor 141 and the diode-connected transistor 142. Furthermore, the configuration in which the signal readout circuit is formed on a stacked chip may be applied to any of the configurations of the second to seventh embodiments described above.
  • capacitive load readout is applied to the pixel 120 in which one photodiode 121 is provided for one amplification transistor 124.
  • capacitive load readout is applied to a cell in which four photodiodes are provided for one amplification transistor 124.
  • FIG. 19 is a diagram showing a configuration example of a signal readout circuit for one column according to the ninth embodiment.
  • this signal readout circuit is provided with a cell 130 in place of the pixel 120 of the signal readout circuit of the first embodiment described above.
  • the rest of the configuration of the signal readout circuit of the ninth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • the cell 130 is provided with photodiodes 121-1 to 121-4 and transfer transistors 122-1 to 122-4 in place of the photodiode 121 and transfer transistor 122 of the first embodiment described above.
  • the other configuration of the cell 130 of the ninth embodiment is similar to the configuration of the pixel 120 of the first embodiment described above.
  • Each photodiode 121-1 to 121-4 can be arranged in two rows and two columns. Each of the photodiodes 121-1 to 121-4 is connected to the floating diffusion 126 via transfer transistors 122-1 to 122-4, respectively. Transfer signals ⁇ TG1 to ⁇ TG4 are applied to the gates of each of the transfer transistors 122-1 to 122-4. By controlling the application timing of the transfer signals ⁇ TG1 to ⁇ TG4, signals can be read out individually from each photodiode 121-1 to 121-4 to the vertical signal line 132.
  • the capacitive load reading operation from each photodiode 121-1 to 121-4 is similar to that in FIG.
  • one amplification transistor 124 shares four photodiodes. Thereby, it is possible to increase the number of pixels while suppressing an increase in the pixel area, and it is also possible to apply capacitive load readout to each pixel.
  • capacitive load readout is applied to read out individual signals from the pixels 120 connected to the vertical signal line 132.
  • capacitive load readout is applied to binning readout from pixels 120 connected to vertical signal line 132.
  • FIG. 20 is a diagram showing a configuration example of a signal readout circuit for one column according to the tenth embodiment.
  • this signal readout circuit is provided with pixels 140 and 150 in place of the pixel 120 of the signal readout circuit of the first embodiment described above. Further, in this signal readout circuit, a binning line 134 is added to the signal readout circuit of the first embodiment described above. The rest of the configuration of the signal readout circuit of the tenth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • Each pixel 140 and 150 has a binning transistor 127 added to the pixel 120 of the first embodiment described above.
  • the other configurations of each pixel 140 and 150 in the tenth embodiment are similar to the configuration of the pixel 120 in the first embodiment described above.
  • a binning transistor 127 is connected between the floating diffusion 126 and the binning line 134 for each pixel 140 and 150.
  • Binning transistor 127 may be a MOS transistor.
  • Binning signals ⁇ BN1 and ⁇ BN2 are applied to the gate of the binning transistor 127 for each pixel 140 and 150.
  • Transfer signals ⁇ TG1 and ⁇ TG2 are applied to the gate of the transfer transistor 122 for each pixel 140 and 150.
  • Pixel reset signals ⁇ PRT1 and ⁇ PRT2 are applied to the gate of the reset transistor 123 for each pixel 140 and 150.
  • Selection signals ⁇ SEL1 and ⁇ SEL2 are applied to the gate of the selection transistor 125 for each pixel 140 and 150.
  • each binning signal ⁇ BN1 and ⁇ BN2 When reading signals from each pixel 140 and 150 individually, each binning signal ⁇ BN1 and ⁇ BN2 is set to low level, and the binning transistor 127 of each pixel 140 and 150 is turned off. When reading the signals of each pixel 140 and 150 by binning, each binning signal ⁇ BN1 and ⁇ BN2 is set to a high level, and the binning transistor 127 of each pixel 140 and 150 is turned on.
  • the capacitive load readout operation from each pixel 140 and 150 is similar to that in FIG. At this time, in the binning readout, either one of the selection transistors 125 of each pixel 140 and 150 may be turned on, or both of the selection transistors 125 of each pixel 140 and 150 may be turned on.
  • the binning transistors 127 are provided in the pixels 140 and 150 connected to the vertical signal line 132. Thereby, capacitive load reading can be applied while reducing the number of times each frame is read, and power consumption can be reduced.
  • the signal read from the pixel 120 is detected based on the potential VSL of the vertical signal line 132 connected to the pixel 120.
  • edge detection is performed based on the comparison result of the potentials of the vertical signal lines based on load capacitance reading from different columns.
  • FIG. 21 is a diagram showing a configuration example of a signal readout circuit for two columns according to the eleventh embodiment.
  • this signal readout circuit includes a plurality of vertical signal lines 132-1 and 132-2, and comparators 143-1 and 143-2 in place of the comparator 143 of the first embodiment described above. Be prepared.
  • the rest of the configuration of the signal readout circuit of the eleventh embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
  • Pixels 120-1 and 120-2 are connected to each vertical signal line 132-1 and 132-2, respectively, and vertical signal lines 132-1 and 132-2 are connected to each comparator 143-1 and 143-2. 2 are connected together.
  • Each pixel 120-1 and 120-2 can be configured similarly to pixel 120 in FIG. 6.
  • Each pixel 120-1 and 120-2 is connected to vertical signal lines 132-1 and 132-2, respectively.
  • a diode-connected transistor 142 is connected to each vertical signal line 132-1 and 132-2 via a signal line transistor 141.
  • Each comparator 143-1 and 143-2 compares potentials VLS1 and VLS2 of each vertical signal line 132-1 and 132-2. Then, if the difference between the potentials VLS1 and VLS2 of each vertical signal line 132-1 and 132-2 is equal to or greater than a threshold value, it can be determined that an edge exists.
  • FIG. 22 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the eleventh embodiment.
  • the capacitive load read operation is the same as in FIG. 7.
  • pixel currents IPX1 and IPX2 flow through vertical signal lines 132-1 and 132-2, respectively, when reading signals from pixels 120-1 and 120-2.
  • charges corresponding to each pixel current IPX1 and IPX2 are accumulated in the capacitor 133 for each vertical signal line 132-1 and 132-2.
  • the potentials VSL1 and VSL2 of each vertical signal line 132-1 and 132-2 change according to the charges accumulated in the capacitor 133 of each vertical signal line 132-1 and 132-2, and the potentials VSL1 and VSL2 of each vertical signal line 132-1 and 132-2 change, and 143-2.
  • each comparator 143-1 and 143-2 when the comparison signal COT rises (t16), the potentials VSL1 and VSL2 of each vertical signal line 132-1 and 132-2 are compared, and the comparison result is output. .
  • each comparator 143-1 and 143-2 detects the difference between the potentials VLS1 and VLS2 of each vertical signal line 132-1 and 132-2 based on load capacitance reading. do. This makes it possible to detect edges of a subject while reducing power consumption.
  • the diode-connected transistor 142 is connected to the signal line transistor 141 that is electrically connected to the vertical signal line 132 that transmits the signal read out from the pixel 120.
  • substrates on which a solid-state imaging device including a pixel array section in which pixels 120 are arranged in a matrix are formed are laminated.
  • FIG. 23 is a perspective view showing a configuration example of an imaging device according to the twelfth embodiment.
  • the solid-state imaging device 901 includes a support substrate 911 and a semiconductor substrate 912.
  • a semiconductor substrate 912 is stacked on a support substrate 911.
  • a pixel array section 913 and a peripheral circuit 914 are formed on the semiconductor substrate 912.
  • a column readout circuit 915 and a column ADC 916 are formed in the peripheral circuit 914.
  • the column readout circuit 915 and the column ADC 916 may be formed on both sides of the pixel array section 913 in the column direction.
  • pixels 120 are arranged in a matrix along the row and column directions.
  • Column readout circuit 915 can read signals from each pixel 120 based on capacitive load readout.
  • the signal line reset transistor 141 and diode-connected transistor 142 in FIG. 6 may be formed in the column readout circuit 915.
  • the column ADC 916 can AD convert signals read out via the column readout circuit 915 for each column.
  • the solid-state imaging device 901 can constitute a back-illuminated image sensor.
  • the solid-state imaging device 902 includes semiconductor substrates 921 and 922.
  • a semiconductor substrate 922 is stacked on the semiconductor substrate 921.
  • a pixel array section 923 is formed on the semiconductor substrate 922.
  • a peripheral circuit 924 is formed on the semiconductor substrate 922 .
  • a column readout circuit 925 and a column ADC 926 are formed.
  • the column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction.
  • the solid-state imaging device 902 can constitute a back-illuminated image sensor.
  • the substrates on which the solid-state imaging devices 901 and 902 are formed are laminated.
  • the semiconductor substrates 912 and 922 on which each pixel array section 913 and 923 are formed can be thinned, and a back-illuminated image sensor can be formed. can.
  • the technology according to the present disclosure (this technology) can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as a car, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, robot, etc. It's okay.
  • FIG. 24 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output section 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 includes a drive force generation device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits the drive force to wheels, and a drive force transmission mechanism that controls the steering angle of the vehicle. It functions as a control device for a steering mechanism to adjust and a braking device to generate braking force for the vehicle.
  • the body system control unit 12020 controls the operations of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a turn signal, or a fog lamp.
  • radio waves transmitted from a portable device that replaces a key or signals from various switches may be input to the body control unit 12020.
  • the body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, power window device, lamp, etc. of the vehicle.
  • the external information detection unit 12030 detects information external to the vehicle in which the vehicle control system 12000 is mounted.
  • an imaging section 12031 is connected to the outside-vehicle information detection unit 12030.
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the external information detection unit 12030 may perform object detection processing such as a person, car, obstacle, sign, or text on the road surface or distance detection processing based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electrical signal as an image or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • a driver condition detection section 12041 that detects the condition of the driver is connected to the in-vehicle information detection unit 12040.
  • the driver condition detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver condition detection unit 12041. It may be calculated, or it may be determined whether the driver is falling asleep.
  • the microcomputer 12051 calculates control target values for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, Control commands can be output to 12010.
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or shock mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or shock mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of autonomous driving, etc., which does not rely on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of preventing glare, such as switching from high beam to low beam. It can be carried out.
  • the audio and image output unit 12052 transmits an output signal of at least one of audio and images to an output device that can visually or audibly notify information to the occupants of the vehicle or to the outside of the vehicle.
  • an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 25 is a diagram showing an example of the installation position of the imaging section 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle 12100.
  • An imaging unit 12101 provided in the front nose and an imaging unit 12105 provided above the windshield inside the vehicle mainly acquire images in front of the vehicle 12100.
  • Imaging units 12102 and 12103 provided in the side mirrors mainly capture images of the sides of the vehicle 12100.
  • An imaging unit 12104 provided in the rear bumper or back door mainly captures images of the rear of the vehicle 12100.
  • the imaging unit 12105 provided above the windshield inside the vehicle is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 25 shows an example of the imaging range of the imaging units 12101 to 12104.
  • An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • an imaging range 12114 shows the imaging range of the imaging unit 12101 provided on the front nose.
  • the imaging range of the imaging unit 12104 provided in the rear bumper or back door is shown. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of image sensors, or may be an image sensor having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. In particular, by determining the three-dimensional object that is closest to the vehicle 12100 on its path and that is traveling at a predetermined speed (for example, 0 km/h or more) in approximately the same direction as the vehicle 12100, it is possible to extract the three-dimensional object as the preceding vehicle. can.
  • a predetermined speed for example, 0 km/h or more
  • the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for the purpose of autonomous driving, etc., in which the vehicle travels autonomously without depending on the driver's operation.
  • the microcomputer 12051 transfers three-dimensional object data to other three-dimensional objects such as two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, and utility poles based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceeds a set value and there is a possibility of a collision, the microcomputer 12051 transmits information via the audio speaker 12061 and the display unit 12062. By outputting a warning to the driver via the vehicle control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
  • the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceed
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101 to 12104.
  • pedestrian recognition involves, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and a pattern matching process is performed on a series of feature points indicating the outline of an object to determine whether it is a pedestrian or not.
  • the audio image output unit 12052 creates a rectangular outline for emphasis on the recognized pedestrian.
  • the display unit 12062 is controlled to display the .
  • the audio image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above.
  • the above-described camera 100 can be applied to the imaging unit 12031.
  • the present technology can also have the following configuration.
  • a signal line whose potential changes based on the charge accumulated in accordance with the current flowing when reading signals from the pixel; a signal line transistor electrically connected to the signal line;
  • An imaging device comprising: a voltage generation section connected in series to the signal line transistor and capable of generating a voltage higher than 0V.
  • the pixel is photodiode and a transfer transistor that transfers the charge accumulated in the photodiode to a floating diffusion; a reset transistor that resets the floating diffusion; an amplification transistor that outputs a signal according to the potential of the floating diffusion;
  • the voltage generation section includes a diode-connected transistor.
  • the voltage generation section includes a plurality of diode-connected transistors having different numbers of series connections.
  • the voltage generation unit sets the reset level of the signal line when the reset level is read from the pixel to be equal to or higher than the reset level of the signal line when the signal level is read from the pixel (1).
  • the imaging device according to any one of (5) to (5).
  • An imaging device In constant current reading using the constant current transistor, the constant current transistor is turned on; The imaging device according to (9), wherein the constant current transistor is turned off in capacitive load reading using the voltage generation section. (11) a sample hold circuit that operates the signal line transistor as a constant current transistor; The imaging device according to any one of (1) to (8), further comprising a switch that switches a connection destination of the signal line transistor between the voltage generation section and a ground potential.
  • connection destination of the signal line transistor is switched to the ground potential, and the signal line transistor is turned on;
  • the voltage generation section a series transistor connected in series to the signal line transistor;
  • the switching transistor is turned off, The imaging device according to (13), wherein the switching transistor is turned on in capacitive load reading.

Abstract

This invention enables capacitive load reading, while suppressing the increases of the current consumption and of the settling time.　This imaging device comprises: a signal line the potential of which changes on the basis of a charge stored in accordance with a current flowing during signal reading from a pixel; a signal line transistor that is electrically connected to the signal line; and a voltage generation unit that is series connected to the signal line transistor and that can generate a voltage higher than 0V. The pixel may comprise: a photodiode; a transfer transistor that transfers a charge stored in the photodiode to a floating diffusion; a reset transistor that resets the floating diffusion; an amplification transistor that outputs a signal in accordance with the potential of the floating diffusion; and a selection transistor that is connected between the amplification transistor and the signal line.

Description

撮像装置Imaging device
　本技術は、撮像装置に関する。詳しくは、本技術は、容量負荷読出しが可能な撮像装置に関する。 The present technology relates to an imaging device. Specifically, the present technology relates to an imaging device capable of capacitive load reading.
　画素からの信号の読出し時にソースフォロワの負荷に容量を用いる容量負荷読出し方式が知られている。このような容量負荷読出し方式として、例えば、リセット部により出力線の電圧をリセットした後に定電流源により出力線に一定の電流を流すとともに、増幅トランジスタのソースを出力線に接続する撮像装置が提案されている（例えば、特許文献１参照）。 A capacitive load readout method is known in which a capacitor is used as the load of a source follower when reading signals from a pixel. As such a capacitive load readout method, for example, an imaging device has been proposed in which a reset unit resets the voltage of the output line, and then a constant current source causes a constant current to flow through the output line, and the source of the amplification transistor is connected to the output line. (For example, see Patent Document 1).
特開２０２１－４０２７０号公報JP2021-40270A
　しかしながら、上述の従来技術では、リセット部により出力線の電圧をリセットするために、出力線リセット電圧を生成する出力線リセット電圧生成回路が設けられ、その分の消費電流が増大するおそれがあった。一方、出力線リセット電圧生成回路を省略し、出力線リセット電圧を接地電圧に設定すると、セトリング時間の増大を招くおそれがあった。 However, in the above-mentioned conventional technology, an output line reset voltage generation circuit that generates an output line reset voltage is provided in order to reset the voltage of the output line by the reset section, which may increase current consumption. . On the other hand, if the output line reset voltage generation circuit is omitted and the output line reset voltage is set to the ground voltage, there is a risk that the settling time will increase.
　本技術はこのような状況に鑑みて生み出されたものであり、消費電流およびセトリング時間の増大を抑制しつつ、容量負荷読出しを可能とすることを目的とする。 The present technology was created in view of this situation, and its purpose is to enable capacitive load reading while suppressing increases in current consumption and settling time.
　本技術は、上述の問題点を解消するためになされたものであり、その第１の側面は、画素からの信号読出し時に流れる電流に応じて蓄積された電荷に基づいて電位が変化する信号線と、前記信号線に電気的に接続された信号線トランジスタと、前記信号線トランジスタに直列に接続され、０Ｖより高い電圧を生成可能な電圧生成部とを具備する撮像装置である。これにより、信号線のリセット時に信号線が０Ｖより高い電圧に設定されるという作用をもたらす。 This technology was developed to solve the above-mentioned problems, and its first aspect is that the signal line has a potential that changes based on the electric charge accumulated in accordance with the current that flows when reading signals from the pixel. The imaging device includes: a signal line transistor electrically connected to the signal line; and a voltage generation section connected in series to the signal line transistor and capable of generating a voltage higher than 0V. This brings about the effect that the signal line is set to a voltage higher than 0V when the signal line is reset.
　また、第１の側面において、前記信号線の電位は、前記信号線の寄生容量の電位でもよい。これにより、信号線に容量素子を付加することなく、容量負荷読出しが可能となるという作用をもたらす。 Furthermore, in the first aspect, the potential of the signal line may be a potential of a parasitic capacitance of the signal line. This brings about the effect that capacitive load reading can be performed without adding a capacitive element to the signal line.
　また、第１の側面において、前記画素は、フォトダイオードと、前記フォトダイオードに蓄積された電荷をフローティングディフュージョンに転送する転送トランジスタと、前記フローティングディフュージョンをリセットするリセットトランジスタと、前記フローティングディフュージョンの電位に応じた信号を出力する増幅トランジスタと、前記増幅トランジスタと前記信号線との間に接続された選択トランジスタとを備えてもよい。これにより、画素からの信号の読出し時に画素との間でソースフォロワが形成されるという作用をもたらす。 Further, in the first aspect, the pixel includes a photodiode, a transfer transistor that transfers the charge accumulated in the photodiode to the floating diffusion, a reset transistor that resets the floating diffusion, and a potential of the floating diffusion. The device may include an amplification transistor that outputs a corresponding signal, and a selection transistor connected between the amplification transistor and the signal line. This brings about the effect that a source follower is formed between the pixel and the pixel when a signal is read from the pixel.
　また、第１の側面において、前記電圧生成部は、ダイオード接続トランジスタを備えてもよい。これにより、信号線のリセット時にダイオード接続トランジスタの順方向電圧に応じて信号線の電位が持ち上げられるという作用をもたらす。 Furthermore, in the first aspect, the voltage generation section may include a diode-connected transistor. This brings about the effect that the potential of the signal line is raised in accordance with the forward voltage of the diode-connected transistor when the signal line is reset.
　また、第１の側面において、前記電圧生成部は、直列数が互いに異なる複数のダイオード接続トランジスタを備えてもよい。これにより、信号線のリセット時の信号線の電圧が切り替え可能となるという作用をもたらす。 Furthermore, in the first aspect, the voltage generation section may include a plurality of diode-connected transistors having different numbers of series connections. This brings about the effect that the voltage of the signal line at the time of resetting the signal line can be switched.
　また、第１の側面において、前記電圧生成部は、前記画素からリセットレベルが読み出される時の前記信号線のリセットレベルを、前記画素から信号レベルが読み出される時の前記信号線のリセットレベル以上としてもよい。これにより、画素からリセットレベルが読み出される時のセトリング時間が短縮されるという作用をもたらす。 Further, in the first aspect, the voltage generation unit sets the reset level of the signal line when the reset level is read from the pixel to be equal to or higher than the reset level of the signal line when the signal level is read from the pixel. Good too. This brings about the effect of shortening the settling time when the reset level is read from the pixel.
　また、第１の側面において、前記信号線の電位とランプ信号とを比較するコンパレータをさらに具備してもよい。これにより、画素から読み出された信号が信号線の電位に基づいて検出可能となるという作用をもたらす。 Furthermore, in the first aspect, the device may further include a comparator that compares the potential of the signal line and the ramp signal. This brings about the effect that the signal read from the pixel can be detected based on the potential of the signal line.
　また、第１の側面において、異なるカラムに設けられた信号線の電位を互いに比較するコンパレータをさらに具備してもよい。これにより、容量負荷読出しに基づいて、被写体のエッジが検出されるという作用をもたらす。 Furthermore, in the first aspect, a comparator may be further provided to compare the potentials of the signal lines provided in different columns. This brings about the effect that the edge of the object is detected based on the capacitive load readout.
　また、第１の側面において、前記信号線に電気的に接続可能であり、前記画素との間に形成されるソースフォロワに基づいて定電流を流す定電流トランジスタをさらに具備してもよい。これにより、容量負荷読出しを実施しないときは、定電流読出しが可能となるという作用をもたらす。 Further, in the first aspect, the device may further include a constant current transistor that is electrically connectable to the signal line and that flows a constant current based on a source follower formed between the pixel and the pixel. This brings about the effect that constant current reading is possible when capacitive load reading is not performed.
　また、第１の側面において、前記定電流トランジスタを用いた定電流読出しでは、前記定電流トランジスタはオンされ、前記電圧生成部を用いた容量負荷読出しでは、前記定電流トランジスタはオフされてもよい。これにより、容量負荷読出しと定電流読出しとが切替可能となるという作用をもたらす。 Further, in the first aspect, the constant current transistor may be turned on in constant current readout using the constant current transistor, and the constant current transistor may be turned off in capacitive load readout using the voltage generation section. . This brings about the effect that capacitive load readout and constant current readout can be switched.
　また、第１の側面において、前記信号線トランジスタを定電流トランジスタとして動作させるサンプルホールド回路と、前記信号線トランジスタの接続先を前記電圧生成部とグランド電位との間で切り替えるスイッチとをさらに具備してもよい。これにより、信号線トランジスタが定電流読出しおよび容量負荷読出しで共用されるという作用をもたらす。 In the first aspect, the device further includes a sample hold circuit that operates the signal line transistor as a constant current transistor, and a switch that switches a connection destination of the signal line transistor between the voltage generation section and a ground potential. It's okay. This brings about the effect that the signal line transistor is shared for constant current reading and capacitive load reading.
　また、第１の側面において、定電流読出しでは、前記信号線トランジスタの接続先が前記グランド電位に切り替えられるとともに、前記信号線トランジスタはオンされ、容量負荷読出しでは、前記信号線トランジスタの接続先が前記電圧生成部に切り替えられるとともに、前記信号線がリセットされた後に前記信号線トランジスタはオフされてもよい。これにより、容量負荷読出しと定電流読出しとが切替可能となるという作用をもたらす。 In the first aspect, in constant current readout, the connection destination of the signal line transistor is switched to the ground potential and the signal line transistor is turned on, and in the capacitive load readout, the connection destination of the signal line transistor is switched to the ground potential, and the signal line transistor is turned on. The signal line transistor may be turned off after being switched to the voltage generating section and the signal line being reset. This brings about the effect that capacitive load readout and constant current readout can be switched.
　また、第１の側面において、前記電圧生成部は、前記信号線トランジスタに直列に接続された直列トランジスタと、前記直列トランジスタのゲートとドレインとの間を開閉する開閉トランジスタとを備えてもよい。これにより、直列トランジスタが定電流読出および容量負荷読出しで共用されるという作用をもたらす。 Furthermore, in the first aspect, the voltage generation section may include a series transistor connected in series to the signal line transistor, and an opening/closing transistor that opens and closes between a gate and a drain of the series transistor. This brings about the effect that the series transistor is shared for constant current reading and capacitive load reading.
　また、第１の側面において、定電流読出しでは、前記開閉トランジスタはオフされ、容量負荷読出しでは、前記開閉トランジスタはオンされてもよい。これにより、容量負荷読出しと定電流読出しとが切替可能となるという作用をもたらす。 Furthermore, in the first aspect, the switching transistor may be turned off in constant current reading, and the switching transistor may be turned on in capacitive load reading. This brings about the effect that capacitive load readout and constant current readout can be switched.
　また、第１の側面において、前記画素が形成されたチップを備え、前記信号線トランジスタは前記チップに形成されてもよい。これにより、信号線トランジスタの特性と画素トランジスタの特性とのバラツキが低減されるという作用をもたらす。 Furthermore, the first side surface may include a chip on which the pixel is formed, and the signal line transistor may be formed on the chip. This brings about the effect that variations in the characteristics of the signal line transistor and the characteristics of the pixel transistor are reduced.
　また、第１の側面において、前記電圧生成部は前記チップに形成されてもよい。これにより、電圧生成部の特性と画素トランジスタの特性とのバラツキが低減されるという作用をもたらす。 Furthermore, in the first aspect, the voltage generation section may be formed on the chip. This brings about the effect that variations in the characteristics of the voltage generation section and the characteristics of the pixel transistor are reduced.
　また、第１の側面において、前記画素がロウ方向およびカラム方向にマトリックス状に配置された画素アレイ部を備え、前記信号線は前記カラム方向に配線されるようにして前記ロウ方向に複数設けられ、前記信号線トランジスタは、前記信号線のそれぞれに設けられてもよい。これにより、信号線の電位が信号線ごとにリセットされるという作用をもたらす。 The first side surface further includes a pixel array section in which the pixels are arranged in a matrix in the row direction and the column direction, and a plurality of the signal lines are provided in the row direction so as to be wired in the column direction. , the signal line transistor may be provided for each of the signal lines. This brings about the effect that the potential of the signal line is reset for each signal line.
　また、第１の側面において、前記電圧生成部は、カラムが互いに異なる信号線のそれぞれに設けられてもよい。これにより、信号線の電位が信号線ごとに設定されるという作用をもたらす。 Furthermore, in the first aspect, the voltage generation section may be provided in each of the signal lines having different columns. This brings about the effect that the potential of the signal line is set for each signal line.
　また、第１の側面において、前記電圧生成部は、カラムが互いに異なる複数の信号線で共有されてもよい。これにより、カラム数に対して電圧生成部の個数が低減されるという作用をもたらす。 Furthermore, in the first aspect, the voltage generation section may be shared by a plurality of signal lines having different columns. This brings about the effect that the number of voltage generating sections is reduced relative to the number of columns.
　また、第１の側面において、カラムが互いに異なる複数の信号線のそれぞれに設けられた前記電圧生成部を短絡する短絡線を備えてもよい。これにより、信号線の電位のカラムごとのばらつきが低減されるという作用をもたらす。 Furthermore, in the first aspect, each column may include a shorting line that shorts the voltage generation sections provided in each of the plurality of signal lines different from each other. This brings about the effect that variations in the potential of the signal line from column to column are reduced.
第１の実施の形態に係る撮像装置が適用されるカメラの構成例を示すブロック図である。FIG. 1 is a block diagram illustrating a configuration example of a camera to which the imaging device according to the first embodiment is applied. 第１の実施の形態に係る固体撮像装置の構成例を示すブロック図である。1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment. FIG. 第１の実施の形態に係る固体撮像装置に設けられた画素の回路構成例を示すブロック図である。FIG. 2 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. 第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の構成例を示す断面図である。FIG. 3 is a cross-sectional view showing a configuration example of a pixel array section provided in the solid-state imaging device according to the first embodiment. 第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の変形例を示す断面図である。FIG. 7 is a cross-sectional view showing a modification of the pixel array section provided in the solid-state imaging device according to the first embodiment. 第１の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。FIG. 3 is a diagram illustrating a configuration example of a signal readout circuit for one column according to the first embodiment. 第１の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。FIG. 3 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the first embodiment. 第１の実施の形態に係る撮像装置の垂直信号線に接続される電圧生成部の回路構成例を示す図である。FIG. 3 is a diagram illustrating an example of a circuit configuration of a voltage generation section connected to a vertical signal line of the imaging device according to the first embodiment. 第２の実施の形態に係る１カラム分の信号読出し回路の容量負荷読出し時の切替例を示すブロック図である。FIG. 7 is a block diagram showing an example of switching when reading a capacitive load of a signal reading circuit for one column according to a second embodiment. 第２の実施の形態に係る１カラム分の信号読出し回路の定電流読出し時の切替例を示すブロック図である。FIG. 7 is a block diagram showing an example of switching during constant current readout of the signal readout circuit for one column according to the second embodiment. 第２の実施の形態に係る信号読出し回路の定電流読出しにおける各部の波形の一例を示す図である。FIG. 7 is a diagram showing an example of waveforms of various parts during constant current readout of the signal readout circuit according to the second embodiment. 第３の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。FIG. 7 is a diagram showing a configuration example of a signal readout circuit for one column according to a third embodiment. 第４の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing a configuration example of a signal readout circuit for one column according to a fourth embodiment. 第５の実施の形態に係る２カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing a configuration example of a signal readout circuit for two columns according to a fifth embodiment. 第６の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for four columns according to a sixth embodiment. 第７の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for one column according to a seventh embodiment. 第７の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。FIG. 12 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the seventh embodiment. 第８の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing a configuration example of a signal readout circuit for one column according to an eighth embodiment. 第９の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing an example of the configuration of a signal readout circuit for one column according to a ninth embodiment. 第１０の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。10 is a diagram showing an example of the configuration of a signal readout circuit for one column according to a tenth embodiment. FIG. 第１１の実施の形態に係る２カラム分の信号読出し回路の構成例を示す図である。FIG. 12 is a diagram showing a configuration example of a signal readout circuit for two columns according to an eleventh embodiment. 第１１の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。FIG. 12 is a diagram showing an example of waveforms of various parts during signal readout of the imaging device according to the eleventh embodiment. 第１２の実施の形態に係る撮像装置の構成例を示す斜視図である。FIG. 12 is a perspective view showing a configuration example of an imaging device according to a twelfth embodiment. 車両制御システムの概略的な構成例を示すブロック図である。FIG. 1 is a block diagram showing a schematic configuration example of a vehicle control system. 撮像部の設置位置の一例を示す説明図である。FIG. 3 is an explanatory diagram showing an example of an installation position of an imaging unit.
　以下、本技術を実施するための形態（以下、実施の形態と称する）について説明する。説明は以下の順序により行う。
　１．第１の実施の形態（垂直信号線に電気的に接続された信号線トランジスタを介してダイオード接続トランジスタを接続した例）
　２．第２の実施の形態（垂直信号線に電気的に接続された信号線トランジスタが定電流トランジスタとして動作するように切り替えたり、ダイオード接続トランジスタに接続されるように切り替えたりする例）
　３．第３の実施の形態（信号線トランジスタとダイオード接続トランジスタとの直列回路に並列に定電流トランジスタを接続した例）
　４．第４の実施の形態（垂直信号線に電気的に接続された信号線トランジスタに直列に接続された直列トランジスタをダイオード接続トランジスタとして動作させたり、定電流トランジスタとして動作させたりする例）
　５．第５の実施の形態（複数のカラムでダイオード接続トランジスタを共有した例）
　６．第６の実施の形態（ダイオード接続トランジスタのドレインを複数のカラム間で短絡した例）
　７．第７の実施の形態（垂直信号線に電気的に接続された信号線トランジスタを介して接続されるダイオード接続トランジスタの直列数を切り替え可能とした例）
　８．第８の実施の形態（画素が設けられた上層チップに信号線トランジスタおよびダイオード接続トランジスタを設けるとともに、定電流トランジスタを下層チップに設けた例）
　９．第９の実施の形態（信号線トランジスタとダイオード接続トランジスタとの直列回路を用いた容量負荷読出しを４個のフォトダイオードで増幅トランジスタが共有されるセルに適用した例）
　１０．第１０の実施の形態（信号線トランジスタとダイオード接続トランジスタとの直列回路を用いた容量負荷読出しをビニング読出しに適用した例）
　１１．第１１の実施の形態（信号線トランジスタとダイオード接続トランジスタとの直列回路を用いた容量負荷読出しをエッジ検出に適用した例）
　１２．第１２の実施の形態（固体撮像装置が形成される基板を積層化した例）
　１３．移動体への応用例 Hereinafter, a mode for implementing the present technology (hereinafter referred to as an embodiment) will be described. The explanation will be given in the following order.
1. First embodiment (example in which a diode-connected transistor is connected via a signal line transistor electrically connected to a vertical signal line)
2. Second embodiment (example in which a signal line transistor electrically connected to a vertical signal line is switched to operate as a constant current transistor or switched to be connected to a diode-connected transistor)
3. Third embodiment (example in which a constant current transistor is connected in parallel to a series circuit of a signal line transistor and a diode-connected transistor)
4. Fourth embodiment (example in which a series transistor connected in series to a signal line transistor electrically connected to a vertical signal line operates as a diode-connected transistor or as a constant current transistor)
5. Fifth embodiment (example where diode-connected transistors are shared by multiple columns)
6. Sixth embodiment (example where drains of diode-connected transistors are shorted between multiple columns)
7. Seventh embodiment (an example in which the number of series diode-connected transistors connected via a signal line transistor electrically connected to a vertical signal line can be switched)
8. Eighth embodiment (an example in which a signal line transistor and a diode-connected transistor are provided in an upper layer chip where pixels are provided, and a constant current transistor is provided in a lower layer chip)
9. Ninth embodiment (example in which capacitive load readout using a series circuit of a signal line transistor and a diode-connected transistor is applied to a cell in which an amplification transistor is shared by four photodiodes)
10. Tenth embodiment (example where capacitive load readout using a series circuit of a signal line transistor and a diode-connected transistor is applied to binning readout)
11. Eleventh embodiment (example in which capacitive load readout using a series circuit of a signal line transistor and a diode-connected transistor is applied to edge detection)
12. Twelfth embodiment (example in which substrates on which a solid-state imaging device is formed are laminated)
13. Example of application to mobile objects
　＜１．第１の実施の形態＞
　図１は、第１の実施の形態に係る撮像装置が適用されるカメラの構成例を示すブロック図である。 <1. First embodiment>
FIG. 1 is a block diagram showing a configuration example of a camera to which an imaging device according to a first embodiment is applied.
　同図において、カメラ１００は、光学系１０１、固体撮像装置１０２、撮像制御部１０３、画像処理部１０４、記憶部１０５、表示部１０６および操作部１０７を備える。撮像制御部１０３、画像処理部１０４、記憶部１０５、表示部１０６および操作部１０７は、バス１０８を介して互いに接続されている。なお、カメラ１００は、単体としても用いられてもよいし、スマートフォンなどの携帯端末に組み込まれてもよいし、認証装置や監視装置に組み込まれてもよい。 In the figure, a camera 100 includes an optical system 101, a solid-state imaging device 102, an imaging control section 103, an image processing section 104, a storage section 105, a display section 106, and an operation section 107. The imaging control section 103, the image processing section 104, the storage section 105, the display section 106, and the operation section 107 are connected to each other via a bus 108. Note that the camera 100 may be used alone, or may be incorporated into a mobile terminal such as a smartphone, or may be incorporated into an authentication device or a monitoring device.
　光学系１０１は、被写体からの光を固体撮像装置１０２に入射させ、被写像を固体撮像装置１０２の受光面に結像させる。光学系１０１は、例えば、フォーカスレンズ、ズームレンズおよび絞りなどを備えることができる。光学系１０１は、広角レンズ、標準レンズおよび望遠レンズなどの複数のレンズを備えてもよい。 The optical system 101 makes light from a subject enter the solid-state imaging device 102 and forms an image of the subject on the light-receiving surface of the solid-state imaging device 102. The optical system 101 can include, for example, a focus lens, a zoom lens, an aperture, and the like. Optical system 101 may include multiple lenses such as a wide-angle lens, a standard lens, and a telephoto lens.
　固体撮像装置１０２は、被写体からの光を画素ごとに電気信号に変換し、その電気信号をデジタル化して出力する。固体撮像装置１０２は、例えば、ＣＭＯＳ（Complementary Metal Oxide Semiconductor）イメージセンサでもよいし、ＣＣＤ(Charge Coupled Device)でもよい。 The solid-state imaging device 102 converts light from a subject into an electrical signal for each pixel, digitizes the electrical signal, and outputs the digital signal. The solid-state imaging device 102 may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device).
　撮像制御部１０３は、操作部１０７からの指令に基づいて固体撮像装置１０２による撮像を制御する。このとき、撮像制御部１０３は、固体撮像装置１０２の露光時間、露光量および撮像タイミングなどを制御することができる。 The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.
　画像処理部１０４は、固体撮像装置１０２からの出力に基づいて画像処理を実施する。画像処理は、例えば、ガンマ補正、ホワイトバランス処理、シャープネス処理、階調変換処理である。画像処理部１０４は、ソフトウェアに基づいて処理を実行するプロセッサを備えてもよい。 The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing. The image processing unit 104 may include a processor that executes processing based on software.
　記憶部１０５は、固体撮像装置１０２で撮像された撮像画像を記憶したり、固体撮像装置１０２の撮像パラメータなどを記憶したりする。また、記憶部１０５は、ソフトウェアに基づいてカメラ１００を動作させるプログラムを記憶することができる。記憶部１０５は、ＲＯＭ（Read Only Memory）、ＲＡＭ（Random Access Memory）およびメモリカードを含んでもよい。 The storage unit 105 stores captured images captured by the solid-state imaging device 102, and stores imaging parameters of the solid-state imaging device 102. Furthermore, the storage unit 105 can store a program for operating the camera 100 based on software. The storage unit 105 may include a ROM (Read Only Memory), a RAM (Random Access Memory), and a memory card.
　表示部１０６は、撮像画像を表示したり、撮像操作をサポートする各種情報を表示したりする。表示部１０６は、液晶ディスプレイでもよいし、有機ＥＬ（Electro Luminescence）ディスプレイでもよい。 The display unit 106 displays captured images and various information that supports imaging operations. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.
　操作部１０７は、カメラ１００を操作するユーザインターフェースを提供する。操作部１０７は、例えば、カメラ１００に設けられたボタン、ダイヤルおよびスイッチを含んでもよい。操作部１０７は、表示部１０６とともにタッチパネルで構成してもよい。 The operation unit 107 provides a user interface for operating the camera 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the camera 100. The operation unit 107 may be configured with a touch panel together with the display unit 106.
　図２は、第１の実施の形態に係る固体撮像装置の構成例を示すブロック図である。 FIG. 2 is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment.
　同図において、固体撮像装置１０２は、画素アレイ部１１１、垂直走査回路１１２、カラム読出し回路１１３、カラム信号処理部１１４、水平走査回路１１５および制御回路１１６を備える。 In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.
　画素アレイ部１１１は、複数の画素１２０を備える。画素１２０は、ロウ方向（水平方向とも言う）およびカラム方向（垂直方向とも言う）に沿ってマトリックス状に配列される。各画素１２０は、信号の読出し時にカラム読出し回路１１３との間でソースフォロワを構成することができる。各画素１２０は、ロウごとに水平駆動線１３１に接続され、カラムごとに垂直信号線１３２に接続される。水平駆動線１３１は、各画素１２０からの信号の読出し時に各画素１２０をロウごとに駆動する。垂直信号線１３２は、画素１２０からの信号読出し時に流れる電流に応じて蓄積された電荷に基づく電位をカラムごとにカラム信号処理部１１４に伝送する。なお、垂直信号線１３２は、特許請求の範囲に記載の信号線の一例である。 The pixel array section 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel 120 can form a source follower with the column readout circuit 113 during signal readout. Each pixel 120 is connected to a horizontal drive line 131 for each row and to a vertical signal line 132 for each column. The horizontal drive line 131 drives each pixel 120 row by row when reading signals from each pixel 120. The vertical signal line 132 transmits a potential based on accumulated charges according to a current flowing when reading a signal from the pixel 120 to the column signal processing unit 114 for each column. Note that the vertical signal line 132 is an example of a signal line described in the claims.
　垂直走査回路１１２は、読出し対象となる画素１２０をカラム方向に走査する。垂直走査回路１１２は、垂直レジスタを用いて構成してもよい。 The vertical scanning circuit 112 scans the pixels 120 to be read in the column direction. The vertical scanning circuit 112 may be configured using vertical registers.
　カラム読出し回路１１３は、各画素１２０からの信号の読出し時に、各画素１２０との間でソースフォロワを構成することができる。このとき、カラム読出し回路１１３は、画素１２０に保持された電荷に基づいて垂直信号線１３２の電位を変化させることができる。カラム読出し回路１１３は、容量負荷読出しに対応することができる。カラム読出し回路１１３は、定電流読出しにも対応してもよい。 The column readout circuit 113 can form a source follower with each pixel 120 when reading signals from each pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120. Column readout circuit 113 can support capacitive load readout. The column readout circuit 113 may also support constant current readout.
　カラム信号処理部１１４は、各画素１２０からカラム方向に伝送された信号を処理する。例えば、カラム信号処理部１１４は、各画素１２０からカラム方向に伝送された信号に基づいて、相関二重サンプリング（ＣＤＳ：Correlated Double Sampling）処理を実施することができる。また、カラム信号処理部１１４は、各画素１２０からカラム方向に伝送された信号に基づいて、ＡＤ（Analog to Digital）変換処理を実施し、撮像信号Ｇｏｕｔを出力することができる。 The column signal processing unit 114 processes signals transmitted from each pixel 120 in the column direction. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on signals transmitted from each pixel 120 in the column direction. Further, the column signal processing unit 114 can perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 120, and output the image pickup signal Gout.
　水平走査回路１１５は、読出し対象となる画素１２０をロウ方向に走査する。水平走査回路１１５は、水平レジスタを用いて構成してもよい。 The horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.
　制御回路１１６は、垂直走査回路１１２、カラム読出し回路１１３、カラム信号処理部１１４および水平走査回路１１５を制御する。例えば、制御回路１１６は、カラム方向の走査タイミング、ロウ方向の走査タイミング、カラム読出し回路１１３の動作タイミングおよびカラム信号処理部１１４の処理タイミングを制御することができる。 The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing section 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scan timing in the column direction, the scan timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing section 114.
　図３は、第１の実施の形態に係る固体撮像装置に設けられた画素の回路構成例を示すブロック図である。 FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.
　同図において、画素１２０は、フォトダイオード１２１、転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４、選択トランジスタ１２５およびフローティングディフュージョン１２６を備える。転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４および選択トランジスタ１２５として、ＭＯＳ（Metal Oxide Semiconductor）トランジスタを用いることができる。 In the figure, a pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion 126. MOS (Metal Oxide Semiconductor) transistors can be used as the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.
　増幅トランジスタ１２４と選択トランジスタ１２５は、直列に接続されている。フォトダイオード１２１のカソードは、転送トランジスタ１２２を介してフローティングディフュージョン１２６に接続されている。また、フローティングディフュージョン１２６は、リセットトランジスタ１２３を介して電源Ｖｄｄに接続されている。また、電源Ｖｄｄは、増幅トランジスタ１２４と選択トランジスタ１２５の直列回路を介して垂直信号線１３２に接続されている。増幅トランジスタ１２４のゲートはフローティングディフュージョン１２６に接続されている。 The amplification transistor 124 and the selection transistor 125 are connected in series. A cathode of the photodiode 121 is connected to a floating diffusion 126 via a transfer transistor 122. Furthermore, the floating diffusion 126 is connected to the power supply Vdd via the reset transistor 123. Further, the power supply Vdd is connected to the vertical signal line 132 via a series circuit of an amplification transistor 124 and a selection transistor 125. The gate of amplification transistor 124 is connected to floating diffusion 126 .
　転送トランジスタ１２２のゲートには、転送信号ΦＴＧが印加される。リセットトランジスタ１２３のゲートには、画素リセット信号ΦＰＲＴが印加される。選択トランジスタ１２５のゲートには、選択信号ΦＳＥＬが印加される。転送信号ΦＴＧ、画素リセット信号ΦＰＲＴおよび選択信号ΦＳＥＬは、図２の水平駆動線１３１を介して各画素１２０に伝送することができる。 A transfer signal ΦTG is applied to the gate of the transfer transistor 122. A pixel reset signal ΦPRT is applied to the gate of the reset transistor 123. A selection signal ΦSEL is applied to the gate of the selection transistor 125. The transfer signal ΦTG, pixel reset signal ΦPRT, and selection signal ΦSEL can be transmitted to each pixel 120 via the horizontal drive line 131 in FIG.
　転送トランジスタ１２２がオンすると、フォトダイオード１２１に蓄積された電荷がフローティングディフュージョン１２６に転送される。そして、選択トランジスタ１２５がオンすると、フローティングディフュージョン１２６の電位に応じて増幅トランジスタ１２４のソース電位が変化する。そして、増幅トランジスタ１２４のソース電位は、選択トランジスタ１２５を介して垂直信号線１３２に印加され、垂直信号線１３２を介して伝送される。また、リセットトランジスタ１２３がオンすると、フローティングディフュージョン１２６に蓄積された電荷が排出される。 When the transfer transistor 122 is turned on, the charges accumulated in the photodiode 121 are transferred to the floating diffusion 126. Then, when the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion 126. The source potential of the amplification transistor 124 is applied to the vertical signal line 132 via the selection transistor 125 and transmitted via the vertical signal line 132. Furthermore, when the reset transistor 123 is turned on, the charges accumulated in the floating diffusion 126 are discharged.
　図４は、第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の構成例を示す断面図である。なお、図４では、表面照射型固体撮像装置の例を示す。また、図４では、３画素分の構成例を示した。 FIG. 4 is a cross-sectional view showing an example of the configuration of a pixel array section provided in the solid-state imaging device according to the first embodiment. Note that FIG. 4 shows an example of a front-illuminated solid-state imaging device. Further, FIG. 4 shows a configuration example for three pixels.
　同図において、半導体基板２３１には、画素１２０ごとにフォトダイオード２３２が形成されている。半導体基板２３１の材料は、Ｓｉでもよいし、ＩｎＧａＡｓでもよいし、ＩｎＰでもよい。 In the figure, a photodiode 232 is formed on a semiconductor substrate 231 for each pixel 120. The material of the semiconductor substrate 231 may be Si, InGaAs, or InP.
　半導体基板２３１上には、ゲート電極２１４および配線層２１０が形成される。ゲート電極２１４は、ゲート絶縁膜２１３を介して半導体基板２３１上に形成される。ゲート電極２１４の側壁には、サイドウォール２１５が形成される。ゲート電極２１４の材料は、例えば、不純物が導入された多結晶シリコンを用いることができる。ゲート絶縁膜２１３の材料は、例えば、シリコン酸化膜を用いることができる。サイドウォール２１５の材料は、例えば、シリコン酸化膜またはシリコン窒化膜を用いることができる。 A gate electrode 214 and a wiring layer 210 are formed on the semiconductor substrate 231. Gate electrode 214 is formed on semiconductor substrate 231 with gate insulating film 213 interposed therebetween. A sidewall 215 is formed on the sidewall of the gate electrode 214 . As the material of the gate electrode 214, for example, polycrystalline silicon into which impurities are introduced can be used. As the material of the gate insulating film 213, for example, a silicon oxide film can be used. As the material of the sidewall 215, for example, a silicon oxide film or a silicon nitride film can be used.
　ゲート電極２１４は、画素トランジスタに用いることができる。画素トランジスタは、図３の転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４および選択トランジスタ１２５を含む。 The gate electrode 214 can be used for a pixel transistor. The pixel transistors include the transfer transistor 122, reset transistor 123, amplification transistor 124, and selection transistor 125 in FIG.
　ゲート電極２１４上には、配線２１６が形成される。図４では、３層配線の例を示した。このとき、配線２１６には、光をフォトダイオード２３２に入射させる開口部ＯＰ１が設けられる。ゲート電極２１４および配線２１６は、絶縁層２１７を介して絶縁される。絶縁層２１７は、例えば、シリコン酸化膜を用いることができる。配線２１６の材料は、例えば、ＡｌまたはＣｕなどの金属を用いることができる。 A wiring 216 is formed on the gate electrode 214. FIG. 4 shows an example of three-layer wiring. At this time, the wiring 216 is provided with an opening OP1 that allows light to enter the photodiode 232. Gate electrode 214 and wiring 216 are insulated via insulating layer 217. For example, a silicon oxide film can be used as the insulating layer 217. As the material of the wiring 216, for example, metal such as Al or Cu can be used.
　配線層２１０上には、画素１２０ごとにカラーフィルタ２１８が形成される。カラーフィルタ２１８上には、画素１２０ごとにマイクロレンズ２１９が形成されている。カラーフィルタ２１８およびマイクロレンズ２１９の材料は、例えば、アクリルまたはポリカーボネートなどの透明樹脂を用いることができる。カラーフィルタ２１８は、着色に顔料が添加されてもよい。カラーフィルタ２１８は、例えば、ベイヤ配列を構成することができる。 A color filter 218 is formed on the wiring layer 210 for each pixel 120. A microlens 219 is formed on the color filter 218 for each pixel 120. As the material of the color filter 218 and the microlens 219, for example, transparent resin such as acrylic or polycarbonate can be used. A pigment may be added to the color filter 218 for coloring. The color filter 218 can have a Bayer array, for example.
　図５は、第１の実施の形態に係る固体撮像装置に設けられた画素アレイ部の変形例を示す断面図である。なお、図５では、裏面照射型固体撮像装置の例を示す。また、図５では、３画素分の構成例を示した。 FIG. 5 is a cross-sectional view showing a modification of the pixel array section provided in the solid-state imaging device according to the first embodiment. Note that FIG. 5 shows an example of a back-illuminated solid-state imaging device. Further, FIG. 5 shows a configuration example for three pixels.
　同図において、半導体層２２１には、画素１２０ごとにフォトダイオード２２２が形成されている。半導体層２２１の材料は、Ｓｉでもよいし、ＩｎＧａＡｓでもよいし、ＩｎＰでもよい。半導体層２２１は、例えば、フォトダイオード２２２が表面側に形成された半導体基板を裏面側から薄膜化して形成することができる。 In the figure, a photodiode 222 is formed in a semiconductor layer 221 for each pixel 120. The material of the semiconductor layer 221 may be Si, InGaAs, or InP. The semiconductor layer 221 can be formed, for example, by thinning a semiconductor substrate on which the photodiode 222 is formed from the back side.
　半導体層２２１上には、ゲート電極２２４および配線層２２０が形成される。ゲート電極２２４は、ゲート絶縁膜２２３を介して半導体層２２１上に形成される。ゲート電極２２４の側壁には、サイドウォール２２５が形成される。 A gate electrode 224 and a wiring layer 220 are formed on the semiconductor layer 221. Gate electrode 224 is formed on semiconductor layer 221 with gate insulating film 223 interposed therebetween. A sidewall 225 is formed on the sidewall of the gate electrode 224 .
　ゲート電極２２４は、画素トランジスタに用いることができる。画素トランジスタは、図３の転送トランジスタ１２２、リセットトランジスタ１２３、増幅トランジスタ１２４および選択トランジスタ１２５を含む。 The gate electrode 224 can be used for a pixel transistor. The pixel transistors include the transfer transistor 122, reset transistor 123, amplification transistor 124, and selection transistor 125 in FIG.
　ゲート電極２２４上には、配線２２６が形成される。図５では、３層配線の例を示した。ゲート電極２２４および配線２２６は、絶縁層２２７を介して絶縁される。半導体層２２１は、絶縁層２２７を介し、支持基板２３０上に支持される。支持基板２３０は、ガラス基板でもよいし、Ｓｉ基板でもよいし、サファイア基板でもよい。 A wiring 226 is formed on the gate electrode 224. FIG. 5 shows an example of three-layer wiring. Gate electrode 224 and wiring 226 are insulated via insulating layer 227. The semiconductor layer 221 is supported on a support substrate 230 with an insulating layer 227 interposed therebetween. The support substrate 230 may be a glass substrate, a Si substrate, or a sapphire substrate.
　半導体層２２１の裏面側には、画素１２０ごとにカラーフィルタ２２８が形成される。カラーフィルタ２２８上には、画素１２０ごとにマイクロレンズ２２９が形成されている。カラーフィルタ２２８は、例えば、ベイヤ配列を構成することができる。 A color filter 228 is formed for each pixel 120 on the back side of the semiconductor layer 221. A microlens 229 is formed on the color filter 228 for each pixel 120. The color filter 228 can have a Bayer array, for example.
　図６は、第１の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。 FIG. 6 is a diagram showing a configuration example of a signal readout circuit for one column according to the first embodiment.
　同図において、増幅トランジスタ１２４は、選択トランジスタ１２５を介して垂直信号線１３２に接続されている。また、垂直信号線１３２には、容量１３３が付加される。この容量１３３は、垂直信号線１３２の寄生容量でもよいし、垂直信号線１３２に接続された容量素子でもよい。 In the figure, an amplification transistor 124 is connected to a vertical signal line 132 via a selection transistor 125. Further, a capacitor 133 is added to the vertical signal line 132. This capacitance 133 may be a parasitic capacitance of the vertical signal line 132 or a capacitive element connected to the vertical signal line 132.
　また、垂直信号線１３２には、信号線トランジスタ１４１が電気的に接続される。信号線トランジスタ１４１は、垂直信号線１３２の電位ＶＳＬをリセットすることができる。信号線トランジスタ１４１は、例えば、ＭＯＳトランジスタを用いることができる。信号線トランジスタ１４１のゲートには、信号線リセット信号ΦＲＴが印加される。 Further, a signal line transistor 141 is electrically connected to the vertical signal line 132. The signal line transistor 141 can reset the potential VSL of the vertical signal line 132. For example, a MOS transistor can be used as the signal line transistor 141. A signal line reset signal ΦRT is applied to the gate of the signal line transistor 141.
　信号線トランジスタ１４１には、ダイオード接続トランジスタ１４２が直列に接続される。ダイオード接続トランジスタ１４２は、例えば、ＭＯＳトランジスタを用いることができる。このとき、ダイオード接続トランジスタ１４２のゲートは、ダイオード接続トランジスタ１４２のドレインに接続される。ダイオード接続トランジスタ１４２のソースは接地される。ダイオード接続トランジスタ１４２のソースは、接地電位よりも高い電位に接続してもよい。ダイオード接続トランジスタ１４２は、０Ｖより高い電圧（例えば、０．５Ｖ）を生成し、信号線トランジスタ１４１を介して垂直信号線１３２の電位ＶＳＬを０Ｖより高い電位に設定することができる。なお、ダイオード接続トランジスタ１４２は、特許請求の範囲に記載の電圧生成部の一例である。 A diode-connected transistor 142 is connected in series to the signal line transistor 141. For example, a MOS transistor can be used as the diode-connected transistor 142. At this time, the gate of diode-connected transistor 142 is connected to the drain of diode-connected transistor 142. The source of diode-connected transistor 142 is grounded. The source of diode-connected transistor 142 may be connected to a potential higher than ground potential. The diode-connected transistor 142 can generate a voltage higher than 0V (for example, 0.5V), and can set the potential VSL of the vertical signal line 132 to a potential higher than 0V via the signal line transistor 141. Note that the diode-connected transistor 142 is an example of a voltage generating section described in the claims.
　垂直信号線１３２は、ＤＣカットコンデンサ１４４を介してコンパレータ１４３の反転入力に接続される。このとき、コンパレータ１４３の反転入力には、ＤＣカットコンデンサ１４４を介して垂直信号線１３２の電位ＶＳＬが印加される。コンパレータ１４３の非反転入力には、ＤＣカットコンデンサ１４５を介して参照信号ＲＡＰが入力される。参照信号ＲＡＰは、例えば、ランプ信号である。 The vertical signal line 132 is connected to an inverting input of a comparator 143 via a DC cut capacitor 144. At this time, the potential VSL of the vertical signal line 132 is applied to the inverting input of the comparator 143 via the DC cut capacitor 144. A reference signal RAP is input to a non-inverting input of the comparator 143 via a DC cut capacitor 145. Reference signal RAP is, for example, a ramp signal.
　ここで、画素１２０からの信号の読出し前に、信号線トランジスタ１４１がオンすることで、垂直信号線１３２の電位ＶＳＬが０Ｖより高い電位に設定される。そして、信号線トランジスタ１４１がオフした後、選択トランジスタ１２５がオンすることで、画素１２０から信号が読み出され、画素電流ＩＰＸが選択トランジスタ１２５を介して垂直信号線１３２に流れる。このとき、画素電流ＩＰＸに応じた電荷が容量１３３に蓄積され、容量１３３に蓄積された電荷に基づいて垂直信号線１３２の電位ＶＳＬが変化する。そして、コンパレータ１４３において、垂直信号線１３２の電位ＶＳＬが参照信号ＲＡＰと比較され、その比較結果ＣＯＰが出力される。 Here, by turning on the signal line transistor 141 before reading out the signal from the pixel 120, the potential VSL of the vertical signal line 132 is set to a potential higher than 0V. Then, after the signal line transistor 141 is turned off, the selection transistor 125 is turned on, so that a signal is read out from the pixel 120, and the pixel current IPX flows to the vertical signal line 132 via the selection transistor 125. At this time, charges corresponding to the pixel current IPX are accumulated in the capacitor 133, and the potential VSL of the vertical signal line 132 changes based on the charges accumulated in the capacitor 133. Then, the comparator 143 compares the potential VSL of the vertical signal line 132 with the reference signal RAP, and outputs the comparison result COP.
　図７は、第１の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。 FIG. 7 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the first embodiment.
　同図において、容量負荷読出しでは、画素リセット／ＶＳＬリセットが実施される（Ｋ１１）。このとき、画素リセット信号ΦＰＲＴが立ち上がり（ｔ１１）、リセットトランジスタ１２３がオンしてフローティングディフュージョン１２６がリセットされる。なお、フローティングディフュージョン１２６のリセットレベルは、電源電位Ｖｄｄに設定することができる。また、信号線リセット信号ΦＲＴが立ち上がり（ｔ１１）、信号線トランジスタ１４１がオンして垂直信号線１３２がリセットされる。このとき、信号線トランジスタ１４１がオンすると、信号線トランジスタ１４１を介してダイオード接続トランジスタ１４２に電流が流れる。このため、垂直信号線１３２のリセットレベルは、ダイオード接続トランジスタ１４２の順方向電圧ＶＲ１だけ０Ｖより高い電位（例えば、０．５Ｖ）に設定される。なお、画素リセット信号ΦＰＲＴの立ち上がりタイミングと、信号線リセット信号ΦＲＴの立ち上がりタイミングは、必ずしも同時でなくてもよく、互いにずれていてもよい。また、信号線リセット信号ΦＲＴの立ち下がりタイミングは、画素リセット信号ΦＰＲＴの立ち下がりタイミングよりも遅い必要はなく、選択信号ΦＳＥＬの立ち上がり前なら特に限定されない。 In the figure, pixel reset/VSL reset is performed in capacitive load readout (K11). At this time, the pixel reset signal ΦPRT rises (t11), the reset transistor 123 is turned on, and the floating diffusion 126 is reset. Note that the reset level of the floating diffusion 126 can be set to the power supply potential Vdd. Further, the signal line reset signal ΦRT rises (t11), the signal line transistor 141 is turned on, and the vertical signal line 132 is reset. At this time, when the signal line transistor 141 is turned on, current flows to the diode-connected transistor 142 via the signal line transistor 141. Therefore, the reset level of the vertical signal line 132 is set to a potential higher than 0V (for example, 0.5V) by the forward voltage VR1 of the diode-connected transistor 142. Note that the rising timing of the pixel reset signal ΦPRT and the rising timing of the signal line reset signal ΦRT do not necessarily have to be simultaneous, and may be shifted from each other. Further, the fall timing of the signal line reset signal ΦRT does not need to be later than the fall timing of the pixel reset signal ΦPRT, and is not particularly limited as long as it is before the rise of the selection signal ΦSEL.
　次に、Ｐ相ＶＳＬセトリングが実施される（Ｋ１２）。このとき、信号線リセット信号ΦＲＴが立ち下がるとともに、選択信号ΦＳＥＬが立ち上がり（ｔ１２）、選択トランジスタ１２５がオンする。そして、増幅トランジスタ１２４のソースフォロワ動作に基づいてフローティングディフュージョン１２６のリセットレベルに応じた画素電流ＩＰＸが選択トランジスタ１２５を介して垂直信号線１３２に流れる。そして、その画素電流ＩＰＸに応じた電荷が容量１３３に蓄積され、容量１３３に蓄積された電荷に基づいて垂直信号線１３２の電位ＶＳＬが設定される。 Next, P-phase VSL settling is performed (K12). At this time, the signal line reset signal ΦRT falls, the selection signal ΦSEL rises (t12), and the selection transistor 125 is turned on. Based on the source follower operation of the amplification transistor 124, a pixel current IPX corresponding to the reset level of the floating diffusion 126 flows to the vertical signal line 132 via the selection transistor 125. Then, charges corresponding to the pixel current IPX are accumulated in the capacitor 133, and the potential VSL of the vertical signal line 132 is set based on the charges accumulated in the capacitor 133.
　次に、Ｐ相ＡＤが実施される（Ｋ１３）。このとき、選択信号ΦＳＥＬが立ち下がった後（ｔ１３）、参照信号ＲＡＰとしてランプ信号がコンパレータ１４３に供給される。そして、コンパレータ１４３において、リセットレベルに応じた垂直信号線１３２の電位ＶＳＬが参照信号ＲＡＰと比較され、参照信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＳＬと一致したときのタイミングが比較結果ＣＯＰとして出力される。このとき、参照信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＳＬと一致するまでのカウント動作に基づいて、画素１２０から読み出されたリセットレベルがＡＤ変換される。 Next, P-phase AD is performed (K13). At this time, after the selection signal ΦSEL falls (t13), the ramp signal is supplied to the comparator 143 as the reference signal RAP. Then, in the comparator 143, the potential VSL of the vertical signal line 132 according to the reset level is compared with the reference signal RAP, and the timing when the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 is determined as the comparison result COP. Output. At this time, the reset level read from the pixel 120 is AD converted based on a counting operation until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132.
　次に、転送／ＶＳＬリセットが実施される（Ｋ１４）。このとき、転送信号ΦＴＧが立ち上がり（ｔ１４）、転送トランジスタ１２２がオンしてフォトダイオード１２１に蓄積された電荷がフローティングディフュージョン１２６に転送される。また、信号線リセット信号ΦＲＴが立ち上がり（ｔ１４）、信号線トランジスタ１４１がオンして垂直信号線１３２がリセットされる。このとき、信号線トランジスタ１４１がオンすると、信号線トランジスタ１４１を介してダイオード接続トランジスタ１４２に電流が流れる。このため、垂直信号線１３２のリセットレベルは、ダイオード接続トランジスタ１４２の順方向電圧ＶＲ１だけ０Ｖより高い電位（例えば、０．５Ｖ）に設定される。なお、転送信号ΦＴＧの立ち上がりタイミングと、信号線リセット信号ΦＲＴの立ち上がりタイミングは、必ずしも同時でなくてもよく、互いにずれていてもよい。また、信号線リセット信号ΦＲＴの立ち下がりタイミングは、転送信号ΦＴＧの立ち下がりタイミングよりも遅い必要はなく、選択信号ΦＳＥＬの立ち上がり前なら特に限定されない。 Next, transfer/VSL reset is performed (K14). At this time, the transfer signal ΦTG rises (t14), the transfer transistor 122 is turned on, and the charges accumulated in the photodiode 121 are transferred to the floating diffusion 126. Further, the signal line reset signal ΦRT rises (t14), the signal line transistor 141 is turned on, and the vertical signal line 132 is reset. At this time, when the signal line transistor 141 is turned on, current flows to the diode-connected transistor 142 via the signal line transistor 141. Therefore, the reset level of the vertical signal line 132 is set to a potential higher than 0V (for example, 0.5V) by the forward voltage VR1 of the diode-connected transistor 142. Note that the rising timing of the transfer signal ΦTG and the rising timing of the signal line reset signal ΦRT do not necessarily have to be simultaneous, and may be shifted from each other. Further, the fall timing of the signal line reset signal ΦRT does not need to be later than the fall timing of the transfer signal ΦTG, and is not particularly limited as long as it is before the rise of the selection signal ΦSEL.
　次に、Ｄ相ＶＳＬセトリングが実施される（Ｋ１５）。このとき、信号線リセット信号ΦＲＴが立ち下がるとともに、選択信号ΦＳＥＬが立ち上がり（ｔ１５）、選択トランジスタ１２５がオンする。そして、増幅トランジスタ１２４のソースフォロワ動作に基づいてフローティングディフュージョン１２６の信号レベルに応じた画素電流ＩＰＸが選択トランジスタ１２５を介して垂直信号線１３２に流れる。そして、その画素電流ＩＰＸに応じた電荷が容量１３３に蓄積され、容量１３３に蓄積された電荷に基づいて垂直信号線１３２の電位ＶＳＬが設定される。 Next, D-phase VSL settling is performed (K15). At this time, the signal line reset signal ΦRT falls, the selection signal ΦSEL rises (t15), and the selection transistor 125 is turned on. Based on the source follower operation of the amplification transistor 124, a pixel current IPX corresponding to the signal level of the floating diffusion 126 flows to the vertical signal line 132 via the selection transistor 125. Then, charges corresponding to the pixel current IPX are accumulated in the capacitor 133, and the potential VSL of the vertical signal line 132 is set based on the charges accumulated in the capacitor 133.
　次に、Ｄ相ＡＤが実施される（Ｋ１６）。このとき、選択信号ΦＳＥＬが立ち下がるとともに（ｔ１６）、参照信号ＲＡＰとしてランプ信号がコンパレータ１４３に供給される（ｔ１６－ｔ１７）。そして、コンパレータ１４３において、信号レベルに応じた垂直信号線１３２の電位ＶＳＬが参照信号ＲＡＰと比較され、参照信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＳＬと一致したときのタイミングが比較結果ＣＯＰとして出力される。このとき、参照信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＳＬと一致するまでのカウント動作に基づいて、画素１２０から読み出された信号レベルがＡＤ変換される。 Next, D-phase AD is performed (K16). At this time, the selection signal ΦSEL falls (t16), and the ramp signal is supplied to the comparator 143 as the reference signal RAP (t16-t17). Then, in the comparator 143, the potential VSL of the vertical signal line 132 according to the signal level is compared with the reference signal RAP, and the timing when the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 is determined as the comparison result COP. Output. At this time, the signal level read from the pixel 120 is AD converted based on a counting operation until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132.
　図８は、第１の実施の形態に係る撮像装置の垂直信号線に接続される電圧生成部の回路構成例を示す図である。 FIG. 8 is a diagram illustrating an example of a circuit configuration of a voltage generation section connected to a vertical signal line of the imaging device according to the first embodiment.
　同図におけるａにおいて、垂直信号線１３２に接続される電圧生成部は、信号線トランジスタ１４１およびダイオード接続トランジスタ１４２を備えてもよい。このとき、ダイオード接続トランジスタ１４２はＮＭＯＳトランジスタでもよい。また、ダイオード接続トランジスタ１４２のドレイン側に信号線トランジスタ１４１が接続されてもよい。 In a in the figure, the voltage generation section connected to the vertical signal line 132 may include a signal line transistor 141 and a diode-connected transistor 142. At this time, the diode-connected transistor 142 may be an NMOS transistor. Further, the signal line transistor 141 may be connected to the drain side of the diode-connected transistor 142.
　同図におけるｂにおいて、垂直信号線１３２に接続される電圧生成部は、信号線トランジスタ１４１およびダイオード接続トランジスタ１４２を備えてもよい。このとき、ダイオード接続トランジスタ１４２のソース側に信号線トランジスタ１４１が接続されてもよい。 In b in the figure, the voltage generation section connected to the vertical signal line 132 may include a signal line transistor 141 and a diode-connected transistor 142. At this time, the signal line transistor 141 may be connected to the source side of the diode-connected transistor 142.
　同図におけるｃにおいて、垂直信号線１３２に接続される電圧生成部は、信号線トランジスタ１４１およびダイオード接続トランジスタ１４６を備えてもよい。このとき、ダイオード接続トランジスタ１４６はＰＭＯＳトランジスタでもよい。また、ダイオード接続トランジスタ１４６のドレイン側に信号線トランジスタ１４１が接続されてもよいし、ダイオード接続トランジスタ１４６のソース側に信号線トランジスタ１４１が接続されてもよい。 At c in the same figure, the voltage generation section connected to the vertical signal line 132 may include a signal line transistor 141 and a diode-connected transistor 146. At this time, the diode-connected transistor 146 may be a PMOS transistor. Furthermore, the signal line transistor 141 may be connected to the drain side of the diode-connected transistor 146, or the signal line transistor 141 may be connected to the source side of the diode-connected transistor 146.
　同図におけるｄにおいて、垂直信号線１３２に接続される電圧生成部は、信号線トランジスタ１４１およびＰＮ接合ダイオード１４７を備えてもよい。このとき、ＰＮ接合ダイオード１４７のアノード側に信号線トランジスタ１４１が接続されてもよいし、ＰＮ接合ダイオード１４７のカソード側に信号線トランジスタ１４１が接続されてもよい。 At d in the figure, the voltage generation section connected to the vertical signal line 132 may include a signal line transistor 141 and a PN junction diode 147. At this time, the signal line transistor 141 may be connected to the anode side of the PN junction diode 147, or the signal line transistor 141 may be connected to the cathode side of the PN junction diode 147.
　同図におけるｅにおいて、垂直信号線１３２に接続される電圧生成部は、信号線トランジスタ１４１と、分圧抵抗１４８および１４９とを備えてもよい。分圧抵抗１４８および１４９は、互いに直列接続される。また、信号線トランジスタ１４１のソースは、分圧抵抗１４８および１４９の接続点に接続される。ここで、分圧抵抗１４８および１４９に流れる電流を低減するために、分圧抵抗１４８および１４９の抵抗値を大きくしてもよい。 At e in the figure, the voltage generation section connected to the vertical signal line 132 may include a signal line transistor 141 and voltage dividing resistors 148 and 149. Voltage dividing resistors 148 and 149 are connected in series with each other. Further, the source of the signal line transistor 141 is connected to a connection point between voltage dividing resistors 148 and 149. Here, in order to reduce the current flowing through the voltage dividing resistors 148 and 149, the resistance values of the voltage dividing resistors 148 and 149 may be increased.
　このように、上述の第１の実施の形態では、画素１２０からの信号読出し時に垂直信号線１３２をリセットすることで、画素１２０からの信号読出し時に流れる画素電流ＩＰＸに応じた電荷を容量１３３に蓄積することができる。このため、画素１２０から読出された信号を検出するために、画素１２０から読出された信号に応じた定電流を垂直信号線１３２に流す必要がなくなり、画素１２０からの信号読出し時の消費電流を低減することができる。 In this way, in the first embodiment described above, by resetting the vertical signal line 132 when reading out a signal from the pixel 120, charges corresponding to the pixel current IPX flowing when reading out a signal from the pixel 120 are transferred to the capacitor 133. Can be accumulated. Therefore, in order to detect the signal read out from the pixel 120, it is no longer necessary to flow a constant current according to the signal read out from the pixel 120 through the vertical signal line 132, and the current consumption when reading out the signal from the pixel 120 is reduced. can be reduced.
　また、信号線トランジスタ１４１と直列にダイオード接続トランジスタ１４２を接続することにより、垂直信号線１３２のリセット時にダイオード接続トランジスタ１４２の順方向電圧ＶＲ１に応じて垂直信号線１３２の電位を持ち上げることができる。このため、Ｐ相ＶＳＬセトリング開始時の垂直信号線１３２の電位を０Ｖより高くすることができ、セトリング時間を短縮することができる。 Furthermore, by connecting the diode-connected transistor 142 in series with the signal line transistor 141, the potential of the vertical signal line 132 can be raised according to the forward voltage VR1 of the diode-connected transistor 142 when the vertical signal line 132 is reset. Therefore, the potential of the vertical signal line 132 at the start of P-phase VSL settling can be made higher than 0V, and the settling time can be shortened.
　＜２．第２の実施の形態＞
　上述の第１の実施の形態では、垂直信号線１３２に電気的に接続された信号線トランジスタ１４１を介してダイオード接続トランジスタ１４２を接続した。この第２の実施の形態では、垂直信号線１３２に電気的に接続された信号線トランジスタ１４１が定電流トランジスタとして動作するように切り替えたり、ダイオード接続トランジスタ１４２に接続されるように切り替えたりする。 <2. Second embodiment>
In the first embodiment described above, the diode-connected transistor 142 is connected via the signal line transistor 141 electrically connected to the vertical signal line 132. In this second embodiment, the signal line transistor 141 electrically connected to the vertical signal line 132 is switched to operate as a constant current transistor or switched to be connected to the diode-connected transistor 142.
　図９は、第２の実施の形態に係る１カラム分の信号読出し回路の容量負荷読出し時の切替例を示すブロック図である。 FIG. 9 is a block diagram illustrating an example of switching during capacitive load reading of the signal readout circuit for one column according to the second embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路にサンプルホールド回路２０１と、スイッチ２０２および２０３とが追加されている。第２の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit has a sample and hold circuit 201 and switches 202 and 203 added to the signal readout circuit of the first embodiment described above. The other configuration of the signal readout circuit of the second embodiment is the same as that of the signal readout circuit of the first embodiment described above.
　サンプルホールド回路２０１は、信号線トランジスタ１４１を定電流トランジスタとして動作させるバイアス電圧Ｖｂをサンプルホールドし、信号線トランジスタ１４１のゲートに印加する。サンプルホールド回路２０１は、トランジスタ２１１およびコンデンサ２１２を備える。トランジスタ２１１は、ＭＯＳトランジスタでもよい。トランジスタ２１１のゲートには、サンプルホールド信号ΦＳＨが印加される。コンデンサ２１２は、トランジスタ２１１のソースとグランド電位との間に接続される。 The sample and hold circuit 201 samples and holds the bias voltage Vb that causes the signal line transistor 141 to operate as a constant current transistor, and applies it to the gate of the signal line transistor 141. Sample and hold circuit 201 includes a transistor 211 and a capacitor 212. Transistor 211 may be a MOS transistor. A sample and hold signal ΦSH is applied to the gate of the transistor 211. Capacitor 212 is connected between the source of transistor 211 and ground potential.
　スイッチ２０２は、信号線トランジスタ１４１のゲート入力を信号線リセット信号ΦＲＴとサンプルホールド回路２０１の出力との間で切り替える。スイッチ２０３は、信号線トランジスタ１４１の接続先をグランド電位とダイオード接続トランジスタ１４２との間で切り替える。 The switch 202 switches the gate input of the signal line transistor 141 between the signal line reset signal ΦRT and the output of the sample and hold circuit 201. The switch 203 switches the connection destination of the signal line transistor 141 between the ground potential and the diode-connected transistor 142.
　ここで、容量負荷読出しでは、スイッチ２０２は、信号線トランジスタ１４１のゲート入力を信号線リセット信号ΦＲＴに切り替える。また、スイッチ２０３は、信号線トランジスタ１４１の接続先をダイオード接続トランジスタ１４２に切り替える。このとき、信号読出し回路の動作は、図７と同様である。 Here, in capacitive load reading, the switch 202 switches the gate input of the signal line transistor 141 to the signal line reset signal ΦRT. Further, the switch 203 switches the connection destination of the signal line transistor 141 to the diode-connected transistor 142. At this time, the operation of the signal readout circuit is similar to that in FIG.
　図１０は、第２の実施の形態に係る１カラム分の信号読出し回路の定電流読出し時の切替例を示すブロック図である。 FIG. 10 is a block diagram showing an example of switching during constant current readout of the signal readout circuit for one column according to the second embodiment.
　同図において、定電流読出しでは、スイッチ２０２は、信号線トランジスタ１４１のゲート入力をサンプルホールド回路２０１の出力に切り替える。このとき、バイアス電圧Ｖｂは、信号線トランジスタ１４１がオンするように設定される。また、スイッチ２０３は、信号線トランジスタ１４１の接続先をグランド電位に切り替える。 In the figure, in constant current reading, a switch 202 switches the gate input of the signal line transistor 141 to the output of the sample and hold circuit 201. At this time, the bias voltage Vb is set so that the signal line transistor 141 is turned on. Further, the switch 203 switches the connection destination of the signal line transistor 141 to the ground potential.
　図１１は、第２の実施の形態に係る信号読出し回路の定電流読出しにおける各部の波形の一例を示す図である。 FIG. 11 is a diagram showing an example of waveforms of various parts during constant current readout of the signal readout circuit according to the second embodiment.
　同図において、定電流読出しでは、ＡＤ変換時の横引きノイズを防止するため、トランジスタ２１１がオンしてバイアス電圧Ｖｂがサンプルホールドされる。そして、トランジスタ２１１がオフし、サンプルホールド回路２０１にサンプルホールドされたバイアス電圧Ｖｂが信号線トランジスタ１４１のゲートに印加されることで、信号線トランジスタ１４１が定電流トランジスタとして動作する。 In the figure, in constant current readout, the transistor 211 is turned on and the bias voltage Vb is sampled and held in order to prevent horizontal scanning noise during AD conversion. Then, the transistor 211 is turned off and the bias voltage Vb sampled and held by the sample and hold circuit 201 is applied to the gate of the signal line transistor 141, so that the signal line transistor 141 operates as a constant current transistor.
　次に、画素リセットが実施される（Ｋ２１）。このとき、画素リセット信号ΦＰＲＴが立ち上がり（ｔ２１）、リセットトランジスタ１２３がオンしてフローティングディフュージョン１２６がリセットされる。また、選択信号ΦＳＥＬが立ち上がり（ｔ２１）、選択トランジスタ１２５がオンする。このとき、電源電位Ｖｄｄが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて垂直信号線１３２の電位ＶＳＬが設定される。 Next, pixel reset is performed (K21). At this time, the pixel reset signal ΦPRT rises (t21), the reset transistor 123 is turned on, and the floating diffusion 126 is reset. Further, the selection signal ΦSEL rises (t21), and the selection transistor 125 is turned on. At this time, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the power supply potential Vdd is applied to the gate of the amplification transistor 124.
　次に、Ｐ相ＶＳＬセトリングが実施される（Ｋ２２）。このとき、画素リセット信号ΦＰＲＴが立ち下がり（ｔ２２）、リセットトランジスタ１２３がオフする。そして、フローティングディフュージョン１２６のリセットレベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて垂直信号線１３２の電位ＶＳＬが設定される。 Next, P-phase VSL settling is performed (K22). At this time, the pixel reset signal ΦPRT falls (t22), and the reset transistor 123 is turned off. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the reset level of the floating diffusion 126 is applied to the gate of the amplification transistor 124.
　次に、Ｐ相ＡＤが実施される（Ｋ２３）。このとき、参照信号ＲＡＰとしてランプ信号がコンパレータ１４３に供給される。そして、コンパレータ１４３において、リセットレベルに応じた垂直信号線１３２の電位ＶＳＬが参照信号ＲＡＰと比較され、参照信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＳＬと一致したときのタイミングが比較結果ＣＯＰとして出力される。このとき、参照信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＳＬと一致するまでのカウント動作に基づいて、画素１２０から読み出されたリセットレベルがＡＤ変換される。 Next, P-phase AD is performed (K23). At this time, the ramp signal is supplied to the comparator 143 as the reference signal RAP. Then, in the comparator 143, the potential VSL of the vertical signal line 132 according to the reset level is compared with the reference signal RAP, and the timing when the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 is determined as the comparison result COP. Output. At this time, the reset level read from the pixel 120 is AD converted based on a counting operation until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132.
　次に、転送が実施される（Ｋ２４）。このとき、転送信号ΦＴＧが立ち上がり（ｔ２４）、転送トランジスタ１２２がオンしてフォトダイオード１２１に蓄積された電荷がフローティングディフュージョン１２６に転送される。また、フォトダイオード１２１のカソード電位が増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて垂直信号線１３２の電位ＶＳＬが設定される。 Next, transfer is performed (K24). At this time, the transfer signal ΦTG rises (t24), the transfer transistor 122 is turned on, and the charges accumulated in the photodiode 121 are transferred to the floating diffusion 126. Further, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the cathode potential of the photodiode 121 is applied to the gate of the amplification transistor 124.
　次に、Ｄ相ＶＳＬセトリングが実施される（Ｋ２５）。このとき、転送信号ΦＴＧが立ち下がり（ｔ２５）、転送トランジスタ１２２がオフする。そして、フローティングディフュージョン１２６の信号レベルが増幅トランジスタ１２４のゲートに印加された時のソースフォロワ動作に基づいて垂直信号線１３２の電位ＶＳＬが設定される。 Next, D-phase VSL settling is performed (K25). At this time, the transfer signal ΦTG falls (t25) and the transfer transistor 122 is turned off. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the signal level of the floating diffusion 126 is applied to the gate of the amplification transistor 124.
　次に、Ｐ相ＡＤが実施される（Ｋ２６）。このとき、参照信号ＲＡＰとしてランプ信号がコンパレータ１４３に供給される（ｔ２６－ｔ２７）。そして、コンパレータ１４３において、信号レベルに応じた垂直信号線１３２の電位ＶＳＬが参照信号ＲＡＰと比較され、参照信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＳＬと一致したときのタイミングが比較結果ＣＯＰとして出力される。このとき、参照信号ＲＡＰのレベルが垂直信号線１３２の電位ＶＳＬと一致するまでのカウント動作に基づいて、画素１２０から読み出された信号レベルがＡＤ変換される。 Next, P-phase AD is performed (K26). At this time, the ramp signal is supplied to the comparator 143 as the reference signal RAP (t26-t27). Then, in the comparator 143, the potential VSL of the vertical signal line 132 according to the signal level is compared with the reference signal RAP, and the timing when the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 is determined as the comparison result COP. Output. At this time, the signal level read from the pixel 120 is AD converted based on a counting operation until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132.
　このように、上述の第２の実施の形態では、垂直信号線１３２をリセットするために信号線トランジスタ１４１を用いたり、定電流トランジスタとして信号線トランジスタ１４１を用いたりすることができる。これにより、容量負荷読出しと定電流読出しとを切り替えることが可能となり、撮像装置の使用形態に応じて撮像装置を低消費電力動作させたり、高速動作させたりすることができる。 In this way, in the second embodiment described above, the signal line transistor 141 can be used to reset the vertical signal line 132, or the signal line transistor 141 can be used as a constant current transistor. This makes it possible to switch between capacitive load readout and constant current readout, and it is possible to operate the imaging device with low power consumption or at high speed depending on how the imaging device is used.
　＜３．第３の実施の形態＞
　上述の第２の実施の形態では、スイッチ２０２および２０３の切替動作に基づいて、定電流読出しと容量負荷読出しとを切替可能とした。この第３の実施の形態では、定電流読出しと容量負荷読出しとを切替可能とするために、信号線トランジスタ１４１とダイオード接続トランジスタ１４２との直列回路に並列に定電流トランジスタを接続する。 <3. Third embodiment>
In the second embodiment described above, it is possible to switch between constant current readout and capacitive load readout based on the switching operations of switches 202 and 203. In this third embodiment, a constant current transistor is connected in parallel to a series circuit of a signal line transistor 141 and a diode-connected transistor 142 in order to enable switching between constant current readout and capacitive load readout.
　図１２は、第３の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。 FIG. 12 is a diagram showing a configuration example of a signal readout circuit for one column according to the third embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路にサンプルホールド回路２０１および定電流トランジスタ３０１が追加されている。第３の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit has a sample hold circuit 201 and a constant current transistor 301 added to the signal readout circuit of the first embodiment described above. The other configuration of the signal readout circuit of the third embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　定電流トランジスタ３０１は、垂直信号線１３２に電気的に接続される。定電流トランジスタ３０１は、ＭＯＳトランジスタでもよい。サンプルホールド回路２０１の出力は、定電流トランジスタ３０１のゲートに接続される。 The constant current transistor 301 is electrically connected to the vertical signal line 132. Constant current transistor 301 may be a MOS transistor. The output of sample hold circuit 201 is connected to the gate of constant current transistor 301.
　ここで、容量負荷読出しでは、バイアス電圧Ｖｂは０Ｖに設定され、サンプルホールド信号ΦＳＨはハイレベルに設定される。この場合、定電流トランジスタ３０１はオフされ、定電流トランジスタ３０１には電流は流れない。このときの信号読出し回路の動作は、図７と同様である。 Here, in capacitive load reading, bias voltage Vb is set to 0V and sample hold signal ΦSH is set to high level. In this case, the constant current transistor 301 is turned off, and no current flows through the constant current transistor 301. The operation of the signal readout circuit at this time is similar to that in FIG.
　定電流読出しでは、トランジスタ２１１がオンしてバイアス電圧Ｖｂがサンプルホールドされる。そして、トランジスタ２１１がオフし、サンプルホールド回路２０１にサンプルホールドされたバイアス電圧Ｖｂが定電流トランジスタ３０１のゲートに印加される。この場合、定電流トランジスタ３０１はオンされ、定電流トランジスタ３０１には定電流が流れる。このときの信号読出し回路の動作は、図１１と同様である。 In constant current reading, the transistor 211 is turned on and the bias voltage Vb is sampled and held. Then, the transistor 211 is turned off, and the bias voltage Vb sampled and held by the sample and hold circuit 201 is applied to the gate of the constant current transistor 301. In this case, the constant current transistor 301 is turned on, and a constant current flows through the constant current transistor 301. The operation of the signal readout circuit at this time is similar to that in FIG.
　このように、上述の第３の実施の形態では、信号線トランジスタ１４１とダイオード接続トランジスタ１４２との直列回路に並列に定電流トランジスタ３０１を接続する。これにより、スイッチ２０２および２０３を設けることなく、定電流読出しと容量負荷読出しとを切り替えることが可能となるとともに、容量負荷読出し時のセトリング時間を短縮することができる。 In this manner, in the third embodiment described above, the constant current transistor 301 is connected in parallel to the series circuit of the signal line transistor 141 and the diode-connected transistor 142. This makes it possible to switch between constant current readout and capacitive load readout without providing switches 202 and 203, and to shorten the settling time during capacitive load readout.
　＜４．第４の実施の形態＞
　上述の第３の実施の形態では、定電流読出しと容量負荷読出しとを切替可能とするために、信号線トランジスタ１４１とダイオード接続トランジスタ１４２との直列回路に並列に定電流トランジスタ３０１を接続した。この第４の実施の形態では、定電流読出しと容量負荷読出しとを切替可能とするために、垂直信号線１３２に電気的に接続された信号線トランジスタ１４１に直列に接続された直列トランジスタのゲートとドレインとの間に開閉トランジスタを接続する。 <4. Fourth embodiment>
In the third embodiment described above, the constant current transistor 301 is connected in parallel to the series circuit of the signal line transistor 141 and the diode-connected transistor 142 in order to enable switching between constant current reading and capacitive load reading. In this fourth embodiment, in order to enable switching between constant current readout and capacitive load readout, the gate of a series transistor connected in series to a signal line transistor 141 electrically connected to a vertical signal line 132 is used. A switching transistor is connected between the and the drain.
　図１３は、第４の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。 FIG. 13 is a diagram showing a configuration example of a signal readout circuit for one column according to the fourth embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路のダイオード接続トランジスタ１４２に代えて、直列トランジスタ４０２が設けられている。また、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路にサンプルホールド回路２０１および開閉トランジスタ４０１が追加されている。第４の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit is provided with a series transistor 402 in place of the diode-connected transistor 142 of the signal readout circuit of the first embodiment described above. Further, this signal readout circuit has a sample hold circuit 201 and an open/close transistor 401 added to the signal readout circuit of the first embodiment described above. The other configuration of the signal readout circuit of the fourth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　直列トランジスタ４０２は、信号線トランジスタ１４１に直列に接続されている。直列トランジスタ４０２のゲートとドレインとの間には、開閉トランジスタ４０１が接続されている。開閉トランジスタ４０１のゲートには、開閉信号ＤＳＦが印加される。直列トランジスタ４０２および開閉トランジスタ４０１は、ＭＯＳトランジスタでもよい。 The series transistor 402 is connected in series to the signal line transistor 141. A switching transistor 401 is connected between the gate and drain of the series transistor 402. A switching signal DSF is applied to the gate of the switching transistor 401. The series transistor 402 and the switching transistor 401 may be MOS transistors.
　ここで、容量負荷読出しでは、開閉信号ＤＳＦはハイレベルに設定され、開閉トランジスタ４０１はオンされる。このとき、直列トランジスタ４０２のゲートとドレインとは短絡され、直列トランジスタ４０２はダイオード接続トランジスタとして動作する。また、サンプルホールド信号ΦＳＨはロウレベルに設定され、トランジスタ２１１はオフされる。このときの信号読出し回路の動作は、図７と同様である。 Here, in capacitive load reading, the switching signal DSF is set to a high level, and the switching transistor 401 is turned on. At this time, the gate and drain of the series transistor 402 are short-circuited, and the series transistor 402 operates as a diode-connected transistor. Further, the sample hold signal ΦSH is set to low level, and the transistor 211 is turned off. The operation of the signal readout circuit at this time is similar to that in FIG.
　定電流読出しでは、開閉信号ＤＳＦはロウレベルに設定され、開閉トランジスタ４０１はオフされる。また、トランジスタ２１１がオンしてバイアス電圧Ｖｂがサンプルホールドされる。そして、トランジスタ２１１がオフし、サンプルホールド回路２０１にサンプルホールドされたバイアス電圧Ｖｂが直列トランジスタ４０２のゲートに印加される。この場合、直列トランジスタ４０２はオンされ、直列トランジスタ４０２には定電流が流れる。このときの信号読出し回路の動作は、図１１と同様である。 In constant current reading, the switching signal DSF is set to low level, and the switching transistor 401 is turned off. Further, the transistor 211 is turned on and the bias voltage Vb is sampled and held. Then, the transistor 211 is turned off, and the bias voltage Vb sampled and held by the sample and hold circuit 201 is applied to the gate of the series transistor 402. In this case, the series transistor 402 is turned on and a constant current flows through the series transistor 402. The operation of the signal readout circuit at this time is similar to that in FIG.
　このように、上述の第４の実施の形態では、信号線トランジスタ１４１に直列に直列トランジスタ４０２を接続し、直列トランジスタ４０２のゲートとドレインとの間に開閉トランジスタ４０１を接続する。これにより、スイッチ２０２および２０３を設けることなく、定電流読出しと容量負荷読出しとを切り替えることが可能となるとともに、容量負荷読出し時のセトリング時間を短縮することができる。 In this way, in the fourth embodiment described above, the series transistor 402 is connected in series to the signal line transistor 141, and the opening/closing transistor 401 is connected between the gate and drain of the series transistor 402. This makes it possible to switch between constant current readout and capacitive load readout without providing switches 202 and 203, and to shorten the settling time during capacitive load readout.
　＜５．第５の実施の形態＞
　上述の第１の実施の形態では、ダイオード接続トランジスタ１４２をカラムごとに設けた。この第５の実施の形態では、複数のカラムでダイオード接続トランジスタ１４２を共有する。 <5. Fifth embodiment>
In the first embodiment described above, diode-connected transistors 142 are provided for each column. In this fifth embodiment, a diode-connected transistor 142 is shared by a plurality of columns.
　図１４は、第５の実施の形態に係る２カラム分の信号読出し回路の構成例を示す図である。 FIG. 14 is a diagram showing a configuration example of a signal readout circuit for two columns according to the fifth embodiment.
　同図において、この信号読出し回路は、複数の垂直信号線１３２－１および１３２－２が設けられるとともに、上述の第１の実施の形態の信号読出し回路にスイッチ５０１および５０２が追加されている。第５の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit is provided with a plurality of vertical signal lines 132-1 and 132-2, and switches 501 and 502 are added to the signal readout circuit of the above-described first embodiment. The rest of the configuration of the signal readout circuit of the fifth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　垂直信号線１３２－１および１３２－２には、画素１２０が接続されるとともに、垂直信号線１３２－１および１３２－２ごとにコンパレータ１４３が設けられる。また、各垂直信号線１３２－１および１３２－２には、信号線トランジスタ１４１が接続されるとともに、垂直信号線１３２－１および１３２－２ごとにスイッチ５０１および５０２が設けられる。 The pixels 120 are connected to the vertical signal lines 132-1 and 132-2, and a comparator 143 is provided for each of the vertical signal lines 132-1 and 132-2. Further, a signal line transistor 141 is connected to each vertical signal line 132-1 and 132-2, and switches 501 and 502 are provided for each vertical signal line 132-1 and 132-2.
　スイッチ５０１は、垂直信号線１３２－１に接続された信号線トランジスタ１４１の接続先を、グランド電位とダイオード接続トランジスタ１４２との間で切り替える。スイッチ５０２は、垂直信号線１３２－２に接続された信号線トランジスタ１４１の接続先を、グランド電位とダイオード接続トランジスタ１４２との間で切り替える。ここで、垂直信号線１３２－１および１３２－２ごとに接続されたそれぞれの信号線トランジスタ１４１の接続先を、ダイオード接続トランジスタ１４２に切り替えることにより、複数のカラムでダイオード接続トランジスタ１４２を共有することができる。 The switch 501 switches the connection destination of the signal line transistor 141 connected to the vertical signal line 132-1 between the ground potential and the diode-connected transistor 142. The switch 502 switches the connection destination of the signal line transistor 141 connected to the vertical signal line 132-2 between the ground potential and the diode-connected transistor 142. Here, by switching the connection destination of each signal line transistor 141 connected to each vertical signal line 132-1 and 132-2 to a diode-connected transistor 142, the diode-connected transistor 142 can be shared by a plurality of columns. I can do it.
　このとき、垂直信号線１３２－１に接続されたコンパレータ１４３では、垂直信号線１３２－１の電位ＶＳＬ１は参照信号ＲＡＰと比較され、その比較結果ＣＯＰ１が出力される。垂直信号線１３２－２に接続されたコンパレータ１４３では、垂直信号線１３２－２の電位ＶＳＬ２は参照信号ＲＡＰと比較され、その比較結果ＣＯＰ２が出力される。 At this time, the comparator 143 connected to the vertical signal line 132-1 compares the potential VSL1 of the vertical signal line 132-1 with the reference signal RAP, and outputs the comparison result COP1. A comparator 143 connected to the vertical signal line 132-2 compares the potential VSL2 of the vertical signal line 132-2 with the reference signal RAP, and outputs the comparison result COP2.
　このように、上述の第５の実施の形態では、複数のカラムでダイオード接続トランジスタ１４２を共有する。これにより、ダイオード接続トランジスタ１４２の個数の増大を抑制しつつ、カラム数を増大させることが可能となる。 In this way, in the fifth embodiment described above, the diode-connected transistor 142 is shared by a plurality of columns. This makes it possible to increase the number of columns while suppressing an increase in the number of diode-connected transistors 142.
　＜６．第６の実施の形態＞
　上述の第１の実施の形態では、垂直信号線１３２のリセットレベルをカラムごとに設定した。この第６の実施の形態では、垂直信号線１３２のリセットレベルを複数のカラムで共通に設定する。 <6. Sixth embodiment>
In the first embodiment described above, the reset level of the vertical signal line 132 is set for each column. In this sixth embodiment, the reset level of the vertical signal line 132 is set commonly for a plurality of columns.
　図１５は、第６の実施の形態に係る４カラム分の信号読出し回路の構成例を示す図である。 FIG. 15 is a diagram showing a configuration example of a signal readout circuit for four columns according to the sixth embodiment.
　同図において、この信号読出し回路は、複数の垂直信号線１３２－１から１３２－４が設けられるとともに、上述の第１の実施の形態の信号読出し回路に短絡線６０１が追加されている。第６の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit is provided with a plurality of vertical signal lines 132-1 to 132-4, and a shorting line 601 is added to the signal readout circuit of the first embodiment described above. The rest of the configuration of the signal readout circuit of the sixth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　各垂直信号線１３２－１から１３２－４には、画素１２０が接続されるとともに、垂直信号線１３２－１から１３２－４ごとにコンパレータ１４３が設けられる。また、各垂直信号線１３２－１から１３２－４には、信号線トランジスタ１４１をそれぞれ介してダイオード接続トランジスタ１４２が接続される。また、垂直信号線１３２－１から１３２－４ごとに設けられたダイオード接続トランジスタ１４２のドレインは、短絡線６０１を介して互いに接続される。 A pixel 120 is connected to each vertical signal line 132-1 to 132-4, and a comparator 143 is provided for each vertical signal line 132-1 to 132-4. Further, a diode-connected transistor 142 is connected to each of the vertical signal lines 132-1 to 132-4 via a signal line transistor 141, respectively. Furthermore, the drains of the diode-connected transistors 142 provided for each of the vertical signal lines 132-1 to 132-4 are connected to each other via a shorting line 601.
　このとき、垂直信号線１３２－１に接続されたコンパレータ１４３では、垂直信号線１３２－１の電位ＶＳＬ１は参照信号ＲＡＰと比較され、その比較結果ＣＯＰ１が出力される。垂直信号線１３２－２に接続されたコンパレータ１４３では、垂直信号線１３２－２の電位ＶＳＬ２は参照信号ＲＡＰと比較され、その比較結果ＣＯＰ２が出力される。垂直信号線１３２－３に接続されたコンパレータ１４３では、垂直信号線１３２－３の電位ＶＳＬ３は参照信号ＲＡＰと比較され、その比較結果ＣＯＰ３が出力される。垂直信号線１３２－４に接続されたコンパレータ１４３では、垂直信号線１３２－４の電位ＶＳＬ４は参照信号ＲＡＰと比較され、その比較結果ＣＯＰ４が出力される。 At this time, the comparator 143 connected to the vertical signal line 132-1 compares the potential VSL1 of the vertical signal line 132-1 with the reference signal RAP, and outputs the comparison result COP1. A comparator 143 connected to the vertical signal line 132-2 compares the potential VSL2 of the vertical signal line 132-2 with the reference signal RAP, and outputs the comparison result COP2. A comparator 143 connected to the vertical signal line 132-3 compares the potential VSL3 of the vertical signal line 132-3 with the reference signal RAP, and outputs the comparison result COP3. A comparator 143 connected to the vertical signal line 132-4 compares the potential VSL4 of the vertical signal line 132-4 with the reference signal RAP, and outputs the comparison result COP4.
　このように、上述の第６の実施の形態では、短絡線６０１を介して異なるカラムのダイオード接続トランジスタ１４２のドレインを互いに接続する。これにより、垂直信号線１３２のリセットレベルのカラムごとのバラツキを低減しつつ、カラムごとに容量負荷読出しを実施することができる。 In this manner, in the sixth embodiment described above, the drains of diode-connected transistors 142 in different columns are connected to each other via the shorting line 601. Thereby, capacitive load reading can be performed for each column while reducing variations in the reset level of the vertical signal line 132 from column to column.
　＜７．第７の実施の形態＞
　上述の第１の実施の形態では、垂直信号線１３２のリセットレベルがＰ相ＶＳＬセトリングとＤ相ＶＳＬセトリングとで１つの値に固定されていた。この第７の実施の形態では、垂直信号線１３２のリセットレベルをＰ相ＶＳＬセトリングとＤ相ＶＳＬセトリングとで切り替え可能とする。 <7. Seventh embodiment>
In the first embodiment described above, the reset level of the vertical signal line 132 is fixed to one value for P-phase VSL settling and D-phase VSL settling. In this seventh embodiment, the reset level of the vertical signal line 132 can be switched between P-phase VSL settling and D-phase VSL settling.
　図１６は、第７の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。 FIG. 16 is a diagram showing a configuration example of a signal readout circuit for one column according to the seventh embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路にスイッチ７０１と、ダイオード接続トランジスタ７０２および７０３が追加されている。第７の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit has a switch 701 and diode-connected transistors 702 and 703 added to the signal readout circuit of the first embodiment described above. The rest of the configuration of the signal readout circuit of the seventh embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　ダイオード接続トランジスタ７０２および７０３は、互いに直列に接続されている。スイッチ７０１は、信号線トランジスタ１４１の接続先をダイオード接続トランジスタ１４２と、ダイオード接続トランジスタ７０２および７０３の直列回路との間で切り替える。 Diode-connected transistors 702 and 703 are connected in series with each other. Switch 701 switches the connection destination of signal line transistor 141 between diode-connected transistor 142 and a series circuit of diode-connected transistors 702 and 703.
　このとき、信号線トランジスタ１４１がダイオード接続トランジスタ１４２に接続された場合、垂直信号線１３２のリセットレベルをダイオード接続トランジスタ１４２の順方向電圧ＶＲ１だけ持ち上げることができる。信号線トランジスタ１４１がダイオード接続トランジスタ７０２および７０３の直列回路に接続された場合、垂直信号線１３２のリセットレベルを各ダイオード接続トランジスタ７０２および７０３の順方向電圧の和ＶＲ２だけ持ち上げることができる。 At this time, if the signal line transistor 141 is connected to the diode-connected transistor 142, the reset level of the vertical signal line 132 can be raised by the forward voltage VR1 of the diode-connected transistor 142. When signal line transistor 141 is connected to a series circuit of diode-connected transistors 702 and 703, the reset level of vertical signal line 132 can be raised by the sum VR2 of the forward voltages of each diode-connected transistor 702 and 703.
　図１７は、第７の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。 FIG. 17 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the seventh embodiment.
　同図において、容量負荷読出し動作は、図７と同様である。ただし、Ｐ相ＡＤ（Ｋ１３）前の画素リセット／ＶＳＬリセット（Ｋ１１）において、信号線トランジスタ１４１は、ダイオード接続トランジスタ７０２および７０３の直列回路に接続される。このとき、垂直信号線１３２のリセットレベルは、各ダイオード接続トランジスタ７０２および７０３の順方向電圧の和ＶＲ２に設定される。Ｄ相ＡＤ（Ｋ１６）前の転送／ＶＳＬリセット（Ｋ１４）において、信号線トランジスタ１４１は、ダイオード接続トランジスタ１４２に接続される。このとき、垂直信号線１３２のリセットレベルは、ダイオード接続トランジスタ１４２の順方向電圧ＶＲ１に設定される。 In the figure, the capacitive load read operation is the same as in FIG. 7. However, in the pixel reset/VSL reset (K11) before the P-phase AD (K13), the signal line transistor 141 is connected to the series circuit of diode-connected transistors 702 and 703. At this time, the reset level of the vertical signal line 132 is set to the sum VR2 of the forward voltages of the respective diode-connected transistors 702 and 703. In the transfer/VSL reset (K14) before the D-phase AD (K16), the signal line transistor 141 is connected to the diode-connected transistor 142. At this time, the reset level of the vertical signal line 132 is set to the forward voltage VR1 of the diode-connected transistor 142.
　このように、上述の第７の実施の形態では、Ｐ相ＶＳＬセトリングにおける垂直信号線１３２のリセットレベルを、Ｄ相ＶＳＬセトリングにおける垂直信号線１３２のリセットレベルより高くする。これにより、容量負荷読出しにおけるＰ相ＡＤ（Ｋ１３）前のセトリング時間を短縮することが可能となる。また、大光量入射時の垂直信号線１３２の垂直信号線１３２の電位ＶＳＬを各ダイオード接続トランジスタ７０２および７０３の順方向電圧の和ＶＲ２でクリップすることができ、太陽黒点現象を防止することができる。 In this manner, in the seventh embodiment described above, the reset level of the vertical signal line 132 during P-phase VSL settling is set higher than the reset level of the vertical signal line 132 during D-phase VSL settling. This makes it possible to shorten the settling time before P-phase AD (K13) in capacitive load reading. Further, the potential VSL of the vertical signal line 132 when a large amount of light is incident can be clipped by the sum VR2 of the forward voltages of the respective diode-connected transistors 702 and 703, and the sunspot phenomenon can be prevented. .
　なお、上述の第７の実施の形態では、垂直信号線１３２のリセットレベルを切り替え可能とするために、ダイオード接続トランジスタ１４２に加えて、ダイオード接続トランジスタ７０２および７０３の直列回路を設けた。垂直信号線１３２のリセットレベルを切り替え可能とするために、ダイオード接続トランジスタの３段以上の直列回路を設けてもよい。また、垂直信号線１３２のリセットレベルが切り替え可能な構成は、上述の第２の実施の形態から第６の実施の形態のいずれの構成に適用してもよい。 Note that in the seventh embodiment described above, in addition to the diode-connected transistor 142, a series circuit of diode-connected transistors 702 and 703 is provided in order to make it possible to switch the reset level of the vertical signal line 132. In order to make it possible to switch the reset level of the vertical signal line 132, a series circuit of three or more stages of diode-connected transistors may be provided. Further, the configuration in which the reset level of the vertical signal line 132 can be switched may be applied to any of the configurations of the second to sixth embodiments described above.
　＜８．第８の実施の形態＞
　上述の第１の実施の形態では、画素１２０から読み出された信号を伝送する垂直信号線１３２に電気的に接続された信号線トランジスタ１４１を介してダイオード接続トランジスタ１４２を接続した。この第８の実施の形態では、画素１２０が設けられた上層チップに信号線トランジスタ１４１およびダイオード接続トランジスタ１４２を設け、定電流トランジスタ３０１を下層チップに設ける。 <8. Eighth embodiment>
In the first embodiment described above, the diode-connected transistor 142 is connected via the signal line transistor 141 that is electrically connected to the vertical signal line 132 that transmits the signal read out from the pixel 120. In this eighth embodiment, a signal line transistor 141 and a diode-connected transistor 142 are provided in the upper layer chip in which the pixel 120 is provided, and a constant current transistor 301 is provided in the lower layer chip.
　図１８は、第８の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。 FIG. 18 is a diagram showing a configuration example of a signal readout circuit for one column according to the eighth embodiment.
　同図において、この信号読出し回路の回路構成は、図１２の信号読出し回路の回路構成と同様である。ただし、この信号読出し回路は積層チップに形成される。この積層チップは、上層チップ８０１および下層チップ８０２を備える。上層チップ８０１は、下層チップ８０２上に積層される。 In the figure, the circuit configuration of this signal readout circuit is similar to the circuit configuration of the signal readout circuit in FIG. However, this signal readout circuit is formed on a stacked chip. This stacked chip includes an upper layer chip 801 and a lower layer chip 802. Upper layer chip 801 is stacked on lower layer chip 802 .
　上層チップ８０１には、画素１２０、垂直信号線１３２、信号線トランジスタ１４１およびダイオード接続トランジスタ１４２が形成される。このとき、信号線トランジスタ１４１のサイズおよびしきい値は、選択トランジスタ１２５のサイズおよびしきい値と同様に設定することができる。ダイオード接続トランジスタ１４２のサイズおよびしきい値は、リセットトランジスタ１２３のサイズおよびしきい値と同様に設定することができる。 A pixel 120, a vertical signal line 132, a signal line transistor 141, and a diode-connected transistor 142 are formed on the upper layer chip 801. At this time, the size and threshold of the signal line transistor 141 can be set similarly to the size and threshold of the selection transistor 125. The size and threshold of diode-connected transistor 142 can be set similarly to the size and threshold of reset transistor 123.
　下層チップ８０２には、サンプルホールド回路２０１、定電流トランジスタ３０１およびコンパレータ１４３が形成される。このとき、垂直信号線１３２は、上層チップ８０１から下層チップ８０２にかけて配線することができる。 A sample and hold circuit 201, a constant current transistor 301, and a comparator 143 are formed in the lower chip 802. At this time, the vertical signal line 132 can be wired from the upper layer chip 801 to the lower layer chip 802.
　このように、上述の第８の実施の形態では、画素１２０が形成された上層チップ８０１に信号線トランジスタ１４１およびダイオード接続トランジスタ１４２を形成する。これにより、画素１２０に設けられた画素トランジスタの特性バラツキと、信号線トランジスタ１４１およびダイオード接続トランジスタ１４２の特性バラツキとを等しくすることができる。また、信号読出し回路が積層チップに形成される構成は、上述の第２の実施の形態から第７の実施の形態のいずれの構成に適用してもよい。 In this manner, in the eighth embodiment described above, the signal line transistor 141 and the diode-connected transistor 142 are formed in the upper layer chip 801 on which the pixel 120 is formed. Thereby, variations in the characteristics of the pixel transistor provided in the pixel 120 can be made equal to variations in the characteristics of the signal line transistor 141 and the diode-connected transistor 142. Furthermore, the configuration in which the signal readout circuit is formed on a stacked chip may be applied to any of the configurations of the second to seventh embodiments described above.
　＜９．第９の実施の形態＞
　上述の第１の実施の形態では、１つの増幅トランジスタ１２４に対して１つのフォトダイオード１２１が設けられた画素１２０に容量負荷読出しを適用した。この第９の実施の形態では、１つの増幅トランジスタ１２４に対して４つのフォトダイオードが設けられたセルに容量負荷読出しを適用する。 <9. Ninth embodiment>
In the first embodiment described above, capacitive load readout is applied to the pixel 120 in which one photodiode 121 is provided for one amplification transistor 124. In this ninth embodiment, capacitive load readout is applied to a cell in which four photodiodes are provided for one amplification transistor 124.
　図１９は、第９の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。 FIG. 19 is a diagram showing a configuration example of a signal readout circuit for one column according to the ninth embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路の画素１２０に代えて、セル１３０が設けられている。第９の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit is provided with a cell 130 in place of the pixel 120 of the signal readout circuit of the first embodiment described above. The rest of the configuration of the signal readout circuit of the ninth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　セル１３０は、上述の第１の実施の形態のフォトダイオード１２１および転送トランジスタ１２２に代えて、フォトダイオード１２１－１から１２１－４および転送トランジスタ１２２－１から１２２－４が設けられている。第９の実施の形態のセル１３０のそれ以外の構成は、上述の第１の実施の形態の画素１２０の構成と同様である。 The cell 130 is provided with photodiodes 121-1 to 121-4 and transfer transistors 122-1 to 122-4 in place of the photodiode 121 and transfer transistor 122 of the first embodiment described above. The other configuration of the cell 130 of the ninth embodiment is similar to the configuration of the pixel 120 of the first embodiment described above.
　各フォトダイオード１２１－１から１２１－４は、２行×２列に配置することができる。各フォトダイオード１２１－１から１２１－４は、転送トランジスタ１２２－１から１２２－４をそれぞれ介し、フローティングディフュージョン１２６に接続されている。各転送トランジスタ１２２－１から１２２－４のゲートには、転送信号ΦＴＧ１～ΦＴＧ４が印加される。この転送信号ΦＴＧ１～ΦＴＧ４の印加タイミングを制御することにより、各フォトダイオード１２１－１から１２１－４から垂直信号線１３２に個別に信号を読み出すことができる。各フォトダイオード１２１－１から１２１－４からの容量負荷読出し動作は、図７と同様である。 Each photodiode 121-1 to 121-4 can be arranged in two rows and two columns. Each of the photodiodes 121-1 to 121-4 is connected to the floating diffusion 126 via transfer transistors 122-1 to 122-4, respectively. Transfer signals ΦTG1 to ΦTG4 are applied to the gates of each of the transfer transistors 122-1 to 122-4. By controlling the application timing of the transfer signals ΦTG1 to ΦTG4, signals can be read out individually from each photodiode 121-1 to 121-4 to the vertical signal line 132. The capacitive load reading operation from each photodiode 121-1 to 121-4 is similar to that in FIG.
　このように、上述の第９の実施の形態では、１つの増幅トランジスタ１２４に対して４つのフォトダイオードを共有する。これにより、画素領域の増大を抑制しつつ、画素数を増大させることが可能となるとともに、画素ごとに容量負荷読出しを適用することができる。 In this way, in the ninth embodiment described above, one amplification transistor 124 shares four photodiodes. Thereby, it is possible to increase the number of pixels while suppressing an increase in the pixel area, and it is also possible to apply capacitive load readout to each pixel.
　なお、上述の第９の実施の形態では、１つの増幅トランジスタ１２４に対して４つのフォトダイオード１２１－１から１２１－４を共有した例を示したが、１つの増幅トランジスタ１２４に対して８つのフォトダイオードを共有してもよい。また、セル１３０が設けられた構成について、上述の第２の実施の形態から第８の実施の形態のいずれの構成を適用してもよい。 In the above-described ninth embodiment, an example was shown in which four photodiodes 121-1 to 121-4 were shared for one amplification transistor 124, but eight photodiodes 121-1 to 121-4 were shared for one amplification transistor 124. Photodiodes may be shared. Furthermore, for the configuration in which the cell 130 is provided, any of the configurations from the second embodiment to the eighth embodiment described above may be applied.
　＜１０．第１０の実施の形態＞
　上述の第１の実施の形態では、垂直信号線１３２に接続された画素１２０からの個別の信号読出しに容量負荷読出しを適用した。この第１０の実施の形態では、垂直信号線１３２に接続された画素１２０からのビニング読出しに容量負荷読出しを適用する。 <10. Tenth embodiment>
In the first embodiment described above, capacitive load readout is applied to read out individual signals from the pixels 120 connected to the vertical signal line 132. In this tenth embodiment, capacitive load readout is applied to binning readout from pixels 120 connected to vertical signal line 132.
　図２０は、第１０の実施の形態に係る１カラム分の信号読出し回路の構成例を示す図である。 FIG. 20 is a diagram showing a configuration example of a signal readout circuit for one column according to the tenth embodiment.
　同図において、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路の画素１２０に代えて、画素１４０および１５０が設けられている。また、この信号読出し回路は、上述の第１の実施の形態の信号読出し回路にビニング線１３４が追加されている。第１０の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit is provided with pixels 140 and 150 in place of the pixel 120 of the signal readout circuit of the first embodiment described above. Further, in this signal readout circuit, a binning line 134 is added to the signal readout circuit of the first embodiment described above. The rest of the configuration of the signal readout circuit of the tenth embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　各画素１４０および１５０は、上述の第１の実施の形態の画素１２０にビニングトランジスタ１２７が追加されている。第１０の実施の形態の各画素１４０および１５０のそれ以外の構成は、上述の第１の実施の形態の画素１２０の構成と同様である。 Each pixel 140 and 150 has a binning transistor 127 added to the pixel 120 of the first embodiment described above. The other configurations of each pixel 140 and 150 in the tenth embodiment are similar to the configuration of the pixel 120 in the first embodiment described above.
　ビニングトランジスタ１２７は、フローティングディフュージョン１２６とビニング線１３４との間に画素１４０および１５０ごとに接続される。ビニングトランジスタ１２７は、ＭＯＳトランジスタでもよい。ビニングトランジスタ１２７のゲートには、ビニング信号ΦＢＮ１およびΦＢＮ２が画素１４０および１５０ごとに印加される。転送トランジスタ１２２のゲートには、転送信号ΦＴＧ１およびΦＴＧ２が画素１４０および１５０ごとに印加される。リセットトランジスタ１２３のゲートには、画素リセット信号ΦＰＲＴ１およびΦＰＲＴ２が画素１４０および１５０ごとに印加される。選択トランジスタ１２５のゲートには、選択信号ΦＳＥＬ１およびΦＳＥＬ２が画素１４０および１５０ごとに印加される。 A binning transistor 127 is connected between the floating diffusion 126 and the binning line 134 for each pixel 140 and 150. Binning transistor 127 may be a MOS transistor. Binning signals ΦBN1 and ΦBN2 are applied to the gate of the binning transistor 127 for each pixel 140 and 150. Transfer signals ΦTG1 and ΦTG2 are applied to the gate of the transfer transistor 122 for each pixel 140 and 150. Pixel reset signals ΦPRT1 and ΦPRT2 are applied to the gate of the reset transistor 123 for each pixel 140 and 150. Selection signals ΦSEL1 and ΦSEL2 are applied to the gate of the selection transistor 125 for each pixel 140 and 150.
　各画素１４０および１５０から個別に信号を読出す場合、各ビニング信号ΦＢＮ１およびΦＢＮ２はロウレベルに設定され、各画素１４０および１５０のビニングトランジスタ１２７はオフされる。各画素１４０および１５０の信号をビニング読出しする場合、各ビニング信号ΦＢＮ１およびΦＢＮ２はハイレベルに設定され、各画素１４０および１５０のビニングトランジスタ１２７はオンされる。各画素１４０および１５０からの容量負荷読出し動作は、図７と同様である。このとき、ビニング読出しでは、各画素１４０および１５０の選択トランジスタ１２５のいずれか一方をオンさせてもよいし、各画素１４０および１５０の選択トランジスタ１２５の両方をオンさせてもよい。 When reading signals from each pixel 140 and 150 individually, each binning signal ΦBN1 and ΦBN2 is set to low level, and the binning transistor 127 of each pixel 140 and 150 is turned off. When reading the signals of each pixel 140 and 150 by binning, each binning signal ΦBN1 and ΦBN2 is set to a high level, and the binning transistor 127 of each pixel 140 and 150 is turned on. The capacitive load readout operation from each pixel 140 and 150 is similar to that in FIG. At this time, in the binning readout, either one of the selection transistors 125 of each pixel 140 and 150 may be turned on, or both of the selection transistors 125 of each pixel 140 and 150 may be turned on.
　このように、上述の第１０の実施の形態では、垂直信号線１３２に接続された画素１４０および１５０にビニングトランジスタ１２７を設ける。これにより、各フレームの読出し回数を低減させつつ、容量負荷読出しを適用することができ、低消費電力化を図ることができる。 In this manner, in the tenth embodiment described above, the binning transistors 127 are provided in the pixels 140 and 150 connected to the vertical signal line 132. Thereby, capacitive load reading can be applied while reducing the number of times each frame is read, and power consumption can be reduced.
　なお、画素１４０および１５０が設けられた構成について、上述の第２の実施の形態から第９の実施の形態のいずれの構成を適用してもよい。 Note that any of the configurations from the second to ninth embodiments described above may be applied to the configuration in which the pixels 140 and 150 are provided.
　＜１１．第１１の実施の形態＞
　上述の第１の実施の形態では、画素１２０に接続された垂直信号線１３２の電位ＶＳＬに基づいて画素１２０から読み出された信号を検出した。この第１１の実施の形態では、異なるカラムからの負荷容量読出しに基づく垂直信号線の電位の比較結果に基づいてエッジ検出を実施する。 <11. Eleventh embodiment>
In the first embodiment described above, the signal read from the pixel 120 is detected based on the potential VSL of the vertical signal line 132 connected to the pixel 120. In the eleventh embodiment, edge detection is performed based on the comparison result of the potentials of the vertical signal lines based on load capacitance reading from different columns.
　図２１は、第１１の実施の形態に係る２カラム分の信号読出し回路の構成例を示す図である。 FIG. 21 is a diagram showing a configuration example of a signal readout circuit for two columns according to the eleventh embodiment.
　同図において、この信号読出し回路は、複数の垂直信号線１３２－１および１３２－２を備えるとともに、上述の第１の実施の形態のコンパレータ１４３に代えて、コンパレータ１４３－１および１４３－２を備える。第１１の実施の形態の信号読出し回路のそれ以外の構成は、上述の第１の実施の形態の信号読出し回路の構成と同様である。 In the figure, this signal readout circuit includes a plurality of vertical signal lines 132-1 and 132-2, and comparators 143-1 and 143-2 in place of the comparator 143 of the first embodiment described above. Be prepared. The rest of the configuration of the signal readout circuit of the eleventh embodiment is similar to the configuration of the signal readout circuit of the first embodiment described above.
　各垂直信号線１３２－１および１３２－２には、画素１２０－１および１２０－２がそれぞれ接続されるとともに、各コンパレータ１４３－１および１４３－２には、垂直信号線１３２－１および１３２－２が共に接続される。 Pixels 120-1 and 120-2 are connected to each vertical signal line 132-1 and 132-2, respectively, and vertical signal lines 132-1 and 132-2 are connected to each comparator 143-1 and 143-2. 2 are connected together.
　各画素１２０－１および１２０－２は、図６の画素１２０と同様に構成することができる。各画素１２０－１および１２０－２は、垂直信号線１３２－１および１３２－２にそれぞれ接続される。また、各垂直信号線１３２－１および１３２－２には、信号線トランジスタ１４１を介してダイオード接続トランジスタ１４２が接続される。各コンパレータ１４３－１および１４３－２は、各垂直信号線１３２－１および１３２－２の電位ＶＬＳ１およびＶＬＳ２を比較する。そして、各垂直信号線１３２－１および１３２－２の電位ＶＬＳ１およびＶＬＳ２の差分がしきい値以上の場合、エッジ有と判定することができる。 Each pixel 120-1 and 120-2 can be configured similarly to pixel 120 in FIG. 6. Each pixel 120-1 and 120-2 is connected to vertical signal lines 132-1 and 132-2, respectively. Further, a diode-connected transistor 142 is connected to each vertical signal line 132-1 and 132-2 via a signal line transistor 141. Each comparator 143-1 and 143-2 compares potentials VLS1 and VLS2 of each vertical signal line 132-1 and 132-2. Then, if the difference between the potentials VLS1 and VLS2 of each vertical signal line 132-1 and 132-2 is equal to or greater than a threshold value, it can be determined that an edge exists.
　図２２は、第１１の実施の形態に係る撮像装置の信号読出し時の各部の波形の一例を示す図である。 FIG. 22 is a diagram showing an example of waveforms of each part during signal readout of the imaging device according to the eleventh embodiment.
　同図において、容量負荷読出し動作は、図７と同様である。ただし、第１１の実施の形態では、各画素１２０－１および１２０－２からの信号の読出し時に画素電流ＩＰＸ１およびＩＰＸ２が垂直信号線１３２－１および１３２－２にそれぞれ流れる。このとき、各画素電流ＩＰＸ１およびＩＰＸ２に応じた電荷が垂直信号線１３２－１および１３２－２ごとに容量１３３に蓄積される。そして、各垂直信号線１３２－１および１３２－２の容量１３３に蓄積された電荷に応じて各垂直信号線１３２－１および１３２－２の電位ＶＳＬ１およびＶＳＬ２が変化し、各コンパレータ１４３－１および１４３－２に入力される。そして、各コンパレータ１４３－１および１４３－２において、比較信号ＣＯＴが立ち上がると（ｔ１６）、各垂直信号線１３２－１および１３２－２の電位ＶＳＬ１およびＶＳＬ２が比較され、その比較結果が出力される。 In the figure, the capacitive load read operation is the same as in FIG. 7. However, in the eleventh embodiment, pixel currents IPX1 and IPX2 flow through vertical signal lines 132-1 and 132-2, respectively, when reading signals from pixels 120-1 and 120-2. At this time, charges corresponding to each pixel current IPX1 and IPX2 are accumulated in the capacitor 133 for each vertical signal line 132-1 and 132-2. Then, the potentials VSL1 and VSL2 of each vertical signal line 132-1 and 132-2 change according to the charges accumulated in the capacitor 133 of each vertical signal line 132-1 and 132-2, and the potentials VSL1 and VSL2 of each vertical signal line 132-1 and 132-2 change, and 143-2. Then, in each comparator 143-1 and 143-2, when the comparison signal COT rises (t16), the potentials VSL1 and VSL2 of each vertical signal line 132-1 and 132-2 are compared, and the comparison result is output. .
　このように、上述の第１１の実施の形態では、各コンパレータ１４３－１および１４３－２は、負荷容量読出しに基づく各垂直信号線１３２－１および１３２－２の電位ＶＬＳ１およびＶＬＳ２の差分を検出する。これにより、低消費電力化を図りつつ、被写体のエッジを検出することができる。 In this manner, in the eleventh embodiment described above, each comparator 143-1 and 143-2 detects the difference between the potentials VLS1 and VLS2 of each vertical signal line 132-1 and 132-2 based on load capacitance reading. do. This makes it possible to detect edges of a subject while reducing power consumption.
　＜１２．第１２の実施の形態＞
　上述の第１の実施の形態では、画素１２０から読み出された信号を伝送する垂直信号線１３２に電気的に接続された信号線トランジスタ１４１にダイオード接続トランジスタ１４２を接続した。この第１２の実施の形態では、画素１２０がマトリックス状に配列された画素アレイ部が設けられた固体撮像装置が形成される基板を積層化する。 <12. Twelfth embodiment>
In the first embodiment described above, the diode-connected transistor 142 is connected to the signal line transistor 141 that is electrically connected to the vertical signal line 132 that transmits the signal read out from the pixel 120. In the twelfth embodiment, substrates on which a solid-state imaging device including a pixel array section in which pixels 120 are arranged in a matrix are formed are laminated.
　図２３は、第１２の実施の形態に係る撮像装置の構成例を示す斜視図である。 FIG. 23 is a perspective view showing a configuration example of an imaging device according to the twelfth embodiment.
　同図におけるａにおいて、固体撮像装置９０１は、支持基板９１１および半導体基板９１２を備える。半導体基板９１２は、支持基板９１１上に積層されている。半導体基板９１２には、画素アレイ部９１３および周辺回路９１４が形成される。周辺回路９１４には、カラム読出し回路９１５およびカラムＡＤＣ９１６が形成される。カラム読出し回路９１５およびカラムＡＤＣ９１６は、画素アレイ部９１３のカラム方向の両側に形成してもよい。 At a in the figure, the solid-state imaging device 901 includes a support substrate 911 and a semiconductor substrate 912. A semiconductor substrate 912 is stacked on a support substrate 911. A pixel array section 913 and a peripheral circuit 914 are formed on the semiconductor substrate 912. In the peripheral circuit 914, a column readout circuit 915 and a column ADC 916 are formed. The column readout circuit 915 and the column ADC 916 may be formed on both sides of the pixel array section 913 in the column direction.
　画素アレイ部９１３には、ロウ方向およびカラム方向に沿ってマトリックス状に画素１２０が配列される。カラム読出し回路９１５は、容量負荷読出しに基づいて各画素１２０から信号を読出すことができる。カラム読出し回路９１５には、例えば、図６の信号線リセットトランジスタ１４１およびダイオード接続トランジスタ１４２を形成してもよい。カラムＡＤＣ９１６は、カラム読出し回路９１５を介して読み出された信号をカラムごとにＡＤ変換することができる。このとき、固体撮像装置９０１は、裏面照射型イメージセンサを構成することができる。 In the pixel array section 913, pixels 120 are arranged in a matrix along the row and column directions. Column readout circuit 915 can read signals from each pixel 120 based on capacitive load readout. For example, the signal line reset transistor 141 and diode-connected transistor 142 in FIG. 6 may be formed in the column readout circuit 915. The column ADC 916 can AD convert signals read out via the column readout circuit 915 for each column. At this time, the solid-state imaging device 901 can constitute a back-illuminated image sensor.
　同図におけるｂにおいて、固体撮像装置９０２は、半導体基板９２１および９２２を備える。半導体基板９２２は、半導体基板９２１上に積層されている。半導体基板９２２には、画素アレイ部９２３が形成される。半導体基板９２２には、周辺回路９２４が形成される。周辺回路９２４には、カラム読出し回路９２５およびカラムＡＤＣ９２６が形成される。カラム読出し回路９２５およびカラムＡＤＣ９２６は、画素アレイ部９２３のカラム方向の両側の位置に対応するように形成してもよい。このとき、固体撮像装置９０２は、裏面照射型イメージセンサを構成することができる。 In b in the figure, the solid-state imaging device 902 includes semiconductor substrates 921 and 922. A semiconductor substrate 922 is stacked on the semiconductor substrate 921. A pixel array section 923 is formed on the semiconductor substrate 922. A peripheral circuit 924 is formed on the semiconductor substrate 922 . In the peripheral circuit 924, a column readout circuit 925 and a column ADC 926 are formed. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction. At this time, the solid-state imaging device 902 can constitute a back-illuminated image sensor.
　このように、上述の第１２の実施の形態では、各固体撮像装置９０１および９０２が形成される基板をそれぞれ積層化する。これにより、各画素アレイ部９１３および９２３を支持しつつ、各画素アレイ部９１３および９２３がそれぞれ形成される半導体基板９１２および９２２を薄膜化することができ、裏面照射型イメージセンサを形成することができる。 In this manner, in the twelfth embodiment described above, the substrates on which the solid- state imaging devices 901 and 902 are formed are laminated. As a result, while supporting each pixel array section 913 and 923, the semiconductor substrates 912 and 922 on which each pixel array section 913 and 923 are formed can be thinned, and a back-illuminated image sensor can be formed. can.
　＜１３．移動体への応用例＞
　本開示に係る技術（本技術）は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 <13. Example of application to mobile objects>
The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as a car, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, robot, etc. It's okay.
　図２４は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。 FIG. 24 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present disclosure can be applied.
　車両制御システム１２０００は、通信ネットワーク１２００１を介して接続された複数の電子制御ユニットを備える。図２４に示した例では、車両制御システム１２０００は、駆動系制御ユニット１２０１０、ボディ系制御ユニット１２０２０、車外情報検出ユニット１２０３０、車内情報検出ユニット１２０４０、及び統合制御ユニット１２０５０を備える。また、統合制御ユニット１２０５０の機能構成として、マイクロコンピュータ１２０５１、音声画像出力部１２０５２、及び車載ネットワークＩ／Ｆ(interface)１２０５３が図示されている。 The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 24, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. Further, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/image output section 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
　駆動系制御ユニット１２０１０は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット１２０１０は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。 The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 includes a drive force generation device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits the drive force to wheels, and a drive force transmission mechanism that controls the steering angle of the vehicle. It functions as a control device for a steering mechanism to adjust and a braking device to generate braking force for the vehicle.
　ボディ系制御ユニット１２０２０は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット１２０２０は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット１２０２０には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット１２０２０は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。 The body system control unit 12020 controls the operations of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a turn signal, or a fog lamp. In this case, radio waves transmitted from a portable device that replaces a key or signals from various switches may be input to the body control unit 12020. The body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, power window device, lamp, etc. of the vehicle.
　車外情報検出ユニット１２０３０は、車両制御システム１２０００を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット１２０３０には、撮像部１２０３１が接続される。車外情報検出ユニット１２０３０は、撮像部１２０３１に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット１２０３０は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。 The external information detection unit 12030 detects information external to the vehicle in which the vehicle control system 12000 is mounted. For example, an imaging section 12031 is connected to the outside-vehicle information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image. The external information detection unit 12030 may perform object detection processing such as a person, car, obstacle, sign, or text on the road surface or distance detection processing based on the received image.
　撮像部１２０３１は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部１２０３１は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部１２０３１が受光する光は、可視光であってもよいし、赤外線等の非可視光であってもよい。 The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. Furthermore, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
　車内情報検出ユニット１２０４０は、車内の情報を検出する。車内情報検出ユニット１２０４０には、例えば、運転者の状態を検出する運転者状態検出部１２０４１が接続される。運転者状態検出部１２０４１は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット１２０４０は、運転者状態検出部１２０４１から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。 The in-vehicle information detection unit 12040 detects in-vehicle information. For example, a driver condition detection section 12041 that detects the condition of the driver is connected to the in-vehicle information detection unit 12040. The driver condition detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver condition detection unit 12041. It may be calculated, or it may be determined whether the driver is falling asleep.
　マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット１２０１０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むＡＤＡＳ(Advanced Driver Assistance System)の機能実現を目的とした協調制御を行うことができる。 The microcomputer 12051 calculates control target values for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, Control commands can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or shock mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of autonomous driving, etc., which does not rely on operation.
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で取得される車外の情報に基づいて、ボディ系制御ユニット１２０２０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。 Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of preventing glare, such as switching from high beam to low beam. It can be carried out.
　音声画像出力部１２０５２は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図２４の例では、出力装置として、オーディオスピーカ１２０６１、表示部１２０６２及びインストルメントパネル１２０６３が例示されている。表示部１２０６２は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。 The audio and image output unit 12052 transmits an output signal of at least one of audio and images to an output device that can visually or audibly notify information to the occupants of the vehicle or to the outside of the vehicle. In the example of FIG. 24, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
　図２５は、撮像部１２０３１の設置位置の例を示す図である。 FIG. 25 is a diagram showing an example of the installation position of the imaging section 12031.
　図２５では、撮像部１２０３１として、撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５を有する。 In FIG. 25, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
　撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５は、例えば、車両１２１００のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部１２１０１及び車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として車両１２１００の前方の画像を取得する。サイドミラーに備えられる撮像部１２１０２，１２１０３は、主として車両１２１００の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部１２１０４は、主として車両１２１００の後方の画像を取得する。車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。 The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle 12100. An imaging unit 12101 provided in the front nose and an imaging unit 12105 provided above the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. Imaging units 12102 and 12103 provided in the side mirrors mainly capture images of the sides of the vehicle 12100. An imaging unit 12104 provided in the rear bumper or back door mainly captures images of the rear of the vehicle 12100. The imaging unit 12105 provided above the windshield inside the vehicle is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
　なお、図２５には、撮像部１２１０１ないし１２１０４の撮影範囲の一例が示されている。撮像範囲１２１１１は、フロントノーズに設けられた撮像部１２１０１の撮像範囲を示し、撮像範囲１２１１２，１２１１３は、それぞれサイドミラーに設けられた撮像部１２１０２，１２１０３の撮像範囲を示し、撮像範囲１２１１４は、リアバンパ又はバックドアに設けられた撮像部１２１０４の撮像範囲を示す。例えば、撮像部１２１０１ないし１２１０４で撮像された画像データが重ね合わせられることにより、車両１２１００を上方から見た俯瞰画像が得られる。 Note that FIG. 25 shows an example of the imaging range of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 shows the imaging range of the imaging unit 12101 provided on the front nose. The imaging range of the imaging unit 12104 provided in the rear bumper or back door is shown. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、距離情報を取得する機能を有していてもよい。例えば、撮像部１２１０１ないし１２１０４の少なくとも１つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。 At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of image sensors, or may be an image sensor having pixels for phase difference detection.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を基に、撮像範囲１２１１１ないし１２１１４内における各立体物までの距離と、この距離の時間的変化（車両１２１００に対する相対速度）を求めることにより、特に車両１２１００の進行路上にある最も近い立体物で、車両１２１００と略同じ方向に所定の速度（例えば、０ｋｍ／ｈ以上）で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ１２０５１は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御（追従停止制御も含む）や自動加速制御（追従発進制御も含む）等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 For example, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. In particular, by determining the three-dimensional object that is closest to the vehicle 12100 on its path and that is traveling at a predetermined speed (for example, 0 km/h or more) in approximately the same direction as the vehicle 12100, it is possible to extract the three-dimensional object as the preceding vehicle. can. Furthermore, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for the purpose of autonomous driving, etc., in which the vehicle travels autonomously without depending on the driver's operation.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を元に、立体物に関する立体物データを、２輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ１２０５１は、車両１２１００の周辺の障害物を、車両１２１００のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ１２０５１は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ１２０６１や表示部１２０６２を介してドライバに警報を出力することや、駆動系制御ユニット１２０１０を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。 For example, the microcomputer 12051 transfers three-dimensional object data to other three-dimensional objects such as two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, and utility poles based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceeds a set value and there is a possibility of a collision, the microcomputer 12051 transmits information via the audio speaker 12061 and the display unit 12062. By outputting a warning to the driver via the vehicle control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部１２１０１ないし１２１０４の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ１２０５１が、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部１２０５２は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部１２０６２を制御する。また、音声画像出力部１２０５２は、歩行者を示すアイコン等を所望の位置に表示するように表示部１２０６２を制御してもよい。 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition involves, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and a pattern matching process is performed on a series of feature points indicating the outline of an object to determine whether it is a pedestrian or not. This is done through a procedure that determines the When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 creates a rectangular outline for emphasis on the recognized pedestrian. The display unit 12062 is controlled to display the . Furthermore, the audio image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
　以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、撮像部１２０３１に適用され得る。具体的には、例えば、上述のカメラ１００は、撮像部１２０３１に適用することができる。車両制御システム１２０００に本開示に係る技術を適用することにより、消費電力の増大を抑制しつつ、撮影画像を得ることが可能となるとともに、太陽黒点現象を防止することができる。 An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, for example, the above-described camera 100 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to obtain captured images while suppressing an increase in power consumption, and it is also possible to prevent sunspot phenomena.
　なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。また、本明細書に記載された効果はあくまで例示であって、限定されるものではなく、また、他の効果があってもよい。 Note that the above-described embodiments show an example for embodying the present technology, and the matters in the embodiments and the matters specifying the invention in the claims have a corresponding relationship, respectively. Similarly, the matters specifying the invention in the claims and the matters in the embodiments of the present technology having the same names have a corresponding relationship. However, the present technology is not limited to the embodiments, and can be realized by making various modifications to the embodiments without departing from the gist thereof. Further, the effects described in this specification are merely examples and are not limited, and other effects may also be present.
　なお、本技術は以下のような構成もとることができる。
（１）画素からの信号読出し時に流れる電流に応じて蓄積された電荷に基づいて電位が変化する信号線と、
　前記信号線に電気的に接続された信号線トランジスタと、
　前記信号線トランジスタに直列に接続され、０Ｖより高い電圧を生成可能な電圧生成部と
を具備する撮像装置。
（２）前記信号線の電位は、前記信号線の寄生容量の電位である
前記（１）記載の撮像装置。
（３）前記画素は、
　フォトダイオードと、
　前記フォトダイオードに蓄積された電荷をフローティングディフュージョンに転送する転送トランジスタと、
　前記フローティングディフュージョンをリセットするリセットトランジスタと、
　前記フローティングディフュージョンの電位に応じた信号を出力する増幅トランジスタと、
　前記増幅トランジスタと前記信号線との間に接続された選択トランジスタと
を備える前記（１）または（２）に記載の撮像装置。
（４）前記電圧生成部は、ダイオード接続トランジスタを備える
前記（１）から（３）のいずれかに記載の撮像装置。
（５）前記電圧生成部は、直列数が互いに異なる複数のダイオード接続トランジスタを備える
前記（１）から（３）のいずれかに記載の撮像装置。
（６）前記電圧生成部は、前記画素からリセットレベルが読み出される時の前記信号線のリセットレベルを、前記画素から信号レベルが読み出される時の前記信号線のリセットレベル以上とする
前記（１）から（５）のいずれかに記載の撮像装置。
（７）前記信号線の電位とランプ信号とを比較するコンパレータを
さらに具備する前記（１）から（６）のいずれかに記載の撮像装置。
（８）異なるカラムに設けられた信号線の電位を互いに比較するコンパレータを
さらに具備する前記（１）から（７）のいずれかに記載の撮像装置。
（９）前記信号線に電気的に接続可能であり、前記画素との間に形成されるソースフォロワに基づいて定電流を流す定電流トランジスタを
さらに具備する前記（１）から（８）のいずれかに記載の撮像装置。
（１０）前記定電流トランジスタを用いた定電流読出しでは、前記定電流トランジスタはオンされ、
　前記電圧生成部を用いた容量負荷読出しでは、前記定電流トランジスタはオフされる
前記（９）記載の撮像装置。
（１１）前記信号線トランジスタを定電流トランジスタとして動作させるサンプルホールド回路と、
　前記信号線トランジスタの接続先を前記電圧生成部とグランド電位との間で切り替えるスイッチとを
さらに具備する前記（１）から（８）のいずれかに記載の撮像装置。
（１２）定電流読出しでは、前記信号線トランジスタの接続先が前記グランド電位に切り替えられるとともに、前記信号線トランジスタはオンされ、
　容量負荷読出しでは、前記信号線トランジスタの接続先が前記電圧生成部に切り替えられるとともに、前記信号線がリセットされた後に前記信号線トランジスタはオフされる
前記（１１）記載の撮像装置。
（１３）前記電圧生成部は、
　前記信号線トランジスタに直列に接続された直列トランジスタと、
　前記直列トランジスタのゲートとドレインとの間を開閉する開閉トランジスタと
を備える前記（１）から（８）のいずれかに記載の撮像装置。
（１４）定電流読出しでは、前記開閉トランジスタはオフされ、
　容量負荷読出しでは、前記開閉トランジスタはオンされる
前記（１３）記載の撮像装置。
（１５）前記画素が形成されたチップを備え、
　前記信号線トランジスタは前記チップに形成される
前記（１）から（１４）のいずれかに記載の撮像装置。
（１６）前記電圧生成部は前記チップに形成される
前記（１５）記載の撮像装置。
（１７）前記画素がロウ方向およびカラム方向にマトリックス状に配置された画素アレイ部を備え、
　前記信号線は前記カラム方向に配線されるようにして前記ロウ方向に複数設けられ、
　前記信号線トランジスタは、前記信号線のそれぞれに設けられる
前記（１）から（１６）のいずれかに記載の撮像装置。
（１８）前記電圧生成部は、カラムが互いに異なる信号線のそれぞれに設けられる
前記（１７）記載の撮像装置。
（１９）前記電圧生成部は、カラムが互いに異なる複数の信号線で共有される
前記（１７）記載の撮像装置。
（２０）カラムが互いに異なる複数の信号線のそれぞれに設けられた前記電圧生成部を短絡する短絡線を備える
前記（１８）記載の撮像装置。 Note that the present technology can also have the following configuration.
(1) A signal line whose potential changes based on the charge accumulated in accordance with the current flowing when reading signals from the pixel;
a signal line transistor electrically connected to the signal line;
An imaging device comprising: a voltage generation section connected in series to the signal line transistor and capable of generating a voltage higher than 0V.
(2) The imaging device according to (1), wherein the potential of the signal line is a potential of a parasitic capacitance of the signal line.
(3) The pixel is
photodiode and
a transfer transistor that transfers the charge accumulated in the photodiode to a floating diffusion;
a reset transistor that resets the floating diffusion;
an amplification transistor that outputs a signal according to the potential of the floating diffusion;
The imaging device according to (1) or (2), further comprising a selection transistor connected between the amplification transistor and the signal line.
(4) The imaging device according to any one of (1) to (3), wherein the voltage generation section includes a diode-connected transistor.
(5) The imaging device according to any one of (1) to (3), wherein the voltage generation section includes a plurality of diode-connected transistors having different numbers of series connections.
(6) The voltage generation unit sets the reset level of the signal line when the reset level is read from the pixel to be equal to or higher than the reset level of the signal line when the signal level is read from the pixel (1). The imaging device according to any one of (5) to (5).
(7) The imaging device according to any one of (1) to (6), further comprising a comparator that compares the potential of the signal line and a ramp signal.
(8) The imaging device according to any one of (1) to (7), further comprising a comparator that compares potentials of signal lines provided in different columns.
(9) Any one of (1) to (8) above, further comprising a constant current transistor that is electrically connectable to the signal line and that flows a constant current based on a source follower formed between the pixel and the pixel. An imaging device according to claim 1.
(10) In constant current reading using the constant current transistor, the constant current transistor is turned on;
The imaging device according to (9), wherein the constant current transistor is turned off in capacitive load reading using the voltage generation section.
(11) a sample hold circuit that operates the signal line transistor as a constant current transistor;
The imaging device according to any one of (1) to (8), further comprising a switch that switches a connection destination of the signal line transistor between the voltage generation section and a ground potential.
(12) In constant current reading, the connection destination of the signal line transistor is switched to the ground potential, and the signal line transistor is turned on;
The imaging device according to (11), wherein in capacitive load reading, the connection destination of the signal line transistor is switched to the voltage generation section, and the signal line transistor is turned off after the signal line is reset.
(13) The voltage generation section:
a series transistor connected in series to the signal line transistor;
The imaging device according to any one of (1) to (8), including an opening/closing transistor that opens and closes between the gate and drain of the series transistor.
(14) In constant current readout, the switching transistor is turned off,
The imaging device according to (13), wherein the switching transistor is turned on in capacitive load reading.
(15) comprising a chip on which the pixel is formed;
The imaging device according to any one of (1) to (14), wherein the signal line transistor is formed on the chip.
(16) The imaging device according to (15), wherein the voltage generation section is formed on the chip.
(17) comprising a pixel array section in which the pixels are arranged in a matrix in a row direction and a column direction;
A plurality of the signal lines are provided in the row direction so as to be wired in the column direction,
The imaging device according to any one of (1) to (16), wherein the signal line transistor is provided in each of the signal lines.
(18) The imaging device according to (17), wherein the voltage generation section is provided for each of the signal lines having different columns.
(19) The imaging device according to (17), wherein the voltage generation unit has columns that are shared by a plurality of different signal lines.
(20) The imaging device according to (18), further comprising a short-circuit line that short-circuits the voltage generation sections provided in each of a plurality of signal lines having different columns.
　１００　カメラ
　１０１　光学系
　１０２　固体撮像装置
　１０３　撮像制御部
　１０４　画像処理部
　１０５　記憶部
　１０６　表示部
　１０７　操作部
　１０８　バス
　１１１　画素アレイ部
　１１２　垂直走査回路
　１１３　カラム読出し回路
　１１４　カラム信号処理部
　１１５　水平走査回路
　１１６　制御回路
　１２１　フォトダイオード
　１２２　転送トランジスタ
　１２３　リセットトランジスタ
　１２４　増幅トランジスタ
　１２５　選択トランジスタ
　１２６　フローティングディフュージョン
　１３１　水平駆動線
　１３２　垂直信号線
　１３３　容量
　１４１　信号線トランジスタ
　１４２　ダイオード接続トランジスタ
　１４３　コンパレータ
　１４４、１４５　ＤＣカットコンデンサ 100 Camera 101 Optical system 102 Solid-state imaging device 103 Imaging control section 104 Image processing section 105 Storage section 106 Display section 107 Operation section 108 Bus 111 Pixel array section 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing section 115 Horizontal scanning circuit 116 Control circuit 121 Photodiode 122 Transfer transistor 123 Reset transistor 124 Amplification transistor 125 Selection transistor 126 Floating diffusion 131 Horizontal drive line 132 Vertical signal line 133 Capacitor 141 Signal line transistor 142 Diode-connected transistor 143 Comparator 144, 145 DC cut capacitor

Claims (20)

  1. 　画素からの信号読出し時に流れる電流に応じて蓄積された電荷に基づいて電位が変化する信号線と、
    　前記信号線に電気的に接続された信号線トランジスタと、
    　前記信号線トランジスタに直列に接続され、０Ｖより高い電圧を生成可能な電圧生成部と
    を具備する撮像装置。     a signal line whose potential changes based on the charge accumulated in accordance with the current flowing when reading signals from the pixel;
    a signal line transistor electrically connected to the signal line;
    An imaging device comprising: a voltage generation section connected in series to the signal line transistor and capable of generating a voltage higher than 0V.
  2. 　前記信号線の電位は、前記信号線の寄生容量の電位である
    請求項１記載の撮像装置。     The imaging device according to claim 1, wherein the potential of the signal line is a potential of a parasitic capacitance of the signal line.
  3. 　前記画素は、
    　フォトダイオードと、
    　前記フォトダイオードに蓄積された電荷をフローティングディフュージョンに転送する転送トランジスタと、
    　前記フローティングディフュージョンをリセットするリセットトランジスタと、
    　前記フローティングディフュージョンの電位に応じた信号を出力する増幅トランジスタと、
    　前記増幅トランジスタと前記信号線との間に接続された選択トランジスタと
    を備える請求項１記載の撮像装置。     The pixel is
    photodiode and
    a transfer transistor that transfers the charge accumulated in the photodiode to a floating diffusion;
    a reset transistor that resets the floating diffusion;
    an amplification transistor that outputs a signal according to the potential of the floating diffusion;
    The imaging device according to claim 1, further comprising a selection transistor connected between the amplification transistor and the signal line.
  4. 　前記電圧生成部は、ダイオード接続トランジスタを備える
    請求項１記載の撮像装置。     The imaging device according to claim 1, wherein the voltage generation section includes a diode-connected transistor.
  5. 　前記電圧生成部は、直列数が互いに異なる複数のダイオード接続トランジスタを備える
    請求項１記載の撮像装置。     The imaging device according to claim 1, wherein the voltage generation section includes a plurality of diode-connected transistors having different numbers of series connections.
  6. 　前記電圧生成部は、前記画素からリセットレベルが読み出される時の前記信号線のリセットレベルを、前記画素から信号レベルが読み出される時の前記信号線のリセットレベル以上とする
    請求項１記載の撮像装置。     The imaging device according to claim 1, wherein the voltage generation unit sets the reset level of the signal line when the reset level is read from the pixel to be equal to or higher than the reset level of the signal line when the signal level is read from the pixel. .
  7. 　前記信号線の電位とランプ信号とを比較するコンパレータを
    さらに具備する請求項１記載の撮像装置。     The imaging device according to claim 1, further comprising a comparator that compares the potential of the signal line and a ramp signal.
  8. 　異なるカラムに設けられた信号線の電位を互いに比較するコンパレータを
    さらに具備する請求項１記載の撮像装置。     The imaging device according to claim 1, further comprising a comparator that compares the potentials of the signal lines provided in different columns.
  9. 　前記信号線に電気的に接続可能であり、前記画素との間に形成されるソースフォロワに基づいて定電流を流す定電流トランジスタを
    さらに具備する請求項１記載の撮像装置。     The imaging device according to claim 1, further comprising a constant current transistor that is electrically connectable to the signal line and that flows a constant current based on a source follower formed between the pixel and the pixel.
  10. 　前記定電流トランジスタを用いた定電流読出しでは、前記定電流トランジスタはオンされ、
    　前記電圧生成部を用いた容量負荷読出しでは、前記定電流トランジスタはオフされる
    請求項１記載の撮像装置。     In constant current reading using the constant current transistor, the constant current transistor is turned on;
    The imaging device according to claim 1, wherein the constant current transistor is turned off during capacitive load reading using the voltage generating section.
  11. 　前記信号線トランジスタを定電流トランジスタとして動作させるサンプルホールド回路と、
    　前記信号線トランジスタの接続先を前記電圧生成部とグランド電位との間で切り替えるスイッチとを
    さらに具備する請求項１記載の撮像装置。     a sample hold circuit that operates the signal line transistor as a constant current transistor;
    The imaging device according to claim 1, further comprising a switch that switches a connection destination of the signal line transistor between the voltage generation section and a ground potential.
  12. 　定電流読出しでは、前記信号線トランジスタの接続先が前記グランド電位に切り替えられるとともに、前記信号線トランジスタはオンされ、
    　容量負荷読出しでは、前記信号線トランジスタの接続先が前記電圧生成部に切り替えられるとともに、前記信号線がリセットされた後に前記信号線トランジスタはオフされる
    請求項１１記載の撮像装置。     In constant current reading, the connection destination of the signal line transistor is switched to the ground potential, and the signal line transistor is turned on,
    12. The imaging device according to claim 11, wherein in capacitive load reading, the connection destination of the signal line transistor is switched to the voltage generation section, and the signal line transistor is turned off after the signal line is reset.
  13. 　前記電圧生成部は、
    　前記信号線トランジスタに直列に接続された直列トランジスタと、
    　前記直列トランジスタのゲートとドレインとの間を開閉する開閉トランジスタと
    を備える請求項１記載の撮像装置。     The voltage generation section is
    a series transistor connected in series to the signal line transistor;
    The imaging device according to claim 1, further comprising an opening/closing transistor that opens and closes between the gate and drain of the series transistor.
  14. 　定電流読出しでは、前記開閉トランジスタはオフされ、
    　容量負荷読出しでは、前記開閉トランジスタはオンされる
    請求項１３記載の撮像装置。     For constant current readout, the switching transistor is turned off;
    14. The imaging device according to claim 13, wherein the switching transistor is turned on during capacitive load reading.
  15. 　前記画素が形成されたチップを備え、
    　前記信号線トランジスタは前記チップに形成される
    請求項１記載の撮像装置。     comprising a chip on which the pixel is formed,
    The imaging device according to claim 1, wherein the signal line transistor is formed on the chip.
  16. 　前記電圧生成部は前記チップに形成される
    請求項１５記載の撮像装置。     The imaging device according to claim 15, wherein the voltage generation section is formed on the chip.
  17. 　前記画素がロウ方向およびカラム方向にマトリックス状に配置された画素アレイ部を備え、
    　前記信号線は前記カラム方向に配線されるようにして前記ロウ方向に複数設けられ、
    　前記信号線トランジスタは、前記信号線のそれぞれに設けられる
    請求項１記載の撮像装置。     comprising a pixel array section in which the pixels are arranged in a matrix in a row direction and a column direction,
    A plurality of the signal lines are provided in the row direction so as to be wired in the column direction,
    The imaging device according to claim 1, wherein the signal line transistor is provided for each of the signal lines.
  18. 　前記電圧生成部は、カラムが互いに異なる信号線のそれぞれに設けられる
    請求項１７記載の撮像装置。     The imaging device according to claim 17, wherein the voltage generation section is provided for each of the signal lines having different columns.
  19. 　前記電圧生成部は、カラムが互いに異なる複数の信号線で共有される
    請求項１７記載の撮像装置。     The imaging device according to claim 17, wherein the voltage generation section is shared by a plurality of signal lines having different columns.
  20. 　カラムが互いに異なる複数の信号線のそれぞれに設けられた前記電圧生成部を短絡する短絡線を備える
    請求項１８記載の撮像装置。     19. The imaging device according to claim 18, wherein each column includes a shorting line that shorts the voltage generating sections provided in each of the plurality of signal lines having different columns.
PCT/JP2023/024422 2022-08-25 2023-06-30 Imaging device WO2024042862A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022134126 2022-08-25
JP2022-134126 2022-08-25

Publications (1)

Publication Number Publication Date
WO2024042862A1 true WO2024042862A1 (en) 2024-02-29

Family

ID=90012860

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/024422 WO2024042862A1 (en) 2022-08-25 2023-06-30 Imaging device

Country Status (1)

Country Link
WO (1) WO2024042862A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011210837A (en) * 2010-03-29 2011-10-20 Sony Corp Solid-state image pickup element and image pickup apparatus
WO2020262629A1 (en) * 2019-06-26 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Imaging device
JP2021048588A (en) * 2020-10-28 2021-03-25 パナソニックＩｐマネジメント株式会社 Voltage supply circuit
JP2021193760A (en) * 2018-09-26 2021-12-23 ソニーセミコンダクタソリューションズ株式会社 Image sensor and photodetector
JP2022017676A (en) * 2020-07-14 2022-01-26 ソニーセミコンダクタソリューションズ株式会社 Imaging device and electronic apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011210837A (en) * 2010-03-29 2011-10-20 Sony Corp Solid-state image pickup element and image pickup apparatus
JP2021193760A (en) * 2018-09-26 2021-12-23 ソニーセミコンダクタソリューションズ株式会社 Image sensor and photodetector
WO2020262629A1 (en) * 2019-06-26 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Imaging device
JP2022017676A (en) * 2020-07-14 2022-01-26 ソニーセミコンダクタソリューションズ株式会社 Imaging device and electronic apparatus
JP2021048588A (en) * 2020-10-28 2021-03-25 パナソニックＩｐマネジメント株式会社 Voltage supply circuit

Similar Documents

Publication Publication Date Title
US11418749B2 (en) Solid-state image pick-up device and electronic device
CN111615824B (en) Imaging device and electronic apparatus
CN111164965A (en) Solid-state imaging device and electronic apparatus
US20220038648A1 (en) Solid-state imaging device and electronic device
US20220052088A1 (en) Solid-state imaging device and electronic apparatus
WO2022024574A1 (en) Solid-state imaging device and control method therefor
WO2020129657A1 (en) Sensor and control method
WO2020085085A1 (en) Solid-state imaging device
US11381764B2 (en) Sensor element and electronic device
US11917317B2 (en) Solid-state imaging element and imaging device that detects address event
WO2024042862A1 (en) Imaging device
US20230326940A1 (en) Imaging device and electronic apparatus
WO2022009573A1 (en) Imaging device and imaging method
WO2024042863A1 (en) Imaging device
WO2024042864A1 (en) Imaging device
US11477402B2 (en) Solid-state image sensor with improved dark current removal
KR20230108730A (en) Imaging devices and electronic devices
JPWO2020012943A1 (en) Comparator and imaging device
US11438534B2 (en) Solid-state imaging device and electronic apparatus
WO2023100547A1 (en) Imaging device and electronic apparatus
WO2023026576A1 (en) Imaging device and electronic apparatus
WO2024042946A1 (en) Photodetector element
WO2024075399A1 (en) Imaging device
WO2022254832A1 (en) Image capturing apparatus, electronic device, and image capturing method
US20240080587A1 (en) Solid-state imaging device and electronic instrument

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23856979

Country of ref document: EP

Kind code of ref document: A1