WO2024040752A1 - 阵列基板、显示面板及阵列基板的制备方法 - Google Patents

阵列基板、显示面板及阵列基板的制备方法 Download PDF

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Publication number
WO2024040752A1
WO2024040752A1 PCT/CN2022/130720 CN2022130720W WO2024040752A1 WO 2024040752 A1 WO2024040752 A1 WO 2024040752A1 CN 2022130720 W CN2022130720 W CN 2022130720W WO 2024040752 A1 WO2024040752 A1 WO 2024040752A1
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Prior art keywords
layer
sub
insulating
insulating layer
substrate
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PCT/CN2022/130720
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English (en)
French (fr)
Inventor
詹皇泰
李阳
彭兆基
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Kunshan Govisionox Optoelectronics Co Ltd
Hefei Visionox Technology Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
Hefei Visionox Technology Co Ltd
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Priority to KR1020257001197A priority Critical patent/KR102944204B1/ko
Publication of WO2024040752A1 publication Critical patent/WO2024040752A1/zh
Priority to US19/008,677 priority patent/US20250142961A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present application relates to the field of display, and specifically to an array substrate, a display panel and a method for preparing the array substrate.
  • the display panel includes light-emitting devices and driving devices.
  • the driving devices include thin film transistors and capacitor plates and other components that require two layers of wires to overlap at specific positions. In these components, if the overlapping position of the double-layer wires is inaccurate, the device The characteristics are unstable and affect the yield of the display panel.
  • Embodiments of the present application provide an array substrate, a display panel and a method for preparing the array substrate, aiming to provide an array substrate with stable device characteristics.
  • An embodiment of the first aspect of the present application provides an array substrate, including: a substrate; a first insulating layer located on one side of the substrate, and a surface of the first insulating layer facing away from the substrate is recessed to form a limiting groove; a first metal layer , located on the side of the first insulating layer facing away from the substrate, the first metal layer includes a signal line, the signal line includes a first portion and a second portion surrounding at least part of the first portion, the first portion is located in the limiting groove , at least part of the second portion is located on the surface of the first insulating layer facing away from the substrate; the second insulating layer is located on the side of the first metal layer facing away from the substrate, and the second insulating layer includes a receiving groove with an opening facing the first metal layer, The second part is located in the receiving tank.
  • a second embodiment of the present application provides a display panel, which includes the array substrate of any of the above embodiments.
  • An embodiment of the third aspect of the present application provides a method for preparing an array substrate, including:
  • a first insulating material layer is provided on the substrate, and the first insulating material layer is patterned to form a first insulating layer including a limiting groove, and the limiting groove is formed by a surface depression of the first insulating layer facing away from the substrate;
  • a first metal material layer is disposed on a side of the first insulating layer facing away from the substrate.
  • the first metal material layer is patterned using a wet etching process to form a first metal layer including a signal line.
  • the signal line includes a first subsection. and a second portion surrounding at least part of the first portion, the first portion is located in the limiting groove, and at least part of the second portion is located on a surface of the first insulating layer facing away from the substrate;
  • An insulating material is provided on a side of the first metal layer facing away from the first insulating layer to form a second insulating layer. At least part of the insulating material is deposited on the second part to form a receiving groove that opens toward the first metal layer and accommodates the second part. .
  • the array substrate includes a substrate, a first insulating layer, a first metal layer and a second insulating layer.
  • a limiting groove is provided on the first insulating layer, and at least part of the signal lines is located in the limiting groove.
  • the signal line includes a first portion located inside the limiting groove and a second portion located outside the limiting groove.
  • the receiving groove on the second insulating layer accommodates the second portion.
  • the second insulating layer can be directly deposited on the first insulating layer. layer and the first metal layer, which can simplify the preparation of the array substrate.
  • the limit groove can provide a limit to the signal line, thereby determining the position and size of the signal line.
  • the array substrate provided by the embodiment of the present application has the advantage of stable device characteristics.
  • Figure 1 is a partial cross-sectional view of an array substrate provided by the first embodiment of the present application
  • Figure 2 is a partial cross-sectional view of an array substrate provided by another embodiment of the first aspect of the present application.
  • Figure 3 is a partial cross-sectional view of an array substrate provided by yet another embodiment of the first aspect of the present application.
  • Figure 4 is a partial cross-sectional view of an array substrate provided by yet another embodiment of the first aspect of the present application.
  • Figure 5 is a partial cross-sectional view of an array substrate provided by yet another embodiment of the first aspect of the present application.
  • Figure 6 is a partial cross-sectional view of an array substrate provided by yet another embodiment of the first aspect of the present application.
  • Figure 7 is a partial cross-sectional view of an array substrate provided by yet another embodiment of the first aspect of the present application.
  • Figure 8 is a partial cross-sectional view of an array substrate provided by yet another embodiment of the first aspect of the present application.
  • Figure 9 is a top view of a partial layer structure of an array substrate provided by the first embodiment of the present application.
  • Figure 10 is a top view of a partial layer structure of an array substrate provided by another embodiment of the first aspect of the present application.
  • Figure 11 is a top view of a partial layer structure of an array substrate provided by yet another embodiment of the first aspect of the present application.
  • Figure 12 is a partial cross-sectional view of a display panel provided by the second embodiment of the present application.
  • Figure 13 is a schematic flow chart of a method for preparing an array substrate provided by the third embodiment of the present application.
  • Figure 14 is a schematic flowchart of a certain step in a method for preparing an array substrate provided by the third embodiment of the present application;
  • FIG. 15 is a schematic flowchart of another step in a method for preparing an array substrate provided by the third embodiment of the present application.
  • Display panel 10. Array substrate; 20. Pixel electrode layer; 21. Pixel electrode; 30. Pixel definition layer; 31. Isolation part; 32. Pixel opening; 40. Light-emitting unit; 50. Common electrode layer;
  • First insulating layer 301. Limiting groove; 310. First sub-insulating layer; 320. Second sub-insulating layer; 321. Insulating definition part; 330. Insulating stop layer; 331. Etching stop part; 30. Pixel definition layer; 31. Isolation part; 32. Pixel opening;
  • First metal layer 410. Signal line; 411. First sub-layer; 412. Second sub-layer; 413. First division; 414. Second division; 414a, relief groove; 414b, relief hole; 40. Light-emitting unit;
  • Second metal layer 500.
  • Source electrode 520. Drain electrode
  • First sub-section 502.
  • Common electrode layer 501.
  • the embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing the array substrate.
  • Each embodiment of the display panel and display device will be described below with reference to the accompanying drawings.
  • An embodiment of the present application provides an array substrate for use in a display panel.
  • the display panel may be an organic light emitting diode (OLED) display panel.
  • OLED organic light emitting diode
  • FIG. 1 is a partial cross-sectional view of an array substrate 10 provided by the first embodiment of the present application.
  • the array substrate 10 provided by the first embodiment of the present application includes: a substrate 100 and a first insulating layer 300 , a first metal layer 400 and a second insulating layer 600 provided on the substrate 100 .
  • An insulating layer 300 is located on one side of the substrate 100, and the surface of the first insulating layer 300 facing away from the substrate 100 is recessed to form a limiting groove 301; the first metal layer 400 is located on the side of the first insulating layer 300 facing away from the substrate 100.
  • a metal layer 400 includes a signal line 410.
  • the signal line 410 includes a first portion 413 and a second portion 414 surrounding at least part of the first portion 413.
  • the first portion 413 is located in the limiting groove 301 and at least part of the second portion 414.
  • the portion 414 is located on the surface of the first insulating layer 300 facing away from the substrate 100; the second insulating layer 600 is located on the side of the first metal layer 400 facing away from the substrate 100, and the second insulating layer 600 includes a receiving groove that opens toward the first metal layer 400. (Not shown in the figure), the second portion 414 is located in the receiving groove.
  • the array substrate 10 includes a substrate 100, a first insulating layer 300, a first metal layer 400 and a second insulating layer 600.
  • a limiting groove 301 is provided on the first insulating layer 300 , and at least part of the signal line 410 is located in the limiting groove 301 .
  • the signal line 410 includes a first branch 413 located in the limiting groove 301 and a second branch 414 located outside the limiting groove 301.
  • the receiving groove on the second insulating layer 600 accommodates the second branch 414.
  • the second insulating layer 600 can be directly deposited on the first insulating layer 300 and the first metal layer 400, which can simplify the preparation of the array substrate 10.
  • the limiting groove 301 can provide a limiting position for the signal line 410, thereby determining the position and size of the signal line 410. Therefore, a relatively mature process such as wet etching can be used to prepare the signal line 410, which can simplify the preparation of the array substrate 10.
  • the distance between the first subsection 413 located in the limiting groove 301 and other conductors is relatively close, so the size of the overlapping area between the first subsection 413 and other conductors is It can affect the device characteristics.
  • the size and position of the limiting groove 301 the device characteristics can be controlled and the stability of the device characteristics can be improved. Therefore, the array substrate 10 provided by the embodiment of the present application has the advantage of stable device characteristics.
  • the signal line 410 can be arranged in various ways.
  • the signal line 410 can be located in the frame area, and the signal line 410 includes a scan driving circuit.
  • the signal line 410 is one of the plates of the capacitor in the array substrate.
  • the array substrate 10 further includes an active layer 200 disposed on the substrate 100; the active layer 200 is located between the substrate 100 and the first insulating layer 300, and the active layer 200 includes a semiconductor portion 210.
  • the orthographic projection of the bit slot 301 on the substrate 100 and the orthographic projection of the semiconductor portion 210 on the substrate 100 are at least partially overlapped, and the signal line 410 is a gate line.
  • the semiconductor part 210 and the signal line 410 constitute a part of the thin film transistor of the driving circuit of the array substrate 10 .
  • the distance between the first subsection 413 of the signal line 410 and the semiconductor part 210 located in the limiting groove 301 is relatively close. Therefore, the aspect ratio of the overlapping region of the first subsection 413 and the semiconductor part 210 can affect the performance of the thin film transistor.
  • Device characteristics, by reasonably setting the size and position of the limiting groove 301 the characteristics of the thin film transistor can be controlled and the characteristic stability of the thin film transistor can be improved. Therefore, the array substrate 10 provided by the embodiment of the present application has the advantage of stable device characteristics.
  • the substrate 100 is a rigid substrate 100, and the material of the substrate 100 includes rigid materials such as glass.
  • the substrate 100 is a flexible substrate 100, and the material of the substrate 100 includes flexible materials such as polyimide.
  • the array substrate 10 may also include a support layer located on the side of the substrate 100 facing away from the active layer 200 , and the support layer may include a steel plate layer and/or a foam layer.
  • a layer structure such as a buffer layer may also be provided between the substrate 100 and the active layer 200 .
  • a shielding part 110 may also be provided in the substrate 100. The shielding part 110 is used to shield light, so as to improve the impact of light incident on the semiconductor part 210 on the device characteristics of the thin film transistor.
  • the active layer 200 includes a plurality of semiconductor portions 210 distributed at intervals, and each semiconductor portion 210 belongs to a different thin film transistor.
  • the active layer 200 includes a plurality of limiting grooves 301 , and each limiting groove 301 is provided corresponding to each semiconductor part 210 , that is, the orthographic projection of each limiting groove 301 on the substrate 100 is consistent with the orthographic projection of each semiconductor part 210 on the substrate 100 .
  • Orthographic projections are set up with at least partial overlap.
  • There are also multiple signal lines 410 and the first branch 413 of each signal line 410 is located in each limiting slot 301 .
  • the limiting groove 301 is a groove formed by a depression on the surface of the first insulating layer 300 . Therefore, part of the material of the first insulating layer 300 remains between the bottom of the limiting groove 301 and the semiconductor part 210 . That is to say, the limiting groove 301 is not provided through the first insulating layer 300 , and there is insulating material between the bottom wall surface of the limiting groove 301 and the semiconductor part 210 to prevent the signal line 410 and the semiconductor part 210 from short-circuiting.
  • the semiconductor part 210 includes a source region 211, a channel region 213 and a drain region 212 sequentially arranged along the first direction, the orthographic projection of the limiting groove 301 on the substrate 100 and the channel region 213 on the substrate 100.
  • the orthographic projections of are at least partially coincident.
  • the array substrate 10 also includes a second metal layer 500.
  • the second metal layer 500 includes a source electrode 510 and a drain electrode 520.
  • the source electrode 510 is connected to the source region 211 through a via hole
  • the drain region 212 is connected to the drain electrode 520 through a hole.
  • the source electrode 510, the drain electrode 520, the signal line 410 and the semiconductor portion 210 are combined to form a thin film transistor.
  • the distance between the signal line 410 and the channel region 213 located in the limiting groove 301 is relatively close. Therefore, the overlapping area of the signal line 410 and the channel region 213 located in the limiting groove 301 determines the device characteristics of the thin film transistor.
  • the device characteristics of the thin film transistor can be adjusted by reasonably setting the position and size of the limiting groove 301 .
  • the second insulating layer 600 is located between the first metal layer 400 and the second metal layer 500 to prevent the first metal layer 400 and the second metal layer 500 from short-circuit connection.
  • other metal layers may be disposed between the first metal layer 400 and the second metal layer 500 .
  • the via hole connection between the source electrode 510 and the source region 211 means that a via hole is provided on the insulating material layer (including the first insulating layer 300) between the second metal layer 500 and the semiconductor part 210.
  • the metal material It will fall into the via hole and connect to the semiconductor part 210, so that the source electrode 510 is connected to the source region 211 through the via hole, and the drain electrode 520 is connected to the drain region 212 through the via hole.
  • the array substrate 10 also includes a plurality of conductive lines.
  • the conductive lines of the array substrate 10 include data lines, scan lines, power lines, voltage reference lines, etc.
  • the signal lines 410 can be connected to the scan lines.
  • the scan line and the signal line 410 are set on the same layer.
  • the signal line 410 can be considered as a partial segment on the conductive line in the first metal layer 400 that overlaps the channel region 213 , and the scan line can be a partial segment on the signal line in the first metal layer 400 that is misaligned with the channel region 213 . part.
  • One of the source electrode 510 and the drain electrode 520 is connected to a data line.
  • the data line is arranged in the same layer as the source electrode 510 and the drain electrode 520 and is located in the second metal layer 500 .
  • the source electrode 510 can be considered as a portion of the second metal layer 500 where the signal line is connected to the source region 211 via a via hole
  • the drain electrode 520 can be considered as a portion of the second metal layer 500 where the signal line is connected to the drain region 212 via a via hole.
  • the orthographic projection of the channel region 213 on the substrate 100 is located within the orthographic projection of the limiting groove 301 on the substrate 100 .
  • the overlapping area of the channel region 213 and the signal line 410 in the limiting groove 301 can be ensured, thereby ensuring the advancement characteristics of the thin film transistor.
  • the orthographic projection of the limiting groove 301 on the substrate 100 can be the orthographic projection of the opening or the bottom of the limiting groove 301 on the substrate 100 , or can be any point between the opening and the bottom of the limiting groove 301 . The orthographic projection of the position on the substrate 100.
  • the first insulating layer 300 can be arranged in a variety of ways. For example, as shown in FIG. 1 , the first insulating layer 300 can be arranged in a one-layer structure. The first insulating layer 300 is formed by patterning the first insulating layer 300 . The limiting groove 301 is concave on the surface.
  • the first insulating layer 300 includes: a first sub-insulating layer 310 and a second sub-insulating layer 320 .
  • the first sub-insulating layer 310 is located on the side of the active layer 200 away from the substrate 100 ; the second sub-insulating layer
  • the layer 320 is located on the side of the first sub-insulating layer 310 away from the active layer 200 , and the limiting groove 301 is provided in the second sub-insulating layer 320 .
  • the first insulating layer 300 includes a first sub-insulating layer 310 and a second sub-insulating layer 320, and the limiting groove 301 is provided in the second sub-insulating layer 320, that is, the limiting groove 301 is located in the second sub-insulating layer 320.
  • the distance between the bottom wall surface of the limiting groove 301 and the semiconductor part 210 can be adjusted by controlling the thickness of the first sub-insulating layer 310.
  • the limiting groove 301 is provided in the second sub-insulating layer 320.
  • the limiting groove 301 can be obtained by patterning only the second sub-insulating layer 320, which can also reduce the risk of the limiting groove 301 penetrating the entire first insulating layer 300. .
  • the first sub-insulating layer 310 is provided on the entire surface.
  • the first sub-insulating layer 310 is continuously provided at least in the display area of the display panel, which can improve the insulation performance between the first metal layer 400 and the active layer 200 .
  • the second sub-insulating layer 320 is provided on the entire surface.
  • the second sub-insulating layer 320 is continuously provided in at least the display area of the display panel, and the second sub-insulating layer 320 is patterned to form a plurality of limiting grooves 301 .
  • FIG. 3 is a partial cross-sectional view of an array substrate 10 provided by yet another embodiment of the first aspect of the present application.
  • the second sub-insulating layer 320 includes an insulating definition. portion 321 , the insulating defining portion 321 is located between the source electrode 510 and the drain electrode 520 , and the orthographic projection of the signal line 410 on the substrate 100 is located within the orthographic projection of the insulating defining portion 321 on the substrate 100 .
  • the second sub-insulation layer 320 includes an insulation definition portion 321 independently provided corresponding to the signal line 410 and the limiting groove 301, which can reduce the film layer between two adjacent insulation definition portions 321. Thickness, that is, the thickness of the film layer in areas other than the area where the insulating definition portion 321 is located can be reduced, making the display panel lighter and thinner.
  • the first sub-insulating layer 310 is an inter-gate insulating layer, and the material of the first sub-insulating layer 310 includes silicon dioxide.
  • the second sub-insulating layer 320 can be made of various materials.
  • the material of the second sub-insulating layer 320 includes at least one of silicon nitride and silicon oxide.
  • photolithography may be used to pattern the second sub-insulating layer 320 to form the limiting groove 301.
  • photoresist can be disposed on the surface of the second sub-insulating layer 320, and exposed, developed, and etched to form the limiting groove 301.
  • the thickness of the second sub-insulating layer 320 is That is, the depth of the limiting groove 301 is When the depth of the limiting groove 301 is within the above range, it can improve the situation that the distance between the signal line 410 located in the limiting groove 301 and the signal line 410 located outside the limiting groove 301 is too small, resulting in the problem that the signal line 410 located in the limiting groove 301 is too small.
  • the overlap of the outer signal line 410 and the channel region 213 will affect the device characteristics of the thin film transistor, and can also improve the excessive distance between the signal line 410 located in the limiting groove 301 and the signal line 410 located outside the limiting groove 301 , causing the signal line 410 to break at the side wall of the limiting groove 301, affecting the conductive performance of the signal line 410.
  • FIG. 4 is a partial cross-sectional view of an array substrate 10 provided by yet another embodiment of the first aspect of the present application.
  • the first insulating layer 300 further includes an insulating stop layer 330 located between the first sub-insulating layer 310 and the second sub-insulating layer 320 .
  • the second sub-insulating layer 320 can be patterned.
  • the distance between the bottom wall surface of the limiting groove 301 and the semiconductor part 210 can be ensured.
  • the insulating stop layer 330 can be arranged on the entire surface to better improve the corrosiveness of the etching liquid during the etching process of the second sub-insulating layer 320. The influence of materials on the first sub-insulating layer 310.
  • FIG. 5 is a partial cross-sectional view of an array substrate 10 provided by yet another embodiment of the first aspect of the present application.
  • FIG. 6 is a partial cross-sectional view of an array substrate 10 provided by yet another embodiment of the first aspect of the present application.
  • the difference between Figure 5 and Figure 6 lies in the arrangement of the second sub-insulating layer 320.
  • the insulating stop layer 330 may also include an etching stop part 331 , the etching stop part 331 is located between the source electrode 510 and the drain electrode 520 and limits The orthographic projection of the bit trench 301 on the substrate 100 is located within the orthographic projection of the etching stop 331 on the substrate 100 .
  • the limiting groove 301 is located on the etching stopper 331, and the etching stopper 331 can improve the impact on the first sub-insulating layer 310 when the limiting groove 301 is formed due to etching. Moreover, the corresponding arrangement of the etching stopper 331 and the limiting groove 301 can reduce the film thickness in areas other than the area where the etching stopper 331 is located, making the display panel lighter and thinner.
  • the second sub-insulating layer 320 can be disposed over the entire surface to save material and reduce etching on the array substrate 10 .
  • the second sub-insulating layer 320 can also be provided over a non-entire surface and includes an insulating definition portion 321 to further save material. And reduce the thickness of the area on the array substrate 10 except for the etching stopper 331 and the insulation definition portion 321 .
  • the material of the insulating stop layer 330 includes at least one of amorphous silicon and silicon oxide, so that the second sub-insulating layer 320 is etched. , the impact of the etching liquid on the insulating stop layer 330 can be reduced.
  • the thickness of the insulating stop layer 330 is When the thickness of the insulating stop layer 330 is within the above range, it can not only improve the erroneous etching of the first sub-insulating layer 310 caused by insufficient protection of the insulating stop layer 330 due to the too small thickness of the insulating stop layer 330, It can also improve the excessive thickness of the film layer of the display panel caused by the excessive thickness of the insulating stop layer 330 .
  • the materials of the insulating stop layer 330 and the second sub-insulating layer 320 are different or the material ratios are different, so that the problem of the insulating stop layer 330 being etched during the etching process can be improved.
  • the material hardness of the insulating stop layer 330 is greater than the material hardness of the second sub-insulating layer 320 , thereby improving the problem of the insulating stop layer 330 being etched.
  • the signal line 410 is, for example, a single metal layer, and at least part of the metal material layer is located in the limiting groove 301 .
  • the material of the signal line 410 includes metal materials such as aluminum and aluminum alloy.
  • the signal line 410 includes a first sub-layer 411 and a second sub-layer 412 .
  • the first sub-layer 411 is located on a side of the first insulating layer 300 away from the active layer 200 . side; the second sub-layer 412 is located on the side of the first sub-layer 411 away from the first insulating layer 300, and the material of the second sub-layer 412 includes copper.
  • the signal line 410 includes two structural layers, that is, the signal line 410 includes a first sub-layer 411 and a second sub-layer 412.
  • the material of the second sub-layer 412 includes copper.
  • Copper material has the advantages of low impedance and good electrical conductivity, so that the signal line 410 has good electrical conductivity.
  • the first subsection 413 is located in the limiting groove 301, and the overlapping area of the first subsection 413 and the channel region 213 determines the device characteristics of the thin film transistor. Therefore, even if The size of the signal line 410 is relatively large, and the larger size of the signal line 410 is provided outside the limiting groove 301, which will not affect the device characteristics. That is to say, the size of the signal line 410 in the embodiment of the present application is not limited.
  • the second sub-layer 412 can be patterned using a wet etching method, which can improve Since the line width of the signal line 410 is too small, the wet etching method cannot be used to pattern the second sub-layer 412 .
  • the scan line and the signal line 410 are arranged in the same layer of copper material, that is, the scan line may also include two structural layers, and the two structural layers of the scan line are in contact with the signal line 410
  • the first sub-layer 411 and the second sub-layer 412 are arranged in the same layer and with the same material.
  • the material of the first sub-layer 411 may include at least one of molybdenum, molybdenum alloy, titanium and titanium alloy.
  • the thickness of the first sub-layer 411 may be any thickness of the first sub-layer 411.
  • the thickness of the second sub-layer 412 may be greater than or equal to
  • the thickness of the second sub-layer 412 is So that the second sub-layer 412 has good conductive properties.
  • the source electrode 510 and the drain electrode 520 are many ways to arrange the source electrode 510 and the drain electrode 520, as shown in Figures 1 to 6.
  • via holes can be opened on the first insulating layer 300 between the second metal layer 500 and the active layer 200.
  • the metal material falls into the via hole so that the source electrode 510 is connected to the source region 211 through the hole, and the drain electrode 520 is connected to the drain region 212 through the hole.
  • the source electrode 510 and the drain electrode 520 can also be formed in sections.
  • at least one of the source electrode 510 and the drain electrode 520 includes a first sub-section 501 and a second sub-section 502 , the first sub-section 501 is located in the first metal layer 400 , and the first sub-section 501 It is connected to the source region 211 and/or the drain region 212 via vias, and the first sub-segment 501 and the signal line 410 are made of the same material; the second sub-segment 502 is located in the second metal layer 500, and the second sub-segment 502 and the first sub-segment 501 via connection.
  • the source electrode 510 and/or the drain electrode 520 includes a first sub-section 501 and a second sub-section 502. Preparing the source electrode 510 and/or the drain electrode 520 in sections can ensure that the source electrode 510 and/or the drain electrode 520 are segmented. /or the electrical conductivity of drain 520 .
  • both the source electrode 510 and the drain electrode 520 include a first sub-section 501 and a second sub-section 502, which can simultaneously improve the conductive properties of the source electrode 510 and the drain electrode 520 and ensure that the conductive properties of the source electrode 510 and the drain electrode 520 are close to each other. .
  • the first sub-section 501 when the signal line 410 includes the first sub-layer 411 and the second sub-layer 412, the first sub-section 501 also includes the first sub-layer 411 and the second sub-layer 412, and the material of the first sub-section 501 includes copper.
  • the material can improve the conductive performance of the first sub-segment 501.
  • the signal line 410 can be arranged in various shapes.
  • the signal line 410 is completely located in the limiting groove 301 .
  • Figure 8 is a cross-sectional view of an array substrate 10 provided by the first embodiment of the present application.
  • Figure 9 is a top view of a partial layer structure of an array substrate 10 provided by an embodiment of the present application. In order to To better illustrate the layer structure, FIG. 9 only shows the relative positional relationship between the semiconductor part 210, the source electrode 510, the drain electrode 520 and the signal line 410.
  • the extension size of the channel region 213 in the second direction Y is smaller than the extension size of the limiting groove 301 in the second direction Y.
  • the extension size of the limiting groove 301 in the second direction Y is relatively large, which can ensure the overlapping area of the limiting groove 301 and the channel region 213 and improve the device characteristics of the thin film transistor.
  • the second sub-part 414 can be located at any position in the circumferential direction of the first sub-part 413, as long as the second sub-part 414 and the first sub-part 413 are connected to each other.
  • the second subsection 414 is located on at least one side of the first subsection 413 in the second direction, and the second direction intersects the first direction.
  • the second direction may be the extension direction of the scan line, and the second subsection 414 is located on one side of the first subsection 413 in the second direction, so that the first subsection 413 can pass through the second subsection 414 and scan. lines are connected to each other.
  • the second subsection 414 is located on at least one side of the first subsection 413 in the first direction, and the second subsection 414 is in contact with the source electrode 510 and the drain electrode 520 Insulated from each other.
  • the first direction is the width direction of the scan line and signal line 410
  • the second subsection 414 is located on at least one side of the first subsection 413 in the first direction, which can increase the width of the signal line 410 and increase the width of the signal line 410.
  • the distribution area of the signal line 410 further reduces the resistance of the signal line 410.
  • the second sub-part 414 is insulated from the source electrode 510 and the drain electrode 520.
  • the second sub-part 414 is provided with an escape groove 414a.
  • the through hole is located in the avoidance groove 414a , so that the source electrode 510 and the drain electrode 520 are insulated from each other from the second part 414 through the escape groove 414a.
  • the second part 414 may also include an escape hole 414b, that is, the second part 414 includes an escape hole 414b provided through the thickness direction Z, and the escape hole 414b is away from the first part.
  • a part of the second subsection 414 is also provided on one side of the part 413. The parts where the source electrode 510 and the drain electrode 520 are connected to the semiconductor part 210 through the holes are located in the escape hole 414b, so that the source electrode 510 and the drain electrode 520 are connected to the semiconductor part 210 through the escape hole 414b.
  • the second sections 414 are insulated from each other.
  • the through hole is located in the escape hole 414b , so that the source electrode 510 and the drain electrode 520 are insulated from each other from the second part 414 through the escape hole 414b.
  • the distance between the source electrode 510 and the drain electrode 520 can be smaller, resulting in that the source electrode 510 and/or the drain electrode 520 and
  • the positions of the second sub-parts 414 interfere with each other, it is still possible to ensure that the source electrode 510, the drain electrode 520 and the second sub-part 414 are insulated from each other, thereby improving the short-circuit connection problem between the source electrode 510, the drain electrode 520 and the second sub-part 414, and further The yield of the array substrate 10 is improved.
  • a second embodiment of the present application also provides a display panel 1, including the array substrate 10 of any of the above first embodiments. Since the display panel 1 of the embodiment of the present application includes the array substrate 10 of any of the above embodiments, the display panel 1 of the embodiment of the present application has the beneficial effects of any of the above array substrates 10 .
  • the display panel 1 may also include a light-emitting structure layer located on one side of the array substrate 10 .
  • a pixel electrode layer 20 may be disposed between the light-emitting structure layer and the array substrate 10.
  • the pixel electrode layer 20 includes a plurality of pixel electrodes 21 distributed at intervals.
  • the pixel electrodes 21 may be interconnected with the source electrode 510 or the drain electrode 520 of some thin film transistors.
  • the light-emitting structure layer may include a pixel definition layer 30.
  • the pixel definition layer 30 includes an isolation part 31 and a pixel opening 32 formed by the isolation part 31.
  • the pixel electrode 21 is exposed by the pixel opening 32, and the light-emitting unit 40 may be disposed in the pixel opening 32.
  • a common electrode layer 50 may be provided on a side of the pixel definition layer 30 away from the array substrate 10 . The common electrode layer 50 interacts with the pixel electrode 21 and is used to drive the light-emitting unit 40 to emit light.
  • the third embodiment of the present application also provides a method for preparing an array substrate 10 .
  • the array substrate 10 may be the array substrate 10 described in any of the embodiments of FIGS. 1 to 11 .
  • the preparation method of the array substrate 10 may include:
  • Step S01 A first insulating material layer is provided on the substrate 100, and the first insulating material layer is patterned to form a first insulating layer 300 including a limiting groove 301.
  • the limiting groove 301 is separated from the substrate by the first insulating layer 300.
  • the surface of the bottom 100 is recessed.
  • the active material layer may be patterned to form a plurality of limiting grooves 301.
  • an active material layer is also provided on the substrate 100 and patterned to form a layer including: Active layer 200 of semiconductor portion 210 .
  • dry etching or wet etching may be used to pattern the active material layer.
  • Step S02 Set a first metal material layer on the side of the first insulating layer 300 facing away from the substrate, and pattern the first metal material layer using a wet etching process to form the first metal layer 400 including the signal line 410.
  • the signal The line 410 includes a first portion 413 and a second portion 414 surrounding at least part of the first portion 413.
  • the first portion 413 is located in the limiting groove 301, and at least part of the second portion 414 is located away from the first insulation layer 300. bottom surface.
  • Step S03 Dispose an insulating material on the side of the first metal layer 400 away from the first insulating layer 300 to form a second insulating layer 600. At least part of the insulating material is deposited on the second portion 414 to form an opening facing the first metal layer 400, and A receiving slot for receiving the second portion 414 .
  • the array substrate 10 includes a substrate 100, a first insulating layer 300, a first metal layer 400 and a second insulating layer 600.
  • a limiting groove 301 is provided on the first insulating layer 300 , and at least part of the signal line 410 is located in the limiting groove 301 .
  • the signal line 410 includes a first portion 413 located inside the limiting groove 301 and a second portion 414 located outside the limiting groove 301.
  • the receiving groove on the second insulating layer 600 accommodates the second portion 414.
  • the second insulating layer 600 can be directly deposited on the first insulating layer 300 and the first metal layer 400, which can simplify the preparation of the array substrate 10.
  • the limiting groove 301 can provide a limiting position for the signal line 410, thereby determining the position and size of the signal line 410. Therefore, a relatively mature process such as wet etching can be used to prepare the signal line 410, which can simplify the preparation of the array substrate 10.
  • the distance between the first subsection 413 located in the limiting groove 301 and other conductors is relatively close, so the size of the overlapping area between the first subsection 413 and other conductors is It can affect the device characteristics.
  • the size and position of the limiting groove 301 the device characteristics can be controlled and the stability of the device characteristics can be improved. Therefore, the array substrate 10 provided by the embodiment of the present application has the advantage of stable device characteristics.
  • step S02 includes:
  • Step S021 Set the first sub-insulating layer 310 on the substrate 100.
  • Step S022 A second insulating material layer is provided on the side of the first sub-insulating layer 310 facing away from the active layer 200, and the second insulating material layer is patterned to form a second sub-insulating layer 320 including the limiting groove 301.
  • the first insulating layer 300 includes a first sub-insulating layer 310 and a second sub-insulating layer 320, and the limiting groove 301 is provided in the second sub-insulating layer 320, that is, the limiting groove 301 is located in the second sub-insulating layer 320.
  • the distance between the bottom wall surface of the limiting groove 301 and the semiconductor part 210 can be adjusted by controlling the thickness of the first sub-insulating layer 310.
  • the limiting groove 301 is provided in the second sub-insulating layer 320.
  • the limiting groove 301 can be obtained by patterning only the second sub-insulating layer 320, which can also reduce the risk of the limiting groove 301 penetrating the entire first insulating layer 300. .
  • an insulating stop layer 330 may also be provided on a side of the first sub-insulating layer 310 facing away from the active layer 200.
  • the insulating stop layer 330 can also be patterned to form the above-mentioned etching stop portion 331 .
  • a second insulating material layer is provided on a side of the insulating stop layer 330 away from the active layer 200 in step S02.
  • the second sub-insulating layer 320 can be patterned.
  • the distance between the bottom wall surface of the limiting groove 301 and the semiconductor part 210 can be ensured.
  • the signal line 410 may include a first sub-layer 411 and a second sub-layer 412.
  • the first sub-layer 411 is located on a side of the first insulating layer 300 away from the active layer 200.
  • the second sub-layer 412 is located on the side of the first sub-layer 411 away from the first insulating layer 300, and the material of the second sub-layer 412 includes copper, as shown in Figure 15, then step S03 can include:
  • Step S031 Sputter to form a first sub-material layer on the side of the first insulating layer 300 facing away from the active layer 200.
  • Step S032 A second sub-material layer is provided on the first sub-material layer.
  • the first sub-material layer and the second sub-material layer form a first metal material layer, and the second sub-material layer includes copper material.
  • Step S033 Use wet etching to pattern the first sub-material layer and the second sub-material layer to form the signal line 410.
  • the first sub-material layer forms the first sub-layer 411
  • the second sub-material layer forms the second sub-layer. 412.
  • the signal line 410 includes two structural layers, that is, the signal line 410 includes a first sub-layer 411 and a second sub-layer 412.
  • the material of the second sub-layer 412 includes copper.
  • Copper material has the advantages of low impedance and good electrical conductivity, so that the signal line 410 has good electrical conductivity.
  • the signal line 410 is located in the limiting groove 301.
  • the overlapping area of the signal line 410 and the channel region 213 located in the limiting groove 301 determines the performance of the thin film transistor. Therefore, even if the size of the signal line 410 is relatively large and the larger size signal line 410 is provided outside the limiting groove 301, the device characteristics will not be affected. That is to say, the size of the signal line 410 in the embodiment of the present application is not limited.
  • the second sub-layer 412 can be patterned using a wet etching method, which can improve Since the line width of the signal line 410 is too small, the wet etching method cannot be used to pattern the second sub-layer 412 .
  • the wet etching method When the wet etching method is used to pattern the second sub-layer 412, the copper material can be effectively removed, and the process is more mature. And due to the existence of the limiting groove 301, copper material can be deposited in the limiting groove 301. By changing the position and size of the limiting groove 301, the position and size of the signal line 410 can be controlled, thereby improving the inability of the wet etching process to be applied. The line width is too small. Compared with dry etching, the process equipment for wet etching of the second sub-layer 412 is more mature, and the requirements for the thickness of the second sub-layer 412 are lower. Even if the thickness of the second sub-layer 412 is small, it can be processed well. The second sub-layer 412 is patterned without generating too much waste material and affecting the process yield.

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Abstract

本申请公开了一种阵列基板、显示面板及阵列基板的制备方法，阵列基板包括：衬底；第一绝缘层，位于衬底的一侧，第一绝缘层背离衬底的表面凹陷形成有限位槽；第一金属层，位于第一绝缘层背离衬底的一侧，第一金属层包括信号线，信号线包括第一分部和环绕至少部分第一分部的第二分部，第一分部位于限位槽，至少部分第二分部位于第一绝缘层背离衬底的表面；第二绝缘层，位于第一金属层背离衬底的一侧，第二绝缘层包括开口朝向第一金属层的容纳槽，第二分部位于容纳槽。通过合理设置限位槽的尺寸和位置能够控制器件特性，提高器件特性稳定性，因此本申请实施例提供的阵列基板具有器件特性稳定的优势。

Description

阵列基板、显示面板及阵列基板的制备方法
相关申请的交叉引用
本申请要求享有于2022年08月24日提交的名称为“阵列基板、显示面板及阵列基板的制备方法”的中国专利申请第202211023799.7号的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请涉及显示领域，具体涉及一种阵列基板、显示面板及阵列基板的制备方法。
背景技术
随着电子设备的快速发展，用户对显示面板的要求越来越高。显示面板包括发光器件和驱动器件，驱动器件包括薄膜晶体管和电容极板等需要两层导线在特定位置交叠的零部件，在这些零部件中如果双层导线的交叠位置不准确会导致器件特性不稳定，影响显示面板的良率。
发明内容
本申请实施例提供一种阵列基板、显示面板及阵列基板的制备方法，旨在提供一种器件特性稳定的阵列基板。
本申请第一方面的实施例提供一种阵列基板，包括：衬底；第一绝缘层，位于衬底的一侧，第一绝缘层背离衬底的表面凹陷形成有限位槽；第一金属层，位于第一绝缘层背离衬底的一侧，第一金属层包括信号线，信号线包括第一分部和环绕至少部分第一分部的第二分部，第一分部位于限位槽，至少部分第二分部位于第一绝缘层背离衬底的表面；第二绝缘层，位于第一金属层背离衬底的一侧，第二绝缘层包括开口朝向第一金属层的容纳槽，第二分部位于容纳槽。
本申请第二方面的实施例提供一种显示面板，其包括上述任一实施方式的阵列基板。
本申请第三方面的实施例提供一种阵列基板的制备方法，包括：
在衬底上设置第一绝缘材料层，对第一绝缘材料层进行图案化处理形成包括限位 槽的第一绝缘层，限位槽由第一绝缘层背离衬底的表面凹陷形成；
在第一绝缘层背离衬底的一侧设置第一金属材料层，利用湿刻蚀工艺对第一金属材料层进行图案化处理形成包括信号线的第一金属层，信号线包括第一分部和环绕至少部分第一分部的第二分部，第一分部位于限位槽，至少部分第二分部位于第一绝缘层背离衬底的表面；
在第一金属层背离第一绝缘层的一侧设置绝缘材料形成第二绝缘层，至少部分绝缘材料沉积于第二分部上形成开口朝向第一金属层、并容纳第二分部的容纳槽。
在本申请实施例提供的阵列基板中，阵列基板包括衬底、第一绝缘层、第一金属层和第二绝缘层。第一绝缘层上设置有限位槽，至少部分信号线位于限位槽内。信号线包括位于限位槽内的第一分部和位于限位槽外的第二分部，第二绝缘层上的容纳槽容纳第二分部，第二绝缘层可以直接沉积在第一绝缘层和第一金属层上获得，能够简化阵列基板的制备。限位槽能够向信号线提供限位，进而决定信号线的位置和尺寸，因此可以使用湿刻蚀等较为成熟的工艺制备信号线，能够简化阵列基板的制备。此外，当信号线需要与其他导线交叠时，位于限位槽内的信号线与其他导线之间的距离较近，因此限位槽内的信号线和其他导线的交叠区域尺寸能够影响器件特性，通过合理设置限位槽的尺寸和位置能够控制器件特性，提高器件特性稳定性，因此本申请实施例提供的阵列基板具有器件特性稳定的优势。
附图说明
通过阅读以下参照附图对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显，其中，相同或相似的附图标记表示相同或相似的特征，附图并未按照实际的比例绘制。
图1是本申请第一方面实施例提供的一种阵列基板的局部剖视图；
图2是本申请第一方面另一实施例提供的一种阵列基板的局部剖视图；
图3是本申请第一方面又一实施例提供的一种阵列基板的局部剖视图；
图4是本申请第一方面还一实施例提供的一种阵列基板的局部剖视图；
图5是本申请第一方面再一实施例提供的一种阵列基板的局部剖视图；
图6是本申请第一方面再一实施例提供的一种阵列基板的局部剖视图；
图7是本申请第一方面再一实施例提供的一种阵列基板的局部剖视图；
图8是本申请第一方面再一实施例提供的一种阵列基板的局部剖视图；
图9是本申请第一方面实施例提供的一种阵列基板的部分层结构俯视图；
图10是本申请第一方面另一实施例提供的一种阵列基板的部分层结构俯视图；
图11是本申请第一方面又一实施例提供的一种阵列基板的部分层结构俯视图；
图12是本申请第二方面实施例提供的一种显示面板的局部剖视图。
图13是本申请第三方面实施例提供的一种阵列基板的制备方法流程示意图；
图14是本申请第三方面实施例提供的一种阵列基板的制备方法中某步骤的流程示意图；
图15是本申请第三方面实施例提供的一种阵列基板的制备方法中另一步骤的流程示意图。
附图标记说明：
1、显示面板；10、阵列基板；20、像素电极层；21、像素电极；30、像素定义层；31、隔离部；32、像素开口；40、发光单元；50、公共电极层；
100、衬底；110、遮挡部；
200、有源层；210、半导体部；211、源区；212、漏区；213、沟道区；20、像素电极层；21、像素电极；
300、第一绝缘层；301、限位槽；310、第一子绝缘层；320、第二子绝缘层；321、绝缘定义部；330、绝缘止挡层；331、刻蚀止挡部；30、像素定义层；31、隔离部；32、像素开口；
400、第一金属层；410、信号线；411、第一子层；412、第二子层；413、第一分部；414、第二分部；414a、避让槽；414b、避让孔；40、发光单元；
500、第二金属层；510、源极；520、漏极；501、第一子段；502、第二子段；50、公共电极层；
600、第二绝缘层。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。应理解，此处所描述的具体实施例仅被配置为解释本申请，并不被配置为限定本申请。对于本领域技术人员来说，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请更好的理解。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括……”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。
应当理解，在描述部件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将部件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
本申请实施例提供了一种阵列基板、显示面板及阵列基板的制备方法，以下将结合附图对显示面板及显示装置的各实施例进行说明。
本申请实施例提供一种阵列基板，用于显示面板，该显示面板可以是有机发光二极管(Organic Light Emitting Diode，OLED)显示面板。
请参阅图1，图1是本申请第一方面实施例提供的一种阵列基板10的局部剖视图。
如图1所示，本申请第一方面的实施例提供的阵列基板10包括：衬底100和设置于衬底100的第一绝缘层300、第一金属层400和第二绝缘层600，第一绝缘层300位于衬底100的一侧，第一绝缘层300背离衬底100的表面凹陷形成有限位槽301；第一金属层400位于第一绝缘层300背离衬底100的一侧，第一金属层400包括信号线410，信号线410包括第一分部413和环绕至少部分第一分部413的第二分部414，第一分部413位于限位槽301，至少部分第二分部414位于第一绝缘层300背离衬底100的表面；第二绝缘层600位于第一金属层400背离衬底100的一侧，第二绝缘层600包括开口朝向第一金属层400的容纳槽(图中未示出)，第二分部414位于容纳槽。
在本申请实施例提供的阵列基板10中，阵列基板10包括衬底100、第一绝缘层300、第一金属层400和第二绝缘层600。第一绝缘层300上设置有限位槽301，至少部分信号线410位于限位槽301内。信号线410包括位于限位槽301内的第一分部413和位于限位槽301外的第二分部414，第二绝缘层600上的容纳槽容纳第二分部414，第二绝缘层600可以直接沉积在第一绝缘层300和第一金属层400上获得，能够简化阵列基板10的制备。限位槽301能够向信号线410提供限位，进而决定信号线410的位置和尺寸，因此可以使用湿刻蚀等较为成熟的工艺制备信号线410，能够简化阵列基板10的制备。此外，当信号线410需要与其他导线交叠时，位于限位槽301内的第一分部413与其他导线之间的距离较近，因此第一分部413和其他导线的交叠区域尺寸能够影响器件特性，通过合理设置限位槽301的尺寸和位置能够控制器件特性，提高器件特性稳定性，因此本申请实施例提供的阵列基板10具有器件特性稳定的优势。
信号线410的设置方式有多种，例如信号线410可以位于边框区，信号线410包括扫描驱动电路。或者，信号线410为阵列基板中电容的其中一个极板。
在另一些实施例中，阵列基板10还包括设置于衬底100的有源层200；有源层200位于衬底100和第一绝缘层300之间，有源层200包括半导体部210，限位槽301在衬底100上的正投影和半导体部210在衬底100上的正投影至少部分交叠设置，信 号线410为栅极线。
在本申请实施例提供的阵列基板10中，半导体部210和信号线410构成阵列基板10驱动电路的薄膜晶体管的一部分。位于限位槽301内的信号线410的第一分部413与半导体部210之间的距离较近，因此第一分部413和半导体部210的交叠区域的长宽比能够影响薄膜晶体管的器件特性，通过合理设置限位槽301的尺寸和位置能够控制薄膜晶体管的特性，提高薄膜晶体管的特性稳定性，因此本申请实施例提供的阵列基板10具有器件特性稳定的优势。
衬底100的设置方式有多种，例如衬底100为硬性衬底100，衬底100的材料包括玻璃等硬性材料。或者衬底100为柔性衬底100，衬底100的材料包括聚酰亚胺等柔性材料。阵列基板10还可以包括位于衬底100背离有源层200一侧的支撑层，支撑层可以包括钢板层和/或泡棉层。衬底100和有源层200之间还可以设置缓冲层等层结构。可选的，衬底100内还可以设置有遮挡部110，遮挡部110用于遮挡光线，以改善光线入射至半导体部210影响薄膜晶体管的器件特性。
有源层200中半导体部210的设置方式有多种，例如有源层200包括多个间隔分布的半导体部210，各半导体部210分别属于各不同的薄膜晶体管。限位槽301的个数也为多个，各限位槽301与各半导体部210对应设置，即各限位槽301在衬底100上的正投影与各半导体部210在衬底100上的正投影至少部分交叠设置。信号线410的个数也为多个，各信号线410的第一分部413位于各限位槽301。
限位槽301为第一绝缘层300表面凹陷形成的凹槽，因此限位槽301的底部和半导体部210之间保留了部分第一绝缘层300材料。也就是说，限位槽301未贯穿第一绝缘层300设置，限位槽301的底壁面与半导体部210之间具有绝缘材料，以免信号线410和半导体部210短路连接。
可选的，半导体部210包括沿第一方向依次设置的源区211、沟道区213和漏区212，限位槽301在衬底100上的正投影和沟道区213在衬底100上的正投影至少部分重合。阵列基板10还包括第二金属层500，第二金属层500包括源极510和漏极520，源极510和源区211过孔连接，漏区212和漏极520过孔连接。
在这些可选的实施例中，源极510、漏极520、信号线410和半导体部210组合形成薄膜晶体管。位于限位槽301内的信号线410与沟道区213之间的距离较近，因此位于限位槽301内的信号线410与沟道区213的交叠区域决定了薄膜晶体管的器件特性，通过合理设置限位槽301的位置和尺寸可以调整薄膜晶体管的器件特性。
当阵列基板10包括第二金属层500时，第二绝缘层600位于第一金属层400和第二金属层500之间，以避免第一金属层400和第二金属层500短路连接。可选的，第一金属层400和第二金属层500之间还可以设置有其他金属层。源极510和源区211过孔连接是指第二金属层500和半导体部210之间的绝缘材料层(包括第一绝缘层 300)上设置有过孔，制备第二金属层500时金属材料会落入过孔内与半导体部210相互连接，使得源极510通过过孔与源区211相互连接，漏极520通过过孔与漏区212相互连接。
在一些实施例中，阵列基板10还包括多条导线，例如阵列基板10的导线包括数据线、扫描线、电源线、电压参考线等，信号线410可以与扫描线相互连接。可选的，扫描线和信号线410同层设置。信号线410可以认为是第一金属层400中的导线上与沟道区213交叠的部分分段，扫描线可以是第一金属层400中的信号线上与沟道区213错位的部分分段。源极510和漏极520中的一者连接于数据线，数据线与源极510、漏极520同层设置并位于第二金属层500。源极510可以认为是第二金属层500中信号线上与源区211过孔连接的部位，漏极520可以认为是第二金属层500中信号线上与漏区212过孔连接的部位。
可选的，沟道区213在衬底100上的正投影位于限位槽301在衬底100上的正投影之内。在这些实施例中，能够保证沟道区213与限位槽301内信号线410的交叠面积，进而保证薄膜晶体管的前进特性。可选的，限位槽301在衬底100上的正投影可以为限位槽301的开口或底部在衬底100上的正投影，也可以为限位槽301的开口和底部之间的任意位置在衬底100上的正投影。
第一绝缘层300的设置方式有多种，例如，如图1所示，第一绝缘层300可以为一层结构设置，通过对第一绝缘层300进行图案化处理形成由第一绝缘层300表面凹陷的限位槽301。
在另一些实施例中，请参阅图2，图2是本申请第一方面另一实施例提供的一种阵列基板10的局部剖视图。如图2所示，第一绝缘层300包括：第一子绝缘层310和第二子绝缘层320，第一子绝缘层310位于有源层200背离衬底100的一侧；第二子绝缘层320位于第一子绝缘层310背离有源层200的一侧，限位槽301设置于第二子绝缘层320。
在这些可选的实施例中，第一绝缘层300包括第一子绝缘层310和第二子绝缘层320，且限位槽301设置于第二子绝缘层320，即限位槽301位于第一子绝缘层310之上，通过控制第一子绝缘层310的厚度可以调节限位槽301底壁面和半导体部210之间的距离。此外，限位槽301设置于第二子绝缘层320，仅对第二子绝缘层320图案化处理即可获得限位槽301，还能够改善限位槽301贯穿整个第一绝缘层300的风险。
可选的，第一子绝缘层310整面设置。当阵列基板10用于显示面板时，第一子绝缘层310至少在显示面板的显示区域连续设置，能够提高第一金属层400和有源层200之间的绝缘性能。
可选的，如图2所示，第二子绝缘层320整面设置。当阵列基板10用于显示面板时，第二子绝缘层320至少在显示面板的显示区域连续设置，并对第二子绝缘层320 图案化处理形成多个限位槽301。
在另一些实施例中，请参阅图3，图3是本申请第一方面又一实施例提供的一种阵列基板10的局部剖视图，如图3所示，第二子绝缘层320包括绝缘定义部321，绝缘定义部321位于源极510和漏极520之间，且信号线410在衬底100上的正投影位于绝缘定义部321在衬底100上的正投影之内。
在这些可选的实施例中，第二子绝缘层320包括对应于信号线410和限位槽301独立设置的绝缘定义部321，能够减小相邻两个绝缘定义部321之间的膜层厚度，即能够减少除绝缘定义部321所在区域以外区域的膜层厚度，使得显示面板更加轻薄化。
第一子绝缘层310的材料设置方式有多种，例如第一子绝缘层310为栅间绝缘层，第一子绝缘层310的材料包括二氧化硅等。
第二子绝缘层320的材料设置方式有多种，例如第二子绝缘层320的材料包括氮化硅和氧化硅中的至少一者。可选的，可以选用光刻的方式对第二子绝缘层320进行图案化处理形成限位槽301。例如，可以在第二子绝缘层320表面设置光刻胶，并曝光显影刻蚀形成限位槽301。
第二子绝缘层320的厚度为
Figure PCTCN2022130720-appb-000001
即限位槽301的深度为
Figure PCTCN2022130720-appb-000002
当限位槽301的深度在上述范围之内时，既能够改善位于限位槽301内的信号线410和位于限位槽301外的信号线410之间距离过小，导致位于限位槽301外的信号线410与沟道区213交叠会影响薄膜晶体管的器件特性，也能够改善位于限位槽301内的信号线410和位于限位槽301外的信号线410之间的距离过大，导致信号线410可能在限位槽301的侧壁位置断裂，影响信号线410的导电性能。
请参阅图4，图4是本申请第一方面还一实施例提供的一种阵列基板10的局部剖视图。
在一些实施例中，如图4所示，第一绝缘层300还包括绝缘止挡层330，绝缘止挡层330位于第一子绝缘层310和第二子绝缘层320之间。
在这些可选的实施例中，通过在第二子绝缘层320和第一子绝缘层310之间设置绝缘止挡层330，在对第二子绝缘层320进行图案化处理时，能够改善第一子绝缘层310被误刻蚀的情况，能够保证限位槽301底壁面与半导体部210之间的距离。
绝缘止挡层330的形状设置方式有多种，如图4所示，绝缘止挡层330可以整面设置，更好地改善第二子绝缘层320刻蚀过程中，刻蚀液等腐蚀性材料对第一子绝缘层310的影响。
请参阅图5和图6，图5是本申请第一方面再一实施例提供的一种阵列基板10的局部剖视图。图6是本申请第一方面还一实施例提供的一种阵列基板10的局部剖视图。图5和图6不同之处在于第二子绝缘层320的设置方式不同。
在另一些实施例中，如图5和图6所示，绝缘止挡层330还可以包括刻蚀止挡部 331，刻蚀止挡部331位于源极510和漏极520之间，且限位槽301在衬底100上的正投影位于刻蚀止挡部331在衬底100上的正投影之内。
在这些可选的实施例中，限位槽301位于刻蚀止挡部331上，刻蚀止挡部331能够改善由于刻蚀形成限位槽301时对第一子绝缘层310的影响。且刻蚀止挡部331和限位槽301对应设置能够减少除刻蚀止挡部331所在区域以外区域的膜层厚度，使得显示面板更加轻薄化。
如图5所示，当绝缘止挡层330非整面设置并包括刻蚀止挡部331时，第二子绝缘层320可以整面设置，以节省材料并减小阵列基板10上除刻蚀止挡部331以外区域的厚度。或者如图6所示，当绝缘止挡层330非整面设置并包括刻蚀止挡部331时，第二子绝缘层320也可以非整面设置并包括绝缘定义部321，以进一步节省材料并减小阵列基板10上除刻蚀止挡部331和绝缘定义部321以外区域的厚度。
绝缘止挡层330的材料设置方式有多种，可选的，绝缘止挡层330的材料包括非晶硅和氧化硅中的至少一者，使得在对第二子绝缘层320进行刻蚀处理时，能够减小刻蚀液对绝缘止挡层330的影响。可选的，绝缘止挡层330的厚度在
Figure PCTCN2022130720-appb-000003
当绝缘止挡层330的厚度在上述范围之内时，既能够改善由于绝缘止挡层330厚度过小导致绝缘止挡层330保护力度不足导致的对第一子绝缘层310的误刻蚀，也能够改善由于绝缘止挡层330的厚度过大导致的显示面板的膜层过厚。
可选的，在制备过程中，绝缘止挡层330和第二子绝缘层320的材料不同或者材料比例不同，使得刻蚀过程中可以改善绝缘止挡层330被刻蚀的问题。或者，绝缘止挡层330的材料硬度大于第二子绝缘层320的材料硬度，改善改善绝缘止挡层330被刻蚀的问题。
信号线410的设置方式有多种，信号线410例如为单层金属层，且至少部分金属材料层位于限位槽301内。例如信号线410的材料包括铝、铝合金等金属材料。
在另一些实施例中，如图1至图6所示，信号线410包括第一子层411和第二子层412，第一子层411位于第一绝缘层300背离有源层200的一侧；第二子层412位于第一子层411背离第一绝缘层300的一侧，第二子层412的材料包括铜。
在这些可选的实施例中，信号线410包括两层结构层，即信号线410包括第一子层411和第二子层412，第二子层412的材料包括铜，通过设置第一子层411能够改善第二子层412中铜材料的扩散问题。铜材料具有阻抗低、导电性能好等优势，使得信号线410具有良好的导电性能。
此外，在本申请实施例提供的阵列基板10中，第一分部413位于限位槽301内，第一分部413和沟道区213的交叠面积决定了薄膜晶体管的器件特性，因此即使信号线410的尺寸较大，在限位槽301外设置了较大尺寸的信号线410，也不会对器件特性产生影响。也就是说，本申请实施例中信号线410的尺寸不会受到限制，当第二子层 412的材料包括铜时，可以利用湿刻蚀方法对第二子层412进行图案化处理，能够改善由于信号线410线宽过小导致无法使用湿刻蚀方法对第二子层412进行图案化处理的问题。
可选的，当第一金属层400包括扫描线时，扫描线和信号线410同层铜材料设置，即扫描线也可以包括两层结构层，且扫描线的两层结构层与信号线410的第一子层411、第二子层412同层且同材料设置。
第一子层411的材料设置方式有多种，为了更好的防止铜材料的扩散，第一子层411的材料可以包括钼、钼合金、钛和钛合金中的至少一者。
在一些可选的实施例中，第一子层411的厚度可以为
Figure PCTCN2022130720-appb-000004
可选的，第二子层412的厚度可以大于或等于
Figure PCTCN2022130720-appb-000005
例如第二子层412的厚度为
Figure PCTCN2022130720-appb-000006
使得第二子层412具有良好的导电性能。
源极510和漏极520的设置方式有多种，如图1至图6所示，例如可以在第二金属层500和有源层200之间的第一绝缘层300上开设过孔，在形成第二金属层500的源极510和漏极520时，金属材料落入过孔内使得源极510与源区211过孔连接，漏极520与漏区212过孔连接。
在另一些可选的实施例中，还可以将源极510和漏极520分段成型。例如，如图7所示，源极510和漏极520中的至少一者包括第一子段501和第二子段502，第一子段501位于第一金属层400，第一子段501和源区211和/或漏区212过孔连接，且第一子段501和信号线410的材料相同；第二子段502位于第二金属层500，第二子段502和第一子段501过孔连接。
在这些可选的实施例中，源极510和/或漏极520包括第一子段501和第二子段502，将源极510和/或漏极520分段制备能够保证源极510和/或漏极520的导电性能。
可选的，源极510和漏极520均包括第一子段501和第二子段502，能够同时提高源极510和漏极520的导电性能，保证源极510和漏极520导电性能接近。
可选的，当信号线410包括第一子层411和第二子层412时，第一子段501也包括第一子层411和第二子层412，第一子段501的材料包括铜材料，能够提高第一子段501的导电性能。
信号线410的形状设置方式有多种，例如信号线410完全位于限位槽301内。
请参阅图8和图9，图8是本申请第一方面实施例提供的一种阵列基板10的剖视图，图9是本申请实施例提供的一种阵列基板10的部分层结构的俯视图，为了更好地展示层结构，图9中仅展示了半导体部210、源极510、漏极520和信号线410的相对位置关系。
在另一些实施例中，如图8和图9所示，在一些实施例中，沟道区213在第二方 向Y上的延伸尺寸小于限位槽301在第二方向Y上的延伸尺寸。限位槽301在第二方向Y上的延伸尺寸较大，能够保证限位槽301和沟道区213的交叠面积，提高薄膜晶体管的器件特性。
第二分部414的设置位置有多种，第二分部414可以位于第一分部413周向上的任意位置，只要第二分部414与第一分部413相互连接即可。
可选的，如图9所示，至少部分第二分部414位于第一分部413在第二方向上的至少一侧，第二方向与第一方向相交。可选的，第二方向可以为扫描线的延伸方向，第二分部414位于第一分部413在第二方向上的一侧，便于第一分部413能够通过第二分部414与扫描线相互连接。
可选的，如图10和图11所示，至少部分第二分部414位于第一分部413在第一方向上的至少一侧，且第二分部414与源极510、漏极520相互绝缘。可选的，第一方向为扫描线和信号线410的宽度方向，第二分部414位于第一分部413在第一方向上的至少一侧，能够增大信号线410的宽度，增大信号线410的分布面积，进而减小信号线410的电阻，当第二分部414与栅极、漏极520绝缘能够避免信号线410和源极510、漏极520短路连接。
第二分部414和源极510、漏极520相互绝缘设置的方式有多种，例如如图10所示，第二分部414上设置有避让槽414a，避让槽414a沿厚度方向Z贯穿第二分部414，第二分部414远离第一分部413的边缘朝向第一分部413沿X方向凹陷形成避让槽414a，源极510、漏极520与半导体部210过孔连接的部分位于避让槽414a内。例如当第二金属层500和半导体部210之间的绝缘材料层上设置有通孔，使得源极510、漏极520通过通孔与半导体部210过孔连接时，通孔位于避让槽414a内，使得源极510、漏极520通过避让槽414a与第二分部414相互绝缘。
在另一些实施例中，如图11所示，第二分部414还可以包括避让孔414b，即第二分部414包括沿厚度方向Z贯穿设置的避让孔414b，避让孔414b背离第一分部413的一侧还设置有部分第二分部414，源极510、漏极520与半导体部210过孔连接的部分位于避让孔414b内，使得源极510、漏极520通过避让孔414b与第二分部414相互绝缘。例如当第二金属层500和半导体部210之间的绝缘材料层上设置有通孔，使得源极510、漏极520通过通孔与半导体部210过孔连接时，通孔位于避让孔414b内，使得源极510、漏极520通过避让孔414b与第二分部414相互绝缘。
在本申请实施例中，通过在第二分部414上设置避让槽414a或避让孔414b，可以在源极510和漏极520之间间距较小，导致源极510和/或漏极520与第二分部414的位置相互干涉时，仍能够保证源极510、漏极520与第二分部414相互绝缘，改善源极510、漏极520与第二分部414短路连接的问题，进而提升阵列基板10的良率。
如图12所示，本申请第二方面的实施例还提供一种显示面板1，包括上述任一第 一方面实施例的阵列基板10。由于本申请实施例的显示面板1包括上述任一实施例的阵列基板10，因此本申请实施例的显示面板1具有上述任一阵列基板10所具有的有益效果。
可选的，显示面板1还可以包括发光结构层，位于阵列基板10的一侧。发光结构层和阵列基板10之间可以设置有像素电极层20，像素电极层20包括间隔分布的多个像素电极21，像素电极21可以与部分薄膜晶体管的源极510或漏极520相互连接。
发光结构层可以包括像素定义层30，像素定义层30包括隔离部31和由隔离部31围合形成的像素开口32，像素电极21由像素开口32露出，像素开口32内可以设置有发光单元40。像素定义层30背离阵列基板10的一侧可以设置有公共电极层50，公共电极层50和像素电极21相互作用并用于驱动发光单元40发光。
本申请第三方面的实施例还提供一种阵列基板10的制备方法，该阵列基板10可以为上述图1至图11任一实施例所述的阵列基板10。如图13所示，阵列基板10的制备方法可以包括：
步骤S01：在衬底100上设置第一绝缘材料层，对第一绝缘材料层进行图案化处理形成包括限位槽301的第一绝缘层300，限位槽301由第一绝缘层300背离衬底100的表面凹陷形成。
如上，当第一绝缘层300包括多个间隔分布的限位槽301时，可以对有源材料层进行图案化处理形成多个限位槽301。
可选的，当阵列基板10包括有源层200时，在步骤S01中设置第一绝缘材料层之前，还在衬底100上设置有源材料层并对有源材料层进行图案化处理形成包括半导体部210的有源层200。可选的，可以选用干刻蚀或者湿刻蚀的方式对有源材料层进行图案化处理。
步骤S02：在第一绝缘层300背离衬底的一侧设置第一金属材料层，利用湿刻蚀工艺对第一金属材料层进行图案化处理形成包括信号线410的第一金属层400，信号线410包括第一分部413和环绕至少部分第一分部413的第二分部414，第一分部413位于限位槽301，至少部分第二分部414位于第一绝缘层300背离衬底的表面。
步骤S03：在第一金属层400背离第一绝缘层300的一侧设置绝缘材料形成第二绝缘层600，至少部分绝缘材料沉积于第二分部414上形成开口朝向第一金属层400、并容纳第二分部414的容纳槽。
利用本申请实施例提供的制备方法制备成型的阵列基板10中，阵列基板10包括衬底100、第一绝缘层300、第一金属层400和第二绝缘层600。第一绝缘层300上设置有限位槽301，至少部分信号线410位于限位槽301内。信号线410包括位于限位槽301内的第一分部413和位于限位槽301外的第二分部414，第二绝缘层600上的容纳槽容纳第二分部414，第二绝缘层600可以直接沉积在第一绝缘层300和第一金属层 400上获得，能够简化阵列基板10的制备。限位槽301能够向信号线410提供限位，进而决定信号线410的位置和尺寸，因此可以使用湿刻蚀等较为成熟的工艺制备信号线410，能够简化阵列基板10的制备。此外，当信号线410需要与其他导线交叠时，位于限位槽301内的第一分部413与其他导线之间的距离较近，因此第一分部413和其他导线的交叠区域尺寸能够影响器件特性，通过合理设置限位槽301的尺寸和位置能够控制器件特性，提高器件特性稳定性，因此本申请实施例提供的阵列基板10具有器件特性稳定的优势。
步骤S02的设置方式有多种，可选的，如图14所示，当第一绝缘层300包括第一子绝缘层310和第二子绝缘层320时，步骤S02包括：
步骤S021：在衬底100上设置第一子绝缘层310。
步骤S022：在第一子绝缘层310背离有源层200的一侧设置第二绝缘材料层，对第二绝缘材料层进行图案化处理形成包括限位槽301的第二子绝缘层320。
在这些可选的实施例中，第一绝缘层300包括第一子绝缘层310和第二子绝缘层320，且限位槽301设置于第二子绝缘层320，即限位槽301位于第一子绝缘层310之上，通过控制第一子绝缘层310的厚度可以调节限位槽301底壁面和半导体部210之间的距离。此外，限位槽301设置于第二子绝缘层320，仅对第二子绝缘层320图案化处理即可获得限位槽301，还能够改善限位槽301贯穿整个第一绝缘层300的风险。
可选的，在步骤S022之前还可以在在第一子绝缘层310背离有源层200的一侧设置绝缘止挡层330。可选的，还可以对绝缘止挡层330进行图案化处理形成上述的刻蚀止挡部331。
当第一子绝缘层310上设置有绝缘止挡层330时，在步骤S02中在绝缘止挡层330背离有源层200的一侧设置第二绝缘材料层。
在这些可选的实施例中，通过在第二子绝缘层320和第一子绝缘层310之间设置绝缘止挡层330，在对第二子绝缘层320进行图案化处理时，能够改善第一子绝缘层310被误刻蚀的情况，能够保证限位槽301底壁面与半导体部210之间的距离。
可选的，如上所述，信号线410可以包括第一子层411和第二子层412，所述第一子层411位于所述第一绝缘层300背离所述有源层200的一侧，所述第二子层412位于所述第一子层411背离所述第一绝缘层300的一侧，所述第二子层412的材料包括铜，如图15所示，那么步骤S03可以包括：
步骤S031：在第一绝缘层300背离有源层200的一侧溅镀形成第一子材料层。
步骤S032：在第一子材料层上设置第二子材料层，第一子材料层和第二子材料层形成第一金属材料层，第二子材料层包括铜材料。
步骤S033：利用湿刻蚀对第一子材料层和第二子材料层进行图案化处理形成信号线410，第一子材料层形成第一子层411，第二子材料层形成第二子层412。
在这些可选的实施例中，信号线410包括两层结构层，即信号线410包括第一子层411和第二子层412，第二子层412的材包括铜，通过设置第一子层411能够改善第二子层412中铜材料的扩散问题。铜材料具有阻抗低、导电性能好等优势，使得信号线410具有良好的导电性能。
此外，在本申请实施例提供的阵列基板10中，至少部分信号线410位于限位槽301内，位于限位槽301内的信号线410和沟道区213的交叠面积决定了薄膜晶体管的器件特性，因此即使信号线410的尺寸较大，在限位槽301外设置了较大尺寸的信号线410，也不会对器件特性产生影响。也就是说，本申请实施例中信号线410的尺寸不会受到限制，当第二子层412的材料包括铜时，可以利用湿刻蚀方法对第二子层412进行图案化处理，能够改善由于信号线410线宽过小导致无法使用湿刻蚀方法对第二子层412进行图案化处理的问题。
在利用湿刻蚀方法对第二子层412进行图案化处理时，可以有效地将铜材料去除，工艺制程更加成熟。且由于限位槽301的存在，铜材料可以沉积于限位槽301内，通过改变限位槽301的位置和尺寸可以控制信号线410的位置和尺寸，进而可以改善湿刻蚀工艺无法应用于线宽太小的缺陷。湿刻蚀处理第二子层412相对于干刻蚀来说，工艺设备也更加成熟，对第二子层412厚度的要求较低，即使第二子层412厚度较小也能够很好地对第二子层412进行图案化处理，不会产生过多的废料影响工艺良率。
依照本申请如上文的实施例，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本申请的原理和实际应用，从而使所属技术领域技术人员能很好地利用本申请以及在本申请基础上的修改使用。本申请仅受权利要求书及其全部范围和等效物的限制。

Claims (20)

  1. 一种阵列基板，包括：
    衬底；
    第一绝缘层，位于所述衬底的一侧，所述第一绝缘层背离所述衬底的表面凹陷形成有限位槽；
    第一金属层，位于所述第一绝缘层背离所述衬底的一侧，所述第一金属层包括信号线，所述信号线包括第一分部和环绕至少部分所述第一分部的第二分部，所述第一分部位于所述限位槽，至少部分所述第二分部位于所述第一绝缘层背离所述衬底的表面；
    第二绝缘层，位于所述第一金属层背离所述衬底的一侧，所述第二绝缘层包括开口朝向所述第一金属层的容纳槽，所述第二分部位于所述容纳槽。
  2. 根据权利要求1所述的阵列基板，其中，还包括有源层，所述有源层位于所述衬底和所述第一绝缘层之间，所述有源层包括半导体部，所述限位槽在所述衬底上的正投影和所述半导体部在所述衬底上的正投影至少部分重合，所述信号线为栅极线。
  3. 根据权利要求2所述的阵列基板，其中，
    所述半导体部包括沿第一方向依次设置的源区、沟道区和漏区，所述限位槽在所述衬底上的正投影和所述沟道区在所述衬底上的正投影至少部分重合；
    所述阵列基板还包括第二金属层，所述第二金属层位于所述第一金属层背离所述绝缘层的一侧，所述第二金属层包括源极和漏极，所述源极和所述源区过孔连接，所述漏极和所述漏区过孔连接。
  4. 根据权利要求3所述的阵列基板，其中，所述沟道区在所述衬底上的正投影位于所述限位槽在所述衬底上的正投影之内；
    和/或，所述沟道区在第二方向上的延伸尺寸小于所述限位槽在所述第二方向上的延伸尺寸，所述第二方向与所述第一方向、所述阵列基板的厚度方向均相交；
  5. 根据权利要求3所述的阵列基板，其中，所述第一绝缘层包括：
    第一子绝缘层，位于所述有源层背离所述衬底的一侧；
    第二子绝缘层，位于所述第一子绝缘层背离所述有源层的一侧，所述限位槽设置于所述第二子绝缘层。
  6. 根据权利要求5所述的阵列基板，其中，所述限位槽贯穿所述第二子绝缘层设置，所述第二子绝缘层整面设置，或者所述第二子绝缘层包括绝缘定义部，所述绝缘定义部位于所述源极和所述漏极之间，且所述信号线在所述衬底上的正投影位于所述绝缘定义部在所述衬底上的正投影之内；
  7. 根据权利要求5所述的阵列基板，其中，所述第一绝缘层还包括绝缘止挡层，所 述绝缘止挡层位于所述第一子绝缘层和所述第二子绝缘层之间。
  8. 根据权利要求7所述的阵列基板，其中，所述绝缘止挡层整面设置，或者所述绝缘止挡层包括刻蚀止挡部，所述刻蚀止挡部位于所述源极和所述漏极之间，且所述限位槽在所述衬底上的正投影位于所述刻蚀止挡部在所述衬底上的正投影之内。
  9. 根据权利要求7所述的阵列基板，其中，所述第二子绝缘层的材料包括氮化硅和氧化硅中的至少一者；
    和/或，所述绝缘止挡层的材料包括非晶硅和氧化硅中的至少一者。
  10. 根据权利要求7所述的阵列基板，其中，所述第二子绝缘层的厚度为
    Figure PCTCN2022130720-appb-100001
    和/或，所述绝缘止挡层的厚度为
    Figure PCTCN2022130720-appb-100002
  11. 根据权利要求3所述的阵列基板，其中，所述源极和所述漏极中的至少一者包括：
    第一子段，位于所述第一金属层，所述第一子段与所述源区和/或漏区过孔连接，且所述第一子段和所述信号线的材料相同；
    第二子段，位于所述第二金属层，所述第二子段和所述第一子段过孔连接。
  12. 根据权利要求3所述的阵列基板，其中，
    至少部分所述第二分部位于所述第一分部在第二方向上的至少一侧，所述第二方向与所述第一方向相交。
  13. 根据权利要求12所述的阵列基板，其中，，至少部分所述第二分部位于所述第一分部在所述第一方向上的至少一侧，且所述第二分部与所述源极、所述漏极相互绝缘。
  14. 根据权利要求12所述的阵列基板，其中，，所述第二分部包括避让槽或避让孔，所述第二分部通过所述避让槽或所述避让孔与所述源极、所述漏极相互绝缘。
  15. 根据权利要求1所述的阵列基板，其中，所述信号线包括：
    第一子层，位于所述第一绝缘层背离所述有源层的一侧；
    第二子层，位于所述第一子层背离所述第一绝缘层的一侧，所述第二子层的材料包括铜。
  16. 一种显示面板，其中，包括权利要求1-6任一项所述的阵列基板。
  17. 一种阵列基板的制备方法，其中，包括：
    在衬底上设置第一绝缘材料层，对所述第一绝缘材料层进行图案化处理形成包括限位槽的第一绝缘层，所述限位槽由所述第一绝缘层背离所述衬底的表面凹陷形成；
    在所述第一绝缘层背离所述衬底的一侧设置第一金属材料层，利用湿刻蚀工艺对所述第一金属材料层进行图案化处理形成包括信号线的第一金属层，所述信号线包括第一分部和环绕至少部分所述第一分部的第二分部，所述第一分部位于所述限位槽， 至少部分所述第二分部位于所述第一绝缘层背离所述衬底的表面；
    在所述第一金属层背离所述第一绝缘层的一侧设置绝缘材料形成第二绝缘层，至少部分绝缘材料沉积于所述第二分部上形成开口朝向所述第一金属层、并容纳所述第二分部的容纳槽。
  18. 根据权利要求17所述的方法，其中，在所述衬底上设置第一绝缘材料层，对所述第一绝缘材料层进行图案化处理形成包括限位槽的第一绝缘层的步骤中：
    在所述衬底上设置第一子绝缘层；
    在所述第一子绝缘层背离所述衬底的一侧设置第二子绝缘材料层，对所述第二子绝缘材料层进行图案化处理形成包括所述限位槽的第二子绝缘层。
  19. 根据权利要求18所述的方法，其中，在所述第一子绝缘层背离所述衬底的一侧设置第二子绝缘材料层，对所述第二子绝缘材料层进行图案化处理形成包括所述限位槽的第二子绝缘层得步骤之前还包括：
    在所述第一子绝缘层背离所述衬底的一侧设置绝缘止挡层；
    在所述第一子绝缘层背离所述衬底的一侧设置第二子绝缘材料层，对所述第二子绝缘材料层进行图案化处理形成包括所述限位槽的第二子绝缘层的步骤中：在所述绝缘止挡层背离所述衬底的一侧设置所述第二子绝缘材料层。
  20. 根据权利要求17所述的方法，其中，所述信号线包括第一子层和第二子层，所述第一子层位于所述第一绝缘层背离所述衬底的一侧，所述第二子层位于所述第一子层背离所述第一绝缘层的一侧，所述第二子层的材料包括铜，
    在所述第一绝缘层背离所述衬底的一侧设置第一金属材料层，对所述金属材料层进行图案化处理形成包括信号线的第一金属层的步骤中：
    在所述第一绝缘层背离所述衬底的一侧溅镀形成第一子材料层；
    在所述第一子材料层上设置第二子材料层，所述第一子材料层和所述第二子材料层形成所述第一金属材料层，所述第二子材料层包括铜材料；
    利用湿刻蚀对所述第一子材料层和所述第二子材料层进行图案化处理形成所述信号线，所述第一子材料层形成所述第一子层，所述第二子材料层形成所述第二子层。
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