WO2024040565A1 - 封装基板及其制备方法和功能基板及其制备方法 - Google Patents

封装基板及其制备方法和功能基板及其制备方法 Download PDF

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Publication number
WO2024040565A1
WO2024040565A1 PCT/CN2022/115096 CN2022115096W WO2024040565A1 WO 2024040565 A1 WO2024040565 A1 WO 2024040565A1 CN 2022115096 W CN2022115096 W CN 2022115096W WO 2024040565 A1 WO2024040565 A1 WO 2024040565A1
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Prior art keywords
substrate
signal trace
electrically connected
chip
away
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PCT/CN2022/115096
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English (en)
French (fr)
Inventor
张敬书
吴艺凡
徐帅
李月
肖月磊
赵斌
韩基挏
冯昱霖
安齐昌
王子健
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to PCT/CN2022/115096 priority Critical patent/WO2024040565A1/zh
Publication of WO2024040565A1 publication Critical patent/WO2024040565A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

Definitions

  • the present disclosure belongs to the field of packaging technology, and specifically relates to a packaging substrate and its preparation method and a functional substrate and its preparation method.
  • Packaging plays a pillar role in the development of semiconductor technology.
  • Semiconductor packaging technology is the method, structure, and process of encapsulating semiconductor (integrated circuit) chips in a certain standard component.
  • packaging technology has gradually developed from two-dimensional packaging to three-dimensional packaging in the 21st century.
  • the substrate's main function is to carry the chip, provide structural support, transmit signals, and amplify pin size. , enhance heat dissipation, etc., and vertical interconnection technology based on substrate through holes is the focus of advanced three-dimensional packaging research.
  • common commercial packaging substrates mainly include organic substrates, ceramic substrates, metal substrates and some composite substrates.
  • a common problem is that organic substrates cannot prepare fine vias, and metal substrates cannot be used in high-frequency signal transmission due to high radio frequency losses.
  • ceramic substrates are potential materials for packaging substrates, but they also have problems such as insufficient fine wiring and high processing costs.
  • Some currently commonly used composite substrates have higher costs and greater technical difficulties, and are in a monopoly position in the industry. It is not conducive to further expansion of the market.
  • glass-based devices have begun to emerge in the field of microelectronics manufacturing.
  • As a substrate material for packaging glass has many inherent advantages: good insulation, low dielectric loss, and excellent surface flatness. , low material cost, high chemical stability, good thermal expansion coefficient (CTE) matching with chips and printed circuit boards, etc., it is a relatively promising substrate material in the industry. But the biggest problem is that glass is a brittle material, especially when it is thinned to less than a hundred microns. Glass is directly used as a packaging substrate in the reflow soldering, molding and other temperature and pressure processes of chip packaging, and there is a risk of fragmentation.
  • CTE thermal expansion coefficient
  • the present invention aims to solve at least one of the technical problems existing in the prior art and provide a packaging substrate and a preparation method thereof and a functional substrate and a preparation method thereof.
  • An embodiment of the present disclosure provides a method for preparing a packaging substrate, which includes:
  • the initial substrate includes a first surface and a second surface that are oppositely arranged along its thickness direction; the initial substrate includes a glass base;
  • a first connection electrode is formed in the blind hole, and a first signal trace is formed on the first surface, and one end of the first signal trace is electrically connected to the first connection electrode;
  • a second signal trace is formed on a side of the dielectric substrate away from the first signal trace; one of the first signal trace and the second signal trace is configured to be electrically connected to the chip , the other is configured to be electrically connected to the printed circuit board.
  • the step of thinning the second surface side of the initial substrate to form a dielectric substrate and exposing the first connection electrode includes:
  • the method further includes:
  • the carrier substrate is removed.
  • the method further includes:
  • a chip is installed on the side of the first signal trace away from the dielectric substrate, and the chip is electrically connected to the first signal trace;
  • the chip and the first signal trace are electrically connected by soldering.
  • the auxiliary substrate is fixed on a side of the first adhesive layer and the second signal trace away from the dielectric substrate.
  • the carrier substrate is fixed to a side of the first signal trace away from the first surface through a second adhesive layer.
  • the step of thinning the second surface side of the initial substrate, forming a dielectric substrate, and exposing the first connection electrode it also includes:
  • a chip is installed on a side of the first signal trace away from the first surface, and the chip is electrically connected to the first signal trace.
  • the step of thinning the second surface side of the initial substrate, forming a dielectric substrate, and exposing the first connection electrode it also includes:
  • the method further includes:
  • the chip is installed on the side of the second trace away from the dielectric substrate, and the chip is electrically connected to the second trace;
  • the auxiliary substrate is fixed to a side of the first signal trace away from the first surface through a first adhesive layer.
  • One end of the first signal trace is connected to the first connection electrode, and a first connection pad is formed on the other end of the first signal trace away from the dielectric substrate.
  • One end of the second signal trace is connected to the first connection electrode, and a second connection pad is formed on the other end of the second signal trace away from the dielectric substrate.
  • the first connection electrode is formed by electroplating process or chemical plating process.
  • An embodiment of the present disclosure provides a packaging substrate, which includes:
  • the dielectric substrate has a through hole penetrating along its thickness direction; the dielectric substrate is a glass base;
  • a first connection electrode is provided in the through hole
  • the first signal trace and the second signal trace are respectively provided on two opposite sides of the dielectric board substrate, and the first signal trace and the second signal trace are electrically connected through the first connection electrode. connect;
  • one of the first signal trace and the second signal trace is configured to be electrically connected to the chip, and the other is configured to be electrically connected to the printed circuit board.
  • the packaging substrate further includes a chip; the chip is electrically connected to the first signal line, and a packaging layer is provided on a side of the chip away from the dielectric substrate.
  • one end of the first signal trace is electrically connected to the first connection electrode, and the other end is electrically connected to the first connection pad.
  • the first connection pad is disposed on a side of the first signal trace away from the dielectric substrate. side.
  • one end of the second signal trace is electrically connected to the first connection electrode, and the other end is electrically connected to the second connection pad.
  • the second connection pad is provided on a side of the second signal trace away from the dielectric substrate. side.
  • Embodiments of the present disclosure provide a method for preparing a functional substrate, which includes the method for preparing a packaging substrate described in any one of the above.
  • the preparation method further includes:
  • the preparation method further includes:
  • the first signal trace is electrically connected to the printed circuit board.
  • the step of electrically connecting the second signal trace to the printed circuit board includes:
  • the second signal trace is electrically connected to the printed circuit board by soldering.
  • the step of electrically connecting the first signal trace to the printed circuit board includes:
  • the first signal trace is electrically connected to the printed circuit board by soldering.
  • Embodiments of the present disclosure provide a functional substrate, which includes any of the above-mentioned packaging substrates; wherein one of the first signal trace and the second signal trace is electrically connected to the chip, and the other Electrically connected to the printed circuit board.
  • FIG. 1 is a schematic structural diagram of a packaging substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a functional substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a flow chart of a method for preparing a packaging substrate according to a first example of an embodiment of the present disclosure.
  • FIG. 4 is a flow chart of a method for preparing a packaging substrate according to a second example of an embodiment of the present disclosure.
  • FIG. 5 is a flow chart of a method for preparing a packaging substrate according to a third example of an embodiment of the present disclosure.
  • Figure 1 is a schematic structural diagram of a packaging substrate according to an embodiment of the present disclosure; as shown in Figure 1, the packaging substrate includes a dielectric substrate 10, a first signal trace 11, a second signal trace 12, a first connection electrode 13, and a chip 14 and encapsulation layer 15. Among them, the dielectric substrate 11 has a through hole penetrating along its thickness direction. The first connection electrode 13 is filled in the through hole. The first signal trace 11 and the second signal trace 12 are respectively located on both sides of the dielectric substrate 10 along its thickness direction. On opposite sides, the first signal trace 11 and the second signal trace 12 are electrically connected through the first connection electrode 13 .
  • the chip 14 is connected to the first signal trace 11 , and the side of the chip 14 away from the first signal trace 11 is covered with an encapsulation layer 15 .
  • a first insulating layer 18 is also provided on the side of the first signal trace 11 away from the dielectric substrate 10 .
  • the first insulating layer 18 has a first via hole that exposes the electrical connection position between the first signal trace 11 and the chip 14 .
  • a second insulating layer 19 is also provided on the side of the second signal trace 12 away from the dielectric substrate 10 .
  • the first insulating layer 19 has a second via hole that exposes the electrical connection position between the second signal trace 12 and the printed circuit board.
  • the dielectric substrate 10 in the embodiment of the present disclosure adopts a glass base.
  • the glass base has small dielectric loss and has good application prospects in the high-frequency field.
  • the chip 14 and the first signal trace 11 may be connected together by welding. Therefore, a first connection pad 16 is formed at one end of the first signal trace 11 that is electrically connected to the chip 14, and the first connection pad 16 is formed. The connection pad 16 is welded to the chip 14 to realize the electrical connection between the first signal trace 11 and the chip 14 . Furthermore, tin balls or copper pillars can be used for soldering.
  • a second connection pad 17 may be formed at one end of the second signal trace 12 that is electrically connected to the printed circuit board 20 , and the second connection pad 17 may be soldered to the printed circuit board 20 to realize the second signal trace.
  • Wire 12 is electrically connected to the printed circuit board 20 .
  • tin balls or copper pillars can be used for soldering.
  • FIG 2 is a schematic structural diagram of a functional substrate according to an embodiment of the present disclosure; as shown in Figure 2, an embodiment of the present disclosure provides a functional substrate, which includes the above-mentioned packaging substrate and a printed circuit board connected to the second signal trace 12 20, thereby realizing the electrical connection between the chip 14 and the printed circuit board 20.
  • the second signal trace 12 and the printed circuit board 20 may be electrically connected by soldering.
  • a second connection pad 17 can be formed on one end of the second signal trace 12 that is electrically connected to the printed circuit board 20, and the second connection pad 17 is welded to the printed circuit board 20 to realize the second signal.
  • the traces 12 are electrically connected to the printed circuit board 20 .
  • tin balls or copper pillars can be used for soldering.
  • the thickness of the dielectric substrate 10 will be reduced. However, when the thickness of the dielectric substrate 10 is reduced to a certain level, there may be a risk of debris during processing.
  • embodiments of the present disclosure provide a method for preparing a packaging substrate, which can effectively avoid the problem of debris during processing. Detailed description will be given with reference to examples.
  • An embodiment of the present disclosure provides a method for preparing a packaging substrate, which includes the following steps:
  • S01 Provide an initial substrate; wherein the initial substrate includes a first surface and a second surface oppositely arranged along its thickness direction.
  • the starting substrate includes, but is not limited to, a glass substrate.
  • the initial substrate is taken as an example of a glass base.
  • the glass-based dielectric loss is small and has good application prospects in the high-frequency field.
  • S02. Process the initial substrate to form a blind hole that penetrates part of the initial substrate in the thickness direction of the initial substrate, and the first opening of the blind hole penetrates the first surface.
  • step S02 may include using processes such as mechanical, laser, chemical etching, laser modification combined with wet etching, etc. to form a blind hole that extends through a partial thickness of the initial substrate.
  • a first insulating layer is formed on one side of the substrate.
  • the first insulating layer has a first via hole, and the first via hole exposes one end of the first signal line connected to the chip.
  • step S03 may include coating the blind hole and the first surface of the initial substrate with a first conductive film, that is, forming a first seed layer, and then performing electroplating or electroless plating to form the first seed layer.
  • a long and thick first connection electrode is formed in the blind hole, and then the long and thick first seed layer on the first surface is patterned (ie, glued, exposed, developed, etched) to form a first signal including Trace graphics.
  • a first insulating layer is formed on a side of the first signal line away from the original substrate, and a first via hole is formed through the first insulating layer. The first via hole exposes one end of the first signal line connected to the chip.
  • step S04 may include thinning the second surface side of the initial substrate, and then polishing with a CMP process to reduce the roughness and expose the first connection electrode. That is to say, a through hole penetrating the dielectric substrate is formed in step S04.
  • S05 Form a second signal line on the side of the dielectric substrate away from the first signal line, and have one end of the second signal line electrically connected to the first connection electrode, and form a second signal line on the side of the dielectric substrate away from the dielectric substrate.
  • the second insulation layer has a second via hole, and the second via hole exposes one end of the second signal trace connected to the printed circuit board.
  • step S05 may include forming a second conductive film on a side of the dielectric substrate facing away from the first signal trace, and coating a photoresist on a side of the second conductive film facing away from the dielectric substrate, and then performing exposure. Develop and etch to form a pattern including the second signal trace. Finally, a second insulating layer is formed on a side of the second signal line facing away from the dielectric substrate, and a second via hole is formed through the second insulating layer. The second via hole exposes one end of the second signal line connected to the printed circuit board.
  • one of the first signal trace and the second signal trace is electrically connected to the subsequent chip to be installed, and the other is electrically connected to the printed circuit board.
  • Figure 3 is a flow chart of a method for preparing a packaging substrate according to the first example of the embodiment of the present disclosure; as shown in Figure 3, the first signal trace 11 in the packaging substrate is electrically connected to the chip 14, The second signal trace 12 is electrically connected to the printed circuit board 20 .
  • the preparation method of the packaging substrate specifically includes the following steps:
  • the initial substrate 100 includes a first surface and a second surface oppositely arranged along its thickness direction.
  • the initial substrate 100 includes, but is not limited to, a glass substrate.
  • the initial substrate 100 is based on glass as an example. Glass-based materials have low energy loss and have good application prospects in high-frequency fields.
  • S12 Process the initial substrate 100 to form a blind hole 101 that penetrates part of the initial substrate 100 in the thickness direction of the initial substrate 100, and the first opening of the blind hole 101 penetrates the first surface.
  • step S12 may include using processes such as mechanical, laser, chemical etching, laser modification and wet etching to form blind holes 101 that penetrate part of the thickness of the initial substrate 100 .
  • first connection electrode 13 located in the blind hole 101, the first signal trace 11 located on the first surface of the initial substrate 100, and one end of the first signal trace 11 is electrically connected to the first connection electrode 13, and A first insulating layer 18 is formed on the side of the first signal line away from the initial substrate 100 .
  • the first insulating layer 18 has a first via hole, and the first via hole exposes one end of the first signal line 11 connected to the chip 14 .
  • step S13 may include coating the blind hole 101 and the first surface of the initial substrate 100 with a first conductive film, that is, forming a first seed layer, and then performing electroplating or electroless plating to make the first
  • the seed layer is grown thick to form the first connection electrode 13 located in the blind hole 101, and then the long and thick first seed layer on the first surface is patterned (ie, glued, exposed, developed, etched) to form A pattern of first signal trace 11 is included.
  • the first insulating layer 18 is formed on the side of the first signal line away from the initial substrate 100 , and a first via hole is formed through the first insulating layer 18 .
  • the first via hole exposes the first signal trace 11 and is connected to the chip 14 one end.
  • carrier substrate 200 includes, but is not limited to, carrier glass.
  • the carrier substrate 200 may be fixed on the side of the first signal trace 11 away from the first surface of the original substrate 100 through the second adhesive layer 201 .
  • the second adhesive layer 201 includes but is not limited to temperature control glue.
  • the carrier substrate 200 is attached to the initial substrate 100 through temperature-controlled glue before thinning the initial substrate 100, which can play a role in temporary reinforcement and protection.
  • step S15 may include thinning the second surface side of the initial substrate 100 and then polishing it using a CMP process to reduce the roughness and expose the first connection electrode 13 . That is to say, a through hole penetrating the dielectric substrate 10 is formed in step S15.
  • a second insulating layer 19 is formed on one side of the substrate 10 .
  • the second insulating layer 19 has a second via hole. The second via hole exposes one end of the second signal trace 12 connected to the printed circuit board 20 .
  • step S16 may include forming a second conductive film on a side of the dielectric substrate 10 facing away from the first signal trace 11 , and coating a photoresist on a side of the second conductive film facing away from the dielectric substrate 10 , and then Exposure, development, and etching are performed to form a pattern including the second signal trace 12 . Finally, a second insulating layer 19 is formed on the side of the second signal line facing away from the dielectric substrate 10, and a second via hole is formed through the second insulating layer 19. The second via hole exposes the second signal trace 12 and the printed circuit board. 20 connect one end.
  • the auxiliary substrate 300 serves as a reinforcing plate.
  • the auxiliary substrate 300 can be made of double-sided copper-plated glass, or can be made of other materials such as stainless steel.
  • the first adhesive layer 301 may be used to fix the auxiliary substrate 300 on the side of the second signal trace 12 away from the dielectric substrate 10 .
  • the first adhesive layer 301 includes but is not limited to bonding glue, and the bonding glue may specifically be temperature-control glue. For example: bonding glue bonded at 200°C and temperature-controlled glue debonded at 200°C.
  • fixing the reinforcing plate before installing the chip 14 can effectively increase the strength of the dielectric substrate 10 and reduce the risk of debris.
  • the first signal trace 11 and the chip 14 may be electrically connected together by soldering in step S18.
  • a first connection pad 16 is formed on one end of the first signal trace 11 connected to the chip 14, and then the first connection pad 16 and the chip 14 are soldered and connected through solder balls or copper pillars, thereby realizing the first signal trace. 11 electrical connection to chip 14. in.
  • the first connection pad 16 may be nickel-gold.
  • the encapsulation layer 15 may be plastic encapsulation material.
  • the second connection pad 17 is formed at one end of the second signal trace 12 connected to the printed circuit board 20, and then the second connection pad 17 and the printed circuit board 20 are soldered and connected through solder balls or copper pillars, thereby realizing the second connection pad 17.
  • the two signal traces 12 are electrically connected to the printed circuit board 20 .
  • the second connection pad 17 may be made of nickel gold.
  • inventions of the present disclosure also provide a method for preparing a functional substrate.
  • the method for preparing the functional substrate includes the above-mentioned step of forming a packaging substrate.
  • the method for preparing the functional substrate further includes: 2. The step of electrically connecting the signal trace 12 to the printed circuit board 20.
  • the second signal trace 12 and the printed circuit board 20 may be connected together by soldering. Therefore, the second connection pad 17 is formed at one end of the second signal trace 12 connected to the printed circuit board 20, and then the second connection pad 17 and the printed circuit board 20 are soldered and connected through solder balls or copper pillars, thereby realizing the second connection pad 17.
  • the two signal traces 12 are electrically connected to the printed circuit board 20 . in.
  • the second connection pad 17 may be made of nickel gold.
  • the carrier substrate 200 is attached to the initial substrate 100 through temperature-controlled glue, which can serve as a temporary reinforcement and protection; the patch is fixed before the chip 14 is installed.
  • the strong board can effectively increase the strength of the dielectric substrate 10 and reduce the risk of fragments.
  • Figure 4 is a flow chart of a method for preparing a packaging substrate according to the second example of the embodiment of the present disclosure; as shown in Figure 4, the first signal trace 11 in the packaging substrate is electrically connected to the chip 14, The second signal trace 12 is electrically connected to the printed circuit board 20 .
  • the preparation method of the packaging substrate specifically includes the following steps:
  • the initial substrate 100 includes a first surface and a second surface oppositely arranged along its thickness direction.
  • the initial substrate 100 includes, but is not limited to, a glass substrate.
  • the initial substrate 100 is based on glass as an example. Glass-based materials have low energy loss and have good application prospects in high-frequency fields.
  • step S22 may include using processes such as mechanical, laser, chemical etching, laser modification and wet etching to form blind holes 101 that penetrate part of the thickness of the initial substrate 100 .
  • first connection electrode 13 located in the blind hole 101, the first signal trace 11 located on the first surface of the initial substrate 100, and one end of the first signal trace 11 is electrically connected to the first connection electrode 13, and A first insulating layer 18 is formed on the side of the first signal line away from the initial substrate 100 .
  • the first insulating layer 18 has a first via hole, and the first via hole exposes one end of the first signal line 11 connected to the chip 14 .
  • step S23 may include coating the blind hole 101 and the first surface of the initial substrate 100 with a first conductive film, that is, forming a first seed layer, and then performing electroplating or electroless plating to make the first
  • the seed layer is grown thick to form the first connection electrode 13 located in the blind hole 101, and then the long and thick first seed layer on the first surface is patterned (ie, glued, exposed, developed, etched) to form A pattern of first signal trace 11 is included.
  • the first insulating layer 18 is formed on the side of the first signal line away from the initial substrate 100 , and a first via hole is formed through the first insulating layer 18 .
  • the first via hole exposes the first signal trace 11 and is connected to the chip 14 one end.
  • the first signal trace 11 and the chip 14 may be electrically connected together by soldering in step S24.
  • a first connection pad 16 is formed on one end of the first signal trace 11 connected to the chip 14, and then the first connection pad 16 and the chip 14 are soldered and connected through solder balls or copper pillars, thereby realizing the first signal trace. 11 electrical connection to chip 14. in.
  • the first connection pad 16 may be nickel-gold.
  • the encapsulation layer 15 may be plastic encapsulation material.
  • step S25 may include thinning the second surface side of the initial substrate 100, and then polishing using a CMP process to reduce the roughness and expose the first connection electrode 13. That is to say, in step S25, a through hole penetrating the dielectric substrate 10 is formed.
  • a second insulating layer 19 is formed on one side of the substrate 10 .
  • the second insulating layer 19 has a second via hole. The second via hole exposes one end of the second signal trace 12 connected to the printed circuit board 20 .
  • step S26 may include forming a second conductive film on a side of the dielectric substrate 10 facing away from the first signal trace 11 , and coating a photoresist on a side of the second conductive film facing away from the dielectric substrate 10 , and then Exposure, development, and etching are performed to form a pattern including the second signal trace 12 . Finally, a second insulating layer 19 is formed on the side of the second signal line facing away from the dielectric substrate 10, and a second via hole is formed through the second insulating layer 19. The second via hole exposes the second signal trace 12 and the printed circuit board. 20 connect one end.
  • the second connection pad 17 is formed at one end of the second signal trace 12 connected to the printed circuit board 20, and then the second connection pad 17 and the printed circuit board 20 are soldered and connected through solder balls or copper pillars, thereby realizing the second connection pad 17.
  • the two signal traces 12 are electrically connected to the printed circuit board 20 .
  • the second connection pad 17 may be made of nickel gold.
  • inventions of the present disclosure also provide a method for preparing a functional substrate.
  • the method for preparing the functional substrate includes the above-mentioned step of forming a packaging substrate.
  • the method for preparing the functional substrate further includes: 2. The step of electrically connecting the signal trace 12 to the printed circuit board 20.
  • the second signal trace 12 and the printed circuit board 20 may be connected together by soldering. Therefore, the second connection pad 17 is formed at one end of the second signal trace 12 connected to the printed circuit board 20, and then the second connection pad 17 and the printed circuit board 20 are soldered and connected through solder balls or copper pillars, thereby realizing the second connection pad 17.
  • the two signal traces 12 are electrically connected to the printed circuit board 20 . in.
  • the second connection pad 17 may be made of nickel gold.
  • the encapsulated chip 14 is used as a reinforcing plate. There is no need to add additional reinforcing plates in this preparation method, which greatly simplifies the process.
  • the plastic packaging material has greater mechanical lightness and strength, which is more conducive to the entire crystallization process. Round-level processing effectively improves warpage and other problems.
  • Figure 5 is a flow chart of a method for preparing a packaging substrate according to the third example of the embodiment of the present disclosure; as shown in Figure 5, the first signal trace 11 in the packaging substrate is electrically connected to the printed circuit board 20 connection, the second signal trace 12 is electrically connected to the chip 14 .
  • the preparation method of the packaging substrate specifically includes the following steps:
  • the initial substrate 100 includes a first surface and a second surface oppositely arranged along its thickness direction.
  • the initial substrate 100 includes, but is not limited to, a glass substrate.
  • the initial substrate 100 is based on glass as an example. Glass-based materials have low energy loss and have good application prospects in high-frequency fields.
  • S32 Process the initial substrate 100 to form a blind hole 101 that penetrates part of the initial substrate 100 in the thickness direction of the initial substrate 100, and the first opening of the blind hole 101 penetrates the first surface.
  • step S32 may include using processes such as mechanical, laser, chemical etching, laser modification and wet etching to form blind holes 101 that penetrate part of the thickness of the initial substrate 100 .
  • first connection electrode 13 located in the blind hole 101, the first signal trace 11 located on the first surface of the initial substrate 100, and one end of the first signal trace 11 is electrically connected to the first connection electrode 13, and A first insulating layer 18 is formed on the side of the first signal line away from the initial substrate 100 .
  • the first insulating layer 18 has a first via hole, and the first via hole exposes one end of the first signal line 11 connected to the chip 14 .
  • step S33 may include coating the blind hole 101 and the first surface of the initial substrate 100 with a first conductive film, that is, forming a first seed layer, and then performing electroplating or electroless plating to make the first
  • the seed layer is grown thick to form the first connection electrode 13 located in the blind hole 101, and then the long and thick first seed layer on the first surface is patterned (ie, glued, exposed, developed, etched) to form A pattern of first signal trace 11 is included.
  • the first insulating layer 18 is formed on the side of the first signal line away from the initial substrate 100 , and a first via hole is formed through the first insulating layer 18 .
  • the first via hole exposes the first signal trace 11 and is connected to the chip 14 one end.
  • the auxiliary substrate 300 serves as a reinforcing plate.
  • the auxiliary substrate 300 can be made of double-sided copper-plated glass, or can be made of other materials such as stainless steel.
  • the first adhesive layer 301 may be used to fix the auxiliary substrate 300 on the side of the first signal trace 11 away from the dielectric substrate 10 .
  • the first adhesive layer 301 includes but is not limited to bonding glue, and the bonding glue may specifically be temperature-control glue. For example: bonding glue bonded at 200°C and temperature-controlled glue debonded at 200°C.
  • fixing the reinforcing plate before installing the chip 14 can effectively increase the strength of the dielectric substrate 10 and reduce the risk of debris.
  • step S35 may include thinning the second surface side of the initial substrate 100, and then polishing using a CMP process to reduce the roughness and expose the first connection electrode 13. That is to say, a through hole penetrating the dielectric substrate 10 is formed in step S35.
  • a second insulating layer 19 is formed on one side of the substrate 10 .
  • the second insulating layer 19 has a second via hole. The second via hole exposes one end of the second signal trace 12 connected to the printed circuit board 20 .
  • step S36 may include forming a second conductive film on a side of the dielectric substrate 10 facing away from the first signal trace 11 , and coating a photoresist on a side of the second conductive film facing away from the dielectric substrate 10 , and then Exposure, development, and etching are performed to form a pattern including the second signal trace 12 . Finally, a second insulating layer 19 is formed on the side of the second signal line facing away from the dielectric substrate 10, and a second via hole is formed through the second insulating layer 19. The second via hole exposes the second signal trace 12 and the printed circuit board. 20 connect one end.
  • the second signal trace 12 and the chip 14 may be electrically connected together by soldering in step S37.
  • a first connection pad 16 is formed on one end of the second signal trace 12 connected to the chip 14, and then the first connection pad 16 and the chip 14 are soldered and connected through solder balls or copper pillars, thereby realizing the second signal trace. 12 electrical connection to chip 14. in.
  • the first connection pad 16 may be nickel-gold.
  • the encapsulation layer 15 may be plastic encapsulation material.
  • the second connection pad 17 is formed at one end of the first signal trace 11 connected to the printed circuit board 20, and then the second connection pad 17 and the printed circuit board 20 are soldered and connected through solder balls or copper pillars, thereby realizing the second connection pad 17.
  • a signal trace 11 is electrically connected to the printed circuit board 20 . in.
  • the second connection pad 17 may be made of nickel gold.
  • inventions of the present disclosure also provide a method for preparing a functional substrate.
  • the method for preparing the functional substrate includes the above-mentioned step of forming a packaging substrate.
  • the method for preparing the functional substrate further includes: A step of electrically connecting the signal trace 11 to the printed circuit board 20.
  • the first signal trace 11 and the printed circuit board 20 may be connected together by soldering. Therefore, the second connection pad 17 is formed at one end of the first signal trace 11 connected to the printed circuit board 20, and then the second connection pad 17 and the printed circuit board 20 are soldered and connected through solder balls or copper pillars, thereby realizing the second connection pad 17.
  • a signal trace 11 is electrically connected to the printed circuit board 20 . in.
  • the second connection pad 17 may be made of nickel gold.
  • the preparation method only needs to add a reinforcing plate once.
  • the reinforcing plate can play a role in temporary protection and reinforcement during the thinning process, and can also play a supplementary role in the process of packaging the chip 14. Strong effect.

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Abstract

一种封装基板及其制备方法和功能基板及其制备方法。封装基板的制备方法包括：提供一初始基板（100）；初始基板（100）包括沿其厚度方向相对设置的第一表面和第二表面；对初始基板（100）进行处理，形成在初始基板（100）厚度方向上贯穿部分初始基板（100）的盲孔（101），且盲孔（101）的第一开口贯穿第一表面：在盲孔（101）内形成第一连接电极（13），以及在第一表面形成第一信号走线（11），且第一信号走线（11）的一端与第一连接电极（13）电连接；对初始基板（100）的第二表面侧进行减薄，形成介质基板（10），并裸露第一连接电极（13）；在介质基板（10）背离第一信号走线（11）的一侧形成第二信号走线（12）；第一信号走线（11）和第二信号走线（12）中的一者被配置与芯片（14）电连接，另一被配置为与印刷电路板（20）电连接。

Description

封装基板及其制备方法和功能基板及其制备方法 技术领域
本公开属于封装技术领域，具体涉及一种封装基板及其制备方法和功能基板及其制备方法。
背景技术
封装在半导体技术发展中起着支柱性的作用，半导体封装技术是将半导体(集成电路)芯片包封在某一种标准组件中的方法、结构、工艺。随着封装技术的不断发展，21世纪以来封装技术逐渐从二维封装向三维封装发展，基板作为三维模块化封装的重要部件，主要作用是承载芯片，起结构支撑、传递信号、管脚尺寸放大、加强散热等的作用，而基于基板通孔的垂直互连技术更是先进三维封装研究的焦点。目前，商业常见的封装基板主要有有机基板、陶瓷基板、金属基板和一些复合基板，普遍问题是有机基板无法进行精细化过孔的制备，金属基板因射频损耗较高无法应用在高频信号传输领域，陶瓷基板是作为封装基板的潜力材料，但也有着精细化走线程度不够以及加工成本较高等问题，而一些目前普遍应用的复合基板成本较高、技术难度较大，处于行业垄断地位，不利于市场的进一步拓展。
随着玻璃加工技术的快速发展，玻璃基器件开始在微电子制造领域崭露头角，玻璃作为封装的基板材料，有着其固有的许多优势：良好的绝缘性、低的介电损耗、优异的表面平整度、低廉的材料成本、高的化学稳定性、热膨胀系数(CTE)与芯片及印刷电路板匹配性好等，是业内目前比较看好的基板材料。但最大问题是玻璃是脆性材料，特别是减薄到百微米以下，玻璃直接作为封装基板在芯片封装的回流焊、molding等温压工序有发生碎片的风险。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种封装基板及其制备方法和功能基板及其制备方法。
本公开实施例一种封装基板的制备方法，其包括：
提供一初始基板；所述初始基板包括沿其厚度方向相对设置的第一表面和第二表面；所述初始基板包括玻璃基；
对所述初始基板进行处理，形成在所述初始基板厚度方向上贯穿部分所述初始基板的盲孔，且所述盲孔的第一开口贯穿所述第一表面；
在所述盲孔内形成第一连接电极，以及在所述第一表面形成第一信号走线，且所述第一信号走线的一端与所述第一连接电极电连接；
对所述初始基板的第二表面侧进行减薄，形成具有通孔的介质基板，并裸露所述第一连接电极；
在所述介质基板背离所述第一信号走线的一侧形成第二信号走线；所述第一信号走线和所述第二信号走线中的一者被配置与所述芯片电连接，另一者被配置为与所述印刷电路板电连接。
其中，所述对所述初始基板的第二表面侧进行减薄，形成介质基板，并裸露所述第一连接电极的步骤包括：
在所述第一信号走线背离所述第一表面的一侧固定载体基板；
对所述所述初始基板的第二表面侧进行减薄，形成介质基板，并裸露所述第一连接电极；
在所述在所述介质基板背离所述第一信号走线的一侧形成第二信号走线的步骤之前，还包括：
将所述载板基板去除。
其中，在所述介质基板背离所述第一信号走线的一侧形成第二信号走线的步骤之后，还包括：
在所述第二信号走线背离所述介质基板的一侧固定辅助基板；
在所述第一信号走线背离所述介质基板的一侧安装芯片，所述芯片与所述第一信号走线电连接；
在所述芯片背离所述介质基板的一侧形成封装层；
去除所述辅助基板。
其中，所述芯片与所述第一信号走线采用焊接的方式电连接。
其中，所述辅助基板通过第一粘合层与所述第二信号走线背离所述介质基板的一侧固定。
其中，所述载板基板通过第二粘合层与所述第一信号走线背离所述第一表面的一侧固定。
其中，在所述对所述初始基板的第二表面侧进行减薄，形成介质基板，并裸露所述第一连接电极的步骤之前，还包括：
在所述第一信号走线背离所述第一表面的一侧安装芯片，所述芯片与所述第一信号走线电连接。
其中，在所述对所述初始基板的第二表面侧进行减薄，形成介质基板，并裸露所述第一连接电极的步骤之前，还包括：
在所述第一信号走线背离第一表面的一侧固定辅助基板；
对所述所述初始基板的第二表面侧进行减薄，形成介质基板，并裸露所述第一连接电极；
在所述在所述介质基板背离所述第一信号走线的一侧形成第二信号走线的步骤之后，还包括：
在所述第二走线背离所述介质基板的一侧安装所述芯片，所述芯片与所述第二走线电连接；
去除所述辅助基板。
其中，所述辅助基板通过第一粘合层与所述第一信号走线背离第一表面的一侧固定。
其中，所述第一信号走线的一端与所述第一连接电极连接，所述第一信号走线的另一端背离所述介质基板的一侧形成有第一连接焊盘。
所述第二信号走线的一端与所述第一连接电极连接，所述第二信号走线的另一端背离所述介质基板的一侧形成有第二连接焊盘。
其中，所述第一连接电极采用电镀工艺或者化学镀工艺形成。
本公开实施例提供一种封装基板，其包括：
介质基板，具有沿其厚度方向贯穿的通孔；所述介质基板为玻璃基；
第一连接电极，设置在所述通孔内；
第一信号走线和第二信号走线，分别设置在所述介质板基板的两相对侧面上，且所述第一信号走线和所述第二信号走线通过所述第一连接电极电连接；
其中，所述第一信号走线和所述第二信号走线中的一者被配置与所述芯片电连接，另一者被配置为与所述印刷电路板电连接。
其中，所述封装基板还包括芯片；所述芯片与所述第一信号走线电连接，且在所述芯片背离所述介质基板的一侧设置有封装层。
其中，所述第一信号走线一端电连接第一连接电极，另一端电连接第一连接焊盘，所述第一连接焊盘设置在所述第一信号走线背离所述介质基板的一侧。
其中，所述第二信号走线一端电连接第一连接电极，另一端电连接第二连接焊盘，所述第二连接焊盘设置在所述第二信号走线背离所述介质基板的一侧。
本公开实施例提供一种功能基板的制备方法，其包括上述任一项所述的封装基板的制备方法。
其中，当所述第一信号走线与所述芯片电连接时，所述制备方法还包括：
将所述第二信号走线与印刷电路板电连接；
当所述第二信号走线与所述芯片电连接时，所述制备方法还包括：
将所述第一信号走线与印刷电路板电连接。
其中，所述将所述第二信号走线与印刷电路板电连接的步骤，包括：
将所述第二信号走线与所述印刷电路板采用焊接的方式电连接。
其中，将所述第一信号走线与印刷电路板电连接的步骤，包括：
将所述第一信号走线与所述印刷电路板采用焊接的方式电连接。
本公开实施例提供一种功能基板，其包括上述任一所述的封装基板；其中，所述第一信号走线和所述第二信号走线中的一者与芯片电连接，另一者与印刷电路板电连接。
附图说明
图1为本公开实施例的封装基板的结构示意图。
图2为本公开实施例的功能基板的结构示意图。
图3为本公开实施例的第一种示例的封装基板的制备方法的流程图。
图4为本公开实施例的第二种示例的封装基板的制备方法的流程图。
图5为本公开实施例的第三种示例的封装基板的制备方法的流程图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为本公开实施例的封装基板的结构示意图；如图1所示，该封装基板包括介质基板10、第一信号走线11、第二信号走线12、第一连接电极13、芯片14和封装层15。其中，介质基板11具有延其厚度方向贯穿的通孔，第一连接电极13填充在通孔内，第一信号走线11和第二信号走线12分别位于介质基板10沿其厚度方向的两相对侧，且第一信号走线11和第二信号走 线12通过第一连接电极13电连接。芯片14与第一信号走线11连接，且在芯片14背离第一信号走线11的一侧覆盖有封装层15。当然在第一信号走线11背离介质基板10的一侧还设置有第一绝缘层18，第一绝缘层18具有裸露第一信号走线11与芯片14电连接位置的第一过孔。在第二信号走线12背离介质基板10的一侧还设置有第二绝缘层19，第一绝缘层19具有裸露第二信号走线12与印刷电路板电连接位置的第二过孔。
其中，本公开实施例中的介质基板10采用玻璃基，玻璃基的介质损耗小，在高频领域有着较好的应用前景。
在一些示例中，芯片14与第一信号走线11可以通过焊接的方式连接在一起，因此在第一信号走线11与芯片14电连接的一端形成有第一连接焊盘16，将第一连接焊盘16与芯片14焊接，从而实现第一信号走线11与芯片14的电连接。进一步的，焊接时可以采用锡球或者铜柱进行焊接。
在一些示例中，在第二信号走线12与印刷电路板20电连接的一端可以形成第二连接焊盘17，将第二连接焊盘17与印刷电路板20焊接，从而实现第二信号走线12与印刷电路板20的电连接。进一步的，焊接时可以采用锡球或者铜柱进行焊接。
图2为本公开实施例的功能基板的结构示意图；如图2所示，本公开实施例提供一种功能基板，其包括上述的封装基板，以及第二信号走线12所连接的印刷电路板20，从而实现芯片14与印刷电路板20的电连接。其中，第二信号走线12与印刷电路板20之间可以采用焊接的方式实现电连接。在该种情况下，在第二信号走线12与印刷电路板20电连接的一端可以形成第二连接焊盘17，将第二连接焊盘17与印刷电路板20焊接，从而实现第二信号走线12与印刷电路板20的电连接。进一步的，焊接时可以采用锡球或者铜柱进行焊接。
发明人发现为了实现封装基板的轻薄化，因此会将介质基板10的厚度降低，但是在将介质基板10的厚度降低到一定水平时，在加工过程中可能会有碎片的风险。
针对上述问题，在本公开实施例中提供了封装基板的制备方法，从而可以有效的避免在加工过程中出现碎片的问题。具体结合实施例进行说明。
本公开实施例提供一种封装基板的制备方法，其包括如下步骤：
S01、提供一初始基板；其中，初始基板包括沿其厚度方向相对设置的第一表面和第二表面。
在一些示例中，初始基板包括但不限于玻璃基。在本公开实施例已猴子那个初始基板以玻璃基为例。玻璃基的介质损耗小，在高频领域有着较好的应用前景。
S02、对初始基板进行处理，形成在初始基板厚度方向上贯穿部分初始基板的盲孔，且所盲孔的第一开口贯穿所述第一表面。
在一些示例中，步骤S02可以包括采用机械、激光、化学腐蚀、激光改性与湿法刻蚀结合等工艺，形成贯穿初始基板部分厚度的盲孔。
S03、形成位于盲孔内的第一连接电极，位于初始基板第一表面的第一信号走线，且第一信号走线的一端与第一连接电极电连接，以及在第一信号线背离初始基板的一侧形成第一绝缘层，第一绝缘层具有第一过孔，第一过孔裸露第一信号走线与芯片连接的一端。
在一些示例中，步骤S03可以包括对盲孔和初始基板的第一表面进行第一导电薄膜的涂覆，也即也即形成第一种子层，之后进行电镀或者化学镀以使第一种子层长厚，形成位于盲孔中的第一连接电极，之后对第一表面上的长厚的第一种子层进行图案化处理(也即涂胶、曝光、显影、刻蚀)形成包括第一信号走线的图形。最后，在第一信号线背离初始基板的一侧形成第一绝缘层，并形成贯穿第一绝缘层的第一过孔，第一过孔裸露第一信号走线与芯片连接的一端。
S04、对初始基板的第二表面侧进行减薄，形成介质基板，并裸露第一连接电极。
在一些示例中，步骤S04可以包括对初始基板的第二表面侧进行减薄，之后再用CMP工艺抛光降低粗糙度，并裸露第一连接电极。也就是说在步 骤S04中形成贯穿介质基板的通孔。
S05、在介质基板背离第一信号走线的一侧形成第二信号走线，且第二信号走线的一端与第一连接电极电连接，以及在第二信号线背离介质基板的一侧形成第二绝缘层，第二绝缘层具有第二过孔，第二过孔裸露第二信号走线与印刷电路板连接的一端。
在一些示例中，步骤S05可以包括在介质基板背离第一信号走线的一侧形成第二导电薄膜，并在第二导电薄膜背离介质基板的一侧涂覆光刻胶，接下来进行曝光、显影、刻蚀形成包括第二信号走线的图形。最后，在第二信号线背离介质基板的一侧形成第二绝缘层，并形成贯穿第二绝缘层的第二过孔，第二过孔裸露第二信号走线与印刷电路板连接的一端。
需要说明的是，第一信号走线和第二信号走线中的一者与后续的待安装芯片电连接，另一者则与印刷电路板电连接。
以下结合具体示例对本公开实施例的封装基板的制备方法进行说明。
第一种示例：图3为本公开实施例的第一种示例的封装基板的制备方法的流程图；如图3所示，该封装基板中的第一信号走线11与芯片14电连接，第二信号走线12与印刷电路板20电连接。该封装基板的制备方法具体包括如下步骤：
S11、提供一初始基板100；初始基板100包括沿其厚度方向相对设置的第一表面和第二表面。
在一些示例中，初始基板100包括但不限于玻璃基。在本公开实施例已猴子那个初始基板100以玻璃基为例。玻璃基的机智损耗小，在高频领域有着较好的应用前景。
S12、对初始基板100进行处理，形成在初始基板100厚度方向上贯穿部分初始基板100的盲孔101，且所盲孔101的第一开口贯穿所述第一表面。
在一些示例中，步骤S12可以包括采用机械、激光、化学腐蚀、激光改性与湿法刻蚀结合等工艺，形成贯穿初始基板100部分厚度的盲孔101。
S13、形成位于盲孔101内的第一连接电极13，位于初始基板100第一 表面的第一信号走线11，且第一信号走线11的一端与第一连接电极13电连接，以及在第一信号线背离初始基板100的一侧形成第一绝缘层18，第一绝缘层18具有第一过孔，第一过孔裸露第一信号走线11与芯片14连接的一端。
在一些示例中，步骤S13可以包括对盲孔101和初始基板100的第一表面进行第一导电薄膜的涂覆，也即也即形成第一种子层，之后进行电镀或者化学镀以使第一种子层长厚，形成位于盲孔101中的第一连接电极13，之后对第一表面上的长厚的第一种子层进行图案化处理(也即涂胶、曝光、显影、刻蚀)形成包括第一信号走线11的图形。最后，在第一信号线背离初始基板100的一侧形成第一绝缘层18，并形成贯穿第一绝缘层18的第一过孔，第一过孔裸露第一信号走线11与芯片14连接的一端。
S14、在第一信号走线11背离初始基板100的第一表面的一侧固定载体基板200。
在一些示例中，载体基板200包括但不限于载体玻璃。在步骤S14中，可以通过第二粘合层201将载体基板200固定在第一信号走线11背离初始基板100的第一表面的一侧。其中，第二粘合层201包括但不限于温控胶。在本公开实施例中，在对初始基板100进行减薄处理前通过温控胶将载体基板200贴附在初始基板100上，可以起到临时增强和保护的作用。
S15、对初始基板100的第二表面侧进行减薄，形成介质基板10，并裸露第一连接电极13。
在一些示例中，步骤S15可以包括对初始基板100的第二表面侧进行减薄，之后再用CMP工艺抛光降低粗糙度，并裸露第一连接电极13。也就是说在步骤S15中形成贯穿介质基板10的通孔。
S16、在介质基板10背离第一信号走线11的一侧形成第二信号走线12，且第二信号走线12的一端与第一连接电极13电连接，以及在第二信号线背离介质基板10的一侧形成第二绝缘层19，第二绝缘层19具有第二过孔，第二过孔裸露第二信号走线12与印刷电路板20连接的一端。
在一些示例中，步骤S16可以包括在介质基板10背离第一信号走线11的一侧形成第二导电薄膜，并在第二导电薄膜背离介质基板10的一侧涂覆光刻胶，接下来进行曝光、显影、刻蚀形成包括第二信号走线12的图形。最后，在第二信号线背离介质基板10的一侧形成第二绝缘层19，并形成贯穿第二绝缘层19的第二过孔，第二过孔裸露第二信号走线12与印刷电路板20连接的一端。
S17、将载体基板200去除，并在第二信号走线12背离介质基板10的一侧固定辅助基板300。
在一些示例中，辅助基板300作为补强板，辅助基板300可以采用双面镀铜的玻璃基，也可以是不锈钢等其他材料。具体的，在步骤S17中可以采用第一粘合层301将辅助基板300固定在第二信号走线12背离介质基板10的一侧。其中，第一粘合层301包括但不限于键合胶，键合胶具体可以为温控胶。例如：200℃键合的键合胶和200℃解粘的温控胶。
在本公开实施例中，在安装芯片14之前固定补强板，可以有效的增加介质基板10的强度，降低碎片的风险。
S18、在第一信号走线11背离介质基板10的一侧安装芯片14，并在芯片14背离介质基板10的一侧形成封装层15，也即对芯片14进行封装。
在一些示例中，在步骤S18中可以通过焊接的方式将第一信号走线11与芯片14电连接在一起。例如：在第一信号走线11与芯片14连接的一端形成第一连接焊盘16，之后通过锡球或者铜柱将第一连接焊盘16和芯片14焊接连接，从而实现第一信号走线11与芯片14的电连接。其中。第一连接焊盘16可以为化镍金。封装层15可以为塑封料。
S19、将辅助基板300去除。
至此完成封装基板的制备。
其中，由于第二信号走线12后续要与印刷电路板20电连接，而第二信号走线12与印刷电路板20可以采用焊接的方式连接在一起。因此，在第二信号走线12与印刷电路板20连接的一端形成第二连接焊盘17，之后通过 锡球或者铜柱将第二连接焊盘17和印刷电路板20焊接连接，从而实现第二信号走线12与印刷电路板20的电连接。其中。第二连接焊盘17可以为化镍金。
相应的，本公开实施例还提供一种功能基板的制备方法，该功能基板的制备方法包括上述形成封装基板的步骤，该功能基板的制备方法在上述形成封装基板的基础上，还包括将第二信号走线12与印刷电路板20电连接的步骤。
在一些示例中，第二信号走线12与印刷电路板20可以采用焊接的方式连接在一起。因此，在第二信号走线12与印刷电路板20连接的一端形成第二连接焊盘17，之后通过锡球或者铜柱将第二连接焊盘17和印刷电路板20焊接连接，从而实现第二信号走线12与印刷电路板20的电连接。其中。第二连接焊盘17可以为化镍金。
在第一种示例中，在对初始基板100进行减薄处理前通过温控胶将载体基板200贴附在初始基板100上，可以起到临时增强和保护的作用；在安装芯片14之前固定补强板，可以有效的增加介质基板10的强度，降低碎片的风险。
第二种示例：图4为本公开实施例的第二种示例的封装基板的制备方法的流程图；如图4所示，该封装基板中的第一信号走线11与芯片14电连接，第二信号走线12与印刷电路板20电连接。该封装基板的制备方法具体包括如下步骤：
S21、提供一初始基板100；初始基板100包括沿其厚度方向相对设置的第一表面和第二表面。
在一些示例中，初始基板100包括但不限于玻璃基。在本公开实施例已猴子那个初始基板100以玻璃基为例。玻璃基的机智损耗小，在高频领域有着较好的应用前景。
S22、对初始基板100进行处理，形成在初始基板100厚度方向上贯穿部分初始基板100的盲孔101，且所盲孔101的第一开口贯穿所述第一表面。
在一些示例中，步骤S22可以包括采用机械、激光、化学腐蚀、激光改性与湿法刻蚀结合等工艺，形成贯穿初始基板100部分厚度的盲孔101。
S23、形成位于盲孔101内的第一连接电极13，位于初始基板100第一表面的第一信号走线11，且第一信号走线11的一端与第一连接电极13电连接，以及在第一信号线背离初始基板100的一侧形成第一绝缘层18，第一绝缘层18具有第一过孔，第一过孔裸露第一信号走线11与芯片14连接的一端。
在一些示例中，步骤S23可以包括对盲孔101和初始基板100的第一表面进行第一导电薄膜的涂覆，也即也即形成第一种子层，之后进行电镀或者化学镀以使第一种子层长厚，形成位于盲孔101中的第一连接电极13，之后对第一表面上的长厚的第一种子层进行图案化处理(也即涂胶、曝光、显影、刻蚀)形成包括第一信号走线11的图形。最后，在第一信号线背离初始基板100的一侧形成第一绝缘层18，并形成贯穿第一绝缘层18的第一过孔，第一过孔裸露第一信号走线11与芯片14连接的一端。
S24、在第一信号走线11背离介质基板10的一侧安装芯片14，并在芯片14背离介质基板10的一侧形成封装层15，也即对芯片14进行封装。
在一些示例中，在步骤S24中可以通过焊接的方式将第一信号走线11与芯片14电连接在一起。例如：在第一信号走线11与芯片14连接的一端形成第一连接焊盘16，之后通过锡球或者铜柱将第一连接焊盘16和芯片14焊接连接，从而实现第一信号走线11与芯片14的电连接。其中。第一连接焊盘16可以为化镍金。封装层15可以为塑封料。
S25、对初始基板100的第二表面侧进行减薄，形成介质基板10，并裸露第一连接电极13。
在一些示例中，步骤S25可以包括对初始基板100的第二表面侧进行减薄，之后再用CMP工艺抛光降低粗糙度，并裸露第一连接电极13。也就是说在步骤S25中形成贯穿介质基板10的通孔。
S26、在介质基板10背离第一信号走线11的一侧形成第二信号走线12， 且第二信号走线12的一端与第一连接电极13电连接，以及在第二信号线背离介质基板10的一侧形成第二绝缘层19，第二绝缘层19具有第二过孔，第二过孔裸露第二信号走线12与印刷电路板20连接的一端。
在一些示例中，步骤S26可以包括在介质基板10背离第一信号走线11的一侧形成第二导电薄膜，并在第二导电薄膜背离介质基板10的一侧涂覆光刻胶，接下来进行曝光、显影、刻蚀形成包括第二信号走线12的图形。最后，在第二信号线背离介质基板10的一侧形成第二绝缘层19，并形成贯穿第二绝缘层19的第二过孔，第二过孔裸露第二信号走线12与印刷电路板20连接的一端。
至此完成封装基板的制备。
其中，由于第二信号走线12后续要与印刷电路板20电连接，而第二信号走线12与印刷电路板20可以采用焊接的方式连接在一起。因此，在第二信号走线12与印刷电路板20连接的一端形成第二连接焊盘17，之后通过锡球或者铜柱将第二连接焊盘17和印刷电路板20焊接连接，从而实现第二信号走线12与印刷电路板20的电连接。其中。第二连接焊盘17可以为化镍金。
相应的，本公开实施例还提供一种功能基板的制备方法，该功能基板的制备方法包括上述形成封装基板的步骤，该功能基板的制备方法在上述形成封装基板的基础上，还包括将第二信号走线12与印刷电路板20电连接的步骤。
在一些示例中，第二信号走线12与印刷电路板20可以采用焊接的方式连接在一起。因此，在第二信号走线12与印刷电路板20连接的一端形成第二连接焊盘17，之后通过锡球或者铜柱将第二连接焊盘17和印刷电路板20焊接连接，从而实现第二信号走线12与印刷电路板20的电连接。其中。第二连接焊盘17可以为化镍金。
在第二种示例中，通过封装后的芯片14作为补强板，该制备方法中无需额外增加补强板，大大简化了工艺过程，且塑封料的机械轻强度较大，更 有利于全程晶圆级的加工，有效改善翘曲等问题。
第三种示例：图5为本公开实施例的第三种示例的封装基板的制备方法的流程图；如图5所示，该封装基板中的第一信号走线11与印刷电路板20电连接，第二信号走线12与芯片14电连接。该封装基板的制备方法具体包括如下步骤：
S31、提供一初始基板100；初始基板100包括沿其厚度方向相对设置的第一表面和第二表面。
在一些示例中，初始基板100包括但不限于玻璃基。在本公开实施例已猴子那个初始基板100以玻璃基为例。玻璃基的机智损耗小，在高频领域有着较好的应用前景。
S32、对初始基板100进行处理，形成在初始基板100厚度方向上贯穿部分初始基板100的盲孔101，且所盲孔101的第一开口贯穿所述第一表面。
在一些示例中，步骤S32可以包括采用机械、激光、化学腐蚀、激光改性与湿法刻蚀结合等工艺，形成贯穿初始基板100部分厚度的盲孔101。
S33、形成位于盲孔101内的第一连接电极13，位于初始基板100第一表面的第一信号走线11，且第一信号走线11的一端与第一连接电极13电连接，以及在第一信号线背离初始基板100的一侧形成第一绝缘层18，第一绝缘层18具有第一过孔，第一过孔裸露第一信号走线11与芯片14连接的一端。
在一些示例中，步骤S33可以包括对盲孔101和初始基板100的第一表面进行第一导电薄膜的涂覆，也即也即形成第一种子层，之后进行电镀或者化学镀以使第一种子层长厚，形成位于盲孔101中的第一连接电极13，之后对第一表面上的长厚的第一种子层进行图案化处理(也即涂胶、曝光、显影、刻蚀)形成包括第一信号走线11的图形。最后，在第一信号线背离初始基板100的一侧形成第一绝缘层18，并形成贯穿第一绝缘层18的第一过孔，第一过孔裸露第一信号走线11与芯片14连接的一端。
S34、在第一信号走线11背离介质基板10的一侧固定辅助基板300。
在一些示例中，辅助基板300作为补强板，辅助基板300可以采用双面镀铜的玻璃基，也可以是不锈钢等其他材料。具体的，在步骤S34中可以采用第一粘合层301将辅助基板300固定在第一信号走线11背离介质基板10的一侧。其中，第一粘合层301包括但不限于键合胶，键合胶具体可以为温控胶。例如：200℃键合的键合胶和200℃解粘的温控胶。
在本公开实施例中，在安装芯片14之前固定补强板，可以有效的增加介质基板10的强度，降低碎片的风险。
S35、对初始基板100的第二表面侧进行减薄，形成介质基板10，并裸露第一连接电极13。
在一些示例中，步骤S35可以包括对初始基板100的第二表面侧进行减薄，之后再用CMP工艺抛光降低粗糙度，并裸露第一连接电极13。也就是说在步骤S35中形成贯穿介质基板10的通孔。
S36、在介质基板10背离第一信号走线11的一侧形成第二信号走线12，且第二信号走线12的一端与第一连接电极13电连接，以及在第二信号线背离介质基板10的一侧形成第二绝缘层19，第二绝缘层19具有第二过孔，第二过孔裸露第二信号走线12与印刷电路板20连接的一端。
在一些示例中，步骤S36可以包括在介质基板10背离第一信号走线11的一侧形成第二导电薄膜，并在第二导电薄膜背离介质基板10的一侧涂覆光刻胶，接下来进行曝光、显影、刻蚀形成包括第二信号走线12的图形。最后，在第二信号线背离介质基板10的一侧形成第二绝缘层19，并形成贯穿第二绝缘层19的第二过孔，第二过孔裸露第二信号走线12与印刷电路板20连接的一端。
S37、在第二信号走线12背离介质基板10的一侧安装芯片14，并在芯片14背离介质基板10的一侧形成封装层15，也即对芯片14进行封装。
在一些示例中，在步骤S37中可以通过焊接的方式将第二信号走线12与芯片14电连接在一起。例如：在第二信号走线12与芯片14连接的一端形成第一连接焊盘16，之后通过锡球或者铜柱将第一连接焊盘16和芯片14 焊接连接，从而实现第二信号走线12与芯片14的电连接。其中。第一连接焊盘16可以为化镍金。封装层15可以为塑封料。
S38、将辅助基板300去除。
至此完成封装基板的制备。
其中，由于第一信号走线11后续要与印刷电路板20电连接，而第一信号走线11与印刷电路板20可以采用焊接的方式连接在一起。因此，在第一信号走线11与印刷电路板20连接的一端形成第二连接焊盘17，之后通过锡球或者铜柱将第二连接焊盘17和印刷电路板20焊接连接，从而实现第一信号走线11与印刷电路板20的电连接。其中。第二连接焊盘17可以为化镍金。
相应的，本公开实施例还提供一种功能基板的制备方法，该功能基板的制备方法包括上述形成封装基板的步骤，该功能基板的制备方法在上述形成封装基板的基础上，还包括将第一信号走线11与印刷电路板20电连接的步骤。
在一些示例中，第一信号走线11与印刷电路板20可以采用焊接的方式连接在一起。因此，在第一信号走线11与印刷电路板20连接的一端形成第二连接焊盘17，之后通过锡球或者铜柱将第二连接焊盘17和印刷电路板20焊接连接，从而实现第一信号走线11与印刷电路板20的电连接。其中。第二连接焊盘17可以为化镍金。
在第三种示例中，在该制备方法仅需增加一次补强板，该补强板可以在减薄工艺中起到临时保护和补强的作用，还可以在封装芯片14过程中起到补强的作用。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (20)

  1. 一种封装基板的制备方法，其包括：
    提供一初始基板；所述初始基板包括沿其厚度方向相对设置的第一表面和第二表面；所述初始基板包括玻璃基；
    对所述初始基板进行处理，形成在所述初始基板厚度方向上贯穿部分所述初始基板的盲孔，且所述盲孔的第一开口贯穿所述第一表面；
    在所述盲孔内形成第一连接电极，以及在所述第一表面形成第一信号走线，且所述第一信号走线的一端与所述第一连接电极电连接；
    对所述初始基板的第二表面侧进行减薄，形成具有通孔的介质基板，并裸露所述第一连接电极；
    在所述介质基板背离所述第一信号走线的一侧形成第二信号走线；所述第一信号走线和所述第二信号走线中的一者被配置与所述芯片电连接，另一者被配置为与所述印刷电路板电连接。
  2. 根据权利要求1所述的封装基板的制备方法，其中，所述对所述初始基板的第二表面侧进行减薄，形成介质基板，并裸露所述第一连接电极的步骤包括：
    在所述第一信号走线背离所述第一表面的一侧固定载体基板；
    对所述所述初始基板的第二表面侧进行减薄，形成介质基板，并裸露所述第一连接电极；
    在所述在所述介质基板背离所述第一信号走线的一侧形成第二信号走线的步骤之前，还包括：
    将所述载板基板去除。
  3. 根据权利要求2所述的封装基板的制备方法，其中，在所述介质基板背离所述第一信号走线的一侧形成第二信号走线的步骤之后，还包括：
    在所述第二信号走线背离所述介质基板的一侧固定辅助基板；
    在所述第一信号走线背离所述介质基板的一侧安装芯片，所述芯片与所 述第一信号走线电连接；
    在所述芯片背离所述介质基板的一侧形成封装层；
    去除所述辅助基板。
  4. 根据权利要求3所述的封装基板的制备方法，其中，所述芯片与所述第一信号走线采用焊接的方式电连接。
  5. 根据权利要求3所述的封装基板的制备方法，其中，所述辅助基板通过第一粘合层与所述第二信号走线背离所述介质基板的一侧固定。
  6. 根据权利要求2所述的封装基板的制备方法，其中，所述载板基板通过第二粘合层与所述第一信号走线背离所述第一表面的一侧固定。
  7. 根据权利要求1所述的封装基板的制备方法，其中，在所述对所述初始基板的第二表面侧进行减薄，形成介质基板，并裸露所述第一连接电极的步骤之前，还包括：
    在所述第一信号走线背离所述第一表面的一侧安装芯片，所述芯片与所述第一信号走线电连接。
  8. 根据权利要求1所述的封装基板的制备方法，其中，在所述对所述初始基板的第二表面侧进行减薄，形成介质基板，并裸露所述第一连接电极的步骤之前，还包括：
    在所述第一信号走线背离第一表面的一侧固定辅助基板；
    对所述所述初始基板的第二表面侧进行减薄，形成介质基板，并裸露所述第一连接电极；
    在所述在所述介质基板背离所述第一信号走线的一侧形成第二信号走线的步骤之后，还包括：
    在所述第二走线背离所述介质基板的一侧安装所述芯片，所述芯片与所述第二走线电连接；
    去除所述辅助基板。
  9. 根据权利要求1所述的封装基板的制备方法，其中，所述辅助基板 通过第一粘合层与所述第一信号走线背离第一表面的一侧固定。
  10. 根据权利要求1-9中任一项所述的封装基板的制备方法，其中，所述第一信号走线的一端与所述第一连接电极连接，所述第一信号走线的另一端背离所述介质基板的一侧形成有第一连接焊盘；
    所述第二信号走线的一端与所述第一连接电极连接，所述第二信号走线的另一端背离所述介质基板的一侧形成有第二连接焊盘。
  11. 根据权利要求1-10中任一项所述的封装基板的制备方法，其中，所述第一连接电极采用电镀工艺或者化学镀工艺形成。
  12. 一种封装基板，其包括：
    介质基板，具有沿其厚度方向贯穿的通孔；所述介质基板为玻璃基；
    第一连接电极，设置在所述通孔内；
    第一信号走线和第二信号走线，分别设置在所述介质板基板的两相对侧面上，且所述第一信号走线和所述第二信号走线通过所述第一连接电极电连接；
    其中，所述第一信号走线和所述第二信号走线中的一者被配置与所述芯片电连接，另一者被配置为与所述印刷电路板电连接。
  13. 根据权利要求12所述的封装基板，其中，还包括芯片；所述芯片与所述第一信号走线电连接，且在所述芯片背离所述介质基板的一侧设置有封装层。
  14. 根据权利要求12所述的封装基板，其中，所述第一信号走线一端电连接第一连接电极，另一端电连接第一连接焊盘，所述第一连接焊盘设置在所述第一信号走线背离所述介质基板的一侧。
  15. 根据权利要求12所述的封装基板，其中，所述第二信号走线一端电连接第一连接电极，另一端电连接第二连接焊盘，所述第二连接焊盘设置在所述第二信号走线背离所述介质基板的一侧。
  16. 一种功能基板的制备方法，其包括权利要求1-11中任一项所述的封 装基板的制备方法。
  17. 根据权利要求16所述的功能基板的制备方法，其中，当所述第一信号走线与所述芯片电连接时，所述制备方法还包括：
    将所述第二信号走线与印刷电路板电连接；
    当所述第二信号走线与所述芯片电连接时，所述制备方法还包括：
    将所述第一信号走线与印刷电路板电连接。
  18. 根据权利要求17所述的功能基板的制备方法，其中，所述将所述第二信号走线与印刷电路板电连接的步骤，包括：
    将所述第二信号走线与所述印刷电路板采用焊接的方式电连接。
  19. 根据权利要求17所述的功能基板的制备方法，其中，将所述第一信号走线与印刷电路板电连接的步骤，包括：
    将所述第一信号走线与所述印刷电路板采用焊接的方式电连接。
  20. 一种功能基板，其包括权利要求12-15中任一项所述的封装基板；其中，所述第一信号走线和所述第二信号走线中的一者与芯片电连接，另一者与印刷电路板电连接。
PCT/CN2022/115096 2022-08-26 2022-08-26 封装基板及其制备方法和功能基板及其制备方法 WO2024040565A1 (zh)

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