WO2024037573A1 - 时钟信号传输装置及其制造方法、光学时钟平衡装置 - Google Patents

时钟信号传输装置及其制造方法、光学时钟平衡装置 Download PDF

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WO2024037573A1
WO2024037573A1 PCT/CN2023/113423 CN2023113423W WO2024037573A1 WO 2024037573 A1 WO2024037573 A1 WO 2024037573A1 CN 2023113423 W CN2023113423 W CN 2023113423W WO 2024037573 A1 WO2024037573 A1 WO 2024037573A1
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Prior art keywords
clock
optical signal
optical
signal
electrical
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PCT/CN2023/113423
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English (en)
French (fr)
Inventor
沈亦晨
孟怀宇
王鲁
柏艳飞
陈炜
华士跃
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南京光智元科技有限公司
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Publication of WO2024037573A1 publication Critical patent/WO2024037573A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation

Definitions

  • the present invention relates to the technical field of clock synchronization, and more specifically, to a clock signal transmission device and a manufacturing method thereof, and an optical clock balancing device.
  • a clock network is formed inside the chip through metal lines and logic devices such as buffers and inverters for clock signal transmission.
  • This kind of clock network has the problems of too high delay and being greatly affected by PVT (Process-Voltage-Temperature: process-voltage-temperature) differences.
  • PVT Process-Voltage-Temperature: process-voltage-temperature
  • the invention provides a clock signal transmission device, a manufacturing method thereof, and an optical clock balancing device, which utilizes an on-chip optical network to complete the transmission of clock signals, and can complete the balancing of the delay time of arrival of clock signals at various points on the optical network.
  • a clock signal transmission device which includes:
  • An on-chip optical network which includes an optical signal transmitting end, a plurality of optical signal receiving ends, and a plurality of waveguides connecting the optical signal transmitting end and the optical signal receiving end;
  • An electro-optical conversion module which is disposed at the optical signal transmitting end, is used to receive clock electrical signals from a clock source, and convert the clock electrical signals into clock optical signals.
  • the clock optical signals are transmitted to the optical signal transmitter through different waveguides. Different optical signal receiving ends; and
  • a plurality of photoelectric conversion modules are respectively provided at the plurality of optical signal receiving ends for converting the respective received clock optical signals. signal is converted into a clock electrical signal.
  • the plurality of waveguides are configured to make the transmission time of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends approximately equal.
  • the plurality of waveguides are configured such that the transmission distance of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends is approximately equal.
  • different waveguides located in the same clock balancing system among the plurality of waveguides are arranged so that the transmission distance of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends is approximately equal.
  • different waveguides located in different clock balancing systems among the plurality of waveguides are configured such that the transmission distances of the clock optical signals from the optical signal transmitting end to different optical signal receiving ends are approximately equal or unequal. .
  • the clock signal transmission device further includes at least one electrical clock balancing module, which is communicatively connected to at least one photoelectric conversion module among the plurality of photoelectric conversion modules, and is used to obtain the signal from the at least one photoelectric conversion module. Receive clock electrical signals and repair clock balance.
  • the clock signal transmission device is configured to transmit a delay time stamp of a clock signal from the clock source to each optical signal receiving end through the on-chip optical network to a clock electrical signal of the electrical clock balancing module in the origin.
  • the electrical clock balancing module includes a clock tree.
  • the clock signal transmission device includes a photonic integrated circuit chip
  • the photonic integrated circuit chip includes the on-chip optical network, the electro-optical conversion module, and the photoelectric conversion module.
  • a manufacturing method of a clock signal transmission device which includes:
  • the on-chip optical network including an optical signal transmitting end, a plurality of optical signal receiving ends, and a plurality of waveguides connecting the optical signal transmitting end and the optical signal receiving end;
  • An electro-optical conversion module is provided at the optical signal sending end.
  • the electro-optical conversion module is configured to receive a clock electrical signal from a clock source and convert the clock electrical signal into a clock optical signal.
  • the clock optical signal passes through different The waveguide is transmitted to different optical signal receiving ends;
  • a plurality of photoelectric conversion modules are provided at the plurality of optical signal receiving ends, and each photoelectric conversion module is configured to convert a respective received clock optical signal into a clock electrical signal.
  • the manufacturing method further includes: adjusting the length of each waveguide so that the transmission time of the clock optical signal from the optical signal transmitting end to the different optical signal receiving ends is approximately equal. In some embodiments, the length of each waveguide is adjusted so that the transmission distance of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends is approximately equal.
  • the manufacturing method further includes: adjusting the length of each waveguide so that different waveguides located in the same clock balancing system are configured to make the clock optical signal flow from the optical signal transmitting end to different optical signals.
  • the transmission distance at the receiving end is approximately the same.
  • the manufacturing method further includes: adjusting the length of each waveguide so that different waveguides located in different clock balancing systems transmit the clock optical signal from the optical signal transmitting end to different optical signal receiving ends. The transmission distances are roughly equal or unequal.
  • the manufacturing method further includes: providing at least one electrical clock balancing module, the at least one electrical clock balancing module being communicatively connected to at least one optoelectronic conversion module among the plurality of optoelectronic conversion modules to obtain the signal from the photoelectric conversion module.
  • the at least one photoelectric conversion module receives the clock electrical signal and repairs the clock balance.
  • the manufacturing method further includes: configuring the clock signal transmission device to be able to transmit a delay time stamp of a clock signal from the clock source to each optical signal receiving end through the on-chip optical network to the The origin of the clock electrical signal of the electrical clock balancing module. That is to say, the delay time of the clock origin generated by the clock source and transmitted to each optical signal receiving end (including the photoelectric conversion module) through the on-chip optical network is marked into the clock electrical signal origin of the electrical clock balancing module.
  • the electrical clock balancing module includes a clock tree.
  • the clock signal transmission device includes a photonic integrated circuit chip, and the photonic integrated circuit chip includes the on-chip optical network, the electro-optical conversion module, and the photoelectric conversion module.
  • an optical clock balancing device which includes:
  • An electro-optical conversion module which is used to convert the received clock electrical signal into a clock optical signal
  • An on-chip optical network which includes a plurality of waveguides that transmit the clock optical signal to different clock receiving ends, wherein the plurality of waveguides are configured to transmit the clock optical signal to different The transmission distance of the clock receiving end is approximately the same;
  • a plurality of photoelectric conversion modules are provided at different clock receiving ends for converting the clock optical signal into a clock electrical signal.
  • the photoelectric conversion module is used to convert the clock signal to the on-chip optical network
  • the on-chip optical network is used to complete the transmission of the clock signal.
  • the balance of the delay time of the clock signal arriving at each point on the on-chip optical network can be completed.
  • Using an on-chip optical network to transmit clock signals can reduce the use of on-chip buffers and inverters, thereby reducing power consumption.
  • the on-chip optical network is used to transmit the clock signal, which is not affected by PVT and has small clock skew. Using on-chip optical network to transmit clock signals, the transmission speed is fast and the delay is small.
  • building a chip clock tree through an on-chip optical network can effectively reduce the impact of PVT on clock synchronization, reduce clock deviation, reduce clock delay, and reduce power consumption.
  • the present invention can be used to realize clock synchronization of large-scale chips. step.
  • FIG. 1 is a logical structure diagram of a clock signal transmission device according to an embodiment of the present invention.
  • FIG. 2 is Embodiment 1 of a clock signal transmission device according to an embodiment of the present invention.
  • Figure 3 is Embodiment 2 of a clock signal transmission device according to an embodiment of the present invention.
  • Figure 4 is Embodiment 3 of a clock signal transmission device according to an embodiment of the present invention.
  • Figure 5 is Embodiment 4 of a clock signal transmission device according to an embodiment of the present invention.
  • FIG. 6 is a block diagram of a clock signal transmission device according to an exemplary embodiment of the present invention.
  • the terms “substantially,” “about,” and similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for inherent variations in measured or calculated values that one of ordinary skill in the art will recognize. Additionally, the use of “may” when describing embodiments of the invention means “one or more embodiments of the invention.” As used herein, the terms “use,” “being used,” and “being used” may be considered synonymous with the terms “utilizing,” “utilizing,” and “being utilized,” respectively.
  • FIG. 1 shows the logical structure of a clock signal transmission device according to an embodiment of the present invention.
  • the clock signal transmission device includes an on-chip optical network 101, an electro-optical conversion module 102 located at the optical signal transmitting end of the on-chip optical network 101, and multiple photoelectric conversion modules located at the optical signal receiving end of the on-chip optical network 101.
  • the electro-optical conversion module 102 receives the clock electrical signal generated by the clock source S and converts the clock electrical signal into a clock optical signal.
  • the on-chip optical network 101 includes a plurality of waveguides and a replication unit (such as an optical beam splitter), through which the clock optical signal is distributed to the plurality of waveguides, so that the plurality of waveguides are
  • the clock optical signal is transmitted to multiple photoelectric conversion modules 103 located at different optical signal receiving ends.
  • the photoelectric conversion module 103 converts the received clock optical signal into a clock electrical signal.
  • the transmission distance of each optical path through each waveguide can be equal or approximately equal, and when the clock deviation, maximum fanout (Max Fanout) and maximum transition time (Max Transition)
  • the photoelectric conversion module 103 can be directly connected to the clock receiving end D.
  • the multiple waveguides of the on-chip optical network 101 constitute an optical clock tree (which may be called a "master clock tree") for achieving clock balancing.
  • an electrical clock balancing module 400 can be connected between the photoelectric conversion module 103 and the corresponding clock receiving end D.
  • the electrical clock balance module 400 may include a clock tree (which may be called a "sub-clock tree”), and use the sub-clock tree to repair the clock balance, or further adjust the maximum fanout and Maximum conversion time fixed.
  • the sub-clock tree included in the electrical clock balancing module 400 is an electrical clock tree, which is mainly composed of logical devices such as buffers and/or inverters connected by electrical lines.
  • the clock deviation can be adjusted by adjusting the waveguide length, electrical line length, and sub-clock tree; the maximum fan-out can usually be adjusted by the sub-clock tree; the maximum conversion time can be adjusted by adjusting the maximum fan-out, transmission distance , line RC (resistance and capacitance) to adjust.
  • the delay time when the clock origin is transmitted to each optical signal receiving end (including the photoelectric conversion module) through the optical chip is marked into the clock electrical signal origin of the electrical clock balancing module 400, thereby correcting the clock signal to help complete the Timing analysis.
  • the clock signal transmission device includes a photonic integrated circuit (Photonic Integrated Circuits, PIC) chip.
  • the PIC chip includes the above-mentioned electro-optical conversion module 102, an on-chip optical network 101 including the optical clock tree, and multiple A photoelectric conversion module 103.
  • the optical clock balancing device of the present invention includes the above-mentioned electro-optical conversion module 102, an on-chip optical network 101 including the optical clock tree, and a plurality of photoelectric conversion modules 103.
  • the optical balancing device is used for clock balancing.
  • the optical clock balancing device is implemented as the PIC chip.
  • the on-chip optical network 101 may not have a clock balancing function, that is, the transmission distances of each optical path through each waveguide are not equal.
  • the plurality of photoelectric conversion modules 103 need to be connected to a circuit.
  • the clock balancing module 400 is used to perform clock balancing.
  • FIG. 2 shows Embodiment 1 of a clock signal transmission device according to an embodiment of the present invention.
  • the clock signal transmission device includes a PIC chip 100
  • the PIC chip 100 includes an on-chip optical network 101, which includes an optical signal transmitting end, a plurality of optical signal receiving ends, and a plurality of optical signal receiving ends.
  • the optical signal transmitting end and the optical signal receiving end include a plurality of waveguides 105 and a replicating unit 104.
  • the PIC chip 100 also includes an electro-optical conversion module 102, which is disposed at the optical signal transmitting end for receiving a clock electrical signal from the clock source S and converting the clock electrical signal into a clock optical signal.
  • the clock optical signal is copied or distributed to different waveguides 105 by the copying unit 104, and transmitted to different optical signal receiving ends through the different waveguides 105.
  • the PIC chip 100 also includes a plurality of photoelectric conversion modules 103, which are respectively provided at the plurality of optical signal receiving ends for converting the clock optical signals received by each into clock electrical signals.
  • the plurality of waveguides 105 are arranged to make the transmission time of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends approximately equal.
  • the plurality of waveguides 105 are arranged The transmission distance of the clock optical signal from the electro-optical conversion module 102 to different photoelectric conversion modules 103 is approximately equal, thereby achieving clock balance.
  • the multiple waveguides 105 on the on-chip optical network 101 can constitute an optical clock for clock balancing. Tree. Therefore, the photoelectric conversion module 103 can be directly connected to the clock receiving terminal D.
  • the clock source S may be a phase locked loop (Phase Locked Loop, PLL) circuit integrated in the electronic integrated circuit (EIC) chip 200 .
  • the clock source S may also be an external clock source integrated on the EIC chip 200 .
  • the on-chip optical network 101 can be separately formed on a substrate or an interposer, and a plurality of photonic integrated circuit chips are disposed on the substrate or the interposer, and one of the photonic integrated circuit chips is laid out
  • the electro-optical conversion module is arranged on the remaining multiple photonic integrated circuit chips.
  • the on-chip optical network 101 itself includes an optical clock tree that implements clock balancing, so it can be used as a clock balancing system. Therefore, the electro-optical conversion module 102, the on-chip optical network 101 and the photoelectric conversion module 103 can constitute an optical clock balancing device and play the role of clock balancing.
  • the plurality of waveguides in the same clock balancing system among the plurality of waveguides 105 are arranged so that the transmission distance of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends is approximately Equality; multiple waveguides located in different clock balancing systems are arranged so that the transmission distances of the clock optical signals from the optical signal transmitting end to different optical signal receiving ends are approximately equal or unequal.
  • the electro-optical conversion module 102 includes a modulator and a light source provided on the PIC chip 100 , wherein the digital-to-analog conversion unit provided on the EIC chip 200 converts the clock source S
  • the generated clock digital electrical signal is converted into a clock analog electrical signal.
  • the clock electrical signal is transmitted to the PIC chip 100 through a conductive path.
  • the modulator provided on the PIC chip 100 modulates the clock analog electrical signal to the clock analog electrical signal generated by the light source. optical signal, thereby obtaining a clock optical signal carrying clock information.
  • the clock optical signal is transmitted to a plurality of photoelectric conversion modules 103 through an on-chip optical network including a replica unit and a plurality of waveguides.
  • Each of the photoelectric conversion modules 103 includes a detection unit provided on the PIC chip 100 , where the detection unit includes, for example, a photodiode for converting the received clock optical signal into a clock analog electrical signal.
  • the clock analog electrical signal is transmitted to the EIC chip 200 through a conductive path.
  • the analog-to-digital conversion unit provided on the EIC chip 200 converts the clock analog electrical signal into a clock digital electrical signal.
  • the clock digital electrical signal is sent to different Clock receiving terminal D, so that different clock receiving terminals D can achieve clock synchronization.
  • different clock receiving terminals D and clock sources S are integrated in the same EIC chip 200 .
  • different clock receiving terminals D and clock sources S may be on different EIC chips.
  • FIG. 3 shows Embodiment 2 of a clock signal transmission device according to an embodiment of the present invention.
  • the clock signal transmission device has basically the same structure as the clock signal transmission device in Embodiment 1.
  • the main difference between the two is that the clock signal transmission device in Embodiment 2 also includes a clock signal transmission device integrated in the EIC chip 200
  • the electrical clock balancing module 400 is directly connected in communication with the photoelectric conversion module 103.
  • the electrical clock balancing module 400 includes an electrical clock tree.
  • a clock receiving end receives a clock electrical signal from the photoelectric conversion module 103 via the electrical clock tree, and the electrical clock tree performs clock balancing. Balance repair.
  • the clock signal transmission device is configured to transmit the delay time stamp of the clock signal from the clock source S to each optical signal receiving end through the on-chip optical network 101 to the electrical clock balancing module 400
  • the clock electrical signal is at the origin. That is to say, in Embodiment 2, the position where each clock optical signal is converted into a clock electrical signal is used as the origin, and a clock tree is established to repair clock balance, maximum fan-out, and maximum conversion time, and complete the connection of the clock receiving end.
  • the electrical clock balancing module 400 may be disposed on other EIC chips or other electronic devices that are independent from the EIC chip 200 where the clock source S is located.
  • FIG. 4 shows Embodiment 3 of a clock signal transmission device according to an embodiment of the present invention.
  • the clock signal transmission device has basically the same structure as the clock signal transmission device in Embodiment 2.
  • the main difference between the two is that Embodiment 3 can handle clock receiving ends that do not have to perform clock balancing.
  • the electrical clock signal of the clock source S is directly received through the electrical clock balancing module 400 .
  • the clock electrical signal generated by the clock source S can directly pass through the electrical clock balancing module 400 without being transmitted through the on-chip optical network of the PIC chip 100
  • the clock tree is sent to the clock receiving end.
  • FIG. 5 shows Embodiment 4 of a clock signal transmission device according to an embodiment of the present invention.
  • the clock signal transmission device has basically the same structure as the clock signal transmission device in Embodiment 3.
  • the main difference between the two is that in Embodiment 4, for part of the clock receiving end D, through the PIC chip
  • the on-chip optical network 101 on the 100 has reached the design requirements such as clock deviation, maximum fan-out, maximum conversion time, etc., and can be directly connected to the photoelectric conversion module 103 to receive the clock signal; for the other part of the clock receiving end, an electrical clock is required
  • the balancing module 400 receives the clock signal, and repairs the clock balance through the electrical clock balancing module 400, so that the clock deviation, maximum fan-out, maximum conversion time, etc. meet the design requirements.
  • the clock signal transmission device of the present invention has been specifically described above through different embodiments, and the manufacturing method of the clock signal transmission device will be described below.
  • the manufacturing method of the clock signal transmission device includes:
  • S1 Provide an on-chip optical network, which includes an optical signal transmitting end, a plurality of optical signal receiving ends, and a plurality of waveguides connecting the optical signal transmitting end and the optical signal receiving end;
  • An electro-optical conversion module is provided at the optical signal transmitting end.
  • the electro-optical conversion module is configured to receive a clock electrical signal from a clock source and convert the clock electrical signal into a clock optical signal.
  • the clock optical signal Transmitted to different optical signal receiving ends through different waveguides;
  • each photoelectric conversion module is configured to convert the clock optical signal received by each into a clock electrical signal.
  • the manufacturing method further includes: adjusting the length of each waveguide so that the transmission time of the clock optical signal from the optical signal transmitting end to the different optical signal receiving ends is approximately equal.
  • the length of each waveguide is adjusted so that the transmission distance of the clock optical signal from the optical signal transmitting end to different optical signal receiving ends is approximately equal.
  • the electro-optical conversion module serves as the clock signal source of the on-chip optical network, completes the connection of the farthest clock signal receiving end through waveguides, and calculates the transmission distance; completes the connection of other clock receiving ends through other waveguides; According to the longest transmission distance, the length of each optical waveguide is adjusted through waveguide wiring design so that the transmission distance of each optical path is equal or approximately equal.
  • the on-chip optical network can then be fabricated by forming waveguides on the substrate or substrate used to form the on-chip optical network according to the waveguide routing design.
  • the length of each waveguide can be adjusted according to the above method, so that different waveguides located in the same clock balancing system are configured to transmit the clock optical signal from the optical signal transmitting end to different optical signal receiving ends. The distances are roughly equal. In some embodiments, the length of each waveguide can be adjusted according to the above method, so that different waveguides located in different clock balancing systems transmit the clock optical signal from the optical signal transmitting end to different optical signal receiving ends over a transmission distance of approximately Equal or unequal.
  • the manufacturing method further includes: providing at least one electrical clock balancing module, the at least one electrical clock balancing module being communicatively connected to at least one optoelectronic conversion module among the plurality of optoelectronic conversion modules to obtain the signal from the photoelectric conversion module.
  • the at least one photoelectric conversion module receives the clock electrical signal and repairs the clock balance.
  • the electrical clock balancing module includes a clock tree for repairing clock skew, maximum fanout, and maximum transition time so that they meet design requirements.
  • the clock tree includes buffers, inverters, and/or other logic devices.
  • the manufacturing method further includes: configuring the clock signal transmission device to be able to transmit a delay time stamp of a clock signal from the clock source to each optical signal receiving end through the on-chip optical network to the Describe the clock electrical signal origin of the electrical clock balancing module to help complete timing analysis.

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Abstract

本发明涉及时钟同步技术领域，其提供了一种时钟信号传输装置及其制造方法、光学时钟平衡装置。示例性地，所述时钟信号传输装置可以包括：片上光网络，其包括光信号发送端、多个光信号接收端、以及连接所述光信号发送端和光信号接收端的多条波导；电光转换模块，其设置在所述光信号发送端，用于接收来自于时钟源的时钟电信号，并将所述时钟电信号转换为时钟光信号，所述时钟光信号通过不同的波导传输至不同的光信号接收端；以及多个光电转换模块，其分别设置于所述多个光信号接收端，用于将各自接收的时钟光信号转换为时钟电信号。本发明利用片上光网络完成时钟信号的传输，可以在光网络上完成时钟信号到达各个时钟接收端的延迟时间的平衡。

Description

时钟信号传输装置及其制造方法、光学时钟平衡装置
相关申请的交叉引用
本申请要求于2022年8月19日提交的申请号为202210995622.7、名称为“时钟信号传输装置及其制造方法、光学时钟平衡装置”的中国发明专利申请的权益和优先权，该中国专利申请的全部内容通过引用并入本文。
技术领域
本发明涉及时钟同步技术领域，更为具体而言，涉及一种时钟信号传输装置及其制造方法、光学时钟平衡装置。
背景技术
在传统的电子集成电路芯片中，通过金属线和诸如缓冲器(buffer)、反相器(inverter)之类的逻辑器件在芯片内部构成时钟网络，进行时钟信号传输。这种时钟网络，存在延迟过高以及受PVT(Process-Voltage-Temperature：工艺-电压-温度)差异影响过大的问题。尤其是当芯片面积比较大，需要传输的距离比较长的情况下，很难做到将整个芯片同步在一个时钟周期内。
比如，一颗宽度为20000um的芯片，假设时钟源在中心点，大约需要1ns的时钟长度才能完成时钟平衡。然而，考虑到OCV(On-Chip Variation：片上波动)的影响，实际上最近的时钟接收点和最远的时钟接收点之间的延迟差会达到约200ps，使得两端的时钟难以同步。从而，需要额外的电路设计来实现这两端的时钟同步，这必然会增加功耗和设计复杂度。
发明内容
本发明提供了一种时钟信号传输装置及其制造方法、光学时钟平衡装置，其利用片上光网络完成时钟信号的传输，可以在光网络上完成时钟信号到达各个点延迟时间的平衡。
根据本发明的一方面，提供了一种时钟信号传输装置，其包括：
片上光网络，其包括光信号发送端、多个光信号接收端、以及连接所述光信号发送端和光信号接收端的多条波导；
电光转换模块，其设置在所述光信号发送端，用于接收来自于时钟源的时钟电信号，并将所述时钟电信号转换为时钟光信号，所述时钟光信号通过不同的波导传输至不同的光信号接收端；以及
多个光电转换模块，其分别设置在所述多个光信号接收端，用于将各自接收的时钟光信 号转换为时钟电信号。
在一些实施方式中，所述多条波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输时间大致相等。
在一些实施方式中，所述多条波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等。
在一些实施方式中，所述多条波导中位于同一时钟平衡系统的不同波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等。
在一些实施方式中，所述多条波导中位于不同时钟平衡系统的不同波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等或不相等。
在一些实施方式中，所述时钟信号传输装置还包括至少一个电时钟平衡模块，其与所述多个光电转换模块中的至少一个光电转换模块通信连接，用于从所述至少一个光电转换模块接收时钟电信号并对时钟平衡进行修复。
在一些实施方式中，所述时钟信号传输装置被设置成将时钟信号从所述时钟源经所述片上光网络传输到各个光信号接收端的延迟时间标记到所述电时钟平衡模块的时钟电信号原点中。
在一些实施方式中，所述电时钟平衡模块包括时钟树。
在一些实施方式中，所述时钟信号传输装置包括光子集成电路芯片，所述光子集成电路芯片包括所述片上光网络、所述电光转换模块、以及所述光电转换模块。
根据本发明的另一方面，提供了一种时钟信号传输装置的制造方法，其包括：
提供片上光网络，所述片上光网络包括光信号发送端、多个光信号接收端、以及连接所述光信号发送端和光信号接收端的多条波导；
在所述光信号发送端设置电光转换模块，所述电光转换模块被设置成接收来自于时钟源的时钟电信号，并将所述时钟电信号转换为时钟光信号，所述时钟光信号通过不同的波导传输至不同的光信号接收端；以及
在所述多个光信号接收端设置多个光电转换模块，各光电转换模块被设置成将各自接收的时钟光信号转换为时钟电信号。
在一些实施方式中，所述制造方法还包括：调整各个波导的长度，以使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输时间大致相等。在一些实施方式中，调整各个波导的长度，以使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等。
在一些实施方式中，所述制造方法还包括：调整各个波导的长度，以使位于同一时钟平衡系统的不同波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等。在一些实施方式中，所述制造方法还包括：调整各个波导的长度，以使位于不同时钟平衡系统的不同波导将所述时钟光信号从所述光信号发送端传输至不同的光信号接收端的传输距离大致相等或不相等。
在一些实施方式中，所述制造方法还包括：提供至少一个电时钟平衡模块，所述至少一个电时钟平衡模块与所述多个光电转换模块中的至少一个光电转换模块通信连接，以从所述至少一个光电转换模块接收时钟电信号并对时钟平衡进行修复。
在一些实施方式中，所述制造方法还包括：配置所述时钟信号传输装置，使其能够将时钟信号从所述时钟源经所述片上光网络传输到各个光信号接收端的延迟时间标记到所述电时钟平衡模块的时钟电信号原点中。也就是说，将时钟源产生的时钟原点经过片上光网络传输至各个光信号接收端(包括光电转换模块)的延迟时间标记到所述电时钟平衡模块的时钟电信号原点中。
在一些实施方式中，所述电时钟平衡模块包括时钟树。在一些实施方式中，所述时钟信号传输装置包括光子集成电路芯片，所述光子集成电路芯片包括所述片上光网络、所述电光转换模块、以及所述光电转换模块。
根据本发明的再一方面，提供了一种光学时钟平衡装置，其包括：
电光转换模块，其用于将接收的时钟电信号转换为时钟光信号；
片上光网络，其包括多条波导，所述多条波导将所述时钟光信号传输至不同的时钟接收端，其中，所述多条波导设置成不同的波导将所述时钟光信号传输至不同的时钟接收端的传输距离大致相等；
多个光电转换模块，其设置在不同的时钟接收端，用于将所述时钟光信号转换时钟电信号。
在本发明的实施方式中，利用光电转换模块，将时钟信号转换到片上光网络，利用片上光网络完成时钟信号的传输，可以在片上光网络上完成时钟信号到达各个点延迟时间的平衡。用片上光网络传输时钟信号可以减少芯片上缓冲器和反相器的使用，从而可以降低功耗。利用片上光网络传输时钟信号，不受PVT的影响，时钟偏差(skew)小。利用片上光网络传输时钟信号，传输速度快，延迟小。
综上所述，通过片上光网络构建芯片时钟树，可以有效降低PVT对时钟同步的影响，降低时钟偏差，并可以降低时钟延迟，减小功耗。本发明可用于实现大规模芯片的时钟同 步。
本发明实施方式的各个方面、特征、优点等将在下文结合附图进行具体描述。根据以下结合附图的具体描述，本发明的上述方面、特征、优点等将会变得更加清楚。
附图说明
图1是根据本发明实施方式的时钟信号传输装置的逻辑结构图。
图2是根据本发明实施方式的时钟信号传输装置的实施例1。
图3是根据本发明实施方式的时钟信号传输装置的实施例2。
图4是根据本发明实施方式的时钟信号传输装置的实施例3。
图5是根据本发明实施方式的时钟信号传输装置的实施例4。
图6是根据本发明示例性实施方式的时钟信号传输装置的模块图。
具体实施方式
在下文中，将参考附图更详细地描述示例性实施方式。然而，本发明可以以各种不同形式体现，并且不应被解释为仅限于本文所示的实施方式。相反，这些实施方式作为示例来提供以便本公开将是透彻而全面的，并且将向本领域技术人员充分传达本发明的各方面和特征。因此，可能不会描述本领域普通技术人员充分理解本发明的各方面和特征所不必要的过程、元件和技术。除非另有说明，否则在整个附图和文字描述中，类似的附图标记表示类似的元件，因此，可能不会重复其描述。此外，每个示例性实施方式内的特征或方面通常应被视为可用于其他示例性实施方式中的其他类似特征或方面。
以下描述中可使用某些术语以仅供参考，因此这些术语并非旨在进行限制。例如，术语诸如“顶部”、“底部”、“上部”、“下部”、“在…上方”和“在…下方”可用于指代作为参考的附图中的方向。术语诸如“正面”、“背面”、“后面”、“侧面”、“外侧”和“内侧”可用于描述部件的各部分在一致但任意的参照系内的取向和/或位置，通过参考描述所讨论的部件的文字和相关联的附图可以清楚地了解所述取向和/或位置。此类术语可包括上文具体提及的词语、它们的衍生词语以及类似含义的词语。类似地，除非上下文明确指出，否则术语“第一”、“第二”以及其他此类指代结构的数字术语并不意味着次序或顺序。
应当理解，当元件或特征被称为“在另一元件或层上”、“连接到”或“联接到”另一元件或层时，其可直接在另一元件或特征上、连接到或联接到另一元件或特征，或可存在一个或多个中间元件或特征。另外，还应当理解，当元件或特征被称为在两个元件或特征“之间”时，其可为这两个元件或特征之间的唯一元件或特征，或也可存在一个或多个中间元件 或特征。
本文使用的术语是为了描述特定实施方式的目的，而非旨在限制本发明。如本文所用，单数形式“一个”和“一种”旨在也包括复数形式，除非上下文另外明确指明。还应当理解，术语“包含”、“包括”和“具有”在本说明书中使用时指定所陈述的特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或它们的集合的存在或添加。如本文所用，术语“和/或”包括相关联的所列项目中的一个或多个的任何和所有组合。诸如“…中的至少一个”之类的表达在要素列表之前时修饰整个要素列表，而不是修饰该列表的单独要素。
如本文所用，术语“基本上”、“约”和类似术语用作近似术语而不是用作程度术语，并且旨在考虑本领域普通技术人员将认识到的测量值或计算值的固有变化。此外，在描述本发明的实施方式时“可”的使用是指“本发明的一个或多个实施方式”。如本文所用，术语“使用”、“正使用”和“被使用”可被视为分别与术语“利用”、“正利用”和“被利用”同义。
除非另有定义，否则本文使用的所有术语(包括技术和科学术语)具有本发明所属领域的普通技术人员通常理解的相同含义。还应当理解，除非在本文中明确地如此定义，否则术语(诸如在常用词典中定义的那些术语)应被解释为具有与它们在相关领域和/或本说明书的上下文中的含义一致的含义，并且不应以理想化或过于正式的意义来解释。
图1示出了根据本发明实施方式的时钟信号传输装置的逻辑结构。在本发明的实施方式中，所述时钟信号传输装置包括片上光网络101、位于片上光网络101的光信号发送端的电光转换模块102、以及位于片上光网络101的光信号接收端的多个光电转换模块103。所述电光转换模块102接收时钟源S产生的时钟电信号，并将所述时钟电信号转换为时钟光信号。所述片上光网络101包括多条波导和复制单元(例如光分束器)，通过所述复制单元将所述时钟光信号分配至所述多条波导，以便通过所述多条波导将所述时钟光信号传输至位于不同光信号接收端的多个光电转换模块103。所述光电转换模块103将接收的时钟光信号转换为时钟电信号。在一些实施方式中，通过设置波导的长度，能够实现经过各波导的各个光通路的传输距离相等或大致相等，并且，当时钟偏差、最大扇出(Max Fanout)和最大转换时间(Max Transition)符合设计要求时，可以将所述光电转换模块103直接连接时钟接收端D。此时，所述片上光网络101的多条波导构成光学时钟树(可以称为“主时钟树”)，用于实现时钟平衡。在一些实施方式中，当时钟偏差、最大扇出和最大转换时间不符合设计要求时，可以在所述光电转换模块103与相应的时钟接收端D之间接入电时钟平衡模块400 来对时钟平衡进行修复，例如，所述电时钟平衡模块400可以包括时钟树(可以称为“子时钟树”)，利用该子时钟树来对时钟平衡进行修复，或进一步对最大扇出和最大转换时间进行修复。其中，电时钟平衡模块400中包含的子时钟树为电时钟树，其主要通过电线路连接缓冲器和/或反相器等逻辑器件构成。在一些实施方式中，时钟偏差可以通过调整波导长度、电线路长度、子时钟树来进行调整；最大扇出通常可通过子时钟树来进行调整；最大转换时间可以通过调整最大扇出、传输距离、线路RC(电阻电容)来进行调整。在一些实施方式中，将时钟原点经过光芯片传输到各个光信号接收端(包含光电转换模块)的延迟时间标记到电时钟平衡模块400的时钟电信号原点中，从而修正时钟信号，以帮助完成时序分析。
在一些实施方式中，所述时钟信号传输装置包括光子集成电路(Photonic Integrated Circuits，PIC)芯片，所述PIC芯片包括上述电光转换模块102、包含所述光学时钟树的片上光网络101、以及多个光电转换模块103。
在一些实施方式中，本发明的光学时钟平衡装置包括上述电光转换模块102、包含所述光学时钟树的片上光网络101、以及多个光电转换模块103。此时，所述光学平衡装置用于时钟平衡。在一些实施方式中，所述光学时钟平衡装置实施为所述PIC芯片。在可选的实施方式中，所述片上光网络101可以不具有时钟平衡功能，即经过各波导的各个光通路的传输距离不相等，此时，所述多个光电转换模块103需接入电时钟平衡模块400来进行时钟平衡。
【实施例1】
图2示出了根据本发明实施方式的时钟信号传输装置的实施例1。在实施例1中，如图2所示，所述时钟信号传输装置包括PIC芯片100，所述PIC芯片100包括片上光网络101，其包括光信号发送端、多个光信号接收端、连接所述光信号发送端和光信号接收端的多条波导105、以及复制单元104。所述PIC芯片100还包括电光转换模块102，其设置在所述光信号发送端，用于接收来自于时钟源S的时钟电信号，并将所述时钟电信号转换为时钟光信号，所述时钟光信号被所述复制单元104复制到或分配到不同的波导105上，并通过不同的波导105传输至不同的光信号接收端。所述PIC芯片100还包括多个光电转换模块103，其分别设置于所述多个光信号接收端，用于将各自接收的时钟光信号转换为时钟电信号。在一些实施方式中，所述多条波导105被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输时间大致相等，例如，所述多条波导105被设置成所述时钟光信号从所述电光转换模块102到不同的光电转换模块103的传输距离大致相等，由此实现时钟平衡。也就是说，所述片上光网络101上的多条波导105可构成用于时钟平衡的光学时钟 树。因此，所述光电转换模块103可以直接连接时钟接收端D。在本实施例中，所述时钟源S可以是集成在电子集成电路(EIC)芯片200中的锁相环(Phase Locked Loop，PLL)电路。在其他实施方式中，所述时钟源S也可以是集成在EIC芯片200上的外部时钟源。在一些实施方式中，所述片上光网络101可以单独地形成在基板或者中介板上，并在该基板或该中介板上设置多个光子集成电路芯片，在其中的一个光子集成电路芯片上布设电光转换模块，在其余的多个光子集成电路芯片上布设光电转换模块。根据本实施例，片上光网络101自身包括实现时钟平衡的光学时钟树，因此，其可以作为时钟平衡系统使用。因此，所述电光转换模块102、片上光网络101和光电转换模块103可以构成光学时钟平衡装置，发挥时钟平衡的作用。在可选的实施方式中，所述多条波导105中位于同一时钟平衡系统的多条波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等；位于不同时钟平衡系统的多条波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等或不相等。
在本发明的示例性实施方式中，如图6所示，所述电光转换模块102包括设置在PIC芯片100的调制器和光源，其中，设置在EIC芯片200的数模转换单元将时钟源S产生的时钟数字电信号转换为时钟模拟电信号，所述时钟电信号通过导电路径传输至PIC芯片100，设置在PIC芯片100的调制器将所述时钟模拟电信号调制到由所述光源产生的光信号，从而得到承载时钟信息的时钟光信号。所述时钟光信号通过包括复制单元和多条波导的片上光网络传输至多个光电转换模块103。每一个所述光电转换模块103包括设置在PIC芯片100的检测单元，其中所述检测单元例如包括光电二极管，用于将接收的时钟光信号转换为时钟模拟电信号。所述时钟模拟电信号通过导电路径传输至EIC芯片200，设置在EIC芯片200的模数转换单元将所述时钟模拟电信号转换为时钟数字电信号，所述时钟数字电信号被发送至不同的时钟接收端D，从而使不同时钟接收端D实现时钟同步。在本实施方式中，不同的时钟接收端D和时钟源S集成在同一EIC芯片200中。在可选的实施方式中，不同的时钟接收端D、时钟源S可以在不同的EIC芯片上。
【实施例2】
图3示出了根据本发明实施方式的时钟信号传输装置的实施例2。在实施例2中，所述时钟信号传输装置与实施例1的时钟信号传输装置具有基本相同的结构，二者的主要区别在于，实施例2的时钟信号传输装置还包括集成在EIC芯片200中的电时钟平衡模块400，其与所述光电转换模块103直接通信连接。所述电时钟平衡模块400包括电时钟树，时钟接收端经由所述电时钟树从所述光电转换模块103接收时钟电信号，由所述电时钟树进行时钟平 衡的修复。在一些实施方式中，所述时钟信号传输装置被设置成将时钟信号从所述时钟源S经所述片上光网络101传输到各个光信号接收端的延迟时间标记到所述电时钟平衡模块400的时钟电信号原点中。也就是说，在实施例2中，以各个时钟光信号转换为时钟电信号的位置为原点，建立时钟树进行时钟平衡、最大扇出、以及最大转换时间的修复，完成时钟接收端的连接。
在可选的实施方式中，所述电时钟平衡模块400可以设置在相对于时钟源S所在的EIC芯片200独立的其他EIC芯片上或其他电子设备上。
【实施例3】
图4示出了根据本发明实施方式的时钟信号传输装置的实施例3。在实施例3中，所述时钟信号传输装置与实施例2的时钟信号传输装置具有基本相同的结构，二者的主要区别在于，实施例3对那些不是必须进行时钟平衡的时钟接收端，可以通过电时钟平衡模块400直接接收时钟源S的时钟电信号。在本实施例中，当部分时钟接收端没有时钟平衡必要性时，所述时钟源S产生的时钟电信号可以不经过PIC芯片100的片上光网络的传输而直接经过所述电时钟平衡模块400的时钟树发送至所述时钟接收端。
【实施例4】
图5示出了根据本发明实施方式的时钟信号传输装置的实施例4。在实施例4中，所述时钟信号传输装置与实施例3的时钟信号传输装置具有基本相同的结构，二者的主要区别在于，在实施例4中，对于部分时钟接收端D，经过PIC芯片100上的片上光网络101进行时钟平衡后时钟偏差、最大扇出、最大转换时间等已达到设计要求，可以直接连接于光电转换模块103接收时钟信号；对于另一部分时钟接收端，需要通过电时钟平衡模块400来接收时钟信号，通过电时钟平衡模块400对时钟平衡进行修复，使时钟偏差、最大扇出、最大转换时间等达到设计要求。
以上通过不同的实施例对本发明的时钟信号传输装置进行了具体说明，下面对所述时钟信号传输装置的制造方法进行说明。
在一些实施方式中，所述时钟信号传输装置的制造方法包括：
S1：提供片上光网络，所述片上光网络包括光信号发送端、多个光信号接收端、以及连接所述光信号发送端和光信号接收端的多条波导；
S2：在所述光信号发送端设置电光转换模块，所述电光转换模块被设置成接收来自于时钟源的时钟电信号，并将所述时钟电信号转换为时钟光信号，所述时钟光信号通过不同的波导传输至不同的光信号接收端；以及
S3：在所述多个光信号接收端设置多个光电转换模块，各光电转换模块被设置成将各自接收的时钟光信号转换为时钟电信号。
在一些实施方式中，所述制造方法还包括：调整各个波导的长度，以使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输时间大致相等。例如，调整各个波导的长度，以使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等。在示例性实施方式中，所述电光转换模块作为所述片上光网络的时钟信号源，通过波导完成最远端时钟信号接收端的连接，并计算传输距离；通过其他波导完成其他时钟接收端的连接；根据最长传输距离，通过波导布线设计，调整各个光波导的长度，以使各个光通路的传输距离相等或大致相等。随后可以根据所述波导布线设计在用来形成片上光网络的基板或衬底上形成波导，由此制作出所述片上光网络。
在一些实施方式中，可以按照上述方法调整各个波导的长度，以使位于同一时钟平衡系统的不同波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等。在一些实施方式中，可以按照上述方法调整各个波导的长度，以使位于不同时钟平衡系统的不同波导将所述时钟光信号从所述光信号发送端传输至不同的光信号接收端的传输距离大致相等或不相等。
在一些实施方式中，所述制造方法还包括：提供至少一个电时钟平衡模块，所述至少一个电时钟平衡模块与所述多个光电转换模块中的至少一个光电转换模块通信连接，以从所述至少一个光电转换模块接收时钟电信号并对时钟平衡进行修复。在一些实施方式中，所述电时钟平衡模块包括时钟树，用于修复时钟偏差、最大扇出和最大转换时间，使它们满足设计要求。所述时钟树包括缓冲器、反相器、和/或其他逻辑器件。
在一些实施方式中，所述制造方法还包括：配置所述时钟信号传输装置，使其能够将时钟信号从所述时钟源经所述片上光网络传输到各个光信号接收端的延迟时间标记到所述电时钟平衡模块的时钟电信号原点中，以帮助完成时序分析。
本领技术人员应当理解，以上所公开的仅为本发明的实施方式而已，当然不能以此来限定本发明请求专利保护的权利范围，依本发明实施方式所作的等同变化，仍属本发明之权利要求所涵盖的范围。

Claims (19)

  1. 一种时钟信号传输装置，其特征在于，包括：
    片上光网络，其包括光信号发送端、多个光信号接收端、以及连接所述光信号发送端和光信号接收端的多条波导；
    电光转换模块，其设置在所述光信号发送端，用于接收来自于时钟源的时钟电信号，并将所述时钟电信号转换为时钟光信号，所述时钟光信号通过不同的波导传输至不同的光信号接收端；以及
    多个光电转换模块，其分别设置在所述多个光信号接收端，用于将各自接收的时钟光信号转换为时钟电信号。
  2. 根据权利要求1所述的时钟信号传输装置，其特征在于，所述多条波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输时间大致相等。
  3. 根据权利要求2所述的时钟信号传输装置，其特征在于，所述多条波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等。
  4. 根据权利要求1所述的时钟信号传输装置，其特征在于，所述多条波导中位于同一时钟平衡系统的不同波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等。
  5. 根据权利要求4所述的时钟信号传输装置，其特征在于，所述多条波导中位于不同时钟平衡系统的不同波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等或不相等。
  6. 根据权利要求1所述的时钟信号传输装置，其特征在于，还包括至少一个电时钟平衡模块，其与所述多个光电转换模块中的至少一个光电转换模块通信连接，用于从所述至少一个光电转换模块接收时钟电信号，并对时钟平衡进行修复。
  7. 根据权利要求6所述的时钟信号传输装置，其特征在于，所述时钟信号传输装置被设置成将时钟信号从所述时钟源经所述片上光网络传输到各个光信号接收端的延迟时间标记到所述电时钟平衡模块的时钟电信号原点中。
  8. 根据权利要求6所述的时钟信号传输装置，其特征在于，所述电时钟平衡模块包括时钟树。
  9. 根据权利要求1至8中任意一项所述的时钟信号传输装置，其特征在于，所述时钟信号传输装置包括光子集成电路芯片，所述光子集成电路芯片包括所述片上光网络、所述电 光转换模块、以及所述光电转换模块。
  10. 一种时钟信号传输装置的制造方法，其特征在于，包括：
    提供片上光网络，所述片上光网络包括光信号发送端、多个光信号接收端、以及连接所述光信号发送端和光信号接收端的多条波导；
    在所述光信号发送端设置电光转换模块，所述电光转换模块被设置成接收来自于时钟源的时钟电信号，并将所述时钟电信号转换为时钟光信号，所述时钟光信号通过不同的波导传输至不同的光信号接收端；以及
    在所述多个光信号接收端设置多个光电转换模块，各光电转换模块被设置成将各自接收的时钟光信号转换为时钟电信号。
  11. 根据权利要求10所述的制造方法，其特征在于，还包括：
    调整各个波导的长度，以使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输时间大致相等。
  12. 根据权利要求11所述的制造方法，其特征在于，调整各个波导的长度，以使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等。
  13. 根据权利要求10所述的制造方法，其特征在于，还包括：
    调整各个波导的长度，以使位于同一时钟平衡系统的不同波导被设置成使所述时钟光信号从所述光信号发送端到不同的光信号接收端的传输距离大致相等。
  14. 根据权利要求13所述的制造方法，其特征在于，还包括：
    调整各个波导的长度，以使位于不同时钟平衡系统的不同波导将所述时钟光信号从所述光信号发送端传输至不同的光信号接收端的传输距离大致相等或不相等。
  15. 根据权利要求10所述的制造方法，其特征在于，还包括：
    提供至少一个电时钟平衡模块，所述至少一个电时钟平衡模块与所述多个光电转换模块中的至少一个光电转换模块通信连接，以从所述至少一个光电转换模块接收时钟电信号并对时钟平衡进行修复。
  16. 根据权利要求15所述的制造方法，其特征在于，还包括：
    配置所述时钟信号传输装置，使其能够将时钟信号从所述时钟源经所述片上光网络传输到各个光信号接收端的延迟时间标记到所述电时钟平衡模块的时钟电信号原点中。
  17. 根据权利要求15所述的制造方法，其特征在于，所述电时钟平衡模块包括时钟树。
  18. 根据权利要求10至17中任意一项所述的制造方法，其特征在于，所述时钟信号传 输装置包括光子集成电路芯片，所述光子集成电路芯片包括所述片上光网络、所述电光转换模块、以及所述光电转换模块。
  19. 一种光学时钟平衡装置，其特征在于，包括：
    电光转换模块，其用于将接收的时钟电信号转换为时钟光信号；
    片上光网络，其包括多条波导，所述多条波导将所述时钟光信号传输至不同的时钟接收端，其中，所述多条波导设置成不同的波导将所述时钟光信号传输至不同的时钟接收端的传输距离大致相等；
    多个光电转换模块，其设置在不同的时钟接收端，用于将所述时钟光信号转换时钟电信号。
PCT/CN2023/113423 2022-08-19 2023-08-17 时钟信号传输装置及其制造方法、光学时钟平衡装置 WO2024037573A1 (zh)

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