WO2024037259A1 - 横向扩散金属氧化物半导体器件及其制备方法 - Google Patents

横向扩散金属氧化物半导体器件及其制备方法 Download PDF

Info

Publication number
WO2024037259A1
WO2024037259A1 PCT/CN2023/106985 CN2023106985W WO2024037259A1 WO 2024037259 A1 WO2024037259 A1 WO 2024037259A1 CN 2023106985 W CN2023106985 W CN 2023106985W WO 2024037259 A1 WO2024037259 A1 WO 2024037259A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
region
layer
semiconductor device
drift region
Prior art date
Application number
PCT/CN2023/106985
Other languages
English (en)
French (fr)
Inventor
安丽琪
宋亮
王琼
王亚南
Original Assignee
无锡华润上华科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华科技有限公司 filed Critical 无锡华润上华科技有限公司
Publication of WO2024037259A1 publication Critical patent/WO2024037259A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular to a laterally diffused metal oxide semiconductor device and a preparation method thereof.
  • LDMOS Lateral Double-diffuse MOS
  • the present application provides a laterally diffused metal oxide semiconductor device, including:
  • a substrate is provided with a trench, the trench includes a first side wall and a bottom wall connected to the first side wall;
  • drift region located in the substrate, and the trench is arranged around the drift region;
  • a gate electrode is provided around the drift region, the gate electrode covers part of the dielectric layer, and extends toward the bottom wall to cover part of the bottom wall.
  • the groove is at least surrounding both sides of the drift region along the first direction; the first The direction is perpendicular to the thickness direction of the substrate.
  • the number of the grooves is two, and the two grooves are located on both sides of the drift region along the first direction;
  • At least part of the drift region is located in the substrate between the two first sidewalls of the two trenches.
  • the dielectric layer covers the entire first sidewall.
  • the laterally diffused metal oxide semiconductor device further includes:
  • a body region is provided in the substrate at the bottom of the trench; the orthographic projection of the gate on the substrate has an overlapping area with the body region;
  • a source region is provided in the body region; the orthographic projection of the gate on the substrate is tangent to or has an overlapping area with the source region, and one end of the source region close to the drift region is connected to the There is a gap between one end of the body region and close to the drift region;
  • a drain region is located in the substrate and on the side of the gate away from the source region;
  • a buried layer is located within the substrate and on a side of the drift region away from the gate.
  • the dielectric layer includes a high temperature oxide layer.
  • the gate includes a stacked gate oxide layer and a polysilicon layer, the gate oxide layer is located on a side of the polysilicon layer close to the dielectric layer, and the dielectric layer The thickness is greater than the thickness of the gate oxide layer.
  • the outer contour of the orthographic projection of the dielectric layer on the substrate is located within the outer contour of the drift region.
  • the outer contour of the orthographic projection of the gate on the bottom wall is located outside the outer contour of the drift region.
  • This application also provides a method for preparing a laterally diffused metal oxide semiconductor device, including:
  • the trench includes a first side wall and a bottom wall connected to each other;
  • a drift region is formed in the substrate, and the trench and the dielectric layer are arranged around the drift region;
  • a gate electrode is formed on the substrate, and the gate electrode is arranged around the drift region; the gate electrode covers part of the dielectric layer, and extends toward the bottom wall to cover part of the bottom wall.
  • the step of forming a dielectric layer on the substrate to cover at least a portion of the first side wall and a portion of the bottom wall connected to the first side wall includes:
  • the first oxide layer is etched to form the dielectric layer.
  • the step of forming a dielectric layer on the substrate to cover at least a portion of the first side wall and a portion of the bottom wall connected to the first side wall includes:
  • the mask layer and the first oxide layer located on the surface of the mask layer are removed to form the dielectric layer.
  • the step before the step of forming a trench on the surface of the substrate, the step further includes;
  • a buried layer is formed in the substrate.
  • the step of forming a gate electrode on the substrate and disposing the gate electrode around the drift region includes:
  • the second oxide layer and the polysilicon material layer are etched to form a gate oxide layer and a polysilicon layer.
  • the method further includes:
  • a body region is formed in the substrate, the body region is disposed in the substrate at the bottom of the trench, and the orthographic projection of the gate on the substrate has an overlapping area with the body region;
  • a source region is formed in the substrate, the source region is disposed in the body region, the orthographic projection of the gate on the substrate is tangent to the source region or has an overlapping area, and the There is a gap between an end of the source region close to the drift region and an end of the body region close to the drift region.
  • Figure 1 is a flow chart of a method for preparing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application
  • Figure 2 is a preparation flow chart of a dielectric layer in a method for preparing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application;
  • Figure 3 is another preparation flow chart of the dielectric layer in the preparation method of a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application;
  • Figure 4 is a flow chart of gate electrode preparation in a method for preparing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application
  • 5 to 13 are schematic cross-sectional structural diagrams of the device structure during the preparation method of a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application;
  • Figure 14 is a partial cross-sectional structural diagram of the laterally diffused metal oxide semiconductor device in Figure 13;
  • Figure 15 is a schematic top view of a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.
  • FIG. 16 is a schematic top view of another laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.
  • 1-Laterally diffused metal oxide semiconductor device 10-substrate; 11-base layer; 12-epitaxial layer; 13-heavily doped region; 14-isolation region; 141-first doped region; 1411-first connection area; 15-buried layer; 16-trench; 16a-first sidewall; 16b-bottom wall; 17-isolation trench; 18-second doped region; 181-second connection region; 20-dielectric layer; 21 -First oxide layer; 30-drift region; 31-buffer region; 32-drain extraction region; 40-gate; 41-gate oxide layer; 42-polysilicon layer; 43-second oxide layer; 44 -Polysilicon material layer; 50-body region; 51-source region; 52-body lead-out region; 60-channel region; 70-accumulation region.
  • first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the application; for example, a first element, component, region, layer, doping type or section could be termed
  • the first doping type becomes the second doping type, and similarly, the second doping type can become the first doping type; the first doping type and the second doping type are different doping types, for example,
  • the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • Spatial relational terms such as “under”, “under”, “under”, “under”, “on”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below” or “under” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” may include both upper and lower orientations. Additionally, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations in the shapes shown are contemplated due, for example, to manufacturing techniques and/or tolerances.
  • embodiments of the present application should not be limited to the specific shapes of the regions shown herein but include deviations in shapes due, for example, to manufacturing techniques.
  • an implanted region that appears as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region.
  • a buried region formed by an implant may result in some implantation in the area between the buried region and the surface through which the implant occurs. Therefore, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.
  • Embodiments of the present application provide a method for preparing a laterally diffused metal oxide semiconductor device and a laterally diffused metal oxide semiconductor device, which can flexibly adjust the breakdown voltage of the laterally diffused metal oxide semiconductor device while reducing the on-resistance, especially While reducing the on-resistance, the breakdown voltage of the laterally diffused metal oxide semiconductor device is increased.
  • the laterally diffused metal oxide semiconductor device is an N-type laterally diffused metal oxide semiconductor device.
  • the first doping type is P type and the second doping type is N type.
  • the laterally diffused metal oxide semiconductor device may also be a P-type laterally diffused metal oxide semiconductor device, the first doping type is N type and the second doping type is P type.
  • embodiments of the present application provide a method for preparing a laterally diffused metal oxide semiconductor device.
  • the preparation method of the laterally diffused metal oxide semiconductor device includes the following steps:
  • the structure of the substrate 10 is shown in FIG. 5 .
  • the material of the substrate 10 may be monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon-on-insulator (SOI) or low-temperature polycrystalline silicon (Low-temperature silicon). Temperature Poly-Silicon, LTPS), etc., or other materials known to those skilled in the art, the substrate 10 can provide a supporting foundation for the structural layer on the substrate 10.
  • the substrate 10 includes a base layer 11 and an epitaxial layer 12 located on the base layer 11 .
  • S100 The step of providing a substrate, which may include the following steps:
  • the base layer 11 is a P-type semiconductor.
  • S120 Form a heavily doped region in the base layer.
  • N-type ions can be implanted into the base layer 11 through ion implantation to form the heavily doped region 13 .
  • S130 Form an epitaxial layer on the base layer.
  • the epitaxial layer 12 can be grown on the base layer 11 by vapor phase epitaxy or molecular beam epitaxy.
  • the substrate 10 can be formed through the above steps. After the substrate 10 is formed, the following steps may also be included:
  • S140 Form a buried layer in the substrate.
  • P-type ions can be implanted into the epitaxial layer 12 through ion implantation to form the buried layer 15 , and the buried layer 15 is used to deplete the drift region 30 .
  • S150 Form an isolation area in the substrate.
  • N-type ions can be implanted into the epitaxial layer 12 through ion implantation to form two isolation regions 14 .
  • the two isolation regions 14 are located on both sides of the buried layer 15 and are connected to the heavily doped region 13 .
  • the isolation region 14 and the heavily doped region 13 form an isolation cover, and the main device of the laterally diffused metal oxide semiconductor device 1 is located in the isolation cover.
  • the structure after the buried layer 15 and the isolation region 14 are formed is shown in FIG. 5 .
  • this step may include the following steps:
  • the mask layer may be a photoresist layer or a hard mask layer such as a silicon nitride layer or a carbon layer.
  • S220 Pattern the mask layer to obtain a patterned mask layer.
  • the patterned mask layer has an opening, and the opening exposes the substrate and defines the shape and position of the trench.
  • S220 Etch the substrate based on the patterned mask layer to form trenches in the substrate.
  • isolation grooves 17 may also be formed on the surface of the substrate 10 , and the isolation grooves 17 mainly play an isolation role.
  • the structure after the trench 16 is formed is shown in Figure 6 .
  • the trench 16 includes a first side wall 16a and a bottom wall 16b that are interconnected.
  • the number of grooves 16 may be two, the two grooves 16 are spaced apart, and the two side walls of the two grooves 16 that are close to each other are first side walls 16 a.
  • the cross-sectional shape of the groove 16 may be an inverted trapezoid, a rectangle, a semicircle, etc.
  • S300 Form a dielectric layer on the substrate to cover at least part of the first sidewall and part of the bottom wall connected to the first sidewall.
  • the structure of the dielectric layer 20 after formation is shown in FIG. 8 .
  • the dielectric layer 20 is made of silicon dioxide. It can be understood that the dielectric layer 20 may cover only part of the first side wall 16a, or may cover the entire first side wall 16a. This embodiment of the present application takes the dielectric layer 20 covering the entire first side wall 16a as an example for description.
  • a drift area is formed in the substrate, and trenches and dielectric layers are arranged around the drift area. Specifically, N-type ions may be implanted into the epitaxial layer 12 through ion implantation to form the drift region 30 .
  • the structure of the drift region 30 after formation is shown in FIG. 9 .
  • the substrate 10 between the two trenches 16 is equivalent to a bump.
  • the drift region 30 is located within the bump and extends toward the buried layer 15 , and part of the drift region 30 is located between the two trenches 16 . bottom.
  • the embodiment of the present application is equivalent to "stretching" part of the drift region 30 in the direction away from the substrate 10, so that the drift region 30 is "stretched". Part of the drift region 30 extends in the vertical direction (thickness direction of the substrate 10).
  • N-type ions can also be implanted in the isolation region 14 to form the first doping region 141 , and a side of the isolation region 14 away from the drift region 30 can be lined with P-type ions are implanted into the bottom 10 to form the second doped region 18 , and N-type ions are implanted into the top of the drift region 30 (the area close to the surface of the substrate 10 ) to form the buffer region 31 in the drift region 30 .
  • the buffer region 31 is also a part of the drift region 30 , but the doping concentration of the buffer region 31 is greater than the doping concentration of other regions in the drift region 30 (regions other than the buffer region 31 ).
  • the substrate 10 may be annealed.
  • the annealing process can repair the lattice loss caused to the substrate 10 during the ion implantation process and activate the doping ions.
  • a rapid thermal annealing (RTA) process can be used to anneal the substrate 10 after ion implantation.
  • RTA rapid thermal annealing
  • the rapid thermal annealing process has a shorter annealing time and can avoid long-term high temperature. Doping ion diffusion, and reducing the instantaneous enhanced diffusion of doping ions.
  • S500 Form a gate electrode on the substrate, and place the gate electrode around the drift region.
  • the structure after the gate 40 is formed is shown in Figure 12. It can be seen from the figure that the gate 40 covers part of the surface of the dielectric layer 20 and extends toward the bottom wall 16 b of the trench 16 to cover part of the bottom wall 16 b of the trench 16 . It can be understood that the gate 40 not only covers the surface of the dielectric layer 20 on the side facing away from the substrate 10 , but also covers part of the surface of the bottom wall 16 b of the trench 16 .
  • the method for preparing a laterally diffused metal oxide semiconductor device is to arrange the trench 16 around the drift region 30, which is equivalent to "stretching" part of the drift region 30 so that the part of the drift region 30 extends in the vertical direction. , which can ensure the performance of the laterally diffused metal oxide semiconductor device 1 and at the same time reduce the lateral size of the laterally diffused metal oxide semiconductor device 1 to a large extent.
  • the dielectric layer 20 is also made to cover the first sidewall 16a and part of the bottom wall 16b to achieve a large area coverage of the drift region 30 by the dielectric layer 20.
  • the portion of the gate 40 covering the dielectric layer 20 serves as a field plate.
  • the portion of the gate 40 covering the dielectric layer 20 assists the depletion of the drift region 30 from around the drift region 30, which can effectively reduce the peak electric field on the surface of the drift region 30 and improve the drift.
  • the critical breakdown electric field of the region 30 can be flexibly adjusted while reducing the on-resistance of the laterally diffused metal oxide semiconductor device 1.
  • the on-resistance of the laterally diffused metal oxide semiconductor device 1 can be improved while reducing the on-resistance. breakdown voltage.
  • the breakdown voltage of the existing laterally diffused metal oxide semiconductor device Assuming that the breakdown voltage of the existing laterally diffused metal oxide semiconductor device is used as the standard value, then the breakdown voltage of the laterally diffused metal oxide semiconductor device 1 of the present application has a "margin". Therefore, in the technology of the present application, In the solution, the on-resistance can be reduced by increasing the doping concentration of the drift region 30 or reducing the size of the laterally diffused metal oxide semiconductor device 1. While reducing the on-resistance, the on-resistance of the laterally diffused metal oxide semiconductor device 1 can be reduced.
  • the breakdown voltage is reduced until the breakdown voltage of the laterally diffused metal oxide semiconductor device 1 reaches a standard value, so as to flexibly adjust the breakdown voltage of the laterally diffused metal oxide semiconductor device 1 while reducing the on-resistance.
  • the present application can achieve lower on-resistance under the same breakdown voltage.
  • the laterally diffused metal oxide semiconductor device 1 provided by the present application can ensure a higher breakdown voltage while reducing the on-resistance.
  • S300 The step of forming a dielectric layer on a substrate to cover at least part of the first sidewall and part of the bottom wall connected to the first sidewall specifically includes the following steps:
  • S310 Use high-temperature oxide deposition technology to form a first oxide layer on the substrate.
  • the structure of the first oxide layer 21 after formation is shown in FIG. 7 .
  • S320 Etch the first oxide layer to form a dielectric layer.
  • the first oxide layer 21 may be etched through a dry etching or wet etching process.
  • the structure of the dielectric layer 20 after formation is shown in FIG. 8 .
  • S300 the step of forming a dielectric layer on a substrate to cover at least part of the first sidewall and part of the bottom wall connected to the first sidewall specifically includes the following steps:
  • S310 Form a mask layer on the surface of the substrate, and expose at least part of the surface of the first side wall and part of the surface of the bottom wall connected to the first side wall.
  • a nitride layer and a photoresist layer may be formed on the surface of the substrate 10 in sequence, and then the nitride layer and the photoresist layer may be etched to expose at least part of the surface of the first sidewall, and with A portion of the surface of the bottom wall to which the first side wall is connected.
  • S320 Form a first oxide layer on the exposed surface of the substrate and the surface of the mask layer.
  • the first oxide layer may be formed through a local thermal oxidation process.
  • S500 forming a gate electrode on the substrate.
  • the step of arranging the gate electrode around the drift region specifically includes the following steps:
  • the second oxide layer 43 can be formed by methods such as dry oxygen oxidation, high temperature oxidation, or wet oxygen oxidation.
  • the structure of the second oxide layer 43 after formation is shown in FIG. 10 .
  • the second oxide layer 43 covers the substrate 10 On the exposed surface and the surface of the dielectric layer 20 , the thickness of the second oxide layer 43 is smaller than the thickness of the dielectric layer 20 .
  • the material of the second oxide layer 43 may be silicon dioxide.
  • S520 Form a polysilicon material layer on the surface of the second oxide layer.
  • the structure of the polysilicon material layer 44 after formation is shown in FIG. 11 .
  • the material of the polysilicon material layer 44 may be polysilicon.
  • S530 Etch the second oxide layer and the polysilicon material layer to form a gate oxide layer and a polysilicon layer.
  • the gate oxide layer 41 and the polysilicon layer 42 form the gate electrode 40, and the structure of the gate electrode 40 after formation is shown in FIG. 12.
  • the second oxide layer 43 and the polysilicon material layer 44 can be etched through a dry etching or wet etching process.
  • S500 forming a gate on the substrate. After the step of arranging the gate around the drift region, the step further includes:
  • S600 Form a body region in the substrate.
  • the body region is disposed in the substrate at the bottom of the trench.
  • the orthographic projection of the gate on the substrate has an overlapping area with the body region.
  • P-type ions can be implanted into the substrate 10 through ion implantation to form the body region 50 .
  • the structure after the body region 50 is formed is shown in Figure 13. It can be seen from the figure that the body region 50 is disposed in the substrate 10 at the bottom of the trench 16.
  • the orthographic projection of the gate 40 on the substrate 10 is in line with the body region 50. Have overlapping areas.
  • S700 Form a source region in the substrate.
  • the source region is arranged in the body region.
  • the orthographic projection of the gate on the substrate is tangent to the source region or has an overlapping area.
  • the end of the source region close to the drift region is close to the drift region.
  • the orthographic projection of the gate 40 on the substrate 10 is tangent to the source region 51.
  • One end of the source region 51 is close to the drift region 30 and the body region 50 is close to the drift region.
  • There is a spacing between one ends of 30, and the area where the spacing is located is the channel region 60.
  • the source region 51 and the gate electrode 40 do not overlap in the thickness direction of the substrate 10, and the gate electrode 40 and the body region 50
  • the overlapping region in the thickness direction of the substrate 10 is the channel region 60 .
  • the gate 40 can also extend to cover the source region 51 to ensure that the channel can be completely inverted when the laterally diffused metal oxide semiconductor device 1 operates.
  • N-type ions may also be implanted into the first doped region 141 in the substrate 10 to form the first connection region 1411
  • P-type ions may be implanted into the second doped region 18 in the substrate 10 to form the first connection region 1411.
  • the two connection areas 181, the first connection area 1411 and the second connection area 181 can be used as electrical lead-out terminals, and can be connected to corresponding potentials as required. It can be understood that the doping concentration of the first connection region 1411 is greater than the doping concentration of the first doping region 141 , and the doping concentration of the second connection region 181 is greater than the doping concentration of the second doping region 18 .
  • the drift region 30 and the drain region are integrated.
  • N-type ions can also be implanted into the buffer region 31 in the substrate 10 to form a drain extraction region 32.
  • the drain extraction region 32 can be used as an electrical extraction end of the drain electrode.
  • the doping concentration of the drain extraction region 32 is greater than
  • the doping concentration of the buffer region 31 is greater than the doping concentration of the drift region 30.
  • the buffer region 31 can reduce the concentration gradient between the drain extraction region 32 and the drift region 30, and improve the lateral diffusion of metal oxide semiconductor devices 1
  • the breakdown voltage in the on state reduces the on-resistance and the peak electric field in the drain lead-out region 32 .
  • P-type ions can also be implanted into the body region 50 in the substrate 10 to form the body extraction region 52, where the source region 51 and the body extraction region 52 are adjacent, and the doping of the source region 51 and the body extraction region 52 is The concentrations are all greater than the doping concentration of the body region 50 .
  • the source region 51 can be used as an electrical lead-out terminal of the source electrode, and the body lead-out region 52 can be used as an electrical lead-out terminal of the body electrode.
  • the region where the drift region 30 and the gate electrode 40 overlap in the thickness direction of the substrate 10 and do not overlap with the dielectric layer 20 in the thickness direction of the substrate 10 is the carrier accumulation region 70 .
  • steps in the flowchart of FIG. 1 are shown in sequence as indicated by arrows, these steps are not necessarily executed in the order indicated by arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figure 1 may include multiple steps or stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these steps or stages is also It does not necessarily need to be performed sequentially, but may be performed in turn or alternately with other steps or at least part of steps or stages in other steps.
  • the laterally diffused metal oxide semiconductor device 1 includes:
  • the substrate 10 has grooves 16 on its surface.
  • the substrate 10 includes a base layer 11 and an epitaxial layer 12 located on the base layer 11 .
  • the doping type of the base layer 11 is P type, and the trench 16 is located on the epitaxial layer 12 .
  • the cross-sectional shape of the trench 16 is an “inverted trapezoid”, and the trench 16 includes a first side wall 16 a and a bottom wall 16 b that are connected to each other. It can be understood that the cross-sectional shape of the groove 16 can also be rectangular, semicircular, etc.
  • the drift region 30 is located in the substrate 10, and the doping type of the drift region 30 is N-type. Referring to FIG. 9 , the drift region 30 is located in the epitaxial layer 12 , and the trench 16 is provided around the drift region 30 . It should be noted here that, taking the plane where the substrate 10 is located as an example, as shown in FIG. 15 , the plane where the substrate 10 is located has a first direction a and a second direction b. The drift region 30 It has four sides, namely two sides in the first direction a and two sides in the second direction b. “surrounding” means that the groove 16 surrounds at least two sides of the drift region 30 superior.
  • the trench 16 may be surrounding two sides of the drift region 30 in the second direction b, or may be surrounding one side of the drift region 30 in the first direction a, and the drift region 30 is One side in the second direction b.
  • the groove 16 can be a continuous groove or an intermittent groove.
  • the dielectric layer 20 is located on the substrate 10 and is arranged around the drift region 30 .
  • the dielectric layer 20 covers at least part of the first side wall 16a and part of the bottom wall 16b connected to the first side wall 16a.
  • the dielectric layer 20 is made of silicon dioxide.
  • the gate 40 is arranged around the drift region 30 .
  • the gate 40 covers part of the surface of the dielectric layer 20 and extends toward the bottom wall 16 b of the trench 16 to cover part of the bottom wall 16 b of the trench 16 . It can be understood that the gate 40 not only covers part of the surface of the dielectric layer 20 on the side facing away from the substrate 10 , but also covers part of the surface of the bottom wall 16 b of the trench 16 .
  • the laterally diffused metal oxide semiconductor device 1 provided by the embodiment of the present application, by arranging the trench 16 around the drift region 30, it is equivalent to "stretching" part of the drift region 30 so that the part of the drift region 30 extends in the vertical direction. While ensuring the performance of the laterally diffused metal oxide semiconductor device 1, the lateral size of the laterally diffused metal oxide semiconductor device 1 can be reduced to a large extent.
  • the dielectric layer 20 is also made to cover the first sidewall 16a and part of the bottom wall 16b to achieve a large area coverage of the drift region 30 by the dielectric layer 20.
  • the portion of the gate 40 covering the dielectric layer 20 serves as a field plate.
  • the portion of the gate 40 covering the dielectric layer 20 assists the depletion of the drift region 30 from around the drift region 30, which can effectively reduce the peak electric field on the surface of the drift region 30 and improve the drift.
  • the critical breakdown electric field of the region 30 can be flexibly adjusted while reducing the on-resistance of the laterally diffused metal oxide semiconductor device 1.
  • the on-resistance of the laterally diffused metal oxide semiconductor device 1 can be improved while reducing the on-resistance. breakdown voltage.
  • the trench 16 is at least surrounding both sides of the drift region 30 along a first direction a; the first direction a is perpendicular to the thickness direction of the substrate 10 .
  • the gate 40 on the surface of the dielectric layer 20 serves as a field plate to assist the depletion of the drift region 30 on both sides of the drift region 30 along the first direction a, which can effectively reduce the peak electric field on the surface of the drift region 30 and improve the criticality of the drift region 30 breakdown electric field.
  • the number of trenches 16 is two, and the two trenches are located on both sides of the drift region 30 along the first direction a. At least part of the drift region 30 is located in the substrate 10 between the two first sidewalls 16a of the two trenches 16. It can also be understood that the substrate 10 between the two trenches 16 is equivalent to a bump, and the drift region 30 is located within the bump and extends toward the direction close to the buried layer 15 , and some of the drift regions 30 are located on both sides. At the bottom of each trench 16, the cross-sectional shape of the drift region 30 is "convex". It can be seen that the embodiment of the present application is equivalent to "stretching" part of the drift region 30 in the direction away from the substrate 10, so that this part The drift region 30 extends in the vertical direction.
  • the laterally diffused metal oxide semiconductor device 1 further includes:
  • the body region 50 is disposed in the substrate 10 at the bottom of the trench 16, and the doping type of the body region 50 is P type. Among them, an adjacent source region 51 and a body lead-out region 52 are also provided in the body region 50 close to the bottom wall 16b of the trench 16.
  • the source region 51 and the body lead-out region are The doping type of the region 52 is opposite.
  • the doping type of the source region 51 may be N type, and the doping type of the body extraction region 52 may be P type.
  • the source region 51 and the body extraction region 52 are both part of the body region 50 , and the doping concentration of both is greater than that of other regions of the body region 50 (areas in the body region 50 other than the source region 51 and the body extraction region 52 ). concentration.
  • the source region 51 can be used as an electrical lead-out terminal of the source electrode
  • the body lead-out region 52 can be used as an electrical lead-out terminal of the body electrode.
  • the orthographic projection of the gate 40 on the substrate 10 is tangent to the source region 51 .
  • the source region 51 and the gate electrode 40 do not overlap in the thickness direction of the substrate 10 , and the area where the gate electrode 40 and the body region 50 overlap in the thickness direction of the substrate 10 is the channel region 60 .
  • the gate 40 can also extend to cover the source region 51 to ensure that the channel can be completely inverted when the laterally diffused metal oxide semiconductor device 1 operates.
  • the buried layer 15 is located in the epitaxial layer 12 of the substrate 10 and is located on the side of the drift region 30 away from the gate electrode 40 .
  • the doping type of the buried layer 15 is P type, and the buried layer 15 can be used to deplete the drift region 30 .
  • the drain region (not shown) and part of the drift region 30 of the laterally diffused metal oxide semiconductor device 1 are integrally provided, wherein the drain region is located in the substrate 10 and is located away from the gate electrode 40 and the body region 50 side.
  • the top of the drift region 30 (the region close to the surface of the substrate 10) also has a buffer region 31, and the doping type of the buffer region 31 is N-type. It should be noted that the buffer region 31 is also a part of the drift region 30 , but the doping concentration of the buffer region 31 is greater than the doping concentration of other regions in the drift region 30 (regions other than the buffer region 31 ).
  • the top of the buffer region 31 (the area close to the surface of the substrate 10) also has a drain extraction region 32.
  • the doping type of the drain extraction region 32 is N-type, and the drain extraction region 32 can serve as the electrical extraction end of the drain electrode. It should be noted that the doping concentration of the drain extraction region 32 is greater than the doping concentration of the buffer region 31 .
  • the buffer region 31 can reduce the concentration gradient between the drain extraction region 32 and the drift region 30 , increase the breakdown voltage of the laterally diffused metal oxide semiconductor device 1 in the on state, reduce the on-resistance, and reduce the peak electric field of the drain extraction region 32 .
  • the drift region 30 can be adjacent to or spaced apart from the body region 50.
  • the epitaxial layer 12 is also P-type, the area of the epitaxial layer 12 covered by the gate electrode 40 will also be inverted as Conductive channel.
  • the doping concentration of the epitaxial layer 12 is generally low. Although this part of the epitaxial layer 12 serves as the channel region 60 , the turn-on voltage of the laterally diffused metal oxide semiconductor device 1 is still determined by the overlapping region of the gate 40 and the body region 50 .
  • a heavily doped region 13 is also formed in the base layer 11 , and two spaced apart isolation regions 14 are formed in the epitaxial layer 12 .
  • the two isolation regions 14 are located on both sides of the buried layer 15 and are connected with each other.
  • the heavily doped regions 13 are connected.
  • the isolation region 14 and the heavily doped region 13 form an isolation cover, and the main devices of the laterally diffused metal oxide semiconductor device 1 (for example, the drift region 30, the body region 50, the gate 40, etc.) are located in the area surrounded by the isolation cover. .
  • the isolation region 14 also has a first doping region 141, and the first doping region 141 also has a first connection region 1411.
  • the doping of the first doping region 141 and the first connection region 1411 The types are all N-type, and the doping concentration of the first connection region 1411 is greater than the doping concentration of the first doping region 141 .
  • the side of the isolation area 14 away from the drift area 30 is also provided with
  • the second doping region 18 has a second connection region 181 in the second doping region 18.
  • the doping types of the second doping region 18 and the second connection region 181 are both P-type.
  • the doping type of the second connection region 181 is P-type.
  • the impurity concentration is greater than the doping concentration of the second doped region 18 .
  • the first connection area 1411 and the second connection area 181 can be used as electrical leads, and can be connected to corresponding potentials as required.
  • field plates are provided on both sides of the drift region 30, and the field plates on both sides jointly deplete the drift region 30 in the middle, so that the drift region 30 can be better depleted.
  • the peak electric field on the surface of the drift region 30 is reduced to the greatest extent, thereby increasing the critical breakdown electric field of the drift region 30 and thereby increasing the breakdown voltage of the laterally diffused metal oxide semiconductor device 1 . Therefore, the doping concentration of the drift region 30 can be made more concentrated, thereby reducing the on-resistance of the laterally diffused metal oxide semiconductor device 1 and increasing the on-state current of the laterally diffused metal oxide semiconductor device 1 .
  • the same breakdown voltage can be ensured to reduce the size of the laterally diffused metal oxide semiconductor device 1 and improve the overall performance of the laterally diffused metal oxide semiconductor device 1 .
  • the dielectric layer 20 covers the entire first sidewall 16a.
  • the field plate formed by the gate 40 can cover a larger range of the drift region 30 , thereby better depleting the drift region 30 , minimizing the peak electric field on the surface of the drift region 30 , thereby improving the critical voltage of the drift region 30 .
  • the electric field is penetrated, thereby increasing the breakdown voltage of the laterally diffused metal oxide semiconductor device 1 . Therefore, the doping concentration of the drift region 30 can be made more concentrated, thereby reducing the on-resistance of the laterally diffused metal oxide semiconductor device 1 and increasing the on-state current of the laterally diffused metal oxide semiconductor device 1 .
  • the same breakdown voltage can be ensured to reduce the size of the laterally diffused metal oxide semiconductor device 1 and improve the overall performance of the laterally diffused metal oxide semiconductor device 1 .
  • the dielectric layer includes a high-temperature oxidation (HTO) layer.
  • the material of the dielectric layer can be silicon dioxide, which can be prepared through a high-temperature oxidation process.
  • the gate 40 includes a stacked gate oxide layer 41 and a polysilicon layer 42 .
  • the gate oxide layer 41 is located on a side of the polysilicon layer 42 close to the dielectric layer 20 .
  • the gate oxide layer 41 is made of silicon dioxide, and the polysilicon layer 42 is made of polysilicon.
  • the thickness of the dielectric layer 20 is greater than the thickness of the gate oxide layer 41 . In this way, the dielectric layer 20 can withstand a higher electric field and prevent the dielectric layer 20 from being broken down in advance.
  • the outer contour of the orthographic projection of the dielectric layer 20 on the substrate 10 is located within the outer contour of the drift region 30 . It can also be understood that the drift region 30 at the bottom of the trench 16 and the dielectric layer 20 have a non-overlapping region in the thickness direction of the substrate 10 , and the non-overlapping region is the carrier accumulation region 70 , and the field plate formed by the gate 40 There is no depletion effect on the carrier accumulation region 70 .
  • the outer contour of the orthographic projection of the gate 40 on the bottom wall 16 b is located outside the outer contour of the drift region 30 .
  • the gate electrode 40 may extend toward the direction of the body region 50 , thereby having an overlapping area with the body region 50 in the thickness direction of the substrate 10 , and the overlapping area is the channel region 60 .
  • the laterally diffused metal oxide semiconductor device 1 provided by the embodiment of the present application can be used as follows: Two arrangement methods are available for setting.
  • the first arrangement can be considered as a “trench strip” arrangement, that is, the drift region 30 is located in the middle of the laterally diffused metal oxide semiconductor device 1 , and the gate 40 and the body region 50 face toward The directions away from the drift area 30 are arranged in sequence.
  • the trenches 16 can be considered to be intermittent trenches (or the number of trenches 16 is two), that is, the drift region 30 is provided with trenches 16 on both sides of the first direction a.
  • the second arrangement can be considered as a "trench ring" arrangement.
  • the drift region 30 is located at the center of the laterally diffused metal oxide semiconductor device 1, the gate 40 is arranged around the drift region 30, and the body region 50 is disposed around the gate 40 .
  • the groove 16 can be considered as a continuous groove (or the number of the groove 16 is one and the groove 16 is an annular groove).
  • the field plate formed by the gate 40 is located around the drift region 30 . Therefore, the field plate assists the depletion of the drift region 30 around the drift region 30 and can minimize the peak value on the surface of the drift region 30 .
  • electric field thereby increasing the critical breakdown electric field of the drift region 30 and thereby increasing the breakdown voltage of the laterally diffused metal oxide semiconductor device 1 . Therefore, the doping concentration of the drift region 30 can be made more concentrated, thereby reducing the on-resistance of the laterally diffused metal oxide semiconductor device 1 and increasing the on-state current of the laterally diffused metal oxide semiconductor device 1 .
  • the same breakdown voltage can be ensured to reduce the size of the laterally diffused metal oxide semiconductor device 1 and improve the overall performance of the laterally diffused metal oxide semiconductor device 1 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种横向扩散金属氧化物半导体器件及其制备方法，该横向扩散金属氧化物半导体器件（1）包括：衬底（10），设有沟槽（16）；漂移区（30），位于衬底（10）内；其中，沟槽（16）围绕漂移区（30）设置；介质层（20），位于衬底（10）上，且围绕漂移区（30）设置；其中，介质层（20）覆盖第一侧壁（16a）的至少部分，以及与第一侧壁（16a）连接的部分底壁（16b）；栅极（40），围绕漂移区（30）设置。其中，栅极（40）覆盖介质层（20）的部分表面，且向沟槽（16）的底壁（16b）延伸以覆盖沟槽（16）的部分底壁（16b）。

Description

横向扩散金属氧化物半导体器件及其制备方法
相关申请
本申请要求2022年8月15日申请的，申请号为2022109763154，名称为“横向扩散金属氧化物半导体器件及其制备方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种横向扩散金属氧化物半导体器件及其制备方法。
背景技术
随着半导体技术的不断发展，横向双扩散金属氧化物半导体(Lateral Double-diffuse MOS，LDMOS)器件的应用也日益广泛，同时对横向扩散金属氧化物半导体器件的性能提出了更高的要求。但对于横向扩散金属氧化物半导体器件，不可避免地存在降低导通电阻与保证较高的击穿电压之间的技术矛盾，难以进一步提升器件性能。此外，在提升器件性能的同时器件尺寸也难以进一步缩小，进而影响整个芯片面积的降低。
发明内容
基于此，有必要针对上述至少一个问题，提供一种横向扩散金属氧化物半导体器件及其制备方法。
为了实现上述至少一个目的，一方面，本申请提供了一种横向扩散金属氧化物半导体器件，包括：
衬底，设有沟槽，所述沟槽包括第一侧壁以及与所述第一侧壁连接的底壁；
漂移区，位于所述衬底内，所述沟槽围绕所述漂移区设置；
介质层，位于所述衬底上，且围绕所述漂移区设置；所述介质层覆盖至少部分所述第一侧壁，以及与所述第一侧壁连接的部分所述底壁；
栅极，围绕所述漂移区设置，所述栅极覆盖部分所述介质层，且向所述底壁延伸以覆盖部分所述底壁。
在其中一个实施例中，所述沟槽至少围设在所述漂移区沿第一方向的两侧；所述第一 方向垂直于所述衬底的厚度方向。
在其中一个实施例中，所述沟槽的数量为两个，两个所述沟槽位于所述漂移区沿第一方向的两侧；
至少部分所述漂移区位于该两个所述沟槽的两个所述第一侧壁之间的所述衬底内。
在其中一个实施例中，所述介质层覆盖全部所述第一侧壁。
在其中一个实施例中，所述横向扩散金属氧化物半导体器件还包括：
体区，设置于所述沟槽底部的所述衬底内；所述栅极在所述衬底上的正投影与所述体区具有重叠区域；
源区，设置于所述体区内；所述栅极在所述衬底上的正投影与所述源区相切或具有重叠区域，且所述源区靠近所述漂移区的一端与所述体区靠近所述漂移区的一端之间具有间距；
漏区，位于所述衬底内，位于所述栅极远离所述源区的一侧；
埋层，位于所述衬底内，且位于所述漂移区远离所述栅极的一侧。
在其中一个实施例中，所述介质层包括高温氧化层。
在其中一个实施例中，所述栅极包括层叠设置的栅极氧化物层和多晶硅层，所述栅极氧化物层位于所述多晶硅层靠近所述介质层的一侧，所述介质层的厚度大于所述栅极氧化物层的厚度。
在其中一个实施例中，所述介质层在所述衬底上的正投影的外轮廓位于所述漂移区的外轮廓内。
在其中一个实施例中，所述栅极在所述底壁上的正投影的外轮廓位于所述漂移区的外轮廓外。
本申请还提供了一种横向扩散金属氧化物半导体器件的制备方法，包括：
提供衬底；
于所述衬底上形成沟槽；所述沟槽包括相互连接的第一侧壁和底壁；
于所述衬底上形成介质层，以覆盖至少部分所述第一侧壁，以及与所述第一侧壁连接的部分所述底壁；
于所述衬底内形成漂移区，所述沟槽和所述介质层均围绕所述漂移区设置；
于所述衬底上形成栅极，所述栅极围绕所述漂移区设置；所述栅极覆盖部分所述介质层，且向所述底壁延伸以覆盖部分所述底壁。
在其中一个实施例中，所述于所述衬底上形成介质层，以覆盖至少部分所述第一侧壁，以及与所述第一侧壁连接的部分所述底壁的步骤包括：
采用高温氧化物沉积技术在所述衬底上形成第一氧化物层；
对所述第一氧化物层进行刻蚀以形成所述介质层。
在其中一个实施例中，所述于所述衬底上形成介质层，以覆盖至少部分所述第一侧壁，以及与所述第一侧壁连接的部分所述底壁的步骤包括：
于所述衬底的表面形成掩膜层，并裸露所述第一侧壁的至少部分表面，以及与所述第一侧壁连接的所述底壁的部分表面；
于所述衬底的裸露表面，以及所述掩膜层的表面上形成第一氧化物层；
去除所述掩膜层以及位于所述掩膜层表面的第一氧化物层，以形成所述介质层。
在其中一个实施例中，所述于所述衬底的表面形成沟槽的步骤之前，还包括；
于所述衬底内形成埋层。
在其中一个实施例中，所述于所述衬底上形成栅极，所述栅极围绕所述漂移区设置的步骤包括：
于所述衬底的表面形成第二氧化物层；
于所述第二氧化物层的表面形成多晶硅材料层；
对所述第二氧化物层和所述多晶硅材料层进行刻蚀，以形成栅极氧化物层和多晶硅层。
在其中一个实施例中，所述于所述衬底上形成栅极，所述栅极围绕所述漂移区设置的步骤之后，还包括：
于所述衬底内形成体区，所述体区设置于所述沟槽底部的所述衬底内，所述栅极在所述衬底上的正投影与所述体区具有重叠区域；
于所述衬底内形成源区，所述源区设置于所述体区内，所述栅极在所述衬底上的正投影与所述源区相切或具有重叠区域，且所述源区靠近所述漂移区的一端与所述体区靠近所述漂移区的一端之间具有间距。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据公开的附图获得其他的附图。
图1为本申请一实施例中提供的横向扩散金属氧化物半导体器件的制备方法的流程图；
图2为本申请一实施例中提供的横向扩散金属氧化物半导体器件的制备方法中介质层的一种制备流程图；
图3为本申请一实施例中提供的横向扩散金属氧化物半导体器件的制备方法中介质层的另一种制备流程图；
图4为本申请一实施例中提供的横向扩散金属氧化物半导体器件的制备方法中栅极的制备流程图；
图5至图13为本申请一实施例中提供的横向扩散金属氧化物半导体器件的制备方法的过程中器件结构的截面结构示意图；
图14为图13中的横向扩散金属氧化物半导体器件的部分截面结构示意图；
图15为本申请一实施例中提供的一种横向扩散金属氧化物半导体器件的俯视结构示意图；
图16为本申请一实施例中提供的另一种横向扩散金属氧化物半导体器件的俯视结构示意图。
附图标记说明：
1-横向扩散金属氧化物半导体器件；10-衬底；11-基底层；12-外延层；13-重掺杂区；14-隔离区；141-第一掺杂区；1411-第一连接区；15-埋层；16-沟槽；16a-第一侧壁；16b-底壁；17-隔离槽；18-第二掺杂区；181-第二连接区；20-介质层；21-第一氧化物层；30-漂移区；31-缓冲区；32-漏引出区；40-栅极；41-栅极氧化物层；42-多晶硅层；43-第二氧化物层；44-多晶硅材料层；50-体区；51-源区；52-体引出区；60-沟道区；70-积累区。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述申请的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本申请的范围。
本申请实施例提供一种横向扩散金属氧化物半导体器件的制备方法及横向扩散金属氧化物半导体器件，能够在降低导通电阻的同时灵活调整横向扩散金属氧化物半导体器件的击穿电压，尤其可在降低导通电阻的同时提高横向扩散金属氧化物半导体器件的击穿电压。
在本申请实施例中，该横向扩散金属氧化物半导体器件以N型横向扩散金属氧化物半导体器件为例，第一掺杂类型为P型且第二掺杂类型为N型。在其他实施例中，该横向扩散金属氧化物半导体器件也可以为P型横向扩散金属氧化物半导体器件，第一掺杂类型为N型且第二掺杂类型为P型。
第一方面，本申请实施例提供一种横向扩散金属氧化物半导体器件的制备方法。参照图1所示，该横向扩散金属氧化物半导体器件的制备方法，包括如下步骤：
S100：提供衬底。衬底10的结构参照图5所示，该衬底10的材料可以是单晶硅、多晶硅、无定型硅、锗硅化合物、绝缘体上硅(Silicon-On-Insulator，SOI)或低温多晶硅(Low Temperature Poly-Silicon，LTPS)等，或者本领域技术人员已知的其他材料，该衬底10可以为衬底10上的结构层提供支撑基础。在本申请实施例中，衬底10包括基底层11以及位于基底层11上的外延层12。
S100：提供衬底的步骤，具体可以包括如下步骤：
S110：提供本体层。其中，基底层11为P型半导体。
S120：于基底层内形成重掺杂区。其中，可以通过离子注入的方式在基底层11内注入N型离子以形成重掺杂区13。
S130：于基底层上形成外延层。其中，可以通过气相外延或分子束外延的方式在基底层11上生长外延层12。
通过上述步骤可以形成衬底10。形成衬底10后，还可以包括如下步骤：
S140：于衬底内形成埋层。其中，可以通过离子注入的方式在外延层12内注入P型离子以形成埋层15，埋层15用于耗尽漂移区30。
S150：于衬底内形成隔离区。其中，可以通过离子注入的方式在外延层12内注入N型离子以形成两个隔离区14。两个隔离区14位于埋层15的两侧，且与重掺杂区13相接。这样，隔离区14与重掺杂区13形成隔离罩，横向扩散金属氧化物半导体器件1的主器件位于隔离罩内。埋层15和隔离区14形成后的结构如图5所示。
隔离区14形成后，可以进行如下步骤：
S200：于衬底上形成沟槽。其中，该步骤可以包括如下步骤：
S210：于衬底表面形成掩膜层。掩膜层可以为光刻胶层或氮化硅层、碳层等硬掩膜层。
S220：对掩膜层进行图形化处理以得到图形化掩膜层，图形化掩膜层内具有开口，开口暴露出衬底并定义出沟槽的形状及位置。
S220：基于图形化掩膜层对衬底进行刻蚀，以于衬底内形成沟槽。
S230：去除图形化掩膜层。沟槽16形成后的结构如图6所示。
可以理解的是，在该步骤中，还可以在衬底10的表面形成隔离槽17，隔离槽17主要起隔离作用。沟槽16形成后的结构如图6所示。作为一个实施例，沟槽16包括相互连接的第一侧壁16a和底壁16b。沟槽16的数量可以为两个，两个沟槽16间隔设置，且两个沟槽16相互靠近的两个侧壁为第一侧壁16a。可以理解的是，沟槽16的截面形状可以为倒梯形、矩形、半圆形等。
S300：于衬底上形成介质层，以覆盖至少部分第一侧壁，以及与第一侧壁连接的部分底壁。介质层20形成后的结构如图8所示。介质层20的材质包括二氧化硅。可以理解的是，介质层20可以只覆盖第一侧壁16a的部分，也可以覆盖全部第一侧壁16a，本申请实施例以介质层20覆盖全部第一侧壁16a为例进行说明。
S400：于衬底内形成漂移区，沟槽和介质层均围绕漂移区设置。具体地，可以通过离子注入的方式在外延层12内注入N型离子以形成漂移区30。漂移区30形成后的结构如图9所示。两个沟槽16之间的衬底10相当于一个凸起，漂移区30位于该凸起内，并且朝靠近埋层15的方向延伸，且还有部分漂移区30位于两个沟槽16的底部。相较于已有的平面型横向扩散金属氧化物半导体器件的漂移区周围无沟槽的结构，本申请实施例相当于将部分漂移区30沿背离衬底10的方向“拉伸”，使该部分漂移区30沿垂直方向(衬底10的厚度方向)延伸。
可以理解的是，请继续参照图9所示，在该步骤中，还可以在隔离区14内注入N型离子以形成第一掺杂区141，在隔离区14远离漂移区30的一侧衬底10内注入P型离子以形成第二掺杂区18，在漂移区30内的顶部(靠近衬底10表面的区域)注入N型离子以在漂移区30内形成缓冲区31。这里需要说明的是，缓冲区31也是漂移区30的一部分，只是缓冲区31的掺杂浓度大于漂移区30中其他区域(缓冲区31以外的区域)的掺杂浓度。
可以理解的是，在离子注入后，可以对衬底10进行退火处理。退火处理可以修复离子注入过程中对衬底10造成的晶格损失并激活掺杂离子。具体的可以采用快速热退火(Rapid thermal Annealing，RTA)工艺对离子注入后的衬底10进行退火处理，快速热退火工艺相较于普通的退火工艺退火处理时间短，可以避免长时间的高温导致掺杂离子扩散，以及减小掺杂离子的瞬间增强扩散。
S500：于衬底上形成栅极，栅极围绕漂移区设置。栅极40形成后的结构如图12所示， 从图中可以看出，栅极40覆盖介质层20的部分表面，且向沟槽16的底壁16b延伸以覆盖沟槽16的部分底壁16b。可以理解为：栅极40不仅覆盖介质层20背离衬底10一侧的表面，还覆盖沟槽16的部分底壁16b的表面。
本申请实施例提供的横向扩散金属氧化物半导体器件的制备方法，通过将沟槽16围绕漂移区30设置，相当于将部分漂移区30“拉伸”，使该部分漂移区30沿垂直方向延伸，可确保在横向扩散金属氧化物半导体器件1性能的同时较大程度上缩小横向扩散金属氧化物半导体器件1的横向尺寸。此外，还使介质层20覆盖第一侧壁16a以及部分底壁16b，以实现介质层20对漂移区30的大面积覆盖，栅极40覆盖在介质层20上的部分作为场板。又因沟槽16设置在漂移区30周围，栅极40覆盖在介质层20上的部分从漂移区30的周围辅助漂移区30的耗尽，可有效降低漂移区30表面的峰值电场，提高漂移区30的临界击穿电场，从而可在降低导通电阻的同时灵活调整横向扩散金属氧化物半导体器件1的击穿电压，尤其可在降低导通电阻的同时提高横向扩散金属氧化物半导体器件1的击穿电压。
假设以已有的横向扩散金属氧化物半导体器件的击穿电压为标准值，那么，本申请的横向扩散金属氧化物半导体器件1的击穿电压有“裕量”，因此，在本申请的技术方案中，可以通过增加漂移区30的掺杂浓度或减小横向扩散金属氧化物半导体器件1尺寸的方式来降低导通电阻，在降低导通电阻的同时横向扩散金属氧化物半导体器件1的击穿电压降低，直至横向扩散金属氧化物半导体器件1的击穿电压到达标准值，以实现在降低导通电阻的同时灵活调整横向扩散金属氧化物半导体器件1的击穿电压。此外，与已有的横向扩散金属氧化物半导体器件相比，本申请在同样的击穿电压下能够实现较低的导通电阻。换句话说，本申请提供的横向扩散金属氧化物半导体器件1，在降低导通电阻的同时能够保证较高的击穿电压。
在其中一个实施例中，参照图2所示，S300：于衬底上形成介质层，以覆盖至少部分第一侧壁，以及与第一侧壁连接的部分底壁的步骤具体包括以下步骤：
S310：采用高温氧化物沉积技术在衬底上形成第一氧化物层。第一氧化物层21形成后的结构如图7所示。
S320：对第一氧化物层进行刻蚀以形成介质层。其中，可以通过干法刻蚀或湿法刻蚀的工艺对第一氧化物层21进行刻蚀。介质层20形成后的结构如图8所示。
在另一个实施例中，参照图3所示，S300：于衬底上形成介质层，以覆盖至少部分第一侧壁，以及与第一侧壁连接的部分底壁的步骤具体包括以下步骤：
S310：于衬底的表面形成掩膜层，并裸露第一侧壁的至少部分表面，以及与第一侧壁连接的底壁的部分表面。
作为一个实施例，可以依次在衬底10的表面形成氮化物层和光刻胶层，然后对氮化物层和光刻胶层进行刻蚀，以裸露第一侧壁的至少部分表面，以及与第一侧壁连接的底壁的部分表面。
S320：于衬底的裸露表面，以及掩膜层的表面上形成第一氧化物层。其中，可以通过局部热氧化的工艺形成第一氧化物层。
S330：去除掩膜层以及位于掩膜层表面的第一氧化物层，以形成介质层。
在其中一个实施例中，参照图4所示，S500：于衬底上形成栅极，栅极围绕漂移区设置的步骤具体包括以下步骤：
S510：于衬底的表面形成第二氧化物层。其中，可以通过干氧氧化、高温氧化或湿氧氧化等方法形成第二氧化物层43，第二氧化物层43形成后的结构如图10所示，第二氧化物层43覆盖衬底10裸露的表面以及介质层20的表面，第二氧化物层43的厚度小于介质层20的厚度。第二氧化物层43的材质可以是二氧化硅。
S520：于第二氧化物层的表面形成多晶硅材料层。多晶硅材料层44形成后的结构如图11所示。多晶硅材料层44的材质可以是多晶硅。
S530：对第二氧化物层和多晶硅材料层进行刻蚀，以形成栅极氧化物层和多晶硅层。栅极氧化物层41和多晶硅层42形成栅极40，栅极40形成后的结构如图12所示。其中，可以通过干法刻蚀或湿法刻蚀的工艺对第二氧化物层43和多晶硅材料层44进行刻蚀。
在其中一个实施例中，S500：于衬底上形成栅极，栅极围绕漂移区设置的步骤之后，还包括：
S600：于衬底内形成体区，体区设置于沟槽底部的衬底内，栅极在衬底上的正投影与体区具有重叠区域。可以通过离子注入的方式在衬底10内注入P型离子以形成体区50。体区50形成后的结构如图13所示，从图中可以看出，体区50设置于沟槽16底部的衬底10内，栅极40在衬底10上的正投影与体区50具有重叠区域。
S700：于衬底内形成源区，源区设置于体区内，栅极在衬底上的正投影与源区相切或具有重叠区域，且源区靠近漂移区的一端与体区靠近漂移区的一端之间具有间距。参照图13和图14所示，从图中可以看出，栅极40在衬底10上的正投影与源区51相切，源区51靠近漂移区30的一端与体区50靠近漂移区30的一端之间具有间距，该间距所在的区域为沟道区60，也可以理解为：源区51与栅极40在衬底10的厚度方向上不重叠，并且栅极40与体区50在衬底10的厚度方向上重叠的区域为沟道区60。在另一实施例中，栅极40也可以延伸覆盖至源区51上方，确保横向扩散金属氧化物半导体器件1工作时沟道能够完全反型。
在该步骤中，还可以在衬底10内的第一掺杂区141注入N型离子以形成第一连接区1411，在衬底10内的第二掺杂区18注入P型离子以形成第二连接区181，第一连接区1411和第二连接区181可以作为电性引出端，根据需求接相应的电位。可以理解的是，第一连接区1411的掺杂浓度大于第一掺杂区141的掺杂浓度，第二连接区181的掺杂浓度大于第二掺杂区18的掺杂浓度。
在本申请实施例中，漂移区30和漏区为一体。在该步骤中，还可以在衬底10内的缓冲区31注入N型离子以形成漏引出区32，漏引出区32可以作为漏极的电性引出端，漏引出区32的掺杂浓度大于缓冲区31的掺杂浓度，缓冲区31的掺杂浓度大于漂移区30的掺杂浓度，缓冲区31可以降低漏引出区32与漂移区30的浓度梯度，提高横向扩散金属氧化物半导体器件1开通状态的击穿电压，减小导通电阻，降低漏引出区32的峰值电场。
在该步骤中，还可以在衬底10内的体区50注入P型离子以形成体引出区52，其中，源区51和体引出区52邻接，源区51和体引出区52的掺杂浓度均大于体区50的掺杂浓度。源区51可以作为源极的电性引出端，体引出区52可以作为体极的电性引出端。
参照图14所示，漂移区30与栅极40在衬底10的厚度方向上重叠，且与介质层20在衬底10的厚度方向上不重叠的区域为载流子积累区70。
应该理解的是，虽然图1的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
第二方面，本申请实施例提供一种横向扩散金属氧化物半导体器件。参照图13和图14所示，该横向扩散金属氧化物半导体器件1包括：
衬底10，其表面设有沟槽16。其中，衬底10包括基底层11以及位于基底层11上的外延层12，基底层11的掺杂类型为P型，沟槽16位于外延层12上。参照图6所示，沟槽16的截面形状为“倒梯形”，沟槽16包括相互连接的第一侧壁16a和底壁16b。可以理解的是，沟槽16的截面形状还可以为矩形、半圆形等。
漂移区30，位于衬底10内，漂移区30的掺杂类型为N型。参照图9所示，漂移区30位于外延层12内，沟槽16围绕漂移区30设置。这里需要说明的是，以衬底10所在的平面为例，参照图15所示，衬底10所在的平面具有第一方向a和第二方向b，漂移区30 具有四个侧边，分别为第一方向a上的两个侧边，以及第二方向b上的两个侧边，“围绕”指沟槽16围设在漂移区30的至少两个侧边上。示例性的，沟槽16可以围设在漂移区30在第二方向b上的两个侧边，也可以围设在漂移区30在第一方向a上的一个侧边，以及漂移区30在第二方向b上的一侧侧边。沟槽16可以为一连续的沟槽，也可以为间断的沟槽。
介质层20，位于衬底10上，且围绕漂移区30设置。其中，介质层20覆盖至少部分第一侧壁16a，以及与第一侧壁16a连接的部分底壁16b。介质层20的材质包括二氧化硅。
栅极40，围绕漂移区30设置。其中，栅极40覆盖介质层20的部分表面，且向沟槽16的底壁16b延伸以覆盖沟槽16的部分底壁16b。可以理解为：栅极40不仅覆盖介质层20背离衬底10一侧的部分表面，还覆盖沟槽16的部分底壁16b的表面。
本申请实施例提供的横向扩散金属氧化物半导体器件1，通过将沟槽16围绕漂移区30设置，相当于将部分漂移区30“拉伸”，使该部分漂移区30沿垂直方向延伸，可确保在横向扩散金属氧化物半导体器件1性能的同时较大程度上缩小横向扩散金属氧化物半导体器件1的横向尺寸。此外，还使介质层20覆盖第一侧壁16a以及部分底壁16b，以实现介质层20对漂移区30的大面积覆盖，栅极40覆盖在介质层20上的部分作为场板。又因沟槽16设置在漂移区30周围，栅极40覆盖在介质层20上的部分从漂移区30的周围辅助漂移区30的耗尽，可有效降低漂移区30表面的峰值电场，提高漂移区30的临界击穿电场，从而可在降低导通电阻的同时灵活调整横向扩散金属氧化物半导体器件1的击穿电压，尤其可在降低导通电阻的同时提高横向扩散金属氧化物半导体器件1的击穿电压。
在其中一个实施例中，沟槽16至少围设在漂移区30沿第一方向a的两侧；第一方向a垂直于衬底10的厚度方向。这样，介质层20表面的栅极40作为场板在漂移区30沿第一方向a的两侧辅助漂移区30的耗尽，可有效降低漂移区30表面的峰值电场，提高漂移区30的临界击穿电场。
在其中一个实施例中，沟槽16的数量为两个，两个沟槽位于漂移区30沿第一方向a的两侧。至少部分漂移区30位于该两个沟槽16的两个第一侧壁16a之间的衬底10内。也可以这样理解：两个沟槽16之间的衬底10相当于一个凸起，漂移区30位于该凸起内，并且朝靠近埋层15的方向延伸，且还有部分漂移区30位于两个沟槽16的底部，漂移区30的截面形状为“凸”字型，可以看出，本申请实施例相当于将部分漂移区30沿背离衬底10的方向“拉伸”，使该部分漂移区30沿垂直方向延伸。
在其中一个实施例中，参照图14所示，横向扩散金属氧化物半导体器件1还包括：
体区50，设置于沟槽16底部的衬底10内，体区50的掺杂类型为P型。其中，体区50内靠近沟槽16的底壁16b处还设置有邻接的源区51和体引出区52，源区51和体引出 区52的掺杂类型相反，源区51的掺杂类型可以为N型，体引出区52的掺杂类型可以为P型。源区51和体引出区52均为体区50的一部分，二者的掺杂浓度均大于体区50的其他区域(体区50中源区51和体引出区52以外的区域)的掺杂浓度。源区51可以作为源极的电性引出端，体引出区52可以作为体极的电性引出端。
栅极40在衬底10上的正投影与源区51相切。源区51靠近漂移区30的一端与体区50靠近漂移区30的一端之间具有间距，该间距所在的区域为沟道区60。也可以理解为：源区51与栅极40在衬底10的厚度方向上不重叠，并且栅极40与体区50在衬底10的厚度方向上重叠的区域为沟道区60。在另一实施例中，栅极40也可以延伸覆盖至源区51上方，确保横向扩散金属氧化物半导体器件1工作时沟道能够完全反型。
埋层15，位于衬底10的外延层12内，且位于漂移区30远离栅极40的一侧。埋层15的掺杂类型为P型，埋层15可以用于耗尽漂移区30。
在本申请实施例中，横向扩散金属氧化物半导体器件1的漏区(未示出)和部分漂移区30一体设置，其中，漏区位于衬底10内，且位于栅极40远离体区50的一侧。漂移区30内的顶部(靠近衬底10表面的区域)还具有缓冲区31，缓冲区31的掺杂类型为N型。需要说明的是，缓冲区31也是漂移区30的一部分，只是缓冲区31的掺杂浓度大于漂移区30中其他区域(缓冲区31以外的区域)的掺杂浓度。同时，缓冲区31内的顶部(靠近衬底10表面的区域)还具有漏引出区32，漏引出区32的掺杂类型为N型，漏引出区32可以作为漏极的电性引出端。需要说明的是，漏引出区32的掺杂浓度大于缓冲区31的掺杂浓度。缓冲区31可以降低漏引出区32与漂移区30的浓度梯度，提高横向扩散金属氧化物半导体器件1开通状态的击穿电压，减小导通电阻，降低漏引出区32的峰值电场。
需要说明的是，漂移区30可以和体区50相邻或间隔设置，二者间隔设置时，由于外延层12也为P型，栅极40所覆盖的外延层12的区域也会反型作为导电沟道。外延层12的掺杂浓度一般较低，该部分外延层12虽然作为沟道区60，但是横向扩散金属氧化物半导体器件1的开启电压还是由栅极40和体区50的交叠区域所决定。
在其中一个实施例中，基底层11内还形成有重掺杂区13，外延层12内形成有两个间隔设置的隔离区14，两个隔离区14位于埋层15的两侧，且与重掺杂区13相接。这样，隔离区14与重掺杂区13形成隔离罩，横向扩散金属氧化物半导体器件1的主器件(例如：漂移区30、体区50和栅极40等)位于隔离罩围成的区域内。
在其中一个实施例中，隔离区14内还具有第一掺杂区141，第一掺杂区141内还具有第一连接区1411，第一掺杂区141和第一连接区1411的掺杂类型均为N型，第一连接区1411的掺杂浓度大于第一掺杂区141的掺杂浓度。隔离区14远离漂移区30的一侧还设有 第二掺杂区18，第二掺杂区18内设有第二连接区181，第二掺杂区18和第二连接区181的掺杂类型均为P型，第二连接区181的掺杂浓度大于第二掺杂区18的掺杂浓度。第一连接区1411和第二连接区181可以作为电性引出端，根据需求接相应的电位。
在本申请实施例中，漂移区30的两侧均设置有场板(栅极40)，两侧的场板共同耗尽位于中间的漂移区30，从而可以更好地耗尽漂移区30，最大程度降低漂移区30表面的峰值电场，从而提高漂移区30的临界击穿电场，进而提高横向扩散金属氧化物半导体器件1的击穿电压。因此，可以使漂移区30的掺杂浓度更浓，进而可以减小横向扩散金属氧化物半导体器件1的导通电阻，增加横向扩散金属氧化物半导体器件1的通态电流。或者，也可以保证相同的击穿电压，来缩小横向扩散金属氧化物半导体器件1的尺寸，提高横向扩散金属氧化物半导体器件1的整体性能。
在其中一个实施例中，介质层20覆盖全部第一侧壁16a。这样，可以使栅极40形成的场板覆盖较大范围的漂移区30，从而可以更好地耗尽漂移区30，最大程度降低漂移区30表面的峰值电场，从而提高漂移区30的临界击穿电场，进而提高横向扩散金属氧化物半导体器件1的击穿电压。因此，可以使漂移区30的掺杂浓度更浓，进而可以减小横向扩散金属氧化物半导体器件1的导通电阻，增加横向扩散金属氧化物半导体器件1的通态电流。或者，也可以保证相同的击穿电压，来缩小横向扩散金属氧化物半导体器件1的尺寸，提高横向扩散金属氧化物半导体器件1的整体性能。
在其中一个实施例中，介质层包括高温氧化(High-TemperatureOxidation，HTO)层。介质层的材质可以是二氧化硅，具体可以通过高温氧化工艺制备而成。
在其中一个实施例中，栅极40包括层叠设置的栅极氧化物层41和多晶硅层42，栅极氧化物层41位于多晶硅层42靠近介质层20的一侧。栅极氧化物层41的材质包括二氧化硅，多晶硅层42的材质包括多晶硅。作为一个实施例，介质层20的厚度大于栅极氧化物层41的厚度。这样，可以使介质层20承受较高的电场，避免介质层20被提前击穿。
在其中一个实施例中，介质层20在衬底10上的正投影的外轮廓位于漂移区30的外轮廓内。也可以理解为：位于沟槽16底部的漂移区30与介质层20在衬底10的厚度方向上具有未重叠区域，该未重叠区域为载流子积累区70，栅极40形成的场板对载流子积累区70无耗尽作用。
在其中一个实施例中，栅极40在底壁16b上的正投影的外轮廓位于漂移区30的外轮廓外。这样，栅极40可以向体区50的方向延伸，从而与体区50在衬底10的厚度方向上具有重叠区域，该重叠区域为沟道区60。
需要说明的是，本申请实施例提供的横向扩散金属氧化物半导体器件1可以按照以下 两种排布方式进行设置。参照图15所示，第一种排布方式可以认为是“沟槽条形”排布，即：漂移区30位于横向扩散金属氧化物半导体器件1的中间位置，栅极40和体区50朝远离漂移区30的方向依次排布。同时，在该排布方式中，可以认为沟槽16为间断沟槽(或者认为沟槽16的数量为两个)，即漂移区30在第一方向a的两侧均设置沟槽16。参照图16所示，第二种排布方式可以认为是“沟槽环形”排布，漂移区30位于横向扩散金属氧化物半导体器件1的中心位置，栅极40围绕漂移区30设置，体区50围绕栅极40设置。同时，在该排布方式中，可以认为沟槽16为连续沟槽(或者认为沟槽16的数量为一个，沟槽16为环形沟槽)。
在第二种设置方式中，栅极40形成的场板位于漂移区30的四周，因此，场板在漂移区30的四周辅助漂移区30的耗尽，可以最大程度降低漂移区30表面的峰值电场，从而提高漂移区30的临界击穿电场，进而提高横向扩散金属氧化物半导体器件1的击穿电压。因此，可以使漂移区30的掺杂浓度更浓，进而可以减小横向扩散金属氧化物半导体器件1的导通电阻，增加横向扩散金属氧化物半导体器件1的通态电流。或者，也可以保证相同的击穿电压，来缩小横向扩散金属氧化物半导体器件1的尺寸，提高横向扩散金属氧化物半导体器件1的整体性能。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种横向扩散金属氧化物半导体器件，其中，包括：
    衬底，设有沟槽，所述沟槽包括第一侧壁以及与所述第一侧壁连接的底壁；
    漂移区，位于所述衬底内；所述沟槽围绕所述漂移区设置；
    介质层，位于所述衬底上，且围绕所述漂移区设置；所述介质层覆盖至少部分所述第一侧壁，以及与所述第一侧壁连接的部分所述底壁；
    栅极，围绕所述漂移区设置；所述栅极覆盖部分所述介质层，且向所述底壁延伸以覆盖部分所述底壁。
  2. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，所述沟槽至少围设在所述漂移区沿第一方向的两侧；所述第一方向垂直于所述衬底的厚度方向。
  3. 根据权利要求2所述的横向扩散金属氧化物半导体器件，其中，所述沟槽的数量为两个，两个所述沟槽位于所述漂移区沿第一方向的两侧；
    至少部分所述漂移区位于该两个所述沟槽的两个所述第一侧壁之间的所述衬底内。
  4. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，所述介质层覆盖全部所述第一侧壁。
  5. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，所述横向扩散金属氧化物半导体器件还包括：
    体区，设置于所述沟槽底部的所述衬底内；所述栅极在所述衬底上的正投影与所述体区具有重叠区域；
    源区，设置于所述体区内；所述栅极在所述衬底上的正投影与所述源区相切或具有重叠区域，且所述源区靠近所述漂移区的一端与所述体区靠近所述漂移区的一端之间具有间距；
    漏区，位于所述衬底内，且位于所述栅极远离所述源区的一侧；
    埋层，位于所述衬底内，且位于所述漂移区远离所述栅极的一侧。
  6. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，所述介质层包括高温氧化层。
  7. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，所述栅极包括层叠设置的栅极氧化物层和多晶硅层，所述栅极氧化物层位于所述多晶硅层靠近所述介质层的一侧，所述介质层的厚度大于所述栅极氧化物层的厚度。
  8. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，所述介质层在所 述衬底上的正投影的外轮廓位于所述漂移区的外轮廓内。
  9. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，所述栅极在所述底壁上的正投影的外轮廓位于所述漂移区的外轮廓外。
  10. 一种横向扩散金属氧化物半导体器件的制备方法，其中，包括：
    提供衬底；
    于所述衬底上形成沟槽；所述沟槽包括相互连接的第一侧壁和底壁；
    于所述衬底上形成介质层，以覆盖至少部分所述第一侧壁，以及与所述第一侧壁连接的部分所述底壁；
    于所述衬底内形成漂移区，所述沟槽和所述介质层均围绕所述漂移区设置；
    于所述衬底上形成栅极，所述栅极围绕所述漂移区设置；所述栅极覆盖部分所述介质层，且向所述底壁延伸以覆盖部分所述底壁。
  11. 根据权利要求10所述的横向扩散金属氧化物半导体器件的制备方法，其中，所述于所述衬底上形成介质层，以覆盖至少部分所述第一侧壁，以及与所述第一侧壁连接的部分所述底壁的步骤包括：
    采用高温氧化物沉积技术在所述衬底上形成第一氧化物层；
    对所述第一氧化物层进行刻蚀以形成所述介质层。
  12. 根据权利要求10所述的横向扩散金属氧化物半导体器件的制备方法，其中，所述于所述衬底上形成介质层，以覆盖至少部分所述第一侧壁，以及与所述第一侧壁连接的部分所述底壁的步骤包括：
    于所述衬底的表面形成掩膜层，并裸露所述第一侧壁的至少部分表面，以及与所述第一侧壁连接的所述底壁的部分表面；
    于所述衬底的裸露表面，以及所述掩膜层的表面上形成第一氧化物层；
    去除所述掩膜层以及位于所述掩膜层表面的第一氧化物层，以形成所述介质层。
  13. 根据权利要求10所述的横向扩散金属氧化物半导体器件的制备方法，其中，所述于所述衬底的表面形成沟槽的步骤之前，还包括；
    于所述衬底内形成埋层。
  14. 根据权利要求10所述的横向扩散金属氧化物半导体器件的制备方法，其中，所述于所述衬底上形成栅极，所述栅极围绕所述漂移区设置的步骤包括：
    于所述衬底的表面形成第二氧化物层；
    于所述第二氧化物层的表面形成多晶硅材料层；
    对所述第二氧化物层和所述多晶硅材料层进行刻蚀，以形成栅极氧化物层和多晶硅层。
  15. 根据权利要求10所述的横向扩散金属氧化物半导体器件的制备方法，其中，所述于所述衬底上形成栅极，所述栅极围绕所述漂移区设置的步骤之后，还包括：
    于所述衬底内形成体区，所述体区设置于所述沟槽底部的所述衬底内，所述栅极在所述衬底上的正投影与所述体区具有重叠区域；
    于所述衬底内形成源区，所述源区设置于所述体区内，所述栅极在所述衬底上的正投影与所述源区相切或具有重叠区域，且所述源区靠近所述漂移区的一端与所述体区靠近所述漂移区的一端之间具有间距。
PCT/CN2023/106985 2022-08-15 2023-07-12 横向扩散金属氧化物半导体器件及其制备方法 WO2024037259A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210976315.4 2022-08-15
CN202210976315.4A CN117637840A (zh) 2022-08-15 2022-08-15 横向扩散金属氧化物半导体器件及其制备方法

Publications (1)

Publication Number Publication Date
WO2024037259A1 true WO2024037259A1 (zh) 2024-02-22

Family

ID=89940670

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/106985 WO2024037259A1 (zh) 2022-08-15 2023-07-12 横向扩散金属氧化物半导体器件及其制备方法

Country Status (2)

Country Link
CN (1) CN117637840A (zh)
WO (1) WO2024037259A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386211A (zh) * 2010-08-31 2012-03-21 无锡华润上华半导体有限公司 Ldmos器件及其制造方法
CN103325672A (zh) * 2012-07-20 2013-09-25 成都芯源系统有限公司 双栅介电层及半导体器件的制造方法
CN109148583A (zh) * 2018-07-11 2019-01-04 上海华虹宏力半导体制造有限公司 Snldmos器件及其制造方法
US20200119189A1 (en) * 2018-10-16 2020-04-16 Richtek Technology Corporation High voltage device and manufacturing method thereof
CN111540785A (zh) * 2020-05-13 2020-08-14 上海华虹宏力半导体制造有限公司 Ldmos器件及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386211A (zh) * 2010-08-31 2012-03-21 无锡华润上华半导体有限公司 Ldmos器件及其制造方法
CN103325672A (zh) * 2012-07-20 2013-09-25 成都芯源系统有限公司 双栅介电层及半导体器件的制造方法
CN109148583A (zh) * 2018-07-11 2019-01-04 上海华虹宏力半导体制造有限公司 Snldmos器件及其制造方法
US20200119189A1 (en) * 2018-10-16 2020-04-16 Richtek Technology Corporation High voltage device and manufacturing method thereof
CN111540785A (zh) * 2020-05-13 2020-08-14 上海华虹宏力半导体制造有限公司 Ldmos器件及其制造方法

Also Published As

Publication number Publication date
CN117637840A (zh) 2024-03-01

Similar Documents

Publication Publication Date Title
JP4123636B2 (ja) 炭化珪素半導体装置及びその製造方法
TWI475614B (zh) 溝渠裝置結構及製造
US7714383B2 (en) Semiconductor device
US7982224B2 (en) Semiconductor device with silicon carbide epitaxial layer including dopant profiles for reducing current overconcentration
TWI487110B (zh) 半導體裝置及其製造方法
TWI289355B (en) Trench MOSFET and method of manufacturing same
US9698248B2 (en) Power MOS transistor and manufacturing method therefor
CN107425046B (zh) 一种ldmos器件及其制作方法
JP4490094B2 (ja) トレンチ金属酸化膜半導体電界効果トランジスタ素子の製造方法
KR102228655B1 (ko) 고전압 집적소자 및 그 제조방법
KR20010098551A (ko) 반도체장치 및 그 제조방법
US20120098056A1 (en) Trench device structure and fabrication
CN114566540A (zh) Ldmos器件及其制造方法
WO2020073459A1 (zh) 半导体器件及其制造方法及包括该器件的电子设备
US11296222B2 (en) Lateral double diffused metal oxide semiconductor and method of fabricating same
JP3344381B2 (ja) 半導体装置及びその製造方法
US10615079B2 (en) Semiconductor device and method for manufacturing the same
CN117153888A (zh) 半导体器件及其制造方法
WO2024037259A1 (zh) 横向扩散金属氧化物半导体器件及其制备方法
CN111584634A (zh) 半导体器件及其制造方法
CN108695387B (zh) Mosfet、mosfet制备方法以及电子设备
WO2021147626A1 (zh) 半导体器件及其制备方法
CN108511346B (zh) Ldmos器件的制造方法
TWI517393B (zh) 半導體裝置及其製作方法
CN111785617A (zh) Ldmos的制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23854164

Country of ref document: EP

Kind code of ref document: A1