WO2024037115A1 - 芯片封装结构、封装方法、电子设备 - Google Patents

芯片封装结构、封装方法、电子设备 Download PDF

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Publication number
WO2024037115A1
WO2024037115A1 PCT/CN2023/097529 CN2023097529W WO2024037115A1 WO 2024037115 A1 WO2024037115 A1 WO 2024037115A1 CN 2023097529 W CN2023097529 W CN 2023097529W WO 2024037115 A1 WO2024037115 A1 WO 2024037115A1
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WIPO (PCT)
Prior art keywords
chip
packaging
layer
bare chip
bridge
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PCT/CN2023/097529
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English (en)
French (fr)
Inventor
张训迪
贺凡
陶军磊
王家明
陈诚
黄超
陈志伟
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华为技术有限公司
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Publication of WO2024037115A1 publication Critical patent/WO2024037115A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies

Definitions

  • Embodiments of the present application relate to the chip field, and in particular, to a chip packaging structure, packaging method, and electronic equipment.
  • chip packaging technology As semiconductor technology advances with each passing day, chip packaging technology also continues to develop.
  • the main function of chip packaging is to seal and protect the chip, and to realize the interconnection between chips and between the internal circuits of the chips and the external circuits.
  • the performance of chip packaging directly affects the service life of the chip.
  • the chip packaging structure is prone to warping, which affects the mechanical strength of the packaging structure and increases the risk of reliability failure.
  • Embodiments of the present application provide a chip packaging structure, packaging method, and electronic equipment. Aimed at improving the problem of chip packaging structure warpage.
  • a chip packaging structure in a first aspect, includes a first packaging layer, a bridge bare chip, a second packaging layer, a bonding pad and a plurality of first bare chips;
  • the first packaging layer has a first accommodation cavity, Opposing the first surface and the second surface, the first accommodation cavity has a first opening located on the first surface;
  • the bridge die is located in the first accommodation cavity;
  • the second packaging layer is disposed close to the first surface; a plurality of The first bare chips are all located in the second packaging layer; the plurality of first bare chips are electrically connected to the bridge bare chip;
  • the bonding pad is located on the second surface; the bridge bare chip or the first bare chip is connected to the The pads are electrically connected; the thermal expansion coefficients of the first packaging layer and the bridge bare chip are the same.
  • the deformation difference between the first packaging layer and the bridged bare chip is small, and the first packaging layer is not easy to warp. It can reduce the impact of warpage on the mechanical reliability of the chip packaging structure, thereby improving the reduction in electrical performance reliability caused by the reduction in mechanical reliability and extending the service life of the chip packaging structure.
  • the difference in thermal expansion coefficient between the first packaging layer and the bridge bare chip is less than 6 ⁇ 10 -6 /°C. As a result, the difference in thermal expansion coefficient is small. Under the same temperature difference, the deformation amounts of the first packaging layer and the bridged bare chip are close to the same. The probability of warpage is small, the impact on mechanical reliability is small, and the electrical performance is stable.
  • the material of the first encapsulation layer includes at least one of silicon, ceramics, and glass. Therefore, under the same temperature difference, the deformation amounts of the material of the first packaging layer and the substrate bridging the bare chip are close to each other, and they are less likely to warp. In addition, when polymer materials are coated on the surface of silicon, ceramics or glass, the probability of process problems such as flow marks and non-wetting is small, the yield of the chip packaging structure is improved, and the reliability is increased.
  • the chip packaging structure further includes: a first plastic compound; the first plastic compound is located in the gap between the bridge bare chip and the inner wall of the first accommodation cavity. Therefore, the first plastic encapsulation material can fix the bridge bare chip and improve the structural reliability. In addition, the first plastic encapsulating material can improve the sealing performance of the bridged bare chip and improve its electrical performance stability.
  • the first bare chip is buried in the second packaging layer. Therefore, the packaging process cost of the first bare chip is lower.
  • the second encapsulation layer includes a second plastic encapsulation material. Therefore, the second packaging layer has better sealing performance on the first bare chip, which is beneficial to the stable operation of the first bare chip.
  • the second packaging layer includes a second accommodation cavity, the second accommodation cavity has a second opening located on the surface of the second packaging layer, and the first bare chip is located on the first In the second accommodation cavity, the thermal expansion coefficients of the second packaging layer and the first bare chip are the same. Therefore, when the temperature changes, the deformation amounts of the first bare chip and the second packaging layer are smaller. Both the first packaging layer and the second packaging layer are not easy to warp, further stabilizing the structural reliability of the chip packaging structure.
  • the difference in thermal expansion coefficient between the second packaging layer and the first bare chip is less than 6 ⁇ 10 -6 /°C. As a result, there is almost no difference in deformation between the second packaging layer and the first bare chip, and the deformation after temperature changes is small.
  • the material of the second encapsulation layer includes at least one of silicon, ceramics, and glass. Therefore, the difference between the thermal expansion coefficient of silicon, ceramics or glass and the thermal expansion coefficient of the first bare chip is small, making it less likely to warp.
  • the chip packaging structure further includes: a third plastic compound; the third plastic compound is located in the gap between the first bare chip and the inner wall of the second accommodation cavity. Therefore, the third plastic sealing material can stabilize the first bare chip, and the third plastic sealing material can provide a sealed environment for the first bare chip, providing an excellent environment for the stable operation of the first bare chip.
  • the chip packaging structure further includes: a first electrical connector; the first electrical connector penetrates the first surface and the second surface; the first bare chip passes through the The first electrical connector is electrically connected to the soldering pad. Therefore, the first electrical connection member can provide more wiring solutions between the first bare chip and the bonding pad.
  • the bridge bare chip it is beneficial to reduce the distribution density of the first electrical connectors in the first packaging layer, thus contributing to reducing the manufacturing cost of the chip packaging structure.
  • the first accommodation cavity also has a third opening located on the second surface. Therefore, when installing the bare bridge chip, the bare bridge chip can be placed into the first accommodation cavity through the first opening or the third opening, which facilitates the installation of the bare bridge chip.
  • the bare bridge chip can be directly connected to the pad, which is beneficial to shortening the length of the signal path. , reduce losses.
  • the first accommodation cavity has a bottom wall, and the bottom wall is opposite to the first opening. Therefore, the bottom wall has the function of carrying the bridge bare chip, which is beneficial to the positioning of the bridge bare chip.
  • the bottom wall can receive the raw material of the first plastic sealing material and reduce the overflow of the first plastic sealing material.
  • the chip packaging structure further includes: a second electrical connector that penetrates the second surface and the surface of the bottom wall; the bridge bare chip passes through the The second electrical connector is electrically connected to the soldering pad. Therefore, the second electrical connection member can shorten the path between the bridging bare chip and the bonding pad, thereby reducing loss.
  • the second electrical connector provides more connection options for structures with bottom walls.
  • the chip packaging structure further includes: a first wiring layer, the first wiring layer is located between the second packaging layer and the first packaging layer, and the bridging bare chip passes through The first wiring layer is electrically connected to the first bare chip. Therefore, the first wiring layer provides more interconnection space for the first die and the bridge die.
  • the chip packaging structure further includes: a second wiring layer located between the bonding pad and the first packaging layer, the bridge bare chip, the soldering layer The disks are electrically connected to the second wiring layer. Therefore, the second wiring layer provides more interconnection space for the chip packaging structure.
  • a chip packaging method including:
  • the bridge bare chip is placed in the first accommodation cavity of the first packaging layer; wherein the first packaging layer has the first accommodation cavity and opposite first and second surfaces; the first accommodation cavity has a structure located on the first accommodation cavity. a first opening on a surface; the first encapsulation layer and the bridge bare chip have the same thermal expansion coefficient;
  • a second packaging layer is formed on the first surface; a plurality of first bare chips are formed in the second packaging layer, and the plurality of first bare chips are electrically connected to the bridge bare chip;
  • a bonding pad is formed on the second surface, and the bridge bare chip or the first bare chip is electrically connected to the bonding pad.
  • the method before placing the bridge bare chip in the first receiving cavity of the first packaging layer, the method further includes:
  • a first electrical connector is formed in the first packaging layer, and the first electrical connector penetrates the first surface and the second surface; the first bare chip is electrically connected to the pad through the first electrical connector.
  • the method before placing the bridge bare chip in the first receiving cavity of the first packaging layer, the method further includes:
  • a second electrical connector is formed on the first packaging layer; wherein the second electrical connector penetrates the bottom wall of the first accommodation cavity and the second surface, the bottom wall is opposite to the first opening, and the bridge bare chip The second electrical connector is electrically connected to the pad.
  • the method further includes:
  • the first plastic compound is filled in the gap between the bridge die and the inner wall of the first accommodation cavity.
  • the method before forming the second encapsulation layer on the first surface, the method further includes:
  • the bridge bare chip is electrically connected to the first bare chip through the first wiring layer.
  • forming the second encapsulation layer on the first surface includes:
  • the second packaging layer is formed; wherein the first bare chip is buried in the second packaging layer.
  • forming the second encapsulation layer on the first surface includes:
  • the first bare chip is placed in the second accommodation cavity of the second packaging layer, and the second accommodation cavity is provided with a second opening; the thermal expansion coefficients of the first bare chip and the second packaging layer are the same;
  • placing the first bare chip in the second receiving cavity of the second packaging layer further includes:
  • a third plastic compound is formed in the gap between the first bare chip and the inner wall of the second accommodation cavity.
  • the method before forming the bonding pad on the second surface, the method further includes:
  • a second wiring layer is formed on the second surface, wherein the bridge bare chip and the pad are electrically connected to the second wiring layer.
  • an electronic device in a third aspect, includes a printed circuit board and any chip packaging structure provided in the first aspect; wherein the soldering pad is electrically connected to the printed circuit board. Since the warpage problem of the chip packaging structure is improved, its mechanical reliability is improved, and the electrical performance is better guaranteed during use. Correspondingly, the performance of electronic equipment is also guaranteed.
  • Figure 1 is a schematic structural diagram of a communication system provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a printed circuit board assembly provided by an embodiment of the present application.
  • Figure 3a is a schematic diagram of an example chip packaging structure.
  • Figure 3b is a schematic diagram of another example of a chip packaging structure.
  • FIG. 4 is a schematic structural diagram of a chip packaging structure provided by an embodiment of the present application.
  • Figure 5a is a schematic structural diagram of a first packaging layer and a first electrical connector provided in Embodiment 1 of the present application.
  • Figure 5b is a schematic structural diagram of another chip packaging structure provided in Embodiment 1 of the present application.
  • Figure 6a is a packaging flow chart of Example 1 of the chip packaging structure provided in Embodiment 1 of the present application.
  • Figure 6b is a schematic structural diagram of the first encapsulation layer in Figure 6a.
  • Figure 6c is a schematic structural diagram after executing S1 shown in Figure 6a.
  • Figure 6d is a schematic structural diagram after executing S2 shown in Figure 6a.
  • Figure 6e is a schematic structural diagram after executing S3 shown in Figure 6a.
  • Figure 7a is a packaging flow chart of Example 2 of the chip packaging structure provided in Embodiment 1 of the present application.
  • Figure 7b is a schematic structural diagram after executing S4 in Figure 7a.
  • Figure 7c is a flow chart of S4 in Figure 7a.
  • Figure 7d is a schematic structural diagram before executing S4 in Figure 7a.
  • Figure 7e is a schematic structural diagram after executing S41 in Figure 7c.
  • Figure 8a is a packaging flow chart of Example 3 of the chip packaging structure provided in Embodiment 1 of the present application.
  • Figure 8b is a schematic structural diagram after executing S5 in Figure 8a.
  • Figure 9a is a packaging flow chart of Example 4 of the chip packaging structure provided in Embodiment 1 of the present application.
  • Figure 9b is a schematic structural diagram after executing S6 in Figure 9a.
  • Figure 10a is a packaging flow chart of Example 5 of the chip packaging structure provided in Embodiment 1 of the present application.
  • Figure 10b is a schematic structural diagram after executing S7 in Figure 10a.
  • Figure 11a is a flow chart of the preparation of the second encapsulation layer in the structure shown in Figure 4.
  • Figure 11b is a schematic structural diagram after executing S21 in Figure 11a.
  • Figure 11c is a flow chart for the preparation of S2 in the structure shown in Figure 5b.
  • Figure 11d is a schematic structural diagram after executing S23 in Figure 11c.
  • Figure 11e is a schematic structural diagram after executing S24 in Figure 11c.
  • Figure 12a is a schematic structural diagram of the chip packaging structure provided in Embodiment 2 of the present application.
  • Figure 12b is another structural schematic diagram of the chip packaging structure provided in Embodiment 2 of the present application.
  • FIG. 13a is a schematic structural diagram of the first packaging layer in the chip packaging structure shown in FIG. 12a.
  • Figure 13b is a packaging flow chart provided in Embodiment 2 of the present application.
  • Figure 13c is a schematic structural diagram after executing S8 in Figure 13b.
  • FIG. 1 is a schematic structural diagram of a communication system 001 provided by an embodiment of the present application. Please refer to Figure 1 .
  • the communication system 001 includes a base station 002 and a terminal device 003.
  • the base station 002 and the terminal device 003 are connected through communication.
  • the terminal device 003 can be a mobile phone (mobile phone), a tablet computer (pad), a personal digital assistant (personal digital assistant, PDA), a television, or a smart wearable product.
  • the terminal device 003 can be a mobile phone (mobile phone), a tablet computer (pad), a personal digital assistant (personal digital assistant, PDA), a television, or a smart wearable product.
  • smart watches, smart bracelets virtual reality (VR) terminal equipment, augmented reality (AR) terminal equipment, rechargeable small household appliances (such as soymilk machines, sweeping robots), drones, Radar, aerospace equipment and vehicle-mounted equipment, etc.
  • VR virtual reality
  • AR augmented reality
  • rechargeable small household appliances such as soymilk machines, sweeping robots
  • drones Radar
  • aerospace equipment and vehicle-mounted equipment etc.
  • Terminal equipment 003 includes printed circuit boards (PCB), and chip packaging components provided on the printed circuit board.
  • PCB is used to carry system-level chips, chip packaging components, etc., and is used with system-level chips, chip packaging components, etc. Electrical connection.
  • Base station 002 includes, for example, a printed circuit board assembly.
  • FIG. 2 is a schematic structural diagram of a printed circuit board assembly 10 provided by an embodiment of the present application. Please refer to FIG. 2 .
  • the printed circuit board assembly 10 includes a printed circuit board 20 , a chip packaging structure 100 , a thermal conductor 30 and a heat sink 40 .
  • the thermal conductive member 30 is connected to the printed circuit board 20.
  • the thermal conductive member 30 and the printed circuit board 20 are surrounded by a cavity 201.
  • the chip packaging structure 100 is located in the cavity 201.
  • the chip packaging structure 100 is electrically connected to the printed circuit board 20 for heat dissipation.
  • the heat sink 40 is connected to the heat conducting member 30, and the heat sink 40 and the printed circuit board 20 are respectively located on opposite sides of the heat conducting member 30.
  • the thermal conductive member 30 may be a metal cover, and the metal cover is fastened with the printed circuit board 20 to form the cavity 201.
  • the thermal conductor 30 is used to conduct the heat generated by the chip packaging structure 100 to the heat sink 40 and dissipate the heat through the heat sink 40 .
  • the printed circuit board 20 is used for electrical connection with other electronic components.
  • the chip packaging structure 100 will affect the reliability of the chip performance, and the reliability of the chip performance will affect the electrical performance of the printed circuit board assembly 10, thereby affecting the operation of the equipment, such as affecting the operation of the terminal equipment 003 or the base station 002.
  • FIG 3a is a schematic diagram of an example chip packaging structure 01.
  • the chip packaging structure 01 includes: a silicon wafer 11, a wiring layer 12, a copper via 13, a bare chip 14 and a dielectric layer 15.
  • the silicon wafer 11, The wiring layer 12 and the dielectric layer 15 are stacked in sequence.
  • the bare chip 14 is located in the dielectric layer 15 . Both the silicon chip 11 and the dielectric layer 15 are provided with copper vias 13 . The copper vias 13 are electrically connected to the wiring layer 12 , and the pins of the bare chip 14 are electrically connected to the wiring layer 12 .
  • copper vias 13 need to be provided on the silicon wafer 11. As the size of the bare chip 14 increases, the density of the copper vias 13 increases, and the copper vias 13 and the wiring layer 12 interconnection has increased process requirements, resulting in higher costs and lower yields.
  • FIG 3b is a schematic diagram of another example of a chip packaging structure 01.
  • the chip packaging structure 01 includes a first dielectric layer 21, a bottom bare chip 22, a wiring layer 12, a copper via 13, and a second dielectric layer. 23 and the upper bare chip 24.
  • the first dielectric layer 21 , the wiring layer 12 , and the second dielectric layer 23 are stacked in sequence. Copper vias 13 are provided in both the first dielectric layer 21 and the second dielectric layer 23 . The copper vias 13 are connected to the wiring layer 12 For connection, the bottom die chip 22 is located in the first dielectric layer 21 , and the upper die chip 24 is located in the second dielectric layer 23 .
  • the material of the first dielectric layer 21 is a polymer material such as epoxy resin
  • the underlying bare chip 22 includes a silicon substrate and an epitaxial layer grown on the surface of the silicon substrate.
  • the material of the second dielectric layer 23 refers to the first dielectric layer 21.
  • the structure of the upper bare chip 24 refer to the bottom bare chip 22, which will not be described again here.
  • Embodiments of the present application provide a chip packaging structure, aiming to improve the yield of the chip packaging structure.
  • This chip packaging structure can be used in the above-mentioned base station 002 or terminal equipment 003.
  • FIG. 4 is a schematic structural diagram of a chip packaging structure 100 provided by an embodiment of the present application.
  • the chip packaging structure 100 includes a bridge die 101 , a first die 102 , a first packaging layer 110 , a second packaging layer 120 and a bonding pad 130 .
  • the bridge die 101 is located in the first packaging layer 110 , the first die 102 is located in the second packaging layer 120 , and the first packaging layer 110 is located between the second packaging layer 120 and the bonding pad 130 .
  • the first bare chip 102 is electrically connected to the bridge bare chip 101
  • the first bare chip 102 or the bridge bare chip 101 is electrically connected to the bonding pad 130 .
  • the first die 102 may be electrically connected to the pad 130 through the bridge die 101 .
  • some components of the first bare chip 102 may not be electrically connected to the bonding pad 130 through the bridge bare chip 101.
  • the signal from the ground terminal of the first bare chip 102 is directly connected to the bonding pad 130 without passing through the bridge bare chip 101.
  • the components of the bridge bare chip 101 may be electrically connected to the bonding pad 130 through the first bare chip 102 , or may be directly electrically connected to the bonding pad 130 without passing through the first bare chip 102 .
  • the thermal expansion coefficients of the first packaging layer 110 and the bridge die 101 are the same.
  • the thermal expansion coefficient of the bridge die 101 may be approximated by the thermal expansion coefficient of the substrate material of the bridge die 101 .
  • the thermal expansion coefficients of the first packaging layer 110 and the substrate of the bridge die 101 are the same.
  • the thermal expansion coefficient of the first encapsulation layer 110 is close to that of silicon.
  • the thermal expansion coefficient of the first encapsulation layer 110 in the embodiment in which the thermal expansion coefficient of the first encapsulation layer 110 is anisotropic, the thermal expansion coefficient of the first encapsulation layer 110 along the stacking direction of the first encapsulation layer 110 to the second encapsulation layer 120 The same coefficient of thermal expansion as the bridge die 101.
  • thermal expansion coefficients are not limited to being absolutely identical in numerical value, and may be close to the same.
  • the difference in thermal expansion coefficient between the two is less than 20 ⁇ 10 -6 /°C.
  • the difference in thermal expansion coefficient between the two is 0, 6 ⁇ 10 -6 /°C, 2 ⁇ 10 -6 /°C, 3 ⁇ 10 -6 /°C, 5 ⁇ 10 -6 / °C, 6 ⁇ 10 -6 / °C, 7 ⁇ 10 -6 /°C, 8 ⁇ 10 -6 /°C, 9 ⁇ 10 -6 /°C, 10 ⁇ 10 -6 /°C, 15 ⁇ 10 -6 /°C, 18 ⁇ 10 -6 /°C or 20 ⁇ 10 -6 /°C and so on.
  • the thermal expansion coefficients of the first packaging layer 110 and the bridge bare chip 101 are the same, when the temperature changes, the difference in deformation amount between the two is small, which can effectively improve the warpage of the chip packaging structure 100 caused by the large difference in deformation amount between the two, and enhance the The mechanical reliability of the chip packaging structure 100 improves the electrical performance reliability caused by the reduced mechanical reliability and extends its service life.
  • the number of bridge dies 101 is less than the number of first dies 102 .
  • the chip content in the first packaging layer 110 is smaller than the chip content in the second packaging layer 120 .
  • the warpage of the first packaging layer 110 with a small chip content is more severe than the warpage of the second packaging layer 120 . Therefore, improving the warpage of the first packaging layer 110 has a better effect on improving the warpage of the chip packaging structure 100 .
  • the first packaging layer 110 with a small chip content has a small number of first receiving cavities 113 and the process cost is relatively low.
  • the material of the first encapsulation layer 110 includes at least one of silicon, ceramics, and glass.
  • the material of the first packaging layer 110 may be a silicon wafer, and the difference in thermal expansion coefficient between it and the bridge bare chip 101 whose substrate is silicon is very small.
  • the material of the first packaging layer 110 may be glass or ceramics. The difference in thermal expansion coefficient between the glass or ceramics and the bridge bare chip 101 is small, and the cost of the glass or ceramics is low.
  • the material of the first encapsulation layer 110 may be a mixture of silicon and ceramic, which is beneficial to reducing the cost of the first encapsulation layer 110 .
  • the silicon material may be monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, etc., which is not limited in the embodiment of the present application.
  • the deformation amount difference between the first packaging layer 110 and the bridge bare chip 101 is small.
  • the probability of process problems such as flow marks and non-wetting is small, the yield of the chip packaging structure 100 is improved, and the reliability is increased.
  • the first encapsulation layer 110 is made of silicon, ceramics, glass or other materials. After other layers (such as encapsulation layers and wiring layers) are laminated on the surface of the first encapsulation layer 110, the surface of the layer structure laminated on the first encapsulation layer 110 is Good surface finish. Surfaces with good coplanarity provide excellent conditions for good electrical contact of electrical connectors. For example, after the wiring layer surface with good coplanarity is connected to the electrical connector, the connection position has good contact and is not easy to separate, which is beneficial to reliability.
  • the embodiment of the present application does not limit the number of bridge bare chips 101.
  • the number of bridge bare chips 101 may be one, two, three or more.
  • the embodiment of the present application does not limit the structure of the bare bridge chip 101.
  • the signal terminal and the ground terminal of the bridge bare chip 101 are located on the same side, or the signal terminals and ground terminals of the bridge bare chip 101 are distributed on both sides.
  • the first encapsulation layer 110 has a first surface 111 , a second surface 112 and a first receiving cavity 113 .
  • the first surface 111 and the second surface 112 are arranged oppositely, and the first receiving cavity 113 has a first opening 114 located on the first surface 111 .
  • the first receiving cavity 113 also has a third opening 115 located on the second surface 112 .
  • the first accommodation cavity 113 is a groove structure, the first accommodation cavity 113 has a bottom wall 116, and the bottom wall 116 is opposite to the first surface 111.
  • the bridge bare chip 101 is located in the first receiving cavity 113.
  • the bridge bare chip 101 can be placed in the first receiving cavity 113 through the first opening 114.
  • the embodiment of the present application does not limit the shape of the first receiving cavity 113.
  • the shape of the first receiving cavity 113 is adapted to the shape of the bridge bare chip 101.
  • the first receiving cavity 113 may be a square cavity, a cylindrical cavity, a trapezoidal cavity, etc.
  • the chip packaging structure 100 further includes a first plastic compound 141 .
  • the first plastic compound 141 is located in the gap between the bridging bare chip 101 and the inner wall of the first receiving cavity 113 .
  • the first plastic encapsulation material 141 can fix the bridge bare chip 101 and improve the structural reliability.
  • the first plastic encapsulating material 141 can improve the sealing performance of the bridge bare chip 101 and improve its electrical performance stability.
  • the embodiment of the present application does not limit the material of the first plastic molding material 141.
  • the material of the first plastic molding material 141 is a high molecular polymer.
  • the material of the first plastic molding material 141 is epoxy resin. The good waterproof ability and sealing performance of epoxy resin provide a stable working environment for the bridge bare chip 101, which is beneficial to the stable electrical performance of the bridge bare chip 101.
  • the first plastic encapsulating material 141 may not be provided.
  • the embodiment of the present application does not limit the connection method between the first bare chip 102 and the bonding pad 130 .
  • first die 102 is electrically connected to pad 130 .
  • the chip packaging structure 100 further includes a first electrical connector 151 , the first electrical connector 151 penetrates the first surface 111 and the second surface 112 , and the first bare chip 102 is connected through the first electrical connector 151 .
  • Component 151 is electrically connected to pad 130.
  • the first electrical connector 151 can provide more wiring solutions between the first bare chip 102 and the bonding pad 130 to increase selectivity, and the first electrical connector 151 can fully utilize the space of the first packaging layer 110 .
  • the embodiment of the present application does not limit the material of the first electrical connector 151.
  • the material of the first electrical connector 151 is copper. Copper has low cost and good electrical conductivity, which can reduce signal loss.
  • the embodiment of the present application does not limit the distribution of the first electrical connectors 151. Bridging the bare chip 101 is beneficial to reducing the distribution density of the first electrical connectors 151 in the first packaging layer 110. Therefore, it is beneficial to reduce the density of the chip packaging structure 100. Make a larger contribution to manufacturing costs.
  • the chip packaging structure 100 may not be provided with the first electrical connector 151.
  • the first bare chip 102 is connected to the pad 130 through the bridge die 101, wherein the first die 102 is connected to the bridge die 130.
  • the bare chip 101 is electrically connected, and the bridge bare chip 101 and the pad 130 are electrically connected.
  • the chip packaging structure 100 further includes a first wiring layer 160 .
  • the first wiring layer 160 is located between the second packaging layer 120 and the first packaging layer 110 , and the bridge bare chip 101 is electrically connected to the first bare chip 102 through the first wiring layer 160 .
  • the first wiring layer 160 can provide more interconnection space for the first die 102 and the bridge die 101 .
  • the first wiring layer 160 may be multiple layers.
  • the multiple first wiring layers 160 are overlapped in a direction away from the first surface 111 , and two adjacent first wiring layers 160 Electrical connection.
  • the chip packaging structure 100 also includes a second wiring layer 170.
  • the second wiring layer 170 is located between the bonding pad 130 and the first packaging layer 110, bridging the bare chip 101 and the bonding pad 130 with the second wiring layer. 170 connection, the bridge die 101 is electrically connected to the pad 130 through the second wiring layer 170 .
  • the first electrical connector 151 may also be connected to the second wiring layer 170 .
  • the second wiring layer 170 can increase the interconnection path between the bridging bare chip 101 and the bonding pad 130 and reduce the parasitic inductance caused by over-density of interconnection lines.
  • the second wiring layer 170 may not be provided.
  • the bridge bare chip 101 is directly electrically connected to the bonding pad 130
  • the first electrical connector 151 is directly electrically connected to the bonding pad 130 .
  • the embodiment of the present application does not limit the number of the first bare chips 102.
  • the number of the first bare chips 102 may be two, three, four or more.
  • the embodiment of the present application does not limit the structure of the first bare chip 102, and it can be set according to the function of the chip packaging structure 100.
  • the first bare chips 102 are located in a second packaging layer 120 . It can be understood that in other embodiments of the present application, the first bare chips 102 can be distributed in different packaging layers.
  • the second encapsulation layer 120 has multiple layers.
  • the multiple second encapsulation layers 120 are stacked in a direction away from the first encapsulation layer 110 .
  • the plurality of first bare chips 102 are distributed in different second encapsulation layers 120 .
  • the number of the second packaging layers 120 and the distribution relationship of the first bare chips 102 can be set according to the performance requirements of the chip packaging structure 100, and the embodiments of the present application do not limit this.
  • the embodiments of the present application do not limit the structures of the first encapsulation layer 110 and the second encapsulation layer 120, and different structures may need to be formed using different preparation processes. Different structures and methods are described below as examples.
  • FIG. 4 A chip packaging structure 100 provided in Embodiment 1 is shown in Figure 4.
  • Figure 5a is a schematic structural diagram of a first packaging layer 110 and a first electrical connector 151 provided in Embodiment 1 of the present application. Please refer to FIG. 4 and FIG. 5 a together.
  • the first receiving cavity 113 penetrates the first surface 111 and the second surface 112 .
  • the first receiving cavity 113 has a first opening 114 and a third opening 115.
  • the first opening 114 is located on the first surface 111
  • the third opening 115 is located on the second surface 112 .
  • the bridge bare chip 101 when installing the bridge bare chip 101, the bridge bare chip 101 can be placed into the first accommodating cavity 113 through the first opening 114, or can be placed into the first accommodating cavity 113 through the third opening 115. Secondly, the position of the bridge bare chip 101 located in the first receiving cavity 113 can also be adjusted from the first opening 114 or the third opening 115 . In addition, the bridge bare chip 101 can be directly connected to the pad 130, which is beneficial to shortening the signal path length and reducing loss.
  • the embodiment of the present application does not limit the relationship between the first bare chip 102 and the second packaging layer 120 .
  • the first bare chip 102 is embedded in the second packaging layer 120 .
  • the outer periphery of the first bare chip 102 may be wrapped by the second encapsulation layer 120 .
  • the surface of the first bare chip 102 facing the first surface 111 and the surface facing away from the first surface 111 may not be wrapped by the second encapsulation layer 120 .
  • the embodiment of the present application does not limit the material of the second encapsulation layer 120.
  • the second encapsulation layer 120 includes a second plastic encapsulation material 142.
  • the first bare chip 102 is embedded in the second plastic encapsulation material 142 , so the material cost and process cost are low.
  • the second plastic encapsulation compound 142 has better sealing performance for the first bare chip 102 , which is beneficial to the stable operation of the first bare chip 102 .
  • Figure 5b is a schematic structural diagram of another chip packaging structure 100 provided in Embodiment 1 of the present application.
  • the main difference between Figure 5b and Figure 4 is the second packaging layer 120.
  • the second encapsulation layer 120 includes a second accommodation cavity 121 , and the second accommodation cavity 121 has a second opening 122 located on the surface of the second encapsulation layer 120 .
  • the first bare chip 102 is located in the second containing cavity 121 , and the second packaging layer 120 has the same thermal expansion coefficient as the first bare chip 102 .
  • the thermal expansion coefficient of the second packaging layer 120 and the first bare chip 102 are the same as the thermal expansion coefficients of the first packaging layer 110 and the bridge bare chip 101, which will not be described again here.
  • the material of the second encapsulation layer 120 please refer to the material selection of the first encapsulation layer 110, which will not be described again here.
  • the structure of the second accommodation cavity 121 please refer to the structure of the first accommodation cavity 113 in Figure 5a above.
  • the second opening 122 please refer to the description of the first opening 114 in Figure 5a above, which will not be described again here.
  • the second accommodation cavity 121 has a third plastic compound 143 , and the third plastic compound 143 is located in the gap between the first bare chip 102 and the inner wall of the second accommodation cavity 121 .
  • the third plastic sealant 143 prevents the relative position between the first bare chip 102 and the second packaging layer 120 from changing easily, and the third plastic sealant 143 can provide a waterproof and airtight environment for the first bare chip 102 .
  • the material selection of the third plastic sealing material 143 please refer to the above description of the first plastic sealing material 141, which will not be described again here.
  • This application does not limit the packaging method of the chip packaging structure 100 provided in Embodiment 1.
  • FIG. 6a is a packaging flow chart of Example 1 of the chip packaging structure 100 provided in Embodiment 1 of the present application.
  • the packaging method includes:
  • the structure of the first encapsulation layer 110 is shown in FIG. 6b, in which the first encapsulation layer 110 has a first receiving cavity 113 and opposite first and second surfaces 111 and 112.
  • the first accommodation cavity 113 has a first opening 114 located on the first surface 111 , and the thermal expansion coefficients of the bridging bare chip 101 and the first packaging layer 110 are the same.
  • the first accommodation cavity 113 also has a third opening 115, and the third opening 115 is located on the second surface 112.
  • Figure 6c is a schematic structural diagram after executing S1 shown in Figure 6a.
  • the bridge bare chip 101 can be placed into the first accommodation cavity 113 from the first opening 114 or the third opening 115.
  • Figure 6d is a schematic structural diagram after executing S2 shown in Figure 6a, in which a plurality of first bare chips 102 are formed in the second packaging layer 120, and the plurality of first bare chips 102 are all electrically connected to the bridge bare chip 101.
  • Figure 6e is a schematic structural diagram after executing S3 shown in Figure 6a, in which the bridge bare chip 101 or the first bare chip 102 is electrically connected to the bonding pad 130.
  • S2 may be executed first or S3 may be executed first.
  • FIG. 7a is a packaging flow chart of Example 2 of the chip packaging structure 100 provided in Embodiment 1 of the present application. As shown in Figure 7a, S1 also includes:
  • Figure 7b is a schematic structural diagram after executing S4 in Figure 7a.
  • the first electrical connector 151 penetrates the first surface 111 and the second surface 112 .
  • Figure 7c is a flow chart of S4 in Figure 7a.
  • S4 includes:
  • Figure 7e is a schematic structural diagram after executing S41 in Figure 7c. This embodiment of the present application does not limit the number, size and size of via holes 144.
  • the structure after executing S42 in Figure 7c is shown in Figure 7b.
  • the embodiment of the present application does not limit the formation process of the first electrical connector 151.
  • it can be formed by electroplating, evaporation, atomic sputtering, etc.
  • FIG. 8a is a packaging flow chart of Example 3 of the chip packaging structure 100 provided in Embodiment 1 of the present application. As shown in Figure 8a, after S1 it also includes:
  • Figure 8b is a schematic structural diagram after executing S5 in Figure 8a.
  • Figure 9a is a packaging flow chart of Example 4 of the chip packaging structure 100 provided in Embodiment 1 of the present application. As shown in Figure 9a, S2 also includes:
  • Figure 9b is a schematic structural diagram after executing S6 in Figure 9a.
  • the embodiment of the present application does not limit the formation process of the first wiring layer 160.
  • a photoresist layer is formed on the first surface 111, the photoresist layer is photolithographed to form a pattern, and the first wiring is formed in the foregoing pattern.
  • Layer 160 is a photoresist layer formed on the first surface 111, the photoresist layer is photolithographed to form a pattern, and the first wiring is formed in the foregoing pattern.
  • Layer 160 is a schematic structural diagram after executing S6 in Figure 9a.
  • the bridge bare chip 101 is electrically connected to the first bare chip 102 through the first wiring layer 160 .
  • the chip packaging structure 100 further includes a second wiring layer 170
  • FIG 10a is a packaging flow chart of Example 5 of the chip packaging structure 100 provided in Embodiment 1 of the present application. As shown in Figure 10a, S3 also includes:
  • Figure 10b is a schematic structural diagram after executing S7 in Figure 10a.
  • the formation process of the second wiring layer 170 please refer to the foregoing description of the first wiring layer 160, and will not be described again here.
  • the bridge bare chip 101 and the bonding pad 130 are electrically connected to the second wiring layer 170.
  • S4, S5, S6 and S7 are not mutually exclusive. According to requirements, S4, S4 and S7 can be executed simultaneously in the same packaging method. S5, S6 and S7 can also be executed by selecting one, two or three.
  • the chip packaging structure 100 shown in FIG. 4 can be obtained by executing the aforementioned S1 to S8.
  • S5 and S6 may be formed through the same process.
  • plastic molding material is formed on the first receiving cavity 113 and the first surface 111 at the same time.
  • the first wiring layer 160 is formed by wiring on the surface of the plastic encapsulation material of the first surface 111 .
  • the structure of the second packaging layer 120 is not limited, and therefore, the process of S2 is not limited either.
  • FIG 11a is a flow chart of the preparation of the second encapsulation layer 120 in the structure shown in Figure 4.
  • S2 includes:
  • Figure 11b is a schematic structural diagram after executing S21 in Figure 11a. There are multiple first bare chips 102, and the plurality of first bare chips 102 are spaced apart.
  • the first die 102 is placed on the surface of the first wiring layer 160 .
  • the structure for executing S22 in Figure 11a is shown in Figure 6d.
  • the first bare chip 102 is embedded in the second packaging layer 120 .
  • the embodiment of the present application does not limit the specific process in S22.
  • the plastic sealing material is coated and then the plastic sealing material is cured to form the second packaging layer 120.
  • the cost of the plastic sealing material is low, which is beneficial to reducing process costs.
  • FIG 11c is a flow chart for the preparation of S2 in the structure shown in Figure 5b.
  • S2 includes:
  • Figure 11d is a schematic structural diagram after executing S23 in Figure 11c.
  • the second accommodation cavity 121 is provided with a second opening 122 .
  • the thermal expansion coefficients of the first bare chip 102 and the second packaging layer 120 are the same.
  • Figure 11e is a schematic structural diagram after executing S24 in Figure 11c.
  • S2 shown in FIG. 11 c is beneficial to reducing the warpage between the second packaging layer 120 and the first bare chip 102 .
  • the gap between the first bare chip 102 and the inner wall of the second receiving cavity 121 is filled with the third plastic compound 143.
  • the specific steps are the same as S5 in FIG. 8a and will not be described again here.
  • the preparation method of the chip packaging structure 100 provided in Embodiment 1 of the present application can effectively improve the warpage between the bridge bare chip 101 and the first packaging layer 110 .
  • the packaging method provided in Embodiment 1 can prefabricate the first packaging layer 110 and then connect it to the bridge bare chip 101, which is beneficial to shortening the process flow.
  • the first encapsulation layer 110 can be made of silicon, glass, ceramics, or other materials, problems such as flow marks and non-wetting are less likely to occur when the plastic sealant is coated on the surface of the first encapsulation layer 110 . It is important to stabilize the electrical performance of the chip packaging structure 100 .
  • the structure of the first encapsulation layer 110 is not limited to the structure shown in FIG. 4 and FIG. 5b.
  • Figure 12a is a schematic structural diagram of the chip packaging structure 100 provided in Embodiment 2 of the present application.
  • the main difference between Embodiment 2 and Embodiment 1 is that the structure of the first packaging layer 110 is different. Please refer to Embodiment 1 for the remaining structures, which will not be described again here.
  • the first receiving cavity 113 has a first opening 114 and a bottom wall 116, and the bottom wall 116 is opposite to the first opening 114.
  • the first receiving cavity 113 is a groove structure, and the groove structure has a bottom wall 116 .
  • the bottom wall 116 can carry the bridge bare chip 101, which is beneficial to the positioning of the bridge bare chip 101.
  • the bottom wall 116 can receive the raw material of the first plastic compound 141 , and the probability of the first plastic compound 141 overflowing is small, and the process may not consider the first plastic compound 141 due to the first plastic compound 141 .
  • Figure 12b is another structural schematic diagram of the chip packaging structure 100 provided in Embodiment 2 of the present application. Please refer to Figures 12b and 12a.
  • the difference between the example of Figure 12b and the example of Figure 12a is that the chip packaging structure 100 also includes a second The electrical connector 152 and the second electrical connector 152 penetrate the second surface 112 and the surface of the bottom wall 116 .
  • the bridge die 101 is electrically connected to the pad 130 through the second electrical connection 152 .
  • the second electrical connector 152 can shorten the path between the bridging bare chip 101 and the pad 130 and reduce the loss.
  • the second electrical connector 152 provides more connection options for the structure having the bottom wall 116 .
  • the material and structure of the second electrical connector 152 please refer to the relevant description of the first electrical connector 151 and will not be described again here.
  • the embodiment of the present application does not limit the packaging method of the chip packaging structure 100 provided in Embodiment 2. Please refer to Figure 6a of Embodiment 1 for the packaging method.
  • Embodiment 2 The main difference between Embodiment 2 and Embodiment 1 lies in the different preprocessing of the first encapsulation layer 110 .
  • Embodiment 2 can be encapsulated using the flow charts shown in Figures 6a, 7a, 8a, 9a, and 10a.
  • the main difference is that the shape of the first encapsulation layer 110 is different.
  • the difference between the packaging method of Embodiment 2 and that shown in Figure 6a is that the first packaging layer 110 is different.
  • the first packaging layer 110 in S1 in Figure 6a adopts the structure shown in Figure 13a to obtain the chip packaging structure 100 shown in Figure 12a.
  • the first accommodation cavity 113 does not penetrate the first encapsulation layer 110.
  • the first accommodation cavity 113 has a first opening 114 located on the first surface 111.
  • the first accommodation cavity 113 There is also a bottom wall 116 opposite to the first surface 111 .
  • Figure 13b is a packaging flow chart provided in Embodiment 2 of the present application. The difference between Figure 13b and Figure 6a is that S1 in Figure 13b also includes:
  • FIG. 13c is a schematic structural diagram after executing S8 in FIG. 13b , in which the second electrical connector 152 penetrates the bottom wall 116 and the second surface 112 of the first accommodation cavity 113 .
  • the bottom wall 116 is opposite to the first opening 114 , and the bridge die 101 is electrically connected to the pad 130 through the second electrical connector 152 .
  • the embodiment of the present application does not limit the formation process of the second electrical connector 152. Please refer to the formation process of the first electrical connector 151 in Embodiment 1, which will not be described again here.
  • Embodiment 2 please refer to Figure 7a, Figure 8a, Figure 9a, Figure 10a and Figure 13a again.
  • the packaging method provided in Embodiment 2 can also prefabricate the first packaging layer 110 and the second electrical connector 152, which is also beneficial to shortening the process flow.
  • the first electrical connector 151 and the second electrical connector 152 need to be prefabricated, due to the arrangement of the bridge bare chip 101 , the density of the first electrical connector 151 and the second electrical connector 152 can be smaller, which is beneficial to Save process costs.
  • the chip packaging structure 100 provided by the embodiment of the present application can effectively improve the warpage problem of the first packaging layer 110 and the bridge bare chip 101.
  • the material of the first encapsulation layer 110 includes at least one of silicon, glass, and ceramics
  • the existing problems of easy flow marks and non-wetting of polymer materials on the surface of the first encapsulation layer 110 can be improved. Therefore, the electrical performance of the chip packaging structure 100 is better guaranteed during use.
  • the performance of the base station 002 and the terminal equipment 003 including the above-mentioned chip packaging structure 100 is also guaranteed.

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Abstract

本申请实施例公开了一种芯片封装结构、封装方法、电子设备，涉及芯片领域，改善芯片封装易翘曲的问题。具体方案为：芯片封装结构包括第一封装层和桥接裸芯片。桥接裸芯片位于第一封装层内。第一封装层选用硅、玻璃、陶瓷等热膨胀系数与桥接裸芯片接近的材料。当工作温度发生变化后，桥接裸芯片与第一封装层的形变量接近相同，改善封装层翘曲的问题。此外，在硅、玻璃或陶瓷表面涂高分子材料时，不易流痕、易湿润，可提高良率。桥接裸芯片与第一封装层的间隙填充塑封料，可固定桥接裸芯片，且塑封料为桥接裸芯片提供封闭的环境。由此，芯片封装结构的机械可靠性得到有效保障，运行过程中电性能稳定。

Description

芯片封装结构、封装方法、电子设备
本申请要求于2022年08月16日提交国家知识产权局、申请号为202210982698.6、申请名称为“芯片封装结构、封装方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及芯片领域，尤其涉及一种芯片封装结构、封装方法、电子设备。
 背景技术
随着半导体技术的日新月异，芯片封装技术也不断发展。芯片封装主要作用在于密封、保护芯片，实现芯片与芯片之间、芯片内部电路与外部电路之间的互连。芯片封装的性能直接影响芯片的使用寿命。
在使用过程中，芯片封装结构易发生翘曲，影响封装结构的机械强度，增加可靠性失效的风险。
发明内容
本申请实施例提供一种芯片封装结构、封装方法、电子设备。旨在改善芯片封装结构翘曲的问题。
为达到上述目的，本申请实施例采用如下技术方案：
第一方面，提供一种芯片封装结构，该芯片封装结构包括第一封装层、桥接裸芯片、第二封装层、焊盘和多个第一裸芯片；第一封装层具有第一容纳腔、相对的第一表面和第二表面，该第一容纳腔具有位于该第一表面的第一开口；桥接裸芯片位于该第一容纳腔内；第二封装层靠近该第一表面设置；多个该第一裸芯片均位于该第二封装层内；多个该第一裸芯片均与该桥接裸芯片电连接；焊盘位于该第二表面；该桥接裸芯片或该第一裸芯片与该焊盘电连接；该第一封装层与该桥接裸芯片的热膨胀系数相同。由此，当环境温度或者芯片封装结构自身的温度变化后，第一封装层与桥接裸芯片的形变量差异小，第一封装层不易翘曲。可降低因翘曲对芯片封装结构的机械可靠性的影响，从而改善因机械可靠性降低而导致电性能可靠性降低，延长芯片封装结构的使用寿命。
[根据细则91更正 01.08.2023]
结合第一方面，在一些可实现的方式中，该第一封装层与该桥接裸芯片的热膨胀系数相差小于6×10-6/℃。由此，热膨胀系数相差小，相同温差下，第一封装层与桥接裸芯片的形变量接近相同，翘曲的概率小，机械可靠性影响小，电性能稳定。
结合第一方面，在一些可实现的方式中，该第一封装层的材料包括硅、陶瓷以及玻璃中的至少一种。由此，相同温差下，第一封装层的材料与桥接裸芯片的衬底的形变量接近，不易翘曲。此外，在硅、陶瓷或者玻璃的表面涂布高分子材料时，流痕和不润湿等工艺问题产生的概率小，芯片封装结构的良率提高，可靠性增加。
结合第一方面，在一些可实现的方式中，该芯片封装结构还包括：第一塑封料；该第一塑封料位于该桥接裸芯片与该第一容纳腔内壁之间的间隙内。由此，第一塑封料可以固定桥接裸芯片，提高结构可靠性。此外，第一塑封料可以使桥接裸芯片的密封性能更佳，提高其电性能稳定性。
结合第一方面，在一些可实现的方式中，该第一裸芯片埋设于该第二封装层内。由此，第一裸芯片的封装工艺成本较低。
结合第一方面，在一些可实现的方式中，该第二封装层包括第二塑封料。由此，第二封装层对第一裸芯片的密封性能较好，有利于第一裸芯片稳定运行。
结合第一方面，在一些可实现的方式中，该第二封装层包括第二容纳腔，该第二容纳腔具有位于该第二封装层表面的第二开口，该第一裸芯片位于该第二容纳腔内，该第二封装层与该第一裸芯片的热膨胀系数相同。由此，当温度发生变化后，第一裸芯片和第二封装层的形变量较小。第一封装层和第二封装层均不易翘曲，进一步稳定芯片封装结构的的结构可靠性。
[根据细则91更正 01.08.2023]
结合第一方面，在一些可实现的方式中，该第二封装层与该第一裸芯片的热膨胀系数相差小于6×10-6/℃。由此，第二封装层与第一裸芯片几乎没有形变量之差，温度变化后形变较小。
结合第一方面，在一些可实现的方式中，该第二封装层的材料包括硅、陶瓷以及玻璃中的至少一种。由此，硅、陶瓷或者玻璃的热膨胀系数与第一裸芯片的热膨胀系数相差小，不易翘曲。
结合第一方面，在一些可实现的方式中，该芯片封装结构还包括：第三塑封料；该第三塑封料位于该第一裸芯片与该第二容纳腔内壁之间的间隙内。由此，第三塑封料可以稳固第一裸芯片，且第三塑封料可以为第一裸芯片提供密闭的环境，为第一裸芯片的稳定运行提供优良环境。
结合第一方面，在一些可实现的方式中，该芯片封装结构还包括：第一电连接件；该第一电连接件贯穿该第一表面和该第二表面；该第一裸芯片通过该第一电连接件与该焊盘电连接。由此，第一电连接件可以使第一裸芯片与焊盘之间有更多的布线方案。此外，由于桥接裸芯片的设置，对降低第一电连接件在第一封装层内的分布密度有利，因此，对降低芯片封装结构的制造成本做贡献。
结合第一方面，在一些可实现的方式中，该第一容纳腔还具有位于该第二表面的第三开口。由此，安装桥接裸芯片时，桥接裸芯片可以从第一开口或第三开口置入第一容纳腔，便于安装桥接裸芯片，桥接裸芯片可以与焊盘直接连接，有利于缩短信号路径长度，减小损耗。
结合第一方面，在一些可实现的方式中，该第一容纳腔具有底壁，该底壁和该第一开口相对。由此，底壁具有承载桥接裸芯片的功能，有利于桥接裸芯片的定位。此外，底壁可以承接第一塑封料的原料，降低第一塑封料的外溢。
结合第一方面，在一些可实现的方式中，该芯片封装结构还包括：第二电连接件，该第二电连接件贯穿该第二表面和该底壁的表面；该桥接裸芯片通过该第二电连接件与该焊盘电连接。由此，第二电连接件可以缩短桥接裸芯片与焊盘之间的路径，降低损耗。第二电连接件为具有底壁的结构提供更多的连接方案。
结合第一方面，在一些可实现的方式中，该芯片封装结构还包括：第一布线层，该第一布线层位于该第二封装层与该第一封装层之间，该桥接裸芯片通过该第一布线层与该第一裸芯片电连接。由此，第一布线层为第一裸芯片与桥接裸芯片提供更多的互连空间。
结合第一方面，在一些可实现的方式中，该芯片封装结构还包括：第二布线层，该第二布线层位于该焊盘与该第一封装层之间，该桥接裸芯片、该焊盘均与该第二布线层电连接。由此，第二布线层为芯片封装结构提供更多的互连空间。
第二方面，提供一种芯片封装方法，包括：
将桥接裸芯片置于第一封装层的第一容纳腔内；其中，该第一封装层具有该第一容纳腔和相对的第一表面和第二表面；该第一容纳腔具有位于该第一表面的第一开口；该第一封装层与该桥接裸芯片的热膨胀系数相同；
于该第一表面形成第二封装层；该第二封装层内形成有多个第一裸芯片，多个该第一裸芯片均与该桥接裸芯片电连接；
于该第二表面形成焊盘，该桥接裸芯片或该第一裸芯片与该焊盘电连接。
结合第二方面，在一些可实现的方式中，该将桥接裸芯片置于第一封装层的第一容纳腔内之前还包括：
于该第一封装层内形成第一电连接件，该第一电连接件贯穿该第一表面和该第二表面；该第一裸芯片通过该第一电连接件与该焊盘电连接。
结合第二方面，在一些可实现的方式中，该将桥接裸芯片置于第一封装层的第一容纳腔内之前还包括：
于该第一封装层形成第二电连接件；其中，该第二电连接件贯穿该第一容纳腔的底壁和该第二表面，该底壁和该第一开口相对，该桥接裸芯片通过该第二电连接件与该焊盘电连接。
结合第二方面，在一些可实现的方式中，该将桥接裸芯片置于第一封装层的第一容纳腔内之后还包括：
于该桥接裸芯片与该第一容纳腔内壁之间的间隙填充第一塑封料。
结合第二方面，在一些可实现的方式中，该于该第一表面形成第二封装层之前还包括：
于该第一表面形成第一布线层；
其中，该桥接裸芯片通过该第一布线层与该第一裸芯片电连接。
结合第二方面，在一些可实现的方式中，该于该第一表面形成第二封装层包括：
将该第一裸芯片置于该第一表面；
形成该第二封装层；其中，该第一裸芯片埋设于该第二封装层内。
结合第二方面，在一些可实现的方式中，该于该第一表面形成第二封装层包括：
将该第一裸芯片置于该第二封装层的第二容纳腔内，该第二容纳腔上设有第二开口；该第一裸芯片与该第二封装层的热膨胀系数相同；
将该第二封装层与该第一表面连接。
结合第二方面，在一些可实现的方式中，该将该第一裸芯片置于该第二封装层的第二容纳腔内之后还包括：
于该第一裸芯片与该第二容纳腔内壁之间的间隙形成第三塑封料。
结合第二方面，在一些可实现的方式中，该于该第二表面形成焊盘之前还包括：
于该第二表面形成第二布线层，其中，该桥接裸芯片、该焊盘均与该第二布线层电连接。
第三方面，提供一种电子设备，电子设备包括印刷电路板和第一方面提供的任一种芯片封装结构；其中，该焊盘与该印刷电路板电性连接。由于芯片封装结构的翘曲问题得到改善，其机械可靠性提高，使用过程中电性能得到较好保障。相应地，电子设备的性能也因此而得到保证。
 附图说明
图1为本申请实施例提供的通信系统的结构示意图。
图2为本申请实施例提供的印刷电路板组件的结构示意图。
图3a为一种示例的芯片封装结构示意图。
图3b为又一种示例的种芯片封装结构示意图。
图4为本申请实施例提供的芯片封装结构的结构示意图。
图5a为本申请实施例1提供的一种第一封装层和第一电连接件的结构示意图。
图5b为本申请实施例1提供的另一种芯片封装结构的结构示意图。
图6a为本申请实施例1提供的芯片封装结构示例一的封装流程图。
图6b为图6a中第一封装层的结构示意图。
图6c为执行图6a所示S1后的结构示意图。
图6d为执行图6a所示S2后的结构示意图。
图6e为执行图6a所示S3后的结构示意图。
图7a为本申请实施例1提供的芯片封装结构的示例二的封装流程图。
图7b为执行图7a中S4后的结构示意图。
图7c为图7a中S4的流程图。
图7d为执行图7a中S4之前的结构示意图。
图7e为执行图7c中S41后的结构示意图。
图8a为本申请实施例1提供的芯片封装结构的示例三的封装流程图。
图8b为执行图8a中S5后的结构示意图。
图9a为本申请实施例1提供的芯片封装结构的示例四的封装流程图。
图9b为执行图9a中S6后的结构示意图。
图10a为本申请实施例1提供的芯片封装结构的示例五的封装流程图。
图10b为执行图10a中S7后的结构示意图。
图11a为图4所示结构中第二封装层的制备流程图。
图11b为执行图11a中S21后的结构示意图。
图11c为图5b所示结构中S2的制备流程图。
图11d为执行图11c中S23后的结构示意图。
图11e为执行图11c中S24后的结构示意图。
图12a为本申请实施例2提供的芯片封装结构的一种结构示意图。
图12b为本申请实施例2提供的芯片封装结构的又一种结构示意图。
图13a为图12a所示的芯片封装结构中第一封装层的结构示意图。
图13b为本申请实施例2提供的一种封装流程图。
图13c为执行图13b中S8后的结构示意图。
图中：001-通信系统；002-基站；003-终端设备；10-印刷电路板组件；20-印刷电路板；201-腔体；30-导热件；40-散热器；01-芯片封装结构；11-硅片；12-布线层；13-铜过孔；14-芯片；15-介质层；21-第一介质层；22-底层裸芯片；23-第二介质层；24-上层裸芯片；100-芯片封装结构；101-桥接裸芯片；102-第一裸芯片；110-第一封装层；111-第一表面；112-第二表面；113-第一容纳腔；114-第一开口；115-第三开口；116-底壁；141-第一塑封料；142-第二塑封料；143-第三塑封料；144-过孔；151-第一电连接件；152-第二电连接件；120-第二封装层；121-第二容纳腔；122-第二开口；130-焊盘；160-第一布线层；170-第二布线层。
 具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
以下，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请中，“上”、“下”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
本申请的实施例提供一种通信系统，图1为本申请实施例提供的通信系统001的结构示意图，请参阅图1，通信系统001包括基站002和终端设备003。基站002和终端设备003通信连接。
本申请实施例对终端设备003的具体形式不做限制，例如，终端设备003可以为手机(mobile phone)、平板电脑(pad)、个人数字助理(personal digital assistant，PDA)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、充电家用小型电器(例如豆浆机、扫地机器人)、无人机、雷达、航空航天设备和车载设备等。
终端设备003包括印刷电路板(printed circuit boards，PCB)，以及设置于印刷电路板上芯片封装组件等，PCB用于承载系统级芯片、芯片封装组件等，且与系统级芯片、芯片封装组件等电性连接。
基站002例如包括印刷电路板组件。
图2为本申请实施例提供的印刷电路板组件10的结构示意图，请参阅图2，印刷电路板组件10包括印刷电路板20、芯片封装结构100、导热件30以及散热器40。
其中，导热件30与印刷电路板20连接，导热件30与印刷电路板20围设成腔体201，芯片封装结构100位于腔体201内，芯片封装结构100与印刷电路板20电连接，散热器40与导热件30连接，散热器40与印刷电路板20分别位于导热件30相对的两侧。
本申请实施例对导热件30的结构不做限制，例如，导热件30可以为金属罩，金属罩与印刷电路板20扣合以形成腔体201。
导热件30用于将芯片封装结构100产生的热量传导至散热器40，并通过散热器40进行散热。
印刷电路板20用于与其他电子元件电连接。
芯片封装结构100会影响芯片性能的可靠性，芯片性能的可靠性会影响印刷电路板组件10的电性能，从而影响设备的运行，例如影响终端设备003或者影响基站002的运行。
图3a为一种示例的芯片封装结构01示意图，如图3a所示，芯片封装结构01包括：硅片11、布线层12、铜过孔13、裸芯片14以及介质层15，硅片11、布线层12、介质层15依次叠层设置。
裸芯片14位于介质层15内，硅片11以及介质层15内均设置有铜过孔13，铜过孔13与布线层12电连接，裸芯片14的引脚与布线层12电连接。
在形成图1的芯片封装结构01过程中，需要在硅片11上设置铜过孔13，随着裸芯片14尺寸的增大，铜过孔13的密度增大，铜过孔13与布线层12的互连对工艺要求提高，导致成本提高的同时良率也随之下降。
图3b为又一种示例的种芯片封装结构01示意图，如图3b所示，芯片封装结构01包括第一介质层21、底层裸芯片22、布线层12、铜过孔13、第二介质层23以及上层裸芯片24。
第一介质层21、布线层12、第二介质层23依次叠层设置，第一介质层21内和第二介质层23内均设置有铜过孔13，铜过孔13均与布线层12连接，底层裸芯片22位于第一介质层21内，上层裸芯片24位于第二介质层23内。
通常，第一介质层21的材料为环氧树脂等高分子材料，底层裸芯片22包括硅衬底和生长于硅衬底表面的外延层。
第二介质层23的材料参阅第一介质层21，上层裸芯片24的结构参阅底层裸芯片22，此处不再赘述。
环氧树脂和硅衬底由于热膨胀系数差异较大，因此，当芯片封装结构01的温度发生变化后，热膨胀差异导致介质层和裸芯片的形变量差异大，介质层上的内应力增加，芯片封装结构01易翘曲，良率降低。其次，在第一介质层21表面设置布线层12的过程中，流痕和不润湿等问题也会降低芯片封装结构01的良率。再者，随着布线层12数量的增加，布线层12的表面共面度下降，导致铜过孔13与布线层12的连接可靠性下降。
为此，提高芯片封装结构的良率是芯片封装需要重视的问题。
本申请的实施例提供一种芯片封装结构，旨在提高芯片封装结构的良率。该芯片封装结构可以用于上述基站002或者终端设备003。
图4为本申请实施例提供的芯片封装结构100的结构示意图。请参阅图4，芯片封装结构100包括桥接裸芯片101、第一裸芯片102、第一封装层110、第二封装层120和焊盘130。
桥接裸芯片101位于第一封装层110内，第一裸芯片102位于第二封装层120内，第一封装层110位于第二封装层120和焊盘130之间。
其中，第一裸芯片102与桥接裸芯片101电连接，第一裸芯片102或桥接裸芯片101与焊盘130电连接。
示例性地，第一裸芯片102可以通过桥接裸芯片101与焊盘130电连接。或者，第一裸芯片102的部分元件可以不通过桥接裸芯片101与焊盘130电连接，例如，第一裸芯片102的接地端的信号不经过桥接裸芯片101，直接与焊盘130连接。
相应地，桥接裸芯片101的元件可以通过第一裸芯片102与焊盘130电连接，也可以不通过第一裸芯片102，直接与焊盘130电连接。
在本申请的实施例中，第一封装层110与桥接裸芯片101的热膨胀系数相同。
在本申请的一些实施例中，桥接裸芯片101的热膨胀系数可以近似为桥接裸芯片101的衬底材料的热膨胀系数。换言之，第一封装层110与桥接裸芯片101衬底的热膨胀系数相同。例如，在桥接裸芯片101的衬底为硅的实施例中，第一封装层110的热膨胀系数接近硅的热膨胀系数。
在本申请的一些实施例中，在第一封装层110热膨胀系数各向异性的实施例中，沿第第一封装层110至第二封装层120叠设方向，第一封装层110的热膨胀系数与桥接裸芯片101的热膨胀系数相同。
[根据细则91更正 01.08.2023]
需要说明的是，前述的热膨胀系数相同并不限制于数值上的绝对相同，可以接近相同。例如，二者的热膨胀系数之差小于20×10-6/℃。例如，二者的热膨胀系数之差为0、6×10-6/℃、2×10-6/℃、3×10-6/℃、5×10-6/℃、6×10-6/℃、7×10-6/℃、8×10-6/℃、9×10-6/℃、10×10-6/℃、15×10-6/℃、18×10-6/℃或者20×10-6/℃等等。
由于第一封装层110与桥接裸芯片101的热膨胀系数相同，当温度变化后，二者的形变量差异小，可有效改善因为二者形变量差异大而导致芯片封装结构100的翘曲，增强芯片封装结构100的机械可靠性，改善因机械可靠性降低而导致电性能可靠性降低，延长其使用寿命。
在一些实施例中，桥接裸芯片101的数量小于第一裸芯片102的数量。第一封装层110内的芯片含量小于第二封装层120内的芯片含量。通常，与第二封装层120的翘曲相比，芯片含量小的第一封装层110的翘曲更严重。由此，改善第一封装层110的翘曲对芯片封装结构100的翘曲改善效果较佳。此外，芯片含量小的第一封装层110上开设的第一容纳腔113数量少，工艺成本相对较低。
示例性地，第一封装层110的材料包括硅、陶瓷以及玻璃中的至少一种。示例性地，第一封装层110的材料可以为硅片，其与衬底为硅的桥接裸芯片101的热膨胀系数之差常小。第一封装层110的材料可以为玻璃或者陶瓷，玻璃或者陶瓷与桥接裸芯片101的热膨胀系数之差较小，且玻璃或者陶瓷成本较低。或者，在一些实施例中，第一封装层110的材料可以为硅和陶瓷的混合物，有益于降低第一封装层110的成本。
在第一封装层110的材料为硅的实施例中，该硅材料可以为单晶硅、多晶硅或者微晶硅等，本申请实施例对此不做限制。
如此，当芯片封装结构100的温度发生变化后，第一封装层110和桥接裸芯片101的形变量差异小。此外，在硅、陶瓷或者玻璃的表面涂布高分子材料时，流痕和不润湿等工艺问题产生的概率小，芯片封装结构100的良率提高，可靠性增加。
进一步地，第一封装层110选用硅、陶瓷或者玻璃等材料，在第一封装层110表面层叠其他层(例如封装层、布线层)后，层叠于第一封装层110的层结构的表面共面度良好。共面度良好的表面为电连接件的良好电接触提供优良条件。例如，共面度良好的布线层表面与电连接件连接后，连接位置接触良好、不易脱离，对可靠性有利。
本申请实施例对桥接裸芯片101的数量不做限制，例如，桥接裸芯片101的数量可以为一个、两个、三个或者更多个。
本申请实施例对桥接裸芯片101的结构不做限制，例如，桥接裸芯片101的信号端和接地端位于同一侧，或者，桥接裸芯片101的信号端和接地端分布于两侧。
请再次参阅图4，在本申请的实施例中，第一封装层110具有第一表面111、第二表面112和第一容纳腔113。第一表面111和第二表面112相对设置，第一容纳腔113具有位于第一表面111的第一开口114。
在本申请的一些实施例中，如图5a所示，第一容纳腔113还具有位于第二表面112的第三开口115。或者，在本申请的一些实施例中，如图12a所示，第一容纳腔113为槽结构，第一容纳腔113具有底壁116，底壁116与第一表面111相对。
桥接裸芯片101位于第一容纳腔113内，示例性地，安装桥接裸芯片101时，可以将桥接裸芯片101穿过第一开口114置于第一容纳腔113内。
本申请实施例对第一容纳腔113的形状不做限制，第一容纳腔113的形状例如和桥接裸芯片101的外形相适配。示例性地，第一容纳腔113可以为方形腔、圆柱形腔、或者梯形腔等。
在本申请的示例中，芯片封装结构100还包括第一塑封料141。第一塑封料141位于桥接裸芯片101与第一容纳腔113内壁之间的间隙内。如此，第一塑封料141可以固定桥接裸芯片101，提高结构可靠性。此外，第一塑封料141可以使桥接裸芯片101的密封性能更佳，提高其电性能稳定性。
本申请实施例对第一塑封料141的材料不做限制，示例性地，第一塑封料141的材料为高分子聚合物，例如，第一塑封料141的材料为环氧树脂。环氧树脂良好的防水能力和密封性能为桥接裸芯片101提供稳定的工作环境，有益于桥接裸芯片101的电性能稳定。
可以理解的是，在第一容纳腔113的内壁和桥接裸芯片101贴合度较好的实施例中，也可以不设置第一塑封料141。
本申请实施例对第一裸芯片102和焊盘130的连接方式不做限制。
在一些实施例中，第一裸芯片102与焊盘130电连接。示例性的，如图4所示，芯片封装结构100还包括第一电连接件151，第一电连接件151贯穿第一表面111和第二表面112，第一裸芯片102通过第一电连接件151与焊盘130电连接。
第一电连接件151可以使第一裸芯片102与焊盘130之间有更多的布线方案，增加可选择性，且第一电连接件151可以充分利用第一封装层110的空间。
本申请实施例对第一电连接件151的材料不做限制，例如，第一电连接件151的材料为铜，铜的成本较低且导电性能良好，可降低信号损耗。
本申请实施例对第一电连接件151的分布不做限制，桥接裸芯片101对降低第一电连接件151在第一封装层110内的分布密度有利，因此，对降低芯片封装结构100的制造成本做出较大贡献。
在本申请的其他实施例中，芯片封装结构100可以不设置第一电连接件151，例如，第一裸芯片102通过桥接裸芯片101与焊盘130连接，其中，第一裸芯片102与桥接裸芯片101电连接，桥接裸芯片101与焊盘130电连接。
本申请实施例对第一裸芯片102和桥接裸芯片101的连接方式不做限制。请再次参阅图4，在本申请的一些实施例中，芯片封装结构100还包括第一布线层160。第一布线层160位于第二封装层120与第一封装层110之间，桥接裸芯片101通过第一布线层160与第一裸芯片102电连接。
第一布线层160可以为第一裸芯片102与桥接裸芯片101提供更多的互连空间。
在本申请的一些实施例中，为了布线需要，第一布线层160可以为多层，多层第一布线层160沿背离第一表面111的方向重叠设置，相邻两层第一布线层160电连接。
本申请实施例对桥接裸芯片101和焊盘130的连接方式不做限制。如图4所示，芯片封装结构100还包括第二布线层170，第二布线层170位于焊盘130与第一封装层110之间，桥接裸芯片101、焊盘130均与第二布线层170连接，桥接裸芯片101通过第二布线层170与焊盘130电连接。
在芯片封装结构100包括第一电连接件151的实施例中，第一电连接件151还可以与第二布线层170连接。
如此，第二布线层170可以增加桥接裸芯片101和焊盘130之间的互连路径，降低因互连线过密而产生的寄生电感。
在本申请的其他实施例中，可以不设置第二布线层170，例如，桥接裸芯片101直接与焊盘130电连接，第一电连接件151直接与焊盘130电连接。
本申请实施例对第一裸芯片102的数量不做限制，示例性地，第一裸芯片102可以为两个、三个、四个或者更多个，第一裸芯片102与桥接裸芯片101连接，实现第一裸芯片102的互连。
本申请实施例对第一裸芯片102的结构不做限制，可以根据芯片封装结构100的功能进行设置。
图4中，第一裸芯片102均位于一层第二封装层120内，可以理解的是，在本申请的其他实施例中，第一裸芯片102可以分布于不同的封装层内。
例如，第二封装层120具有多层，多层第二封装层120沿背离第一封装层110的方向叠层设置，多个第一裸芯片102分布于不同的第二封装层120。
第二封装层120的数量以及第一裸芯片102的分布关系可以根据芯片封装结构100的性能需求进行设置，本申请的实施例对此不做限制。
本申请实施例对第一封装层110和第二封装层120的结构不做限制，不同结构可能需要采用不同制备工艺形成。以下就不同的结构和方法作为示例进行描述。
实施例1
实施例1提供的一种芯片封装结构100如图4所示，图5a为本申请实施例1提供的一种第一封装层110和第一电连接件151的结构示意图。请一并参阅图4和图5a，实施例1中，第一容纳腔113贯穿第一表面111和第二表面112。
如图5a所示，第一容纳腔113具有位于第一开口114和第三开口115。第一开口114位于第一表面111，第三开口115位于第二表面112。
如此，安装桥接裸芯片101时，可以从第一开口114将桥接裸芯片101置入第一容纳腔113，也可以从第三开口115置入第一容纳腔113。其次，还可以从第一开口114或第三开口115对位于第一容纳腔113内的桥接裸芯片101进行位置调整。此外，桥接裸芯片101可以直接与焊盘130连接，有利于缩短信号路径长度，减小损耗。
本申请实施例对第一裸芯片102和第二封装层120的关系不做限制。如图4所示，第一裸芯片102埋设于第二封装层120内。
在本申请的实施例中，第一裸芯片102外周可以均被第二封装层120包裹。或者，第一裸芯片102面向第一表面111的表面和背离第一表面111的表面可以不被第二封装层120包裹。
本申请实施例对第二封装层120的材料不做限制，例如，第二封装层120包括第二塑封料142。第一裸芯片102埋设于第二塑封料142内，材料成本和工艺成本较低，第二塑封料142对第一裸芯片102的密封性能较好，有利于第一裸芯片102稳定运行。
在本实施例中，第二塑封料142的材料选择请参阅上述第一塑封料141的描述，此处不再赘述。
图5b为本申请实施例1提供的另一种芯片封装结构100的结构示意图，图5b与图4的主要区别在于第二封装层120。
图5b中，第二封装层120包括第二容纳腔121，第二容纳腔121具有位于第二封装层120表面的第二开口122。第一裸芯片102位于第二容纳腔121内，第二封装层120与第一裸芯片102的热膨胀系数相同。
相应地，第二封装层120与第一裸芯片102的热膨胀系数相同，与上述第一封装层110与桥接裸芯片101的热膨胀系数相同同理，此处不再赘述。
第二封装层120的材料请参阅第一封装层110的材料选择，此处不再赘述。
第二容纳腔121的结构请参阅上述图5a关于第一容纳腔113的结构，第二开口122请参阅上述图5a关于第一开口114的描述，此处不再赘述。
在一些实施例中，如图5b所示，第二容纳腔121内具有第三塑封料143，第三塑封料143位于第一裸芯片102与第二容纳腔121内壁之间的间隙内。同样，第三塑封料143使第一裸芯片102与第二封装层120之间的相对位置不易变化，且第三塑封料143可以为第一裸芯片102提供防水好且密闭的环境。
相应地，第三塑封料143的材料选择请参阅上述第一塑封料141的描述，此处不再赘述。
本申请对实施例1提供的芯片封装结构100的封装方法不做限制。
示例性地，图6a为本申请实施例1提供的芯片封装结构100示例一的封装流程图。如图6a所示，封装方法包括：
S1.将桥接裸芯片101置于第一封装层110的第一容纳腔113内。
第一封装层110的结构如图6b所示，其中，第一封装层110具有第一容纳腔113和相对的第一表面111和第二表面112。第一容纳腔113具有位于第一表面111的第一开口114，桥接裸芯片101和第一封装层110的热膨胀系数相同。
图6b中，第一容纳腔113还具有第三开口115，第三开口115位于第二表面112。
图6c为执行图6a所示S1后的结构示意图，桥接裸芯片101可以从第一开口114或者第三开口115置入第一容纳腔113内。
S2.于第一封装层110的第一表面111形成第二封装层120。
图6d为执行图6a所示S2后的结构示意图，其中，第二封装层120内形成有多个第一裸芯片102，多个第一裸芯片102均与桥接裸芯片101电连接。
S3.于第一封装层110的第二表面112形成焊盘130。
图6e为执行图6a所示S3后的结构示意图，其中，桥接裸芯片101或第一裸芯片102与焊盘130电连接。
在本申请的实施例中，S2与S3没有先后关系，可以先执行S2，也可以先执行S3。
图7a为本申请实施例1提供的芯片封装结构100的示例二的封装流程图。如图7a所示，S1之前还包括：
S4.于第一封装层110内形成第一电连接件151。
图7b为执行图7a中S4后的结构示意图。其中，第一电连接件151贯穿第一表面111和第二表面112。
图7a中，其余步骤请参阅图6a，其余不再赘述。形成焊盘130后，第一裸芯片102通过第一电连接件151与焊盘130电连接。
本申请实施例对图7a中S4的工艺不做限制。
例如，图7c为图7a中S4的流程图，S4包括：
S41.于图7d所示的第一封装层110内形成过孔144和第一容纳腔113。
图7e为执行图7c中S41后的结构示意图，本申请实施例对过孔144的数量、尺寸和大小不做限制。
S42.于过孔144内形成第一电连接件151。
执行图7c中S42后的结构如图7b所示。本申请实施例对第一电连接件151的形成工艺不做限制，例如，可以采用电镀、蒸镀、原子溅射等方式形成。
图8a为本申请实施例1提供的芯片封装结构100的示例三的封装流程图。如图8a所示，S1之后还包括：
S5.于桥接裸芯片101与第一容纳腔113内壁之间的间隙填充第一塑封料141。
图8b为执行图8a中S5后的结构示意图。
图9a为本申请实施例1提供的芯片封装结构100的示例四的封装流程图。如图9a所示，S2之前还包括：
S6.于第一封装层110的第一表面111形成第一布线层160。
图9b为执行图9a中S6后的结构示意图。本申请实施例对第一布线层160的形成工艺不做限制，示例性地，于第一表面111形成光刻胶层，对光刻胶层光刻形成图案，于前述图案内形成第一布线层160。
其余步骤请参阅图6a，其余不再赘述。形成第二封装层120后，桥接裸芯片101通过第一布线层160与第一裸芯片102电连接。
承上所述，在本申请的一些实施例中，芯片封装结构100还包括第二布线层170
图10a为本申请实施例1提供的芯片封装结构100的示例五的封装流程图。如图10a所示，S3之前还包括：
S7.于第一封装层110的第二表面112形成第二布线层170。
图10b为执行图10a中S7后的结构示意图。第二布线层170的形成工艺可参阅前述第一布线层160的描述，此处不再赘述。
其余步骤请参阅图6a，形成焊盘130后，桥接裸芯片101、焊盘130均与第二布线层170电连接。
请一并参阅图7a、图8a、图9a、图10a，在本申请的实施例中，S4、S5、S6和S7并不相互排斥，根据需求，可以在同一个封装方法中同时执行S4、S5、S6和S7，也可以择一、择二或者择三执行。
例如，在封装过程中，执行前述S1～S8可得到图4所示的芯片封装结构100。
在均执行S5和S6的实施例中，S5和S6可以通过同一工序形成。例如，同时于第一容纳腔113和第一表面111形成塑封料。然后在第一表面111的塑封料表面布线形成第一布线层160。
请再次参阅图4与图5b，实施例1中，第二封装层120的结构不做限制，因此，S2的工艺也不做限制。
图11a为图4所示结构中第二封装层120的制备流程图，如图11a所示，S2包括：
S21.将第一裸芯片102置于第一封装层110的第一表面111。
图11b为执行图11a中S21后的结构示意图。其中，第一裸芯片102为多个，多个第一裸芯片102间隔分布。
在第一表面111具有第一布线层160的实施例中，将第一裸芯片102置于第一布线层160的表面。
S22.形成第二封装层120。
执行图11a中S22的结构如图6d所示。其中，第一裸芯片102埋设于第二封装层120内。本申请实施例对S22中的具体工艺不做限制，例如，涂布塑封料然后固化塑封料形成第二封装层120。
图11a所示的工艺中，塑封料成本较低，有利于降低工艺成本。
图11c为图5b所示结构中S2的制备流程图，如图11c所示，S2包括：
S23.将第一裸芯片102置于第二封装层120的第二容纳腔121内。
图11d为执行图11c中S23后的结构示意图。其中，第二容纳腔121上设有第二开口122。第一裸芯片102与第二封装层120的热膨胀系数相同。
S24.将第二封装层120与第一封装层110的第一表面111连接。
图11e为执行图11c中S24后的结构示意图。
图11c所示的S2有利于降低第二封装层120和第一裸芯片102之间的翘曲。
于第一裸芯片102和第二容纳腔121的内侧壁之间的间隙填充第三塑封料143，具体步骤同图8a中的S5，此处不再赘述。
本申请实施例1提供的芯片封装结构100的制备方法能够有效改善桥接裸芯片101和第一封装层110之间的翘曲。
实施例1提供的封装方法可以预制第一封装层110，然后再与桥接裸芯片101连接，有利于缩短工艺流程。在第一封装层110可以选用硅、玻璃或者陶瓷等材料的实施例中，在第一封装层110表面涂布塑封料时，不易出现流痕和不润湿等问题。对芯片封装结构100的电性能稳定有重要帮助。
在本申请的实施例中，第一封装层110的结构不限于图4和图5b所示的结构。
实施例2
图12a为本申请实施例2提供的芯片封装结构100的一种结构示意图，实施例2与实施例1的主要区别在于第一封装层110的结构不相同。其余结构请参阅实施例1，此处不再赘述。
请参阅图12a，第一容纳腔113具有第一开口114和底壁116，底壁116与第一开口114相对。换言之，第一容纳腔113为槽结构，该槽结构具有底壁116。如此，底壁116可以承载桥接裸芯片101，有利于桥接裸芯片101的定位。
在芯片封装结构100包括第一塑封料141的实施例中，底壁116可以承接第一塑封料141的原料，第一塑封料141外溢的概率小，工艺过程可以不考虑因第一塑封料141外溢造成的影响。
图12b为本申请实施例2提供的芯片封装结构100的又一种结构示意图，请参阅图12b和图12a，图12b的示例与图12a的示例的区别在于：芯片封装结构100还包括第二电连接件152，第二电连接件152贯穿第二表面112和底壁116的表面。桥接裸芯片101通过第二电连接件152与焊盘130电连接。其余请参阅图12a示例的描述，此处不再赘述。
如此，第二电连接件152可以缩短桥接裸芯片101与焊盘130之间的路径，降低损耗。第二电连接件152为具有底壁116的结构提供更多的连接方案。
第二电连接件152的材料和结构请参阅第一电连接件151的相关描述，此处不再赘述。
本申请实施例对实施例2提供的芯片封装结构100的封装方法不做限制。其封装方法请参阅实施例1的图6a。
实施例2与实施例1的主要区别在于第一封装层110的预处理不同。换言之，实施例2可以采用图6a、图7a、图8a、图9a、图10a所示的流程图进行封装，主要区别在于，第一封装层110的形状不同。
示例性地，请再次参阅图6a，实施例2的封装方法与图6a所示的区别在于第一封装层110不同。图6a中S1中第一封装层110采用图13a所示的结构即可得到图12a所示的芯片封装结构100。
图13a中，第一封装层110的形成过程中，第一容纳腔113并未贯穿第一封装层110，第一容纳腔113具有位于第一表面111的第一开口114，第一容纳腔113还具有底壁116，底壁116与第一表面111相对。
图13b为本申请实施例2提供的一种封装流程图。图13b与图6a的区别在于，图13b的S1之前还包括：
S8.于图13a所示的第一封装层110形成第二电连接件152。
图13c为执行图13b中S8后的结构示意图，其中，第二电连接件152贯穿第一容纳腔113的底壁116和第二表面112。底壁116和第一开口114相对，桥接裸芯片101通过第二电连接件152与焊盘130电连接。
本申请实施例对第二电连接件152的形成工艺不做限制，可参阅实施例1中第一电连接件151的形成工艺，此处不再赘述。
同理，实施例2中，请再次参阅图7a、图8a、图9a、图10a和图13a，实施例2中也可以根据需求选择执行S4、S5、S6、S7和S8中的一个或多个，此处不再赘述。
实施例2提供的封装方法也可以预制第一封装层110、第二电连接件152，同样有利于缩短工艺流程。在需要预制第一电连接件151和第二电连接件152的实施例中，由于桥接裸芯片101的设置，第一电连接件151和第二电连接件152的密度可以较小，有利于节约工艺成本。
本申请实施例提供的芯片封装结构100能够有效改善第一封装层110和桥接裸芯片101的翘曲问题。在第一封装层110的材料包括硅、玻璃和陶瓷中的至少一种的实施例中，能改善现有的因为高分子材料在第一封装层110表面易流痕和不湿润的问题。因此，芯片封装结构100在使用过程中电性能得到较好保障。
相应地，包含上述芯片封装结构100的基站002和终端设备003的性能也因此而得到保证。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种芯片封装结构，其特征在于，所述芯片封装结构包括：
    第一封装层，所述第一封装层具有第一容纳腔、相对的第一表面和第二表面，所述第一容纳腔具有位于所述第一表面的第一开口；
    桥接裸芯片，所述桥接裸芯片位于所述第一容纳腔内；
    第二封装层，所述第二封装层靠近所述第一表面设置；
    多个第一裸芯片，多个所述第一裸芯片均位于所述第二封装层内；多个所述第一裸芯片均与所述桥接裸芯片电连接；
    焊盘，所述焊盘位于所述第二表面；所述桥接裸芯片或所述第一裸芯片与所述焊盘电连接；
    所述第一封装层与所述桥接裸芯片的热膨胀系数相同。
  2. [根据细则91更正 01.08.2023]
    根据权利要求1所述的芯片封装结构，其特征在于，所述第一封装层与所述桥接裸芯片的热膨胀系数相差小于6×10-6/℃。
  3. 根据权利要求2所述的芯片封装结构，其特征在于，所述第一封装层的材料包括硅、陶瓷以及玻璃中的至少一种。
  4. 根据权利要求1-3任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括：第一塑封料；所述第一塑封料位于所述桥接裸芯片与所述第一容纳腔内壁之间的间隙内。
  5. 根据权利要求1-4任一项所述的芯片封装结构，其特征在于，所述第一裸芯片埋设于所述第二封装层内。
  6. 根据权利要求5所述的芯片封装结构，其特征在于，所述第二封装层包括第二塑封料。
  7. 根据权利要求1-4任一项所述的芯片封装结构，其特征在于，所述第二封装层包括第二容纳腔，所述第二容纳腔具有位于所述第二封装层表面的第二开口，所述第一裸芯片位于所述第二容纳腔内，所述第二封装层与所述第一裸芯片的热膨胀系数相同。
  8. [根据细则91更正 01.08.2023]
    根据权利要求7所述的芯片封装结构，其特征在于，所述第二封装层与所述第一裸芯片的热膨胀系数相差小于6×10-6/℃。
  9. 根据权利要求7或8所述的芯片封装结构，其特征在于，所述第二封装层的材料包括硅、陶瓷以及玻璃中的至少一种。
  10. 根据权利要求7-9任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括：第三塑封料；所述第三塑封料位于所述第一裸芯片与所述第二容纳腔内壁之间的间隙内。
  11. 根据权利要求1-10任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括：第一电连接件；所述第一电连接件贯穿所述第一表面和所述第二表面；所述第一裸芯片通过所述第一电连接件与所述焊盘电连接。
  12. 根据权利要求1-11任一项所述的芯片封装结构，其特征在于，所述第一容纳腔还具有位于所述第二表面的第三开口。
  13. 根据权利要求1-11任一项所述的芯片封装结构，其特征在于，所述第一容纳腔具有底壁，所述底壁和所述第一开口相对。
  14. 根据权利要求13所述的芯片封装结构，其特征在于，所述芯片封装结构还包括：第二电连接件，所述第二电连接件贯穿所述第二表面和所述底壁的表面；所述桥接裸芯片通过所述第二电连接件与所述焊盘电连接。
  15. 根据权利要求1-14任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括：第一布线层，所述第一布线层位于所述第二封装层与所述第一封装层之间，所述桥接裸芯片通过所述第一布线层与所述第一裸芯片电连接。
  16. 根据权利要求1-15任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括：
    第二布线层，所述第二布线层位于所述焊盘与所述第一封装层之间，所述桥接裸芯片、所述焊盘均与所述第二布线层电连接。
  17. 一种芯片封装方法，其特征在于，包括：
    将桥接裸芯片置于第一封装层的第一容纳腔内；其中，所述第一封装层具有所述第一容纳腔和相对的第一表面和第二表面；所述第一容纳腔具有位于所述第一表面的第一开口；所述第一封装层与所述桥接裸芯片的热膨胀系数相同；
    于所述第一表面形成第二封装层；所述第二封装层内形成有多个第一裸芯片，多个所述第一裸芯片均与所述桥接裸芯片电连接；
    于所述第二表面形成焊盘，所述桥接裸芯片或所述第一裸芯片与所述焊盘电连接。
  18. 根据权利要求17所述的芯片封装方法，其特征在于，所述将桥接裸芯片置于第一封装层的第一容纳腔内之前还包括：
    于所述第一封装层内形成第一电连接件，所述第一电连接件贯穿所述第一表面和所述第二表面；所述第一裸芯片通过所述第一电连接件与所述焊盘电连接。
  19. 根据权利要求17或18所述的芯片封装方法，其特征在于，所述将桥接裸芯片置于第一封装层的第一容纳腔内之前还包括：
    于所述第一封装层形成第二电连接件；其中，所述第二电连接件贯穿所述第一容纳腔的底壁和所述第二表面，所述底壁和所述第一开口相对，所述桥接裸芯片通过所述第二电连接件与所述焊盘电连接。
  20. 根据权利要求17-19任一项所述的芯片封装方法，其特征在于，所述将桥接裸芯片置于第一封装层的第一容纳腔内之后还包括：
    于所述桥接裸芯片与所述第一容纳腔内壁之间的间隙填充第一塑封料。
  21. 根据权利要求17-20任一项所述的芯片封装方法，其特征在于，所述于所述第一表面形成第二封装层之前还包括：
    于所述第一表面形成第一布线层；
    其中，所述桥接裸芯片通过所述第一布线层与所述第一裸芯片电连接。
  22. 根据权利要求17-20任一项所述的芯片封装方法，其特征在于，所述于所述第一表面形成第二封装层包括：
    将所述第一裸芯片置于所述第一表面；
    形成所述第二封装层；其中，所述第一裸芯片埋设于所述第二封装层内。
  23. 根据权利要求17-20任一项所述的芯片封装方法，其特征在于，所述于所述第一表面形成第二封装层包括：
    将所述第一裸芯片置于所述第二封装层的第二容纳腔内，所述第二容纳腔上设有第二开口；所述第一裸芯片与所述第二封装层的热膨胀系数相同；
    将所述第二封装层与所述第一表面连接。
  24. 根据权利要求23所述的芯片封装方法，其特征在于，所述将所述第一裸芯片置于所述第二封装层的第二容纳腔内之后还包括：
    于所述第一裸芯片与所述第二容纳腔内壁之间的间隙形成第三塑封料。
  25. 根据权利要求17-24任一项所述的芯片封装方法，其特征在于，所述于所述第二表面形成焊盘之前还包括：
    于所述第二表面形成第二布线层，其中，所述桥接裸芯片、所述焊盘均与所述第二布线层电连接。
  26. 一种电子设备，其特征在于，所述电子设备包括印刷电路板和如权利要求1-16任一项所述的芯片封装结构；
    其中，所述焊盘与所述印刷电路板电性连接。
PCT/CN2023/097529 2022-08-16 2023-05-31 芯片封装结构、封装方法、电子设备 WO2024037115A1 (zh)

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