WO2024036724A1 - 一种存储系统及电子设备 - Google Patents

一种存储系统及电子设备 Download PDF

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Publication number
WO2024036724A1
WO2024036724A1 PCT/CN2022/124081 CN2022124081W WO2024036724A1 WO 2024036724 A1 WO2024036724 A1 WO 2024036724A1 CN 2022124081 W CN2022124081 W CN 2022124081W WO 2024036724 A1 WO2024036724 A1 WO 2024036724A1
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Prior art keywords
memory
storage system
memory module
connection
memory controller
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PCT/CN2022/124081
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English (en)
French (fr)
Inventor
文继伟
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a storage system and electronic equipment.
  • the present disclosure discloses a storage system and electronic equipment that can improve the data transmission bandwidth and transmission rate between a memory controller and a memory module, thereby improving the data transmission quality between the memory controller and the memory module.
  • a storage system which is characterized by including:
  • the memory controller is arranged on the base board;
  • the memory module is arranged on the base board, and the memory module and the memory controller are at least partially connected through cables on the outside of the base board.
  • the storage system further includes a first transit structure
  • the memory controller is connected to the memory module through the first transfer structure
  • the first transfer structure and the memory controller are connected through cables, or the first transfer structure and each memory module are connected through cables.
  • the number of memory modules is N
  • the storage system further includes:
  • N groups of corresponding first data channels and first cables, and the i-th group of corresponding first data channels and first cables are used to transmit data between the memory controller and the i-th memory module, where N is Positive integer, i is any positive integer less than or equal to N;
  • the first data channel in the i-th group is arranged inside the substrate and includes a first via hole, a second via hole and a first trace.
  • the upper surface of the first via hole is connected to the memory controller, and the upper surface of the second via hole is connected to the memory controller.
  • the upper surface is connected to the first transfer structure, one end of the first trace is connected to the lower surface of the first via hole, and the other end of the first trace is connected to the lower surface of the second via hole;
  • One end of the first cable in the i-th group is connected to the first switching structure, and the other end of each first cable is connected to the i-th memory module.
  • the number of memory modules is N,
  • the storage system also includes:
  • N groups of corresponding second data channels and second cables, and the i-th group of corresponding second data channels and second cables are used to transmit data between the memory controller and the i-th memory module, where N is Positive integer, i is any positive integer less than or equal to N;
  • one end of the second cable in the i-th group is connected to the memory controller, and the other end of the second cable in the i-th group is connected to the first switching structure;
  • the second data channel in the i-th group is arranged inside the substrate and includes a third via hole, a fourth via hole and a second trace.
  • the upper surface of the third via hole is connected to the first transfer structure, and the fourth via hole is connected to the first transfer structure.
  • the upper surface is connected to the i-th memory module, one end of the second trace is connected to the lower surface of the third via hole, and the other end of the second trace is connected to the lower surface of the fourth via hole.
  • the first transfer structure is disposed above the packaging substrate of the memory controller.
  • the storage system further includes:
  • a memory connection structure is provided on the substrate.
  • the memory connection structure is used to connect the memory module to fix the memory module on the substrate.
  • the number of memory modules is multiple
  • the memory connection structure includes multiple memory connection substructures
  • Each memory connection substructure is provided with at least one groove, wherein each groove is used to connect a memory module.
  • the number of memory modules is N, where N is a positive integer,
  • the memory connection structure includes a memory connection substructure
  • N grooves are provided on the memory connection substructure
  • the i-th groove is used to fix the i-th memory module, and i is any positive integer less than or equal to N.
  • each memory connection substructure includes:
  • the first connection part is used to connect with the target data transmission module.
  • the target data transmission module is a memory controller, a first switching structure or a second switching structure;
  • the second connecting part is provided with a groove.
  • the second connection portion at least partially surrounds the first connection portion.
  • the first connection part is connected to the memory module in each groove through a third cable.
  • the third cable is at least partially buried inside the second connection part.
  • the memory module is a memory module or a memory chip.
  • the memory controller is a central controller CPU or a system on a chip SoC.
  • the number of memory modules is N, and N is a positive integer
  • At least one memory module among the N memory modules is connected to the memory controller at least partially through a cable.
  • an electronic system including the storage system provided by the embodiment of the present disclosure.
  • the cables can increase the data transmission rate and reduce the impact of external physical factors on The interference of the transmission signal can thereby increase the data transmission bandwidth and transmission rate between the memory controller and the memory module, thereby improving the data transmission quality between the memory controller and the memory module.
  • Figure 1 shows a schematic structural diagram of a storage system provided by an embodiment of the present disclosure
  • Figure 2 shows a schematic structural diagram of another storage system provided by an embodiment of the present disclosure
  • Figure 3 shows a schematic structural diagram of an exemplary data channel provided by an embodiment of the present disclosure
  • Figure 4 shows a schematic structural diagram of an exemplary storage system provided by an embodiment of the present disclosure
  • Figure 5 shows a schematic diagram of the connection method between a first switching structure and a memory controller provided by an embodiment of the present disclosure
  • Figure 6 shows a schematic diagram of the connection method between another first switching structure and a memory controller provided by an embodiment of the present disclosure
  • Figure 7 shows a schematic diagram of yet another connection method between the first switching structure and the memory controller provided by an embodiment of the present disclosure
  • Figure 8 shows a schematic structural diagram of yet another storage system provided by an embodiment of the present disclosure.
  • Figure 9 shows a schematic structural diagram of yet another storage system provided by an embodiment of the present disclosure.
  • Figure 10 shows a schematic structural diagram of yet another storage system provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic diagram of an exemplary memory connection substructure provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic diagram of another exemplary memory connection substructure provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic diagram of yet another exemplary memory connection substructure provided by an embodiment of the present disclosure.
  • orderly processing of data can be achieved through a storage system composed of memory modules and memory controllers.
  • Double Data Rate (DDR) storage technology becomes faster and faster, the efficiency requirements are also getting higher and higher. Therefore, how to improve the data transmission quality between the memory controller and the memory module has become a problem that needs to be solved.
  • DDR Double Data Rate
  • embodiments of the present disclosure provide a storage system and electronic device, which can be applied in semiconductor storage scenarios.
  • they can be used in semiconductor storage scenarios based on DDR storage systems.
  • the memory module of the DDR storage system may include at least one DDR memory.
  • the memory module and the memory controller can be connected at least partially through cables on the outside of the substrate, thereby improving the data transmission quality between the memory controller and the memory module. .
  • Figure 1 shows a schematic structural diagram of a storage system provided by an embodiment of the present disclosure.
  • the storage system may include a substrate 11 , a memory controller 12 and a memory module 13 .
  • the substrate 11 may be a structure used to support the memory controller 12, the memory module 13, and the like. In some embodiments, the substrate 11 can also realize the interconnection between the memory controller 12 and the memory module 13 . For example, it may be a printed circuit board (Printed Circuit Board, PCB) or other circuit board. It should be noted that substrates of other materials can also be selected according to actual production needs and specific production scenarios, and there are no specific restrictions on this.
  • PCB printed Circuit Board
  • the memory controller 12 After the substrate 11 has been described, the memory controller 12 will be described next.
  • the memory controller 12 is disposed on the substrate 11 .
  • the memory controller 12 is used to control the memory module 13 and perform data communication.
  • the memory controller 12 may be a device or module with a memory module control function.
  • the memory controller 12 may be a central controller (Central Processing Unit, CPU), a system-on-a-chip (SoC), or the like.
  • CPU Central Processing Unit
  • SoC system-on-a-chip
  • the memory module 13 is disposed on the substrate 11 .
  • the memory module 13 is used for storing digital data.
  • the number of memory modules 13 may be N, where N is a positive integer greater than or equal to 1.
  • a memory module 13 may include at least one memory chip.
  • a memory module 13 may be a single memory chip or a memory module formed by multiple memory chips.
  • the memory module 13 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM).
  • DRAM Dynamic Random Access Memory
  • the memory module may be a DDR memory, such as fourth-generation double-rate synchronous dynamic random access memory (DDR4SDRAM), fourth-generation low-power double-rate synchronous dynamic random access memory (LPDDR4SDRAM), fifth-generation double-rate synchronous dynamic random access memory (LPDDR4SDRAM),
  • DDR4SDRAM fourth-generation double-rate synchronous dynamic random access memory
  • LPDDR4SDRAM fourth-generation low-power double-rate synchronous dynamic random access memory
  • LPDDR4SDRAM fifth-generation double-rate synchronous dynamic random access memory
  • DDR5SDRAM rate synchronous dynamic random access memory
  • LPDDR4SDRAM fifth-generation low-power double rate synchronous dynamic random access memory
  • the memory module may be a single inline memory module (Single Inline Memory Module, SIMM), dual inline memory module (Dual-Inline-Memory-Modules, DIMM), inline memory module ( Rambus Inline Memory Module, RIMM) and other memory modules.
  • SIMM Single Inline Memory Module
  • DIMM Dual Inline memory module
  • DIMM Dual-Inline-Memory-Modules
  • RIMM Rambus Inline Memory Module
  • the embodiments of the present disclosure can improve the data transmission quality between memory modules of different granularities, such as memory modules and memory chips, and memory controllers, thereby improving the applicability of the solution.
  • the memory module 13 and the memory controller 12 are connected at least partially through cables on the outside of the substrate (not shown in FIG. 1).
  • the cable can be an independent component.
  • the independence of cables may refer to the mutual independence between cables, and/or may refer to the independent arrangement between the cables outside the substrate and the substrate.
  • the memory module 13 and the memory controller 12 are partially connected through cables, that is, part of the structure needs to be transmitted through cables, and this part of the structure cannot be transmitted using wiring inside the substrate, or it cannot be transmitted using cables. Cables and wiring inside the substrate are used for joint transmission, otherwise the high bandwidth and high speed requirements of the DDR system cannot be met.
  • Other parts are connected through traces inside the substrate or semiconductor connection processes such as through silicon vias. It should be noted that, in addition to some connections through cables, other parts can also be connected through other connection methods, and there is no specific restriction on this.
  • connection relationship between N memory modules 13 and the memory controller when the number of memory modules 13 is N, at least one memory module among the N memory modules is connected to the memory controller 12 at least partially through a cable.
  • the N memory modules 13 may include at least one first memory module and at least one second memory module, wherein each first memory module is at least partially connected to the memory controller 12 through a cable. Connection, each second memory module can be connected to the memory controller 12 through other connection methods besides cables. For example, for N memory modules 13, one of the two adjacent memory modules is connected to the memory controller 12 through a cable, and the other of the two adjacent memory modules is connected to the memory through the adjacent memory module. Controller 12 is connected.
  • the spacing between the traces can be widened, which reduces the impact of crosstalk, loss, reflection and other data transmission quality between the traces, and improves the data transmission quality between the memory controller 12 and the memory module 13 .
  • each of the N memory modules 13 and the memory controller 12 may be connected at least partially through cables.
  • the data transmission rate can be increased because the cable can be avoided and the interference of external physical factors on the transmission signal can be reduced, thereby improving the data transmission bandwidth and transmission rate between the memory controller and each memory module.
  • the cables can increase the data transmission rate and reduce the impact of external physical factors on the transmission.
  • Signal interference can further increase the data transmission bandwidth and transmission rate between the memory controller 12 and the memory module 13 , thereby improving the data transmission quality between the memory controller 12 and the memory module 13 .
  • cables can reduce the impact of external physical factors such as crosstalk, loss, and reflection caused by the substrate, thereby improving the rate and system delay of the DDR system, thus enabling Taking into account the bandwidth, speed, efficiency and other requirements of the storage system, the quality of data transmission between the memory controller 12 and the memory module 13 is improved.
  • the storage system also includes a first transit structure.
  • the first transfer structure may be disposed above the substrate.
  • the memory controller 12 is connected to the memory module 13 through the first switching structure.
  • the number of first transfer structures may be one.
  • one first transfer structure may realize transfer between the memory controller 12 and N memory modules 13 .
  • the number of first transfer structures may be multiple, and each first transfer structure may implement transfer between the memory controller 12 and at least one memory module 13 .
  • the number of first switching structures may be N, and each first switching structure may implement switching between the memory controller 12 and a memory module 13 .
  • the first transfer structure is connected to the memory controller 12 through cables, or the first transfer structure is connected to each memory module 13 through cables.
  • the first transfer structure and the memory controller 12 can be connected through cables, or the first transfer structure and each memory module 13 can be connected through cables.
  • the interference of external physical factors on the transmission signal can be reduced through the cable, thereby improving the data transmission bandwidth and transmission rate between the memory controller 12 and the memory module 13, thus improving the communication between the memory controller 12 and the memory module 13. Data transfer quality.
  • FIG. 2 shows a schematic structural diagram of another storage system provided by an embodiment of the present disclosure.
  • the storage system also includes N groups of corresponding first data channels 20 and first cables 30 .
  • the dotted arrows in Figure 2 represent data channels, and the solid lines represent cables.
  • the i-th group of corresponding first data channels 20 and first cables 30 are used to transmit the memory controller 12 and the i-th memory module 13 (not shown in Figure 2), where N is a positive integer and i is any positive integer less than or equal to N.
  • N is a positive integer
  • i is any positive integer less than or equal to N.
  • the first data channel 20 and the first cable 30 corresponding to the i-th group after the data is transmitted to the first switching structure through the first data channel 20, the data corresponding to the first switching structure can be determined at the first switching structure.
  • the first cable 30 corresponding to the first data channel 20 then continues to transmit along the first cable 30 to the ith memory module 13 .
  • FIG. 3 shows a schematic structural diagram of an exemplary data channel provided by an embodiment of the present disclosure.
  • N groups of first data channels are provided inside the substrate 11 .
  • the depths of the N groups of first data channels compared to the surface of the substrate may be different.
  • the first data channel 20 in the i-th group includes a first via 21, a second via 22, and a first trace 23.
  • the upper surface of the first via hole 21 is connected to the memory controller 12
  • the upper surface of the second via hole 22 is connected to the first transfer structure 14
  • one end of the first trace 23 is connected to the lower surface of the first via hole 21
  • the other end of the first trace 23 is connected to the lower surface of the second via hole 22 .
  • one end of the first cable 30 in the i-th group is connected to the first switching structure 14, and the other end of each first cable 30 is connected to the i-th memory module.
  • the memory controller 12 and the first transfer structure are connected by wiring in the substrate, so that the connection between the memory controller 12 and the first transfer structure can be realized using the semiconductor interconnection process. connection between the first transfer structure and the memory module 13 using cable technology. Therefore, in the semiconductor manufacturing process, in a scenario where the memory controller 12 and the memory module 13 cannot be directly connected by cables, the process problems can be overcome while improving the data transmission between the memory controller 12 and the memory module 13 quality.
  • FIG. 4 shows a schematic structural diagram of an exemplary storage system provided by an embodiment of the present disclosure.
  • the memory controller 12 and the first switching structure may be arranged adjacently.
  • the wiring distance can be further reduced and the cable length can be increased, thereby further improving the data transmission quality between the memory controller 12 and the memory module 13 .
  • this process problem can be overcome while ensuring the data transmission quality.
  • the first transfer structure is disposed above the packaging substrate of the memory controller 12 . This setup method is explained below with several examples.
  • FIG. 5 shows a schematic diagram of the connection method between a first switching structure and a memory controller provided by an embodiment of the present disclosure.
  • the memory controller 12 may include a memory control chip (die) 121 , a packaging substrate 122 and a packaging layer 123 .
  • the orthographic projection of the first transfer structure on the substrate surface may be located in the memory area (Memory Area).
  • the first transfer structure 14 may be disposed on one side of the memory controller 12 and located on the packaging substrate 122 .
  • the memory control chip 121 can be connected to the packaging substrate 122 through M first connection elements 41, and the first transfer structure 14 can be connected to the packaging substrate 122 through M second connection elements 42, wherein the M first connections
  • the component 41 is connected to the M second connection components 42 through M intra-board wirings 20 .
  • M may be an integer equal to N, or M may be smaller than or larger than N, and there is no specific limitation on this.
  • the memory control chip 121 can also be connected to the packaging substrate 122 through at least one third connection element 43, so as to be connected to the fourth connection element 44 and between the fourth connection element 44 and the third connection element 43.
  • the intra-board traces 45 between them supply power to the memory control chip 121 or transmit signals.
  • first connection element 41 , the second connection element 42 , the third connection element 43 and the fourth connection element 44 can be solder balls, solder bumps (bumps) or other connection elements. Specific restrictions.
  • the packaging substrate 122 may be connected to the substrate 11 through the fourth connection element 44 .
  • the material of the encapsulation layer 123 can be epoxy molding compound (EMC). It should be noted that other encapsulation methods can also be used in the embodiments of the present disclosure, and there is no specific limitation on this. By selecting EMC as the material of the packaging layer 123, the air tightness, high temperature aging resistance, and ultraviolet attenuation resistance of the chip can be ensured, and the chip has the characteristics of small size and low cost.
  • EMC epoxy molding compound
  • the length of the wiring can be shortened, thereby further improving the data transmission quality between the memory controller 12 and the memory module 13 .
  • the quality of data transmission between the memory controller 12 and the memory module 13 can be improved while overcoming the process problems.
  • FIG. 6 shows a schematic diagram of the connection between another first switching structure and a memory controller provided by an embodiment of the present disclosure.
  • FIG. 6 The difference between FIG. 6 and FIG. 5 is that grooves 124 are formed on the packaging layer 123 .
  • the first transfer structure 14 can be located in the groove 124 and connected to the packaging substrate 122 through M second connection elements 42 . It should be noted that for other contents shown in FIG. 6 , reference can be made to the relevant description of the previous example of this disclosure in combination with FIG. 5 , and will not be described again here.
  • the length of the wiring can be shortened, thereby further improving the data transmission quality between the memory controller 12 and the memory module 13 .
  • the quality of data transmission between the memory controller 12 and the memory module 13 can be improved while overcoming the process problems.
  • FIG. 7 shows a schematic diagram of yet another connection method between the first switching structure and the memory controller provided by an embodiment of the present disclosure.
  • the first transfer structure 14 can be connected to the memory control chip 121 through the fifth connecting element 46 .
  • the fifth connection element 46 can be a through silicon via (TSV). It should be noted that other connection elements can also be used, and there is no specific limitation on this.
  • the length of the trace can be increased, thereby further improving the data transmission quality between the memory controller 12 and the memory module 13 .
  • the fifth connection element can be used to overcome the process problems and improve the connection between the memory controller 12 and the memory module 13. Data transfer quality.
  • the first transfer structure 14 can be directly connected to the memory control chip 121 through the through silicon via, without the need to set up additional wiring in the packaging substrate, thereby avoiding the need for wiring during the interconnection process.
  • Crosstalk, loss, reflection and other problems caused by wiring in the packaging substrate can further improve the signal transmission quality.
  • FIG. 8 shows a schematic structural diagram of yet another storage system provided by an embodiment of the present disclosure.
  • the storage system also includes N groups of corresponding second data channels 50 and second cables 60 .
  • the second data channel 50 and the second cable 60 corresponding to the i-th group are used to transmit data between the memory controller 12 and the i-th memory module 13, where N is a positive integer and i is less than or equal to N is any positive integer.
  • each second data channel 50 in the i-th group may be disposed inside the substrate, and each second data channel 50 may include a third via hole, a fourth via hole and a second trace.
  • the upper surface of the third via hole is connected to the first transfer structure, and the upper surface of the fourth via hole is connected to the i-th memory module.
  • One end of the second trace is connected to the lower surface of the third via hole, and the other end of the second trace is connected to the lower surface of the fourth via hole.
  • the second data channel 50 can also use other semiconductor interconnection processes, such as being connected to the packaging substrate of the memory chip in the memory module through solder balls, solder bumps, through silicon vias, etc. There is no specific limit on this.
  • connection between the first transfer structure 14 and the memory controller 12 can be carried out through cables during the semiconductor manufacturing process, thereby reducing crosstalk, loss, reflection and other external physical factors caused by the substrate through the cables. influence, thereby improving the speed and system delay of the DDR system, thereby taking into account the bandwidth, speed, efficiency and other requirements of the storage system, and improving the quality of data transmission between the memory controller 12 and the memory module 13 .
  • the storage system provided by the embodiment of the present disclosure may further include a plurality of second transfer structures.
  • FIG. 9 shows a schematic structural diagram of yet another storage system provided by an embodiment of the present disclosure.
  • the storage system may also include a plurality of second transition structures 16 .
  • the memory controller 12 performs data transmission with the memory module (not shown in Figure 9) through a plurality of second switching structures 16;
  • data transmission meets at least one of the following transmission methods one to three:
  • Transmission method 1 Data transmission is performed through cables between the memory controller 12 and the first second switching structure.
  • Transmission method two data transmission is performed through cables between at least two adjacent second switching structures.
  • the memory controller 12 is connected to the first second transfer structure through a data channel 70 such as an intra-substrate wiring, and the memory module is connected to the last second transfer structure.
  • each second switching structure 14 can be connected through a cable 80 . Therefore, the conversion between the semiconductor interconnection process and the cable interconnection process can be realized through the first second transfer structure and the last second transfer structure, overcoming the process defects of chips that cannot be connected by cables, and improving production. efficiency.
  • the data channel 70 such as an intra-substrate wiring
  • the memory module is connected to the last second transfer structure.
  • each second switching structure 14 can be connected through a cable 80 . Therefore, the conversion between the semiconductor interconnection process and the cable interconnection process can be realized through the first second transfer structure and the last second transfer structure, overcoming the process defects of chips that cannot be connected by cables, and improving production. efficiency.
  • Transmission method three Data is transmitted through cables between the last transfer structure and the memory module.
  • the storage system further includes: N third cables.
  • FIG. 10 shows N third cables 90, where the i-th third cable 90 is used to realize the connection between the memory controller 12 and the i-th memory module 13, where N is a positive integer, i is any positive integer less than or equal to N.
  • One end of the i-th third cable 90 is connected to the memory controller 12, and the other end of the i-th third cable 90 is connected to the i-th memory module 13.
  • the storage system also includes a memory connection structure 15 .
  • the memory connection structure 15 is disposed on the substrate 11 .
  • the memory connection structure 15 is used to connect the memory module 13 to fix the memory module 13 on the substrate.
  • the memory connection structure 15 may be implemented as a memory socket.
  • the memory connection structure 15 may be provided with a groove to fix the memory module by inserting it into the groove.
  • the memory connection structure 15 can also transfer data between the first switching structure 14 and the memory module 13 .
  • the first switching structure 14 can be connected to the memory connection structure 15
  • the memory connection structure 15 is connected to the memory module 13 .
  • the memory module 13 can be fixed, thereby ensuring the reliability of the memory system.
  • the memory connection structure 15 includes multiple memory connection substructures.
  • Each memory connection substructure is provided with at least one groove. Each groove is used to connect a memory module.
  • the memory connection substructure may include N memory connection substructures, in which the i-th memory connection substructure is connected to the i-th memory module.
  • multiple memory connection substructures can be set up relatively independently, so that the number of memory connection substructures and their positions on the substrate can be flexibly set according to the number of memory modules, which improves flexibility.
  • the number of memory modules is N
  • the memory connection structure includes a memory connection substructure.
  • N grooves are provided on the memory connection substructure.
  • the i-th groove is used to fix the i-th memory module, and i is any positive integer less than or equal to N.
  • N grooves can be fixed through one memory connection structure, which reduces the area of the memory connection structure and thus the storage system, facilitates manufacturing and production, and reduces manufacturing costs.
  • each memory connection substructure includes: a first connection part and a second connection part.
  • first connection part and the second connection part may be spaced apart.
  • the first connection part is used to connect with the target data transmission module.
  • the target data transmission module is a memory controller, a first switching structure or a second switching structure.
  • the target data transmission module is the memory controller.
  • the target data transmission module is the first transfer structure. Transfer structure.
  • the target data transmission module is the second switching structure.
  • a groove is provided on the second connection part for fixing the memory module.
  • FIG. 11 is a schematic diagram of an exemplary memory connection substructure provided by an embodiment of the present disclosure.
  • the first memory connection substructure 151 may include a first connection part 1511 , a second connection part 1512 and a third cable 1513 .
  • One end of the third cable 1513 is connected to the first connecting part 1511, and the other end of the third cable 1513 is used to connect to the memory module 13.
  • the second connecting part 1512 may be provided with a plurality of first grooves A1, and the memory module 13 may be inserted into the first grooves A1. And, the plurality of first grooves A1 may be located on different sides of the second connecting portion 1512 .
  • FIG. 12 is a schematic diagram of another exemplary memory connection substructure provided by an embodiment of the present disclosure.
  • the difference between the second memory connection substructure 152 shown in FIG. 12 and the first memory connection substructure 151 shown in FIG. 11 is that the plurality of first grooves A1 may be located on the same side of the second connection portion 1522 .
  • FIG. 13 is an example diagram of yet another exemplary memory connection substructure provided by an embodiment of the present disclosure.
  • the third memory connection substructure 153 shown in FIG. 13 is connected to the first memory connection substructure shown in FIG. 11
  • the difference between the connection substructure 151 is that a first groove A1 is provided on the third memory connection structure 153 .
  • the memory connection structure 15 may be provided with N third memory connection structures 153 .
  • the memory controller side can be connected through the first connection part 151, and the memory module can be fixed through the second connection part 152, thereby ensuring data transmission while improving the stability and reliability of the storage system. .
  • the second connection portion at least partially surrounds the first connection portion.
  • the second connecting part may be provided with a groove, and the first connecting part may be at least partially located within the groove.
  • the second connection part may also be provided with a second groove A2, and the first connection part may be partially located within the second groove A2 to realize the connection of the second connection part to the first 151 surround.
  • the data transmission distance between the first connection part and the second connection part can be reduced, thereby improving the data transmission quality.
  • the first connection part is connected to the memory module in each groove through a third cable.
  • the first connection part can also be connected to the memory module 13 in other ways, and there is no specific limitation on the connection method.
  • connection method signal crosstalk and loss during transmission from the first connection part to each memory module can be reduced through the third cable, thereby achieving orderly connection and improving data transmission quality.
  • the third cable is at least partially buried inside the second connection part.
  • the remaining part of the third cable may be located outside the second connection part.
  • third cables may also be located outside the second connection part, which is not specifically limited.
  • the area of the storage system can be reduced while fixing the third cable, and the orderly connection of each memory module can be achieved, which improves the efficiency of the storage system. Memory system reliability.
  • embodiments of the present disclosure also provide an electronic device, which may include a memory system.
  • a memory system please refer to the above-mentioned part of the embodiment of the present disclosure in conjunction with the relevant descriptions in FIGS. 1-13 , and will not be described again here.
  • the memory module and the memory controller can be connected at least partially through the cable outside the substrate, and the cable can increase the data transmission rate and reduce the impact of external physical factors on the transmission signal. Interference can thereby increase the data transmission bandwidth and transmission rate between the memory controller and the memory module, thereby improving the data transmission quality between the memory controller and the memory module.
  • the memory module and the memory controller can be connected at least partially through cables on the outside of the substrate, and the cables can increase the data transmission rate and reduce the interference of external physical factors on the transmission signals, it is possible to The data transmission bandwidth and transmission rate between the memory controller and the memory module are improved, thereby improving the data transmission quality between the memory controller and the memory module.

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Abstract

一种存储系统及电子设备，涉及半导体技术领域。该系统包括：基板（11）；内存控制器（12），设置于所述基板（11）上；内存模组（13），设置于所述基板（11）上，所述内存模组（13）与所述内存控制器（12）之间至少部分通过基板（11）外侧的线缆进行连接。能够提高内存控制器（12）与内存模组（13）之间的数据传输质量。

Description

一种存储系统及电子设备
交叉引用
本公开要求于2022年08月17日提交的申请号为202210987567.7、名称为“一种存储系统及电子设备”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，特别涉及一种存储系统及电子设备。
背景技术
在半导体技术中，可以通过包括内存模组和内存控制器在内的存储系统，来实现数据的有序处理。
然而，在现有的存储系统中，内存控制器与内存模组之间往往数据传输质量较差。
因此，如何提高内存控制器与内存模组之间的数据传输质量成为了需要解决的问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开公开了一种存储系统及电子设备，能够提高内存控制器与内存模组之间的数据传输带宽和传输速率，从而提高了内存控制器与内存模组之间的数据传输质量。
为达到上述目的，本公开提供以下技术方案：
根据本公开的一方面，提供了一种存储系统，其特征在于，包括：
基板；
内存控制器，设置于基板上；
内存模组，设置于基板上，内存模组与内存控制器之间至少部分通过基板外侧的线缆进行连接。
在一个实施例中，存储系统还包括第一转接结构；
其中，内存控制器通过第一转接结构与内存模组进行连接，
第一转接结构与内存控制器之间通过线缆进行连接，或，第一转接结构与各内存模组之间通过线缆进行连接。
在一个实施例中，内存模组的数量为N个，存储系统还包括：
N组对应的第一数据通道和第一线缆，第i组对应的第一数据通道和第一线缆用于传输内存控制器与第i个内存模组之间的数据，其中，N为正整数，i为小于或等于N的任意正整数；
其中，第i组中的第一数据通道设置于基板内部，包括第一过孔、第二过孔和第一走线，第一过孔的上表面与内存控制器连接，第二过孔的上表面与第一转接结构连接，第一走线的一端与第一过孔的下表面连接，第一走线的另一端与第二过孔的下表面连接；
第i组中的第一线缆的一端与第一转接结构连接，各第一线缆的另一端与第i个内存模组连接。
在一个实施例中，内存模组的数量为N个，
存储系统还包括：
N组对应的第二数据通道和第二线缆，第i组对应的第二数据通道和第二线缆用于传输内存控制器与第i个内存模组之间的数据，其中，N为正整数，i为小于或等于N的任意正整数；
其中，第i组中的第二线缆的一端与内存控制器连接，第i组中的第二线缆的另一端与第一转接结构连接；
第i组中的第二数据通道设置于基板内部，包括第三过孔、第四过孔和第二走线，第三过孔的上表面与第一转接结构连接，第四过孔的上表面与第i个内存模组连接，第二走线的一端与第三过孔的下表面连接，第二走线的另一端与第四过孔的下表面连接。
在一个实施例中，第一转接结构设置于内存控制器的封装基板的上方。
在一个实施例中，存储系统还包括：
设置于基板上的内存连接结构，内存连接结构用于连接内存模组，以将内存模组固定设置于基板之上。
在一个实施例中，内存模组的数量为多个，
内存连接结构包括多个内存连接子结构；
其中，各内存连接子结构上设置有至少一个凹槽，其中，各凹槽用于连接一个内存模组。
在一个实施例中，内存模组的数量为N个，其中，N为正整数，
内存连接结构包括一个内存连接子结构，
其中，内存连接子结构上设置有N个凹槽；
其中，第i个凹槽用于固定第i个内存模组，i为小于或等于N的任意正整数。
在一个实施例中，每一内存连接子结构包括：
第一连接部，用于与目标数据传输模块连接，目标数据传输模块为内存控制器、第一转接结构或者第二转接结构；
第二连接部，第二连接部上设置有凹槽。
在一个实施例中，第二连接部至少部分环绕第一连接部。
在一个实施例中，第一连接部与各凹槽内的内存模组通过第三线缆连接。
在一个实施例中，第三线缆至少部分埋设于第二连接部内部。
在一个实施例中，内存模组为内存模块或者内存芯片。
在一个实施例中，内存控制器为中央控制器CPU或者片上系统SoC。
在一个实施例中，内存模组的数量为N个，N为正整数；
N个内存模组中的至少一个内存模组与内存控制器之间至少部分通过线缆进行连接。
根据本公开的另一方面，提供了一种电子系统，包括本公开实施例提供的存储系统。
根据本公开实施例提供的存储系统及电子设备，由于内存模组与内存控制器之间可以至少部分通过基板外侧的线缆进行连接，由于线缆可以提高数据传输速率且能降低外部物理因素对传输信号的干扰，进而能够提高内存控制器与内存模组之间的数据传输带宽和传输速率，从而提高了内存控制器与内存模组之间的数据传输质量。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开实施例提供的一种存储系统的结构示意图；
图2示出了本公开实施例提供的另一种存储系统的结构示意图；
图3示出了本公开实施例提供的一种示例性的数据通道的结构示意图；
图4示出了本公开实施例提供的一种示例性的存储系统的结构示意图；
图5示出了本公开实施例提供的一种第一转接结构与内存控制器之间的连接方式示意图；
图6示出了本公开实施例提供的另一种第一转接结构与内存控制器之间的连接方式示意图；
图7示出了本公开实施例提供的又一种第一转接结构与内存控制器之间的连接方式示意图；
图8示出了本公开实施例提供的又一种存储系统的结构示意图；
图9示出了本公开实施例提供的再一种存储系统的结构示意图；
图10示出了本公开实施例提供的再一种存储系统的结构示意图；
图11是本公开实施例提供的一种示例性的内存连接子结构的示意图；
图12是本公开实施例提供的另一种示例性的内存连接子结构的示意图；
图13是本公开实施例提供的又一种示例性的内存连接子结构的示意图。
具体实施方式
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开 能够在不同的实施例上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图在本质上是作说明之用，而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构、系统和步骤。应理解的是，可以使用部件、结构、示例性装置、系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”、“之间”、“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
在半导体技术中，可以通过内存模组和内存控制器构成的存储系统来实现数据的有序处理。
然而，内存控制器与内存模组之间的数据传输质量往往制约着存储技术的发展。比如，随着双倍速率(Double Data Rate，DDR)存储技术的速率越来越快，对效率要求也越来越高。因此，如何提高内存控制器与内存模组之间的数据传输质量成为了需要解决的问题。
基于此，本公开实施例提供了一种存储系统及电子设备，可以应用于半导体存储场景中，示例性地，可以用于基于DDR存储系统的半导体存储场景中。其中，DDR存储系统的内存模组中可以包括至少一个DDR存储器。
在本公开实施例提供的技术方案中，内存模组与内存控制器之间可以至少部分通过基板外侧的线缆进行连接的方式，来提高了内存控制器与内存模组之间的数据传输质量。
接下来将通过具体的实施例对本公开实施例提供的技术方案展开说明。
图1示出了本公开实施例提供的一种存储系统的结构示意图。如图1所示，存储系统可以包括基板11、内存控制器12和内存模组13。
对于基板11，其可以为用于支撑内存控制器12、内存模组13等结构。在一些实施例中，基板11还可以实现内存控制器12与内存模组13之间的互连。示例性地，其可以为印刷电路板(Printed Circuit Board，PCB)等电路板。需要说明的是，还可以根据实际生产需要和具体生产场景选择其他材质的基板，对此不作具体限制。
在说明了基板11之后，接下来对内存控制器12进行说明。
对于内存控制器12，其设置于基板11上。内存控制器12用于对内存模组13进行控制和数据通信等。
在一些实施例中，内存控制器12可以为具有内存模组控制功能的器件或者模块。
示例性地，内存控制器12可以为中央控制器(Central Processing Unit，CPU)、片上系统(System-on-a-chip，SoC)等。
通过采用CPU、SoC等作为内存控制器，可以实现对一个或多个内存模组13的有序控制，提高了存储系统对数据的有序处理能力。
在说明了内存控制器12之后，接下来对内存模组13进行说明。
对于内存模组13，其设置于基板11上。内存模组13用于数字数据的存储。内存模组13的数量可以是N个，其中，N为大于或等于1的正整数。
在一些实施例中，一个内存模组13可以包括至少一个内存芯片，比如一个内存模组13可以是单个内存芯片或者由多个内存芯片形成的内存模块。示例性地，内存模组13可以为动态随机存取存储器(Dynamic Random Access Memory，DRAM)。在一个示例中，内存模组可以是DDR存储器，诸如第四代双倍速率同步动态随机存储器(DDR4SDRAM)、第四代低功耗双倍速率同步动态随机存储器(LPDDR4SDRAM)、第五代双倍速率同步动态随机存储器(DDR5SDRAM)、第五代低功耗双倍速率同步动态随机存储器(LPDDR4SDRAM)等动态随机存储器中任意一种，对此不作具体限定。
在另一些实施例中，内存模组可以是诸如单列直插内存模块(Single Inline Memory Module，SIMM)、双列直插内存模块(Dual-Inline-Memory-Modules，DIMM)、内联内存模块(Rambus Inline Memory Module，RIMM)等内存模块。
通过上述实施例，本公开实施例可以提高诸如内存模块、内存芯片等不同粒度的内存模组与内存控制器之间的数据传输质量，从而提高了方案的适用性。
在介绍了内存模组13之后，接下来对内存模组13与内存控制器12之间的连接关系进行说明。
对于内存模组13与内存控制器12之间的连接关系，内存模组13与内存控制器12之间至少部分通过基板外侧的线缆进行连接(图1未示出)。其中，对于线缆(Cable)，其可以是独立元器件。需要说明的是，线缆的独立可以是指线缆之间的相互独立，和/或，可以是指基板外侧的线缆与基板之间的独立设置。
对于具体连接方式。在一些实施例中，内存模组13与内存控制器12之间部分通过线缆连接，即需要部分结构通过线缆进行数据传输，而此部分结构不能采用基板内部的走线传输，亦或者不能采用线缆和基板内部的走线共同传输，否则无法满足DDR系统的高宽带和高速率的要求。另外部分通过基板内部的走线(Trace)或者诸如硅通孔等半导体连接工艺连接。需要说明的是，除了部分通过线缆连接之外，另外部分还可以通过其他连线方式连接，对此不作具体限制。
对于N个内存模组13与内存控制器之间的连接关系。在一个实施例中，在内存模组13的数量为N的情况下，N个内存模组中的至少一个内存模组与内存控制器12之间至少部分通过线缆进行连接。
在一个具体的示例中，N个内存模组13可以包括至少一个第一内存模组和至少一个第二内存模块，其中，各第一内存模组与内存控制器12之间至少部分通过线缆连接，各第二内存模组可以与内存控制器12之间通过除线缆之外的其他连接方式连接。比如，对于N个内存模组13，相邻两个内存模组中的一个通过线缆与内存控制器12连接，该相邻两个内存模组中的另一个通过相邻内存模组与内存控制器12连接。
通过该设置方式，可以增宽走线之间的间距，降低了走线之间的串扰、损耗及反射等 数据传输质量的影响，提高内存控制器12与内存模组13之间的数据传输质量。
在另一个具体的示例中，N个内存模组13中的各内存模组与内存控制器12之间可以至少部分通过线缆连接。
通过该设置方式，由于线缆可以避免可以提高数据传输速率且能降低外部物理因素对传输信号的干扰，进而能够提高内存控制器与各内存模组之间的数据传输带宽和传输速率。
根据本公开实施例提供的存储系统，由于内存模组13与内存控制器12之间可以至少部分通过基板外侧的线缆进行连接，由于线缆可以提高数据传输速率且能降低外部物理因素对传输信号的干扰，进而能够提高内存控制器12与内存模组13之间的数据传输带宽和传输速率，从而提高了内存控制器12与内存模组13之间的数据传输质量。
以及，需要说明的是，通过至少部分通过线缆进行连接，线缆可以降低基板所造成的串扰、损耗、反射等外部物理因素的影响，从而提升DDR系统的速率和系统延时等，从而可以兼顾存储系统的带宽、速率、效率等要求，提高内存控制器12与内存模组13之间的数据传输质量。
在一些实施例中，存储系统还包括第一转接结构。第一转接结构可以设置于基板上方。
从连接关系而言，内存控制器12通过第一转接结构与内存模组13进行连接。在一个示例中，第一转接结构的数量可以为1个，相应地，1个第一转接结构可以实现内存控制器12与N个内存模组13之间的转接。在另一个示例中，第一转接结构的数量可以为多个，每个第一转接结构可以实现内存控制器12与至少一个内存模组13之间的转接。比如，第一转接结构的数量可以为N，每一第一转接结构可以实现内存控制器12与一个内存模组13之间的转接。
具体地，第一转接结构与内存控制器12之间通过线缆进行连接，或，第一转接结构与各内存模组13之间通过线缆进行连接。
通过本实施例，可以通过在第一转接结构与内存控制器12之间通过线缆进行连接，或，第一转接结构与各内存模组13之间通过线缆进行连接的方式，可以通过线缆降低外部物理因素对传输信号的干扰，进而能够提高内存控制器12与内存模组13之间的数据传输带宽和传输速率，从而提高了内存控制器12与内存模组13之间的数据传输质量。
接下来，将通过多个实施例对第一转接结构、内存控制器12、内存模组13之间的连接关系进行具体说明。
在一个实施例中，图2示出了本公开实施例提供的另一种存储系统的结构示意图。如图2所示，存储系统还包括N组对应的第一数据通道20和第一线缆30。其中，图2中的虚线箭头表示数据通道，实线表示线缆。
对于N组对应的第一数据通道20和第一线缆30，其中，第i组对应的第一数据通道20和第一线缆30用于传输内存控制器12与第i个内存模组13(图2中未示出)之间的数据，其中，N为正整数，i为小于或等于N的任意正整数。示例性地，对于第i组对应 的第一数据通道20与第一线缆30，当数据通过第一数据通道20传输到第一转接结构之后，可以在第一转接结构处确定与该第一数据通道20对应的第一线缆30，然后沿着第一线缆30继续传输至第i个内存模组13。
对于第一数据通道，图3示出了本公开实施例提供的一种示例性的数据通道的结构示意图。如图3所示，N组第一数据通道设置于基板11内部。示例性地，为了降低各第一数据通道的串扰、损耗、反射等影响因素，N组第一数据通道相较于基板表面的深度可以不同。
具体地，第i组中的第一数据通道20包括第一过孔21、第二过孔22和第一走线23。其中，第一过孔21的上表面与内存控制器12连接，第二过孔22的上表面与第一转接结构14连接，第一走线23的一端与第一过孔21的下表面连接，第一走线23的另一端与第二过孔22的下表面连接。
对于第一线缆30，第i组中的第一线缆30的一端与第一转接结构14连接，各第一线缆30的另一端与第i个内存模组连接。
通过本实施例，在半导体制造过程中在内存控制器12与第一转接结构之间采用基板内走线连接的方式，能够以半导体互连工艺实现内存控制器12与第一转接结构之间的连接，以及在第一转接结构与内存模组13之间利用线缆工艺进行连接。因此，在半导体制造过程中，可以在内存控制器12与内存模组13无法直接以线缆连接的场景下，克服该工艺困扰的同时提高内存控制器12与内存模组13之间的数据传输质量。
在一个实施例中，图4示出了本公开实施例提供的一种示例性的存储系统的结构示意图。如图4所示，内存控制器12和第一转接结构可以相邻设置。通过该设置方式，可以进一步减少走线距离，增大线缆长度，从而进一步提高内存控制器12与内存模组13之间的数据传输质量。以及，在内存控制器12与内存模组13无法直接以线缆连接的场景下，能够在保证数据传输质量的同时克服该工艺困扰。
在一些示例中，第一转接结构设置于内存控制器12的封装基板的上方。接下来将通过多个示例对该设置方式进行说明。
在一个示例中，图5示出了本公开实施例提供的一种第一转接结构与内存控制器之间的连接方式示意图。如图5所示，内存控制器12可以包括内存控制芯片(die)121、封装基板122和封装层123。可选地，第一转接结构在基底表面的正投影可以位于内存区域(Memory Area)内。
继续参见图5，第一转接结构14可以设置于内存控制器12一侧，且位于封装基板122上。具体地，内存控制芯片121可以通过M个第一连接元件41连接至封装基板122，第一转接结构14可以通过M个第二连接元件42连接至封装基板122，其中，M个第一连接元件41与M个第二连接元件42之间通过通过M条板内走线20连接。其中，M可以为等于N的整数，又或者M可以小于或者大于N，对此不作具体限定。
以及，还需要说明的是，内存控制芯片121还可以通过至少一个第三连接元件43连 接至封装基板122，以通过连接至第四连接元件44以及第四连接元件44与第三连接元件43之间的板内走线45对内存控制芯片121供电或者传递信号。
示例性地，第一连接元件41、第二连接元件42、第三连接元件43和第四连接元件44可以为焊球(Solderball)、焊料凸块(bump)或者其他连接元件，对此不做具体限制。
示例性地，封装基板122可以通过第四连接元件44连接基板11。
示例性地，封装层123的材料可以为环氧树脂模塑料(Epoxy Molding Compound，EMC)，需要说明的是，在本公开实施例中还可以其他封装方式，对此不作具体限制。通过选择EMC作为封装层123的材料，可以保证芯片的气密性、耐高温老化、抗紫外衰减能力，而且兼有体积小，成本低等特点。
通过本示例中的连接方式，可以缩短走线的长度，从而进一步提高提高内存控制器12与内存模组13之间的数据传输质量。以及，还可以在内存控制器12与内存模组13无法直接以线缆连接的场景下，克服该工艺困扰的同时提高内存控制器12与内存模组13之间的数据传输质量。
在另一个示例中，图6示出了本公开实施例提供的另一种第一转接结构与内存控制器之间的连接方式示意图。
图6与图5的不同之处在于，封装层123上形成有凹槽124。第一转接结构14可以位于该凹槽124内，并通过M个第二连接元件42连接至封装基板122。需要说明的是，图6示出的其他内容可以参见本公开上一示例结合图5的相关说明，在此不再赘述。
通过本示例中的连接方式，可以缩短走线的长度，从而进一步提高内存控制器12与内存模组13之间的数据传输质量。以及，还可以在内存控制器12与内存模组13无法直接以线缆连接的场景下，克服该工艺困扰的同时提高内存控制器12与内存模组13之间的数据传输质量。
在又一个示例中，图7示出了本公开实施例提供的又一种第一转接结构与内存控制器之间的连接方式示意图。
图7与图5的不同之处在于，第一转接结构14可以通过第五连接元件46与内存控制芯片121相连。示例性地，第五连接元件46可以为硅通孔(Through Silicon Vias，TSV)，需要说明的是，还可以其他连接元件，对此不作具体限定。
通过本示例中的连接方式，可以增加走线的长度，从而进一步提高内存控制器12与内存模组13之间的数据传输质量。以及，还可以在内存控制器12与内存模组13无法直接以线缆连接的场景下，通过第五连接元件即可克服该工艺困扰的同时提高内存控制器12与内存模组13之间的数据传输质量。
以及，还需要说明的是，通过该设置方式，第一转接结构14可以通过硅通孔与内存控制芯片121直接相连，无需另外设置封装基板内的走线，从而避免了在互连过程中因封装基板中的走线所造成的串扰、损耗、反射等问题，从而能够进一步提高信号传输质量。
在另一个实施例中，图8示出了本公开实施例提供的又一种存储系统的结构示意图。 如图8所示，存储系统还包括N组对应的第二数据通道50和第二线缆60。其中，第i组对应的第二数据通道50和第二线缆60用于传输内存控制器12与第i个内存模组13之间的数据，其中，N为正整数，i为小于或等于N的任意正整数。
具体地，继续参见图8，第i组中的第二线缆60的一端与内存控制器12连接，第i组中的第二线缆60的另一端与第一转接结构14连接。以及，第i组中的第二数据通道50可以设置于基板内部，各第二数据通道50可以包括第三过孔、第四过孔和第二走线。其中，第三过孔的上表面与第一转接结构连接，第四过孔的上表面与第i个内存模组连接。第二走线的一端与第三过孔的下表面连接，第二走线的另一端与第四过孔的下表面连接。需要说明的是，第二数据通道50的具体内容可以参见本公开实施例上述部分结合图3对第一数据通道20的相关描述，在此不再赘述。
以及，还需要说明的是，第二数据通道50还可以采用其他半导体互连工艺，比如可以通过焊球、焊料凸块、硅通孔等连接至内存模组中内存芯片的封装基板上等，对此不作具体限定。
通过本实施例，在半导体制造过程中可以通过线缆进行第一转接结构14与内存控制器12之间的连接，从而通过线缆降低了基板所造成的串扰、损耗、反射等外部物理因素的影响，从而提升DDR系统的速率和系统延时等，从而可以兼顾存储系统的带宽、速率、效率等要求，提高内存控制器12与内存模组13之间的数据传输质量。
在又一个实施例中，本公开实施例提供的存储系统还可以包括多个第二转接结构。
示例性地，图9示出了本公开实施例提供的再一种存储系统的结构示意图。如图10所示，存储系统还可以包括多个第二转接结构16。内存控制器12通过多个第二转接结构16与内存模组(图9未示出)进行数据传输；
其中，数据传输满足下述传输方式一至传输方式三中的至少一者：
传输方式一、内存控制器12与第一个第二转接结构之间通过线缆进行数据传输。
传输方式二、至少两个相邻两个第二转接结构之间通过线缆进行数据传输。示例性地，继续参见图9，内存控制器12与第一个第二转接结构之间通过诸如基板内走线等数据通道70连接，以及内存模组与最后一个第二转接结构之间通过数据通道70连接，各第二转接结构14之间可以通过线缆80连接。从而可以通过第一个第二转接结构和最后一个第二转换结构实现半导体互连工艺与线缆互连工艺之间的转换，克服了芯片等无法以线缆连接的工艺缺陷，提高了生产效率。需要说明的是，数据通道的具体内容可以参见本公开实施例上述部分结合图3的相关说明，对此不再赘述。
传输方式三、最后一个转接结构与内存模组之间通过线缆进行数据传输。
在再一个实施例中，存储系统还包括：N根第三线缆。
示例性地，图10示出了N根第三线缆90，其中，第i根第三线缆90用于实现内存控制器12与第i个内存模组13之间的连接，其中，N为正整数，i为小于或等于N的任意正整数。其中，第i根第三线缆90的一端连接内存控制器12，第i根第三线缆90的另 一端连接第i个内存模组13。
在一些实施例中，存储系统还包括内存连接结构15。内存连接结构15设置于基板11上。内存连接结构15用于连接内存模组13，以将内存模组13固定设置于基板之上。示例性地，内存连接结构15可以实现为存储器插座。
示例性地，内存连接结构15上可以设置有凹槽，以通过将内存模组插入凹槽的方式对其进行固定。可选地，内存连接结构15还可以对第一转接结构14与内存模组13之间的数据进行转接。比如，第一转接结构14可以与内存连接结构15进行连接，内存连接结构15与内存模组13进行连接。
通过设置内存连接结构15，可以对内存模组13进行固定，从而保证了内存系统的可靠性。
接下来通过两个实施例，对内存连接结构的组成子结构进行说明。
在一个实施例中，在内存模组的数量为多个的情况下，内存连接结构15包括多个内存连接子结构。其中，各内存连接子结构上设置有至少一个凹槽。其中，各凹槽用于连接一个内存模组。比如，内存连接子结构可以包括N个内存连接子结构，其中第i个内存连接子结构连接第i个内存模组。
通过本实施例，多个内存连接子结构之间可以相对独立设置，从而可以根据内存模组的数量灵活设置内存连接子结构的数量以及在基板上的位置，提高了灵活性。
在另一个实施例中，内存模组的数量为N个，内存连接结构包括一个内存连接子结构。其中，内存连接子结构上设置有N个凹槽。其中，第i个凹槽用于固定第i个内存模组，i为小于或等于N的任意正整数。
通过本实施例，可以通过一个内存连接结构固定N个凹槽，在减小内存连接结构的面积，进而减小存储系统的面积的同时，便于制造生产，降低了制造成本。
在对内存连接结构的组成子结构进行说明之后，接下来对每一内存子结构的具体组成进行说明。
在一个实施例中，每一内存连接子结构包括：第一连接部和第二连接部。示例性地，为了降低数据干扰等，第一连接部和第二连接部之间可以间隔设置。
对于第一连接部，第一连接部用于与目标数据传输模块连接。其中，目标数据传输模块为内存控制器、第一转接结构或者第二转接结构。示例性地，若内存控制器12直接与内存连接结构相连，则目标数据传输模块为内存控制器，若内存控制器12通过第一转接结构连接内存连接结构，则目标数据传输模块为第一转接结构。同理地，若内存控制器12通过第二转接结构连接内存连接结构，则目标数据传输模块为第二转接结构。
对于第二连接部，第二连接部上设置有凹槽，用于固定内存模组。
在一个示例中，图11是本公开实施例提供的一种示例性的内存连接子结构的示意图。如图11所示，第一内存连接子结构151可以包括第一连接部1511、第二连接部1512以及第三线缆1513。其中，第三线缆1513的一端连接第一连接部1511，第三线缆1513的 另一端用于连接内存模组13。
具体地，第二连接部1512上可以设置有多个第一凹槽A1，内存模组13可以插入第一凹槽A1内。以及，多个第一凹槽A1可以位于第二连接部1512的不同侧。
在另一个示例中，图12是本公开实施例提供的另一种示例性的内存连接子结构的示意图。图12示出的第二内存连接子结构152与图11示出的第一内存连接子结构151的不同之处在于，多个第一凹槽A1可以位于第二连接部1522的同一侧。
在又一个示例中，图13是本公开实施例提供的又一种示例性的内存连接子结构的示例图，图13示出的第三内存连接子结构153与图11示出的第一内存连接子结构151的不同之处在于，第三内存连接结构153上设置有一个第一凹槽A1。相应地，若内存模组13的数量为N，则内存连接结构15可以设置有N个第三内存连接结构153。
通过本实施例，可以通过第一连接部151与内存控制器侧进行连接，以及通过第二连接部152固定内存模组，从而在保证数据传输的同时，能够提高存储系统的稳定性和可靠性。
在一个示例中，第二连接部至少部分环绕第一连接部。比如，第二连接部上可以设置有凹槽，第一连接部可以至少部分位于该凹槽内。
示例性地，继续参见图11-图13，第二连接部还可以设置有第二凹槽A2，第一连接部可以部分位于第二凹槽A2内，以实现第二连接部对第一连接部151的环绕。
通过该设置方式，能够降低第一连接部与第二连接部之间的数据传输距离，从而可以进一步数据传输质量。
示例性地，继续参见图11-图13，第一连接部与各凹槽内的内存模组通过第三线缆连接。
需要说明的是，在本公开实施例中，第一连接部还可以采用其他方式连接内存模组13，对该连接方式不作具体限制。
通过该连接方式，可以通过第三线缆降低由第一连接部传输至各内存模组的过程中的信号串扰和损耗，在实现了有序连接的同时，提高了数据传输质量。
在一个具体的示例中，继续参见图11-图13，第三线缆至少部分埋设于第二连接部内部。可选地，剩余部分第三线缆可以位于第二连接部外侧。
需要说明的是，第三线缆还可以均位于第二连接部外侧，对此不作具体限定。
通过该示例，通过将第三线缆部分埋设于第二连接部内部的方式，可以在固定第三线缆的同时，减小存储系统的面积，实现各内存模组的有序连接，提高了内存系统的可靠性。
基于相同的发明构思，本公开实施例还提供了一种电子设备，该电子设备可以包括内存系统。其中，内存系统可以参见本公开实施例上述部分结合图1-图13的相关说明，在此不再赘述。
根据本公开实施例提供的电子设备，由于内存模组与内存控制器之间可以至少部分通过基板外侧的线缆进行连接，由于线缆可以提高数据传输速率且能降低外部物理因素对传 输信号的干扰，进而能够提高内存控制器与内存模组之间的数据传输带宽和传输速率，从而提高了内存控制器与内存模组之间的数据传输质量。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和示例实施方式仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。
工业实用性
本公开实施例中，由于内存模组与内存控制器之间可以至少部分通过基板外侧的线缆进行连接，以及线缆可以提高数据传输速率且能降低外部物理因素对传输信号的干扰，进而能够提高内存控制器与内存模组之间的数据传输带宽和传输速率，从而提高了内存控制器与内存模组之间的数据传输质量。

Claims (16)

  1. 一种存储系统，包括：
    基板；
    内存控制器，设置于所述基板上；
    内存模组，设置于所述基板上，所述内存模组与所述内存控制器之间至少部分通过基板外侧的线缆进行连接。
  2. 根据权利要求1所述的存储系统，其中，所述存储系统还包括第一转接结构；
    其中，所述内存控制器通过所述第一转接结构与所述内存模组进行连接，
    所述第一转接结构与所述内存控制器之间通过线缆进行连接，或，所述第一转接结构与各内存模组之间通过线缆进行连接。
  3. 根据权利要求2所述的存储系统，其中，所述内存模组的数量为N个，所述存储系统还包括：
    N组对应的第一数据通道和第一线缆，第i组对应的第一数据通道和第一线缆用于传输所述内存控制器与第i个内存模组之间的数据，其中，N为正整数，i为小于或等于N的任意正整数；
    其中，第i组中的第一数据通道设置于基板内部，包括第一过孔、第二过孔和第一走线，所述第一过孔的上表面与所述内存控制器连接，所述第二过孔的上表面与所述第一转接结构连接，所述第一走线的一端与所述第一过孔的下表面连接，所述第一走线的另一端与所述第二过孔的下表面连接；
    第i组中的第一线缆的一端与所述第一转接结构连接，各第一线缆的另一端与第i个内存模组连接。
  4. 根据权利要求2所述的存储系统，其中，所述内存模组的数量为N个，
    所述存储系统还包括：
    N组对应的第二数据通道和第二线缆，第i组对应的第二数据通道和第二线缆用于传输所述内存控制器与第i个内存模组之间的数据，其中，N为正整数，i为小于或等于N的任意正整数；
    其中，第i组中的第二线缆的一端与所述内存控制器连接，第i组中的第二线缆的另一端与所述第一转接结构连接；
    第i组中的第二数据通道设置于所述基板内部，包括第三过孔、第四过孔和第二走线，所述第三过孔的上表面与所述第一转接结构连接，所述第四过孔的上表面与第i个内存模组连接，所述第二走线的一端与所述第三过孔的下表面连接，所述第二走线的另一端与所 述第四过孔的下表面连接。
  5. 根据权利要求2-4任一项所述的存储系统，其中，所述第一转接结构设置于所述内存控制器的封装基板的上方。
  6. 根据权利要求1所述的存储系统，其中，所述存储系统还包括：
    设置于所述基板上的内存连接结构，所述内存连接结构用于连接所述内存模组，以将所述内存模组固定设置于所述基板之上。
  7. 根据权利要求6所述的存储系统，其中，所述内存模组的数量为多个，
    所述内存连接结构包括多个内存连接子结构；
    其中，各内存连接子结构上设置有至少一个凹槽，其中，各凹槽用于连接一个内存模组。
  8. 根据权利要求6所述的存储系统，其中，所述内存模组的数量为N个，其中，N为正整数，
    所述内存连接结构包括一个内存连接子结构，
    其中，所述内存连接子结构上设置有N个凹槽；
    其中，第i个凹槽用于固定第i个内存模组，i为小于或等于N的任意正整数。
  9. 根据权利要求7或8所述的存储系统，其中，每一内存连接子结构包括：
    第一连接部，用于与目标数据传输模块连接，所述目标数据传输模块为所述内存控制器、第一转接结构或者第二转接结构；
    第二连接部，所述第二连接部上设置有凹槽。
  10. 根据权利要求9所述的存储系统，其中，
    所述第二连接部至少部分环绕所述第一连接部。
  11. 根据权利要求9所述的存储系统，其中，所述第一连接部与各凹槽内的内存模组通过第三线缆连接。
  12. 根据权利要求11所述的存储系统，其中，
    所述第三线缆至少部分埋设于所述第二连接部内部。
  13. 根据权利要求1所述的存储系统，其中，
    所述内存模组为内存模块或者内存芯片。
  14. 根据权利要求1所述的存储系统，其中，
    所述内存控制器为中央控制器CPU或者片上系统SoC。
  15. 根据权利要求1所述的存储系统，其中，所述内存模组的数量为N个，N为正整数；
    所述N个内存模组中的至少一个内存模组与所述内存控制器之间至少部分通过线缆进行连接。
  16. 一种电子设备，包括如权利要求1-15任一项所述的存储系统。
PCT/CN2022/124081 2022-08-17 2022-10-09 一种存储系统及电子设备 Ceased WO2024036724A1 (zh)

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CN114647446A (zh) * 2021-03-30 2022-06-21 深圳宏芯宇电子股份有限公司 存储级存储装置、计算机模块及服务器系统

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CN101017701A (zh) * 2006-02-08 2007-08-15 睿颖科技股份有限公司 背贴式内存封装结构及其制造方法
CN104575584A (zh) * 2013-10-23 2015-04-29 钰创科技股份有限公司 具有嵌入式内存的系统级封装内存模块
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