WO2024034267A1 - Substrat de carbure de silicium, substrat épitaxial de carbure de silicium et procédé de fabrication d'un dispositif semi-conducteur en carbure de silicium - Google Patents

Substrat de carbure de silicium, substrat épitaxial de carbure de silicium et procédé de fabrication d'un dispositif semi-conducteur en carbure de silicium Download PDF

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WO2024034267A1
WO2024034267A1 PCT/JP2023/022960 JP2023022960W WO2024034267A1 WO 2024034267 A1 WO2024034267 A1 WO 2024034267A1 JP 2023022960 W JP2023022960 W JP 2023022960W WO 2024034267 A1 WO2024034267 A1 WO 2024034267A1
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silicon carbide
carbide substrate
main surface
substrate
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Japanese (ja)
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翼 本家
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住友電気工業株式会社
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to a method for manufacturing a silicon carbide substrate, a silicon carbide epitaxial substrate, and a silicon carbide semiconductor device.
  • This application claims priority based on Japanese Patent Application No. 2022-126501, which is a Japanese patent application filed on August 8, 2022. All contents described in the Japanese patent application are incorporated herein by reference.
  • Patent Document 1 describes a silicon carbide substrate whose main surface has a surface roughness of 0.1 nm or less.
  • a silicon carbide substrate according to the present disclosure includes a main surface.
  • the main surface is composed of an outer peripheral part within 3 mm from the outer peripheral edge of the main surface, and a central part surrounded by the outer peripheral part.
  • the arithmetic mean height defined as Sa is 0.1 nm or less
  • the skewness defined as Ssk is 0 or more.
  • the length of one side of the square area is 250 ⁇ m.
  • FIG. 1 is a schematic plan view showing the configuration of a silicon carbide substrate according to this embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • FIG. 3 is a schematic plan view showing the configuration of region III in FIG. 1.
  • FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 3.
  • FIG. 5 is a schematic diagram showing a process of chemical mechanical polishing on a silicon carbide substrate.
  • FIG. 6 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to this embodiment.
  • FIG. 7 is a schematic cross-sectional view showing the structure of the silicon carbide epitaxial substrate according to this embodiment.
  • FIG. 8 is a schematic cross-sectional view showing the process of forming the body region.
  • FIG. 9 is a schematic cross-sectional view showing the process of forming a source region.
  • FIG. 10 is a schematic cross-sectional view showing a step of forming a trench on the third main surface of the silicon carbide epitaxial layer.
  • FIG. 11 is a schematic cross-sectional view showing the process of forming a gate insulating film.
  • FIG. 12 is a schematic cross-sectional view showing the process of forming a gate electrode and an interlayer insulating film.
  • FIG. 13 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment.
  • FIG. 14 is a diagram showing the relationship between Sa and Ssk.
  • FIG. 15 is a diagram showing the relationship between Sa and the breakdown voltage failure rate.
  • An object of the present disclosure is to improve the yield of silicon carbide semiconductor devices. [Effects of this disclosure]
  • the yield of silicon carbide semiconductor devices can be improved.
  • Silicon carbide substrate 100 includes main surface 1.
  • the main surface 1 includes an outer peripheral part 12 within 3 mm from the outer peripheral edge 4 of the main surface 1, and a central part 10 surrounded by the outer peripheral part 12.
  • the arithmetic mean height defined as Sa is 0.1 nm or less
  • the skewness defined as Ssk is 0 or more.
  • the length of one side of the square region 5 is 250 ⁇ m.
  • the skewness defined as Ssk may be 0.4 or less.
  • the skewness defined as Ssk may be 0.3 or less.
  • the arithmetic mean height defined as Sa may be 0.06 nm or more.
  • the arithmetic mean height defined as Sa is 0.06 nm or more, and the skewness defined as Ssk is 0.3 or less. There may be.
  • the maximum diameter of the main surface may be 150 mm or more.
  • Silicon carbide epitaxial substrate 200 includes silicon carbide substrate 100 according to any one of (1) to (6) above, silicon carbide epitaxial layer 20 provided on silicon carbide substrate 100, It is equipped with
  • a method for manufacturing silicon carbide semiconductor device 400 according to the present disclosure includes the following steps. Silicon carbide epitaxial substrate 200 described in (7) above is prepared. Silicon carbide epitaxial substrate 200 is processed. [Details of embodiments of the present disclosure] Embodiments of the present disclosure will be described below based on the drawings. In the following drawings, the same or corresponding parts are given the same reference numerals, and the description thereof will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations are indicated by ⁇ >, individual planes are indicated by (), and collective planes are indicated by ⁇ , respectively. Regarding negative indexes, a "-" (bar) is supposed to be placed above the number in terms of crystallography, but in this specification, a negative sign is placed in front of the number.
  • FIG. 1 is a schematic plan view showing the configuration of silicon carbide substrate 100 according to this embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • silicon carbide substrate 100 mainly includes a first main surface 1, a second main surface 2, an outer peripheral edge 4, and an outer peripheral side surface 9. ing.
  • the second main surface 2 is on the opposite side to the first main surface 1.
  • the outer peripheral side surface 9 is continuous with each of the first main surface 1 and the second main surface 2.
  • the outer peripheral edge 4 is a boundary between the first main surface 1 and the outer peripheral side surface 9.
  • the first main surface 1 includes a central portion 10 and an outer peripheral portion 12.
  • the central portion 10 is surrounded by an outer peripheral portion 12.
  • the central portion 10 is continuous with the outer peripheral portion 12.
  • the first main surface 1 when viewed in a direction perpendicular to the first main surface 1, the first main surface 1 extends along each of a first direction 101 and a second direction 102. When viewed in a direction perpendicular to the first principal surface 1, the second direction 102 is a direction perpendicular to the first direction 101.
  • the outer peripheral edge 4 of the first main surface 1 has, for example, an orientation flat 7 and an arcuate portion 8.
  • the orientation flat 7 is linear when viewed in a direction perpendicular to the first main surface 1.
  • the orientation flat 7 extends along a first direction 101.
  • the arcuate portion 8 is continuous with the orientation flat 7.
  • the arcuate portion 8 has an arcuate shape when viewed in a direction perpendicular to the first principal surface 1 .
  • the first direction 101 is, for example, the ⁇ 11-20> direction.
  • the first direction 101 may be, for example, the [11-20] direction.
  • the first direction 101 may be a direction in which the ⁇ 11-20> direction is projected onto the first principal surface 1. From another perspective, the first direction 101 may be a direction including a ⁇ 11-20> direction component, for example.
  • the second direction 102 is, for example, the ⁇ 1-100> direction.
  • the second direction 102 may be, for example, the [1-100] direction.
  • the second direction 102 may be, for example, a direction in which the ⁇ 1-100> direction is projected onto the first principal surface 1. From another perspective, the second direction 102 may be a direction including a ⁇ 1-100> direction component, for example.
  • the first principal surface 1 may be a ⁇ 0001 ⁇ plane or a plane inclined with respect to the ⁇ 0001 ⁇ plane.
  • the inclination angle (off angle ⁇ ) with respect to the ⁇ 0001 ⁇ plane is, for example, 1° or more and 8° or less.
  • the inclination direction (off direction) of the first main surface 1 is, for example, the ⁇ 11-20> direction.
  • the off-angle ⁇ may be 2° or more and 6° or less.
  • the maximum diameter W1 of the first principal surface 1 is, for example, 100 mm (4 inches) or more.
  • the maximum diameter W1 of the first main surface 1 may be 150 mm (6 inches) or more, or 200 mm (8 inches) or more.
  • the maximum diameter W1 of the first main surface 1 is not particularly limited, but may be, for example, 400 mm (16 inches) or less.
  • the maximum diameter W1 of the first main surface 1 is the longest linear distance between two different points on the outer peripheral edge 4.
  • the outer peripheral portion 12 is a region within 3 mm from the outer peripheral edge 4 of the first main surface 1 when viewed in a direction perpendicular to the first main surface 1 . From another point of view, the width W2 of the outer peripheral portion 12 in the direction (radial direction) extending radially from the center of the first main surface 1 is 3 mm.
  • 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm/inch). 6 inches means 150 mm or 152.4 mm (6 inches x 25.4 mm/inch). 8 inches means 200 mm or 203.2 mm (8 inches x 25.4 mm/inch). 16 inches means 400 mm or 406.4 mm (16 inches x 25.4 mm/inch).
  • FIG. 3 is a schematic plan view showing the configuration of region III in FIG. 1.
  • the central portion 10 has a square area 5.
  • the length of one side of the square region 5 is 250 ⁇ m.
  • the first side of the square region 5 is parallel to the first direction 101, for example.
  • the second side of the square region 5 is parallel to the second direction 102, for example.
  • a local recess 6 may be formed in the central portion 10.
  • Local recess 6 is a hole formed by scraping off a portion of silicon carbide substrate 100 with abrasive grains. It is desirable that the number of local recesses 6 be small.
  • the number of local recesses 6 in the square region 5 is not particularly limited, but may be, for example, two or less, one or less, or zero.
  • FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 3.
  • the local recess 6 includes a side surface 62 and a bottom surface 61.
  • the side surface 62 is continuous with the first main surface 1.
  • the bottom surface 61 is continuous with the side surface 62.
  • the length W3 of the local recess 6 is approximately the same as the diameter of the abrasive grain.
  • the length W3 of the local recess 6 is not particularly limited, but is, for example, 1 ⁇ m or more and 50 ⁇ m or less.
  • the length W3 of the local recess 6 is not particularly limited, but may be, for example, 10 ⁇ m or more, or 20 ⁇ m or more.
  • the length W3 of the local recess 6 is not particularly limited, and may be, for example, 45 ⁇ m or less, or 40 ⁇ m or less.
  • the depth D of the local recess 6 is smaller than the length W3 of the local recess 6.
  • the depth D of the local recess 6 is not particularly limited, but may be one-fifth or less of the length W3 of the local recess 6, or one-tenth or less of the length W3 of the local recess 6. Good too.
  • the depth D of the local recess 6 is not particularly limited, but is, for example, 1 ⁇ m or more and 5 ⁇ m or less.
  • the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is It is 0 or more.
  • Sa and Ssk are used as indicators to quantify the surface roughness of silicon carbide substrate 100.
  • Ssk is 0, the height distribution on the surface is symmetrical in the vertical direction.
  • Ssk is greater than 0, there are many fine peaks on the surface.
  • Ssk is smaller than 0, there are many fine valleys on the surface.
  • the arithmetic mean height defined as Sa may be, for example, 0.06 nm or more, 0.07 nm or more, or 0.08 nm or more.
  • the arithmetic mean height defined as Sa may be, for example, 0.95 nm or less, or 0.9 nm or less.
  • the skewness defined as Ssk may be, for example, 0.4 or less, 0.3 or less, or 0.25 or less.
  • the skewness defined as Ssk may be, for example, 0.01 or more, 0.05 or more, or 0.1 or more.
  • the arithmetic mean height defined as Sa is 0.06 nm or more and 0.1 nm or less, and Ssk
  • the defined skewness may be 0 or more and 0.3 or less.
  • the arithmetic mean height defined as Sa may be 0.07 nm or more and 0.09 nm or less, and the skewness defined as Ssk may be 0.01 or more and 0.25 or less.
  • the arithmetic mean height defined as Sa and the skewness defined as Ssk can be measured using, for example, a white interference microscope.
  • a white interference microscope for example, BW-D507 manufactured by Nikon Corporation can be used.
  • the magnification of the objective lens is, for example, 20 times.
  • Sa is a parameter obtained by extending Ra, which is a two-dimensional arithmetic mean roughness, to three dimensions.
  • Each of Sa and Ssk is a three-dimensional surface texture parameter defined in the international standard ISO25178.
  • the measurement area for Sa and Ssk is a square area 5 with a side length of 250 ⁇ m.
  • a crystal growth process is performed. Specifically, a silicon carbide single crystal is formed using a sublimation method. Next, the silicon carbide single crystal is cut into a plurality of silicon carbide substrates 100 using a saw wire.
  • a double-sided mechanical polishing process is performed. Specifically, silicon carbide substrate 100 is placed between a first surface plate (not shown) and a second surface plate (not shown). Next, slurry is introduced between silicon carbide substrate 100 and the first surface plate and between silicon carbide substrate 100 and the second surface plate.
  • the slurry includes, for example, diamond abrasive grains and water. The diameter of the diamond abrasive grains is, for example, 1 ⁇ m or more and 3 ⁇ m or less.
  • mechanical polishing is performed on both sides of silicon carbide substrate 100.
  • FIG. 5 is a schematic diagram showing a process of chemical mechanical polishing on silicon carbide substrate 100.
  • the chemical mechanical polishing apparatus 300 includes a polishing cloth 301, a polishing head 302, a vibration acceleration sensor 303, a vacuum pump 304, and a pressurizing section 305.
  • the polishing cloth 301 is, for example, a suede polishing cloth (G804W) manufactured by Fujibo Ehime.
  • the polishing head 302 is made of, for example, ceramics or stainless steel.
  • a vibration acceleration sensor 303 is attached to the polishing head 302.
  • the pressurizing section 305 is, for example, an air cylinder.
  • the polishing liquid 310 includes, for example, abrasive grains 312 and an oxidizing agent 311.
  • the abrasive grains 312 are, for example, colloidal silica.
  • the oxidizing agent 311 is, for example, hydrogen peroxide, permanganate, nitrate, or hypochlorite.
  • the polishing liquid 310 is, for example, DSC-0902 manufactured by Fujimi Incorporated.
  • silicon carbide substrate 100 is not attached to polishing head 302 using wax. Silicon carbide substrate 100 is directly attached to polishing head 302. Specifically, silicon carbide substrate 100 is vacuum-adsorbed onto polishing head 302 by using vacuum pump 304 .
  • polishing head 302 is controlled so that fluctuations in the pressure applied to silicon carbide substrate 100 are reduced.
  • the vibration of the polishing head 302 is controlled so that the effective value of vibration acceleration in a frequency band of 1 kHz or less is 20 mG or less.
  • the regulator of the air cylinder may be controlled based on the vibration acceleration of the polishing head 302 measured using the vibration acceleration sensor 303. Thereby, it is possible to suppress local pressure fluctuations from occurring during the chemical mechanical polishing process.
  • Silicon carbide substrate 100 is arranged to face polishing cloth 301 .
  • a polishing liquid 310 containing abrasive grains 312 is supplied between silicon carbide substrate 100 and polishing cloth 301 .
  • the rotation speed of polishing head 302 is, for example, 60 rpm.
  • the rotation speed of the surface plate provided with the polishing cloth 301 is, for example, 60 rpm.
  • the average processing surface pressure F is, for example, 450 g/cm 2 .
  • the flow rate of the polishing liquid is, for example, 2 liters per minute.
  • FIG. 6 is a flowchart schematically showing a method for manufacturing silicon carbide semiconductor device 400 according to this embodiment.
  • the method for manufacturing silicon carbide semiconductor device 400 according to the present embodiment includes a step of preparing silicon carbide epitaxial substrate 200 (S1), and a step of processing silicon carbide epitaxial substrate 200 (S2). It mainly has
  • a step (S1) of preparing silicon carbide epitaxial substrate 200 is performed.
  • silicon carbide substrate 100 according to this embodiment is prepared (see FIG. 1).
  • silicon carbide epitaxial layer 20 is formed on silicon carbide substrate 100.
  • silicon carbide epitaxial layer 20 is formed on first main surface 1 of silicon carbide substrate 100 by epitaxial growth.
  • silane (SiH 4 ) and propane (C 3 H 8 ) are used as source gases, and hydrogen (H 2 ) is used as a carrier gas.
  • the temperature for epitaxial growth is, for example, about 1400° C. or more and 1700° C. or less.
  • an n-type impurity, such as nitrogen, is introduced into silicon carbide epitaxial layer 20.
  • FIG. 7 is a schematic cross-sectional view showing the structure of the silicon carbide epitaxial substrate according to this embodiment.
  • the silicon carbide epitaxial substrate according to this embodiment includes a silicon carbide substrate 100 and a silicon carbide epitaxial layer 20. Silicon carbide epitaxial layer 20 is provided on silicon carbide substrate 100.
  • Silicon carbide epitaxial layer 20 may have buffer layer 41 , drift layer 42 , and third main surface 3 .
  • Buffer layer 41 is in contact with silicon carbide substrate 100 .
  • Drift layer 42 is provided on buffer layer 41.
  • the nitrogen concentration contained in the drift layer 42 may be lower than the nitrogen concentration contained in the buffer layer 41.
  • the third main surface 3 is composed of a drift layer 42.
  • a step (S2) of processing silicon carbide epitaxial substrate 200 is performed. Specifically, the following processing is performed on silicon carbide epitaxial substrate 200. First, ion implantation is performed into silicon carbide epitaxial substrate 200.
  • FIG. 8 is a schematic cross-sectional view showing the process of forming the body region.
  • a p-type impurity such as aluminum is ion-implanted into third main surface 3 of silicon carbide epitaxial layer 20 .
  • body region 113 having p-type conductivity is formed.
  • the portion where body region 113 is not formed becomes drift layer 42 and buffer layer 41.
  • the thickness of the body region 113 is, for example, 0.9 ⁇ m.
  • Silicon carbide epitaxial layer 20 includes a buffer layer 41 , a drift layer 42 , and a body region 113 .
  • FIG. 9 is a schematic cross-sectional view showing the process of forming a source region.
  • an n-type impurity such as phosphorus is ion-implanted into body region 113, for example.
  • a source region 114 having an n-type conductivity type is formed.
  • the thickness of the source region 114 is, for example, 0.4 ⁇ m.
  • the concentration of n-type impurities contained in source region 114 is higher than the concentration of p-type impurities contained in body region 113.
  • a contact region 118 is formed by ion-implanting a p-type impurity such as aluminum into the source region 114.
  • Contact region 118 is formed to penetrate source region 114 and body region 113 and be in contact with drift layer 42 .
  • the concentration of p-type impurities contained in contact region 118 is higher than the concentration of n-type impurities contained in source region 114.
  • activation annealing is performed to activate the ion-implanted impurities.
  • the activation annealing temperature is, for example, 1500° C. or more and 1900° C. or less.
  • the activation annealing time is, for example, about 30 minutes.
  • the activation annealing atmosphere is, for example, an argon atmosphere.
  • FIG. 10 is a schematic cross-sectional view showing a step of forming a trench in third main surface 3 of silicon carbide epitaxial layer 20.
  • a mask 117 having an opening is formed on the third main surface 3 composed of the source region 114 and the contact region 118. Using mask 117, source region 114, body region 113, and a portion of drift layer 42 are removed by etching.
  • the etching method for example, inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF 6 or a mixed gas of SF 6 and O 2 as a reactive gas is used. A recess is formed in the third main surface 3 by etching.
  • thermal etching is performed in the recesses.
  • Thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas containing at least one type of halogen atom, with the mask 117 formed on the third main surface 3.
  • At least one type of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom.
  • the atmosphere includes, for example, Cl2 , BCl3 , SF6 or CF4 .
  • thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas, and at a heat treatment temperature of, for example, 700° C. or higher and 1000° C. or lower.
  • the reaction gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas.
  • the carrier gas for example, nitrogen gas, argon gas, or helium gas can be used.
  • trenches 56 are formed in the third main surface 3 by thermal etching.
  • Trench 56 is defined by side wall surface 53 and bottom wall surface 54 .
  • Sidewall surface 53 is composed of source region 114, body region 113, and drift layer 42.
  • the bottom wall surface 54 is composed of the drift layer 42.
  • the mask 117 is removed from the third main surface 3.
  • FIG. 11 is a schematic cross-sectional view showing the process of forming a gate insulating film.
  • silicon carbide epitaxial substrate 200 in which trenches 56 are formed in third main surface 3 is heated at a temperature of, for example, 1300° C. or more and 1400° C. or less in an atmosphere containing oxygen.
  • the bottom wall surface 54 is in contact with the drift layer 42
  • the side wall surface 53 is in contact with each of the drift layer 42 , the body region 113 , and the source region 114
  • the third main surface 3 is in contact with each of the source region 114 and the contact region 118 .
  • a contacting gate insulating film 115 is formed.
  • FIG. 12 is a schematic cross-sectional view showing the process of forming a gate electrode and an interlayer insulating film.
  • Gate electrode 127 is formed inside trench 56 so as to be in contact with gate insulating film 115 .
  • Gate electrode 127 is disposed inside trench 56 and formed on gate insulating film 115 so as to face each of side wall surface 53 and bottom wall surface 54 of trench 56 .
  • the gate electrode 127 is formed, for example, by LPCVD (Low Pressure Chemical Vapor Deposition) method.
  • Interlayer insulating film 126 is formed. Interlayer insulating film 126 is formed to cover gate electrode 127 and to be in contact with gate insulating film 115 .
  • the interlayer insulating film 126 is formed, for example, by chemical vapor deposition.
  • the interlayer insulating film 126 is made of, for example, a material containing silicon dioxide.
  • interlayer insulating film 126 and a portion of gate insulating film 115 are etched so that openings are formed over source region 114 and contact region 118. As a result, contact region 118 and source region 114 are exposed from gate insulating film 115.
  • Source electrode 116 is formed so as to be in contact with each of source region 114 and contact region 118.
  • Source electrode 116 is formed by, for example, a sputtering method.
  • the source electrode 116 is made of a material containing, for example, Ti (titanium), Al (aluminum), and Si (silicon).
  • alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. As a result, a source electrode 116 that is in ohmic contact with the source region 114 is formed. Source electrode 116 may be in ohmic contact with contact region 118.
  • Source wiring 119 is formed.
  • Source wiring 119 is electrically connected to source electrode 116.
  • Source wiring 119 is formed to cover source electrode 116 and interlayer insulating film 126 .
  • a step of forming a drain electrode is performed. First, silicon carbide substrate 100 is polished on second main surface 2 . This reduces the thickness of silicon carbide substrate 100. Next, drain electrode 123 is formed. Drain electrode 123 is formed so as to be in contact with second main surface 2 . Through the above steps, silicon carbide semiconductor device 400 according to this embodiment is manufactured.
  • FIG. 13 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment.
  • Silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • Silicon carbide semiconductor device 400 mainly includes silicon carbide epitaxial substrate 200, gate electrode 127, gate insulating film 115, source electrode 116, drain electrode 123, source wiring 119, and interlayer insulating film 126. ing.
  • Silicon carbide epitaxial substrate 200 has buffer layer 41 , drift layer 42 , body region 113 , source region 114 , and contact region 118 .
  • Silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor).
  • Silicon carbide substrate 100 is required to have an extremely smooth main surface.
  • Arithmetic mean height (Sa) is generally used as an index of surface roughness. However, even when Sa on main surface 1 of silicon carbide substrate 100 is low, the yield of silicon carbide semiconductor device 400 manufactured using silicon carbide substrate 100 may be poor.
  • the minute local recesses 6 that do not affect Sa of the main surface 1 have a strong correlation with the skewness defined as Ssk.
  • the arithmetic mean height defined as Sa is set to 0.1 nm or less, and the skewness defined as Ssk is set to 0 or more, thereby forming a silicon carbide semiconductor. It is possible to improve the yield of the device 400.
  • Silicon carbide is a material with extremely high hardness. Therefore, when polishing silicon carbide substrate 100, a high load is applied to silicon carbide substrate 100. When silicon carbide substrate 100 is polished using a polishing liquid containing abrasive grains, local pressure fluctuations occur due to micro vibrations during pressurization, etc., and local recesses 6 are formed on the surface of silicon carbide substrate 100. Sometimes. In the method for manufacturing silicon carbide substrate 100 according to the present disclosure, chemical mechanical polishing was performed on silicon carbide substrate 100 while suppressing local pressure fluctuations.
  • silicon carbide substrate 100 was directly attached to the polishing head without using wax.
  • silicon carbide substrate 100 is attached to a polishing head, which is a support, using wax.
  • silicon carbide substrate 100 is attached to the polishing head via wax by pressing silicon carbide substrate 100.
  • silicon carbide substrate 100 is pressed, a concave portion may be formed in silicon carbide substrate 100 due to foreign matter biting into silicon carbide substrate 100 .
  • silicon carbide substrate 100 is directly attached to the polishing head without using wax, so it is possible to suppress the formation of local recesses 6 in silicon carbide substrate 100. .
  • polishing head 302 is controlled so that fluctuations in the pressure applied to silicon carbide substrate 100 are reduced. Specifically, the vibration of the polishing head 302 is controlled so that the effective value of vibration acceleration in a frequency band of 1 kHz or less is 20 mG or less. Thereby, it is possible to suppress local pressure fluctuations from occurring during the chemical mechanical polishing process. As a result, formation of local recesses 6 in silicon carbide substrate 100 can be suppressed.
  • the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or more. Thereby, it is possible to improve the yield of silicon carbide semiconductor device 400.
  • the skewness defined as Ssk may be 0.4 or less. Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
  • the skewness defined as Ssk may be 0.3 or less. Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
  • the arithmetic mean height defined as Sa may be 0.06 nm or more. Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
  • the arithmetic mean height defined as Sa may be 0.06 nm or more, and the skewness defined as Ssk may be 0.3 or less. . Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
  • the maximum diameter of the main surface may be 150 mm or more. Therefore, even when using large diameter silicon carbide substrate 100, it is possible to improve the yield of silicon carbide semiconductor device 400.
  • Silicon carbide substrates 100 according to samples 1-1 to 1-5 were manufactured using a chemical mechanical polishing process of group G1.
  • Silicon carbide substrates 100 according to samples 2-1 to 2-4 were manufactured using a chemical mechanical polishing process of group G2.
  • Silicon carbide substrates 100 according to samples 3-1 to 3-12 were manufactured using a chemical mechanical polishing process of group G3.
  • the abrasive grains 312 were colloidal silica.
  • the polishing liquid 310 was DSC-0902 manufactured by Fujimi Incorporated.
  • the rotation speed of the polishing head 302 was 60 rpm.
  • the rotation speed of the surface plate provided with the polishing cloth 301 was 60 rpm.
  • the average working surface pressure F was 450 g/cm 2 .
  • the flow rate of the polishing liquid was 2 liters per minute.
  • silicon carbide substrate 100 was attached to polishing head 302 using wax.
  • silicon carbide substrate 100 was directly attached to polishing head 302 without using wax.
  • vibration control of the polishing head 302 was not performed.
  • vibration control of the polishing head 302 was performed in the chemical mechanical polishing process of group G3. Specifically, the vibration of the polishing head 302 was controlled so that the effective value of vibration acceleration in a frequency band of 1 kHz or less was 20 mG or less.
  • Sa and Ssk were measured in central portions 10 of silicon carbide substrates 100 according to samples 1-1 to 3-12. Sa and Ssk were measured using a white interference microscope (Nikon BW-D507). The measurement area for Sa and Ssk was a square area 5 with a side length of 250 ⁇ m. MOSFETs were fabricated using silicon carbide substrates 100 according to samples 1-1 to 3-12, and the breakdown voltage failure rate of the MOSFETs was determined.
  • Table 1 shows Sa and Ssk in the center portion 10 of the silicon carbide substrates 100 according to samples 1-1 to 1-5, and the breakdown voltage failure rate of MOSFETs manufactured using the silicon carbide substrates 100.
  • Sa was 0.117 nm or more and 0.133 nm or less.
  • Ssk was -0.092 or more and 0.297 or less.
  • the breakdown voltage failure rate was 29% or more and 35% or less.
  • Table 2 shows Sa and Ssk in the center portion 10 of the silicon carbide substrates 100 according to samples 2-1 to 2-4, and the breakdown voltage failure rate of MOSFETs manufactured using the silicon carbide substrates 100.
  • Sa was 0.078 nm or more and 0.095 nm or less.
  • Ssk was -0.427 or more and -0.015 or less.
  • the breakdown voltage failure rate was 27% or more and 31% or less.
  • Table 3 shows Sa and Ssk in the center portion 10 of the silicon carbide substrates 100 according to samples 3-1 to 3-12, and the breakdown voltage failure rate of MOSFETs manufactured using the silicon carbide substrates 100.
  • Sa was 0.079 nm or more and 0.095 nm or less.
  • Ssk was 0.001 or more and 0.237 or less.
  • the breakdown voltage failure rate was 19% or more and 22% or less.
  • FIG. 14 is a diagram showing the relationship between Sa and Ssk. As shown in FIG. 14, in silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of group G2, Sa is low and Ssk is less than 0. On the other hand, in silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of group G3, Sa is low and Ssk is 0 or more.
  • FIG. 15 is a diagram showing the relationship between Sa and the breakdown voltage failure rate.
  • the breakdown voltage failure rate of silicon carbide semiconductor device 400 manufactured using silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of group G2 was relatively high.
  • the breakdown voltage defect rate of silicon carbide semiconductor device 400 manufactured using silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of Group G3 was significantly lower. From the above results, it was confirmed that by setting Sa to 0.1 nm or less and Ssk to 0 or more, the breakdown voltage failure rate of silicon carbide semiconductor device 400 can be significantly reduced.
  • the present disclosure includes the embodiments described below.
  • (Additional note 1) having a main surface;
  • the main surface is composed of an outer peripheral part within 3 mm from the outer peripheral edge of the main surface, and a central part surrounded by the outer peripheral part, In any square area in the central part, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or more,
  • a silicon carbide substrate in which the length of one side of the square region is 250 ⁇ m.
  • (Additional note 2) The silicon carbide substrate according to Supplementary Note 1, wherein the skewness defined as Ssk is 0.4 or less.
  • First main surface (main surface), 2. Second main surface, 3. Third main surface, 4. Outer periphery, 5. Square area, 6. Local recess, 7. Orientation flat, 8. Arc-shaped part, 9. Outer peripheral side surface, 10. Center part. , 12 outer periphery, 20 silicon carbide epitaxial layer, 41 buffer layer, 42 drift layer, 53 side wall surface, 54 bottom wall surface, 56 trench, 61 bottom surface, 62 side surface, 100 silicon carbide substrate, 101 first direction, 102 second direction , 113 body region, 114 source region, 115 gate insulating film, 116 source electrode, 117 mask, 118 contact region, 119 source wiring, 123 drain electrode, 126 interlayer insulating film, 127 gate electrode, 200 silicon carbide epitaxial substrate, 300 chemistry Mechanical polishing device, 301 Polishing cloth, 302 Polishing head, 303 Vibration acceleration sensor, 304 Vacuum pump, 305 Pressure part, 310 Polishing liquid, 311 Oxidizing agent, 312 Abrasive grain, 400 Silicon carbide

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Abstract

Le présent substrat de carbure de silicium présente une surface principale. La surface principale est composée d'une partie périphérique externe dans une plage de 3 mm à partir de la périphérie externe de la surface principale, et d'une partie centrale entourée par la partie périphérique externe. Dans une zone carrée arbitraire dans la partie centrale, la hauteur moyenne arithmétique définie comme Sa est inférieure ou égale à 0,1 nm, et l'asymétrie définie en tant que Ssk est d'au moins 0. La longueur d'un côté de la zone carrée est de 250 µm.
PCT/JP2023/022960 2022-08-08 2023-06-21 Substrat de carbure de silicium, substrat épitaxial de carbure de silicium et procédé de fabrication d'un dispositif semi-conducteur en carbure de silicium WO2024034267A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013012767A (ja) * 2012-08-31 2013-01-17 Fujitsu Ltd 化合物半導体装置、およびその製造方法
JP2016048790A (ja) * 2015-11-05 2016-04-07 住友化学株式会社 トランジスタ用窒化物半導体エピタキシャルウエハ及び窒化物半導体電界効果トランジスタ
JP2021138597A (ja) * 2020-02-28 2021-09-16 エスケイシー・カンパニー・リミテッドSkc Co., Ltd. ウエハ、エピタキシャルウエハ及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013012767A (ja) * 2012-08-31 2013-01-17 Fujitsu Ltd 化合物半導体装置、およびその製造方法
JP2016048790A (ja) * 2015-11-05 2016-04-07 住友化学株式会社 トランジスタ用窒化物半導体エピタキシャルウエハ及び窒化物半導体電界効果トランジスタ
JP2021138597A (ja) * 2020-02-28 2021-09-16 エスケイシー・カンパニー・リミテッドSkc Co., Ltd. ウエハ、エピタキシャルウエハ及びその製造方法

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