WO2024034267A1 - Silicon carbide substrate, silicon carbide epitaxial substrate, and method for manufacturing silicon carbide semiconductor device - Google Patents

Silicon carbide substrate, silicon carbide epitaxial substrate, and method for manufacturing silicon carbide semiconductor device Download PDF

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WO2024034267A1
WO2024034267A1 PCT/JP2023/022960 JP2023022960W WO2024034267A1 WO 2024034267 A1 WO2024034267 A1 WO 2024034267A1 JP 2023022960 W JP2023022960 W JP 2023022960W WO 2024034267 A1 WO2024034267 A1 WO 2024034267A1
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silicon carbide
carbide substrate
main surface
substrate
less
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French (fr)
Japanese (ja)
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翼 本家
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住友電気工業株式会社
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to a method for manufacturing a silicon carbide substrate, a silicon carbide epitaxial substrate, and a silicon carbide semiconductor device.
  • This application claims priority based on Japanese Patent Application No. 2022-126501, which is a Japanese patent application filed on August 8, 2022. All contents described in the Japanese patent application are incorporated herein by reference.
  • Patent Document 1 describes a silicon carbide substrate whose main surface has a surface roughness of 0.1 nm or less.
  • a silicon carbide substrate according to the present disclosure includes a main surface.
  • the main surface is composed of an outer peripheral part within 3 mm from the outer peripheral edge of the main surface, and a central part surrounded by the outer peripheral part.
  • the arithmetic mean height defined as Sa is 0.1 nm or less
  • the skewness defined as Ssk is 0 or more.
  • the length of one side of the square area is 250 ⁇ m.
  • FIG. 1 is a schematic plan view showing the configuration of a silicon carbide substrate according to this embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • FIG. 3 is a schematic plan view showing the configuration of region III in FIG. 1.
  • FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 3.
  • FIG. 5 is a schematic diagram showing a process of chemical mechanical polishing on a silicon carbide substrate.
  • FIG. 6 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to this embodiment.
  • FIG. 7 is a schematic cross-sectional view showing the structure of the silicon carbide epitaxial substrate according to this embodiment.
  • FIG. 8 is a schematic cross-sectional view showing the process of forming the body region.
  • FIG. 9 is a schematic cross-sectional view showing the process of forming a source region.
  • FIG. 10 is a schematic cross-sectional view showing a step of forming a trench on the third main surface of the silicon carbide epitaxial layer.
  • FIG. 11 is a schematic cross-sectional view showing the process of forming a gate insulating film.
  • FIG. 12 is a schematic cross-sectional view showing the process of forming a gate electrode and an interlayer insulating film.
  • FIG. 13 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment.
  • FIG. 14 is a diagram showing the relationship between Sa and Ssk.
  • FIG. 15 is a diagram showing the relationship between Sa and the breakdown voltage failure rate.
  • An object of the present disclosure is to improve the yield of silicon carbide semiconductor devices. [Effects of this disclosure]
  • the yield of silicon carbide semiconductor devices can be improved.
  • Silicon carbide substrate 100 includes main surface 1.
  • the main surface 1 includes an outer peripheral part 12 within 3 mm from the outer peripheral edge 4 of the main surface 1, and a central part 10 surrounded by the outer peripheral part 12.
  • the arithmetic mean height defined as Sa is 0.1 nm or less
  • the skewness defined as Ssk is 0 or more.
  • the length of one side of the square region 5 is 250 ⁇ m.
  • the skewness defined as Ssk may be 0.4 or less.
  • the skewness defined as Ssk may be 0.3 or less.
  • the arithmetic mean height defined as Sa may be 0.06 nm or more.
  • the arithmetic mean height defined as Sa is 0.06 nm or more, and the skewness defined as Ssk is 0.3 or less. There may be.
  • the maximum diameter of the main surface may be 150 mm or more.
  • Silicon carbide epitaxial substrate 200 includes silicon carbide substrate 100 according to any one of (1) to (6) above, silicon carbide epitaxial layer 20 provided on silicon carbide substrate 100, It is equipped with
  • a method for manufacturing silicon carbide semiconductor device 400 according to the present disclosure includes the following steps. Silicon carbide epitaxial substrate 200 described in (7) above is prepared. Silicon carbide epitaxial substrate 200 is processed. [Details of embodiments of the present disclosure] Embodiments of the present disclosure will be described below based on the drawings. In the following drawings, the same or corresponding parts are given the same reference numerals, and the description thereof will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations are indicated by ⁇ >, individual planes are indicated by (), and collective planes are indicated by ⁇ , respectively. Regarding negative indexes, a "-" (bar) is supposed to be placed above the number in terms of crystallography, but in this specification, a negative sign is placed in front of the number.
  • FIG. 1 is a schematic plan view showing the configuration of silicon carbide substrate 100 according to this embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • silicon carbide substrate 100 mainly includes a first main surface 1, a second main surface 2, an outer peripheral edge 4, and an outer peripheral side surface 9. ing.
  • the second main surface 2 is on the opposite side to the first main surface 1.
  • the outer peripheral side surface 9 is continuous with each of the first main surface 1 and the second main surface 2.
  • the outer peripheral edge 4 is a boundary between the first main surface 1 and the outer peripheral side surface 9.
  • the first main surface 1 includes a central portion 10 and an outer peripheral portion 12.
  • the central portion 10 is surrounded by an outer peripheral portion 12.
  • the central portion 10 is continuous with the outer peripheral portion 12.
  • the first main surface 1 when viewed in a direction perpendicular to the first main surface 1, the first main surface 1 extends along each of a first direction 101 and a second direction 102. When viewed in a direction perpendicular to the first principal surface 1, the second direction 102 is a direction perpendicular to the first direction 101.
  • the outer peripheral edge 4 of the first main surface 1 has, for example, an orientation flat 7 and an arcuate portion 8.
  • the orientation flat 7 is linear when viewed in a direction perpendicular to the first main surface 1.
  • the orientation flat 7 extends along a first direction 101.
  • the arcuate portion 8 is continuous with the orientation flat 7.
  • the arcuate portion 8 has an arcuate shape when viewed in a direction perpendicular to the first principal surface 1 .
  • the first direction 101 is, for example, the ⁇ 11-20> direction.
  • the first direction 101 may be, for example, the [11-20] direction.
  • the first direction 101 may be a direction in which the ⁇ 11-20> direction is projected onto the first principal surface 1. From another perspective, the first direction 101 may be a direction including a ⁇ 11-20> direction component, for example.
  • the second direction 102 is, for example, the ⁇ 1-100> direction.
  • the second direction 102 may be, for example, the [1-100] direction.
  • the second direction 102 may be, for example, a direction in which the ⁇ 1-100> direction is projected onto the first principal surface 1. From another perspective, the second direction 102 may be a direction including a ⁇ 1-100> direction component, for example.
  • the first principal surface 1 may be a ⁇ 0001 ⁇ plane or a plane inclined with respect to the ⁇ 0001 ⁇ plane.
  • the inclination angle (off angle ⁇ ) with respect to the ⁇ 0001 ⁇ plane is, for example, 1° or more and 8° or less.
  • the inclination direction (off direction) of the first main surface 1 is, for example, the ⁇ 11-20> direction.
  • the off-angle ⁇ may be 2° or more and 6° or less.
  • the maximum diameter W1 of the first principal surface 1 is, for example, 100 mm (4 inches) or more.
  • the maximum diameter W1 of the first main surface 1 may be 150 mm (6 inches) or more, or 200 mm (8 inches) or more.
  • the maximum diameter W1 of the first main surface 1 is not particularly limited, but may be, for example, 400 mm (16 inches) or less.
  • the maximum diameter W1 of the first main surface 1 is the longest linear distance between two different points on the outer peripheral edge 4.
  • the outer peripheral portion 12 is a region within 3 mm from the outer peripheral edge 4 of the first main surface 1 when viewed in a direction perpendicular to the first main surface 1 . From another point of view, the width W2 of the outer peripheral portion 12 in the direction (radial direction) extending radially from the center of the first main surface 1 is 3 mm.
  • 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm/inch). 6 inches means 150 mm or 152.4 mm (6 inches x 25.4 mm/inch). 8 inches means 200 mm or 203.2 mm (8 inches x 25.4 mm/inch). 16 inches means 400 mm or 406.4 mm (16 inches x 25.4 mm/inch).
  • FIG. 3 is a schematic plan view showing the configuration of region III in FIG. 1.
  • the central portion 10 has a square area 5.
  • the length of one side of the square region 5 is 250 ⁇ m.
  • the first side of the square region 5 is parallel to the first direction 101, for example.
  • the second side of the square region 5 is parallel to the second direction 102, for example.
  • a local recess 6 may be formed in the central portion 10.
  • Local recess 6 is a hole formed by scraping off a portion of silicon carbide substrate 100 with abrasive grains. It is desirable that the number of local recesses 6 be small.
  • the number of local recesses 6 in the square region 5 is not particularly limited, but may be, for example, two or less, one or less, or zero.
  • FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 3.
  • the local recess 6 includes a side surface 62 and a bottom surface 61.
  • the side surface 62 is continuous with the first main surface 1.
  • the bottom surface 61 is continuous with the side surface 62.
  • the length W3 of the local recess 6 is approximately the same as the diameter of the abrasive grain.
  • the length W3 of the local recess 6 is not particularly limited, but is, for example, 1 ⁇ m or more and 50 ⁇ m or less.
  • the length W3 of the local recess 6 is not particularly limited, but may be, for example, 10 ⁇ m or more, or 20 ⁇ m or more.
  • the length W3 of the local recess 6 is not particularly limited, and may be, for example, 45 ⁇ m or less, or 40 ⁇ m or less.
  • the depth D of the local recess 6 is smaller than the length W3 of the local recess 6.
  • the depth D of the local recess 6 is not particularly limited, but may be one-fifth or less of the length W3 of the local recess 6, or one-tenth or less of the length W3 of the local recess 6. Good too.
  • the depth D of the local recess 6 is not particularly limited, but is, for example, 1 ⁇ m or more and 5 ⁇ m or less.
  • the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is It is 0 or more.
  • Sa and Ssk are used as indicators to quantify the surface roughness of silicon carbide substrate 100.
  • Ssk is 0, the height distribution on the surface is symmetrical in the vertical direction.
  • Ssk is greater than 0, there are many fine peaks on the surface.
  • Ssk is smaller than 0, there are many fine valleys on the surface.
  • the arithmetic mean height defined as Sa may be, for example, 0.06 nm or more, 0.07 nm or more, or 0.08 nm or more.
  • the arithmetic mean height defined as Sa may be, for example, 0.95 nm or less, or 0.9 nm or less.
  • the skewness defined as Ssk may be, for example, 0.4 or less, 0.3 or less, or 0.25 or less.
  • the skewness defined as Ssk may be, for example, 0.01 or more, 0.05 or more, or 0.1 or more.
  • the arithmetic mean height defined as Sa is 0.06 nm or more and 0.1 nm or less, and Ssk
  • the defined skewness may be 0 or more and 0.3 or less.
  • the arithmetic mean height defined as Sa may be 0.07 nm or more and 0.09 nm or less, and the skewness defined as Ssk may be 0.01 or more and 0.25 or less.
  • the arithmetic mean height defined as Sa and the skewness defined as Ssk can be measured using, for example, a white interference microscope.
  • a white interference microscope for example, BW-D507 manufactured by Nikon Corporation can be used.
  • the magnification of the objective lens is, for example, 20 times.
  • Sa is a parameter obtained by extending Ra, which is a two-dimensional arithmetic mean roughness, to three dimensions.
  • Each of Sa and Ssk is a three-dimensional surface texture parameter defined in the international standard ISO25178.
  • the measurement area for Sa and Ssk is a square area 5 with a side length of 250 ⁇ m.
  • a crystal growth process is performed. Specifically, a silicon carbide single crystal is formed using a sublimation method. Next, the silicon carbide single crystal is cut into a plurality of silicon carbide substrates 100 using a saw wire.
  • a double-sided mechanical polishing process is performed. Specifically, silicon carbide substrate 100 is placed between a first surface plate (not shown) and a second surface plate (not shown). Next, slurry is introduced between silicon carbide substrate 100 and the first surface plate and between silicon carbide substrate 100 and the second surface plate.
  • the slurry includes, for example, diamond abrasive grains and water. The diameter of the diamond abrasive grains is, for example, 1 ⁇ m or more and 3 ⁇ m or less.
  • mechanical polishing is performed on both sides of silicon carbide substrate 100.
  • FIG. 5 is a schematic diagram showing a process of chemical mechanical polishing on silicon carbide substrate 100.
  • the chemical mechanical polishing apparatus 300 includes a polishing cloth 301, a polishing head 302, a vibration acceleration sensor 303, a vacuum pump 304, and a pressurizing section 305.
  • the polishing cloth 301 is, for example, a suede polishing cloth (G804W) manufactured by Fujibo Ehime.
  • the polishing head 302 is made of, for example, ceramics or stainless steel.
  • a vibration acceleration sensor 303 is attached to the polishing head 302.
  • the pressurizing section 305 is, for example, an air cylinder.
  • the polishing liquid 310 includes, for example, abrasive grains 312 and an oxidizing agent 311.
  • the abrasive grains 312 are, for example, colloidal silica.
  • the oxidizing agent 311 is, for example, hydrogen peroxide, permanganate, nitrate, or hypochlorite.
  • the polishing liquid 310 is, for example, DSC-0902 manufactured by Fujimi Incorporated.
  • silicon carbide substrate 100 is not attached to polishing head 302 using wax. Silicon carbide substrate 100 is directly attached to polishing head 302. Specifically, silicon carbide substrate 100 is vacuum-adsorbed onto polishing head 302 by using vacuum pump 304 .
  • polishing head 302 is controlled so that fluctuations in the pressure applied to silicon carbide substrate 100 are reduced.
  • the vibration of the polishing head 302 is controlled so that the effective value of vibration acceleration in a frequency band of 1 kHz or less is 20 mG or less.
  • the regulator of the air cylinder may be controlled based on the vibration acceleration of the polishing head 302 measured using the vibration acceleration sensor 303. Thereby, it is possible to suppress local pressure fluctuations from occurring during the chemical mechanical polishing process.
  • Silicon carbide substrate 100 is arranged to face polishing cloth 301 .
  • a polishing liquid 310 containing abrasive grains 312 is supplied between silicon carbide substrate 100 and polishing cloth 301 .
  • the rotation speed of polishing head 302 is, for example, 60 rpm.
  • the rotation speed of the surface plate provided with the polishing cloth 301 is, for example, 60 rpm.
  • the average processing surface pressure F is, for example, 450 g/cm 2 .
  • the flow rate of the polishing liquid is, for example, 2 liters per minute.
  • FIG. 6 is a flowchart schematically showing a method for manufacturing silicon carbide semiconductor device 400 according to this embodiment.
  • the method for manufacturing silicon carbide semiconductor device 400 according to the present embodiment includes a step of preparing silicon carbide epitaxial substrate 200 (S1), and a step of processing silicon carbide epitaxial substrate 200 (S2). It mainly has
  • a step (S1) of preparing silicon carbide epitaxial substrate 200 is performed.
  • silicon carbide substrate 100 according to this embodiment is prepared (see FIG. 1).
  • silicon carbide epitaxial layer 20 is formed on silicon carbide substrate 100.
  • silicon carbide epitaxial layer 20 is formed on first main surface 1 of silicon carbide substrate 100 by epitaxial growth.
  • silane (SiH 4 ) and propane (C 3 H 8 ) are used as source gases, and hydrogen (H 2 ) is used as a carrier gas.
  • the temperature for epitaxial growth is, for example, about 1400° C. or more and 1700° C. or less.
  • an n-type impurity, such as nitrogen, is introduced into silicon carbide epitaxial layer 20.
  • FIG. 7 is a schematic cross-sectional view showing the structure of the silicon carbide epitaxial substrate according to this embodiment.
  • the silicon carbide epitaxial substrate according to this embodiment includes a silicon carbide substrate 100 and a silicon carbide epitaxial layer 20. Silicon carbide epitaxial layer 20 is provided on silicon carbide substrate 100.
  • Silicon carbide epitaxial layer 20 may have buffer layer 41 , drift layer 42 , and third main surface 3 .
  • Buffer layer 41 is in contact with silicon carbide substrate 100 .
  • Drift layer 42 is provided on buffer layer 41.
  • the nitrogen concentration contained in the drift layer 42 may be lower than the nitrogen concentration contained in the buffer layer 41.
  • the third main surface 3 is composed of a drift layer 42.
  • a step (S2) of processing silicon carbide epitaxial substrate 200 is performed. Specifically, the following processing is performed on silicon carbide epitaxial substrate 200. First, ion implantation is performed into silicon carbide epitaxial substrate 200.
  • FIG. 8 is a schematic cross-sectional view showing the process of forming the body region.
  • a p-type impurity such as aluminum is ion-implanted into third main surface 3 of silicon carbide epitaxial layer 20 .
  • body region 113 having p-type conductivity is formed.
  • the portion where body region 113 is not formed becomes drift layer 42 and buffer layer 41.
  • the thickness of the body region 113 is, for example, 0.9 ⁇ m.
  • Silicon carbide epitaxial layer 20 includes a buffer layer 41 , a drift layer 42 , and a body region 113 .
  • FIG. 9 is a schematic cross-sectional view showing the process of forming a source region.
  • an n-type impurity such as phosphorus is ion-implanted into body region 113, for example.
  • a source region 114 having an n-type conductivity type is formed.
  • the thickness of the source region 114 is, for example, 0.4 ⁇ m.
  • the concentration of n-type impurities contained in source region 114 is higher than the concentration of p-type impurities contained in body region 113.
  • a contact region 118 is formed by ion-implanting a p-type impurity such as aluminum into the source region 114.
  • Contact region 118 is formed to penetrate source region 114 and body region 113 and be in contact with drift layer 42 .
  • the concentration of p-type impurities contained in contact region 118 is higher than the concentration of n-type impurities contained in source region 114.
  • activation annealing is performed to activate the ion-implanted impurities.
  • the activation annealing temperature is, for example, 1500° C. or more and 1900° C. or less.
  • the activation annealing time is, for example, about 30 minutes.
  • the activation annealing atmosphere is, for example, an argon atmosphere.
  • FIG. 10 is a schematic cross-sectional view showing a step of forming a trench in third main surface 3 of silicon carbide epitaxial layer 20.
  • a mask 117 having an opening is formed on the third main surface 3 composed of the source region 114 and the contact region 118. Using mask 117, source region 114, body region 113, and a portion of drift layer 42 are removed by etching.
  • the etching method for example, inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF 6 or a mixed gas of SF 6 and O 2 as a reactive gas is used. A recess is formed in the third main surface 3 by etching.
  • thermal etching is performed in the recesses.
  • Thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas containing at least one type of halogen atom, with the mask 117 formed on the third main surface 3.
  • At least one type of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom.
  • the atmosphere includes, for example, Cl2 , BCl3 , SF6 or CF4 .
  • thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas, and at a heat treatment temperature of, for example, 700° C. or higher and 1000° C. or lower.
  • the reaction gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas.
  • the carrier gas for example, nitrogen gas, argon gas, or helium gas can be used.
  • trenches 56 are formed in the third main surface 3 by thermal etching.
  • Trench 56 is defined by side wall surface 53 and bottom wall surface 54 .
  • Sidewall surface 53 is composed of source region 114, body region 113, and drift layer 42.
  • the bottom wall surface 54 is composed of the drift layer 42.
  • the mask 117 is removed from the third main surface 3.
  • FIG. 11 is a schematic cross-sectional view showing the process of forming a gate insulating film.
  • silicon carbide epitaxial substrate 200 in which trenches 56 are formed in third main surface 3 is heated at a temperature of, for example, 1300° C. or more and 1400° C. or less in an atmosphere containing oxygen.
  • the bottom wall surface 54 is in contact with the drift layer 42
  • the side wall surface 53 is in contact with each of the drift layer 42 , the body region 113 , and the source region 114
  • the third main surface 3 is in contact with each of the source region 114 and the contact region 118 .
  • a contacting gate insulating film 115 is formed.
  • FIG. 12 is a schematic cross-sectional view showing the process of forming a gate electrode and an interlayer insulating film.
  • Gate electrode 127 is formed inside trench 56 so as to be in contact with gate insulating film 115 .
  • Gate electrode 127 is disposed inside trench 56 and formed on gate insulating film 115 so as to face each of side wall surface 53 and bottom wall surface 54 of trench 56 .
  • the gate electrode 127 is formed, for example, by LPCVD (Low Pressure Chemical Vapor Deposition) method.
  • Interlayer insulating film 126 is formed. Interlayer insulating film 126 is formed to cover gate electrode 127 and to be in contact with gate insulating film 115 .
  • the interlayer insulating film 126 is formed, for example, by chemical vapor deposition.
  • the interlayer insulating film 126 is made of, for example, a material containing silicon dioxide.
  • interlayer insulating film 126 and a portion of gate insulating film 115 are etched so that openings are formed over source region 114 and contact region 118. As a result, contact region 118 and source region 114 are exposed from gate insulating film 115.
  • Source electrode 116 is formed so as to be in contact with each of source region 114 and contact region 118.
  • Source electrode 116 is formed by, for example, a sputtering method.
  • the source electrode 116 is made of a material containing, for example, Ti (titanium), Al (aluminum), and Si (silicon).
  • alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. As a result, a source electrode 116 that is in ohmic contact with the source region 114 is formed. Source electrode 116 may be in ohmic contact with contact region 118.
  • Source wiring 119 is formed.
  • Source wiring 119 is electrically connected to source electrode 116.
  • Source wiring 119 is formed to cover source electrode 116 and interlayer insulating film 126 .
  • a step of forming a drain electrode is performed. First, silicon carbide substrate 100 is polished on second main surface 2 . This reduces the thickness of silicon carbide substrate 100. Next, drain electrode 123 is formed. Drain electrode 123 is formed so as to be in contact with second main surface 2 . Through the above steps, silicon carbide semiconductor device 400 according to this embodiment is manufactured.
  • FIG. 13 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment.
  • Silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • Silicon carbide semiconductor device 400 mainly includes silicon carbide epitaxial substrate 200, gate electrode 127, gate insulating film 115, source electrode 116, drain electrode 123, source wiring 119, and interlayer insulating film 126. ing.
  • Silicon carbide epitaxial substrate 200 has buffer layer 41 , drift layer 42 , body region 113 , source region 114 , and contact region 118 .
  • Silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor).
  • Silicon carbide substrate 100 is required to have an extremely smooth main surface.
  • Arithmetic mean height (Sa) is generally used as an index of surface roughness. However, even when Sa on main surface 1 of silicon carbide substrate 100 is low, the yield of silicon carbide semiconductor device 400 manufactured using silicon carbide substrate 100 may be poor.
  • the minute local recesses 6 that do not affect Sa of the main surface 1 have a strong correlation with the skewness defined as Ssk.
  • the arithmetic mean height defined as Sa is set to 0.1 nm or less, and the skewness defined as Ssk is set to 0 or more, thereby forming a silicon carbide semiconductor. It is possible to improve the yield of the device 400.
  • Silicon carbide is a material with extremely high hardness. Therefore, when polishing silicon carbide substrate 100, a high load is applied to silicon carbide substrate 100. When silicon carbide substrate 100 is polished using a polishing liquid containing abrasive grains, local pressure fluctuations occur due to micro vibrations during pressurization, etc., and local recesses 6 are formed on the surface of silicon carbide substrate 100. Sometimes. In the method for manufacturing silicon carbide substrate 100 according to the present disclosure, chemical mechanical polishing was performed on silicon carbide substrate 100 while suppressing local pressure fluctuations.
  • silicon carbide substrate 100 was directly attached to the polishing head without using wax.
  • silicon carbide substrate 100 is attached to a polishing head, which is a support, using wax.
  • silicon carbide substrate 100 is attached to the polishing head via wax by pressing silicon carbide substrate 100.
  • silicon carbide substrate 100 is pressed, a concave portion may be formed in silicon carbide substrate 100 due to foreign matter biting into silicon carbide substrate 100 .
  • silicon carbide substrate 100 is directly attached to the polishing head without using wax, so it is possible to suppress the formation of local recesses 6 in silicon carbide substrate 100. .
  • polishing head 302 is controlled so that fluctuations in the pressure applied to silicon carbide substrate 100 are reduced. Specifically, the vibration of the polishing head 302 is controlled so that the effective value of vibration acceleration in a frequency band of 1 kHz or less is 20 mG or less. Thereby, it is possible to suppress local pressure fluctuations from occurring during the chemical mechanical polishing process. As a result, formation of local recesses 6 in silicon carbide substrate 100 can be suppressed.
  • the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or more. Thereby, it is possible to improve the yield of silicon carbide semiconductor device 400.
  • the skewness defined as Ssk may be 0.4 or less. Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
  • the skewness defined as Ssk may be 0.3 or less. Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
  • the arithmetic mean height defined as Sa may be 0.06 nm or more. Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
  • the arithmetic mean height defined as Sa may be 0.06 nm or more, and the skewness defined as Ssk may be 0.3 or less. . Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
  • the maximum diameter of the main surface may be 150 mm or more. Therefore, even when using large diameter silicon carbide substrate 100, it is possible to improve the yield of silicon carbide semiconductor device 400.
  • Silicon carbide substrates 100 according to samples 1-1 to 1-5 were manufactured using a chemical mechanical polishing process of group G1.
  • Silicon carbide substrates 100 according to samples 2-1 to 2-4 were manufactured using a chemical mechanical polishing process of group G2.
  • Silicon carbide substrates 100 according to samples 3-1 to 3-12 were manufactured using a chemical mechanical polishing process of group G3.
  • the abrasive grains 312 were colloidal silica.
  • the polishing liquid 310 was DSC-0902 manufactured by Fujimi Incorporated.
  • the rotation speed of the polishing head 302 was 60 rpm.
  • the rotation speed of the surface plate provided with the polishing cloth 301 was 60 rpm.
  • the average working surface pressure F was 450 g/cm 2 .
  • the flow rate of the polishing liquid was 2 liters per minute.
  • silicon carbide substrate 100 was attached to polishing head 302 using wax.
  • silicon carbide substrate 100 was directly attached to polishing head 302 without using wax.
  • vibration control of the polishing head 302 was not performed.
  • vibration control of the polishing head 302 was performed in the chemical mechanical polishing process of group G3. Specifically, the vibration of the polishing head 302 was controlled so that the effective value of vibration acceleration in a frequency band of 1 kHz or less was 20 mG or less.
  • Sa and Ssk were measured in central portions 10 of silicon carbide substrates 100 according to samples 1-1 to 3-12. Sa and Ssk were measured using a white interference microscope (Nikon BW-D507). The measurement area for Sa and Ssk was a square area 5 with a side length of 250 ⁇ m. MOSFETs were fabricated using silicon carbide substrates 100 according to samples 1-1 to 3-12, and the breakdown voltage failure rate of the MOSFETs was determined.
  • Table 1 shows Sa and Ssk in the center portion 10 of the silicon carbide substrates 100 according to samples 1-1 to 1-5, and the breakdown voltage failure rate of MOSFETs manufactured using the silicon carbide substrates 100.
  • Sa was 0.117 nm or more and 0.133 nm or less.
  • Ssk was -0.092 or more and 0.297 or less.
  • the breakdown voltage failure rate was 29% or more and 35% or less.
  • Table 2 shows Sa and Ssk in the center portion 10 of the silicon carbide substrates 100 according to samples 2-1 to 2-4, and the breakdown voltage failure rate of MOSFETs manufactured using the silicon carbide substrates 100.
  • Sa was 0.078 nm or more and 0.095 nm or less.
  • Ssk was -0.427 or more and -0.015 or less.
  • the breakdown voltage failure rate was 27% or more and 31% or less.
  • Table 3 shows Sa and Ssk in the center portion 10 of the silicon carbide substrates 100 according to samples 3-1 to 3-12, and the breakdown voltage failure rate of MOSFETs manufactured using the silicon carbide substrates 100.
  • Sa was 0.079 nm or more and 0.095 nm or less.
  • Ssk was 0.001 or more and 0.237 or less.
  • the breakdown voltage failure rate was 19% or more and 22% or less.
  • FIG. 14 is a diagram showing the relationship between Sa and Ssk. As shown in FIG. 14, in silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of group G2, Sa is low and Ssk is less than 0. On the other hand, in silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of group G3, Sa is low and Ssk is 0 or more.
  • FIG. 15 is a diagram showing the relationship between Sa and the breakdown voltage failure rate.
  • the breakdown voltage failure rate of silicon carbide semiconductor device 400 manufactured using silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of group G2 was relatively high.
  • the breakdown voltage defect rate of silicon carbide semiconductor device 400 manufactured using silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of Group G3 was significantly lower. From the above results, it was confirmed that by setting Sa to 0.1 nm or less and Ssk to 0 or more, the breakdown voltage failure rate of silicon carbide semiconductor device 400 can be significantly reduced.
  • the present disclosure includes the embodiments described below.
  • (Additional note 1) having a main surface;
  • the main surface is composed of an outer peripheral part within 3 mm from the outer peripheral edge of the main surface, and a central part surrounded by the outer peripheral part, In any square area in the central part, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or more,
  • a silicon carbide substrate in which the length of one side of the square region is 250 ⁇ m.
  • (Additional note 2) The silicon carbide substrate according to Supplementary Note 1, wherein the skewness defined as Ssk is 0.4 or less.
  • First main surface (main surface), 2. Second main surface, 3. Third main surface, 4. Outer periphery, 5. Square area, 6. Local recess, 7. Orientation flat, 8. Arc-shaped part, 9. Outer peripheral side surface, 10. Center part. , 12 outer periphery, 20 silicon carbide epitaxial layer, 41 buffer layer, 42 drift layer, 53 side wall surface, 54 bottom wall surface, 56 trench, 61 bottom surface, 62 side surface, 100 silicon carbide substrate, 101 first direction, 102 second direction , 113 body region, 114 source region, 115 gate insulating film, 116 source electrode, 117 mask, 118 contact region, 119 source wiring, 123 drain electrode, 126 interlayer insulating film, 127 gate electrode, 200 silicon carbide epitaxial substrate, 300 chemistry Mechanical polishing device, 301 Polishing cloth, 302 Polishing head, 303 Vibration acceleration sensor, 304 Vacuum pump, 305 Pressure part, 310 Polishing liquid, 311 Oxidizing agent, 312 Abrasive grain, 400 Silicon carbide

Abstract

This silicon carbide substrate has a main surface. The main surface is composed of an outer peripheral portion within 3 mm from the outer periphery of the main surface, and a central portion surrounded by the outer peripheral portion. In an arbitrary square area in the central portion, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is at least 0. The length of one side of the square area is 250 μm.

Description

炭化珪素基板、炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法Method for manufacturing silicon carbide substrate, silicon carbide epitaxial substrate, and silicon carbide semiconductor device
　本開示は、炭化珪素基板、炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法に関する。本出願は、２０２２年８月８日に出願した日本特許出願である特願２０２２－１２６５０１号に基づく優先権を主張する。当該日本特許出願に記載された全ての記載内容は、参照によって本明細書に援用される。 The present disclosure relates to a method for manufacturing a silicon carbide substrate, a silicon carbide epitaxial substrate, and a silicon carbide semiconductor device. This application claims priority based on Japanese Patent Application No. 2022-126501, which is a Japanese patent application filed on August 8, 2022. All contents described in the Japanese patent application are incorporated herein by reference.
　国際公開２０１６／０６３６３２号（特許文献１）には、主面の表面粗さが０．１ｎｍ以下である炭化珪素基板が記載されている。 International Publication No. 2016/063632 (Patent Document 1) describes a silicon carbide substrate whose main surface has a surface roughness of 0.1 nm or less.
国際公開２０１６／０６３６３２号International Publication 2016/063632
　本開示に係る炭化珪素基板は、主面を備えている。主面は、主面の外周縁から３ｍｍ以内の外周部と、外周部に囲まれた中央部とにより構成されている。中央部における任意の正方領域において、Ｓａとして規定される算術平均高さは０．１ｎｍ以下であり、かつ、Ｓｓｋとして規定されるスキューネスは０以上である。正方領域の一辺の長さは、２５０μｍである。 A silicon carbide substrate according to the present disclosure includes a main surface. The main surface is composed of an outer peripheral part within 3 mm from the outer peripheral edge of the main surface, and a central part surrounded by the outer peripheral part. In an arbitrary square area in the center, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or more. The length of one side of the square area is 250 μm.
図１は、本実施形態に係る炭化珪素基板の構成を示す平面模式図である。FIG. 1 is a schematic plan view showing the configuration of a silicon carbide substrate according to this embodiment. 図２は、図１のＩＩ－ＩＩ線に沿った断面模式図である。FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 図３は、図１の領域ＩＩＩの構成を示す平面模式図である。FIG. 3 is a schematic plan view showing the configuration of region III in FIG. 1. 図４は、図３のＩＶ－ＩＶ線に沿った断面模式図である。FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 3. 図５は、炭化珪素基板に対して化学機械研磨を行う工程を示す模式図である。FIG. 5 is a schematic diagram showing a process of chemical mechanical polishing on a silicon carbide substrate. 図６は、本実施形態に係る炭化珪素半導体装置の製造方法を概略的に示すフローチャートである。FIG. 6 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to this embodiment. 図７は、本実施形態に係る炭化珪素エピタキシャル基板の構成を示す断面模式図である。FIG. 7 is a schematic cross-sectional view showing the structure of the silicon carbide epitaxial substrate according to this embodiment. 図８は、ボディ領域を形成する工程を示す断面模式図である。FIG. 8 is a schematic cross-sectional view showing the process of forming the body region. 図９は、ソース領域を形成する工程を示す断面模式図である。FIG. 9 is a schematic cross-sectional view showing the process of forming a source region. 図１０は、炭化珪素エピタキシャル層の第３主面にトレンチを形成する工程を示す断面模式図である。FIG. 10 is a schematic cross-sectional view showing a step of forming a trench on the third main surface of the silicon carbide epitaxial layer. 図１１は、ゲート絶縁膜を形成する工程を示す断面模式図である。FIG. 11 is a schematic cross-sectional view showing the process of forming a gate insulating film. 図１２は、ゲート電極および層間絶縁膜を形成する工程を示す断面模式図である。FIG. 12 is a schematic cross-sectional view showing the process of forming a gate electrode and an interlayer insulating film. 図１３は、本実施形態に係る炭化珪素半導体装置の構成を示す断面模式図である。FIG. 13 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment. 図１４は、ＳａとＳｓｋとの関係を示す図である。FIG. 14 is a diagram showing the relationship between Sa and Ssk. 図１５は、Ｓａと耐圧不良率との関係を示す図である。FIG. 15 is a diagram showing the relationship between Sa and the breakdown voltage failure rate.
[本開示が解決しようとする課題] [Problems to be solved by this disclosure]
　本開示の目的は、炭化珪素半導体装置の歩留まりを向上することである。
[本開示の効果] An object of the present disclosure is to improve the yield of silicon carbide semiconductor devices.
[Effects of this disclosure]
　本開示によれば、炭化珪素半導体装置の歩留まりを向上することができる。 According to the present disclosure, the yield of silicon carbide semiconductor devices can be improved.
［本開示の実施形態の説明］
　最初に本開示の実施形態を列挙して説明する。 [Description of embodiments of the present disclosure]
First, embodiments of the present disclosure will be listed and described.
　（１）本開示に係る炭化珪素基板１００は、主面１を備えている。主面１は、主面１の外周縁４から３ｍｍ以内の外周部１２と、外周部１２に囲まれた中央部１０とにより構成されている。中央部１０における任意の正方領域５において、Ｓａとして規定される算術平均高さは０．１ｎｍ以下であり、かつ、Ｓｓｋとして規定されるスキューネスは０以上である。正方領域５の一辺の長さは、２５０μｍである。 (1) Silicon carbide substrate 100 according to the present disclosure includes main surface 1. The main surface 1 includes an outer peripheral part 12 within 3 mm from the outer peripheral edge 4 of the main surface 1, and a central part 10 surrounded by the outer peripheral part 12. In any square region 5 in the central portion 10, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or more. The length of one side of the square region 5 is 250 μm.
　（２）上記（１）に係る炭化珪素基板１００によれば、Ｓｓｋとして規定されるスキューネスは、０．４以下であってもよい。 (2) According to the silicon carbide substrate 100 according to (1) above, the skewness defined as Ssk may be 0.4 or less.
　（３）上記（１）に係る炭化珪素基板１００によれば、Ｓｓｋとして規定されるスキューネスは、０．３以下であってもよい。 (3) According to the silicon carbide substrate 100 according to (1) above, the skewness defined as Ssk may be 0.3 or less.
　（４）上記（１）から（３）のいずれかに係る炭化珪素基板１００によれば、Ｓａとして規定される算術平均高さは、０．０６ｎｍ以上であってもよい。 (4) According to the silicon carbide substrate 100 according to any one of (1) to (3) above, the arithmetic mean height defined as Sa may be 0.06 nm or more.
　（５）上記（１）に係る炭化珪素基板１００によれば、Ｓａとして規定される算術平均高さは、０．０６ｎｍ以上であり、かつ、Ｓｓｋとして規定されるスキューネスは、０．３以下であってもよい。 (5) According to the silicon carbide substrate 100 according to (1) above, the arithmetic mean height defined as Sa is 0.06 nm or more, and the skewness defined as Ssk is 0.3 or less. There may be.
　（６）上記（１）から（５）のいずれかに係る炭化珪素基板１００によれば、主面の最大径は、１５０ｍｍ以上であってもよい。 (6) According to the silicon carbide substrate 100 according to any one of (1) to (5) above, the maximum diameter of the main surface may be 150 mm or more.
　（７）本開示に係る炭化珪素エピタキシャル基板２００は、上記（１）から（６）のいずれかに記載の炭化珪素基板１００と、炭化珪素基板１００上に設けられた炭化珪素エピタキシャル層２０と、を備えている。 (7) Silicon carbide epitaxial substrate 200 according to the present disclosure includes silicon carbide substrate 100 according to any one of (1) to (6) above, silicon carbide epitaxial layer 20 provided on silicon carbide substrate 100, It is equipped with
　（８）本開示に係る炭化珪素半導体装置４００の製造方法は以下の工程を備えている。上記（７）に記載の炭化珪素エピタキシャル基板２００が準備される。炭化珪素エピタキシャル基板２００が加工される。
［本開示の実施形態の詳細］
　以下、図面に基づいて本開示の実施形態を説明する。なお、以下の図面において同一または相当する部分には同一の参照番号を付し、その説明は繰返さない。本明細書中の結晶学的記載においては、個別方位を［］、集合方位を＜＞、個別面を（）、集合面を｛｝でそれぞれ示している。また、負の指数については、結晶学上、”－”（バー）を数字の上に付けることになっているが、本明細書中では、数字の前に負の符号を付けている。 (8) A method for manufacturing silicon carbide semiconductor device 400 according to the present disclosure includes the following steps. Silicon carbide epitaxial substrate 200 described in (7) above is prepared. Silicon carbide epitaxial substrate 200 is processed.
[Details of embodiments of the present disclosure]
Embodiments of the present disclosure will be described below based on the drawings. In the following drawings, the same or corresponding parts are given the same reference numerals, and the description thereof will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations are indicated by <>, individual planes are indicated by (), and collective planes are indicated by {}, respectively. Regarding negative indexes, a "-" (bar) is supposed to be placed above the number in terms of crystallography, but in this specification, a negative sign is placed in front of the number.
　＜炭化珪素基板＞
　まず、本実施形態に係る炭化珪素基板１００の構成について説明する。図１は、本実施形態に係る炭化珪素基板１００の構成を示す平面模式図である。図２は、図１のＩＩ－ＩＩ線に沿った断面模式図である。 <Silicon carbide substrate>
First, the configuration of silicon carbide substrate 100 according to this embodiment will be described. FIG. 1 is a schematic plan view showing the configuration of silicon carbide substrate 100 according to this embodiment. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
　図１および図２に示されるように、本実施形態に係る炭化珪素基板１００は、第１主面１と、第２主面２と、外周縁４と、外周側面９とを主に有している。第２主面２は、第１主面１と反対側にある。外周側面９は、第１主面１および第２主面２の各々に連なっている。外周縁４は、第１主面１と外周側面９との境界である。第１主面１は、中央部１０と、外周部１２とにより構成されている。中央部１０は、外周部１２に囲まれている。中央部１０は、外周部１２に連なっている。 As shown in FIGS. 1 and 2, silicon carbide substrate 100 according to the present embodiment mainly includes a first main surface 1, a second main surface 2, an outer peripheral edge 4, and an outer peripheral side surface 9. ing. The second main surface 2 is on the opposite side to the first main surface 1. The outer peripheral side surface 9 is continuous with each of the first main surface 1 and the second main surface 2. The outer peripheral edge 4 is a boundary between the first main surface 1 and the outer peripheral side surface 9. The first main surface 1 includes a central portion 10 and an outer peripheral portion 12. The central portion 10 is surrounded by an outer peripheral portion 12. The central portion 10 is continuous with the outer peripheral portion 12.
　図１に示されるように、第１主面１に対して垂直な方向に見て、第１主面１は、第１方向１０１および第２方向１０２の各々に沿って拡がっている。第１主面１に対して垂直な方向に見て、第２方向１０２は、第１方向１０１に対して垂直な方向である。第１主面１の外周縁４は、たとえばオリエンテーションフラット７と、円弧状部８とを有している。 As shown in FIG. 1, when viewed in a direction perpendicular to the first main surface 1, the first main surface 1 extends along each of a first direction 101 and a second direction 102. When viewed in a direction perpendicular to the first principal surface 1, the second direction 102 is a direction perpendicular to the first direction 101. The outer peripheral edge 4 of the first main surface 1 has, for example, an orientation flat 7 and an arcuate portion 8.
　図１に示されるように、オリエンテーションフラット７は、第１主面１に対して垂直な方向に見て、直線状である。オリエンテーションフラット７は、第１方向１０１に沿って延在している。円弧状部８は、オリエンテーションフラット７に連なっている。円弧状部８は、第１主面１に対して垂直な方向に見て、円弧状である。 As shown in FIG. 1, the orientation flat 7 is linear when viewed in a direction perpendicular to the first main surface 1. The orientation flat 7 extends along a first direction 101. The arcuate portion 8 is continuous with the orientation flat 7. The arcuate portion 8 has an arcuate shape when viewed in a direction perpendicular to the first principal surface 1 .
　第１方向１０１は、たとえば＜１１－２０＞方向である。第１方向１０１は、たとえば[１１－２０]方向であってもよい。第１方向１０１は、＜１１－２０＞方向を第１主面１に射影した方向であってもよい。別の観点から言えば、第１方向１０１は、たとえば＜１１－２０＞方向成分を含む方向であってもよい。 The first direction 101 is, for example, the <11-20> direction. The first direction 101 may be, for example, the [11-20] direction. The first direction 101 may be a direction in which the <11-20> direction is projected onto the first principal surface 1. From another perspective, the first direction 101 may be a direction including a <11-20> direction component, for example.
　第２方向１０２は、たとえば＜１－１００＞方向である。第２方向１０２は、たとえば［１－１００]方向であってもよい。第２方向１０２は、たとえば＜１－１００＞方向を第１主面１に射影した方向であってもよい。別の観点から言えば、第２方向１０２は、たとえば＜１－１００＞方向成分を含む方向であってもよい。 The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be, for example, a direction in which the <1-100> direction is projected onto the first principal surface 1. From another perspective, the second direction 102 may be a direction including a <1-100> direction component, for example.
　第１主面１は、｛０００１｝面であってもよいし、｛０００１｝面に対して傾斜した面であってもよい。第１主面１は、｛０００１｝面に対して傾斜している場合、｛０００１｝面に対する傾斜角（オフ角θ）は、たとえば１°以上８°以下である。第１主面１が｛０００１｝面に対して傾斜している場合、第１主面１の傾斜方向（オフ方向）は、たとえば＜１１－２０＞方向である。オフ角θは、２°以上６°以下であってもよい。 The first principal surface 1 may be a {0001} plane or a plane inclined with respect to the {0001} plane. When the first principal surface 1 is inclined with respect to the {0001} plane, the inclination angle (off angle θ) with respect to the {0001} plane is, for example, 1° or more and 8° or less. When the first main surface 1 is inclined with respect to the {0001} plane, the inclination direction (off direction) of the first main surface 1 is, for example, the <11-20> direction. The off-angle θ may be 2° or more and 6° or less.
　第１主面１の最大径Ｗ１は、たとえば１００ｍｍ（４インチ）以上である。第１主面１の最大径Ｗ１は、１５０ｍｍ（６インチ）以上でもあってもよいし、２００ｍｍ（８インチ）以上でもよい。第１主面１の最大径Ｗ１は、特に限定されないが、たとえば４００ｍｍ（１６インチ）以下であってもよい。 The maximum diameter W1 of the first principal surface 1 is, for example, 100 mm (4 inches) or more. The maximum diameter W1 of the first main surface 1 may be 150 mm (6 inches) or more, or 200 mm (8 inches) or more. The maximum diameter W1 of the first main surface 1 is not particularly limited, but may be, for example, 400 mm (16 inches) or less.
　第１主面１に対して垂直な方向に見て、第１主面１の最大径Ｗ１は、外周縁４上の異なる２点間の最長直線距離である。第１主面１に対して垂直な方向に見て、外周部１２は、第１主面１の外周縁４から３ｍｍ以内の領域である。別の観点から言えば、第１主面１の中心から放射状に伸びる方向（径方向）における外周部１２の幅Ｗ２は、３ｍｍである。 When viewed in the direction perpendicular to the first main surface 1, the maximum diameter W1 of the first main surface 1 is the longest linear distance between two different points on the outer peripheral edge 4. The outer peripheral portion 12 is a region within 3 mm from the outer peripheral edge 4 of the first main surface 1 when viewed in a direction perpendicular to the first main surface 1 . From another point of view, the width W2 of the outer peripheral portion 12 in the direction (radial direction) extending radially from the center of the first main surface 1 is 3 mm.
　なお本明細書において、４インチは、１００ｍｍ又は１０１．６ｍｍ（４インチ×２５．４ｍｍ／インチ）のことである。６インチは、１５０ｍｍ又は１５２．４ｍｍ（６インチ×２５．４ｍｍ／インチ）のことである。８インチは、２００ｍｍ又は２０３．２ｍｍ（８インチ×２５．４ｍｍ／インチ）のことである。１６インチは、４００ｍｍ又は４０６．４ｍｍ（１６インチ×２５．４ｍｍ／インチ）のことである。 Note that in this specification, 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm/inch). 6 inches means 150 mm or 152.4 mm (6 inches x 25.4 mm/inch). 8 inches means 200 mm or 203.2 mm (8 inches x 25.4 mm/inch). 16 inches means 400 mm or 406.4 mm (16 inches x 25.4 mm/inch).
　図３は、図１の領域ＩＩＩの構成を示す平面模式図である。図３に示されるように、中央部１０は、正方領域５を有している。正方領域５の一辺の長さは、２５０μｍである。第１主面１に対して垂直な方向に見て、正方領域５の第１辺は、たとえば第１方向１０１と平行である。第１主面１に対して垂直な方向に見て、正方領域５の第２辺は、たとえば第２方向１０２と平行である。 FIG. 3 is a schematic plan view showing the configuration of region III in FIG. 1. As shown in FIG. 3, the central portion 10 has a square area 5. As shown in FIG. The length of one side of the square region 5 is 250 μm. When viewed in a direction perpendicular to the first principal surface 1, the first side of the square region 5 is parallel to the first direction 101, for example. When viewed in a direction perpendicular to the first principal surface 1, the second side of the square region 5 is parallel to the second direction 102, for example.
　図３に示されるように、中央部１０には、局所凹部６が形成されていてもよい。局所凹部６は、砥粒によって炭化珪素基板１００の一部が削り取らることによって形成された穴である。局所凹部６の数は、少ないことが望ましい。正方領域５における局所凹部６の数は、特に限定されないが、たとえば２個以下であってもよいし、１個以下であってもよいし、０個であってもよい。 As shown in FIG. 3, a local recess 6 may be formed in the central portion 10. Local recess 6 is a hole formed by scraping off a portion of silicon carbide substrate 100 with abrasive grains. It is desirable that the number of local recesses 6 be small. The number of local recesses 6 in the square region 5 is not particularly limited, but may be, for example, two or less, one or less, or zero.
　図４は、図３のＩＶ－ＩＶ線に沿った断面模式図である。図４に示されるように、局所凹部６は、側面６２と、底面６１とにより構成されている。側面６２は、第１主面１に連なっている。底面６１は、側面６２に連なっている。第１方向１０１において、局所凹部６の長さＷ３は、砥粒の直径と同程度である。 FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 3. As shown in FIG. 4, the local recess 6 includes a side surface 62 and a bottom surface 61. The side surface 62 is continuous with the first main surface 1. The bottom surface 61 is continuous with the side surface 62. In the first direction 101, the length W3 of the local recess 6 is approximately the same as the diameter of the abrasive grain.
　局所凹部６の長さＷ３は、特に限定されないが、たとえば１μｍ以上５０μｍ以下である。局所凹部６の長さＷ３は、特に限定されないが、たとえば１０μｍ以上であってもよいし、２０μｍ以上であってもよい。局所凹部６の長さＷ３は、特に限定されないが、たとえば４５μｍ以下であってもよいし、４０μｍ以下であってもよい。 The length W3 of the local recess 6 is not particularly limited, but is, for example, 1 μm or more and 50 μm or less. The length W3 of the local recess 6 is not particularly limited, but may be, for example, 10 μm or more, or 20 μm or more. The length W3 of the local recess 6 is not particularly limited, and may be, for example, 45 μm or less, or 40 μm or less.
　局所凹部６の深さＤは、局所凹部６の長さＷ３よりも小さい。局所凹部６の深さＤは、特に限定されないが、局所凹部６の長さＷ３の５分の１以下であってもよいし、局所凹部６の長さＷ３の１０分の１以下であってもよい。局所凹部６の深さＤは、特に限定されないが、たとえば１μｍ以上５μｍ以下である。 The depth D of the local recess 6 is smaller than the length W3 of the local recess 6. The depth D of the local recess 6 is not particularly limited, but may be one-fifth or less of the length W3 of the local recess 6, or one-tenth or less of the length W3 of the local recess 6. Good too. The depth D of the local recess 6 is not particularly limited, but is, for example, 1 μm or more and 5 μm or less.
　本実施形態に係る炭化珪素基板１００によれば、中央部１０における任意の正方領域５において、Ｓａとして規定される算術平均高さは０．１ｎｍ以下であり、かつ、Ｓｓｋとして規定されるスキューネスは０以上である。ＳａおよびＳｓｋは、炭化珪素基板１００の表面粗さを定量化する指標として用いられる。Ｓｓｋが０の場合には、表面における高さの分布が上下方向に対称である。Ｓｓｋが０よりも大きい場合には、表面において細かい山が多い状態である。Ｓｓｋが０よりも小さい場合には、表面において細かい谷が多い状態である。 According to silicon carbide substrate 100 according to the present embodiment, in any square region 5 in central portion 10, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is It is 0 or more. Sa and Ssk are used as indicators to quantify the surface roughness of silicon carbide substrate 100. When Ssk is 0, the height distribution on the surface is symmetrical in the vertical direction. When Ssk is greater than 0, there are many fine peaks on the surface. When Ssk is smaller than 0, there are many fine valleys on the surface.
　Ｓａとして規定される算術平均高さは、たとえば０．０６ｎｍ以上であってもよいし、０．０７ｎｍ以上であってもよいし、０．０８ｎｍ以上であってもよい。Ｓａとして規定される算術平均高さは、たとえば０．９５ｎｍ以下であってもよいし、０．９ｎｍ以下であってもよい。 The arithmetic mean height defined as Sa may be, for example, 0.06 nm or more, 0.07 nm or more, or 0.08 nm or more. The arithmetic mean height defined as Sa may be, for example, 0.95 nm or less, or 0.9 nm or less.
　Ｓｓｋとして規定されるスキューネスは、たとえば０．４以下であってもよいし、０．３以下であってもよいし、０．２５以下であってもよい。Ｓｓｋとして規定されるスキューネスは、たとえば０．０１以上であってもよいし、０．０５以上であってもよいし、０．１以上であってもよい。 The skewness defined as Ssk may be, for example, 0.4 or less, 0.3 or less, or 0.25 or less. The skewness defined as Ssk may be, for example, 0.01 or more, 0.05 or more, or 0.1 or more.
　本実施形態に係る炭化珪素基板１００によれば、中央部１０における任意の正方領域５において、Ｓａとして規定される算術平均高さは、０．０６ｎｍ以上０．１ｎｍ以下であり、かつ、Ｓｓｋとして規定されるスキューネスは、０以上０．３以下であってもよい。Ｓａとして規定される算術平均高さは、０．０７ｎｍ以上０．０９ｎｍ以下であり、かつ、Ｓｓｋとして規定されるスキューネスは、０．０１以上０．２５以下であってもよい。 According to silicon carbide substrate 100 according to the present embodiment, in any square region 5 in central portion 10, the arithmetic mean height defined as Sa is 0.06 nm or more and 0.1 nm or less, and Ssk The defined skewness may be 0 or more and 0.3 or less. The arithmetic mean height defined as Sa may be 0.07 nm or more and 0.09 nm or less, and the skewness defined as Ssk may be 0.01 or more and 0.25 or less.
　次に、Ｓａとして規定される算術平均高さおよびＳｓｋとして規定されるスキューネスの測定方法について説明する。 Next, a method for measuring the arithmetic mean height defined as Sa and the skewness defined as Ssk will be described.
　Ｓａとして規定される算術平均高さおよびＳｓｋとして規定されるスキューネスは、たとえば白色干渉顕微鏡により測定することができる。白色干渉顕微鏡として、たとえばニコン社製のＢＷ－Ｄ５０７を用いることができる。対物レンズの倍率は、たとえば２０倍である。Ｓａは、二次元の算術平均粗さであるＲａを三次元に拡張したパラメータである。ＳａおよびＳｓｋの各々は、国際規格ＩＳＯ２５１７８に規定されている三次元表面性状パラメータである。ＳａおよびＳｓｋの測定領域は、一辺の長さが２５０μｍの正方領域５である。 The arithmetic mean height defined as Sa and the skewness defined as Ssk can be measured using, for example, a white interference microscope. As a white interference microscope, for example, BW-D507 manufactured by Nikon Corporation can be used. The magnification of the objective lens is, for example, 20 times. Sa is a parameter obtained by extending Ra, which is a two-dimensional arithmetic mean roughness, to three dimensions. Each of Sa and Ssk is a three-dimensional surface texture parameter defined in the international standard ISO25178. The measurement area for Sa and Ssk is a square area 5 with a side length of 250 μm.
　＜炭化珪素基板の製造方法＞
　次に、本実施形態に係る炭化珪素基板１００の製造方法について説明する。 <Method for manufacturing silicon carbide substrate>
Next, a method for manufacturing silicon carbide substrate 100 according to this embodiment will be described.
　まず、結晶成長工程が実施される。具体的には、昇華法を用いて炭化珪素単結晶が形成される。次に、炭化珪素単結晶がソーワイヤーによって複数の炭化珪素基板１００に切り出される。 First, a crystal growth process is performed. Specifically, a silicon carbide single crystal is formed using a sublimation method. Next, the silicon carbide single crystal is cut into a plurality of silicon carbide substrates 100 using a saw wire.
　次に、両面機械研磨工程が実施される。具体的には、炭化珪素基板１００が第１定盤（図示せず）と第２定盤（図示せず）との間に配置される。次に、炭化珪素基板１００と第１定盤の間および炭化珪素基板１００と第２定盤との間にスラリーが導入される。スラリーは、たとえばダイヤモンド砥粒と水とを含む。ダイヤモンド砥粒の径は、たとえば１μｍ以上３μｍ以下である。以上により、炭化珪素基板１００の両面に対して機械研磨が行われる。 Next, a double-sided mechanical polishing process is performed. Specifically, silicon carbide substrate 100 is placed between a first surface plate (not shown) and a second surface plate (not shown). Next, slurry is introduced between silicon carbide substrate 100 and the first surface plate and between silicon carbide substrate 100 and the second surface plate. The slurry includes, for example, diamond abrasive grains and water. The diameter of the diamond abrasive grains is, for example, 1 μm or more and 3 μm or less. As described above, mechanical polishing is performed on both sides of silicon carbide substrate 100.
　次に、化学機械研磨工程が実施される。図５は、炭化珪素基板１００に対して化学機械研磨を行う工程を示す模式図である。図５に示されるように、化学機械研磨装置３００は、研磨布３０１と、研磨ヘッド３０２と、振動加速度センサ３０３と、真空ポンプ３０４と、加圧部３０５と、を有している。研磨布３０１は、たとえばフジボウ愛媛製のスエード研磨布（Ｇ８０４Ｗ）である。研磨ヘッド３０２は、たとえばセラミックスまたはステンレスなどである。振動加速度センサ３０３は、研磨ヘッド３０２に取り付けられる。加圧部３０５は、たとえばエアシリンダである。 Next, a chemical mechanical polishing process is performed. FIG. 5 is a schematic diagram showing a process of chemical mechanical polishing on silicon carbide substrate 100. As shown in FIG. 5, the chemical mechanical polishing apparatus 300 includes a polishing cloth 301, a polishing head 302, a vibration acceleration sensor 303, a vacuum pump 304, and a pressurizing section 305. The polishing cloth 301 is, for example, a suede polishing cloth (G804W) manufactured by Fujibo Ehime. The polishing head 302 is made of, for example, ceramics or stainless steel. A vibration acceleration sensor 303 is attached to the polishing head 302. The pressurizing section 305 is, for example, an air cylinder.
　図５に示されるように、化学機械研磨工程においては、研磨液３１０を用いて炭化珪素基板１００に対して化学機械研磨が行われる。研磨液３１０は、たとえば砥粒３１２と、酸化剤３１１とを有している。砥粒３１２は、たとえばコロイダルシリカである。酸化剤３１１は、たとえば過酸化水素水、過マンガン酸塩、硝酸塩または次亜塩素酸塩などである。研磨液３１０は、たとえばフジミインコーポレーテッド製のＤＳＣ－０９０２である。 As shown in FIG. 5, in the chemical mechanical polishing process, chemical mechanical polishing is performed on silicon carbide substrate 100 using polishing liquid 310. The polishing liquid 310 includes, for example, abrasive grains 312 and an oxidizing agent 311. The abrasive grains 312 are, for example, colloidal silica. The oxidizing agent 311 is, for example, hydrogen peroxide, permanganate, nitrate, or hypochlorite. The polishing liquid 310 is, for example, DSC-0902 manufactured by Fujimi Incorporated.
　本開示に係る化学機械研磨工程においては、炭化珪素基板１００は、ワックスを用いて研磨ヘッド３０２には貼り付けられていない。炭化珪素基板１００は、研磨ヘッド３０２に直接取り付けられている。具体的には、炭化珪素基板１００は、真空ポンプ３０４を用いることにより、研磨ヘッド３０２に真空吸着されている。 In the chemical mechanical polishing process according to the present disclosure, silicon carbide substrate 100 is not attached to polishing head 302 using wax. Silicon carbide substrate 100 is directly attached to polishing head 302. Specifically, silicon carbide substrate 100 is vacuum-adsorbed onto polishing head 302 by using vacuum pump 304 .
　本開示に係る化学機械研磨工程においては、炭化珪素基板１００に印加される圧力の変動が小さくなるように、研磨ヘッド３０２が制御される。具体的には、１ｋＨｚ以下の周波数帯における振動加速度の実効値が２０ｍＧ以下となるように研磨ヘッド３０２の振動が制御される。具体的には、振動加速度センサ３０３を用いて測定された研磨ヘッド３０２の振動加速度に基づいて、エアシリンダのレギュレータが制御されてもよい。これにより、化学機械研磨工程中において、局所的な圧力変動が発生することを抑制することができる。 In the chemical mechanical polishing process according to the present disclosure, polishing head 302 is controlled so that fluctuations in the pressure applied to silicon carbide substrate 100 are reduced. Specifically, the vibration of the polishing head 302 is controlled so that the effective value of vibration acceleration in a frequency band of 1 kHz or less is 20 mG or less. Specifically, the regulator of the air cylinder may be controlled based on the vibration acceleration of the polishing head 302 measured using the vibration acceleration sensor 303. Thereby, it is possible to suppress local pressure fluctuations from occurring during the chemical mechanical polishing process.
　炭化珪素基板１００は、研磨布３０１に対向するように配置される。炭化珪素基板１００と研磨布３０１との間に、砥粒３１２を含む研磨液３１０が供給される。研磨ヘッド３０２の回転数は、たとえば６０ｒｐｍである。研磨布３０１が設けられた定盤の回転数は、たとえば６０ｒｐｍである。平均加工面圧Ｆは、たとえば４５０ｇ／ｃｍ２である。研磨液の流量は、たとえば毎分２リットルである。以上により、本実施形態に係る炭化珪素基板１００（図１）が得られる。 Silicon carbide substrate 100 is arranged to face polishing cloth 301 . A polishing liquid 310 containing abrasive grains 312 is supplied between silicon carbide substrate 100 and polishing cloth 301 . The rotation speed of polishing head 302 is, for example, 60 rpm. The rotation speed of the surface plate provided with the polishing cloth 301 is, for example, 60 rpm. The average processing surface pressure F is, for example, 450 g/cm 2 . The flow rate of the polishing liquid is, for example, 2 liters per minute. Through the above steps, silicon carbide substrate 100 (FIG. 1) according to the present embodiment is obtained.
　＜炭化珪素半導体装置の製造方法＞
　次に、本実施形態に係る炭化珪素半導体装置４００の製造方法について説明する。図６は、本実施形態に係る炭化珪素半導体装置４００の製造方法を概略的に示すフローチャートである。図６に示されるように、本実施形態に係る炭化珪素半導体装置４００の製造方法は、炭化珪素エピタキシャル基板２００を準備する工程（Ｓ１）と、炭化珪素エピタキシャル基板２００を加工する工程（Ｓ２）とを主に有している。 <Method for manufacturing silicon carbide semiconductor device>
Next, a method for manufacturing silicon carbide semiconductor device 400 according to this embodiment will be described. FIG. 6 is a flowchart schematically showing a method for manufacturing silicon carbide semiconductor device 400 according to this embodiment. As shown in FIG. 6, the method for manufacturing silicon carbide semiconductor device 400 according to the present embodiment includes a step of preparing silicon carbide epitaxial substrate 200 (S1), and a step of processing silicon carbide epitaxial substrate 200 (S2). It mainly has
　まず、炭化珪素エピタキシャル基板２００を準備する工程（Ｓ１）が実施される。炭化珪素エピタキシャル基板２００を準備する工程（Ｓ１）においては、まず、本実施形態に係る炭化珪素基板１００が準備される（図１参照）。 First, a step (S1) of preparing silicon carbide epitaxial substrate 200 is performed. In the step (S1) of preparing silicon carbide epitaxial substrate 200, first, silicon carbide substrate 100 according to this embodiment is prepared (see FIG. 1).
　次に、炭化珪素基板１００上に炭化珪素エピタキシャル層２０が形成される。具体的には、炭化珪素基板１００の第１主面１上に炭化珪素エピタキシャル層２０がエピタキシャル成長により形成される。エピタキシャル成長においては、原料ガスとしてたとえばシラン（ＳｉＨ4）およびプロパン（Ｃ3Ｈ8）が用いられ、キャリアガスとして水素（Ｈ2）が用いられる。エピタキシャル成長の温度は、たとえば１４００℃以上１７００℃以下程度である。エピタキシャル成長において、たとえば窒素などのｎ型不純物が、炭化珪素エピタキシャル層２０に導入される。以上により、本実施形態に係る炭化珪素エピタキシャル基板２００が準備される。 Next, silicon carbide epitaxial layer 20 is formed on silicon carbide substrate 100. Specifically, silicon carbide epitaxial layer 20 is formed on first main surface 1 of silicon carbide substrate 100 by epitaxial growth. In epitaxial growth, for example, silane (SiH 4 ) and propane (C 3 H 8 ) are used as source gases, and hydrogen (H 2 ) is used as a carrier gas. The temperature for epitaxial growth is, for example, about 1400° C. or more and 1700° C. or less. During epitaxial growth, an n-type impurity, such as nitrogen, is introduced into silicon carbide epitaxial layer 20. Through the above steps, silicon carbide epitaxial substrate 200 according to this embodiment is prepared.
　図７は、本実施形態に係る炭化珪素エピタキシャル基板の構成を示す断面模式図である。図７に示されるように、本実施形態に係る炭化珪素エピタキシャル基板は、炭化珪素基板１００と、炭化珪素エピタキシャル層２０とを有している。炭化珪素エピタキシャル層２０は、炭化珪素基板１００上に設けられている。 FIG. 7 is a schematic cross-sectional view showing the structure of the silicon carbide epitaxial substrate according to this embodiment. As shown in FIG. 7, the silicon carbide epitaxial substrate according to this embodiment includes a silicon carbide substrate 100 and a silicon carbide epitaxial layer 20. Silicon carbide epitaxial layer 20 is provided on silicon carbide substrate 100.
　炭化珪素エピタキシャル層２０は、バッファ層４１と、ドリフト層４２と、第３主面３とを有していてもよい。バッファ層４１は、炭化珪素基板１００に接している。ドリフト層４２は、バッファ層４１上に設けられている。ドリフト層４２が含む窒素濃度は、バッファ層４１が含む窒素濃度よりも低くてもよい。第３主面３は、ドリフト層４２により構成される。 Silicon carbide epitaxial layer 20 may have buffer layer 41 , drift layer 42 , and third main surface 3 . Buffer layer 41 is in contact with silicon carbide substrate 100 . Drift layer 42 is provided on buffer layer 41. The nitrogen concentration contained in the drift layer 42 may be lower than the nitrogen concentration contained in the buffer layer 41. The third main surface 3 is composed of a drift layer 42.
　次に、炭化珪素エピタキシャル基板２００を加工する工程（Ｓ２）が実施される。具体的には、炭化珪素エピタキシャル基板２００に対して以下のような加工が行われる。まず、炭化珪素エピタキシャル基板２００に対してイオン注入が行われる。 Next, a step (S2) of processing silicon carbide epitaxial substrate 200 is performed. Specifically, the following processing is performed on silicon carbide epitaxial substrate 200. First, ion implantation is performed into silicon carbide epitaxial substrate 200.
　図８は、ボディ領域を形成する工程を示す断面模式図である。ボディ領域を形成する工程において、炭化珪素エピタキシャル層２０の第３主面３に対して、たとえばアルミニウムなどのｐ型不純物がイオン注入される。これにより、ｐ型の導電型を有するボディ領域１１３が形成される。ボディ領域１１３が形成されなかった部分は、ドリフト層４２およびバッファ層４１となる。ボディ領域１１３の厚みは、たとえば０．９μｍである。炭化珪素エピタキシャル層２０は、バッファ層４１と、ドリフト層４２と、ボディ領域１１３とを含む。 FIG. 8 is a schematic cross-sectional view showing the process of forming the body region. In the step of forming the body region, a p-type impurity such as aluminum is ion-implanted into third main surface 3 of silicon carbide epitaxial layer 20 . As a result, body region 113 having p-type conductivity is formed. The portion where body region 113 is not formed becomes drift layer 42 and buffer layer 41. The thickness of the body region 113 is, for example, 0.9 μm. Silicon carbide epitaxial layer 20 includes a buffer layer 41 , a drift layer 42 , and a body region 113 .
　次に、ソース領域を形成する工程が実施される。図９は、ソース領域を形成する工程を示す断面模式図である。具体的には、ボディ領域１１３に対して、たとえばリンなどのｎ型不純物がイオン注入される。これにより、ｎ型の導電型を有するソース領域１１４が形成される。ソース領域１１４の厚みは、たとえば０．４μｍである。ソース領域１１４が含むｎ型不純物の濃度は、ボディ領域１１３が含むｐ型不純物の濃度よりも高い。 Next, a step of forming a source region is performed. FIG. 9 is a schematic cross-sectional view showing the process of forming a source region. Specifically, an n-type impurity such as phosphorus is ion-implanted into body region 113, for example. As a result, a source region 114 having an n-type conductivity type is formed. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of n-type impurities contained in source region 114 is higher than the concentration of p-type impurities contained in body region 113.
　次に、ソース領域１１４に対して、たとえばアルミニウムなどのｐ型不純物がイオン注入されることにより、コンタクト領域１１８が形成される。コンタクト領域１１８は、ソース領域１１４およびボディ領域１１３を貫通し、ドリフト層４２に接するように形成される。コンタクト領域１１８が含むｐ型不純物の濃度は、ソース領域１１４が含むｎ型不純物の濃度よりも高い。 Next, a contact region 118 is formed by ion-implanting a p-type impurity such as aluminum into the source region 114. Contact region 118 is formed to penetrate source region 114 and body region 113 and be in contact with drift layer 42 . The concentration of p-type impurities contained in contact region 118 is higher than the concentration of n-type impurities contained in source region 114.
　次に、イオン注入された不純物を活性化するため活性化アニールが実施される。活性化アニールの温度は、たとえば１５００℃以上１９００℃以下である。活性化アニールの時間は、たとえば３０分程度である。活性化アニールの雰囲気は、たとえばアルゴン雰囲気である。 Next, activation annealing is performed to activate the ion-implanted impurities. The activation annealing temperature is, for example, 1500° C. or more and 1900° C. or less. The activation annealing time is, for example, about 30 minutes. The activation annealing atmosphere is, for example, an argon atmosphere.
　次に、炭化珪素エピタキシャル層２０の第３主面３にトレンチを形成する工程が実施される。図１０は、炭化珪素エピタキシャル層２０の第３主面３にトレンチを形成する工程を示す断面模式図である。ソース領域１１４およびコンタクト領域１１８から構成される第３主面３上に、開口を有するマスク１１７が形成される。マスク１１７を用いて、ソース領域１１４と、ボディ領域１１３と、ドリフト層４２の一部とがエッチングにより除去される。エッチングの方法としては、たとえば誘導結合プラズマ反応性イオンエッチングを用いることができる。具体的には、たとえば反応ガスとしてＳＦ6またはＳＦ6とＯ2との混合ガスを用いた誘導結合プラズマ反応性イオンエッチングが用いられる。エッチングにより、第３主面３に凹部が形成される。 Next, a step of forming a trench in third main surface 3 of silicon carbide epitaxial layer 20 is performed. FIG. 10 is a schematic cross-sectional view showing a step of forming a trench in third main surface 3 of silicon carbide epitaxial layer 20. A mask 117 having an opening is formed on the third main surface 3 composed of the source region 114 and the contact region 118. Using mask 117, source region 114, body region 113, and a portion of drift layer 42 are removed by etching. As the etching method, for example, inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF 6 or a mixed gas of SF 6 and O 2 as a reactive gas is used. A recess is formed in the third main surface 3 by etching.
　次に、凹部において熱エッチングが行われる。熱エッチングは、第３主面３上にマスク１１７が形成された状態で、たとえば、少なくとも１種類以上のハロゲン原子を有する反応性ガスを含む雰囲気中での加熱によって行い得る。少なくとも１種類以上のハロゲン原子は、塩素（Ｃｌ）原子およびフッ素（Ｆ）原子の少なくともいずれかを含む。当該雰囲気は、たとえば、Ｃｌ2、ＢＣｌ3、ＳＦ6またはＣＦ4を含む。たとえば、塩素ガスと酸素ガスとの混合ガスを反応ガスとして用い、熱処理温度を、たとえば７００℃以上１０００℃以下として、熱エッチングが行われる。なお、反応ガスは、上述した塩素ガスと酸素ガスとに加えて、キャリアガスを含んでいてもよい。キャリアガスとしては、たとえば窒素ガス、アルゴンガスまたはヘリウムガスなどを用いることができる。 Next, thermal etching is performed in the recesses. Thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas containing at least one type of halogen atom, with the mask 117 formed on the third main surface 3. At least one type of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. The atmosphere includes, for example, Cl2 , BCl3 , SF6 or CF4 . For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas, and at a heat treatment temperature of, for example, 700° C. or higher and 1000° C. or lower. Note that the reaction gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen gas, argon gas, or helium gas can be used.
　図１０に示されるように、熱エッチングにより、第３主面３にトレンチ５６が形成される。トレンチ５６は、側壁面５３と、底壁面５４とにより規定される。側壁面５３は、ソース領域１１４と、ボディ領域１１３と、ドリフト層４２とにより構成される。底壁面５４は、ドリフト層４２により構成される。次に、マスク１１７が第３主面３から除去される。 As shown in FIG. 10, trenches 56 are formed in the third main surface 3 by thermal etching. Trench 56 is defined by side wall surface 53 and bottom wall surface 54 . Sidewall surface 53 is composed of source region 114, body region 113, and drift layer 42. The bottom wall surface 54 is composed of the drift layer 42. Next, the mask 117 is removed from the third main surface 3.
　次に、ゲート絶縁膜を形成する工程が実施される。図１１は、ゲート絶縁膜を形成する工程を示す断面模式図である。具体的には、第３主面３にトレンチ５６が形成された炭化珪素エピタキシャル基板２００が、酸素を含む雰囲気中において、たとえば１３００℃以上１４００℃以下の温度で加熱される。これにより、底壁面５４においてドリフト層４２と接し、側壁面５３においてドリフト層４２、ボディ領域１１３およびソース領域１１４の各々に接し、かつ第３主面３においてソース領域１１４およびコンタクト領域１１８の各々と接するゲート絶縁膜１１５が形成される。 Next, a step of forming a gate insulating film is performed. FIG. 11 is a schematic cross-sectional view showing the process of forming a gate insulating film. Specifically, silicon carbide epitaxial substrate 200 in which trenches 56 are formed in third main surface 3 is heated at a temperature of, for example, 1300° C. or more and 1400° C. or less in an atmosphere containing oxygen. As a result, the bottom wall surface 54 is in contact with the drift layer 42 , the side wall surface 53 is in contact with each of the drift layer 42 , the body region 113 , and the source region 114 , and the third main surface 3 is in contact with each of the source region 114 and the contact region 118 . A contacting gate insulating film 115 is formed.
　次に、ゲート電極を形成する工程が実施される。図１２は、ゲート電極および層間絶縁膜を形成する工程を示す断面模式図である。ゲート電極１２７は、トレンチ５６の内部においてゲート絶縁膜１１５に接するように形成される。ゲート電極１２７は、トレンチ５６の内部に配置され、ゲート絶縁膜１１５上においてトレンチ５６の側壁面５３および底壁面５４の各々と対面するように形成される。ゲート電極１２７は、たとえばＬＰＣＶＤ（Ｌｏｗ　Ｐｒｅｓｓｕｒｅ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法により形成される。 Next, a step of forming a gate electrode is performed. FIG. 12 is a schematic cross-sectional view showing the process of forming a gate electrode and an interlayer insulating film. Gate electrode 127 is formed inside trench 56 so as to be in contact with gate insulating film 115 . Gate electrode 127 is disposed inside trench 56 and formed on gate insulating film 115 so as to face each of side wall surface 53 and bottom wall surface 54 of trench 56 . The gate electrode 127 is formed, for example, by LPCVD (Low Pressure Chemical Vapor Deposition) method.
　次に、層間絶縁膜１２６が形成される。層間絶縁膜１２６は、ゲート電極１２７を覆い、かつゲート絶縁膜１１５と接するように形成される。層間絶縁膜１２６は、たとえば化学気相成長法により形成される。層間絶縁膜１２６は、たとえば二酸化珪素を含む材料により構成される。次に、ソース領域１１４およびコンタクト領域１１８上に開口部が形成されるように、層間絶縁膜１２６およびゲート絶縁膜１１５の一部がエッチングされる。これにより、コンタクト領域１１８およびソース領域１１４がゲート絶縁膜１１５から露出する。 Next, an interlayer insulating film 126 is formed. Interlayer insulating film 126 is formed to cover gate electrode 127 and to be in contact with gate insulating film 115 . The interlayer insulating film 126 is formed, for example, by chemical vapor deposition. The interlayer insulating film 126 is made of, for example, a material containing silicon dioxide. Next, interlayer insulating film 126 and a portion of gate insulating film 115 are etched so that openings are formed over source region 114 and contact region 118. As a result, contact region 118 and source region 114 are exposed from gate insulating film 115.
　次に、ソース電極を形成する工程が実施される。ソース電極１１６は、ソース領域１１４およびコンタクト領域１１８の各々に接するように形成される。ソース電極１１６は、たとえばスパッタリング法により形成される。ソース電極１１６は、たとえばＴｉ（チタン）、Ａｌ（アルミニウム）およびＳｉ（シリコン）を含む材料から構成されている。 Next, a step of forming a source electrode is performed. Source electrode 116 is formed so as to be in contact with each of source region 114 and contact region 118. Source electrode 116 is formed by, for example, a sputtering method. The source electrode 116 is made of a material containing, for example, Ti (titanium), Al (aluminum), and Si (silicon).
　次に、合金化アニールが実施される。具体的には、ソース領域１１４およびコンタクト領域１１８の各々と接するソース電極１１６が、たとえば９００℃以上１１００℃以下の温度で５分程度保持される。これにより、ソース電極１１６の少なくとも一部がシリサイド化する。これにより、ソース領域１１４とオーミック接合するソース電極１１６が形成される。ソース電極１１６は、コンタクト領域１１８とオーミック接合してもよい。 Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. As a result, a source electrode 116 that is in ohmic contact with the source region 114 is formed. Source electrode 116 may be in ohmic contact with contact region 118.
　次に、ソース配線１１９が形成される。ソース配線１１９は、ソース電極１１６と電気的に接続される。ソース配線１１９は、ソース電極１１６および層間絶縁膜１２６を覆うように形成される。 Next, source wiring 119 is formed. Source wiring 119 is electrically connected to source electrode 116. Source wiring 119 is formed to cover source electrode 116 and interlayer insulating film 126 .
　次に、ドレイン電極を形成する工程が実施される。まず、第２主面２において、炭化珪素基板１００が研磨される。これにより、炭化珪素基板１００の厚みが薄くなる。次に、ドレイン電極１２３が形成される。ドレイン電極１２３は、第２主面２と接するように形成される。以上により、本実施形態に係る炭化珪素半導体装置４００が製造される。 Next, a step of forming a drain electrode is performed. First, silicon carbide substrate 100 is polished on second main surface 2 . This reduces the thickness of silicon carbide substrate 100. Next, drain electrode 123 is formed. Drain electrode 123 is formed so as to be in contact with second main surface 2 . Through the above steps, silicon carbide semiconductor device 400 according to this embodiment is manufactured.
　図１３は、本実施形態に係る炭化珪素半導体装置の構成を示す断面模式図である。炭化珪素半導体装置４００は、たとえばＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）である。炭化珪素半導体装置４００は、炭化珪素エピタキシャル基板２００と、ゲート電極１２７と、ゲート絶縁膜１１５と、ソース電極１１６と、ドレイン電極１２３と、ソース配線１１９と、層間絶縁膜１２６とを主に有している。炭化珪素エピタキシャル基板２００は、バッファ層４１と、ドリフト層４２と、ボディ領域１１３と、ソース領域１１４と、コンタクト領域１１８とを有している。炭化珪素半導体装置４００は、たとえばＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）等であってもよい。 FIG. 13 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment. Silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Silicon carbide semiconductor device 400 mainly includes silicon carbide epitaxial substrate 200, gate electrode 127, gate insulating film 115, source electrode 116, drain electrode 123, source wiring 119, and interlayer insulating film 126. ing. Silicon carbide epitaxial substrate 200 has buffer layer 41 , drift layer 42 , body region 113 , source region 114 , and contact region 118 . Silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor).
　次に、本実施形態の炭化珪素基板１００、炭化珪素エピタキシャル基板２００および炭化珪素半導体装置４００の製造方法の作用効果について説明する。 Next, the effects of the method for manufacturing silicon carbide substrate 100, silicon carbide epitaxial substrate 200, and silicon carbide semiconductor device 400 of this embodiment will be described.
　炭化珪素基板１００には、極めて平滑な主面が求められる。表面粗さの指標としては、一般的に算術平均高さ（Ｓａ）が用いられる。しかしながら、炭化珪素基板１００の主面１におけるＳａが低い場合であっても、当該炭化珪素基板１００を用いて作製された炭化珪素半導体装置４００の歩留まりが悪いことがあった。 Silicon carbide substrate 100 is required to have an extremely smooth main surface. Arithmetic mean height (Sa) is generally used as an index of surface roughness. However, even when Sa on main surface 1 of silicon carbide substrate 100 is low, the yield of silicon carbide semiconductor device 400 manufactured using silicon carbide substrate 100 may be poor.
　発明者は、炭化珪素半導体装置４００の歩留まりが悪化する原因について鋭意検討を行った結果、主面１のＳａに影響を与えない程度の微小な局所凹部６が、炭化珪素半導体装置４００の歩留まりに悪影響を与えていることを見い出した。局所凹部６上に形成される酸化膜の厚みが薄くなることにより、炭化珪素半導体装置４００の耐圧が低下していることが歩留まり悪化の原因の一つであると考えられる。 As a result of intensive investigation into the causes of the deterioration of the yield of silicon carbide semiconductor device 400, the inventor found that minute local recesses 6 that do not affect Sa on main surface 1 are the cause of deterioration of the yield of silicon carbide semiconductor device 400. It was found that it had a negative impact. It is thought that one of the causes of the deterioration in yield is that the withstand voltage of silicon carbide semiconductor device 400 is reduced due to the thinning of the oxide film formed on local recess 6.
　発明者は、さらに検討を行った結果、主面１のＳａに影響を与えない程度の微小な局所凹部６は、Ｓｓｋとして規定されるスキューネスと強い相関があることに着目した。具体的には、炭化珪素基板１００の主面１において、Ｓａとして規定される算術平均高さを０．１ｎｍ以下とし、かつ、Ｓｓｋとして規定されるスキューネスを０以上とすることにより、炭化珪素半導体装置４００の歩留まりを向上することが可能である。 As a result of further study, the inventor noticed that the minute local recesses 6 that do not affect Sa of the main surface 1 have a strong correlation with the skewness defined as Ssk. Specifically, on main surface 1 of silicon carbide substrate 100, the arithmetic mean height defined as Sa is set to 0.1 nm or less, and the skewness defined as Ssk is set to 0 or more, thereby forming a silicon carbide semiconductor. It is possible to improve the yield of the device 400.
　炭化珪素は、硬度が非常に高い材料である。そのため、炭化珪素基板１００を研磨する際には、炭化珪素基板１００に対して高荷重が印加される。砥粒を含む研磨液を用いて炭化珪素基板１００が研磨される際、加圧中の微振動等により局所的に圧力変動が発生し、炭化珪素基板１００の表面に局所凹部６が形成されることがある。本開示に係る炭化珪素基板１００の製造方法においては、局所的な圧力変動を抑制しつつ、炭化珪素基板１００に対して化学機械研磨を行った。 Silicon carbide is a material with extremely high hardness. Therefore, when polishing silicon carbide substrate 100, a high load is applied to silicon carbide substrate 100. When silicon carbide substrate 100 is polished using a polishing liquid containing abrasive grains, local pressure fluctuations occur due to micro vibrations during pressurization, etc., and local recesses 6 are formed on the surface of silicon carbide substrate 100. Sometimes. In the method for manufacturing silicon carbide substrate 100 according to the present disclosure, chemical mechanical polishing was performed on silicon carbide substrate 100 while suppressing local pressure fluctuations.
　第１の改善点として、本開示に係る化学機械研磨工程においては、炭化珪素基板１００は、ワックスを用いることなく、研磨ヘッドに直接取り付けた。通常、炭化珪素基板１００は、ワックスを用いて支持体である研磨ヘッドに取り付けられる。この際、炭化珪素基板１００を押圧することで、ワックスを介して炭化珪素基板１００を研磨ヘッドに取り付ける。炭化珪素基板１００が押圧される際、異物が炭化珪素基板１００に噛み込むことにより、炭化珪素基板１００に凹部が形成されることがある。本開示に係る化学機械研磨工程においては、炭化珪素基板１００は、ワックスを用いることなく、研磨ヘッドに直接取り付けられるため、炭化珪素基板１００において局所凹部６が形成されることを抑制することができる。 As a first improvement, in the chemical mechanical polishing process according to the present disclosure, silicon carbide substrate 100 was directly attached to the polishing head without using wax. Typically, silicon carbide substrate 100 is attached to a polishing head, which is a support, using wax. At this time, silicon carbide substrate 100 is attached to the polishing head via wax by pressing silicon carbide substrate 100. When silicon carbide substrate 100 is pressed, a concave portion may be formed in silicon carbide substrate 100 due to foreign matter biting into silicon carbide substrate 100 . In the chemical mechanical polishing process according to the present disclosure, silicon carbide substrate 100 is directly attached to the polishing head without using wax, so it is possible to suppress the formation of local recesses 6 in silicon carbide substrate 100. .
　第２の改善点として、本開示に係る化学機械研磨工程においては、炭化珪素基板１００に印加される圧力の変動が小さくなるように、研磨ヘッド３０２が制御される。具体的には、１ｋＨｚ以下の周波数帯における振動加速度の実効値が２０ｍＧ以下となるように研磨ヘッド３０２の振動が制御される。これにより、化学機械研磨工程中において、局所的な圧力変動が発生することを抑制することができる。結果として、炭化珪素基板１００において局所凹部６が形成されることを抑制することができる。 As a second improvement, in the chemical mechanical polishing process according to the present disclosure, polishing head 302 is controlled so that fluctuations in the pressure applied to silicon carbide substrate 100 are reduced. Specifically, the vibration of the polishing head 302 is controlled so that the effective value of vibration acceleration in a frequency band of 1 kHz or less is 20 mG or less. Thereby, it is possible to suppress local pressure fluctuations from occurring during the chemical mechanical polishing process. As a result, formation of local recesses 6 in silicon carbide substrate 100 can be suppressed.
　本実施形態に係る炭化珪素基板１００によれば、Ｓａとして規定される算術平均高さは０．１ｎｍ以下であり、かつ、Ｓｓｋとして規定されるスキューネスは０以上である。これにより、炭化珪素半導体装置４００の歩留まりを向上することが可能である。 According to silicon carbide substrate 100 according to the present embodiment, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or more. Thereby, it is possible to improve the yield of silicon carbide semiconductor device 400.
　本実施形態に係る炭化珪素基板１００によれば、Ｓｓｋとして規定されるスキューネスは、０．４以下であってもよい。これにより、炭化珪素半導体装置４００の歩留まりをさらに向上することが可能である。 According to silicon carbide substrate 100 according to the present embodiment, the skewness defined as Ssk may be 0.4 or less. Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
　本実施形態に係る炭化珪素基板１００によれば、Ｓｓｋとして規定されるスキューネスは、０．３以下であってもよい。これにより、炭化珪素半導体装置４００の歩留まりをさらに向上することが可能である。 According to the silicon carbide substrate 100 according to the present embodiment, the skewness defined as Ssk may be 0.3 or less. Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
　本実施形態に係る炭化珪素基板１００によれば、Ｓａとして規定される算術平均高さは、０．０６ｎｍ以上であってもよい。これにより、炭化珪素半導体装置４００の歩留まりをさらに向上することが可能である。 According to silicon carbide substrate 100 according to the present embodiment, the arithmetic mean height defined as Sa may be 0.06 nm or more. Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
　本実施形態に係る炭化珪素基板１００によれば、Ｓａとして規定される算術平均高さは、０．０６ｎｍ以上であり、かつ、Ｓｓｋとして規定されるスキューネスは、０．３以下であってもよい。これにより、炭化珪素半導体装置４００の歩留まりをさらに向上することが可能である。 According to silicon carbide substrate 100 according to the present embodiment, the arithmetic mean height defined as Sa may be 0.06 nm or more, and the skewness defined as Ssk may be 0.3 or less. . Thereby, it is possible to further improve the yield of silicon carbide semiconductor device 400.
　本実施形態に係る炭化珪素基板１００によれば、主面の最大径は、１５０ｍｍ以上であってもよい。これにより、大口径の炭化珪素基板１００を用いた場合においても、炭化珪素半導体装置４００の歩留まりを向上することが可能である。 According to silicon carbide substrate 100 according to the present embodiment, the maximum diameter of the main surface may be 150 mm or more. Thereby, even when using large diameter silicon carbide substrate 100, it is possible to improve the yield of silicon carbide semiconductor device 400.
　次に、実施例について説明する。サンプル１－１から１－５に係る炭化珪素基板１００は、グループＧ１の化学機械研磨工程を用いて製造された。サンプル２－１から２－４に係る炭化珪素基板１００は、グループＧ２の化学機械研磨工程を用いて製造された。サンプル３－１から３－１２に係る炭化珪素基板１００は、グループＧ３の化学機械研磨工程を用いて製造された。 Next, examples will be described. Silicon carbide substrates 100 according to samples 1-1 to 1-5 were manufactured using a chemical mechanical polishing process of group G1. Silicon carbide substrates 100 according to samples 2-1 to 2-4 were manufactured using a chemical mechanical polishing process of group G2. Silicon carbide substrates 100 according to samples 3-1 to 3-12 were manufactured using a chemical mechanical polishing process of group G3.
　グループＧ１、Ｇ２およびＧ３の化学機械研磨工程において、砥粒３１２は、コロイダルシリカとした。研磨液３１０は、フジミインコーポレーテッド製のＤＳＣ－０９０２とした。研磨ヘッド３０２の回転数は、６０ｒｐｍとした。研磨布３０１が設けられた定盤の回転数は、６０ｒｐｍとした。平均加工面圧Ｆは、４５０ｇ／ｃｍ２とした。研磨液の流量は、毎分２リットルとした。 In the chemical mechanical polishing steps of groups G1, G2, and G3, the abrasive grains 312 were colloidal silica. The polishing liquid 310 was DSC-0902 manufactured by Fujimi Incorporated. The rotation speed of the polishing head 302 was 60 rpm. The rotation speed of the surface plate provided with the polishing cloth 301 was 60 rpm. The average working surface pressure F was 450 g/cm 2 . The flow rate of the polishing liquid was 2 liters per minute.
　グループＧ１の化学機械研磨工程においては、炭化珪素基板１００は、ワックスを用いて研磨ヘッド３０２には貼り付けられた。一方、グループＧ２およびＧ３の化学機械研磨工程においては、炭化珪素基板１００は、ワックスを用いることなく、研磨ヘッド３０２に直接取り付けられた。 In the chemical mechanical polishing process of group G1, silicon carbide substrate 100 was attached to polishing head 302 using wax. On the other hand, in the chemical mechanical polishing steps of groups G2 and G3, silicon carbide substrate 100 was directly attached to polishing head 302 without using wax.
　グループＧ１およびＧ２の化学機械研磨工程においては、研磨ヘッド３０２の振動制御は実施されなかった。一方、グループＧ３の化学機械研磨工程においては、研磨ヘッド３０２の振動制御が実施された。具体的には、１ｋＨｚ以下の周波数帯における振動加速度の実効値が２０ｍＧ以下となるように研磨ヘッド３０２の振動が制御された。 In the chemical mechanical polishing processes of groups G1 and G2, vibration control of the polishing head 302 was not performed. On the other hand, in the chemical mechanical polishing process of group G3, vibration control of the polishing head 302 was performed. Specifically, the vibration of the polishing head 302 was controlled so that the effective value of vibration acceleration in a frequency band of 1 kHz or less was 20 mG or less.
　次に、サンプル１－１から３－１２に係る炭化珪素基板１００の中央部１０において、ＳａおよびＳｓｋが測定された。ＳａおよびＳｓｋは、白色干渉顕微鏡（ニコン社製ＢＷ－Ｄ５０７）を用いて測定された。ＳａおよびＳｓｋの測定領域は、一辺の長さが２５０μｍの正方領域５とした。サンプル１－１から３－１２に係る炭化珪素基板１００を用いてＭＯＳＦＥＴが作製され、ＭＯＳＦＥＴの耐圧不良率が求められた。 Next, Sa and Ssk were measured in central portions 10 of silicon carbide substrates 100 according to samples 1-1 to 3-12. Sa and Ssk were measured using a white interference microscope (Nikon BW-D507). The measurement area for Sa and Ssk was a square area 5 with a side length of 250 μm. MOSFETs were fabricated using silicon carbide substrates 100 according to samples 1-1 to 3-12, and the breakdown voltage failure rate of the MOSFETs was determined.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　表１は、サンプル１－１から１－５に係る炭化珪素基板１００の中央部１０におけるＳａおよびＳｓｋと、当該炭化珪素基板１００を用いて作製されたＭＯＳＦＥＴの耐圧不良率とを示している。Ｓａは、０．１１７ｎｍ以上０．１３３ｎｍ以下であった。Ｓｓｋは、－０．０９２以上０．２９７以下であった。耐圧不良率は、２９％以上３５％以下であった。 Table 1 shows Sa and Ssk in the center portion 10 of the silicon carbide substrates 100 according to samples 1-1 to 1-5, and the breakdown voltage failure rate of MOSFETs manufactured using the silicon carbide substrates 100. Sa was 0.117 nm or more and 0.133 nm or less. Ssk was -0.092 or more and 0.297 or less. The breakdown voltage failure rate was 29% or more and 35% or less.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　表２は、サンプル２－１から２－４に係る炭化珪素基板１００の中央部１０におけるＳａおよびＳｓｋと、当該炭化珪素基板１００を用いて作製されたＭＯＳＦＥＴの耐圧不良率とを示している。Ｓａは、０．０７８ｎｍ以上０．０９５ｎｍ以下であった。Ｓｓｋは、－０．４２７以上－０．０１５以下であった。耐圧不良率は、２７％以上３１％以下であった。 Table 2 shows Sa and Ssk in the center portion 10 of the silicon carbide substrates 100 according to samples 2-1 to 2-4, and the breakdown voltage failure rate of MOSFETs manufactured using the silicon carbide substrates 100. Sa was 0.078 nm or more and 0.095 nm or less. Ssk was -0.427 or more and -0.015 or less. The breakdown voltage failure rate was 27% or more and 31% or less.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
　表３は、サンプル３－１から３－１２に係る炭化珪素基板１００の中央部１０におけるＳａおよびＳｓｋと、当該炭化珪素基板１００を用いて作製されたＭＯＳＦＥＴの耐圧不良率とを示している。Ｓａは、０．０７９ｎｍ以上０．０９５ｎｍ以下であった。Ｓｓｋは、０．００１以上０．２３７以下であった。耐圧不良率は、１９％以上２２％以下であった。 Table 3 shows Sa and Ssk in the center portion 10 of the silicon carbide substrates 100 according to samples 3-1 to 3-12, and the breakdown voltage failure rate of MOSFETs manufactured using the silicon carbide substrates 100. Sa was 0.079 nm or more and 0.095 nm or less. Ssk was 0.001 or more and 0.237 or less. The breakdown voltage failure rate was 19% or more and 22% or less.
　図１４は、ＳａとＳｓｋとの関係を示す図である。図１４に示されるように、グループＧ２の化学機械研磨工程を用いて製造された炭化珪素基板１００においては、Ｓａが低く、かつＳｓｋが０未満である。一方、グループＧ３の化学機械研磨工程を用いて製造された炭化珪素基板１００においては、Ｓａが低く、かつＳｓｋが０以上である。 FIG. 14 is a diagram showing the relationship between Sa and Ssk. As shown in FIG. 14, in silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of group G2, Sa is low and Ssk is less than 0. On the other hand, in silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of group G3, Sa is low and Ssk is 0 or more.
　図１５は、Ｓａと耐圧不良率との関係を示す図である。図１５に示されるように、グループＧ２の化学機械研磨工程を用いて製造された炭化珪素基板１００を用いて作製された炭化珪素半導体装置４００の耐圧不良率は、比較的高かった。一方、グループＧ３の化学機械研磨工程を用いて製造された炭化珪素基板１００を用いて作製された炭化珪素半導体装置４００の耐圧不良率は、顕著に低くなった。以上の結果より、Ｓａを０．１ｎｍ以下とし、かつ、Ｓｓｋを０以上とすることにより、炭化珪素半導体装置４００の耐圧不良率を顕著に低減可能であることが確かめられた。 FIG. 15 is a diagram showing the relationship between Sa and the breakdown voltage failure rate. As shown in FIG. 15, the breakdown voltage failure rate of silicon carbide semiconductor device 400 manufactured using silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of group G2 was relatively high. On the other hand, the breakdown voltage defect rate of silicon carbide semiconductor device 400 manufactured using silicon carbide substrate 100 manufactured using the chemical mechanical polishing process of Group G3 was significantly lower. From the above results, it was confirmed that by setting Sa to 0.1 nm or less and Ssk to 0 or more, the breakdown voltage failure rate of silicon carbide semiconductor device 400 can be significantly reduced.
　本開示は以下に示す実施形態を含む。
（付記１）
　主面を備え、
　前記主面は、前記主面の外周縁から３ｍｍ以内の外周部と、前記外周部に囲まれた中央部とにより構成されており、
　前記中央部における任意の正方領域において、Ｓａとして規定される算術平均高さは０．１ｎｍ以下であり、かつ、Ｓｓｋとして規定されるスキューネスは０以上であり、
　前記正方領域の一辺の長さは、２５０μｍである、炭化珪素基板。
（付記２）
　前記Ｓｓｋとして規定されるスキューネスは、０．４以下である、付記１に記載の炭化珪素基板。
（付記３）
　前記Ｓｓｋとして規定されるスキューネスは、０．３以下である、付記１に記載の炭化珪素基板。
（付記４）
　前記Ｓａとして規定される算術平均高さは、０．０６ｎｍ以上である、付記１から付記３のいずれか１項に記載の炭化珪素基板。
（付記５）
　前記Ｓａとして規定される算術平均高さは、０．０６ｎｍ以上であり、かつ、前記Ｓｓｋとして規定されるスキューネスは、０．３以下である、付記１に記載の炭化珪素基板。（付記６）
　前記主面の最大径は、１５０ｍｍ以上である、付記１から付記３のいずれか１項に記載の炭化珪素基板。
（付記７）
　付記１から付記３のいずれか１項に記載の炭化珪素基板と、
　前記炭化珪素基板上に設けられた炭化珪素エピタキシャル層と、を備えた、炭化珪素エピタキシャル基板。 The present disclosure includes the embodiments described below.
(Additional note 1)
having a main surface;
The main surface is composed of an outer peripheral part within 3 mm from the outer peripheral edge of the main surface, and a central part surrounded by the outer peripheral part,
In any square area in the central part, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or more,
A silicon carbide substrate in which the length of one side of the square region is 250 μm.
(Additional note 2)
The silicon carbide substrate according to Supplementary Note 1, wherein the skewness defined as Ssk is 0.4 or less.
(Additional note 3)
The silicon carbide substrate according to Supplementary Note 1, wherein the skewness defined as Ssk is 0.3 or less.
(Additional note 4)
The silicon carbide substrate according to any one of Supplementary Notes 1 to 3, wherein the arithmetic mean height defined as Sa is 0.06 nm or more.
(Appendix 5)
The silicon carbide substrate according to appendix 1, wherein the arithmetic mean height defined as Sa is 0.06 nm or more, and the skewness defined as Ssk is 0.3 or less. (Appendix 6)
The silicon carbide substrate according to any one of Supplementary notes 1 to 3, wherein the main surface has a maximum diameter of 150 mm or more.
(Appendix 7)
The silicon carbide substrate according to any one of Supplementary notes 1 to 3,
A silicon carbide epitaxial substrate, comprising: a silicon carbide epitaxial layer provided on the silicon carbide substrate.
　今回開示された実施の形態および実施例はすべての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味、および範囲内でのすべての変更が含まれることが意図される。 The embodiments and examples disclosed herein are illustrative in all respects and should not be considered restrictive. The scope of the present invention is indicated by the claims rather than the above description, and it is intended that equivalent meanings to the claims and all changes within the range be included.
１　第１主面（主面）、２　第２主面、３　第３主面、４　外周縁、５　正方領域、６　局所凹部、７　オリエンテーションフラット、８　円弧状部、９　外周側面、１０　中央部、１２　外周部、２０　炭化珪素エピタキシャル層、４１　バッファ層、４２　ドリフト層、５３　側壁面、５４　底壁面、５６　トレンチ、６１　底面、６２　側面、１００　炭化珪素基板、１０１　第１方向、１０２　第２方向、１１３　ボディ領域、１１４　ソース領域、１１５　ゲート絶縁膜、１１６　ソース電極、１１７　マスク、１１８　コンタクト領域、１１９　ソース配線、１２３　ドレイン電極、１２６　層間絶縁膜、１２７　ゲート電極、２００　炭化珪素エピタキシャル基板、３００　化学機械研磨装置、３０１　研磨布、３０２　研磨ヘッド、３０３　振動加速度センサ、３０４　真空ポンプ、３０５　加圧部、３１０　研磨液、３１１　酸化剤、３１２　砥粒、４００　炭化珪素半導体装置、Ｄ　深さ、Ｆ　平均加工面圧、Ｗ１　最大径、Ｗ２　幅、Ｗ３　長さ、θ　オフ角。 1. First main surface (main surface), 2. Second main surface, 3. Third main surface, 4. Outer periphery, 5. Square area, 6. Local recess, 7. Orientation flat, 8. Arc-shaped part, 9. Outer peripheral side surface, 10. Center part. , 12 outer periphery, 20 silicon carbide epitaxial layer, 41 buffer layer, 42 drift layer, 53 side wall surface, 54 bottom wall surface, 56 trench, 61 bottom surface, 62 side surface, 100 silicon carbide substrate, 101 first direction, 102 second direction , 113 body region, 114 source region, 115 gate insulating film, 116 source electrode, 117 mask, 118 contact region, 119 source wiring, 123 drain electrode, 126 interlayer insulating film, 127 gate electrode, 200 silicon carbide epitaxial substrate, 300 chemistry Mechanical polishing device, 301 Polishing cloth, 302 Polishing head, 303 Vibration acceleration sensor, 304 Vacuum pump, 305 Pressure part, 310 Polishing liquid, 311 Oxidizing agent, 312 Abrasive grain, 400 Silicon carbide semiconductor device, D Depth, F Average Machining surface pressure, W1 maximum diameter, W2 width, W3 length, θ off angle.

Claims (8)

  1. 　主面を備え、
    　前記主面は、前記主面の外周縁から３ｍｍ以内の外周部と、前記外周部に囲まれた中央部とにより構成されており、
    　前記中央部における任意の正方領域において、Ｓａとして規定される算術平均高さは０．１ｎｍ以下であり、かつ、Ｓｓｋとして規定されるスキューネスは０以上であり、
    　前記正方領域の一辺の長さは、２５０μｍである、炭化珪素基板。     having a main surface;
    The main surface is composed of an outer peripheral part within 3 mm from the outer peripheral edge of the main surface, and a central part surrounded by the outer peripheral part,
    In any square area in the central part, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or more,
    A silicon carbide substrate in which the length of one side of the square region is 250 μm.
  2. 　前記Ｓｓｋとして規定されるスキューネスは、０．４以下である、請求項１に記載の炭化珪素基板。 The silicon carbide substrate according to claim 1, wherein the skewness defined as the Ssk is 0.4 or less.
  3. 　前記Ｓｓｋとして規定されるスキューネスは、０．３以下である、請求項１に記載の炭化珪素基板。 The silicon carbide substrate according to claim 1, wherein the skewness defined as the Ssk is 0.3 or less.
  4. 　前記Ｓａとして規定される算術平均高さは、０．０６ｎｍ以上である、請求項１から請求項３のいずれか１項に記載の炭化珪素基板。 The silicon carbide substrate according to any one of claims 1 to 3, wherein the arithmetic mean height defined as Sa is 0.06 nm or more.
  5. 　前記Ｓａとして規定される算術平均高さは、０．０６ｎｍ以上であり、かつ、前記Ｓｓｋとして規定されるスキューネスは、０．３以下である、請求項１に記載の炭化珪素基板。 The silicon carbide substrate according to claim 1, wherein the arithmetic mean height defined as Sa is 0.06 nm or more, and the skewness defined as Ssk is 0.3 or less.
  6. 　前記主面の最大径は、１５０ｍｍ以上である、請求項１から請求項５のいずれか１項に記載の炭化珪素基板。 The silicon carbide substrate according to any one of claims 1 to 5, wherein the main surface has a maximum diameter of 150 mm or more.
  7. 　請求項１から請求項６のいずれか１項に記載の炭化珪素基板と、
    　前記炭化珪素基板上に設けられた炭化珪素エピタキシャル層と、を備えた、炭化珪素エピタキシャル基板。     The silicon carbide substrate according to any one of claims 1 to 6,
    A silicon carbide epitaxial substrate, comprising: a silicon carbide epitaxial layer provided on the silicon carbide substrate.
  8. 　請求項７に記載の炭化珪素エピタキシャル基板を準備する工程と、
    　前記炭化珪素エピタキシャル基板を加工する工程と、を備えた、炭化珪素半導体装置の製造方法。     A step of preparing a silicon carbide epitaxial substrate according to claim 7;
    A method for manufacturing a silicon carbide semiconductor device, comprising the step of processing the silicon carbide epitaxial substrate.
PCT/JP2023/022960 2022-08-08 2023-06-21 Silicon carbide substrate, silicon carbide epitaxial substrate, and method for manufacturing silicon carbide semiconductor device WO2024034267A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013012767A (en) * 2012-08-31 2013-01-17 Fujitsu Ltd Compound semiconductor device, and method for manufacturing the same
JP2016048790A (en) * 2015-11-05 2016-04-07 住友化学株式会社 Nitride semiconductor epitaxial wafer for transistor and nitride semiconductor field effect transistor
JP2021138597A (en) * 2020-02-28 2021-09-16 エスケイシー・カンパニー・リミテッドSkc Co., Ltd. Wafer, epitaxial wafer and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013012767A (en) * 2012-08-31 2013-01-17 Fujitsu Ltd Compound semiconductor device, and method for manufacturing the same
JP2016048790A (en) * 2015-11-05 2016-04-07 住友化学株式会社 Nitride semiconductor epitaxial wafer for transistor and nitride semiconductor field effect transistor
JP2021138597A (en) * 2020-02-28 2021-09-16 エスケイシー・カンパニー・リミテッドSkc Co., Ltd. Wafer, epitaxial wafer and method for manufacturing the same

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