JP2022172550A - Method for manufacturing silicon carbide epitaxial substrate, and method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a silicon carbide epitaxial substrate, capable of reducing the probability of causing poor exposure in the step of manufacturing a silicon carbide semiconductor device, and a method for manufacturing the silicon carbide semiconductor device.SOLUTION: A method for manufacturing a silicon carbide epitaxial substrate comprises: measuring each LTV of a plurality of first silicon carbide substrates; measuring each LTV of a plurality of first silicon carbide epitaxial substrates; determining a reference for selecting a second silicon carbide substrate different from each of the plurality of first silicon carbide substrates on the basis of a relationship between each LTV of the plurality of first silicon carbide substrates and each LTV of the plurality of first silicon carbide epitaxial substrates; measuring the LTV of the second silicon carbide substrate; determining whether the LTV of the second silicon carbide substrate satisfies the reference; and forming a second silicon carbide epitaxial layer on the second silicon carbide substrate satisfying the reference.SELECTED DRAWING: Figure 7

Description

The present disclosure relates to a method for manufacturing a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device.

Noboru Otani, "Development trend of large diameter SiC single crystal substrate", Journal of the Vacuum Society of Japan, Vol. method is described.

Noboru Otani, "Development trend of large diameter SiC single crystal substrate", Journal of the Vacuum Society of Japan, Vol.54, No.6, pp.339-345, 2011

An object of the present disclosure is to provide a method for manufacturing a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device that can reduce the probability of occurrence of exposure failure in a manufacturing process of a silicon carbide semiconductor device.

A method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure includes the following steps. A plurality of first silicon carbide substrates are prepared. LTV of each of the plurality of first silicon carbide substrates is measured. A plurality of first silicon carbide epitaxial substrates are obtained by forming a first silicon carbide epitaxial layer on each of the plurality of first silicon carbide substrates. LTV of each of the plurality of first silicon carbide epitaxial substrates is measured. A second silicon carbide substrate different from each of the plurality of first silicon carbide substrates is selected based on the relationship between the LTV of each of the plurality of first silicon carbide substrates and the LTV of each of the plurality of first silicon carbide epitaxial substrates. Criteria for doing so are determined. LTV of the second silicon carbide substrate is measured. It is determined whether the LTV of the second silicon carbide substrate satisfies a standard. A second silicon carbide epitaxial layer is formed on a second silicon carbide substrate meeting the criteria.

A method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure includes the following steps. A plurality of first silicon carbide substrates are prepared. LTIR of each of the plurality of first silicon carbide substrates is measured. A plurality of first silicon carbide epitaxial substrates are obtained by forming a first silicon carbide epitaxial layer on each of the plurality of first silicon carbide substrates. The LTIR of each of the plurality of first silicon carbide epitaxial substrates is measured. Second silicon carbide substrates different from each of the plurality of first silicon carbide substrates are selected based on the relationship between the LTIR of each of the plurality of first silicon carbide substrates and the LTIR of each of the plurality of first silicon carbide epitaxial substrates Criteria for doing so are determined. LTIR of the second silicon carbide substrate is measured. It is determined whether the LTIR of the second silicon carbide substrate meets the criteria. A second silicon carbide epitaxial layer is formed on a second silicon carbide substrate meeting the criteria.

According to the present disclosure, it is possible to provide a method for manufacturing a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device that can reduce the probability of exposure failure occurring in the manufacturing process of a silicon carbide semiconductor device.

FIG. 1 is a schematic plan view showing the configuration of a silicon carbide epitaxial substrate. FIG. 2 is a schematic cross-sectional view taken along line II-II of FIG. FIG. 3 is a schematic plan view showing LTV and LTIR measurement regions. FIG. 4 is a schematic diagram for explaining the definition of LTV. FIG. 5 is a schematic diagram explaining the definition of LTIR. FIG. 6 is a schematic partial cross-sectional view showing the configuration of a silicon carbide epitaxial substrate manufacturing apparatus. FIG. 7 is a flow chart schematically showing a method for manufacturing a silicon carbide epitaxial substrate according to the first embodiment. FIG. 8 is a schematic cross-sectional view showing the configuration of each of the plurality of first silicon carbide substrates. FIG. 9 is a schematic cross-sectional view showing the configuration of each of the plurality of first silicon carbide epitaxial substrates. FIG. 10 shows the first area ratio of the first silicon carbide substrate (the area ratio of the region whose LTV is less than 0.8 μm) and the second area ratio of the first silicon carbide epitaxial substrate (the LTV is less than 1.0 μm). FIG. 10 is a diagram showing the relationship between the area ratio of a region). FIG. 11 is a schematic cross-sectional view showing the configuration of the second silicon carbide substrate. FIG. 12 is a flow chart schematically showing a method for manufacturing a silicon carbide epitaxial substrate according to the second embodiment. FIG. 13 shows the first area ratio of the first silicon carbide substrate (the area ratio of the region where the LTIR is less than 0.8 μm) and the second area ratio of the first silicon carbide epitaxial substrate (the LTIR is less than 1.0 μm). FIG. 10 is a diagram showing the relationship between the area ratio of a region). FIG. 14 is a flow chart schematically showing a method for manufacturing a silicon carbide semiconductor device according to this embodiment. FIG. 15 is a schematic cross-sectional view showing the step of forming the body region. FIG. 16 is a schematic cross-sectional view showing a step of forming a source region. FIG. 17 is a schematic cross-sectional view showing a step of forming trenches in the second main surface of the silicon carbide epitaxial layer. FIG. 18 is a schematic cross-sectional view showing a step of forming a gate insulating film. FIG. 19 is a schematic cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. FIG. 20 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to this embodiment.

[Outline of Embodiment of Present Disclosure]
First, an outline of an embodiment of the present disclosure will be described. In the crystallographic description of this specification, individual orientations are indicated by [ ], collective orientations by <>, individual planes by ( ), and collective planes by { }. Negative crystallographic exponents are usually expressed by placing a "-" (bar) above the number, but here the crystallographic index is expressed by prefixing the number with a negative sign. Represents a negative exponent above.

(1) A method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure includes the following steps. A plurality of first silicon carbide substrates 14 are prepared. The LTV of each of the plurality of first silicon carbide substrates 14 is measured. A plurality of first silicon carbide epitaxial substrates 100 are obtained by forming a first silicon carbide epitaxial layer 15 on each of a plurality of first silicon carbide substrates 14 . LTV of each of a plurality of first silicon carbide epitaxial substrates 100 is measured. Second silicon carbide different from each of the plurality of first silicon carbide substrates 14 based on the relationship between the LTV of each of the plurality of first silicon carbide substrates 14 and the LTV of each of the plurality of first silicon carbide epitaxial substrates 100 Criteria for sorting substrates 24 are determined. The LTV of second silicon carbide substrate 24 is measured. It is determined whether or not the LTV of the second silicon carbide substrate 24 satisfies the standard. A second silicon carbide epitaxial layer 25 is formed on a second silicon carbide substrate 24 that satisfies the criteria.

(2) According to the method for manufacturing a silicon carbide epitaxial substrate according to (1) above, first silicon carbide substrates 14 may have a main surface in contact with first silicon carbide epitaxial layer 15 . The major surface may be divided into a plurality of square regions. A side length of each of the plurality of square regions may be 10 mm. In the step of measuring the LTV of each of the plurality of first silicon carbide substrates 14, the LTV may be measured in each of the plurality of square regions. In the step of measuring the LTV of each of the plurality of first silicon carbide epitaxial substrates 100, the LTV may be measured in each of the plurality of square regions.

(3) According to the method for manufacturing a silicon carbide epitaxial substrate according to (1) or (2) above, in the step of determining whether the LTV of second silicon carbide substrate 24 satisfies the standard, the plurality of square regions 50 may be determined that the LTV of the second silicon carbide substrate 24 satisfies the standard when the area ratio of the region having an LTV of less than 1.0 μm is 90% or more.

(4) A method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure includes the following steps. A plurality of first silicon carbide substrates 14 are prepared. LTIR of each of the plurality of first silicon carbide substrates 14 is measured. A plurality of first silicon carbide epitaxial substrates 100 are obtained by forming a first silicon carbide epitaxial layer 15 on each of a plurality of first silicon carbide substrates 14 . LTIR of each of the plurality of first silicon carbide epitaxial substrates 100 is measured. Second silicon carbide different from each of the plurality of first silicon carbide substrates 14 based on the relationship between the LTIR of each of the plurality of first silicon carbide substrates 14 and the LTIR of each of the plurality of first silicon carbide epitaxial substrates 100 Criteria for sorting substrates 24 are determined. The LTIR of second silicon carbide substrate 24 is measured. It is determined whether the LTIR of the second silicon carbide substrate 24 satisfies the criteria. A second silicon carbide epitaxial layer 25 is formed on a second silicon carbide substrate 24 that satisfies the criteria.

(5) According to the method for manufacturing a silicon carbide epitaxial substrate according to (4) above, first silicon carbide substrates 14 may have a main surface in contact with first silicon carbide epitaxial layer 15 . The major surface may be divided into a plurality of square regions 50. FIG. Each side of the plurality of square regions 50 may have a length of 10 mm. In the step of measuring the LTIR of each of multiple first silicon carbide substrates 14 , the LTIR may be measured in each of multiple square regions 50 . In the step of measuring the LTIR of each of multiple first silicon carbide epitaxial substrates 100 , the LTIR may be measured in each of multiple square regions 50 .

(6) According to the method for manufacturing a silicon carbide epitaxial substrate according to (4) or (5) above, in the step of determining whether or not the LTIR of second silicon carbide substrate 24 satisfies the standard, the plurality of square regions 50 may be determined that the LTIR of the second silicon carbide substrate 24 satisfies the criterion when the area ratio of the region having the LTIR of less than 1.0 μm is 90% or more.

(7) A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the following steps. A silicon carbide epitaxial substrate manufactured by the method for manufacturing a silicon carbide epitaxial substrate according to any one of (1) to (6) above is prepared. A silicon carbide epitaxial substrate is processed.

[Details of the embodiment of the present disclosure]
Details of the embodiments of the present disclosure will be described below. In the following description, the same or corresponding elements are given the same reference numerals and the same descriptions thereof are not repeated.

First, the configuration of silicon carbide epitaxial substrate 200 according to the present embodiment will be described. FIG. 1 is a schematic plan view showing the configuration of a silicon carbide epitaxial substrate 200. FIG. FIG. 2 is a schematic cross-sectional view taken along line II-II of FIG.

As shown in FIGS. 1 and 2 , silicon carbide epitaxial substrate 200 according to the present embodiment has second silicon carbide substrate 24 and second silicon carbide epitaxial layer 25 . A second silicon carbide epitaxial layer 25 is on the second silicon carbide substrate 24 . Second silicon carbide epitaxial layer 25 is in contact with second silicon carbide substrate 24 . Silicon carbide epitaxial substrate 200 has a first main surface 21 and a second main surface 22 . The second major surface 22 is opposite the first major surface 21 .

First main surface 21 is formed of second silicon carbide substrate 24 . Second main surface 22 is formed of second silicon carbide epitaxial layer 25 . Second silicon carbide substrate 24 has a third main surface 23 . Third main surface 23 is in contact with second silicon carbide epitaxial layer 25 . The polytype of silicon carbide forming second silicon carbide substrate 24 is, for example, 4H. The polytype of silicon carbide forming second silicon carbide epitaxial layer 25 is, for example, 4H.

As shown in FIG. 1 , silicon carbide epitaxial substrate 200 has an outer peripheral side surface 9 when viewed in the thickness direction of silicon carbide epitaxial substrate 200 . The outer peripheral side surface 9 has, for example, an orientation flat 7 and an arcuate portion 8 . The orientation flat 7 extends along the first direction 101 . As shown in FIG. 1 , orientation flat 7 is linear when viewed in the thickness direction of silicon carbide epitaxial substrate 200 . The arcuate portion 8 continues to the orientation flat 7 . When viewed in the thickness direction of silicon carbide epitaxial substrate 200, arc-shaped portion 8 is arc-shaped.

As shown in FIG. 1 , second main surface 22 extends along each of first direction 101 and second direction 102 when viewed in the thickness direction of silicon carbide epitaxial substrate 200 . First direction 101 is a direction perpendicular to second direction 102 when viewed in the thickness direction of silicon carbide epitaxial substrate 200 .

The first direction 101 is, for example, the <11-20> direction. The first direction 101 may be the [11-20] direction, for example. The first direction 101 may be a direction obtained by projecting the <11-20> direction onto the second main surface 22 . From another point of view, the first direction 101 may be a direction including a <11-20> direction component, for example.

The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be a direction obtained by projecting the <1-100> direction onto the second major surface 22, for example. From another point of view, the second direction 102 may be a direction including a <1-100> direction component, for example.

As shown in FIG. 1, the diameter (first width W1) of silicon carbide epitaxial substrate 200 is not particularly limited, but is, for example, 100 mm (4 inches) or more. The first width W1 may be 125 mm (5 inches) or more, or may be 150 mm (6 inches) or more. The upper limit of the first width W1 is not particularly limited. The first width W1 may be, for example, 200 (8 inches) mm or less.

In this specification, 4 inches means 100 mm or 101.6 mm (4 inches x 25.4 mm/inch). 5 inches is 125 mm or 127.0 mm (5 inches by 25.4 mm/inch). Six inches is 150 mm or 152.4 mm (6 inches by 25.4 mm/inch). 8 inches is 200 mm or 203.2 mm (8 inches by 25.4 mm/inch).

Second main surface 22 of silicon carbide epitaxial substrate 200 may be inclined at an off angle of 8° or less with respect to the {0001} plane, for example. Specifically, the second main surface 22 may be inclined at an off angle of 8° or less with respect to the (0001) plane or the (0001) plane. The first main surface 21 may be inclined at an off angle of 8° or less with respect to the (000-1) plane or the (000-1) plane.

The upper limit of the off angle is not particularly limited, but may be, for example, 6° or less, or 4° or less. The lower limit of the off angle is not particularly limited, but may be, for example, 2° or more, or 1° or more. The off direction is not particularly limited, but may be, for example, the <11-20> direction or the <0001> direction.

Second silicon carbide substrate 24 contains n-type impurities such as nitrogen (N). The conductivity type of second silicon carbide substrate 24 is, for example, n type (first conductivity type). In this case the carriers are electrons. The carrier concentration of second silicon carbide substrate 24 is, for example, 1×10 ¹⁹ m ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less. The thickness of second silicon carbide substrate 24 is not particularly limited, but may be, for example, 200 μm or more and 500 μm or less.

Second silicon carbide epitaxial layer 25 contains n-type impurities such as nitrogen (N). The conductivity type of second silicon carbide epitaxial layer 25 is, for example, n type (first conductivity type). In this case the carriers are electrons. The carrier concentration of second silicon carbide epitaxial layer 25 is, for example, 1×10 ¹⁴ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less. The thickness of second silicon carbide epitaxial layer 25 is not particularly limited, but may be, for example, 2 μm or more and 100 μm or less.

Next, a method for measuring LTV (Local Thickness Variation) and LTIR (Local Total Indicated Reading) of a substrate will be described. LTV and LTIR can be measured using, for example, "Tropel FlatMaster (registered trademark)" manufactured by Corning Tropel.

FIG. 3 is a schematic plan view showing LTV and LTIR measurement regions. As shown in FIG. 3, the measurement surface A of the substrate is divided into a plurality of square areas 50. As shown in FIG. The length (W2) of one side of each of the plurality of square regions 50 is, for example, 10 mm. A diameter (W1) of the measurement surface A is, for example, 150 mm. First, a 150 mm×150 mm square circumscribing the outer peripheral side surface 9 of the substrate is assumed. A 150 mm×150 mm square is divided into 10 mm×10 mm square regions (15×15=225). The number of square regions 50 surrounded by the outer peripheral side surface 9 is 145 when viewed in the thickness direction of the substrate. When viewed in the thickness direction of the substrate, the square area intersecting with the outer peripheral side surface 9 is partially missing and does not become a complete square area. Therefore, the square area that intersects the outer peripheral side surface 9 is not regarded as the square area 50 forming the measurement surface A. One side of each of the plurality of square regions 50 is parallel to the extending direction of the orientation flat 7 when viewed in the thickness direction of the substrate.

As shown in FIG. 3, when the diameter of the measurement plane A is 150 mm, the measurement plane A is divided into 145 square regions 50 each having a side length W2 of 10 mm. LTV and LTIR are measured in each of the 145 square regions 50 .

Next, the definition of LTV will be explained. FIG. 4 is a schematic diagram for explaining the definition of LTV.

LTV=|T2−T1| (Equation 1)
LTV is measured, for example, by the following procedure. First, a silicon carbide substrate or a silicon carbide epitaxial substrate is prepared. A silicon carbide substrate or a silicon carbide epitaxial substrate has a front surface and a back surface. The back side is the side opposite the front side. One of the front surface and the back surface becomes an attraction surface B that is attracted to the flat chuck surface. The surface on the opposite side of the adsorption surface B becomes the measurement surface A.

An attraction surface B of the silicon carbide substrate or the silicon carbide epitaxial substrate is entirely attracted to the chuck surface. Next, an image of the measurement surface A opposite to the attraction surface B is optically acquired. As shown in FIG. 4 and Equation 1, the LTV is the distance from the attraction surface B to the highest point (first highest point P2) of the measurement surface A in a state where the attraction surface B is entirely attracted to the flat chuck surface. It is a value obtained by subtracting the height (first height T1) from the attraction surface B to the lowest point (first lowest point P1) of the measurement surface A from the height (second height T2). In other words, the LTV is a value obtained by subtracting the shortest distance between the measurement surface A and the attraction surface B from the longest distance between the measurement surface A and the attraction surface B in the direction perpendicular to the attraction surface B. That is, the LTV is a plane (second plane L2) that passes through the first highest point P2 and is parallel to the adsorption surface B, and a plane that passes through the first lowest point P1 and is parallel to the adsorption surface B (first plane L1). is the distance of

Next, a method for measuring LTIR will be described. FIG. 5 is a schematic diagram explaining the definition of LTIR.

LTIR=|T3|+|T4| (Equation 2)
LTIR is measured, for example, by the following procedure. First, the chuck surface B of the silicon carbide substrate or the silicon carbide epitaxial substrate is wholly chucked to the chuck surface. Next, an image of the measurement surface A opposite to the attraction surface B is optically acquired.

Next, a least-squares plane L5 of the square area of the measurement plane A is obtained by calculation. As shown in FIG. 5 and Equation 2, LTIR is the height (maximum It is a value obtained by subtracting the height (lowest point height T3) from the least-squares plane L5 to the third lowest point P3 on the measurement plane A from the point height T4). The third lowest point P3 is the least squares plane L5 and the measurement surface A along the direction perpendicular to the least squares plane L5 in the area of the measurement surface A located on the adsorption surface B side with respect to the least squares plane L5. is the position at which the distance from The fourth highest point P4 is the least-squares plane L5 along the direction perpendicular to the least-squares plane L5 in the region of the measurement surface A located on the opposite side of the least-squares plane L5 to the adsorption surface B side. is the position where the distance between A and the measurement surface A is maximum. That is, LTIR consists of a plane (fourth plane L4) passing through the fourth highest point P4 and parallel to the least squares plane L5, and a plane passing through the third lowest point P3 and parallel to the least squares plane L5 (third plane L3 ).

(Manufacturing apparatus for silicon carbide epitaxial substrate)
Next, the configuration of the manufacturing apparatus for silicon carbide epitaxial substrate 200 will be described. FIG. 6 is a schematic partial cross-sectional view showing the configuration of a manufacturing apparatus for silicon carbide epitaxial substrate 200. As shown in FIG. Manufacturing apparatus 300 for silicon carbide epitaxial substrate 200 is, for example, a hot wall type horizontal CVD (Chemical Vapor Deposition) apparatus. As shown in FIG. 6, manufacturing apparatus 300 for silicon carbide epitaxial substrate 200 includes reaction chamber 201, gas supply unit 235, control unit 245, heating element 203, quartz tube 204, heat insulator (not shown). , an induction heating coil (not shown).

Heating element 203 has, for example, a cylindrical shape, and forms reaction chamber 201 therein. The heating element 203 is made of graphite, for example. The heating element 203 is provided inside the quartz tube 204 . The heat insulating material surrounds the outer circumference of the heating element 203 . The induction heating coil is wound along the outer peripheral surface of the quartz tube 204, for example. The induction heating coil is configured such that an alternating current can be supplied from an external power source (not shown). Thereby, the heating element 203 is induction-heated. As a result, reaction chamber 201 is heated by heating element 203 .

The reaction chamber 201 is a space surrounded by the inner wall surface 205 of the heating element 203 . Reaction chamber 201 is provided with a susceptor 210 that holds second silicon carbide substrate 24 . Susceptor 210 is made of silicon carbide. Second silicon carbide substrate 24 is placed on susceptor 210 . A susceptor 210 is placed on the stage 202 . The stage 202 is rotatably supported by a rotating shaft 209 . Rotation of the stage 202 causes the susceptor 210 to rotate.

Manufacturing apparatus 300 for silicon carbide epitaxial substrate 200 further has gas introduction port 207 and gas exhaust port 208 . The gas exhaust port 208 is connected to an exhaust pump (not shown). Arrows in FIG. 6 indicate gas flows. A gas is introduced into the reaction chamber 201 through a gas inlet 207 and exhausted through a gas exhaust port 208 . The pressure inside the reaction chamber 201 is adjusted by the balance between the amount of gas supplied and the amount of gas exhausted.

The gas supply unit 235 is configured to be able to supply a mixed gas containing a source gas, a dopant gas, and a carrier gas to the reaction chamber 201 . Specifically, the gas supply section 235 includes a first gas supply section 231, a second gas supply section 232, a third gas supply section 233, and a fourth gas supply section 234, for example.

The first gas supply unit 231 is configured to be able to supply a first gas containing carbon atoms, for example. The first gas supply unit 231 is, for example, a gas cylinder filled with the first gas. The first gas is, for example, propane (C ₃ H ₈ ) gas. The first gas may be, for example, methane (CH ₄ ) gas, ethane (C ₂ H ₆ ) gas, acetylene (C ₂ H ₂ ) gas, or the like.

The second gas supply unit 232 is configured to be able to supply a second gas containing, for example, silane gas. The second gas supply unit 232 is, for example, a gas cylinder filled with the second gas. The second gas is, for example, silane (SiH ₄ ) gas. The second gas may be a mixed gas of silane gas and a gas other than silane.

The third gas supply unit 233 is configured to be able to supply a third gas containing nitrogen atoms, for example. The third gas supply unit 233 is, for example, a gas cylinder filled with the third gas. A third gas is a doping gas. The third gas is ammonia gas, for example. Ammonia gas is more likely to be thermally decomposed than nitrogen gas having triple bonds.

The fourth gas supply unit 234 is configured to be able to supply a fourth gas (carrier gas) such as hydrogen. The fourth gas supply unit 234 is, for example, a gas cylinder filled with hydrogen. The fourth gas may be argon gas.

The control section 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply section 235 to the reaction chamber 201 . Specifically, the control unit 245 may include a first gas flow control unit 241, a second gas flow control unit 242, a third gas flow control unit 243, and a fourth gas flow control unit 244. good. Each controller may be, for example, an MFC (Mass Flow Controller). The control section 245 is arranged between the gas supply section 235 and the gas introduction port 207 .

(Manufacturing method of silicon carbide epitaxial substrate)
<First embodiment>
Next, a method for manufacturing silicon carbide epitaxial substrate 200 according to the first embodiment will be described. FIG. 7 is a flowchart schematically showing a method for manufacturing silicon carbide epitaxial substrate 200 according to the first embodiment. As shown in FIG. 7, the method for manufacturing silicon carbide epitaxial substrate 200 according to the first embodiment includes a step of preparing a plurality of first silicon carbide substrates 14 (S11), and a step of preparing a plurality of first silicon carbide substrates 14. the step of measuring each LTV (S12), the step of obtaining a plurality of first silicon carbide epitaxial substrates 100 (S13), and the step of measuring the LTV of each of the plurality of first silicon carbide epitaxial substrates 100 (S14). a step (S15) of determining a criterion for selecting the second silicon carbide substrate 24; a step (S16) of measuring the LTV of the second silicon carbide substrate 24; It mainly has a step (S17) of determining whether or not the conditions are satisfied, and a step (S18) of forming second silicon carbide epitaxial layer 25 on second silicon carbide substrate 24 .

First, the step (S11) of preparing a plurality of first silicon carbide substrates 14 is performed. For example, an ingot made of a silicon carbide single crystal manufactured by a sublimation method is sliced with a wire saw. Thus, a plurality of first silicon carbide substrates 14 are prepared. Each of the plurality of first silicon carbide substrates 14 is made of silicon carbide of polytype 4H, for example. Each of first silicon carbide substrates 14 contains an n-type impurity such as nitrogen. The n-type impurity concentration is, for example, 1×10 ¹⁵ cm ³ or more and 1×10 ¹⁹ cm ³ or less.

FIG. 8 is a schematic cross-sectional view showing the configuration of each of a plurality of first silicon carbide substrates 14. As shown in FIG. As shown in FIG. 8 , each of first silicon carbide substrates 14 has a fourth main surface 11 and a sixth main surface 13 . The sixth major surface 13 is opposite the fourth major surface 11 . The diameter of fourth main surface 11 is, for example, 150 mm.

Next, a step (S12) of measuring the LTV of each of a plurality of first silicon carbide substrates 14 is performed. Let the 4th main surface 11 be the attraction|suction surface B, for example. Let the 6th main surface 13 be the measurement surface A, for example. Measurement surface A of first silicon carbide substrate 14 is divided into a plurality of square regions 50 . LTV is measured in a plurality of square regions 50 . When the diameter of the measurement plane A is 150 mm, the measurement plane A is divided into 145 square regions 50 each having a side length W2 of 10 mm. LTV is measured in each of the 145 square regions 50 .

Next, it is determined whether or not the LTV value is less than the first specific value in each of the plurality of square regions 50 . The first specific value is 0.8 μm, for example. Specifically, it is determined whether or not the LTV value is less than 0.8 μm in each of the plurality of square regions 50 . Next, the area ratio (first area ratio) of the square regions whose LTV value is less than the first specific value is obtained. The first area ratio is a value obtained by dividing the number of square regions whose LTV value is less than the first specific value by the number of all square regions. For example, if the number of square regions having an LTV value of less than 0.8 μm is 135 and the total number of square regions is 145, the first area ratio is 135/145. The first specific value may be, for example, 0.7 μm or 0.6 μm.

Next, a step (S13) of obtaining a plurality of first silicon carbide epitaxial substrates 100 is performed. A plurality of first silicon carbide substrates 14 are arranged on susceptor 210 . The reaction chamber 201 is then depressurized. Specifically, the pressure in the reaction chamber 201 is reduced from the atmospheric pressure to about 1×10 ⁻⁶ Pa, for example. Next, temperature rise of the plurality of first silicon carbide substrates 14 is started. During the temperature rise, hydrogen (H ₂ ) gas, which is a carrier gas, is introduced into the reaction chamber 201 from the fourth gas supply section 234 .

A source gas, a dopant gas and a carrier gas are then supplied to the reaction chamber 201 . Specifically, a mixed gas containing, for example, silane, propane, ammonia, and hydrogen is introduced into reaction chamber 201 . Each gas is thermally decomposed in the reaction chamber 201 . The growth temperature is, for example, 1500° C. or higher and 1750° C. or lower. The mixed gas may contain argon instead of hydrogen.

The flow rate of the first gas (propane gas) is, for example, 29 sccm. The flow rate of the second gas (silane gas) is, for example, 46 sccm. The flow rate of the third gas (ammonia gas) is, for example, 1.5 sccm. The flow rate of the fourth gas (hydrogen gas or argon gas) is 100 slm, for example. The reaction chamber 201 is maintained at a pressure of, for example, 2 kPa or more and 6 kPa or less. Thereby, first silicon carbide epitaxial layer 15 is formed on each of first silicon carbide substrates 14 . Thus, first silicon carbide epitaxial substrate 100 having first silicon carbide substrate 14 and first silicon carbide epitaxial layer 15 is obtained.

FIG. 9 is a schematic cross-sectional view showing the configuration of each of a plurality of first silicon carbide epitaxial substrates 100. As shown in FIG. As shown in FIG. 9 , each of first silicon carbide epitaxial substrates 100 has a fifth main surface 12 and a fourth main surface 11 . The fifth major surface 12 is opposite the fourth major surface 11 . The sixth main surface 13 is located between the fourth main surface 11 and the fifth main surface 12 .

Next, a step (S14) of measuring the LTV of each of a plurality of first silicon carbide epitaxial substrates 100 is performed. Let the 4th main surface 11 be the attraction|suction surface B, for example. Let the 5th main surface 12 be the measurement surface A, for example. Measurement surface A of first silicon carbide epitaxial substrate 100 is divided into a plurality of square regions 50 . LTV is measured in a plurality of square regions 50 . When the diameter of the measurement plane A is 150 mm, the measurement plane A is divided into 145 square regions 50 each having a side length W2 of 10 mm. LTV is measured in each of the 145 square regions 50 .

Next, it is determined whether or not the LTV value is less than the second specific value in each of the plurality of square regions 50 . The second specific value is 1.0 μm, for example. Specifically, it is determined whether or not the LTV value is less than 1.0 μm in each of the plurality of square regions 50 . Next, the area ratio (second area ratio) of the square regions whose LTV value is less than the second specific value is obtained. The second area ratio is a value obtained by dividing the number of square regions whose LTV value is less than the second specific value by the number of all square regions. For example, if the number of square regions with an LTV value of less than 1.0 μm is 140 and the total number of square regions is 145, the second area ratio is 140/145. The second specific value may be, for example, 0.9 μm or 0.8 μm.

Next, a step (S15) of determining a criterion for selecting second silicon carbide substrate 24 is performed. Specifically, the correlation between the LTV of each of the plurality of first silicon carbide substrates 14 and the LTV of each of the plurality of first silicon carbide epitaxial substrates 100 is obtained. FIG. 10 shows a first area ratio of first silicon carbide substrate 14 (an area ratio of a region with an LTV of less than 0.8 μm) and a second area ratio of first silicon carbide epitaxial substrate 100 (with an LTV of less than 1.0 μm). FIG. 10 is a diagram showing the relationship between (area ratio of a region). The horizontal axis of FIG. 10 indicates the first area ratio (the area ratio of the region where the LTV is less than 0.8 μm) of first silicon carbide substrate 14 . The vertical axis of FIG. 10 indicates the second area ratio (the area ratio of the region having an LTV of less than 1.0 μm) of first silicon carbide epitaxial substrate 100 .

As shown in FIG. 10, when the first silicon carbide substrate 14 has a high first area ratio, the first carbonized layer obtained by forming the first silicon carbide epitaxial layer 15 on the first silicon carbide substrate 14 The second area ratio of silicon epitaxial substrate 100 tends to increase. That is, the second area ratio of first silicon carbide epitaxial substrate 100 can be predicted from the first area ratio of first silicon carbide substrate 14 . In order to improve the prediction accuracy of the second area ratio of first silicon carbide epitaxial substrate 100, it is desirable that the number of first silicon carbide substrates 14 is large. The number of first silicon carbide substrates 14 is not particularly limited, but may be, for example, 20 or more, or may be 40 or more.

Next, criteria for selecting second silicon carbide substrate 24 are determined. First, the correlation between the first area ratio of first silicon carbide substrate 14 and the second area ratio of first silicon carbide epitaxial substrate 100 is obtained. For example, linear approximation is used to obtain a correlation between the first area ratio of first silicon carbide substrate 14 and the second area ratio of first silicon carbide epitaxial substrate 100 . A criterion for selecting second silicon carbide substrate 24 may be obtained based on the linear function obtained by linear approximation.

For example, in order to obtain first silicon carbide epitaxial substrate 100 having a second area ratio of 90% or more, first silicon carbide substrate 14 may have a first area ratio of 80% or more. can. In this case, the criterion for selecting second silicon carbide substrate 24 is to satisfy the condition that the first area ratio of second silicon carbide substrate 24 is 80% or more. As described above, criteria for selecting second silicon carbide substrate 24 based on the relationship between the LTV of each of first silicon carbide substrates 14 and the LTV of each of first silicon carbide epitaxial substrates 100 is determined. The criteria for selecting second silicon carbide substrate 24 may be determined by other methods. In order to more reliably obtain first silicon carbide epitaxial substrate 100 in which first silicon carbide epitaxial substrate 100 has a second area ratio of 90% or more, the criteria for selecting second silicon carbide substrate 24 are: The condition that the first area ratio of the silicon substrate 24 is 90% or more may be satisfied.

Next, a step (S16) of measuring the LTV of second silicon carbide substrate 24 is performed. Second silicon carbide substrate 24 is different from each of first silicon carbide substrates 14 . First, second silicon carbide substrate 24 is prepared. FIG. 11 is a schematic cross-sectional view showing the configuration of second silicon carbide substrate 24 . As shown in FIG. 11 , second silicon carbide substrate 24 has a third main surface 23 and a first main surface 21 . The first major surface 21 is opposite the third major surface 23 . Next, the LTV of second silicon carbide substrate 24 is measured. Let the 1st main surface 21 be the attraction|suction surface B, for example. Let the 3rd main surface 23 be the measurement surface A, for example.

As shown in FIG. 3 , measurement surface A of second silicon carbide substrate 24 is divided into a plurality of square regions 50 . LTV is measured in a plurality of square regions 50 . When the diameter of the measurement plane A is 150 mm, the measurement plane A is divided into 145 square regions 50 each having a side length W2 of 10 mm. LTV is measured in each of the 145 square regions 50 .

Next, it is determined whether or not the LTV value is less than the first specific value in each of the plurality of square regions 50 . The first specific value is 0.8 μm, for example. Specifically, it is determined whether or not the LTV value is less than 0.8 μm in each of the plurality of square regions 50 . Next, the area ratio (first area ratio) of the square regions whose LTV value is less than the first specific value is obtained. The first area ratio is a value obtained by dividing the number of square regions whose LTV value is less than the first specific value by the number of all square regions. For example, if the number of square regions having an LTV value of less than 0.8 μm is 135 and the total number of square regions is 145, the first area ratio is 135/145.

Next, a step (S17) of determining whether or not the LTV of second silicon carbide substrate 24 satisfies the reference is performed. Specifically, it is determined whether or not the LTV of second silicon carbide substrate 24 satisfies the criteria determined in the step (S15) of determining criteria for selecting second silicon carbide substrates 24 . For example, when it is determined that the criterion for selecting second silicon carbide substrate 24 is to satisfy the condition that the first area ratio of second silicon carbide substrate 24 is 90% or more, the first area ratio is satisfied. is 90% or more, it is determined that the second silicon carbide substrate 24 satisfies the criterion. Conversely, second silicon carbide substrate 24 having a first area ratio of less than 90% is determined not to satisfy the criterion. Second silicon carbide substrate 24 that does not meet the criteria is discarded, or is subjected to polishing or the like until it meets the criteria.

Next, a step (S18) of forming second silicon carbide epitaxial layer 25 on second silicon carbide substrate 24 is performed. First, second silicon carbide substrates 24 determined to satisfy the above criteria are selected. Next, second silicon carbide epitaxial layer 25 is formed on second silicon carbide substrate 24 . The conditions for forming second silicon carbide epitaxial layer 25 in the step ( S<b>18 ) of forming second silicon carbide epitaxial layer 25 on second silicon carbide substrate 24 are the first silicon carbide epitaxial layer on first silicon carbide substrate 14 . The film formation conditions may be the same as those for forming 15 . Silicon carbide epitaxial substrate 200 is thus obtained (see FIG. 1).

<Second embodiment>
Next, a method for manufacturing silicon carbide epitaxial substrate 200 according to the second embodiment will be described. FIG. 12 is a flow chart schematically showing a method for manufacturing silicon carbide epitaxial substrate 200 according to the second embodiment. As shown in FIG. 12, the method for manufacturing silicon carbide epitaxial substrate 200 according to the second embodiment includes a step of preparing a plurality of first silicon carbide substrates 14 (S21), and a step of preparing a plurality of first silicon carbide substrates 14. a step of measuring the LTIR of each (S22), a step of obtaining a plurality of first silicon carbide epitaxial substrates 100 (S23), and a step of measuring the LTIR of each of the plurality of first silicon carbide epitaxial substrates 100 (S24); a step (S25) of determining a criterion for selecting the second silicon carbide substrate 24; a step (S26) of measuring the LTIR of the second silicon carbide substrate 24; It mainly has a step (S27) of determining whether or not the conditions are satisfied, and a step (S28) of forming second silicon carbide epitaxial layer 25 on second silicon carbide substrate 24 .

The method for manufacturing silicon carbide epitaxial substrate 200 according to the second embodiment differs from the method for manufacturing silicon carbide epitaxial substrate 200 according to the first embodiment mainly in that LTIR is measured instead of LTV, Other points are the same as the method for manufacturing silicon carbide epitaxial substrate 200 according to the second embodiment. Hereinafter, the steps different from the method for manufacturing silicon carbide epitaxial substrate 200 according to the first embodiment will be mainly described.

First, a step (S21) of preparing a plurality of first silicon carbide substrates 14 is performed. The step of preparing a plurality of first silicon carbide substrates 14 (S21) is similar to the step of preparing a plurality of first silicon carbide substrates 14 (S11).

Next, a step (S22) of measuring the LTIR of each of a plurality of first silicon carbide substrates 14 is performed. Let the 4th main surface 11 be the attraction|suction surface B, for example. Let the 6th main surface 13 be the measurement surface A, for example. As shown in FIG. 3 , measurement surface A of first silicon carbide substrate 14 is divided into a plurality of square regions 50 . LTV is measured in a plurality of square regions 50 . When the diameter of the measurement plane A is 150 mm, the measurement plane A is divided into 145 square regions 50 each having a side length W2 of 10 mm. LTV is measured in each of the 145 square regions 50 .

Next, it is determined whether or not the LTIR value is less than the first specific value in each of the plurality of square regions 50 . The first specific value is 0.8 μm, for example. Specifically, it is determined whether or not the LTIR value is less than 0.8 μm in each of the plurality of square regions 50 . Next, the area ratio (first area ratio) of the square regions whose LTIR value is less than the first specific value is obtained. The first area ratio is a value obtained by dividing the number of square regions whose LTIR value is less than the first specific value by the number of all square regions. For example, if the number of square regions with an LTIR value of less than 0.8 μm is 135 and the total number of square regions is 145, the first area ratio is 135/145. The first specific value may be, for example, 0.7 μm or 0.6 μm.

Next, a step (S23) of obtaining a plurality of first silicon carbide epitaxial substrates 100 is performed. The step of obtaining a plurality of first silicon carbide epitaxial substrates 100 (S23) is the same as the step of obtaining a plurality of first silicon carbide epitaxial substrates 100 (S13).

Next, a step (S24) of measuring the LTIR of each of a plurality of first silicon carbide epitaxial substrates 100 is performed. Let the 4th main surface 11 be the attraction|suction surface B, for example. Let the 5th main surface 12 be the measurement surface A, for example. Measurement surface A of first silicon carbide epitaxial substrate 100 is divided into a plurality of square regions 50 . LTIR is measured in a plurality of square regions 50 . When the diameter of the measurement plane A is 150 mm, the measurement plane A is divided into 145 square regions 50 each having a side length W2 of 10 mm. LTIR is measured in each of the 145 square regions 50 .

Next, it is determined whether or not the LTIR value is less than the second specific value in each of the plurality of square regions 50 . The second specific value is 1.0 μm, for example. Specifically, it is determined whether or not the LTIR value is less than 1.0 μm in each of the plurality of square regions 50 . Next, the area ratio (second area ratio) of the square regions whose LTIR value is less than the second specific value is obtained. The second area ratio is a value obtained by dividing the number of square regions whose LTIR value is less than the second specific value by the number of all square regions. For example, if the number of square regions with an LTV value of less than 1.0 μm is 140 and the total number of square regions is 145, the second area ratio is 140/145. The second specific value may be, for example, 0.9 μm or 0.8 μm.

Next, a step (S25) of determining criteria for selecting second silicon carbide substrate 24 is performed. Specifically, the correlation between the LTIR of each of the plurality of first silicon carbide substrates 14 and the LTIR of each of the plurality of first silicon carbide epitaxial substrates 100 is obtained. FIG. 13 shows a first area ratio of first silicon carbide substrate 14 (an area ratio of a region having an LTIR of less than 0.8 μm) and a second area ratio of first silicon carbide epitaxial substrate 100 (LTIR of less than 1.0 μm). FIG. 10 is a diagram showing the relationship between (area ratio of a region). The horizontal axis of FIG. 13 indicates the first area ratio (the area ratio of the region where LTIR is less than 0.8 μm) of first silicon carbide substrate 14 . The vertical axis of FIG. 13 indicates the second area ratio (the area ratio of the region where the LTIR is less than 1.0 μm) of first silicon carbide epitaxial substrate 100 .

As shown in FIG. 13, when the first silicon carbide substrate 14 has a high first area ratio, the first carbonization obtained by forming the first silicon carbide epitaxial layer 15 on the first silicon carbide substrate 14 The second area ratio of silicon epitaxial substrate 100 tends to increase. That is, the second area ratio of first silicon carbide epitaxial substrate 100 can be predicted from the first area ratio of first silicon carbide substrate 14 .

For example, in order to obtain first silicon carbide epitaxial substrate 100 having a second area ratio of 90% or more with high probability, first silicon carbide substrate 14 has a first area ratio of 90% or more. can do. In this case, the criterion for selecting second silicon carbide substrate 24 is to satisfy the condition that the first area ratio of second silicon carbide substrate 24 is 90% or more. As described above, based on the relationship between the LTIR of each of the plurality of first silicon carbide substrates 14 and the LTIR of each of the plurality of first silicon carbide epitaxial substrates 100, the criteria for selecting the second silicon carbide substrates 24. is determined.

Next, a step (S26) of measuring the LTIR of second silicon carbide substrate 24 is performed. Second silicon carbide substrate 24 is different from each of first silicon carbide substrates 14 . First, second silicon carbide substrate 24 is prepared. Measurement surface A of second silicon carbide substrate 24 is divided into a plurality of square regions 50 . LTIR is measured in a plurality of square regions 50 . When the diameter of the measurement plane A is 150 mm, the measurement plane A is divided into 145 square regions 50 each having a side length W2 of 10 mm. LTIR is measured in each of the 145 square regions 50 .

Next, it is determined whether or not the LTIR value is less than the first specific value in each of the plurality of square regions 50 . The first specific value is 0.8 μm, for example. Specifically, it is determined whether or not the LTIR value is less than 0.8 μm in each of the plurality of square regions 50 . Next, the area ratio (first area ratio) of the square regions whose LTIR value is less than the first specific value is obtained. The first area ratio is a value obtained by dividing the number of square regions whose LTIR value is less than the first specific value by the number of all square regions. For example, if the number of square regions with an LTIR value of less than 0.8 μm is 135 and the total number of square regions is 145, the first area ratio is 135/145.

Next, a step (S27) of determining whether or not the LTIR of second silicon carbide substrate 24 satisfies the reference is performed. Specifically, it is determined whether or not the LTIR of second silicon carbide substrate 24 satisfies the criteria determined in the step (S25) of determining criteria for selecting second silicon carbide substrates 24 . For example, when it is determined that the criterion for selecting second silicon carbide substrate 24 is to satisfy the condition that the first area ratio of second silicon carbide substrate 24 is 90% or more, the first area ratio is satisfied. is 90% or more, it is determined that the second silicon carbide substrate 24 satisfies the criterion. Conversely, second silicon carbide substrate 24 having a first area ratio of less than 90% is determined not to satisfy the criterion. Second silicon carbide substrate 24 that does not meet the criteria is discarded, or is subjected to polishing or the like until it meets the criteria.

Next, a step (S28) of forming second silicon carbide epitaxial layer 25 on second silicon carbide substrate 24 is performed. The step of forming second silicon carbide epitaxial layer 25 on second silicon carbide substrate 24 (S28) is the same as the step of forming second silicon carbide epitaxial layer 25 on second silicon carbide substrate 24 (S18). .

(Manufacturing method of silicon carbide semiconductor device)
Next, a method for manufacturing silicon carbide semiconductor device 400 according to the present embodiment will be described. FIG. 14 is a flow chart schematically showing a method for manufacturing silicon carbide semiconductor device 400 according to the present embodiment. As shown in FIG. 14, the method for manufacturing a silicon carbide semiconductor device 400 according to the present embodiment mainly includes a step of preparing a silicon carbide epitaxial substrate (S1) and a step of processing the silicon carbide epitaxial substrate (S2). have in

First, a step (S1) of preparing a silicon carbide epitaxial substrate is performed. In the step of preparing a silicon carbide epitaxial substrate (S1), silicon carbide epitaxial substrate 200 manufactured by the method for manufacturing silicon carbide epitaxial substrate 200 according to the present embodiment is obtained (see FIG. 2).

Next, the step (S2) of processing the silicon carbide epitaxial substrate is performed. Specifically, silicon carbide epitaxial substrate 200 is processed as follows. First, ion implantation is performed on silicon carbide epitaxial substrate 200 . Specifically, ion-implanted regions such as body region 113 are formed in second silicon carbide epitaxial layer 25 .

FIG. 15 is a schematic cross-sectional view showing the step of forming the body region. Specifically, a p-type impurity such as aluminum is ion-implanted into second main surface 22 of second silicon carbide epitaxial layer 25 . Thereby, body region 113 having p-type conductivity is formed. A portion of second silicon carbide epitaxial layer 25 where body region 113 is not formed serves as drift region 121 . The thickness of body region 113 is, for example, 0.9 μm.

Next, a step of forming a source region is performed. FIG. 16 is a schematic cross-sectional view showing a step of forming a source region. Specifically, an n-type impurity such as phosphorus is ion-implanted into body region 113 . Thereby, the source region 114 having n-type conductivity is formed. The thickness of source region 114 is, for example, 0.4 μm. The concentration of n-type impurities contained in source region 114 is higher than the concentration of p-type impurities contained in body region 113 .

Next, contact region 118 is formed by ion-implanting a p-type impurity such as aluminum into source region 114 . Contact region 118 is formed through source region 114 and body region 113 and in contact with drift region 121 . The concentration of p-type impurities contained in contact region 118 is higher than the concentration of n-type impurities contained in source region 114 .

Activation annealing is then performed to activate the ion-implanted impurities. The temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example about 1700°C. The activation annealing time is, for example, about 30 minutes. The atmosphere for activation annealing is preferably an inert gas atmosphere, such as an argon atmosphere.

Next, a step of forming a trench in second main surface 22 of second silicon carbide epitaxial layer 25 is performed. FIG. 17 is a schematic cross-sectional view showing a step of forming trenches in second main surface 22 of second silicon carbide epitaxial layer 25 . A mask 17 having an opening is formed on second main surface 22 comprising source region 114 and contact region 118 . Using mask 17, source region 114, body region 113 and part of drift region 121 are etched away. As an etching method, for example, reactive ion etching, especially inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reactive gas can be used. A concave portion is formed in the second main surface 22 by etching.

A thermal etch is then performed in the recess. Thermal etching can be performed with mask 17 formed on second main surface 22, for example, by heating in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one halogen atom includes at least one of chlorine (Cl) and fluorine (F) atoms. The atmosphere includes, for example, _Cl2 , _BCl3 , _SF6 or _CF4 . For example, a mixed gas of chlorine gas and oxygen gas is used as a reaction gas, and thermal etching is performed at a heat treatment temperature of, for example, 700° C. or higher and 1000° C. or lower. Note that the reaction gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas described above. Nitrogen gas, argon gas, or helium gas, for example, can be used as the carrier gas.

As shown in FIG. 17, trenches 56 are formed in the second major surface 22 by thermal etching. Trench 56 is defined by sidewall surfaces 53 and bottom wall surfaces 54 . Sidewall surface 53 is formed of source region 114 , body region 113 and drift region 121 . Bottom wall surface 54 is configured by drift region 121 . Mask 17 is then removed from second major surface 22 .

Next, a step of forming a gate insulating film is performed. FIG. 18 is a schematic cross-sectional view showing a step of forming a gate insulating film. Specifically, silicon carbide epitaxial substrate 200 having trenches 56 formed in second main surface 22 is heated, for example, at a temperature of 1300° C. or more and 1400° C. or less in an atmosphere containing oxygen. Thus, bottom wall surface 54 is in contact with drift region 121 , side wall surface 53 is in contact with drift region 121 , body region 113 and source region 114 , and second main surface 22 is in contact with source region 114 and contact region 118 . A contacting gate insulating film 115 is formed.

Next, a step of forming a gate electrode is performed. FIG. 19 is a schematic cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. Gate electrode 27 is formed in contact with gate insulating film 115 inside trench 56 . Gate electrode 27 is arranged inside trench 56 and formed on gate insulating film 115 so as to face each of sidewall surface 53 and bottom wall surface 54 of trench 56 . Gate electrode 27 is formed, for example, by LPCVD (Low Pressure Chemical Vapor Deposition).

Next, an interlayer insulating film is formed. Interlayer insulating film 26 is formed to cover gate electrode 27 and to be in contact with gate insulating film 115 . Interlayer insulating film 26 is formed by chemical vapor deposition, for example. Interlayer insulating film 26 is made of a material containing, for example, silicon dioxide. Next, portions of interlayer insulating film 26 and gate insulating film 115 are etched so that openings are formed over source region 114 and contact region 118 . Thereby, contact region 118 and source region 114 are exposed from gate insulating film 115 .

Next, a step of forming a source electrode is performed. Source electrode 16 is formed in contact with each of source region 114 and contact region 118 . Source electrode 16 is formed by sputtering, for example. Source electrode 16 is made of a material containing, for example, Ti (titanium), Al (aluminum) and Si (silicon).

An alloying anneal is then performed. Specifically, source electrode 16 in contact with each of source region 114 and contact region 118 is held at a temperature of 900° C. or higher and 1100° C. or lower, for example, for about 5 minutes. As a result, at least part of the source electrode 16 is silicided. As a result, source electrode 16 is formed in ohmic contact with source region 114 . Preferably, source electrode 16 makes an ohmic contact with contact region 118 .

Next, source wiring 19 is formed. Source wiring 19 is electrically connected to source electrode 16 . Source wiring 19 is formed to cover source electrode 16 and interlayer insulating film 26 .

Next, a step of forming a drain electrode is performed. First, second silicon carbide substrate 24 is polished on first main surface 21 . Thereby, the thickness of second silicon carbide substrate 24 is reduced. Next, a drain electrode 123 is formed. Drain electrode 123 is formed in contact with first main surface 21 . As described above, silicon carbide semiconductor device 400 according to the present embodiment is manufactured.

FIG. 20 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to this embodiment. Silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Silicon carbide semiconductor device 400 mainly includes silicon carbide epitaxial substrate 200 , gate electrode 27 , gate insulating film 115 , source electrode 16 , drain electrode 123 , source interconnection 19 , and interlayer insulating film 26 . ing. Silicon carbide epitaxial substrate 200 has drift region 121 , body region 113 , source region 114 and contact region 118 . Silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like.

Next, the effects of the method for manufacturing silicon carbide epitaxial substrate 200 and the method for manufacturing silicon carbide semiconductor device 400 according to the present disclosure will be described.

When the silicon carbide epitaxial substrate has low flatness, exposure failure (defocus) may occur in an exposure step of manufacturing a silicon carbide semiconductor device using the silicon carbide epitaxial substrate. If the proportion of regions in which exposure failure occurs is high among the plurality of exposure regions on the silicon carbide epitaxial substrate, the yield of silicon carbide semiconductor devices is significantly reduced. Therefore, it is necessary to rework the silicon carbide epitaxial substrate, which has a high rate of exposure failure, to improve the flatness of the silicon carbide epitaxial substrate. Specifically, for example, the silicon carbide epitaxial layer is removed from the silicon carbide epitaxial substrate, and then the silicon carbide substrate is again subjected to planarization such as polishing. In this case, the lead time of the manufacturing process of the silicon carbide semiconductor device is significantly lengthened.

According to the method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure, based on the relationship between the LTV of each of first silicon carbide substrates 14 and the LTV of each of first silicon carbide epitaxial substrates 100, a plurality of A criterion for selecting second silicon carbide substrates 24 different from each of first silicon carbide substrates 14 is determined. By using the reference, the LTV of the second silicon carbide epitaxial substrate can be accurately predicted based on the LTV of the second silicon carbide substrate 24 .

Further, according to the method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure, the LTV of second silicon carbide substrate 24 is measured. It is determined whether or not the LTV of the second silicon carbide substrate 24 satisfies the standard. As a result, even when the LTV of second silicon carbide substrate 24 does not meet the standard, second silicon carbide substrate 24 is quickly polished or the like without removing second silicon carbide epitaxial layer 25 . Thus, the flatness of second silicon carbide substrate 24 can be enhanced. Therefore, it is possible to prevent the lead time of the manufacturing process of the silicon carbide semiconductor device from becoming significantly longer.

Furthermore, according to the method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure, second silicon carbide epitaxial layer 25 is formed on second silicon carbide substrate 24 that satisfies the standard for LTV. Therefore, silicon carbide epitaxial substrates with high flatness can be selected with high accuracy. As a result, the probability of exposure failure occurring in the manufacturing process of the silicon carbide semiconductor device can be reduced.

According to the method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure, based on the relationship between the LTIR of each of first silicon carbide substrates 14 and the LTIR of each of first silicon carbide epitaxial substrates 100, a plurality of A criterion for selecting second silicon carbide substrates 24 different from each of first silicon carbide substrates 14 is determined. By using the reference, the LTIR of the second silicon carbide epitaxial substrate can be accurately predicted based on the LTIR of the second silicon carbide substrate 24 .

Further, according to the method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure, the LTIR of second silicon carbide substrate 24 is measured. It is determined whether the LTIR of the second silicon carbide substrate 24 satisfies the criteria. Thereby, even if the LTIR of the second silicon carbide substrate 24 does not satisfy the standard, the second silicon carbide substrate 24 can be quickly polished or the like without removing the second silicon carbide epitaxial layer 25 . Thus, the flatness of second silicon carbide substrate 24 can be improved. Therefore, it is possible to prevent the lead time of the manufacturing process of the silicon carbide semiconductor device from becoming significantly longer.

Furthermore, according to the method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure, second silicon carbide epitaxial layer 25 is formed on second silicon carbide substrate 24 that satisfies the criteria for LTIR. Therefore, silicon carbide epitaxial substrates with high flatness can be selected with high accuracy. As a result, the probability of exposure failure occurring in the manufacturing process of the silicon carbide semiconductor device can be reduced.

The embodiments disclosed this time are illustrative in all respects and should be considered not restrictive. The scope of the present invention is indicated by the scope of the claims rather than the above-described embodiments and examples, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

7 orientation flat 8 arcuate portion 9 outer peripheral side surface 11 fourth main surface 12 fifth main surface 13 sixth main surface 14 first silicon carbide substrate 15 first silicon carbide epitaxial layer 16 source electrode 17 mask 19 source wiring 21 first main surface Surface 22 Second main surface 23 Third main surface 24 Second silicon carbide substrate 25 Second silicon carbide epitaxial layer 26 Interlayer insulating film 27 Gate electrode 50 Square region 53 Side wall surface 54 Bottom wall surface 56 Trench 100 First silicon carbide epitaxial substrate 101 First direction 102 Second direction 113 Body region 114 Source region 115 Gate insulating film 118 Contact region 121 Drift region 123 Drain electrode 200 Silicon carbide epitaxial substrate 201 Reaction chamber 202 Stage 203 Heating element 204 Quartz tube 205 Inner wall surface 207 Gas introduction port 208 Gas exhaust port 209 Rotary shaft 210 Susceptor 231 First gas supply unit 232 Second gas supply unit 233 Third gas supply unit 234 Fourth gas supply unit 235 Gas supply unit 241 First gas flow control unit 242 Second gas flow control unit 243 Third gas flow control unit 244 Fourth gas flow control unit 245 Control unit 300 Manufacturing apparatus 400 Silicon carbide semiconductor device A Measurement surface B Adsorption surface L1 First plane L2 Second plane L3 Third plane L4 Fourth plane L5 Least square Plane P1 First lowest point P2 First highest point P3 Third lowest point P4 Fourth highest point T1 First height T2 Second height T3 Lowest point height T4 Highest point height W1 First width W2 Length

Claims (7)

preparing a plurality of first silicon carbide substrates;
measuring the LTV of each of the plurality of first silicon carbide substrates;
obtaining a plurality of first silicon carbide epitaxial substrates by forming a first silicon carbide epitaxial layer on each of the plurality of first silicon carbide substrates;
measuring the LTV of each of the plurality of first silicon carbide epitaxial substrates;
second silicon carbide different from each of the plurality of first silicon carbide substrates based on the relationship between the LTV of each of the plurality of first silicon carbide substrates and the LTV of each of the plurality of first silicon carbide epitaxial substrates determining criteria for sorting the substrates;
measuring the LTV of the second silicon carbide substrate;
determining whether the LTV of the second silicon carbide substrate satisfies the standard;
and forming a second silicon carbide epitaxial layer on the second silicon carbide substrate satisfying the criteria. The plurality of first silicon carbide substrates have main surfaces in contact with the first silicon carbide epitaxial layers,
The main surface is divided into a plurality of square areas,
The length of one side of each of the plurality of square regions is 10 mm,
In the step of measuring the LTV of each of the plurality of first silicon carbide substrates, LTV is measured in each of the plurality of square regions,
2. The method of manufacturing a silicon carbide epitaxial substrate according to claim 1, wherein in the step of measuring the LTV of each of said plurality of first silicon carbide epitaxial substrates, LTV is measured in each of said plurality of square regions. In the step of determining whether the LTV of the second silicon carbide substrate satisfies the standard, if the area ratio of the regions having an LTV of less than 1.0 μm in each of the plurality of square regions is 90% or more, 3. The method for manufacturing a silicon carbide epitaxial substrate according to claim 2, wherein it is determined that the LTV of the second silicon carbide substrate satisfies the criterion. preparing a plurality of first silicon carbide substrates;
measuring the LTIR of each of the plurality of first silicon carbide substrates;
obtaining a plurality of first silicon carbide epitaxial substrates by forming a first silicon carbide epitaxial layer on each of the plurality of first silicon carbide substrates;
measuring the LTIR of each of the plurality of first silicon carbide epitaxial substrates;
a second silicon carbide different from each of the plurality of first silicon carbide substrates based on the relationship between the LTIR of each of the plurality of first silicon carbide substrates and the LTIR of each of the plurality of first silicon carbide epitaxial substrates; determining criteria for sorting the substrates;
measuring the LTIR of the second silicon carbide substrate;
determining whether the LTIR of the second silicon carbide substrate satisfies the criteria;
and forming a second silicon carbide epitaxial layer on the second silicon carbide substrate satisfying the criteria. The plurality of first silicon carbide substrates have main surfaces in contact with the first silicon carbide epitaxial layers,
The main surface is divided into a plurality of square areas,
The length of one side of each of the plurality of square regions is 10 mm,
In the step of measuring the LTIR of each of the plurality of first silicon carbide substrates, the LTIR is measured in each of the plurality of square regions,
5. The method of manufacturing a silicon carbide epitaxial substrate according to claim 4, wherein in the step of measuring the LTIR of each of said plurality of first silicon carbide epitaxial substrates, LTIR is measured in each of said plurality of square regions. In the step of determining whether the LTIR of the second silicon carbide substrate satisfies the criterion, if the area ratio of the regions having the LTIR of less than 1.0 μm in each of the plurality of square regions is 90% or more, 6. The method of manufacturing a silicon carbide epitaxial substrate according to claim 5, wherein it is determined that the LTIR of the second silicon carbide substrate satisfies the criterion. preparing a silicon carbide epitaxial substrate manufactured by the method for manufacturing a silicon carbide epitaxial substrate according to any one of claims 1 to 6;
and processing the silicon carbide epitaxial substrate.

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