WO2024031742A1 - 基于动态零点跟随补偿的环路高稳定ldo电路及方法 - Google Patents

基于动态零点跟随补偿的环路高稳定ldo电路及方法 Download PDF

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WO2024031742A1
WO2024031742A1 PCT/CN2022/114424 CN2022114424W WO2024031742A1 WO 2024031742 A1 WO2024031742 A1 WO 2024031742A1 CN 2022114424 W CN2022114424 W CN 2022114424W WO 2024031742 A1 WO2024031742 A1 WO 2024031742A1
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terminal
pmos tube
load
tube
dynamic
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PCT/CN2022/114424
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English (en)
French (fr)
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陈炳杰
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北京同芯科技有限公司
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • the invention proposes a loop highly stable LDO circuit and method based on dynamic zero point following compensation, and belongs to the field of circuit electronics technology.
  • LDO Low-dropout regulator
  • the indicators for evaluating LDO are divided into: 1), static-state specification; 2), dynamic performance indicator (dynamic-state specification), and 3), high-frequency characteristics (high-frequency specification), loop stability It is a static performance indicator.
  • LDO loop compensation many compensation methods are used in LDO loop compensation, such as frequency compensation method using cascode-Miller, frequency compensation method using Damping-Factor-Control, and frequency compensation method using Load-Dependent Zero mobile compensation.
  • dynamic zero following compensation (Load-Dependent Zero Mobile Compensation, LZMC) is widely used in the loop stability design of LDO due to its simple structure.
  • Dynamic zero point following compensation can generate zero points that change with the load at the on-chip nodes, making the entire LDO loop stable.
  • dynamic zero following compensation has a good loop stability compensation effect; however, when the load changes significantly, it often causes the LDO output voltage to produce unrecoverable oscillations, and the output voltage Unrecoverable oscillation occurs in most LDOs, which also limits the load response capability of the LDO circuit.
  • the present invention provides a loop highly stable LDO circuit and method based on dynamic zero point following compensation, which can always maintain loop stability and improve load response capability when the load undergoes large and drastic changes based on dynamic zero point following compensation. It is safe and reliable to solve the problem of unrecoverable oscillation of LDO output voltage in traditional LDO circuits in the existing technology.
  • the technical solutions adopted are as follows:
  • a loop highly stable LDO circuit based on dynamic zero point following compensation includes an LDO circuit body based on dynamic zero point following compensation.
  • the LDO circuit body includes a PMOS tube MP6 for following load changes;
  • the dynamic resistance multiplication circuit adapted and connected to the PMOS tube MP6, for the load adapted and connected to the LDO circuit body represents the change of the load according to the source-drain voltage difference between the source terminal of the PMOS tube MP6 and the drain terminal of the PMOS tube MP6. state, when the change state of the represented load matches the preset load change threshold in the dynamic resistance multiplication circuit, the dynamic resistance multiplication circuit generates a dynamically adjusted resistance in parallel with the PMOS tube MP6 according to the load change state.
  • the dynamic adjustment resistor is connected in parallel with the resistor followed by the PMOS transistor MP6 to form a load equivalent resistance, wherein the formed load equivalent resistance is smaller than the equivalent resistance maximum value of the PMOS transistor MP6 in the loop stable state, so that The high-frequency pole frequency of the LDO circuit body is greater than the unity gain frequency of the LDO circuit body.
  • the PMOS transistor MP6 when the source-drain voltage difference indicates that the changing state of the load is less than the preset load changing threshold in the dynamic resistance multiplier circuit, the PMOS transistor MP6 is in the linear operating area, and the dynamic resistance multiplier circuit generates a dynamic adjustment of a high resistance state according to the load changing state. Resistor; the dynamic resistance multiplier circuit generates a high-resistance state and the resistance value of the dynamically adjusted resistor is much greater than the linear zone resistance value of the PMOS tube MP6 when it is in the linear working zone.
  • the dynamic resistance multiplication circuit includes an NMOS transistor MN4.
  • the gate terminal of the NMOS transistor MN4 forms the input terminal Input of the dynamic resistance multiplication circuit.
  • the input terminal Input of the dynamic resistance multiplication circuit is adaptively connected to the drain terminal of the PMOS tube MP6. ;
  • the source terminal of NMOS tube MN4 is connected to the positive terminal of current source I0 and the first terminal of resistor R0.
  • the negative terminal of current source I0 is grounded or floating.
  • the drain terminal of NMOS tube MN1 is connected to the input voltage VIN and the positive terminal of current source I1.
  • the first terminal of resistor R3, the source terminal of PMOS tube MP10 and the source terminal of PMOS tube MP11 are connected;
  • the negative terminal of the current source I1 is connected to the second terminal of the resistor R0 and the gate terminal of the PMOS tube MP7.
  • the source terminal of the PMOS tube MP7 is connected to the second terminal of the resistor R3.
  • the drain terminal of the PMOS tube MP7 is connected to the drain terminal of the PMOS tube MP8.
  • the gate terminal of PMOS tube MP8 and the gate terminal of PMOS tube MP9 are connected, the source terminal of PMOS tube MP8 and the source terminal of PMOS tube MP9 are both grounded, the drain terminal of PMOS tube MP9 is connected with the drain terminal of PMOS tube MP10 and the drain terminal of PMOS tube MP10.
  • the gate terminal is connected to the gate terminal of PMOS tube MP11.
  • the drain terminal of PMOS tube MP11 forms the output terminal Output of the dynamic resistance multiplication circuit, and the output terminal Output of the dynamic resistance multiplication circuit is adaptively connected to the drain terminal of PMOS tube MP6.
  • the preset load change threshold is I1*R0.
  • the source-drain voltage difference is greater than or equal to I1*R0.
  • the LDO circuit body includes a compensation capacitor Cc connected to the drain terminal of the PMOS tube MP6.
  • One end of the compensation capacitor Cc is connected to the dynamic resistance multiplication circuit and the drain terminal of the PMOS tube MP6.
  • the other end of the compensation capacitor Cc is connected to the main operational amplifier.
  • the output terminal of OPA and the input terminal of buffer Buffer are connected;
  • the gate terminal of PMOS tube MP6 is connected to the gate terminal of PMOS tube MP5, the drain terminal of PMOS tube MP5, the positive terminal of bias current source IBIAS and the drain terminal of NMOS tube MN3.
  • the negative terminal of bias current source IBIAS and NMOS tube MN3 are connected.
  • the source terminals are all grounded;
  • the gate terminal of NMOS tube MN3 is connected to the gate terminal of NMOS tube MN1, the gate terminal of NMOS tube MN2, the drain terminal of NMOS tube MN2 and the drain terminal of PMOS tube MP3.
  • the source terminal of NMOS tube MN2 and the source terminal of NMOS tube MN1 are both connected. Ground; the drain terminal of NMOS tube MN1 is connected to the drain terminal of PMOS tube MP4, the gate terminal of PMOS tube MP4 and the gate terminal of PMOS tube MP3;
  • the source terminal of PMOS tube MP3 is connected to the drain terminal of PMOS tube MP2.
  • the source terminal of PMOS tube MP4 is connected to the drain terminal of PMOS tube MP1 and the first terminal of resistor R1.
  • the source terminal of PMOS tube MP4 and the first terminal of PMOS tube MP1 are connected.
  • the drain terminal and the first terminal of the resistor R1 are connected to each other to form the output terminal VOUT of the LDO circuit body;
  • the second terminal of the resistor R2 is connected to the non-inverting terminal of the main operational amplifier OPA and one terminal of the resistor R2, and the other terminal of the resistor R2 is connected to ground;
  • the output terminal of the buffer Buffer is connected to the gate terminal of the PMOS tube MP2 and the gate terminal of the PMOS tube MP1, and the inverting terminal of the main operational amplifier OPA is connected to the reference voltage VREF.
  • a method for a highly stable LDO circuit based on a dynamic zero point following compensation loop which provides an LDO circuit body based on dynamic zero point following compensation.
  • the LDO circuit body includes a PMOS tube MP6 for following load changes, and is provided with the PMOS tube MP6
  • the adaptively connected dynamic resistance multiplication circuit for the load that is adaptively connected to the LDO circuit body, represents the changing state of the load according to the source-drain voltage difference between the source terminal of the PMOS tube MP6 and the drain terminal of the PMOS tube MP6.
  • the dynamic resistance multiplier circuit When the represented load When the change state matches the preset load change threshold in the dynamic resistance multiplier circuit, the dynamic resistance multiplier circuit generates a dynamic adjustment resistor in parallel with the PMOS transistor MP6 according to the load change state;
  • the dynamic adjustment resistor is connected in parallel with the resistor followed by the PMOS transistor MP6 to form a load equivalent resistance, wherein the formed load equivalent resistance is smaller than the equivalent resistance maximum value of the PMOS transistor MP6 in the loop stable state, so that The high-frequency pole frequency of the LDO circuit body is greater than the unity gain frequency of the LDO circuit body.
  • the PMOS transistor MP6 when the source-drain voltage difference indicates that the changing state of the load is less than the preset load changing threshold in the dynamic resistance multiplier circuit, the PMOS transistor MP6 is in the linear operating area, and the dynamic resistance multiplier circuit generates a dynamic adjustment of a high resistance state according to the load changing state. resistance;
  • the dynamic resistance multiplier circuit generates a high-resistance state and the resistance value of the dynamically adjusted resistor is much greater than the resistance value of the PMOS tube MP6 in the linear region when it is in the linear operating region.
  • the dynamic resistance multiplication circuit includes an NMOS transistor MN4.
  • the gate terminal of the NMOS transistor MN4 forms the input terminal Input of the dynamic resistance multiplication circuit.
  • the input terminal Input of the dynamic resistance multiplication circuit is adaptively connected to the drain terminal of the PMOS tube MP6. ;
  • the source terminal of NMOS tube MN4 is connected to the positive terminal of current source I0 and the first terminal of resistor R0.
  • the negative terminal of current source I0 is grounded or floating.
  • the drain terminal of NMOS tube MN1 is connected to the input voltage VIN and the positive terminal of current source I1.
  • the first terminal of resistor R3, the source terminal of PMOS tube MP10 and the source terminal of PMOS tube MP11 are connected;
  • the negative terminal of the current source I1 is connected to the second terminal of the resistor R0 and the gate terminal of the PMOS tube MP7.
  • the source terminal of the PMOS tube MP7 is connected to the second terminal of the resistor R3.
  • the drain terminal of the PMOS tube MP7 is connected to the drain terminal of the PMOS tube MP8.
  • the gate terminal of PMOS tube MP8 and the gate terminal of PMOS tube MP9 are connected, the source terminal of PMOS tube MP8 and the source terminal of PMOS tube MP9 are both grounded, the drain terminal of PMOS tube MP9 is connected with the drain terminal of PMOS tube MP10 and the drain terminal of PMOS tube MP10.
  • the gate terminal is connected to the gate terminal of PMOS tube MP11.
  • the drain terminal of PMOS tube MP11 forms the output terminal Output of the dynamic resistance multiplication circuit, and the output terminal Output of the dynamic resistance multiplication circuit is adaptively connected to the drain terminal of PMOS tube MP6.
  • the preset load change threshold is I1*R0.
  • the source-drain voltage difference is greater than or equal to I1*R0.
  • the LDO circuit body includes a compensation capacitor Cc connected to the drain terminal of the PMOS tube MP6.
  • One end of the compensation capacitor Cc is connected to the dynamic resistance multiplication circuit and the drain terminal of the PMOS tube MP6.
  • the other end of the compensation capacitor Cc is connected to the main operational amplifier.
  • the output terminal of OPA and the input terminal of buffer Buffer are connected;
  • the gate terminal of PMOS tube MP6 is connected to the gate terminal of PMOS tube MP5, the drain terminal of PMOS tube MP5, the positive terminal of bias current source IBIAS and the drain terminal of NMOS tube MN3.
  • the negative terminal of bias current source IBIAS and NMOS tube MN3 are connected.
  • the source terminals are all grounded;
  • the gate terminal of NMOS tube MN3 is connected to the gate terminal of NMOS tube MN1, the gate terminal of NMOS tube MN2, the drain terminal of NMOS tube MN2 and the drain terminal of PMOS tube MP3.
  • the source terminal of NMOS tube MN2 and the source terminal of NMOS tube MN1 are both connected. Ground; the drain terminal of NMOS tube MN1 is connected to the drain terminal of PMOS tube MP4, the gate terminal of PMOS tube MP4 and the gate terminal of PMOS tube MP3;
  • the source terminal of PMOS tube MP3 is connected to the drain terminal of PMOS tube MP2.
  • the source terminal of PMOS tube MP4 is connected to the drain terminal of PMOS tube MP1 and the first terminal of resistor R1.
  • the source terminal of PMOS tube MP4 and the first terminal of PMOS tube MP1 are connected.
  • the drain terminal and the first terminal of the resistor R1 are connected to each other to form the output terminal VOUT of the LDO circuit body;
  • the second terminal of the resistor R2 is connected to the non-inverting terminal of the main operational amplifier OPA and one terminal of the resistor R2, and the other terminal of the resistor R2 is connected to ground;
  • the output terminal of the buffer Buffer is connected to the gate terminal of the PMOS tube MP2 and the gate terminal of the PMOS tube MP1, and the inverting terminal of the main operational amplifier OPA is connected to the reference voltage VREF.
  • the present invention proposes a loop highly stable LDO circuit and method based on dynamic zero point following compensation.
  • a dynamic resistance multiplier circuit is used to generate a voltage in parallel with the PMOS tube MP6 according to the load change state.
  • Dynamically adjusted resistor the dynamically adjusted resistor is connected in parallel with the resistor followed by PMOS tube MP6 to form a load equivalent resistance.
  • the formed load equivalent resistance is smaller than the maximum equivalent resistance of PMOS tube MP6 in the loop stable state. So that the high-frequency pole frequency of the LDO circuit body is greater than the unity gain frequency of the LDO circuit body.
  • the dynamic adjustment resistor of the dynamic resistance multiplication circuit When the load is stable, the dynamic adjustment resistor of the dynamic resistance multiplication circuit is in a high-resistance state.
  • the dynamic resistance multiplication circuit produces a high-resistance state.
  • the resistance value of the dynamic adjustment resistor is much greater than the resistance value of the linear area when the PMOS tube MP6 is in the linear working area. It will not It affects the working state of the existing LDO circuit body based on dynamic zero point following compensation, that is, it can always maintain the loop stability of the LDO circuit body, improve the load response capability, and be safe and reliable.
  • Figure 1 is a frequency diagram of the LDO circuit body when the load is large or changes drastically;
  • Figure 2 is a frequency diagram of the LDO circuit body when the load is constant or the conversion is small
  • FIG. 3 is a circuit schematic diagram of the LDO circuit of the present invention.
  • Figure 4 is a circuit schematic diagram of the dynamic resistance multiplication circuit of the present invention.
  • the present invention includes an LDO circuit body based on dynamic zero following compensation, so
  • the LDO circuit body includes a PMOS transistor MP6 used to follow load changes;
  • the dynamic resistance multiplication circuit adaptively connected to the PMOS tube MP6.
  • the load adapted to be connected to the LDO circuit body is characterized according to the source-drain voltage difference between the source terminal of the PMOS tube MP6 and the drain terminal of the PMOS tube MP6.
  • the changing state of the load When the changing state of the represented load matches the preset load changing threshold in the dynamic resistance multiplication circuit, the dynamic resistance multiplication circuit generates a dynamically adjusted resistance in parallel with the PMOS transistor MP6 according to the changing state of the load;
  • the dynamic adjustment resistor is connected in parallel with the resistor followed by the PMOS transistor MP6 to form a load equivalent resistance, wherein the formed load equivalent resistance is smaller than the equivalent resistance maximum value of the PMOS transistor MP6 in the loop stable state, so that The high-frequency pole frequency of the LDO circuit body is greater than the unity gain frequency of the LDO circuit body.
  • the LDO circuit body is a loop compensation form that adopts dynamic zero following compensation.
  • the specific situation of the LDO circuit using dynamic zero following compensation to form the LDO circuit body is consistent with the existing situation. Specifically, it is a loop compensation that can form dynamic zero following compensation. shall prevail. From the above description, it can be seen that for the LDO circuit body based on dynamic zero point following compensation, when the load changes greatly or drastically, the loop will be unstable.
  • the LDO circuit body based on dynamic zero point following compensation generally includes a PMOS tube for following the load transformation, which is the PMOS tube MP6 in Figure 3.
  • the PMOS tube MP6 is used to act as a resistor and follows the change of the load.
  • the PMOS tube MP6 is used to follow the load change.
  • Figure 1 shows the frequency diagram of the LDO circuit body based on dynamic zero-point following compensation when the load does not change or changes slightly.
  • the abscissa is the frequency (unit is Hz), and the ordinate is the gain (20lg
  • , unit is dB), ⁇ is the angular frequency, the relationship between the angular frequency ⁇ and the frequency f is: 2 ⁇ *f ⁇ , the unit of the frequency f is Hz (Hertz).
  • p 1 is the main pole of the LDO circuit body
  • p 2 is the secondary pole of the LDO circuit body
  • z1 is the zero point of the LDO circuit body
  • p 3 is the high-frequency pole of the LDO circuit body.
  • the main pole p 1 , the secondary pole p 2 , the high-frequency pole p 3 and the zero point z1 are all related to the configuration parameters of the LDO circuit body.
  • the main pole p 1 of the LDO circuit body based on dynamic zero point following compensation , sub-pole p 2 , high-frequency pole p 3 , and zero point z 1 , the specific corresponding relationships, determination methods and processes are consistent with the existing ones.
  • C 1 is the equivalent capacitance of the LDO circuit body.
  • the specific situation of the equivalent capacitance C 1 of the LDO circuit body is consistent with the existing one.
  • the equivalent capacitance C 1 is the equivalent parasitic capacitance between the output terminal of the main transport amplifier OPA and the input node of the buffer Buffer.
  • the corresponding frequency f p3 of the LDO circuit body can be determined according to the angular frequency ⁇ p3 of the high-frequency pole p 3 .
  • the LDO circuit body also has a corresponding unity-gain frequency, that is, the unity-gain frequency in Figures 1 and 2; when the load is stable, those skilled in the art know that the PMOS tube MP6 is in the linear operating area , at this time, the resistance value followed by PMOS tube MP6 and acting as a resistor is: R MP6-linear ; and the frequency f p3 of the high-frequency pole p3 is greater than the unity gain frequency f unity-gain , as shown in Figure 2.
  • the PMOS transistor MP6 which follows the load change and acts as a resistor, is difficult to maintain in the linear region. Instead, it will enter the saturation region. Then, the resistance of the resistor acted by the PMOS transistor MP6 changes from the linear region resistance R MP6-linear changes to the saturation zone resistance R MP6_sat . Since the resistance value R MP6_sat in the saturation region is greater than the resistance value R MP6-linear in the linear region, it will cause the frequency f p3 of the high-frequency pole p3 to move from outside the unity-gain frequency to within the unity-gain frequency f unity-gain , ultimately leading to the loss of loop stability, as shown in Figure 1.
  • the working range of the PMOS transistor MP6 in the LDO circuit body will change, which will lead to corresponding changes in the frequency and angular frequency of the LDO circuit body.
  • the LDO circuit body's When the frequency does not meet the zero-pole distribution stability conditions of the LDO circuit, the LDO circuit body will produce unrecoverable oscillation problems.
  • a dynamic resistance multiplication circuit adaptively connected to the PMOS transistor MP6 is configured.
  • the change state of the load is represented according to the source-drain voltage difference between the source terminal of the PMOS transistor MP6 and the drain terminal of the PMOS transistor MP6.
  • the changing state of the load represented by the source-drain voltage difference matches the preset load changing threshold in the dynamic resistance multiplier circuit, specifically it means that the load is in a large or drastically changing state based on the source-drain voltage difference of the PMOS tube MP6.
  • the source-drain voltage difference is greater than or equal to the preset load change threshold.
  • the dynamic resistance multiplication circuit generates a dynamically adjusted resistance in parallel with the PMOS transistor MP6 according to the load change state.
  • the dynamic adjustment resistance is connected in parallel with the resistance followed by the PMOS tube MP6 to form a load equivalent resistance, wherein the formed load equivalent resistance is smaller than the PMOS tube MP6 in the loop.
  • the maximum value of the equivalent resistance in the stable state of the circuit is such that the high-frequency pole frequency of the LDO circuit body is greater than the unity gain frequency of the LDO circuit body.
  • the equivalent resistance maximum value of the PMOS tube MP6 in the loop stable state specifically refers to the equivalent resistance value corresponding to the PMOS tube MP6 when the angular frequency of the LDO circuit body is the unit gain angular frequency.
  • the maximum equivalent resistance value R MP6 (max) of PMOS tube MP6 is: f unity-gain is the unit gain frequency corresponding to the unit gain angular frequency. Therefore, for a certain LDO circuit body, the equivalent resistance maximum value R MP6 (max) of PMOS tube MP6 in the loop stable state can be specifically determined.
  • the angular frequency ⁇ p3 of the high-frequency pole p 3 is:
  • R Equal_mos is the load equivalent resistance.
  • the load equivalent resistance R Equal_mos is less than the equivalent resistance maximum value R MP6 (max) of the PMOS tube MP6 in the loop stable state, then the angular frequency ⁇ of the high-frequency pole p 3 p3 is greater than the unit gain angular frequency, and the high-frequency pole frequency f p3 of the LDO circuit body is greater than the unit gain frequency f unity-gain of the LDO circuit body.
  • the PMOS transistor MP6 when the source-drain voltage difference indicates that the changing state of the load is less than the preset load changing threshold in the dynamic resistance multiplier circuit, the PMOS transistor MP6 is in the linear operating area, and the dynamic resistance multiplier circuit generates a dynamic adjustment of a high resistance state according to the load changing state. resistance;
  • the dynamic resistance multiplier circuit generates a high-resistance state and the resistance value of the dynamically adjusted resistor is much greater than the resistance value of the PMOS tube MP6 in the linear region when it is in the linear operating region.
  • the source-drain voltage difference indicates that the changing state of the load is less than the preset load changing threshold in the dynamic resistance multiplication circuit
  • the PMOS tube MP6 It is in the linear operating area, and the dynamic resistance multiplication circuit generates a dynamically adjusted resistance in a high-resistance state according to the load change state. If the load does not change or the change is small, it means the load is stable as mentioned above.
  • the current resistance value of the dynamic adjustment resistor is much greater than the linear area resistance R MP6-linear of the PMOS tube MP6 when it is in the linear working area, and the dynamic adjustment resistor is in a high-resistance state.
  • R MP6-linear is connected in parallel. According to the characteristics of resistors in parallel, the currently formed load equivalent resistance is smaller than and close to the linear zone resistance R MP6-linear . Since the load equivalent resistance R Equal_mos is in the linear working zone with the PMOS tube MP6 The linear region resistance value R MP6 is close to linear , which means it will not affect the working status of the existing LDO circuit body based on dynamic zero point following compensation.
  • the dynamic resistance multiplier circuit when the load changes greatly or drastically, the dynamic resistance multiplier circuit generates a dynamic adjustment resistor in parallel with the PMOS tube MP6 according to the load change state; the dynamic adjustment resistor is connected in parallel with the resistor that the PMOS tube MP6 follows.
  • the load equivalent resistance R Equal_mos is formed, where the formed load equivalent resistance R Equal_mos is smaller than the equivalent resistance maximum value R MP6(max) of the PMOS transistor MP6 in the loop stable state, so that the LDO circuit body
  • the high-frequency pole frequency f p3 is greater than the unity gain frequency f unity-gain of the LDO circuit body.
  • the dynamic adjustment resistor of the dynamic resistance multiplication circuit When the load is stable, the dynamic adjustment resistor of the dynamic resistance multiplication circuit is in a high-resistance state.
  • the dynamic resistance multiplication circuit produces a high-resistance state.
  • the resistance value of the dynamic adjustment resistor is much greater than the linear area resistance value of PMOS tube MP6 when it is in the linear working area.
  • the load equivalent resistance R Equal_mos is close to the linear zone resistance R MP6-linear when the PMOS tube MP6 is in the linear working zone. It will not affect the working state of the existing LDO circuit body based on dynamic zero point following compensation, that is, the LDO can always be maintained.
  • the loop stability of the circuit body improves the load response capability and is safe and reliable.
  • the LDO circuit body includes a compensation capacitor Cc connected to the drain terminal of PMOS tube MP6.
  • the compensation capacitor Cc One end is connected to the drain end of the dynamic resistance multiplication circuit and PMOS tube MP6, and the other end of the compensation capacitor Cc is connected to the output end of the main operational amplifier OPA and the input end of the buffer Buffer;
  • the gate terminal of PMOS tube MP6 is connected to the gate terminal of PMOS tube MP5, the drain terminal of PMOS tube MP5, the positive terminal of bias current source IBIAS and the drain terminal of NMOS tube MN3.
  • the negative terminal of bias current source IBIAS and NMOS tube MN3 are connected.
  • the source terminals are all grounded;
  • the gate terminal of NMOS tube MN3 is connected to the gate terminal of NMOS tube MN1, the gate terminal of NMOS tube MN2, the drain terminal of NMOS tube MN2 and the drain terminal of PMOS tube MP3.
  • the source terminal of NMOS tube MN2 and the source terminal of NMOS tube MN1 are both connected. Ground; the drain terminal of NMOS tube MN1 is connected to the drain terminal of PMOS tube MP4, the gate terminal of PMOS tube MP4 and the gate terminal of PMOS tube MP3;
  • the source terminal of PMOS tube MP3 is connected to the drain terminal of PMOS tube MP2.
  • the source terminal of PMOS tube MP4 is connected to the drain terminal of PMOS tube MP1 and the first terminal of resistor R1.
  • the source terminal of PMOS tube MP4 and the first terminal of PMOS tube MP1 are connected.
  • the drain terminal and the first terminal of the resistor R1 are connected to each other to form the output terminal VOUT of the LDO circuit body;
  • the second terminal of the resistor R2 is connected to the non-inverting terminal of the main operational amplifier OPA and one terminal of the resistor R2, and the other terminal of the resistor R2 is connected to ground;
  • the output terminal of the buffer Buffer is connected to the gate terminal of the PMOS tube MP2 and the gate terminal of the PMOS tube MP1, and the inverting terminal of the main operational amplifier OPA is connected to the reference voltage VREF.
  • the specific conditions of the main operational amplifier OPA, the buffer Buffer, and the reference voltage VREF can all be consistent with the existing ones.
  • the specific implementation of the loop supplement based on zero-point dynamic following compensation is consistent with the existing conditions. Here No longer.
  • R MP6 (ideal) is the ideal load equivalent resistance
  • (W/L) MP6 is the width-to-length ratio of the conductive channel of PMOS tube MP5
  • (W/L) MP6 is the width-to-length ratio of the conductive channel of PMOS tube MP6
  • ⁇ p is the average mobility of PMOS tube MP6
  • ⁇ is the shunt ratio
  • the shunt ratio ⁇ is the current of PMOS tube MP5 divided by the current on PMOS tube MP1
  • C ox is the gate oxide layer capacitance of PMOS tube MP6
  • IL is PMOS
  • the current on the MP1 tube is the load current.
  • the state of large load change means that the load changes greatly or drastically. For specific conditions, please refer to the above description.
  • the load equivalent resistance R Equal_mos that changes with the load is also R parallel //R MP6 .
  • the corresponding equivalent resistance of PMOS tube MP6 is R MP6-linear .
  • R Equal_mos (R parallel //R MP6_sat ) ⁇ R MP6 (max) .
  • the diode connected in parallel can meet the above requirements, when the diode is used in parallel with the PMOS transistor MP6, when the load changes greatly and the instantaneous required voltage drop is greater than the diode conduction voltage drop, the output point voltage of the main operational amplifier OPA will occur.
  • the clamp does not drop as much as it should at each voltage, resulting in unsatisfactory transient response. For example, when the load suddenly becomes much larger, the output voltage of the diode-parallel PMOS transistor MP6 will have a large spike.
  • the dynamic resistance multiplication circuit of the present invention includes an NMOS transistor MN4.
  • the gate terminal of the NMOS transistor MN4 forms the input terminal Input of the dynamic resistance multiplication circuit.
  • the input terminal Input is adaptively connected to the drain terminal of PMOS tube MP6;
  • the source terminal of NMOS tube MN4 is connected to the positive terminal of current source I0 and the first terminal of resistor R0.
  • the negative terminal of current source I0 is grounded or floating.
  • the drain terminal of NMOS tube MN1 is connected to the input voltage VIN and the positive terminal of current source I1.
  • the first terminal of resistor R3, the source terminal of PMOS tube MP10 and the source terminal of PMOS tube MP11 are connected;
  • the negative terminal of the current source I1 is connected to the second terminal of the resistor R0 and the gate terminal of the PMOS tube MP7.
  • the source terminal of the PMOS tube MP7 is connected to the second terminal of the resistor R3.
  • the drain terminal of the PMOS tube MP7 is connected to the drain terminal of the PMOS tube MP8.
  • the gate terminal of PMOS tube MP8 and the gate terminal of PMOS tube MP9 are connected, the source terminal of PMOS tube MP8 and the source terminal of PMOS tube MP9 are both grounded, the drain terminal of PMOS tube MP9 is connected with the drain terminal of PMOS tube MP10 and the drain terminal of PMOS tube MP10.
  • the gate terminal is connected to the gate terminal of PMOS tube MP11.
  • the drain terminal of PMOS tube MP11 forms the output terminal Output of the dynamic resistance multiplication circuit, and the output terminal Output of the dynamic resistance multiplication circuit is adaptively connected to the drain terminal of PMOS tube MP6.
  • the preset load change threshold is I1*R0.
  • the source-drain voltage difference is greater than or equal to I1*R0.
  • the floating ground means that the relative level is at a low level and the absolute potential is not 0. The floating ground situation is consistent with the existing situation and will not be described in detail here.
  • the dynamic resistance multiplier circuit is a circuit with voltage input and current output.
  • the condition for the dynamic resistance multiplier circuit to output current is: V 3 -V 2 ⁇
  • V 2 is the voltage loaded to the gate terminal of PMOS tube MP7 in Figure 4
  • is the threshold voltage of PMOS tube MP7 in Figure 4
  • V 2 V 1 -V thn +I1*R0
  • V 1 is the voltage loaded to the gate terminal of NMOS transistor MN4
  • V thn is the threshold voltage of NMOS transistor MN4, and I1 is the current value of current source I1.
  • ⁇ I1*R0 V thn -
  • the output terminal Output of the dynamic resistance multiplication circuit has no output current.
  • the output terminal Output of the dynamic resistance multiplier circuit will generate an output current.
  • the voltage difference VIN-V 1 across the PMOS tube MP6 is set to ⁇ V.
  • (W/L) MP9 is the width-to-length ratio of the conductive channel of PMOS tube MP9
  • (W/L) MP8 is the width-to-length ratio of the conductive channel of PMOS tube MP8
  • (W/L) MP11 is the conductive channel of PMOS tube MP11
  • the width-to-length ratio, (W/L) MP10 is the width-to-length ratio of the conductive channel of PMOS tube MP10, is the amplification factor ⁇ of resistor R3, and ⁇ can be adjusted in the design to satisfy ⁇ R3 ⁇ R MP6(max) .
  • 0.27R MP6(max) ⁇ R3 ⁇ 0.53R MP6(max) .
  • the stability compensation of the loop can be completed at the minimum cost without affecting the resistance that changes with the load when the load is stable.
  • the load equivalent resistance R Equal_mos is smaller than the maximum equivalent resistance R MP6 (max) of the PMOS transistor MP6 in the loop stable state to ensure the loop stability of the LDO circuit itself.
  • a high-stability loop method based on dynamic zero-point following compensation LDO circuit can be obtained.
  • an LDO circuit body based on dynamic zero-point following compensation is provided.
  • the LDO circuit body includes a PMOS transistor MP6 for following load changes;
  • a dynamic resistance multiplication circuit that is adaptively connected to the PMOS tube MP6.
  • the load is characterized according to the source-drain voltage difference between the source terminal of the PMOS tube MP6 and the drain terminal of the PMOS tube MP6.
  • the changing state of the load when the changing state of the represented load matches the preset load changing threshold in the dynamic resistance multiplication circuit, the dynamic resistance doubling circuit generates a dynamically adjusted resistance in parallel with the PMOS tube MP6 according to the load changing state;
  • the dynamic adjustment resistor is connected in parallel with the resistor followed by the PMOS transistor MP6 to form a load equivalent resistance, wherein the formed load equivalent resistance is smaller than the equivalent resistance maximum value of the PMOS transistor MP6 in the loop stable state, so that The high-frequency pole frequency of the LDO circuit body is greater than the unity gain frequency of the LDO circuit body.
  • the PMOS tube MP6 When the source-drain voltage difference indicates that the changing state of the load is less than the preset load changing threshold in the dynamic resistance multiplier circuit, the PMOS tube MP6 is in the linear operating area, and the dynamic resistance multiplier circuit generates a dynamically adjusted resistor in a high-resistance state according to the load changing state;
  • the dynamic resistance multiplier circuit generates a high-resistance state and the resistance value of the dynamically adjusted resistor is much greater than the resistance value of the PMOS tube MP6 in the linear region when it is in the linear operating region.
  • the above description can be referred to for the LDO circuit body, PMOS tube MP6, dynamic resistance multiplication circuit, source-drain voltage difference of PMOS tube MP6, etc.
  • the specific adjustment method and process to ensure the loop stability of the LDO circuit body can be referred to The above description will not be described in detail here.

Abstract

本发明提出了基于动态零点跟随补偿的环路高稳定LDO电路及方法。其包括基于动态零点跟随补偿的LDO电路本体，LDO电路本体包括PMOS管MP6；还包括与所述PMOS管MP6适配连接的动态电阻倍增电路，动态电阻倍增电路根据负载变化状态产生与所述PMOS管MP6并联的动态调节电阻；所述动态调节电阻与PMOS管MP6所跟随充当的电阻并联形成负载等效电阻，其中，所形成的负载等效电阻小于PMOS管MP6在环路稳定状态下的等效电阻极大值，以使得所述LDO电路本体的高频极点频率大于LDO电路本体的单位增益频率。本发明采用基于动态零点跟随补偿且负载发生较大剧烈变化时，能始终保持环路稳定性，提高负载响应能力。

Description

基于动态零点跟随补偿的环路高稳定LDO电路及方法 技术领域
本发明提出了基于动态零点跟随补偿的环路高稳定LDO电路及方法，属于电路电子技术领域。
背景技术
LDO(Low-dropout regulator)被广泛运用在移动设备，工业控制以及汽车之上。评测LDO的指标分为：1)、静态性能指标(static-state specification)；2)、动态性能指标(dynamic-state specification)以及3)、高频特性(high-frequency specification)，环路稳定性属于静态性能指标。
目前，许多的补偿方法都被用在LDO的环路补偿上，例如通过采用cascode-Miller的频率补偿方法，运用Damping-Factor-Control的频率补偿方法以及运用Load-Dependent Zero mobile compensation的频率补偿方法，其中，动态零点跟随补偿(Load-Dependent Zero Mobile Compensation、LZMC)由于简洁的结构被广泛应用在LDO的环路稳定性设计上。
动态零点跟随补偿可以在片内结点产生随负载变化的零点，使得整个LDO环路达到稳定的目的。在实际应用中，在负载变化较小的时，动态零点跟随补偿具有良好的环路稳定补偿效果；但在负载发生较大变化时，往往会导致LDO输出电压产生不可恢复的震荡，且输出电压产生不可恢复振荡的情况存在大多数的LDO上，这也限制了LDO电路的负载响应能力。
发明内容
本发明提供了一种基于动态零点跟随补偿的环路高稳定LDO电路及方法，其在基于动态零点跟随补偿且负载发生较大剧烈变化时，能始终保持环路稳定性，提高负载响应能力，安全可靠用以解决，用以解决现有技术中传统LDO电路存在LDO输出电压产生不可恢复的震荡的问题，所采取的技术方案如下：
一种基于动态零点跟随补偿的环路高稳定LDO电路，所述环路高稳定LDO电路包括基于动态零点跟随补偿的LDO电路本体，所述LDO电路本体包括用于跟随负载变化的PMOS管MP6；所述PMOS管MP6适配连接的动态电阻倍增电路，对适配连接至所述LDO电路本体的负载，根据PMOS管MP6源极端与所述PMOS管MP6漏极端的源漏电压差表征负载的变化状态，当所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，动态电阻倍增电路根据负载变化状态产生与所述PMOS管MP6并联的动态调节电阻。
所述动态调节电阻与PMOS管MP6所跟随充当的电阻并联形成负载等效电阻，其中，所形成的负载等效电阻小于PMOS管MP6在环路稳定状态下的等效电阻极大值，以使得所 述LDO电路本体的高频极点频率大于LDO电路本体的单位增益频率。
进一步地，源漏电压差表征负载的变化状态小于动态电阻倍增电路内预设负载变化阈值时，PMOS管MP6处于线性工作区，且动态电阻倍增电路根据负载变化状态产生呈高阻状态的动态调节电阻；动态电阻倍增电路产生高阻状态动态调节电阻的阻值远大于PMOS管MP6处于线性工作区时的线性区阻值。
进一步地，所述动态电阻倍增电路包括NMOS管MN4，所述NMOS管MN4的栅极端形成动态电阻倍增电路的输入端Input，动态电阻倍增电路的输入端Input与PMOS管MP6的漏极端适配连接；
NMOS管MN4的源极端与电流源I0的正极端以及电阻R0的第一端连接，电流源I0的负极端接地或浮地，NMOS管MN1的漏极端与输入电压VIN、电流源I1的正极端、电阻R3的第一端、PMOS管MP10的源极端以及PMOS管MP11的源极端连接；
电流源I1的负极端与电阻R0的第二端、PMOS管MP7的栅极端连接，PMOS管MP7的源极端与电阻R3的第二端连接，PMOS管MP7的漏极端与PMOS管MP8的漏极端、PMOS管MP8的栅极端以及PMOS管MP9的栅极端连接，PMOS管MP8的源极端以及PMOS管MP9的源极端均接地，PMOS管MP9的漏极端与PMOS管MP10的漏极端、PMOS管MP10的栅极端以及PMOS管MP11的栅极端连接，PMOS管MP11的漏极端形成动态电阻倍增电路的输出端Output，且所述动态电阻倍增电路的输出端Output与PMOS管MP6的漏极端适配连接。
进一步地，预设负载变化阈值为I1*R0，所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，源漏电压差大于等于I1*R0。
进一步地，所述LDO电路本体包括与PMOS管MP6漏极端连接的补偿电容Cc，补偿电容Cc的一端与动态电阻倍增电路、PMOS管MP6的漏极端连接，补偿电容Cc的另一端与主运算放大器OPA的输出端以及缓冲器Buffer的输入端连接；
PMOS管MP6的栅极端与PMOS管MP5的栅极端、PMOS管MP5的漏极端、偏置电流源IBIAS的正极端以及NMOS管MN3的漏极端连接，偏置电流源IBIAS的负极端以及NMOS管MN3的源极端均接地；
NMOS管MN3的栅极端与NMOS管MN1的栅极端、NMOS管MN2的栅极端、NMOS管MN2的漏极端以及PMOS管MP3的漏极端连接，NMOS管MN2的源极端以及NMOS管MN1的源极端均接地；NMOS管MN1的漏极端与PMOS管MP4的漏极端、PMOS管MP4的栅极端以及PMOS管MP3的栅极端连接；
PMOS管MP3的源极端与PMOS管MP2的漏极端连接，PMOS管MP4的源极端与PMOS管MP1的漏极端、电阻R1的第一端连接，其中，PMOS管MP4的源极端、PMOS管MP1的漏极端以及电阻R1的第一端相互连接后形成LDO电路本体的输出端VOUT；电阻R2的第二端与主运算放大器OPA的同相端以及电阻R2的一端连接，电阻R2的另一端接地；
缓冲器Buffer的输出端与PMOS管MP2的栅极端以及PMOS管MP1的栅极端连接，所述主运算放大器OPA的反相端接参考电压VREF。
一种基于动态零点跟随补偿环路高稳定LDO电路的方法，提供基于动态零点跟随补偿的LDO电路本体，所述LDO电路本体包括用于跟随负载变化的PMOS管MP6，提供与所述PMOS管MP6适配连接的动态电阻倍增电路，对适配连接至所述LDO电路本体的负载，根据PMOS管MP6源极端与所述PMOS管MP6漏极端的源漏电压差表征负载的变化状态，当所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，动态电阻倍增电路根据负载变化状态产生与所述PMOS管MP6并联的动态调节电阻；
所述动态调节电阻与PMOS管MP6所跟随充当的电阻并联形成负载等效电阻，其中，所形成的负载等效电阻小于PMOS管MP6在环路稳定状态下的等效电阻极大值，以使得所述LDO电路本体的高频极点频率大于LDO电路本体的单位增益频率。
进一步地，源漏电压差表征负载的变化状态小于动态电阻倍增电路内预设负载变化阈值时，PMOS管MP6处于线性工作区，且动态电阻倍增电路根据负载变化状态产生呈高阻状态的动态调节电阻；
动态电阻倍增电路产生高阻状态动态调节电阻的阻值远大于PMOS管MP6处于线性工作区时的线性区阻值。
进一步地，所述动态电阻倍增电路包括NMOS管MN4，所述NMOS管MN4的栅极端形成动态电阻倍增电路的输入端Input，动态电阻倍增电路的输入端Input与PMOS管MP6的漏极端适配连接；
NMOS管MN4的源极端与电流源I0的正极端以及电阻R0的第一端连接，电流源I0的负极端接地或浮地，NMOS管MN1的漏极端与输入电压VIN、电流源I1的正极端、电阻R3的第一端、PMOS管MP10的源极端以及PMOS管MP11的源极端连接；
电流源I1的负极端与电阻R0的第二端、PMOS管MP7的栅极端连接，PMOS管MP7的源极端与电阻R3的第二端连接，PMOS管MP7的漏极端与PMOS管MP8的漏极端、PMOS管MP8的栅极端以及PMOS管MP9的栅极端连接，PMOS管MP8的源极端以及PMOS管MP9的源极端均接地，PMOS管MP9的漏极端与PMOS管MP10的漏极端、PMOS管MP10 的栅极端以及PMOS管MP11的栅极端连接，PMOS管MP11的漏极端形成动态电阻倍增电路的输出端Output，且所述动态电阻倍增电路的输出端Output与PMOS管MP6的漏极端适配连接。
进一步地，预设负载变化阈值为I1*R0，所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，源漏电压差大于等于I1*R0。
进一步地，所述LDO电路本体包括与PMOS管MP6漏极端连接的补偿电容Cc，补偿电容Cc的一端与动态电阻倍增电路、PMOS管MP6的漏极端连接，补偿电容Cc的另一端与主运算放大器OPA的输出端以及缓冲器Buffer的输入端连接；
PMOS管MP6的栅极端与PMOS管MP5的栅极端、PMOS管MP5的漏极端、偏置电流源IBIAS的正极端以及NMOS管MN3的漏极端连接，偏置电流源IBIAS的负极端以及NMOS管MN3的源极端均接地；
NMOS管MN3的栅极端与NMOS管MN1的栅极端、NMOS管MN2的栅极端、NMOS管MN2的漏极端以及PMOS管MP3的漏极端连接，NMOS管MN2的源极端以及NMOS管MN1的源极端均接地；NMOS管MN1的漏极端与PMOS管MP4的漏极端、PMOS管MP4的栅极端以及PMOS管MP3的栅极端连接；
PMOS管MP3的源极端与PMOS管MP2的漏极端连接，PMOS管MP4的源极端与PMOS管MP1的漏极端、电阻R1的第一端连接，其中，PMOS管MP4的源极端、PMOS管MP1的漏极端以及电阻R1的第一端相互连接后形成LDO电路本体的输出端VOUT；电阻R2的第二端与主运算放大器OPA的同相端以及电阻R2的一端连接，电阻R2的另一端接地；
缓冲器Buffer的输出端与PMOS管MP2的栅极端以及PMOS管MP1的栅极端连接，所述主运算放大器OPA的反相端接参考电压VREF。
本发明有益效果：
本发明提出的一种基于动态零点跟随补偿的环路高稳定LDO电路及方法，在当负载较大变化或剧烈变化时，通过动态电阻倍增电路根据负载变化状态产生与所述PMOS管MP6并联的动态调节电阻；动态调节电阻与PMOS管MP6所跟随充当的电阻并联形成负载等效电阻，其中，所形成的负载等效电阻小于PMOS管MP6在环路稳定状态下的等效电阻极大值，以使得所述LDO电路本体的高频极点频率大于LDO电路本体的单位增益频率。
当负载稳定时，动态电阻倍增电路的动态调节电阻呈高阻状态，动态电阻倍增电路产生高阻状态动态调节电阻的阻值远大于PMOS管MP6处于线性工作区时的线性区阻值，不会 影响现有基于动态零点跟随补偿的LDO电路本体的工作状态，即能始终保持LDO电路本体的环路稳定性，提高负载响应能力，安全可靠。
附图说明
图1为负载较大或剧烈变化LDO电路本体的频率示意图；
图2为负载不变或变换较小时时LDO电路本体的频率示意图；
图3为本发明LDO电路的电路原理图；
图4为本发明动态电阻倍增电路的电路原理图。
具体实施方式
以下结合附图对本发明的优选实施例进行说明，应当理解，此处所描述的优选实施例仅用于说明和解释本发明，并不用于限定本发明。
如图3所示：在采用基于动态零点跟随补偿且负载发生较大剧烈变化时，为了能始终保持环路稳定性，提高负载响应能力，本发明包括基于动态零点跟随补偿的LDO电路本体，所述LDO电路本体包括用于跟随负载变化的PMOS管MP6；
还包括与所述PMOS管MP6适配连接的动态电阻倍增电路，对适配连接至所述LDO电路本体的负载，根据PMOS管MP6源极端与所述PMOS管MP6漏极端的源漏电压差表征负载的变化状态，当所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，动态电阻倍增电路根据负载变化状态产生与所述PMOS管MP6并联的动态调节电阻；
所述动态调节电阻与PMOS管MP6所跟随充当的电阻并联形成负载等效电阻，其中，所形成的负载等效电阻小于PMOS管MP6在环路稳定状态下的等效电阻极大值，以使得所述LDO电路本体的高频极点频率大于LDO电路本体的单位增益频率。
具体地，LDO电路本体为采用动态零点跟随补偿的环路补偿形式，LDO电路采用动态零点跟随补偿形成LDO电路本体的具体情况与现有相一致，具体以能形成动态零点跟随补偿的环路补偿为准。由上述说明可知，对基于动态零点跟随补偿的LDO电路本体，当负载发生较大变化或剧烈变化时，会导致环路不稳定。
对基于动态零点跟随补偿的LDO电路本体，一般均包括用于跟随负载变换的PMOS管，即为图3中的PMOS管MP6，利用PMOS管MP6充当电阻，并跟随负载的变化，利用PMOS管MP6跟随基于动态零点跟随补偿的LDO电路本体负载变化的情况与现有相一致，为本技术领域人员所熟知，此处不再赘述。
图1中，示出了基于动态零点跟随补偿的LDO电路本体在负载不变化或处于较小变化时频率示意图，其中，横坐标为频率(单位为Hz)，纵坐标为增益(20lg|L(jω)|，单位为dB)， ω为角频率，角频率ω与频率f之间的关系为：2π*f＝ω，频率f的单位为Hz(赫兹)。p 1为LDO电路本体的主极点，p 2为LDO电路本体的次极点，z1为LDO电路本体的零点，p 3为LDO电路本体的高频极点。对一LDO电路本体，主极点p 1、次极点p 2、高频极点p 3、零点z1均与所述LDO电路本体的配置参数相关，基于动态零点跟随补偿的LDO电路本体的主极点p 1、次极点p 2、高频极点p 3、零点z 1具体对应关系、确定方式以及过程均与现有相一致。
对LDO电路本体高频极点p 3的频率为f p3，则有：2π*f p3＝ω p3，一般地，高频极点p 3的角频率ω p3为
Figure PCTCN2022114424-appb-000001
R MP6为PMOS管MP6跟随负载变化时的电阻，C 1为LDO电路本体的等效电容，LDO电路本体的等效电容C 1的具体情况与现有相一致，如对于图3中的电路，等效电容C 1为主运输放大器OPA的输出端与缓冲器Buffer输入结点之间的等效寄生电容。因此，根据高频极点p 3的角频率ω p3可确定LDO电路本体相应的频率f p3。此外，LDO电路本体还存在一相应的单位增益频率，即图1和图2中的unity-gain frequency(单位增益频率)；当负载稳定时，本技术领域人员可知，PMOS管MP6处于线性工作区，此时，PMOS管MP6所跟随并充当电阻的阻值为：R MP6-linear；且高频极点p3的频率f p3大于单位增益频率f unity-gain，如图2所示。
在负载产生较大或者剧烈变化时，跟随负载变化且充当电阻的PMOS管MP6很难维持在线性区，而是会进入饱和区，进而PMOS管MP6所充当电阻的阻值由线性区阻值R MP6-linear变为了饱和区阻值R MP6_sat。由于饱和区阻值R MP6_sat大于线性区阻值R MP6-linear，即会导致高频极点p3的频率f p3由在单位增益频率(unity-gain frequency)外移动到单位增益频率f unity-gain内，最终导致了环路的稳定性丧失，如图1所示。
因此，在负载产生较大或者剧烈变化时，会导致LDO电路本体内PMOS管MP6的工作区间发生变化，进而导致LDO电路本体的频率与角频率进行相应的变化，当负载变化后LDO电路本体的频率不满足LDO电路的零极点分布稳定条件时，LDO电路本体即产生不可恢复的震荡问题。
为了避免环路稳定性丧失，本发明实施例中，配置一与PMOS管MP6适配连接的动态电阻倍增电路。具体地，利用PMOS管MP6跟随LDO电路本体的负载变化时，根据PMOS管MP6源极端与所述PMOS管MP6漏极端的源漏电压差表征负载的变化状态。源漏电压差所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，具体是指根据PMOS管MP6的源漏电压差确定负载处于较大或剧烈变化的状态，一般地，源漏电压差大于等于预设负载变化阈值，此时，动态电阻倍增电路根据负载变化状态产生与所述PMOS管 MP6并联的动态调节电阻。
具体实施时，动态电阻倍增电路产生动态调节电阻后，所述动态调节电阻与PMOS管MP6所跟随充当的电阻并联形成负载等效电阻，其中，所形成的负载等效电阻小于PMOS管MP6在环路稳定状态下的等效电阻极大值，以使得所述LDO电路本体的高频极点频率大于LDO电路本体的单位增益频率。
本发明实施例中，PMOS管MP6在环路稳定状态下的等效电阻极大值，具体是指LDO电路本体的角频率为单位增益角频率时，通过PMOS管MP6所对应的等效电阻值，具体地，PMOS管MP6等效电阻极大值R MP6(max)为：
Figure PCTCN2022114424-appb-000002
f unity-gain为与单位增益角频率对应的单位增益频率。因此，对于一确定的LDO电路本体，PMOS管MP6在环路稳定状态下的等效电阻极大值R MP6(max)可具体确定得到。
由上述零极点分布稳定条件可知，所形成的负载等效电阻小于PMOS管MP6在环路稳定状态下的等效电阻极大值后，高频极点p 3的角频率ω p3为
Figure PCTCN2022114424-appb-000003
R Equal_mos即为负载等效电阻，当负载等效电阻R Equal_mos小于PMOS管MP6在环路稳定状态下的等效电阻极大值R MP6(max)后，则高频极点p 3的角频率ω p3大于单位增益角频率，LDO电路本体的高频极点频率f p3大于LDO电路本体的单位增益频率f unity-gain。
综上且结合图1和图2可知，所形成的负载等效电阻R Equal_mos小于PMOS管MP6在环路稳定状态下的等效电阻极大值R MP6(max)，以使得所述LDO电路本体的高频极点频率f p3大于LDO电路本体的单位增益频率f unity-gain后，即可满足基于动态零点跟随补偿的LDO电路本体的稳定条件，负载发生较大剧烈变化时，能始终保持环路稳定性，避免发生不可恢复振荡的情况，提高负载响应能力。
进一步地，源漏电压差表征负载的变化状态小于动态电阻倍增电路内预设负载变化阈值时，PMOS管MP6处于线性工作区，且动态电阻倍增电路根据负载变化状态产生呈高阻状态的动态调节电阻；
动态电阻倍增电路产生高阻状态动态调节电阻的阻值远大于PMOS管MP6处于线性工作区时的线性区阻值。
本发明实施例中，源漏电压差表征负载的变化状态小于动态电阻倍增电路内预设负载变化阈值时，即表明连接至LDO电路本体的负载未变化或变化较小，此时，PMOS管MP6处于线性工作区，且动态电阻倍增电路根据负载变化状态产生呈高阻状态的动态调节电阻。负 载未变化或变化较小，即为上述中的负载稳定。
动态调节电阻呈高阻状态时，则当前动态调节电阻的阻值远大于PMOS管MP6处于线性工作区时的线性区阻值R MP6-linear，则呈高阻的动态调节电阻与线性区阻值R MP6-linear并联，根据电阻并联的特性可知，当前所形成的负载等效电阻小于且接近线性区阻值R MP6-linear，由于负载等效电阻R Equal_mos与PMOS管MP6处于线性工作区时的线性区阻值R MP6-linear接近，即不会影响现有基于动态零点跟随补偿的LDO电路本体的工作状态。
综上，当负载较大变化或剧烈变化时，通过动态电阻倍增电路根据负载变化状态产生与所述PMOS管MP6并联的动态调节电阻；所述动态调节电阻与PMOS管MP6所跟随充当的电阻并联形成负载等效电阻R Equal_mos，其中，所形成的负载等效电阻R Equal_mos小于PMOS管MP6在环路稳定状态下的等效电阻极大值R MP6(max)，以使得所述LDO电路本体的高频极点频率f p3大于LDO电路本体的单位增益频率f unity-gain。
当负载稳定时，则动态电阻倍增电路的动态调节电阻呈高阻状态，动态电阻倍增电路产生高阻状态动态调节电阻的阻值远大于PMOS管MP6处于线性工作区时的线性区阻值，相应的负载等效电阻R Equal_mos与PMOS管MP6处于线性工作区时的线性区阻值R MP6-linear接近，不会影响现有基于动态零点跟随补偿的LDO电路本体的工作状态，即能始终保持LDO电路本体的环路稳定性，提高负载响应能力，安全可靠。
如图3所示，示出了基于动态零点跟随补偿的LDO电路本体的一种具体实施情况，具体地，所述LDO电路本体包括与PMOS管MP6漏极端连接的补偿电容Cc，补偿电容Cc的一端与动态电阻倍增电路、PMOS管MP6的漏极端连接，补偿电容Cc的另一端与主运算放大器OPA的输出端以及缓冲器Buffer的输入端连接；
PMOS管MP6的栅极端与PMOS管MP5的栅极端、PMOS管MP5的漏极端、偏置电流源IBIAS的正极端以及NMOS管MN3的漏极端连接，偏置电流源IBIAS的负极端以及NMOS管MN3的源极端均接地；
NMOS管MN3的栅极端与NMOS管MN1的栅极端、NMOS管MN2的栅极端、NMOS管MN2的漏极端以及PMOS管MP3的漏极端连接，NMOS管MN2的源极端以及NMOS管MN1的源极端均接地；NMOS管MN1的漏极端与PMOS管MP4的漏极端、PMOS管MP4的栅极端以及PMOS管MP3的栅极端连接；
PMOS管MP3的源极端与PMOS管MP2的漏极端连接，PMOS管MP4的源极端与PMOS管MP1的漏极端、电阻R1的第一端连接，其中，PMOS管MP4的源极端、PMOS管MP1的漏极端以及电阻R1的第一端相互连接后形成LDO电路本体的输出端VOUT；电阻R2的 第二端与主运算放大器OPA的同相端以及电阻R2的一端连接，电阻R2的另一端接地；
缓冲器Buffer的输出端与PMOS管MP2的栅极端以及PMOS管MP1的栅极端连接，所述主运算放大器OPA的反相端接参考电压VREF。
本发明实施例中，主运算放大器OPA、缓冲器Buffer、参考电压VREF的具体情况，可均与现有相一致，具体实现基于零点动态跟随补偿的环路补充情况与现有相一致，此处不再赘述。
因此，根据图3中的LDO电路本体，可以建立一个负载等效电阻的理想数学模型，具体为：
Figure PCTCN2022114424-appb-000004
其中，R MP6(ideal)为理想负载等效电阻，(W/L) MP6为PMOS管MP5导电沟道的宽长比，(W/L) MP6为PMOS管MP6导电沟道的宽长比，μ p为PMOS管MP6的平均迁移率，α是分流比例，分流比例α为PMOS管MP5的电流除以PMOS管MP1上的电流；C ox为PMOS管MP6的栅氧层电容，I L是PMOS管MP1管上的电流，即负载电流。负载大变化状态，即为负载有较大变化或剧烈变化，具体情况可以参考上述说明。
为了满足上述负载等效电阻的理想数学模型，最简单的尝试就是在图3中设置一与PMOS管MP6并联一个电阻，其中，所述并联电阻的阻值R parallel满足：
Figure PCTCN2022114424-appb-000005
并联电阻后，随负载变化的负载等效电阻R Equal_mos也即为R parallel//R MP6。在负载稳定时，PMOS管MP6相对应的等效电阻为R MP6-linear。由于R parallel＞＞R MP6-linear，在负载发生较大或剧烈变化时，由于R parallel的并联，负载等效电阻为：R Equal_mos＝(R parallel//R MP6_sat)＜R MP6(max)。
但这样的设计显然不具备可行性，这是因为：在轻载时，由于随负载变化的PMOS管MP6的线性阻值R MP6-linear＞10MΩ(M这里为10^6，下同)；因此，R parallel如果为了使得R Equal_mos≈R MP6(max)在负载不变时，需要使得R parallel＞10R MP6-linear＞100M，这可能会造成R parallel＞R MP6(max)时，使得在负载发生较大或剧烈变化时，R Equal_mos＞R MP6(max)导致环路的不稳 定。假使能够找到一个合适阻值为R parallel的电阻并将它与图3中的PMOS管MP6并联，满足上述理想数学模型；那么，在芯片设计中，大电阻值的电阻器件所付出的面积代价是不能接受的。
为了实现上述负载等效电阻的理想数学模型，另一种尝试可为在PMOS管MP6两端并联二极管。利用并联的二极管，虽然能够达到在负载不发生变化，PMOS管MP6两端电压降为0时R dio＞＞R MP6-linear的要求，但是在负载发生较大或者剧烈的变化时，PMOS管MP6进入饱和区时，电压降可能小于二极管的导通压降，从而起不到R Equal_mos＝R dio//R MP6_sat＜R MP6(max)的作用。R dio为并联二极管的等效电阻。
即使所并联的二极管能够满足上述的要求，采用二极管并联PMOS管MP6时，在负载变化较大时，瞬时所需压降大于二极管导通压降的情况下，会发生主运算放大器OPA输出点电压钳位在每个电压下不在进行应有的下降，从而导致令人不满意的瞬态响应，如在负载突然变大很多的时候，二极管并联PMOS管MP6的输出电压会有很大的尖峰。
因此，为了能实现上述负载等效电阻的理想数学模型，本发明的动态电阻倍增电路包括NMOS管MN4，所述NMOS管MN4的栅极端形成动态电阻倍增电路的输入端Input，动态电阻倍增电路的输入端Input与PMOS管MP6的漏极端适配连接；
NMOS管MN4的源极端与电流源I0的正极端以及电阻R0的第一端连接，电流源I0的负极端接地或浮地，NMOS管MN1的漏极端与输入电压VIN、电流源I1的正极端、电阻R3的第一端、PMOS管MP10的源极端以及PMOS管MP11的源极端连接；
电流源I1的负极端与电阻R0的第二端、PMOS管MP7的栅极端连接，PMOS管MP7的源极端与电阻R3的第二端连接，PMOS管MP7的漏极端与PMOS管MP8的漏极端、PMOS管MP8的栅极端以及PMOS管MP9的栅极端连接，PMOS管MP8的源极端以及PMOS管MP9的源极端均接地，PMOS管MP9的漏极端与PMOS管MP10的漏极端、PMOS管MP10的栅极端以及PMOS管MP11的栅极端连接，PMOS管MP11的漏极端形成动态电阻倍增电路的输出端Output，且所述动态电阻倍增电路的输出端Output与PMOS管MP6的漏极端适配连接。
具体地，预设负载变化阈值为I1*R0，所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，源漏电压差大于等于I1*R0。所述浮地是相对电平处于低电平，绝对电位不为0，浮地的情况与现有相一致，此处不再详述。
由图4可知，动态电阻倍增电路为电压输入，电流输出的电路，动态电阻倍增电路输出有电流的条件为：V 3-V 2≥|V thp|，其中，V 3为图4中PMOS管MP7源极端的电压，V 2为图4 中加载到PMOS管MP7栅极端的电压，|V thp|为图4中PMOS管MP7的阈值电压，V 3在输出端Output没有输出电流时，近似为VIN，并且V 2＝V 1-V thn+I1*R0，V 1为加载到NMOS管MN4栅极端的电压，V thn为NMOS管MN4的阈值电压，I1为电流源I1的电流值。
与此同时，V thn-|V thp|＜＜I1*R0，因此，可以得到，若动态电阻倍增电路的输出端Output输出电流时，需要满足：V 1≤VIN-I1*R0。
进一步可以理解为：当PMOS管MP6的源极端与所述PMOS管MP6漏极端的源漏电压差VIN-V 1小于I1*R0时，动态电阻倍增电路的输出端Output无输出电流，当PMOS管MP6两端的压差VIN-V 1大于I1*R0时，动态电阻倍增电路的输出端Output会产生输出电流。为便于表述，将PMOS管MP6两端的压差VIN-V 1设定为ΔV。
在负载不改变或者发生微小变化时，即负载稳定时，ΔV＜I1*R0时，动态电阻倍增电路的输出端Output没有电流流出，等效并联在PMOS管MP6两端的动态调节电阻R DRBC为：
Figure PCTCN2022114424-appb-000006
当负载发生较大或者剧烈变化时，ΔV≥I1*R0，动态电阻倍增电路的输出端Output所流出电流为：
Figure PCTCN2022114424-appb-000007
在负载发生较大或者剧烈变化时，ΔV≥I1*R0，因此，动态电阻倍增电路的输出端Output流出电流可以简化为：
Figure PCTCN2022114424-appb-000008
此时，等效并联在PMOS管MP6两端的动态调节电阻R DRBC为：
Figure PCTCN2022114424-appb-000009
其中，(W/L) MP9为PMOS管MP9导电沟道的宽长比，(W/L) MP8为PMOS管MP8导电沟道的宽长比，(W/L) MP11为PMOS管MP11导电沟通的宽长比，(W/L) MP10为PMOS管MP10导电沟道宽长比，
Figure PCTCN2022114424-appb-000010
为电阻R3放大倍数β，可以在设计中调节β以满足βR3＜R MP6(max)。优选地，0.27R MP6(max)＜βR3＜0.53R MP6(max)。
因此，通过动态电阻倍增电路，可用最小的代价实现了在负载稳定时，随负载变化的电 阻不受影响正常完成环路的稳定性补偿。在负载发生较大或者剧烈变化时，保证负载等效电阻R Equal_mos小于PMOS管MP6在环路稳定状态下的等效电阻极大值R MP6(max)，以保证LDO电路本体的环路稳定，使得输出电压稳定过渡。
综上，可得到基于动态零点跟随补偿LDO电路的环路高稳定方法，具体地，提供基于动态零点跟随补偿的LDO电路本体，所述LDO电路本体包括用于跟随负载变化的PMOS管MP6；
提供与所述PMOS管MP6适配连接的动态电阻倍增电路，对适配连接至所述LDO电路本体的负载，根据PMOS管MP6源极端与所述PMOS管MP6漏极端的源漏电压差表征负载的变化状态，当所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，动态电阻倍增电路根据负载变化状态产生与所述PMOS管MP6并联的动态调节电阻；
所述动态调节电阻与PMOS管MP6所跟随充当的电阻并联形成负载等效电阻，其中，所形成的负载等效电阻小于PMOS管MP6在环路稳定状态下的等效电阻极大值，以使得所述LDO电路本体的高频极点频率大于LDO电路本体的单位增益频率。
源漏电压差表征负载的变化状态小于动态电阻倍增电路内预设负载变化阈值时，PMOS管MP6处于线性工作区，且动态电阻倍增电路根据负载变化状态产生呈高阻状态的动态调节电阻；
动态电阻倍增电路产生高阻状态动态调节电阻的阻值远大于PMOS管MP6处于线性工作区时的线性区阻值。
本发明实施例中，LDO电路本体、PMOS管MP6、动态电阻倍增电路、PMOS管MP6的源漏电压差等均可以参考上述说明，具体确保LDO电路本体环路稳定性的调节方式以及过程可参考上述说明，此处不再详述。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种基于动态零点跟随补偿的环路高稳定LDO电路，其特征在于，所述环路高稳定LDO电路包括基于动态零点跟随补偿的LDO电路本体，所述LDO电路本体包括用于跟随负载变化的PMOS管MP6；所述PMOS管MP6适配连接的动态电阻倍增电路，对适配连接至所述LDO电路本体的负载，根据PMOS管MP6源极端与所述PMOS管MP6漏极端的源漏电压差表征负载的变化状态，当所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，动态电阻倍增电路根据负载变化状态产生与所述PMOS管MP6并联的动态调节电阻。
    所述动态调节电阻与PMOS管MP6所跟随充当的电阻并联形成负载等效电阻，其中，所形成的负载等效电阻小于PMOS管MP6在环路稳定状态下的等效电阻极大值，以使得所述LDO电路本体的高频极点频率大于LDO电路本体的单位增益频率。
  2. 根据权利要求1所述的基于动态零点跟随补偿的环路高稳定LDO电路，其特征在于，源漏电压差表征负载的变化状态小于动态电阻倍增电路内预设负载变化阈值时，PMOS管MP6处于线性工作区，且动态电阻倍增电路根据负载变化状态产生呈高阻状态的动态调节电阻；动态电阻倍增电路产生高阻状态动态调节电阻的阻值远大于PMOS管MP6处于线性工作区时的线性区阻值。
  3. 根据权利要求2所述的基于动态零点跟随补偿的环路高稳定LDO电路，其特征在于，所述动态电阻倍增电路包括NMOS管MN4，所述NMOS管MN4的栅极端形成动态电阻倍增电路的输入端Input，动态电阻倍增电路的输入端Input与PMOS管MP6的漏极端适配连接；
    NMOS管MN4的源极端与电流源I0的正极端以及电阻R0的第一端连接，电流源I0的负极端接地或浮地，NMOS管MN1的漏极端与输入电压VIN、电流源I1的正极端、电阻R3的第一端、PMOS管MP10的源极端以及PMOS管MP11的源极端连接；
    电流源I1的负极端与电阻R0的第二端、PMOS管MP7的栅极端连接，PMOS管MP7的源极端与电阻R3的第二端连接，PMOS管MP7的漏极端与PMOS管MP8的漏极端、PMOS管MP8的栅极端以及PMOS管MP9的栅极端连接，PMOS管MP8的源极端以及PMOS管MP9的源极端均接地，PMOS管MP9的漏极端与PMOS管MP10的漏极端、PMOS管MP10的栅极端以及PMOS管MP11的栅极端连接，PMOS管MP11的漏极端形成动态电阻倍增电路的输出端Output，且所述动态电阻倍增电路的输出端Output与PMOS管MP6的漏极端适配连接。
  4. 根据权利要求3所述的基于动态零点跟随补偿的环路高稳定LDO电路，其特征在于，预设负载变化阈值为I1*R0，所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，源漏电压差大于等于I1*R0。
  5. 根据权利要求1至4任一项所述的基于动态零点跟随补偿的环路高稳定LDO电路，其特征在于，所述LDO电路本体包括与PMOS管MP6漏极端连接的补偿电容Cc，补偿电容Cc的一端与动态电阻倍增电路、PMOS管MP6的漏极端连接，补偿电容Cc的另一端与主运算放大器OPA的输出端以及缓冲器Buffer的输入端连接；
    PMOS管MP6的栅极端与PMOS管MP5的栅极端、PMOS管MP5的漏极端、偏置电流源IBIAS的正极端以及NMOS管MN3的漏极端连接，偏置电流源IBIAS的负极端以及NMOS管MN3的源极端均接地；
    NMOS管MN3的栅极端与NMOS管MN1的栅极端、NMOS管MN2的栅极端、NMOS管MN2的漏极端以及PMOS管MP3的漏极端连接，NMOS管MN2的源极端以及NMOS管MN1的源极端均接地；NMOS管MN1的漏极端与PMOS管MP4的漏极端、PMOS管MP4的栅极端以及PMOS管MP3的栅极端连接；
    PMOS管MP3的源极端与PMOS管MP2的漏极端连接，PMOS管MP4的源极端与PMOS管MP1的漏极端、电阻R1的第一端连接，其中，PMOS管MP4的源极端、PMOS管MP1的漏极端以及电阻R1的第一端相互连接后形成LDO电路本体的输出端VOUT；电阻R2的第二端与主运算放大器OPA的同相端以及电阻R2的一端连接，电阻R2的另一端接地；
    缓冲器Buffer的输出端与PMOS管MP2的栅极端以及PMOS管MP1的栅极端连接，所述主运算放大器OPA的反相端接参考电压VREF。
  6. 一种基于动态零点跟随补偿环路高稳定LDO电路的方法，其特征在于，所述方法提供基于动态零点跟随补偿的LDO电路本体，所述LDO电路本体包括用于跟随负载变化的PMOS管MP6；
    提供与所述PMOS管MP6适配连接的动态电阻倍增电路，对适配连接至所述LDO电路本体的负载，根据PMOS管MP6源极端与所述PMOS管MP6漏极端的源漏电压差表征负载的变化状态，当所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，动态电阻倍增电路根据负载变化状态产生与所述PMOS管MP6并联的动态调节电阻；
    所述动态调节电阻与PMOS管MP6所跟随充当的电阻并联形成负载等效电阻，其中，所形成的负载等效电阻小于PMOS管MP6在环路稳定状态下的等效电阻极大值，以使得所述LDO电路本体的高频极点频率大于LDO电路本体的单位增益频率。
  7. 根据权利要求6所述基于动态零点跟随补偿环路高稳定LDO电路的方法，其特征在于，源漏电压差表征负载的变化状态小于动态电阻倍增电路内预设负载变化阈值时，PMOS管MP6处于线性工作区，且动态电阻倍增电路根据负载变化状态产生呈高阻状态的动态调节 电阻；
    动态电阻倍增电路产生高阻状态动态调节电阻的阻值远大于PMOS管MP6处于线性工作区时的线性区阻值。
  8. 根据权利要求7所述基于动态零点跟随补偿环路高稳定LDO电路的方法，其特征在于，所述动态电阻倍增电路包括NMOS管MN4，所述NMOS管MN4的栅极端形成动态电阻倍增电路的输入端Input，动态电阻倍增电路的输入端Input与PMOS管MP6的漏极端适配连接；
    NMOS管MN4的源极端与电流源I0的正极端以及电阻R0的第一端连接，电流源I0的负极端接地或浮地，NMOS管MN1的漏极端与输入电压VIN、电流源I1的正极端、电阻R3的第一端、PMOS管MP10的源极端以及PMOS管MP11的源极端连接；
    电流源I1的负极端与电阻R0的第二端、PMOS管MP7的栅极端连接，PMOS管MP7的源极端与电阻R3的第二端连接，PMOS管MP7的漏极端与PMOS管MP8的漏极端、PMOS管MP8的栅极端以及PMOS管MP9的栅极端连接，PMOS管MP8的源极端以及PMOS管MP9的源极端均接地，PMOS管MP9的漏极端与PMOS管MP10的漏极端、PMOS管MP10的栅极端以及PMOS管MP11的栅极端连接，PMOS管MP11的漏极端形成动态电阻倍增电路的输出端Output，且所述动态电阻倍增电路的输出端Output与PMOS管MP6的漏极端适配连接。
  9. 根据权利要求8所述基于动态零点跟随补偿环路高稳定LDO电路的方法，其特征在于，预设负载变化阈值为I1*R0，所表征负载的变化状态与动态电阻倍增电路内的预设负载变化阈值匹配时，源漏电压差大于等于I1*R0。
  10. 根据权利要求6至9任一项所述基于动态零点跟随补偿环路高稳定LDO电路的方法，其特征在于，所述LDO电路本体包括与PMOS管MP6漏极端连接的补偿电容Cc，补偿电容Cc的一端与动态电阻倍增电路、PMOS管MP6的漏极端连接，补偿电容Cc的另一端与主运算放大器OPA的输出端以及缓冲器Buffer的输入端连接；
    PMOS管MP6的栅极端与PMOS管MP5的栅极端、PMOS管MP5的漏极端、偏置电流源IBIAS的正极端以及NMOS管MN3的漏极端连接，偏置电流源IBIAS的负极端以及NMOS管MN3的源极端均接地；
    NMOS管MN3的栅极端与NMOS管MN1的栅极端、NMOS管MN2的栅极端、NMOS管MN2的漏极端以及PMOS管MP3的漏极端连接，NMOS管MN2的源极端以及NMOS管MN1的源极端均接地；NMOS管MN1的漏极端与PMOS管MP4的漏极端、PMOS管MP4 的栅极端以及PMOS管MP3的栅极端连接；
    PMOS管MP3的源极端与PMOS管MP2的漏极端连接，PMOS管MP4的源极端与PMOS管MP1的漏极端、电阻R1的第一端连接，其中，PMOS管MP4的源极端、PMOS管MP1的漏极端以及电阻R1的第一端相互连接后形成LDO电路本体的输出端VOUT；电阻R2的第二端与主运算放大器OPA的同相端以及电阻R2的一端连接，电阻R2的另一端接地；
    缓冲器Buffer的输出端与PMOS管MP2的栅极端以及PMOS管MP1的栅极端连接，所述主运算放大器OPA的反相端接参考电压VREF。
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