WO2024027471A1 - 测试单元的方法和相关装置 - Google Patents

测试单元的方法和相关装置 Download PDF

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Publication number
WO2024027471A1
WO2024027471A1 PCT/CN2023/106734 CN2023106734W WO2024027471A1 WO 2024027471 A1 WO2024027471 A1 WO 2024027471A1 CN 2023106734 W CN2023106734 W CN 2023106734W WO 2024027471 A1 WO2024027471 A1 WO 2024027471A1
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Prior art keywords
transistor
defects
defect
target
unit
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PCT/CN2023/106734
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English (en)
French (fr)
Inventor
陈晨
黄宇
张威威
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华为技术有限公司
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Publication of WO2024027471A1 publication Critical patent/WO2024027471A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Definitions

  • the embodiments of the present application relate to the field of chip technology, and more specifically, to methods and related devices for testing units in electronic design automation.
  • Embodiments of the present application provide a method and related device for testing a unit, which can reduce the number of error-notation simulation input vectors used for unit defect model generation, thereby reducing the time consumption of simulating transient simulation in unit defect model generation, and thus enabling faster Get unit test results.
  • embodiments of the present application provide a method for testing a unit, which includes: performing error-free simulation on N defects that need to be tested in the unit to obtain an error-free simulation result of the unit; according to the error-free simulation result of the unit;
  • the error injection simulation results determine the test vector used by each of the N defects during the error injection simulation, where the test vector of at least one defect among the N defects includes part of the input vectors among the 2 M input vectors.
  • M is the number of input orders included in the unit
  • M and N are positive integers greater than or equal to 1.
  • the above technical solution can filter the test vectors used during error injection simulation of defects, so as to reduce the number of test vectors used for each defect during error injection simulation. In this way, the number of incorrect injection simulations for each defect can be reduced, thereby reducing the total number of incorrect injection simulations for the unit. Since the number of total error-injection simulations is reduced, the time consumption of simulation is also reduced accordingly, and the defect model of the unit can be obtained faster.
  • determining the N defects that require defect testing in the unit includes: determining that the N defects include N1 based on a plurality of transistors included in the unit. Normally open defects of transistors, wherein the plurality of transistors include N 1 target transistors, the N 1 target transistors correspond to the N 1 normally open defects of the transistors, and the N 1 target transistors are among the plurality of transistor units. Transistors other than parasitic transistors and inactive transistors.
  • Parasitic transistors are transistors that arise due to the electrical characteristics of the wiring in the cell, while inactive transistors are transistors that are provided to facilitate chip manufacturing. Defects in both transistors do not affect the functionality of the cell. Therefore, there is no need to test these two transistors for defects.
  • the above technical solution excludes these two types of transistors that do not need to be tested when determining defects that require defect testing, thereby reducing the number of defects that need to be tested.
  • the test vector used for each of the N defects in the error-injection simulation is determined based on the error-free simulation result of the unit, Including: determining from the unit's error-free simulation results that the A first voltage value set corresponding to a target transistor, wherein the first target transistor is any one of the N 1 target transistors, and the first voltage value set includes 2 M first voltage values and the 2 M There is a one-to-one correspondence between the input vectors, and each of the 2 M first voltage values included in the first voltage value set is the gate voltage of the first target transistor under the corresponding input vector; determine the first Among the 2 M first voltage values included in a voltage value set, the input vector corresponding to the first voltage value that turns off the first target transistor is a first test vector, and the first test vector is used to test the first target. Test vectors for transistor normally-on defects in transistors.
  • a normally-on transistor defect is when a transistor is turned on at a gate voltage that should cause the transistor to turn off. Therefore, the gate voltage that turns the transistor on is meaningless for testing normally open defects. Therefore, the input vector corresponding to the gate voltage that turns off the transistor is screened out as the test vector for the normally-on defect of the transistor.
  • determining the N defects that need to be tested for defects in the unit includes: determining that the N defects include N according to a plurality of transistors included in the unit. 1 transistor low-level turn-off defect and N 1 transistors high-level turn-off defect, wherein the plurality of transistors include N 1 target transistors, the N 1 target transistors and the N 1 transistors have low-level turn-off defects Defects correspond one to one.
  • the N 1 target transistors correspond to the N 1 transistors with high-level turn-off defects.
  • the target transistors are transistors other than parasitic transistors and invalid transistors among the multiple transistors. The transistors have low voltage.
  • the flat turn-off defect is used to test the turn-off defect of the transistor when the open-circuit resistance is connected to a low level
  • the high-level turn-off defect of the transistor is used to test the turn-off defect of the transistor when the open-circuit resistance is connected to a high level.
  • Parasitic transistors are transistors that arise due to the electrical characteristics of the wiring in the cell, while inactive transistors are transistors that are provided to facilitate chip manufacturing. Defects in both transistors do not affect the functionality of the cell. Therefore, there is no need to test these two transistors for defects.
  • the above technical solution excludes these two types of transistors that do not need to be tested when determining defects that require defect testing, thereby reducing the number of defects that need to be tested.
  • the test vector used for each of the N defects in the error-injection simulation is determined based on the error-free simulation result of the unit, Including: determining a second set of voltage values corresponding to the second target transistor from the error-free simulation results of the unit, wherein the second target transistor is any target transistor among the N 1 target transistors, and the second voltage
  • the 2 M subsets included in the value set correspond to the 2 M input vectors one-to-one, and each subset of the 2 M subsets included in the second voltage value set includes the gate of the second target transistor under the corresponding input vector.
  • the second test vector is a test vector used to test the transistor low-level turn-off defect of the second transistor.
  • the first preset condition includes: the gate voltage of the second target transistor causes the second target transistor to be turned on and the second target transistor is turned on. The source or drain of the second target transistor is at a high level.
  • the second preset condition includes: the gate voltage of the second target transistor turns off the second target transistor and the source and drain of the second target transistor.
  • the third preset condition includes: the gate voltage of the second target transistor causes the second target transistor to be turned on and the second target transistor is turned on. The source or drain of the transistor is at a low level.
  • the fourth preset condition includes: the gate voltage of the second target transistor turns off the second target transistor and the source and drain of the second target transistor are not both. high level.
  • the open-circuit resistor When testing a transistor for low-level turn-off defects, the open-circuit resistor is connected low. Therefore, if the gate voltage of a transistor causes the transistor to conduct, the source and drain voltages are the same. If the source and drain are both low voltage, it will be consistent with the voltage state during the error simulation. Therefore, the input vector corresponding to this set of voltages is meaningless for testing the low-level turn-off defects of the transistor. If the transistor is turned off, and both the drain and source voltages are low level, this state is consistent with the voltage state during the error simulation. Therefore, the input vector corresponding to this set of voltages is useful for testing the low-level turn-off defects of the transistor. Pointless.
  • the open-circuit resistor When testing a transistor for high-level turn-off defects, the open-circuit resistor is connected high. Therefore, if the gate voltage of the transistor causes the transistor to turn on, the source and drain voltages are the same. If the source and drain are both high voltages, it is consistent with the voltage state during the error simulation. Therefore, this set of voltages corresponds to The input vector is meaningless for testing of transistor high-level turn-off defects. If the transistor is turned off, and both the drain and source voltages are high level, this state is consistent with the voltage state during the error simulation. Therefore, the input vector corresponding to this set of voltages is useful for testing the high-level turn-off defects of the transistor. Pointless. Through the above solution, the number of input vectors used to test transistor turn-off defects can be reduced, thereby reducing the number of simulations of transistor turn-off defects.
  • determining the N defects that require defect testing in the unit includes: determining that the N defects include N 2 according to the parasitic resistance included in the unit. low-level open-circuit defects and N 2 high-level open-circuit defects, where the unit includes N 2 target branches, and the target branch is a branch in the unit that includes one or more of the parasitic resistances,
  • the low-level open-circuit defect is used to test the open-circuit defect when the open-circuit resistor is connected to a low level
  • the high-level open circuit defect is used to test the open-circuit defect when the open-circuit resistor is connected to a high level.
  • the above technical solution regards a target branch including multiple parasitic resistances as a defect to be tested, rather than treating the multiple parasitic resistances as multiple defects to be tested. This way, you can reduce the number of defects that need to be tested.
  • the test vector used for each of the N defects in the error-injection simulation is determined based on the error-free simulation result of the unit, Including: determining the third voltage value set corresponding to the first target branch from the error-free simulation result of the unit, wherein the first target branch is any branch among the N 2 target branches, the The 2 M second voltage values included in the third voltage value set correspond to the 2 M input vectors one-to-one, and each of the 2 M second voltage values included in the third voltage value set is in The voltage value of the first target branch under the corresponding input vector; determine the input vector corresponding to the high level among the 2 M second voltage values included in the third voltage value set as the fourth test vector, and the fourth test The vector is a test vector used to test the low-level open defect of the first target branch; it is determined that the input vector corresponding to the low level among the 2 M second voltage values included in the third voltage value set is the fifth test vector, the fifth test vector is a test vector used to test
  • the voltage value of the open resistor When testing low-level open defects, the voltage value of the open resistor is low. At this time, if the voltage value on the first target branch is also low, it cannot be determined whether the branch has an open circuit defect. Therefore, it is necessary to select the input vector corresponding to the high level to test the low-level open circuit defect. Similarly, when testing high-level open defects, the voltage value of the open resistor is high. At this time, if the voltage value on the first target branch is also high, it cannot be determined whether the branch has an open circuit defect. Therefore, it is necessary to select the input vector corresponding to the low level to test the high-level open circuit defect. Through the above solution, the number of input vectors used to test open circuit defects can be reduced, thereby reducing the number of simulations of open circuit defects.
  • determining the N defects that require defect testing in the unit includes: determining that the unit includes K pairs of nodes, and each pair of nodes in the K pairs of nodes Including two different nodes, K is a positive integer greater than or equal to 1; according to the coordinate information of the components in the unit, N 3 pairs of nodes are determined from the K pairs of nodes, and each pair of nodes in the N 3 pairs of nodes Including two adjacent nodes; it is determined that the N defects include N 3 short-circuit defects, where the N 3 short-circuit defects correspond to the N3 pairs of nodes one-to-one.
  • Adjacent nodes mean that there are no other components (such as parasitic resistors, transistors, etc.) or nodes between the two nodes. Short-circuit defects are usually only considered between adjacent nodes, and short-circuit defects between two non-adjacent nodes are not considered. Therefore, the above technical solution can reduce the number of defects that need to be tested for short circuit defects.
  • the test vector used for each of the N defects in the error-injection simulation is determined based on the error-free simulation result of the unit, including: determining a fourth voltage value set corresponding to the first node pair from the error-free simulation result of the unit, wherein the first node pair is any pair of nodes in the N 3 pairs of nodes, and the fourth voltage value
  • the 2 M subsets included correspond to the 2 M input vectors one-to-one, and each subset of the 2 M subsets included in the fourth voltage value set includes two nodes in the first node pair under the corresponding input vector. voltage value; it is determined that the input vector corresponding to the subset including different voltage values in the 2 M subsets included in the fourth voltage value is the sixth test vector, and the sixth test vector is used to test the short circuit of the first node pair Defect test vectors.
  • the method further includes: performing an error-injection simulation on the unit to obtain an error-injection simulation result of the unit; and based on the error-free simulation result of the unit and The error-injection simulation result of the unit determines the actual test vector of each of the N defects, where the error-free simulation result of the actual test vector of each of the N defects is different from the error-injection simulation result. ; Generate a defect description model of the unit based on the actual test vector of each defect in the N defects.
  • embodiments of the present application provide a unit testing device, which includes a module for implementing the first aspect or any possible implementation of the first aspect.
  • embodiments of the present application provide a computer-readable storage medium that stores program code.
  • the computer storage medium When the computer storage medium is run on a computer, it causes the computer to execute the first aspect or the first aspect. any possible implementation.
  • inventions of the present application provide a computer program product.
  • the computer program product includes: computer program code.
  • the computer program code When the computer program code is run on a computer, it causes the computer to execute the first aspect or any of the first aspects.
  • inventions of the present application provide a computer device.
  • the computer device includes a processor, the processor being coupled to a memory, reading and executing instructions and/or program codes in the memory to execute the first aspect or Any possible implementation of the first aspect.
  • inventions of the present application provide a chip system.
  • the chip system includes a logic circuit that is coupled to an input/output interface and transmits data through the input/output interface to perform the first aspect or the first aspect. any possible implementation.
  • Figure 1 is a flow chart for generating a defect description model.
  • Figure 2 is a schematic flow chart of a method for testing a unit provided according to an embodiment of the present application.
  • Figure 3 is a partial structural diagram of the unit.
  • FIG. 4 is a schematic diagram of parasitic resistance in the cell 300 shown in FIG. 3 .
  • FIG. 5 is a schematic layout diagram of the transistor M4 and the transistor M5 in the unit 300 shown in FIG. 3 .
  • FIG. 6 is a schematic diagram of the unit 300 after marking defects that require defect testing.
  • Figure 7 is a circuit diagram when performing error injection simulation on the normally open defect of a transistor.
  • Figure 8 is a circuit diagram when performing error injection simulation on defect D1.
  • Figure 9 is a circuit diagram when performing error injection simulation on defect D2.
  • Figure 10 is a circuit diagram when performing error injection simulation on defect D3.
  • Figure 11 is a schematic structural block diagram of a unit testing device provided according to an embodiment of the present application.
  • the unit (cell) in the embodiment of the present application is a group of transistors that provide Boolean logic functions (for example, AND, OR, NOT, AND, NAND, inverter, etc.) or storage functions (flip-flops or latches) and interconnection structures.
  • the unit referred to in the embodiment of this application may be a standard cell (standard cell, std cell), a special standard cell (for example, a filling unit, a voltage clamping unit, a well connection unit, an isolation unit, etc.), a module macro unit, an input unit Output unit (input output pad cell), or other circuit structure containing transistors and interconnect structures.
  • Figure 1 is a flow chart for generating a defect description model.
  • the method shown in Figure 1 can be performed by a computer device.
  • the computer device may be a desktop computer, laptop computer, server, etc.
  • all steps shown in Figure 1 can be performed by the same computer device.
  • different steps in Figure 1 may be performed by different computer devices.
  • the first computer device may perform step 101 to obtain a defect list and send the defect list to the second computer device.
  • the second computer device performs step 102 according to the defect list to obtain an error injection simulation result and sends the error injection simulation result to the first computer device.
  • the first computer device executes steps 103 and 104 to obtain a defect description model.
  • the method shown in FIG. 1 may also be executed by components in one or more computer devices (such as chips or chip systems, etc.).
  • defects that may occur in the unit are recorded in the defect list. These defects are the ones that require defect testing. Common defects in cells include: transistor normally-on defects, turn-off defects, open-circuit defects and short-circuit defects.
  • the number of input vectors included in a unit is related to the number of input terminals of the unit.
  • the input signal at each input terminal of the unit can be 1 or 0. Therefore, if the unit only includes 1 input terminal, then the unit can include two input vectors, respectively 0 and 1; if the unit includes 2 input terminals, then the unit can include four input vectors, respectively 00, 01 , 10 and 11; if the unit includes M input terminals, then the unit can include 2 M input vectors, where M is a positive integer greater than or equal to 1.
  • the input vectors used for the test of each defect can be filtered out (which can be called actual test vectors). Merging test vectors can simplify the number of test vectors. For example, if the actual test vectors filtered out include 111 and 110. In this case, the two input vectors can be combined into 11x, which simplifies the final output to the number of actual test vectors.
  • the defect description model output process prints out information about unit defects to a file. Scan the defect list to print the information of each defect in turn.
  • the defect information includes but is not limited to: the name of the defect, the node corresponding to the defect, the assumed resistance value of the defect, the actual test vector of the defect and the output value of the output terminal of the unit (which can be called an error simulation value), the physics of the defect Information etc.
  • the physical information of the defect includes the coordinates of the defect and the layer of the defect.
  • the embodiment of the present application provides a method for testing a unit, which can reduce the input vectors used when performing error injection simulation, thereby reducing the time and computing resources consumed by error injection simulation.
  • the embodiments of the present application will be introduced below with reference to Figures 2 to 10.
  • Figure 2 is a schematic flow chart of a method for testing a unit provided according to an embodiment of the present application.
  • the method shown in FIG. 2 may be executed by a computer device or a component in the computer device (such as a chip or a chip system, etc.).
  • N is a positive integer greater than or equal to 1.
  • the unit can be described by a netlist, which records the various components present in the unit, such as transistors and the connection relationships between transistors.
  • the unit can also be described by a parasitic netlist.
  • the parasitic netlist In addition to recording the various components included in the unit and the connection relationships between the components, the parasitic netlist also records parasitic components (such as parasitic capacitance, parasitic resistance, parasitic transistors, etc.), parasitic components The connection relationship between them as well as the connection relationship between parasitic components and each component in the unit.
  • the former netlist can be called the actual netlist, and the components recorded in the actual netlist are called actual components.
  • the netlist and parasitic netlist also include nodes (nets) used to connect components. Unless otherwise specified, the elements mentioned in the embodiments of this application may include actual elements and parasitic elements.
  • the library file can be obtained from the process unit library to obtain the parasitic netlist of the unit, and the component types included in the unit and the connection relationships between the components can be obtained through the parasitic netlist.
  • the location information of the components included in the unit can be obtained based on the parasitic netlist.
  • the parasitic netlist records the size and location information of each component. Based on the size and position information of the component, the location of the component on the physical layout can be determined.
  • the N defects that need to be tested for defects in the unit can be determined based on the component types included in the unit, the connection relationships of the components, and the location information of the components.
  • Common defects in cells include: transistor normally-on defects, turn-off defects, open-circuit defects and short-circuit defects.
  • Normally open transistor defects also known as transistor leakage defects or transistor normally open/leakage defects
  • the transistor mentioned in the embodiment of this application may be a field effect transistor (FET), an N-type metal-oxide-semiconductor (NMOS) transistor (can be referred to as an NMOS transistor for short) , P-channel metal-oxide-semiconductor (P-channel metal-oxide-semiconductor) transistor (can be referred to as PMOS transistor for short), etc.
  • FET field effect transistor
  • NMOS N-type metal-oxide-semiconductor
  • PMOS transistor P-channel metal-oxide-semiconductor
  • the NMOS tube if the gate-source voltage (can be called Vgs) is greater than or equal to the voltage threshold (can be called Vth), the NMOS tube is turned on; if Vgs is less than Vth, the NMOS is turned off.
  • Vgs the gate-source voltage
  • Vth the voltage threshold
  • a normally-on defect means that the transistor is always on. In other words, even if Vgs is less than Vth, the NMOS tube is still on.
  • each transistor in a cell may correspond to a transistor normally-on defect.
  • the number of transistors included in the unit can be determined through the parasitic netlist of the unit, thereby determining the number of normally-on defects in the transistors included in the unit and the transistor corresponding to the normally-on defect in each transistor. For example, if a cell includes N t transistors, then the cell may include N t transistor normally-on defects.
  • Cells usually include some parasitic transistors and dummy transistors.
  • Parasitic transistors are transistors that arise due to the electrical characteristics of the wiring in the cell, while inactive transistors are transistors that are provided to facilitate chip manufacturing. Defects in both transistors do not affect the functionality of the cell. Therefore, there is no need to test these two transistors for defects. Therefore, in other embodiments, only transistors other than parasitic transistors and inactive transistors may be determined.
  • this transistor i.e., in addition to the parasitic transistor in the unit and inactive transistors
  • target transistors Each target transistor can correspond to a transistor normally open defect. The above technical solution can reduce unnecessary normally-on defect testing of transistors.
  • the target transistor included in the unit may be based on the parasitic netlist of the unit.
  • the cell's parasitic netlist contains information about all transistors of the cell. Therefore, based on the parasitic netlist of the unit, all target transistors included in the unit are determined.
  • the target transistor of a unit may be determined based on the netlist of the unit.
  • the unit's netlist just lacks information about parasitic components. Cells containing parasitic transistors do not need to be tested for defects. In other words, the relevant information of all the transistors included in the unit that need to be tested for defects (ie, the target transistors) will be recorded in the netlist of the unit. Therefore, all target transistors included in the unit can be determined directly from the netlist included in the unit.
  • Transistor turn-off defects can also be referred to as turn-off defects.
  • an off-defect means that the transistor is always off. Taking the NMOS tube as an example, even if Vgs is greater than or equal to Vth, the NMOS tube is still in the off state.
  • Transistor turn-off defects can be further divided into transistor low-level turn-off defects and transistor high-level turn-off defects.
  • Transistor low-level turn-off defects are turn-off defects when the open-circuit resistor is connected to a low level.
  • Transistor high-level turn-off defects The turn-off defect is used to test the turn-off defect when the open-circuit resistor is connected to a high level.
  • each transistor can correspond to a transistor low-level turn-off defect and a transistor high-level turn-off defect.
  • each transistor in the unit may correspond to a transistor low-level turn-off defect and a transistor high-level turn-off defect.
  • the target transistor includes a transistor turn-off defect.
  • a target transistor includes a transistor low-level turn-off defect and a transistor high-level turn-off defect.
  • the defects that need to be tested for these N 1 target transistors include: N 1 transistor normally open defects, N 1 transistors with low-level turn-off defects and N 1 transistors with high-level turn-off defects.
  • Figure 3 shows some of the transistors contained in the cell.
  • the unit 300 includes six transistors, namely M1 to M7, where M1, M2 and M3 are PMOS transistors, and M4, M5 and M6 are NMOS transistors.
  • Unit 300 has three input terminals, namely A1, A2 and A3.
  • the annotation unit 300 in addition to the nodes used to connect the input terminals, the annotation unit 300 also includes a total of four nodes N1 to N4 , in which the source of the transistor M1 , the source of the transistor M2 and the source of the transistor M3 are connected to the node N1 , Node N1 is the node used to access the power supply terminal (VDD).
  • VDD power supply terminal
  • node N2 The drains of transistor M1 , the drain of transistor M2 , and the drain of transistor M3 are connected to node N2 .
  • the drain of transistor M4 is also connected to node N2.
  • the source of transistor M4 and the drain of transistor M5 are connected to node N3.
  • the source of transistor M5 and the drain of transistor M6 are connected to node N4.
  • node N2 is the output of unit 300. In this case, node N2 may also be represented by the letter Z.
  • each transistor shown in Figure 3 is connected to an input terminal of the unit.
  • the gate voltages of the transistors shown in Figure 3 are all input voltages.
  • the cell may also include transistors whose gates are connected to nodes within the cell. In other words, the gate voltage of these transistors is the internal voltage of the cell.
  • the unit 300 shown in Figure 3 can include 6 transistor normally-on defects and 12 transistor turn-off defects, where the 12 transistor turn-off defects include 6 transistors with low levels. Turn-off defects and high-level turn-off defects of 6 transistors.
  • the open circuit defect refers to the existence of an open circuit in a branch.
  • the open defect included by the cell can be determined based on the parasitic resistance included by the cell.
  • open-circuit defects can also be further divided into low-level open-circuit defects and high-level open-circuit defects.
  • Low-level open circuit defects are used to test open-circuit defects when the open-circuit resistor is connected to a low level.
  • the high level open circuit defect is used to test the open circuit defect when the open circuit resistance is connected to a high level.
  • a parasitic resistance may correspond to a low-level open defect and a high-level open defect.
  • FIG. 4 illustrates parasitic resistance in cell 300 shown in FIG. 3 .
  • the unit 300 includes parasitic resistors Rp1 to Rp6. It can be understood that FIG. 4 only shows six parasitic resistors in the unit 300 for convenience of description, and the unit 300 may also include other parasitic resistors not shown in FIG. 4 .
  • a parasitic resistance can correspond to a low-level open defect and a High level open circuit defect. Then, the six parasitic resistors shown in Figure 4 have a total of 12 open circuit defects that need to be tested, and the 12 open circuit defects include 6 low-level open circuit defects and 6 high-level open circuit defects.
  • a branch may correspond to a low-level open defect and a high-level open defect.
  • the branch containing parasitic resistance may be called the target branch (or first branch), and the branch containing no parasitic resistance may be called the non-target branch (or second branch).
  • the target branch 1 where the parasitic resistance Rp1 is located contains only one parasitic resistance, the parasitic resistance Rp1. Therefore, target branch 1 corresponds to a low-level open circuit defect and a high-level open circuit defect (it can also be said that the parasitic resistance Rp1 corresponds to a low-level open circuit defect and a high-level open circuit defect).
  • the target branch 2 includes a total of three parasitic resistances: parasitic resistance Rp2, parasitic resistance Rp3 and parasitic resistance Rp4. Therefore, the target branch 2 can correspond to a low-level open defect and a high-level open defect (which can also be called the three parasitic resistances included in the branch (parasitic resistance Rp2, parasitic resistance Rp3 and parasitic resistance Rp4) corresponding to A low-level open defect and a high-level open defect).
  • target branch 3 includes parasitic resistance Rp5 and parasitic resistance Rp6.
  • target branch 3 can correspond to a low-level open defect and a high-level open defect (which can be called two parasitic resistances (parasitic resistance Rp5 and parasitic resistance Rp5) included in the branch) corresponding to a low-level open defect. defect and a high-level open defect).
  • the 6 parasitic resistances shown in Figure 4 correspond to a total of 6 open-circuit defects, where the 6 open-circuit defects include 3 low-level open circuit defects and 3 high-level open circuit defects.
  • each target branch contains an average of 3 parasitic resistances. If each parasitic resistance corresponds to a low-level open defect and a high-level open defect, then the unit has a total of 3 ⁇ N 2 low-level open defects and 3 ⁇ N 2 high-level open defects. If a target branch corresponds to a low-level open defect and a high-level open defect, then the unit has 2 ⁇ N 2 open defects, and these 2 ⁇ N 2 open defects include N 2 low-level open defects. and N 2 high-level open defects. It can be seen that by combining multiple parasitic resistors contained on the same branch, the number of open defects that need to be tested can be effectively reduced.
  • the short-circuit defect of the unit is related to the distance between the lines. Typically, a short circuit defect may occur between two adjacent lines. If two lines are separated by other lines, nodes or components, a short circuit defect will not usually occur. Parasitic capacitance may also create short circuit defects. However, if the two endpoints of the parasitic capacitance are far apart or blocked by other lines, nodes or components, short circuit defects usually do not occur. It can be understood that if two adjacent lines are connected to the same node, then the two lines will not cause a short circuit defect. Taking FIG. 3 as an example, the drain of the transistor M1 is connected to the node N2, and the drain of the transistor M2 is also connected to the node N2.
  • Both lines are connected to node N2, so even if the two lines are adjacent, a short circuit defect will not occur. Therefore, two adjacent lines that produce short-circuit defects should be two lines containing different nodes. Therefore, it can also be considered that the short circuit defect corresponds to a pair of adjacent nodes.
  • a pair of adjacent nodes includes two adjacent nodes located on two lines that are physically adjacent. Therefore, if there are N 3 pairs of nodes in the unit, and each pair of nodes in the N 3 pairs of nodes includes two adjacent nodes, then there are N 3 short-circuit defects that need to be tested in the unit, N 3 short-circuit defects and N 3 pairs of nodes correspond one to one.
  • FIG. 5 is a schematic layout diagram of the transistor M4 and the transistor M5 in the unit 300 shown in FIG. 3 .
  • Line L1 is used to connect the gate of transistor M4 and input terminal A1
  • line L2 is used to connect the gate of transistor M5 and input terminal A2
  • line L3 is used to connect transistor M5 and node N4
  • line L4 is used to connect node N2 and the transistor.
  • M4, line L5 is used to connect transistor M4 and transistor M5.
  • line L1 and line L2 are adjacent, so there is a short circuit defect Ds1 that needs to be tested between lines L1 and L2; line L2 and line L3 are adjacent, so there is a short circuit defect Ds1 that needs to be tested between line L2 and line L3.
  • Line L4 and line L5 are separated by transistor M5. The two lines are not adjacent to each other, so there is no short circuit defect that needs to be tested. Similarly, line L2 and line L5 are separated by transistor M5, and there is no short circuit defect that needs to be tested.
  • defect testing can be performed on all types of defects in the unit.
  • the N defects that may be determined in step 201 may include all types of defects.
  • defect testing may be performed on only some types of defects in the marked unit.
  • a user may only care about defects in a transistor. Therefore, only transistor normally-on defects and transistor-off defects need to be tested.
  • the N defects determined in step 201 may only include transistor normally-on defects and transistor turn-off defects.
  • M is the number of inputs the unit contains.
  • the unit 300 shown in Figure 3 includes three input terminals, so if the input vectors to the unit 300 include a total of 8, they are 000, 001, 010, 011, 100, 101, 110 and 111 respectively.
  • the simulation process in step 202 does not require annotation of defects that need to be tested. Therefore, the process of step 202 can also be called error-free simulation.
  • the simulation results of the error-free simulation of the unit include the voltage value of each node in the unit.
  • the list of all nodes of the unit circuit can be determined. In order to reduce the number of nodes, all nodes on the same connection path can be merged into one node. Then, generate the test simulation file (testbench). The simulation method of testbench can be to simulate transient simulation. Then, insert the voltage extraction statement of the node list into the generated testbench. Each node needs to be inserted. After completion, call the simulator to perform transient simulation on testbench. Finally, the simulation results are extracted to obtain the voltage value of each node under different input vectors.
  • the simulator may be a general analog circuit simulator (simulation program with integrated circuit emphasis, SPICE).
  • FIG. 6 is a schematic diagram of the unit 300 after marking defects that require defect testing.
  • Figure 6 shows a total of four defects that need to be tested, namely defects D1 to D4, where defect D1 is a transistor turn-off defect of transistor M1, defect D2 is an open-circuit defect, defect D3 is a short-circuit defect, and defect D4 is a transistor M6 defect. transistor normally open defect.
  • FIG. 6 only shows some defects in the partial circuit of the unit 300 shown in FIG. 3 .
  • the unit 300 shown in FIG. 3 may also include other defects. There are no defects shown that require testing. For example, in addition to transistor M6, each of transistors M1 to M5 needs to be tested for transistor normally-on defects; for another example, except for transistor M1, transistors M2 to transistor M6 all need to be tested for transistor turn-off defects.
  • Table 1 shows the error-free simulation results related to defects D1 to D4 shown in FIG. 6 .
  • the node N1 in the unit 300 is a node used to connect the power supply VDD, so the VDD in Table 1 is equivalent to the voltage of the node N1.
  • test vector used by each of the N defects in the error injection simulation where the test vector of each of the N defects includes 2 M input vectors. Partial input vector.
  • some input vectors can be selected from 2 M input vectors for each defect as input vectors used in error injection simulation. This can reduce the number of input vectors required for error injection simulation, thereby reducing the number of input vectors required for error injection simulation. time and computing resources.
  • the filtered input vectors used for error annotation simulation can be called test vectors.
  • the first voltage value among 2 M voltage values is the voltage value of node 1 under the first input vector among 2 M input vectors
  • the second voltage value among 2 M voltage values is under 2 The voltage value of node 1 under the second input vector among the M input vectors, and so on.
  • the input vector corresponding to the gate voltage can be used as the test vector for the normally open defect of the transistor corresponding to the transistor. Therefore, for any transistor (hereinafter may be referred to as the first transistor), if you want to determine the test vector for testing the normally-on transistor defect of the first transistor, you can determine from the error-free simulation results of the unit 2 M voltage values of the gate node of the first transistor (that is, the node to which the gate is connected). For convenience of description, the 2 M voltage value of the gate node of the first transistor may be called a first voltage value set.
  • a voltage capable of turning off the first transistor can be determined from the first set of voltage values according to the characteristics of the first transistor. value.
  • the input vector corresponding to the determined voltage value is the test vector used to test the normally-on transistor defect of the first transistor during the error injection simulation.
  • a normally-on transistor defect is when a transistor is turned on at a gate voltage that should cause the transistor to turn off. Therefore, the gate voltage that turns the transistor on is meaningless for testing normally open defects. Therefore, the input vector corresponding to the gate voltage that turns off the transistor is screened out as the test vector for the normally-on defect of the transistor.
  • Figure 7 is a circuit diagram when performing error injection simulation on the normally open defect of a transistor.
  • a short-circuit resistor R1 is added between the source and drain of transistor M6.
  • the test vector for the normally-on transistor defect of transistor M6 may be determined by determining from Table 1 the set of voltage values corresponding to the gate of transistor M6.
  • Input A3 provides the gate voltage of transistor M6. Therefore, it can be determined from Table 1 that the voltage value set includes the voltage values of input terminal A3 under 8 input vectors.
  • These 8 voltage values are: 0, 1, 0, 1, 0, 1, 0, 1. Since the transistor M6 is an NMOS transistor, the transistor M6 is turned on at a high level, so four high-level voltage values can be selected from these 8 voltage values, namely the 2nd, 4th, 6th and 8th. voltage values, the input vectors corresponding to these four voltage values are 001, 011, 101 and 111 respectively. Therefore, the input vectors 001, 011, 101 and 111 are the test vectors used to test the transistor normally open defect of transistor M6.
  • the input vector can be used for testing Test vector for transistor low turn-off defect of this transistor.
  • the first preset condition includes: the gate voltage causes the transistor to be turned on, and the drain or source is at a high level;
  • the second preset condition includes: the gate voltage causes the transistor to be turned off, and both the drain and the source are not at a low level.
  • the first preset condition since the gate voltage turns the transistor on, the voltages at the drain and source are the same.
  • the first preset condition only two voltage values need to be determined, one voltage value is one of the drain voltage value or the source voltage value, and the other voltage value is the gate voltage value.
  • the second preset condition since the gate voltage turns off the transistor, the voltage values of both the drain and the source need to be determined. Therefore, for the second preset condition, the gate voltage value, the source voltage value and the drain voltage value need to be determined.
  • the second transistor For any transistor (hereinafter may be referred to as the second transistor), if you want to determine the transistor low-level turn-off defect of the second transistor, you can determine the third transistor corresponding to the second transistor from the simulation results of the unit.
  • the second set of voltage values may include 2 M subsets.
  • the 2M subsets correspond to 2M input vectors one-to-one, and each subset of the 2M subsets includes the voltage of the gate node of the second transistor (that is, the node to which the gate is connected) under the corresponding input vector. value, the voltage value of the drain node (i.e. the node to which the drain is connected) and the voltage value of the source node (i.e. the node to which the source is connected).
  • the first subset of the 2 M subsets in the second voltage value set includes the gate voltage, source voltage and drain voltage of the second node under the first input vector of the 2 M input vectors.
  • the second subset of the 2 M subsets in the second voltage value set includes the gate voltage, source voltage and drain voltage of the second node under the second input vector of the 2 M input vectors, And so on.
  • a subset that can satisfy the first preset condition or the second preset condition can be determined from the second voltage value set according to the characteristics of the second transistor.
  • the input vector corresponding to the determined subset is the test vector used to test the transistor low-level turn-off defect of the second transistor during the error injection simulation.
  • the open-circuit resistor When testing a transistor for low-level turn-off defects, the open-circuit resistor is connected low. Therefore, if the gate voltage of a transistor causes the transistor to conduct, the source and drain voltages are the same. If the source and drain are both low voltage, it will be consistent with the voltage state during the error simulation. Therefore, the input vector corresponding to this set of voltages is meaningless for testing the low-level turn-off defects of the transistor. If the transistor is turned off, and both the drain and source voltages are low level, this state is consistent with the voltage state during the error simulation. Therefore, the input vector corresponding to this set of voltages is useful for testing the low-level turn-off defects of the transistor. Pointless.
  • the input vector can be used for testing Test vector for transistor low turn-off defect of this transistor.
  • the third preset condition includes: the gate voltage causes the transistor to be turned on, and the drain or source is at a low level;
  • the fourth preset condition includes: the gate voltage causes the transistor to be turned off, and both the drain and the source are not at a high level.
  • the third preset condition since the gate voltage turns the transistor on, the voltages at the drain and source are the same.
  • the third preset condition only two voltage values need to be determined, one voltage value is one of the drain voltage value or the source voltage value, and the other voltage value is the gate voltage value.
  • the gate voltage value since the gate voltage turns off the transistor, the voltage values of both the drain and the source need to be determined. Therefore, for the fourth preset condition, the gate voltage value, the source voltage value and the drain voltage value need to be determined.
  • the second transistor if you want to determine the transistor high level turn-off defect, then a subset that can satisfy the third preset condition or the fourth preset condition can be determined from the second voltage value set according to the characteristics of the second transistor.
  • the input vector corresponding to the determined subset is the test vector used to test the transistor high-level turn-off defect of the second transistor during the error injection simulation.
  • the open-circuit resistor When testing a transistor for high-level turn-off defects, the open-circuit resistor is connected high. Therefore, if the gate voltage of the transistor causes the transistor to turn on, the source and drain voltages are the same. If the source and drain are both high voltages, it is consistent with the voltage state during the error simulation. Therefore, this set of voltages corresponds to The input vector is meaningless for testing of transistor high-level turn-off defects. If the transistor is turned off, and both the drain and source voltages are high level, this state is consistent with the voltage state during the error simulation. Therefore, the input vector corresponding to this set of voltages is useful for testing the high-level turn-off defects of the transistor. Pointless.
  • Figure 8 shows a circuit diagram when performing error injection simulation on defect D1.
  • the defect D1 to be tested needs to be a transistor turn-off defect of the transistor M1. More specifically, the defect D1 that needs to be tested needs to be a transistor low-level turn-off defect and a transistor high-level turn-off defect of the transistor M1.
  • an open-circuit resistor R1 and an open-circuit resistor R4 to the drain and source of the transistor M1, respectively.
  • connect the pull-up/down resistors i.e., R2, R3, R5, and R6 shown in Figure 8 on both sides of the open-circuit resistor.
  • the test vector of the transistor low-level turn-off defect of transistor M1 and the test vector of the transistor high-level turn-off defect can be determined as follows:
  • the gate, drain and source voltages of transistor M1 are respectively: input terminal A1, node N2 and VDD. Therefore, the voltage value set corresponding to the transistor M1 can be determined from Table 1.
  • the voltage value set includes 8 subsets, and each of the 8 subsets includes voltage values of the input terminal A1, the node N2, and VDD respectively.
  • Table 2 shows the eight subsets included in the voltage value set corresponding to the transistor M1 and the corresponding relationship between the eight subsets and the input vector.
  • the transistor M1 is a PMOS transistor, so the transistor M1 is turned on at a low level, so if the first preset condition is met, then A1 is equal to 0, and N2 or VDD is equal to 1. It can be seen from Table 2 that subset 1 to subset 4 all satisfy the first preset condition. If the second preset condition is met, then A1 is equal to 1, and N2 and VDD cannot both be 0. It can be seen from Table 2 that subset 5 to subset 8 all satisfy the second preset condition. Therefore, the test vectors used to test transistor M1 for transistor low-level turn-off defects include all eight input vectors. If the third preset condition is met, then A1 is equal to 0 and N2 or VDD is equal to 0.
  • the input vector corresponding to the voltage can be used to test the low-level open circuit defect of the branch; if the uninjected simulation voltage of the branch If the wrong simulation voltage is low level, then the input vector corresponding to this voltage can be used to test the high-level open circuit defect of the branch. Therefore, for any target branch (hereinafter may be referred to as the first target branch), if you want to determine the test vector used to test the open circuit defect of the first target branch, you can start from the error-free simulation of the unit. From the results, 2 M voltage values of the nodes located on the first target branch are determined.
  • the 2M voltage values of the nodes located on the first target branch may be called a third voltage value set.
  • the high level and the low level in the third voltage value set can be determined respectively, wherein the input vector corresponding to the high level in the third voltage value set can be used to test the third voltage value set.
  • the input vector corresponding to the low level in the third voltage value set can be used to test the high-level open circuit defect of the first busy branch.
  • the voltage value of the open resistor When testing low-level open defects, the voltage value of the open resistor is low. At this time, if the voltage value on the first target branch is also If it is low, it cannot be determined whether the branch has an open circuit defect. Therefore, it is necessary to select the input vector corresponding to the high level to test the low-level open circuit defect. Similarly, when testing high-level open defects, the voltage value of the open resistor is high. At this time, if the voltage value on the first target branch is also high, it cannot be determined whether the branch has an open circuit defect. Therefore, it is necessary to select the input vector corresponding to the low level to test the high-level open circuit defect.
  • Figure 9 shows a circuit diagram when performing error injection simulation on defect D2.
  • the defect D2 that needs to be tested is an open defect of the branch containing node N4. More specifically, the defect D4 that needs to be tested is the low-level open defect and the high-level open defect of the branch including the node N3.
  • an open-circuit resistor R1 to the branch, and connect pull-up/down resistors (i.e., R2 and R3 in Figure 9) on both sides of the open-circuit resistor R1.
  • resistors R2 and R3 are both pull-down resistors; if high-level open circuit defects are to be tested, resistors R2 and R3 are both pull-up resistors.
  • the test vector used to test the open circuit defect corresponding to this branch can be determined as follows: Determine the voltage value of node N3 under 8 input vectors from Table 1. The eight voltage values are 0, 0, 0, 0, 1, 1, 1, 0 respectively. Among these 8 voltage values, the 5th to 7th voltage values are high level, and the 1st, 2nd, 3rd, 4th and 8th voltage values are low level.
  • the input vectors corresponding to the 5th to 7th voltage values are test vectors used to test low-level open circuit defects; the 1st, 2nd, 3rd, 4th, and 8th
  • the input vectors corresponding to the voltage values are test vectors used to test high-level open circuit defects.
  • the input vectors corresponding to the two voltage values can be used as the test vector for the short-circuit defect corresponding to the pair of nodes. Therefore, if you want to determine the short circuit defect corresponding to any pair of nodes (hereinafter referred to as the first node pair), you can determine the fourth voltage value set corresponding to the first node pair from the simulation results of the unit .
  • the fourth combination of voltage values includes 2M subsets, the 2M subsets are in one-to-one correspondence with the 2M subsets and the 2M input vectors, and each subset in the 2M subsets includes a The voltage values of the two nodes included in the first node pair.
  • the first subset of the 2M subsets in the second voltage value set includes the voltage values of the two nodes included in the first node pair under the first input vector of the 2M input vectors
  • the first subset The second subset of the 2 M subsets in the two voltage value sets includes the voltage values of the two nodes included in the first node pair under the second input vector of the 2 M input vectors, and so on.
  • a subset containing different voltage values is determined from the second voltage value set.
  • the input vector corresponding to the determined subset is the test vector used to test the short circuit defect corresponding to the first node pair during error injection simulation.
  • Figure 10 shows the circuit diagram when performing error injection simulation on defect D3.
  • the defect D3 that needs to be tested is a short-circuit defect between the gate node of the transistor M5 and the node N4.
  • a short-circuit resistor was inserted into the gate node of transistor M5 and node N4.
  • the test vector used to test the short circuit defect can be determined as follows: determine the set of voltage values from Table 1.
  • the combination of voltage values includes 8 subsets, and each subset of the 8 subsets includes the input terminal A2 and the node N4 respectively. voltage value.
  • Table 3 shows the 8 subsets and the correspondence between these 8 subsets and the input vector.
  • the input vectors are test vectors used to test the gate node of transistor M5 and the node N4 for short-circuit defects.
  • Table 4 summarizes the test vectors for each of the four defects shown in Figure 6.
  • D1_0 in Table 4 represents the transistor turn-off low-level defect in defect D1
  • D1_1 represents the transistor turn-off high-level defect in defect D1
  • D2_0 represents the low-level open circuit defect of defect D2
  • D2_1 represents the high-level defect of defect D2. Open circuit defects.
  • Defect annotation simulation files can be generated based on the determined test vectors.
  • the error injection simulation is implemented by reading the error injection simulation file with a simulator (such as SPICE), which contains the test vector of each defect generated in the previous step.
  • the simulation results of the error-injection simulation include the voltage values of the unit's output terminal under each test vector after the error-injection. For a defect, if the result of the error-injection simulation is different from the result of the simulation without error-injection, then the test vector corresponding to this voltage value can be used as the actual test vector of the defect.
  • Table 5 shows the simulation results of the four defects shown in Figure 6.
  • the test vector corresponding to the defect includes all 8 input vectors. Therefore, each of the eight input vectors has a voltage value in Table 5, which is the voltage value of the output terminal Z of the unit (ie, the voltage value of node N2).
  • the voltage value corresponding to vector 011 in Table 5 is different from the voltage value of node N2 corresponding to vector 011 in Table 1. Therefore, 011 can be used as the actual test vector for the transistor low-level turn-off defect of defect D1.
  • the test vector corresponding to the defect only includes the input vector 111. Therefore, only the input vector 111 has a corresponding voltage value in Table 5, which is the voltage value of the output terminal Z of the unit (ie, the voltage value of node N2).
  • the voltage value corresponding to vector 111 is the same as the voltage value of node N2 corresponding to vector 111 in Table 1.
  • the actual test vector of the transistor high-level turn-off defect of defect D1 is empty.
  • the test vectors corresponding to this defect include 100, 101 and 110. Therefore, each of these three input vectors has a voltage value in Table 5, which is the voltage value of the output terminal Z of the unit (that is, the voltage value of node N2). The voltage values of the corresponding node N2 in Table 1 and Table 3 for these three input vectors are all the same.
  • the actual test vector of the low-level open defect of defect D2 is empty.
  • the test vectors corresponding to this defect include 000, 001, 010, 011 and 111. Therefore, each of the five input vectors has a voltage value in Table 5, which is the voltage value of the output terminal Z of the unit (ie, the voltage value of node N2).
  • the voltage values of the node N2 corresponding to the four input vectors 000, 001, 010 and 011 in Table 1 and Table 5 are the same.
  • the voltage value corresponding to the input vector 111 in Table 5 is the same as the voltage value of the node N2 corresponding to the vector 111 in Table 1. The voltage values are different. Therefore, the actual test vector for the low-level open defect of defect D2 is 111.
  • the test vectors corresponding to this defect include 010, 011 and 111. Therefore, each of the three input vectors has a voltage value in Table 5.
  • This voltage value is the voltage value of the output terminal Z of the unit (that is, the voltage value of node N2).
  • the voltage values of node N2 corresponding to the two input vectors 010 and 011 in Table 1 and Table 5 are the same.
  • the voltage value corresponding to input vector 111 in Table 5 is the same as that of Table 1.
  • the voltage value of the node N2 corresponding to the vector 111 is different. Therefore, the actual test vector for defect D3 is 111. .
  • the test vectors corresponding to this defect include 000, 010, 100 and 110. Therefore, each of the four input vectors has a voltage value in Table 5.
  • This voltage value is the voltage value of the output terminal Z of the unit (that is, the voltage value of node N2). Compared with the voltage value of node N2 in Table 1, the voltage values of node N2 corresponding to the three input vectors 000, 010 and 100 in Table 1 and Table 5 are the same.
  • the voltage value corresponding to input vector 110 in Table 5 is the same as The voltage value of node N2 corresponding to vector 110 in Table 1 is different. Therefore, the actual test vector for defect D4 is 110.
  • Table 6 shows the actual test vectors for defects D1 to D4.
  • the actual test vectors After the actual test vectors are determined, the actual test vectors can be merged, and then the defect description model is determined and output based on the merged test vectors.
  • the actual test vector merging method and the defect description model output method are the same as the existing methods. For the sake of simplicity, they will not be described again here.
  • FIG. 11 is a schematic structural block diagram of a unit testing device provided according to an embodiment of the present application.
  • the unit testing device 1100 shown in FIG. 11 includes a processing module 1101 and a simulation module 1102.
  • the processing module 1101 is used to determine N defects that need to be tested for defects in the unit during error injection simulation, where N is a positive integer greater than or equal to 1.
  • the simulation module 1102 is used to perform an error-free simulation on the unit based on 2 M input vectors to obtain an error-free simulation result of the unit, where the unit includes M input terminals, and M is a positive input terminal greater than or equal to 1. integer.
  • the processing module 1101 is also configured to determine the test vector used by each of the N defects in the error-injection simulation according to the error-free simulation result of the unit, wherein the test of at least one defect among the N defects
  • the vectors include some of the 2 M input vectors.
  • the processing module 1101 and the simulation module 1102 can be implemented by instructions or program codes in the form of software, for example, by a combination of hardware and software modules in a processor.
  • the software module can be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other mature storage media in this field.
  • the storage medium is located in the memory, and the processor reads the information in the memory and implements the processing module 1101 and the simulation module 1102 in combination with its hardware.
  • the specific functions and beneficial effects of the processing module 1101 and the simulation module 1102 can be referred to the descriptions in the above embodiments. For the sake of brevity, they will not be described again here.
  • Embodiments of the present application also provide a computer device, which includes a processor, and the processor is configured to be coupled with a memory, read and execute instructions and/or program codes in the memory, to perform any of the implementations in the above embodiments.
  • a computer device which includes a processor, and the processor is configured to be coupled with a memory, read and execute instructions and/or program codes in the memory, to perform any of the implementations in the above embodiments. The method described in the example.
  • Embodiments of the present application also provide a chip system.
  • the chip system includes a logic circuit that is coupled to an input/output interface and transmits data through the input/output interface to execute any one of the above embodiments. the method described.
  • the processor in the embodiment of the present application may be an integrated circuit chip with signal processing capabilities.
  • each step of the above method embodiment can be completed by an integrated logic circuit of hardware in the processor or instructions or program codes in the form of software.
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • the steps of the method disclosed in conjunction with the embodiments of the present application can be directly implemented by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other mature storage media in this field.
  • the storage medium is located in the memory, and the processor reads the information and complete the steps of the above method in conjunction with its hardware.
  • non-volatile memory can be read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically removable memory. Erase electrically programmable read-only memory (EPROM, EEPROM) or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache.
  • RAM random access memory
  • RAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • double data rate SDRAM double data rate SDRAM
  • DDR SDRAM double data rate SDRAM
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous link dynamic random access memory
  • direct rambus RAM direct rambus RAM
  • the present application also provides a computer program product.
  • the computer program product includes: computer program code.
  • the computer program code When the computer program code is run on a computer, it causes the computer to execute any one of the above embodiments. Example methods.
  • the present application also provides a computer-readable medium.
  • the computer-readable medium stores program code.
  • the program code When the program code is run on a computer, it causes the computer to execute any one of the above embodiments. Example methods.
  • the disclosed systems, devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product.
  • the computer software product is stored in a storage medium, including A number of instructions or program codes are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program code. .

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Abstract

本申请实施例提供一种测试单元的方法和相关装置，该方法包括：对单元中需要进行缺陷测试的N个缺陷进行无注错仿真，得到该单元的无注错仿真结果；根据该单元的无注错仿真结果，确定该N个缺陷中的每个缺陷在该注错仿真时使用的测试向量，其中该N个缺陷中的至少一个缺陷的测试向量包括2M个输入向量中的部分输入向量，M是该单元包括的输入端口的数量，M和N为大于或等于1的正整数。上述技术方案可以减少用于单元缺陷模型生成的注错仿真输入向量数目，从而减少单元缺陷模型生成中模拟瞬态仿真的时间消耗，进而可以更快地得到单元的缺陷模型。

Description

测试单元的方法和相关装置
本申请要求于2022年08月04日提交中国专利局、申请号为202210930926.5、申请名称为“测试单元的方法和相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及芯片技术领域，更具体地，涉及电子设计自动化中测试单元的方法和相关装置。
背景技术
芯片的自动化测试是芯片流入市场前的重要环节，高的测试覆盖率能够有效降低故障芯片未被检测出的概率。同时，故障诊断技术也是芯片生产制造过程中的重要环节，对芯片的物理失效分析和良率提升均有辅助作用。在电子设计自动化中(electronic design automation，EDA)中，为了对芯片进行自动化测试和诊断，需要对芯片内的故障进行建模。业界常用的故障模型均假设故障发生于单元外部。传统的自动测试和诊断技术/工具通常针对这些故障模型进行设计和实现。但是，随着工艺节点的演进和单元的大量应用，越来越多的芯片内故障被发现于单元的内部，传统的工具无法准确的测试和定位这类故障。
为了解决上述问题，业内提出了单元-感知(cell-aware)的测试和诊断技术/工具。为了达到cell-aware的目的，需要建立单元-内部(cell-internal)的单元缺陷描述模型。近些年已出现集成或独立的生成单元缺陷描述模型的工具，这些工具以工艺库文件作为输入，通过网表分析算法和仿真器仿真产生故障描述文件，用于cell-aware的测试和诊断。在工具对一个工艺库进行处理时，工艺库通常包含大量的单元，而每个单元包含的内部缺陷数量成百上千，同时单元所有可能输入组合均需要进行仿真器模拟瞬态仿真。考虑到模拟瞬态仿真消耗时间相对较长，生成整个工艺库的缺陷描述文件通常消耗大量的时间和计算资源。
发明内容
本申请实施例提供一种测试单元的方法和相关装置，能够减少用于单元缺陷模型生成的注错仿真输入向量数目，从而减少单元缺陷模型生成中模拟瞬态仿真的时间消耗，进而可以更快地得到单元的测试结果。
第一方面，本申请实施例提供一种测试单元的方法，包括：对单元中需要进行缺陷测试的N个缺陷进行无注错仿真，得到该单元的无注错仿真结果；根据该单元的无注错仿真结果，确定该N个缺陷中的每个缺陷在该注错仿真时使用的测试向量，其中该N个缺陷中的至少一个缺陷的测试向量包括2M个输入向量中的部分输入向量，M是该单元包括的输入单的数量，M和N为大于或等于1的正整数。
上述技术方案可以对缺陷进行注错仿真时使用的测试向量进行筛选，以减少每个缺陷在注错仿真时使用的测试向量数目。这样，可以减少每个缺陷注错仿真的次数，从而减少该单元的总注错仿真次数。由于总注错仿真次数减少，仿真的时间消耗也就相应减少，进而可以更快地得到单元的缺陷模型。
结合第一方面，在第一方面的一种可能的实现方式中，该确定单元中需要进行缺陷测试的N个缺陷，包括：根据该单元包括的多个晶体管，确定该N个缺陷中包括N1个晶体管常开缺陷，其中该多个晶体管包括N1个目标晶体管，该N1个目标晶体管与该N1个晶体管常开缺陷一一对应，该N1个目标晶体管为该多个晶体管单元中除寄生晶体管和无效晶体管以外的晶体管。
寄生晶体管是由于单元中的线路的电气特性产生的晶体管，而无效晶体管是便于芯片制造而设置的晶体管。这两种晶体管的缺陷不会影响单元的功能。因此，无需对这两种晶体管进行缺陷测试。上述技术方案在确定需要进行缺陷测试的缺陷时排除了这两种无需进行测试的晶体管，从而可以减少需要测试的缺陷数目。
结合第一方面，在第一方面的一种可能的实现方式中，该根据该单元的无注错仿真结果，确定该N个缺陷中的每个缺陷在该注错仿真时使用的测试向量，包括：从该单元的无注错仿真结果中确定与第 一目标晶体管对应的第一电压值集合，其中该第一目标晶体管是该N1个目标晶体管中的任一个目标晶体管，该第一电压值集合包括的2M个第一电压值与该2M个输入向量一一对应，该第一电压值集合包括的2M个第一电压值中的每个第一电压值是在对应的输入向量下该第一目标晶体管的栅极电压；确定该第一电压值集合包括的2M个第一电压值中使得该第一目标晶体管关断的第一电压值对应的输入向量为第一测试向量，该第一测试向量是用于测试该第一目标晶体管的晶体管常开缺陷的测试向量。
晶体管常开缺陷是晶体管在本应使得晶体管关断的栅极电压下处于导通状态。因此，使得晶体管导通的栅极电压对于常开缺陷的测试并没有意义。所以筛选出使得晶体管关断的栅极电压对应的输入向量作为晶体管常开缺陷的测试向量。通过上述方案，可以减少用于测试晶体管常开缺陷的输入向量数目，从而减少晶体管常开缺陷的仿真次数。
结合第一方面，在第一方面的一种可能的实现方式中，该确定单元中需要进行缺陷测试的N个缺陷，包括：根据该单元包括的多个晶体管，确定该N个缺陷中包括N1个晶体管低电平关断缺陷和N1个晶体管高电平关断缺陷，其中该多个晶体管包括N1个目标晶体管，该N1个目标晶体管与该N1个晶体管低电平关断缺陷一一对应，该N1个目标晶体管与该N1个晶体管高电平关断缺陷一一对应，该目标晶体管为该多个晶体管中除寄生晶体管和无效晶体管以外的晶体管，该晶体管低电平关断缺陷用于测试晶体管在开路电阻连接低电平的情况下的关断缺陷，该晶体管高电平关断缺陷用于测试晶体管在开路电阻连接高电平的情况下的关断缺陷。
寄生晶体管是由于单元中的线路的电气特性产生的晶体管，而无效晶体管是便于芯片制造而设置的晶体管。这两种晶体管的缺陷不会影响单元的功能。因此，无需对这两种晶体管进行缺陷测试。上述技术方案在确定需要进行缺陷测试的缺陷时排除了这两种无需进行测试的晶体管，从而可以减少需要测试的缺陷数目。
结合第一方面，在第一方面的一种可能的实现方式中，该根据该单元的无注错仿真结果，确定该N个缺陷中的每个缺陷在该注错仿真时使用的测试向量，包括：从该单元的无注错仿真结果中确定与第二目标晶体管对应的第二电压值集合，其中该第二目标晶体管是该N1个目标晶体管中的任一个目标晶体管，该第二电压值集合包括的2M个子集与该2M个输入向量一一对应，该第二电压值集合包括的2M个子集中的每个子集包括在对应的输入向量下该第二目标晶体管的栅极电压、漏极电压和源极电压；确定该第二电压值集合包括的2M个子集中满足第一预设条件或第二预设条件的子集对应的输入向量为第二测试向量，该第二测试向量是用于测试该第二晶体管的晶体管低电平关断缺陷的测试向量，该第一预设条件包括：该第二目标晶体管的栅极电压使该第二目标晶体管导通且该第二目标晶体管的源极或漏极为高电平，该第二预设条件包括：该第二目标晶体管的栅极电压使该第二目标晶体管关断且该第二目标晶体管的源极和漏极不全为低电平；确定该第二电压值集合包括的2M个子集中满足第三预设条件或第四预设条件的子集对应的输入向量为第三测试向量，该第三测试向量是用于测试该第二晶体管的晶体管高电平关断缺陷的测试向量，该第三预设条件包括：该第二目标晶体管的栅极电压使该第二目标晶体管导通且该第二目标晶体管的源极或漏极为低电平，该第四预设条件包括：该第二目标晶体管的栅极电压使该第二目标晶体管关断且该第二目标晶体管的源极和漏极不全为高电平。
在测试晶体管低电平关断缺陷时，开路电阻连接低电平。因此，如果晶体管的栅极电压使得晶体管导通，源极和漏极电压相同。若源极和漏极都是低电压，则与注错仿真时的电压状态一致，因此这一组电压对应的输入向量对于晶体管低电平关断缺陷的测试没有意义。如果晶体管关断，且漏极和源极电压均为低电平，则该状态与注错仿真时的电压状态一致，因此这一组电压对应的输入向量对于晶体管低电平关断缺陷的测试没有意义。在测试晶体管高电平关断缺陷时，开路电阻连接高电平。因此，如果晶体管的栅极电压使得晶体管导通，源极和漏极电压相同，若源极和漏极都是高电压，则与注错仿真时的电压状态一致，因此这一组电压对应的输入向量对于晶体管高电平关断缺陷的测试没有意义。如果晶体管关断，且漏极和源极电压均为高电平，则该状态与注错仿真时的电压状态一致，因此这一组电压对应的输入向量对于晶体管高电平关断缺陷的测试没有意义。通过上述方案，可以减少用于测试晶体管关断缺陷的输入向量数目，从而减少晶体管关断缺陷的仿真次数。
结合第一方面，在第一方面的一种可能的实现方式中，该确定单元中需要进行缺陷测试的N个缺陷，包括：根据该单元包括的寄生电阻，确定该N个缺陷中包括N2个低电平开路缺陷和N2个高电平开路缺陷，其中该单元包括N2个目标支路，该目标支路是该单元中包括一个或多个该寄生电阻的支路， 该低电平开路缺陷用于测试开路电阻连接低电平的情况下的开路缺陷，该高电平开路缺陷用于测试开路电阻连接高电平的情况下的开路缺陷。
上述技术方案将一个包括多个寄生电阻的目标支路视为一个待测试的缺陷，而非将该多个寄生电阻视为多个待测试的缺陷。这样，可以减少需要进行测试的缺陷数目。
结合第一方面，在第一方面的一种可能的实现方式中，该根据该单元的无注错仿真结果，确定该N个缺陷中的每个缺陷在该注错仿真时使用的测试向量，包括：从该单元的无注错仿真结果中确定与第一目标支路对应的第三电压值集合，其中该第一目标支路是该N2个目标支路中的任一个支路，该第三电压值集合包括的2M个第二电压值与该2M个输入向量一一对应，该第三电压值集合包括的2M个第二电压值中的每个第二电压值是在对应的输入向量下该第一目标支路的电压值；确定该第三电压值集合包括的2M个第二电压值中的高电平对应的输入向量为第四测试向量，该第四测试向量是用于测试该第一目标支路的低电平开路缺陷的测试向量；确定该第三电压值集合包括的2M个第二电压值中的低电平对应的输入向量为第五测试向量，该第五测试向量是用于测试该第一目标支路的高电平开路缺陷的测试向量。
在测试低电平开路缺陷时，开路电阻的电压值为低。此时，如果该第一目标支路上的电压值也为低，则无法确定该支路是否存在开路缺陷。所以需要选择高电平对应的输入向量来测试低电平开路缺陷。类似的，在测试高电平开路缺陷时，开路电阻的电压值为高。此时，如果该第一目标支路上的电压值也为高，则无法确定该支路是否存在开路缺陷。所以需要选择低电平对应的输入向量来测试高电平开路缺陷。通过上述方案，可以减少用于测试开路缺陷的输入向量数目，从而减少开路缺陷的仿真次数。
结合第一方面，在第一方面的一种可能的实现方式中，该确定单元中需要进行缺陷测试的N个缺陷，包括：确定该单元包括K对节点，该K对节点中的每对节点包括两个不同的节点，K为大于或等于1的正整数；根据该单元中的元件的坐标信息，从该K对节点中确定出N3对节点，该N3对节点中的每对节点包括两个相邻的节点；确定该N个缺陷中包括N3个短路缺陷，其中该N3个短路缺陷与该N3对节点一一对应。
相邻的节点是指两个节点之间没有其他元件(例如寄生电阻、晶体管等)或者节点。短路缺陷通常只考虑相邻节点间的，而不相邻的两个节点之间的短路缺陷不做考虑。因此，上述技术方案可以减少需要测试短路缺陷的缺陷数目。
结合第一方面，在第一方面的一种可能的实现方式中，该根据该单元的无注错仿真结果，确定该N个缺陷中的每个缺陷在该注错仿真时使用的测试向量，包括：从该单元的无注错仿真结果中确定与第一节点对对应的第四电压值集合，其中该第一节点对是该N3对节点中的任一对节点，该第四电压值包括的2M个子集与该2M个输入向量一一对应，该第四电压值集合包括的2M个子集中的每个子集包括在对应的输入向量下该第一节点对中的两个节点的电压值；确定该第四电压值包括的2M个子集中包括有不同电压值的子集对应的输入向量是第六测试向量，该第六测试向量是用于测试该第一节点对的短路缺陷的测试向量。
在测试短路缺陷时，需要在测试的一对节点之间插入短路电阻。所以如果输入向量能使得这两个节点电压值相同，那么就无法确定这两个节点是否存在短路。因此，只有使得这两个节点电压值不同的输入向量才能判断出这包含这两个节点的线路是否存在短路缺陷。通过上述方案，可以减少用于测试短路缺陷的输入向量数目，从而减少短路缺陷的仿真次数。
结合第一方面，在第一方面的一种可能的实现方式中，该方法还包括：对该单元进行注错仿真，得到该单元的注错仿真结果；根据该单元的无注错仿真结果和该单元的注错仿真结果，确定该N个缺陷中的每个缺陷的实际测试向量，其中，该N个缺陷中的每个缺陷的实际测试向量的无注错仿真结果与注错仿真结果不同；根据该N个缺陷中的每个缺陷的实际测试向量，生成该单元的缺陷描述模型。
第二方面，本申请实施例提供一种单元测试的装置，该装置包括用于实现第一方面或第一方面的任一种可能的实现方式的模块。
第三方面，本申请实施例提供一种计算机可读存储介质，该计算机可读存储介质存储有程序代码，当该计算机存储介质在计算机上运行时，使得计算机执行如第一方面或第一方面的任一种可能的实现方式。
第四方面，本申请实施例提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得该计算机执行如第一方面或第一方面的任一种可能的实现方式。
第五方面，本申请实施例提供一种计算机设备，该计算机设备包括处理器，该处理器用于与存储器耦合，读取并执行该存储器中的指令和/或程序代码，以执行第一方面或第一方面的任一种可能的实现方式。
第六方面，本申请实施例提供一种芯片系统，该芯片系统包括逻辑电路，该逻辑电路用于与输入/输出接口耦合，通过该输入/输出接口传输数据，以执行第一方面或第一方面任一种可能的实现方式。
附图说明
图1是生成缺陷描述模型的流程图。
图2是根据本申请实施例提供的一种测试单元的方法的示意性流程图。
图3是单元的部分结构性示意图。
图4是图3所示的单元300中的寄生电阻的示意图。
图5是图3所示的单元300中的晶体管M4和晶体管M5的版图示意图。
图6是标注了需要进行缺陷测试的缺陷后的单元300的示意图。
图7是对晶体管常开缺陷进行注错仿真时的电路图。
图8是对缺陷D1进行注错仿真时的电路图。
图9是对缺陷D2进行注错仿真时的电路图。
图10是对缺陷D3进行注错仿真时的电路图。
图11是根据本申请实施例提供的一种单元测试的装置的示意性结构框图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
本申请实施例中的单元(cell)是一组提供布尔逻辑功能(例如，与、或、非、与或、与非、反相器等)或存储功能(触发器或锁存器)的晶体管和互连结构。本申请实施例中所称的单元可以是标准单元(standard cell，std cell)、特殊的标准单元(例如，填充单元、电压钳位单元、阱连接单元、隔离单元等)、模块宏单元、输入输出单元(input output pad cell)，或者其他包含晶体管和互连结构的电路结构。
图1是生成缺陷描述模型的流程图。图1所示的方法可以由计算机设备执行。该计算机设备可以是台式计算机、笔记本计算机、服务器等。在一些实施例中，图1所示的所有步骤都可以由同一个计算机设备执行。在另一些实施例中，图1中的不同步骤可以由不同的计算机设备执行。例如，第一计算机设备可以执行步骤101以获得缺陷列表，并将该缺陷列表发送至第二计算机设备。该第二计算机设备根据该缺陷列表执行步骤102以得到注错仿真结果并将该注错仿真结果发送给第一计算机设备。第一计算机设备执行步骤103和步骤104得到缺陷描述模型。此外，图1所示的方法也可以由一个或多个计算机设备中的部件(例如芯片或芯片系统等)执行。
101，对单元进行缺陷抽取，得到缺陷列表。
缺陷列表中记录了单元中可能出现的缺陷。这些缺陷就是需要进行缺陷测试的缺陷。单元常见的缺陷包括：晶体管常开缺陷、关断缺陷、开路缺陷和短路缺陷。
102，根据缺陷列表，对单元进行注错仿真，得到注错仿真结果。
一个单元包括的输入向量数量与该单元的输入端数量相关。单元的么每个输入端的输入信号可以是1或者0。因此，如果单元仅包括1个输入端，那么该单元可以包括两个输入向量，分别是0和1；如果单元包括2个输入端，那么该单元可以包括四个输入向量，分别是00，01，10和11；如果单元包括M个输入端，那么该单元可以包括2M个输入向量，M是大于或等于1的正整数。
注错仿真的次数与缺陷列表包括的需要进行缺陷测试的缺陷个数以及输入向量有关。每一次注错仿真只针对一个缺陷的一个输入向量进行仿真。因此，如果缺陷列表中包括X个缺陷，那么总共需要进行X×2M次注错仿真才能完成单元的注错仿真。通常情况下，一个单元可能包括几百甚至上千个缺 陷。如果对每个缺陷进行2M次注错仿真，可能需要几千甚至上万次注错仿真。例如，如果单元包括800个缺陷且该单元包括3个输入端，那么该标注单元总共需要进行800×8＝6400次注错仿真才能得到最终的注错仿真结果。
103，根据注错仿真结果，合并测试向量。
根据注错仿真结果，可以筛选出用于每个缺陷的测试的输入向量(可以称为实际测试向量)。合并测试向量可以简化测试向量数量。例如，如果筛选出的实际测试向量包括111和110。在此情况下，可以将这两个输入向量合并成为11x，这样可以简化最终输出到实际测试向量的数量。
104，根据合并后的测试向量，输出缺陷描述模型。
缺陷描述模型输出过程将单元缺陷的相关信息打印输出到文件中。通过扫描缺陷列表将每个缺陷的信息依次打印。缺陷的信息包括但不限于：缺陷的名称，缺陷对应的节点，假设的缺陷电阻值，缺陷的实际测试向量和单元的输出端的输出的输出值(可以称为注错仿真值)，缺陷的物理信息等。缺陷的物理信息包括缺陷的坐标和缺陷的层等。
可以看出，在图1所示的方法中，对于单元中的每个缺陷都需要使用全部的输入向量进行注错仿真。因此，需要花费大量的时间进行注错仿真并且消耗大量的计算资源，从而导致生成缺陷描述模型的时间较长且消耗的计算资源较多。
本申请实施例提供一种测试单元的方法，可以减少进行注错仿真时使用的输入向量，从而可以减少注错仿真消耗的时间和计算资源。下面结合图2至图10对本申请实施例进行介绍。
图2是根据本申请实施例提供的一种测试单元的方法的示意性流程图。图2所示的方法可以由计算机设备或计算机设备中的部件(例如芯片或芯片系统等)执行。
201，确定单元在注错仿真时需要进行缺陷测试的N个缺陷，N是大于或等于1的正整数。
单元可以用网表描述，网表中记录了单元中存在的各个元件，例如晶体管以及晶体管之间的连接关系等。该单元还可以用寄生网表描述，寄生网表除了记录有单元中包括的各个元件和元件间的连接关系以外，还记录了寄生元件(例如寄生电容、寄生电阻、寄生晶体管等)、寄生元件之间的连接关系以及寄生元件和单元中的各个元件的连接关系。为了便于区分，可以将前一种网表称为实际网表，将该实际网表中记录的元件称为实际元件。网表和寄生网表中还包括用于连接元件的节点(net)。除非特殊说明，本申请实施例中所称的元件可以包括实际元件和寄生元件。
在一些实施例中，可以从工艺制程单元库中获取库文件得到该单元的寄生网表，通过该寄生网表获取该单元包括的元件类型以及元件之间的连接关系。
该单元包括的元件的位置信息可以根据该寄生网表获取。该寄生网表中记录有每个元件的尺寸和位置信息。根据元件的尺寸和位置信息，可以确定元件在物理版图上的位置。
该单元中需要进行缺陷测试的N个缺陷可以根据该单元包括的元件类型、元件的连接关系以及元件的位置信息确定。单元常见的缺陷包括：晶体管常开缺陷、关断缺陷、开路缺陷和短路缺陷。
晶体管常开缺陷，也可以称为晶体管漏电缺陷或晶体管常开/漏电缺陷，可以简称为常开缺陷、漏电缺陷或常开/漏电缺陷。本申请实施例中所称的晶体管可以是场效应晶体管(filed effect transistor，FET)、N型金属-氧化物-半导体(N-type metal-oxide-semiconductor，NMOS)晶体管(可以简称为NMOS管)、P沟道金属-氧化物-半导体(P-channel metal–oxide–semiconductor)晶体管(可以简称为PMOS管)等。以NMOS管为例，若栅源极电压(可以称为Vgs)大于或等于电压阈值(可以称为Vth)，则NMOS管导通；若Vgs小于Vth，则NMOS关断。常开缺陷是指晶体管始终处于导通状态。换句话说，即使Vgs小于Vth，NMOS管也处于导通状态。
在一些实施例中，单元中的每个晶体管可以对应一个晶体管常开缺陷。在此情况下，可以通过该单元的寄生网表，确定出该单元包括的晶体管数目，从而确定该单元包括的晶体管常开缺陷数目以及每个晶体管常开缺陷对应的晶体管。例如，如果单元中包括Nt个晶体管，那么这个单元可以包括Nt个晶体管常开缺陷。
单元中通常会包括一些寄生晶体管和无效(dummy)晶体管。寄生晶体管是由于单元中的线路的电气特性产生的晶体管，而无效晶体管是便于芯片制造而设置的晶体管。这两种晶体管的缺陷不会影响单元的功能。因此，无需对这两种晶体管进行缺陷测试。所以，在另一些实施例中，可以只确定出除寄生晶体管和无效晶体管以外的晶体管。为了便于描述，可以将这种晶体管(即单元中除寄生晶体管 和无效晶体管以外的晶体管)称为目标晶体管。每一个目标晶体管可以对应一个晶体管常开缺陷。上述技术方案可以减少不必要的晶体管常开缺陷测试。
可选的，在一些实施例中，单元包括的目标晶体管可以根据该单元的寄生网表。该单元的寄生网表中包括该单元的所有晶体管的信息。因此，根据该单元的寄生网表，确定出该单元包括的全部目标晶体管。
可选的，在另一些实施例中，单元的目标晶体管可以根据该单元的网表确定。与寄生网表相比，单元的网表只是缺少了寄生元件的相关信息。单元包括的寄生晶体管是不需要进行缺陷测试的。换言之，该单元包括的所有需要进行缺陷测试的晶体管(即目标晶体管)的相关信息都会被记录在该单元的网表中。因此，可以直接根据该单元包括的网表确定该单元包括的所有目标晶体管。
晶体管关断缺陷，也可以简称为关断缺陷。与常开缺陷相反，关断缺陷是指晶体管始终处于关断状态。还以NMOS管为例，即使Vgs大于或等于Vth，NMOS管也处于关断状态。
在测试晶体管的晶体管关断缺陷时，需要在晶体管的漏极和源极分别添加开路电阻。同时，在开路电阻两侧均连接上/下拉电阻。晶体管关断缺陷还可以进一部分为晶体管低电平关断缺陷和晶体管高电平关断缺陷，晶体管低电平关断缺陷是开路电阻连接低电平情况下的关断缺陷，晶体管高电平关断缺陷是用于测试开路电阻连接高电平情况下的关断缺陷。开路电阻低电平是指开路电阻两端均为低电平，开率电阻高电平是指开路电阻两端均为高电平。因此，每个晶体管可以对应一个晶体管低电平关断缺陷和一个晶体管高电平关断缺陷。
与晶体管常开缺陷类似，在一些实施例中，可以单元中的每个晶体管可以对应一个晶体管低电平关断缺陷和一个晶体管高电平关断缺陷。
在另一些实施例中，可以只确定目标晶体管包括晶体管关断缺陷。换句话说，一个目标晶体管包括一个晶体管低电平关断缺陷和一个晶体管高电平关断缺陷。
因此，假设单元中包括N1个目标晶体管，那么这N1个目标晶体管需要测试的缺陷(也可以称为对应于N1个目标晶体管的缺陷)包括：N1个晶体管常开缺陷，N1个晶体管低电平关断缺陷和N1个晶体管高电平关断缺陷。
图3示出了单元包含的部分晶体管。如图3所示，单元300包括6个晶体管，分别为M1至M7，其中M1、M2和M3为PMOS管，M4、M5和M6为NMOS管。单元300共有三个输入端，分别为A1、A2和A3。如图2所示，除了用于连接输入端的节点以外，标注单元300还包括N1至N4共四个节点，其中晶体管M1的源极、晶体管M2的源极和晶体管M3的源极连接至节点N1，节点N1是用于接入电源端(VDD)的节点。晶体管M1的漏极、晶体管M2的漏极和晶体管M3的漏极连接至节点N2。晶体管M4的漏极也连接至节点N2。晶体管M4的源极和晶体管M5的漏极连接至节点N3。晶体管M5的源极和晶体管M6的漏极连接至节点N4。为了便于描述，假设节点N2是单元300的输出端。在此情况下，节点N2也可以用字母Z表示。
图3所示的各个晶体管的栅极都是与单元的一个输入端相连。换句话说，图3所示的晶体管的栅极电压都是输入电压。单元中还可以包括一些晶体管，这些晶体管的栅极与单元内部的节点相连。换句话说，这些晶体管的栅极电压是单元的内部电压。
如果图3所示的晶体管都是目标晶体管，那么图3所示的单元300可以包括6个晶体管常开缺陷和12个晶体管关断缺陷，其中12个晶体管关断缺陷包括6个晶体管低电平关断缺陷和6个晶体管高电平关断缺陷。
开路缺陷是指一条支路存在开路。该单元包括的开路缺陷可以根据单元包括的寄生电阻确定。在对开路缺陷进行注错仿真时，需要在断开节点的之路上添加开路电阻，同时在开路电阻的两侧均连接上/下拉电阻。因此，与晶体管关断缺陷类似，开路缺陷也可以进一步分为低电平开路缺陷和高电平开路缺陷，低电平开路缺陷是用于测试开路电阻连接低电平的情况下的开路缺陷，高电平开路缺陷是用于测试开路电阻连接高电平的情况下的开路缺陷。
在一些实施例中，一个寄生电阻可以对应于一个低电平开路缺陷和一个高电平开路缺陷。例如，图4示出了图3所示的单元300中的寄生电阻。如图4所示，单元300中包括寄生电阻Rp1至寄生电阻Rp6。可以理解的是，图4只是为了便于描述展示了单元300中的六个寄生电阻，单元300还可以包括未在图4示出的其他寄生电阻。如上所述，一个寄生电阻可以对应于一个低电平开路缺陷和一个 高电平开路缺陷。那么，图4所示的六个寄生电阻总共12个需要测试的开路缺陷，其中12个开路缺陷中包括6个低电平开路缺陷和6个高电平开路缺陷。
在另一些实施例中，如果一条支路中包括一个或多个寄生电阻，那么这一条支路可以对应于一个低电平开路缺陷和一个高电平开路缺陷。为了便于描述，可以将包含有寄生电阻的支路称为目标支路(或第一支路)，将不包含寄生电阻的支路称为非目标支路(或第二支路)。如图4所示，寄生电阻Rp1所在的目标支路1中只包含寄生电阻Rp1一个寄生电阻。因此目标支路1对应于一个低电平开路缺陷和一个高电平开路缺陷(也可以称寄生电阻Rp1对应于一个低电平开路缺陷和一个高电平开路缺陷)。目标支路2中共包括寄生电阻Rp2，寄生电阻Rp3和寄生电阻Rp4共三个寄生电阻。因此，目标支路2可以对应于一个低电平开路缺陷和一个高电平开路缺陷(也可以称为支路包括的三个寄生电阻(寄生电阻Rp2，寄生电阻Rp3和寄生电阻Rp4)对应于一个低电平开路缺陷和一个高电平开路缺陷)。类似的，目标支路3中包括寄生电阻Rp5和寄生电阻Rp6。因此，目标支路3可以对应于一个低电平开路缺陷和一个高电平开路缺陷(可以称为支路包括的两个寄生电阻(寄生电阻Rp5和寄生电阻Rp5)对应于一个低电平开路缺陷和一个高电平开路缺陷)。通过上述方式，图4所示的6个寄生电阻总共对应于6个开路缺陷，其中6个开路缺陷包括3个低电平开路缺陷和3个高电平开路缺陷。
假设单元中有N2个目标支路，平均每个目标支路包含3个寄生电阻。如果每个寄生电阻对应一个低电平开路缺陷和一个高电平开路缺陷，那么该单元总共有3×N2个低电平开路缺陷和3×N2个高电平开路缺陷。如果一个目标支路对应一个低电平开路缺陷和一个高电平开路缺陷，那么该单元就有2×N2个开路缺陷，这2×N2个开路缺陷包括N2个低电平开路缺陷和N2个高电平开路缺陷。可见，通过将同一支路上包含的多个寄生电阻合并，可以有效地减少需要测试的开路缺陷的数量。
单元的短路缺陷与线路间的距离相关。通常情况下，两条相邻的线路之间可能会产生短路缺陷。如果两条线路被中间被其他线路、节点或者元件隔开，则通常不会产生短路缺陷。寄生电容也可能产生短路缺陷。但是如果寄生电容的两个端点的距离较远或者被其他线路、节点或元件挡住，则通常不会产生短路缺陷。可以理解的是，如果两个相邻的线路是连接同一节点的，那么这两个线路不会产生短路缺陷。还以图3为例，晶体管M1的漏极与节点N2连，晶体管M2的漏极也与节点N2相连。这两个线路都连接节点N2，所以即使这两个线路相邻，也不会产生短路缺陷。因此，产生短路缺陷的两个相邻的线路应该是包含不同节点的两个线路。所以，也可以认为短路缺陷是对应于一对相邻的节点。一对相邻的节点包括两个相邻的节点，这两个节点分别位于两条线路，这两条线路在物理上是相邻的。因此如果单元中有N3对节点，且N3对节点中的每对节点包括两个相邻的节点，那么该单元中就有N3个需要测试的短路缺陷，N3个短路缺陷和N3对节点一一对应。
图5是图3所示的单元300中的晶体管M4和晶体管M5的版图示意图。如图5所示，共包括5条线路分别可以称为L1至L5。线路L1用于连接晶体管M4的栅极和输入端A1，线路L2用于连接晶体管M5的栅极和输入端A2，线路L3用于连接晶体管M5和节点N4；线路L4用于连接节点N2和晶体管M4，线路L5用于连接晶体管M4和晶体管M5。如图5所示，线路L1和线路L2相邻，因此，线路L1和L2之间包括一个需要测试的短路缺陷Ds1；线路L2和线路L3相邻，因此线路L2和线路L3之间包括一个需要测试的短路缺陷Ds2。线路L4和线路L5之间被晶体管M5隔开，这两个线路之间不相邻，因此不存在需要测试的短路缺陷。类似的，线路L2和线路L5被晶体管M5隔开，不存在需要测试的短路缺陷。
可选的，在一些实施例中，可以对单元中的所有类型的缺陷都进行缺陷测试。在此情况下，步骤201可以确定出的N个缺陷可以包括所有类型的缺陷。
可选的，在另一些实施例中，可以仅对标注单元中的部分类型的缺陷进行缺陷测试。例如，用户可能只关心晶体管的缺陷。因此可以只需要测试晶体管常开缺陷和晶体管关断缺陷。在此情况下，步骤201确定出的N个缺陷可以只包括晶体管常开缺陷和晶体管关断缺陷。
202，根据2M个输入向量，对该单元进行仿真，得到该单元的仿真结果。
M是该单元包含的输入端数量。例如，图3所示的单元300包括三个输入端，因此如果要对单元300的输入向量总共包括8个，分别为000，001，010，011，100，101，110和111。
步骤202的仿真过程不需要对需要测试的缺陷进行注错。因此，步骤202的过程也可以称为无注错仿真。该单元的无注错仿真的仿真结果包括所述单元中的每个节点的电压值。
根据该单元的寄生网表，可以确定该单元电路的所有节点列表。为了减少节点的数目，可以将同一条连接通路上的所有节点合并为一个节点。然后，生成测试仿真文件(testbench)。testbench的仿真方法可以是模拟瞬态仿真。然后，向生成的testbench中插入节点列表的电压提取语句，需要对每个节点均进行插入。完成之后，调用仿真器对testbench进行模拟瞬态仿真。最后，提取仿真结果，得到每个节点在不同输入向量下的电压值。该仿真器可以是通用模拟电路仿真器(simulation program with integrated circuit emphasis,SPICE)。
图6是标注了需要进行缺陷测试的缺陷后的单元300的示意图。图6共示出了四个需要测试的缺陷，分别为缺陷D1至缺陷D4，其中缺陷D1是晶体管M1的晶体管关断缺陷，缺陷D2是开路缺陷，缺陷D3是短路缺陷，缺陷D4是晶体管M6的晶体管常开缺陷。可以理解的是，图6仅示出了图3所示的单元300的部分电路中的部分缺陷，如图3所示的单元300除了如图6所示的四个缺陷以外，还可以包括其他没有示出的需要测试的缺陷。例如，除晶体管M6以外，晶体管M1至晶体管M5中的每个晶体管都需要测试晶体管常开缺陷；又如，除晶体管M1以外，晶体管M2至晶体管M6都需要测试晶体管关断缺陷。
表1示出了与图6所示的缺陷D1至D4相关的无注错仿真结果。
表1
单元300中的节点N1是用于连接电源VDD的节点，所以表1中的VDD相当于是节点N1的电压。
203，根据该单元的仿真结果，确定该N个缺陷中的每个缺陷在注错仿真时使用的测试向量，其中该N个缺陷中的每个缺陷的测试向量包括2M个输入向量中的部分输入向量。
通过步骤203，可以为每个缺陷从2M个输入向量中筛选出部分输入向量作为注错仿真时使用的输入向量，这样可以减少注错仿真需要的输入向量数量，从而减少注错仿真所需的时间和计算资源。筛选出的用于注错仿真的输入向量可以称为测试向量。
下面分别对如何筛选测试向量进行介绍。
该单元的仿真结果包括每个节点在2M个输入向量下的电压值。因此，如果该单元包括Y个节点，那么该单元的仿真结果中总共有Y×2M个电压值。假设节点1是该单元中的任一个节点，那么节点1对应于2M个电压值，这2M个电压值与2M个输入向量一一对应，2M个电压值中的每个电压值是在对应的输入向量下节点1的电压值。换句话说，2M个电压值中的第i个电压值是在2M个输入向量中的第i个输入向量下节点1的电压值，i＝1，……，2M。例如，2M个电压值中的第一个电压值是在2M个输入向量中的第一个输入向量下节点1的电压值，2M个电压值中的第二个电压值是在2M个输入向量中的第二个输入向量下节点1的电压值，以此类推。
对于一个晶体管常开缺陷，如果晶体管的栅极电压能够使得该晶体管关断，那么该栅极电压对应的输入向量可以作为该晶体管对应的晶体管常开缺陷的测试向量。因此，对于任一个晶体管(以下可以称为第一晶体管)，若想确定出用于测试该第一晶体管的晶体管常开缺陷的测试向量，那么可以从该单元的无注错仿真结果中确定出该第一晶体管的栅极节点(即栅极所连接的节点)的2M个电压值。为了便于描述，可以将第一晶体管的栅极节点的2M电压值称为第一电压值集合。在确定出第一电压值集合后，可以根据该第一晶体管的特性，从第一电压值集合中确定出能够令该第一晶体管关断的电压 值。确定出的电压值对应的输入向量就是注错仿真时用于测试该第一晶体管的晶体管常开缺陷的测试向量。
晶体管常开缺陷是晶体管在本应使得晶体管关断的栅极电压下处于导通状态。因此，使得晶体管导通的栅极电压对于常开缺陷的测试并没有意义。所以筛选出使得晶体管关断的栅极电压对应的输入向量作为晶体管常开缺陷的测试向量。
下面结合图7对如何确定晶体管常开缺陷的测试向量进行介绍。图7是对晶体管常开缺陷进行注错仿真时的电路图。如图7所示，在对晶体管M6的晶体管常开缺陷(即图6中的缺陷D4)进行注错仿真时，在晶体管M6的源极和漏极之间添加短路电阻R1。晶体管M6的晶体管常开缺陷的测试向量可以通过如下方式确定：从表1中确定对应于晶体管M6的栅极的电压值集合。输入端A3提供晶体管M6的栅极电压。因此，可以从表1中确定出该电压值集合包括的是输入端A3在8个输入向量下的电压值。这8个电压值分别为：0，1，0，1，0，1，0，1。由于晶体管M6是NMOS管，所以晶体管M6是高电平导通，因此可以从这8个电压值中选择出高电平的四个电压值，分别为第2、第4、第6和第8个电压值，这四个电压值对应的输入向量分别为001，011，101和111。因此，输入向量001，011，101和111就是用于测试晶体管M6的晶体管常开缺陷的测试向量。
对于晶体管低电平关断缺陷，如果在一个输入向量下，晶体管输入源极、栅极和漏极电压满足第一预设条件或第二预设条件，那么该输入向量就可以是用于测试该晶体管的晶体管低电平关断缺陷的测试向量。第一预设条件包括：栅极电压使得晶体管导通，漏极或源极为高电平；第二预设条件包括：栅极电压使得晶体管关断，漏极和源极不全为低电平。对于第一预设条件，因为栅极电压使得晶体管导通，所以漏极和源极的电压是相同的。所以，对于第一预设条件，可以只需要确定两个电压值，一个电压值是漏极电压值或源极电压值中的一个，另一个电压值是栅极电压值。对于第二预设条件，因为栅极电压使得晶体管关断，因此漏极和源极的电压值都需要确定。所以，对于第二预设条件，需要确定栅极电压值、源极电压值和漏极电压值。对于任一个晶体管(以下可以称为第二晶体管)，若想确定出该第二晶体管的晶体管低电平关断缺陷，那么可以从该单元的仿真结果中确定出对应于该第二晶体管的第二电压值集合。该第二电压值集合可以包括2M个子集。该2M个子集与2M个输入向量一一对应，该2M个子集中的每个子集包括在对应的输入向量下的第二晶体管的栅极节点(即栅极所连接的节点)的电压值、漏极节点(即漏极所连接的节点)的电压值和源极节点(即源极所连接的节点)的电压值。换句话说，该第二电压值集合中的2M个子集中的第i个子集包括在2M个输入向量中的第i个输入向量下该第二节点的栅极电压、源极电压和漏极电压，i＝1，……，2M。例如，该第二电压值集合中的2M个子集中的第1个子集包括在2M个输入向量中的第1个输入向量下该第二节点的栅极电压、源极电压和漏极电压，该第二电压值集合中的2M个子集中的第2个子集包括在2M个输入向量中的第2个输入向量下该第二节点的栅极电压、源极电压和漏极电压，以此类推。在确定出第二电压值集合后，可以根据该第二晶体管的特性，从第二电压值集合中确定出能够满足第一预设条件或第二预设条件的子集。确定出的子集对应的输入向量就是注错仿真时用于测试该第二晶体管的晶体管低电平关断缺陷的测试向量。
在测试晶体管低电平关断缺陷时，开路电阻连接低电平。因此，如果晶体管的栅极电压使得晶体管导通，源极和漏极电压相同。若源极和漏极都是低电压，则与注错仿真时的电压状态一致，因此这一组电压对应的输入向量对于晶体管低电平关断缺陷的测试没有意义。如果晶体管关断，且漏极和源极电压均为低电平，则该状态与注错仿真时的电压状态一致，因此这一组电压对应的输入向量对于晶体管低电平关断缺陷的测试没有意义。
对于晶体管高电平关断缺陷，如果在一个输入向量下，晶体管输入源极、栅极和漏极电压满足第三预设条件或第四预设条件，那么该输入向量就可以是用于测试该晶体管的晶体管低电平关断缺陷的测试向量。第三预设条件包括：栅极电压使得晶体管导通，漏极或源极为低电平；第四预设条件包括：栅极电压使得晶体管关断，漏极和源极不全为高电平。对于第三预设条件，因为栅极电压使得晶体管导通，所以漏极和源极的电压是相同的。所以，对于第三预设条件，可以只需要确定两个电压值，一个电压值是漏极电压值或源极电压值中的一个，另一个电压值是栅极电压值。对于第四预设条件，因为栅极电压使得晶体管关断，因此漏极和源极的电压值都需要确定。所以，对于第四预设条件，需要确定栅极电压值、源极电压值和漏极电压值。还以第二晶体管为例，若想确定出该第二晶体管的晶体管高 电平关断缺陷，那么可以根据该第二晶体管的特性，从该第二电压值集合中确定出能够满足第三预设条件或第四预设条件的子集。确定出的子集对应的输入向量就是注错仿真时用于测试该第二晶体管的晶体管高电平关断缺陷的测试向量。
在测试晶体管高电平关断缺陷时，开路电阻连接高电平。因此，如果晶体管的栅极电压使得晶体管导通，源极和漏极电压相同，若源极和漏极都是高电压，则与注错仿真时的电压状态一致，因此这一组电压对应的输入向量对于晶体管高电平关断缺陷的测试没有意义。如果晶体管关断，且漏极和源极电压均为高电平，则该状态与注错仿真时的电压状态一致，因此这一组电压对应的输入向量对于晶体管高电平关断缺陷的测试没有意义。
图8示出了对缺陷D1进行注错仿真时的电路图。需要测试的缺陷D1需是晶体管M1的晶体管关断缺陷。更具体地，需要测试的缺陷D1需是晶体管M1的晶体管低电平关断缺陷和晶体管高电平关断缺陷。如图8所示，在对缺陷D1进行注错仿真时，需要在晶体管M1的漏极和源极分别添加开路电阻R1和开路电阻R4。同时，在开路电阻两侧均连接上/下拉电阻(即图8中所示的R2、R3、R5和R6)。
晶体管M1的晶体管低电平关断缺陷的测试向量和晶体管高电平关断缺陷的测试向量可以通过如下方式确定：晶体管M1的栅极、漏极和源极电压分别是：输入端A1、节点N2和VDD。因此，可以从表1中确定出对应于晶体管M1的电压值集合，该电压值集合包括8个子集，该8个子集中的每个子集分别包括输入端A1、节点N2和VDD的电压值。表2示出了对应于晶体管M1的电压值集合包括的8个子集以及这8个子集和输入向量的对应关系。
表2
晶体管M1是PMOS管，所以晶体管M1是低电平导通，所以如果满足第一预设条件，那么A1等于0，N2或VDD等于1。从表2中可以看出，子集1至子集4都满足该第一预设条件。如果满足第二预设条件，那么A1等于1，N2和VDD不能都为0。从表2可以看出，子集5至子集8都满足该第二预设条件。因此，用于测试晶体管M1的晶体管低电平关断缺陷的测试向量包括全部的8个输入向量。如果满足第三预设条件，那么A1等于0，N2或VDD等于0。从表2可以看出，有满足第四预设条件的子集。如果满足第四预设条件，那么A1＝1，N2和VDD不能都为1。从表2可以看出，子集8满足该第四预设条件。因此，用于测试晶体管M1的晶体管低电平关断缺陷的测试向量只有子集8对应的输入向量，即111。
对于一条支路的开路缺陷，如果支路的无注错仿真电压是高电平，那么该电压对应的输入向量可以用于测试该支路的低电平开路缺陷；如果该支路的无注错仿真电压是低电平，那么该电压对应的输入向量可以用于测试该支路的高电平开路缺陷。因此，对于任一个目标支路(以下可以称为第一目标支路)，若想确定出用于测试该第一目标支路的开路缺陷的测试向量，那么可以从该单元的无注错仿真结果中确定出位于该第一目标支路上的节点的2M个电压值。为了便于描述，可以将位于第一目标支路上的节点的2M个电压值称为第三电压值集合。在确定出第三电压值集合后，可以分别确定出第三电压值集合中的高电平和低电平，其中该第三电压值集合中的高电平对应的输入向量可以用于测试该第一目标支路的低电平开路缺陷，该第三电压值集合中的低电平对应的输入向量可以用于测试该第一忙不支路的高电平开路缺陷。
在测试低电平开路缺陷时，开路电阻的电压值为低。此时，如果该第一目标支路上的电压值也为 低，则无法确定该支路是否存在开路缺陷。所以需要选择高电平对应的输入向量来测试低电平开路缺陷。类似的，在测试高电平开路缺陷时，开路电阻的电压值为高。此时，如果该第一目标支路上的电压值也为高，则无法确定该支路是否存在开路缺陷。所以需要选择低电平对应的输入向量来测试高电平开路缺陷。
图9示出了对缺陷D2进行注错仿真时的电路图。需要测试的缺陷D2是包含节点N4的支路的开路缺陷。更具体地，需要测试的缺陷D4是包含节点N3的支路的低电平开路缺陷和高电平开路缺陷。如图9所示，在对缺陷D2进行注错仿真时，需要在支路上添加开路电阻R1，并在开路电阻R1两侧分别连接上/下拉电阻(即图9中的R2和R3)。对于如图9所示的电路，如果要测试低电平开路缺陷，则电阻R2和R3均是下拉电阻；如果要测试高电平开路缺陷，则电阻R2和R3均是上拉电阻。用于测试该支路对应的开路缺陷的测试向量可以通过如下方式确定：从表1中确定出节点N3在8个输入向量下的电压值。该8个电压值分别为0，0，0，0，1，1，1，0。这8个电压值中第5至第7个电压值是高电平，第1、2、3、4和第8个电压值是低电平。因此，第5至第7个电压值对应的输入向量(即输入向量100，101，和110)是用于测试低电平开路缺陷的测试向量；第1、2、3、4和第8个电压值对应的输入向量(即输入向量000，001，010，011和111)是用于测试高电平开路缺陷的测试向量。
对于短路缺陷，如果短路缺陷对应的两个节点在无注错仿真下的电压值不同，那么这两个电压值对应的输入向量可以作为该对节点对应的短路缺陷的测试向量。因此，若想确定出对应于任一对节点(以下可以称为第一节点对)的短路缺陷，那么可以从该单元的仿真结果中确定出对应于该第一节点对的第四电压值集合。该第四电压值结合包括2M个子集，该2M个子集与该2M个子集与2M个输入向量一一对应，该2M个子集中的每个子集包括在对应的输入向量下的第一节点对包括的两个节点的电压值。换句话说，该第二电压值集合中的2M个子集中的第i个子集包括在2M个输入向量中的第i个输入向量下该第一节点对包括的两个节点的电压值，i＝1，……，2M。例如，该第二电压值集合中的2M个子集中的第1个子集包括在2M个输入向量中的第1个输入向量下该第一节点对包括的两个节点的电压值，该第二电压值集合中的2M个子集中的第2个子集包括在2M个输入向量中的第2个输入向量下该第一节点对包括的两个节点的电压值，以此类推。在确定出第四电压值集合后，从第二电压值集合中确定包含有不同电压值的子集。确定出的子集对应的输入向量就是注错仿真时用于测试该第一节点对对应的短路缺陷的测试向量。
在测试短路缺陷时，需要在测试的一对节点之间插入短路电阻。所以如果输入向量能使得这两个节点电压值相同，那么就无法确定这两个节点是否存在短路。因此，只有使得这两个节点电压值不同的输入向量才能判断出这包含这两个节点的线路是否存在短路缺陷。
图10示出了对缺陷D3进行注错仿真时的电路图。需要测试的缺陷D3是晶体管M5的栅极节点和节点N4的短路缺陷。如图10所示，在对缺陷D3进行注错仿真时，在晶体管M5的栅极节点和节点N4中插入了短路电阻。用于测试该短路缺陷的测试向量可以通过如下方式确定：从表1中确定出电压值集合，该电压值结合包括8个子集，该8个子集中的每个子集分别包括输入端A2和节点N4的电压值。表3示出了8个子集以及这8个子集和输入向量的对应关系。
表3
从表3可以看出子集3、4和8包含有不同的电压值，因此子集3、子集4和子集8对应的三个输 入向量(即输入向量010，011和111)是用于测试晶体管M5的栅极节点和节点N4的短路缺陷的测试向量。
表4总结了图6所示的四个缺陷中每个缺陷的测试向量。
表4
表4中的D1_0表示缺陷D1中的晶体管关断低电平缺陷，D1_1表示缺陷D1中的晶体管关断高电平缺陷，D2_0表示缺陷D2的低电平开路缺陷，D2_1表示缺陷D2的高电平开路缺陷。
从表4中可以看出，总共只需要24个测试向量就可以测试图6所示的四处缺陷。而目前业界的方案中，每个缺陷都需要用全部的输入向量来测试。所以，如果按照目前业界的方案，这四处缺陷总共需要48个向量才能完成测试。与现有技术相比，本申请提供的技术方案可以有效减少用于注错仿真的向量数目，从而可以减少注错仿真消耗的时间和计算资源。
可以根据确定出的测试向量生成缺陷注错仿真文件。注错仿真通过仿真器(例如SPICE)读取该注错仿真文件实现，该文件中包含上一步产生的每个缺陷的测试向量。注错仿真的仿真结果包括单元的输出端在注错后的各个测试向量下的电压值。对于一个缺陷，如果注错仿真的结果与无注错仿真的结果不同，那么这个电压值对应的测试向量就可以作为该缺陷的实际测试向量。表5示出了图6所示的四处缺陷的注错仿真结果。
表5
对于缺陷D1的晶体管低电平关断缺陷(即D1_0)，该缺陷对应的测试向量包括全部8个输入向量。因此，这8个输入向量中的每个输入向量在表5中都有一个电压值，该电压值是单元的输出端Z的电压值(即节点N2的电压值)。表5中向量011对应的电压值与表1中向量011对应的节点N2的电压值不同。因此011可以作为缺陷D1的晶体管低电平关断缺陷的实际测试向量。
对于缺陷D1的晶体管高电平关断缺陷(即D1_1)，该缺陷对应的测试向量只包括输入向量111。因此，只有输入向量111在表5中有一个对应的电压值，该电压值是单元的输出端Z的电压值(即节点N2的电压值)。向量111对应的电压值与表1中向量111对应的节点N2的电压值相同。缺陷D1的晶体管高电平关断缺陷的实际测试向量为空。
对于缺陷D2的低电平开路缺陷(即D2_0)，该缺陷对应的测试向量包括100，101和110。因此，这三个输入向量下每个输入向量在表5中都有一个电压值，该电压值是单元的输出端Z的电压值(即节点N2的电压值)。这三个输入向量在表1和表3中对应的节点N2的电压值都相同。缺陷D2的低电平开路缺陷的实际测试向量为空。
对于缺陷D2的高电平开路缺陷(即D2_1)，该缺陷对应的测试向量包括000，001，010，011和111。因此，这五个输入向量中每个输入向量在表5都有一个电压值，该电压值是单元的输出端Z的电压值(即节点N2的电压值)。000，001，010和011这四个输入向量在表1和表5中对应的节点N2的电压值都相同，表5中输入向量111对应的电压值与表1中向量111对应的节点N2的电压值不同。 因此，缺陷D2的低电平开路缺陷的实际测试向量为111。
对于缺陷D3，该缺陷对应的测试向量包括010，011和111。因此，这三个输入向量中的每个输入向量在表5中都有一个电压值。该电压值是单元的输出端Z的电压值(即节点N2的电压值)。与表1中节点N2的电压值相比，010和011这两个输入向量在表1和表5中对应的节点N2的电压值都相同，表5中输入向量111对应的电压值与表1中向量111对应的节点N2的电压值不同。因此，缺陷D3的实际测试向量是111。。
对于缺陷D4，该缺陷对应的测试向量包括000，010，100和110。因此，这四个输入向量中的每个输入向量在表5中都有一个电压值。该电压值是单元的输出端Z的电压值(即节点N2的电压值)。与表1中节点N2的电压值相比，000，010和100这三个输入向量在表1和表5中对应的节点N2的电压值都相同，表5中输入向量110对应的电压值与表1中向量110对应的节点N2的电压值不同。因此，缺陷D4的实际测试向量为110。
表6示出了缺陷D1至D4的实际测试向量。
表6
在确定了实际测试向量之后，可以对实际测试向量进行合并，然后根据合并后的测试向量确定并输出缺陷描述模型。实际测试向量的合并方式以及缺陷描述模型的输出方式与现有方式相同，为了简洁，在此就不再赘述。
图11是根据本申请实施例提供的一种单元测试的装置的示意性结构框图。如图11所示的单元测试的装置1100包括处理模块1101和仿真模块1102。
处理模块1101，用于确定单元在注错仿真时需要进行缺陷测试的N个缺陷，N为大于或等于1的正整数。
仿真模块1102，用于根据2M个输入向量，对该单元进行无注错仿真，得到该单元的无注错仿真结果，其中，该单元包括M个输入端，M为大于或等于1的正整数。
处理模块1101，还用于根据该单元的无注错仿真结果，确定该N个缺陷中的每个缺陷在该注错仿真时使用的测试向量，其中该N个缺陷中的至少一个缺陷的测试向量包括该2M个输入向量中的部分输入向量。
在实现过程中，处理模块1101和仿真模块1102可以通过软件形式的指令或程序代码完成，例如用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件实现处理模块1101和仿真模块1102。处理模块1101和仿真模块1102的具体功能和有益效果可以参见上述实施例中的描述，为了简洁，在此不再赘述。
本申请实施例还提供一种计算机设备，该计算机设备包处理器，该处理器用于与存储器耦合，读取并执行该存储器中的指令和/或程序代码，以执行上述实施例中任一个实施例所述的方法。
本申请实施例还提供了一种芯片系统，该芯片系统包括逻辑电路，该逻辑电路用于与输入/输出接口耦合，通过该输入/输出接口传输数据，以执行上述实施例中任一个实施例所述的方法。
应注意，本申请实施例中的处理器可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令或程序代码完成。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的 信息，结合其硬件完成上述方法的步骤。
可以理解，本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。应注意，本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
根据本申请实施例提供的方法，本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得该计算机执行上述实施例中任意一个实施例的方法。
根据本申请实施例提供的方法，本申请还提供一种计算机可读介质，该计算机可读介质存储有程序代码，当该程序代码在计算机上运行时，使得该计算机执行上述实施例中任意一个实施例的方法。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令或程序代码用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种测试单元的方法，其特征在于，包括：
    确定单元在注错仿真时需要进行缺陷测试的N个缺陷，N为大于或等于1的正整数；
    根据2M个输入向量，对所述单元进行无注错仿真，得到所述单元的无注错仿真结果，其中，所述单元包括M个输入端，M为大于或等于1的正整数；
    根据所述单元的无注错仿真结果，确定所述N个缺陷中的每个缺陷在所述注错仿真时使用的测试向量，其中所述N个缺陷中的至少一个缺陷的测试向量包括所述2M个输入向量中的部分输入向量。
  2. 根据权利要求1所述的方法，其特征在于，所述确定单元中需要进行缺陷测试的N个缺陷，包括：
    根据所述单元包括的多个晶体管，确定所述N个缺陷中包括N1个晶体管常开缺陷，其中所述多个晶体管包括N1个目标晶体管，所述N1个目标晶体管与所述N1个晶体管常开缺陷一一对应，所述N1个目标晶体管为所述多个晶体管单元中除寄生晶体管和无效晶体管以外的晶体管。
  3. 根据权利要求2所述的方法，其特征在于，所述根据所述单元的无注错仿真结果，确定所述N个缺陷中的每个缺陷在所述注错仿真时使用的测试向量，包括：
    从所述单元的无注错仿真结果中确定与第一目标晶体管对应的第一电压值集合，其中所述第一目标晶体管是所述N1个目标晶体管中的任一个目标晶体管，所述第一电压值集合包括的2M个第一电压值与所述2M个输入向量一一对应，所述第一电压值集合包括的2M个第一电压值中的每个第一电压值是在对应的输入向量下所述第一目标晶体管的栅极电压；
    确定所述第一电压值集合包括的2M个第一电压值中使得所述第一目标晶体管关断的第一电压值对应的输入向量为第一测试向量，所述第一测试向量是用于测试所述第一目标晶体管的晶体管常开缺陷的测试向量。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，所述确定单元中需要进行缺陷测试的N个缺陷，包括：
    根据所述单元包括的多个晶体管，确定所述N个缺陷中包括N1个晶体管低电平关断缺陷和N1个晶体管高电平关断缺陷，其中所述多个晶体管包括N1个目标晶体管，所述N1个目标晶体管与所述N1个晶体管低电平关断缺陷一一对应，所述N1个目标晶体管与所述N1个晶体管高电平关断缺陷一一对应，所述目标晶体管为所述多个晶体管中除寄生晶体管和无效晶体管以外的晶体管，所述晶体管低电平关断缺陷用于测试晶体管在开路电阻连接低电平的情况下的关断缺陷，所述晶体管高电平关断缺陷用于测试晶体管在开路电阻连接高电平的情况下的关断缺陷。
  5. 根据权利要求4所述的方法，其特征在于，所述根据所述单元的无注错仿真结果，确定所述N个缺陷中的每个缺陷在所述注错仿真时使用的测试向量，包括：
    从所述单元的无注错仿真结果中确定与第二目标晶体管对应的第二电压值集合，其中所述第二目标晶体管是所述N1个目标晶体管中的任一个目标晶体管，所述第二电压值集合包括的2M个子集与所述2M个输入向量一一对应，所述第二电压值集合包括的2M个子集中的每个子集包括在对应的输入向量下所述第二目标晶体管的栅极电压、漏极电压和源极电压；
    确定所述第二电压值集合包括的2M个子集中满足第一预设条件或第二预设条件的子集对应的输入向量为第二测试向量，所述第二测试向量是用于测试所述第二晶体管的晶体管低电平关断缺陷的测试向量，所述第一预设条件包括：所述第二目标晶体管的栅极电压使所述第二目标晶体管导通且所述第二目标晶体管的源极或漏极为高电平，所述第二预设条件包括：所述第二目标晶体管的栅极电压使所述第二目标晶体管关断且所述第二目标晶体管的源极和漏极不全为低电平；
    确定所述第二电压值集合包括的2M个子集中满足第三预设条件或第四预设条件的子集对应的输入向量为第三测试向量，所述第三测试向量是用于测试所述第二晶体管的晶体管高电平关断缺陷的测试向量，所述第三预设条件包括：所述第二目标晶体管的栅极电压使所述第二目标晶体管导通且所述第二目标晶体管的源极或漏极为低电平，所述第四预设条件包括：所述第二目标晶体管的栅极电压使所述第二目标晶体管关断且所述第二目标晶体管的源极和漏极不全为高电平。
  6. 根据权利要求2至5中任一项所述的方法，其特征在于，所述确定单元中需要进行缺陷测试的N个缺陷，包括：
    根据所述单元包括的寄生电阻，确定所述N个缺陷中包括N2个低电平开路缺陷和N2个高电平开路缺陷，其中所述单元包括N2个目标支路，所述目标支路是所述单元中包括一个或多个所述寄生电阻的支路，所述低电平开路缺陷用于测试开路电阻连接低电平的情况下的开路缺陷，所述高电平开路缺陷用于测试开路电阻连接高电平的情况下的开路缺陷。
  7. 根据权利要求6所述的方法，其特征在于，所述根据所述单元的无注错仿真结果，确定所述N个缺陷中的每个缺陷在所述注错仿真时使用的测试向量，包括：
    从所述单元的无注错仿真结果中确定与第一目标支路对应的第三电压值集合，其中所述第一目标支路是所述N2个目标支路中的任一个支路，所述第三电压值集合包括的2M个第二电压值与所述2M个输入向量一一对应，所述第三电压值集合包括的2M个第二电压值中的每个第二电压值是在对应的输入向量下所述第一目标支路的电压值；
    确定所述第三电压值集合包括的2M个第二电压值中的高电平对应的输入向量为第四测试向量，所述第四测试向量是用于测试所述第一目标支路的低电平开路缺陷的测试向量；
    确定所述第三电压值集合包括的2M个第二电压值中的低电平对应的输入向量为第五测试向量，所述第五测试向量是用于测试所述第一目标支路的高电平开路缺陷的测试向量。
  8. 根据权利要求2至7中任一项所述的方法，其特征在于，所述确定单元中需要进行缺陷测试的N个缺陷，包括：
    确定所述单元包括K对节点，所述K对节点中的每对节点包括两个不同的节点，K为大于或等于1的正整数；
    根据所述单元中的元件的坐标信息，从所述K对节点中确定出N3对节点，所述N3对节点中的每对节点包括两个相邻的节点；
    确定所述N个缺陷中包括N3个短路缺陷，其中所述N3个短路缺陷与所述N3对节点一一对应。
  9. 根据权利要求8所述的方法，其特征在于，所述根据所述单元的无注错仿真结果，确定所述N个缺陷中的每个缺陷在所述注错仿真时使用的测试向量，包括：
    从所述单元的无注错仿真结果中确定与第一节点对对应的第四电压值集合，其中所述第一节点对是所述N3对节点中的任一对节点，所述第四电压值包括的2M个子集与所述2M个输入向量一一对应，所述第四电压值集合包括的2M个子集中的每个子集包括在对应的输入向量下所述第一节点对中的两个节点的电压值；
    确定所述第四电压值包括的2M个子集中包括有不同电压值的子集对应的输入向量是第六测试向量，所述第六测试向量是用于测试所述第一节点对的短路缺陷的测试向量。
  10. 根据权利要求1至9中任一项所述的方法，其特征在于，所述方法还包括：
    对所述单元进行注错仿真，得到所述单元的注错仿真结果；
    根据所述单元的无注错仿真结果和所述单元的注错仿真结果，确定所述N个缺陷中的每个缺陷的实际测试向量，其中，所述N个缺陷中的每个缺陷的实际测试向量的无注错仿真结果与注错仿真结果不同；
    根据所述N个缺陷中的每个缺陷的实际测试向量，生成所述单元的缺陷描述模型。
  11. 一种单元测试的装置，其特征在于，包括：
    处理模块，用于确定所述单元在注错仿真时需要进行缺陷测试的N个缺陷，N为大于或等于1的正整数；
    仿真模块，用于根据2M个输入向量，对所述单元进行无注错仿真，得到所述单元的无注错仿真结果，其中，所述单元包括M个输入端，M为大于或等于1的正整数；
    所述处理模块，还用于根据所述单元的无注错仿真结果，确定所述N个缺陷中的每个缺陷在所述注错仿真时使用的测试向量，其中所述N个缺陷中的至少一个缺陷的测试向量包括所述2M个输入向量中的部分输入向量。
  12. 根据权利要求11所述的装置，其特征在于，所述处理模块，具体用于根据所述单元包括的多个晶体管，确定所述N个缺陷中包括N1个晶体管常开缺陷，其中所述多个晶体管包括N1个目标晶体 管，所述N1个目标晶体管与所述N1个晶体管常开缺陷一一对应，所述N1个目标晶体管为所述多个晶体管单元中除寄生晶体管和无效晶体管以外的晶体管。
  13. 根据权利要求12所述的装置，其特征在于，所述处理模块，具体用于：
    从所述单元的无注错仿真结果中确定与第一目标晶体管对应的第一电压值集合，其中所述第一目标晶体管是所述N1个目标晶体管中的任一个目标晶体管，所述第一电压值集合包括的2M个第一电压值与所述2M个输入向量一一对应，所述第一电压值集合包括的2M个第一电压值中的每个第一电压值是在对应的输入向量下所述第一目标晶体管的栅极电压；
    确定所述第一电压值集合包括的2M个第一电压值中使得所述第一目标晶体管关断的第一电压值对应的输入向量为第一测试向量，所述第一测试向量是用于测试所述第一目标晶体管的晶体管常开缺陷的测试向量。
  14. 根据权利要求11至13中任一项所述的装置，其特征在于，所述处理模块，具体用于根据所述单元包括的多个晶体管，确定所述N个缺陷中包括N1个晶体管低电平关断缺陷和N1个晶体管高电平关断缺陷，其中所述多个晶体管包括N1个目标晶体管，所述N1个目标晶体管与所述N1个晶体管低电平关断缺陷一一对应，所述N1个目标晶体管与所述N1个晶体管高电平关断缺陷一一对应，所述目标晶体管为所述多个晶体管中除寄生晶体管和无效晶体管以外的晶体管，所述晶体管低电平关断缺陷用于测试晶体管在开路电阻连接低电平的情况下的关断缺陷，所述晶体管高电平关断缺陷用于测试晶体管在开路电阻连接高电平的情况下的关断缺陷。
  15. 根据权利要求14所述的装置，其特征在于，所述处理模块，具体用于：
    从所述单元的无注错仿真结果中确定与第二目标晶体管对应的第二电压值集合，其中所述第二目标晶体管是所述N1个目标晶体管中的任一个目标晶体管，所述第二电压值集合包括的2M个子集与所述2M个输入向量一一对应，所述第二电压值集合包括的2M个子集中的每个子集包括在对应的输入向量下所述第二目标晶体管的栅极电压、漏极电压和源极电压；
    确定所述第二电压值集合包括的2M个子集中满足第一预设条件或第二预设条件的子集对应的输入向量为第二测试向量，所述第二测试向量是用于测试所述第二晶体管的晶体管低电平关断缺陷的测试向量，所述第一预设条件包括：所述第二目标晶体管的栅极电压使所述第二目标晶体管导通且所述第二目标晶体管的源极或漏极为高电平，所述第二预设条件包括：所述第二目标晶体管的栅极电压使所述第二目标晶体管关断且所述第二目标晶体管的源极和漏极不全为低电平；
    确定所述第二电压值集合包括的2M个子集中满足第三预设条件或第四预设条件的子集对应的输入向量为第三测试向量，所述第三测试向量是用于测试所述第二晶体管的晶体管高电平关断缺陷的测试向量，所述第三预设条件包括：所述第二目标晶体管的栅极电压使所述第二目标晶体管导通且所述第二目标晶体管的源极或漏极为低电平，所述第四预设条件包括：所述第二目标晶体管的栅极电压使所述第二目标晶体管关断且所述第二目标晶体管的源极和漏极不全为高电平。
  16. 根据权利要求12至15中任一项所述的装置，其特征在于，所述处理模块，具体用于根据所述单元包括的寄生电阻，确定所述N个缺陷中包括N2个低电平开路缺陷和N2个高电平开路缺陷，其中所述单元包括N2个目标支路，所述目标支路是所述单元中包括一个或多个所述寄生电阻的支路，所述低电平开路缺陷用于测试开路电阻连接低电平的情况下的开路缺陷，所述高电平开路缺陷用于测试开路电阻连接高电平的情况下的开路缺陷。
  17. 根据权利要求16所述的装置，其特征在于，处理模块，具体用于：
    从所述单元的无注错仿真结果中确定与第一目标支路对应的第三电压值集合，其中所述第一目标支路是所述N2个目标支路中的任一个支路，所述第三电压值集合包括的2M个第二电压值与所述2M个输入向量一一对应，所述第三电压值集合包括的2M个第二电压值中的每个第二电压值是在对应的输入向量下所述第一目标支路的电压值；
    确定所述第三电压值集合包括的2M个第二电压值中的高电平对应的输入向量为第四测试向量，所述第四测试向量是用于测试所述第一目标支路的低电平开路缺陷的测试向量；
    确定所述第三电压值集合包括的2M个第二电压值中的低电平对应的输入向量为第五测试向量，所述第五测试向量是用于测试所述第一目标支路的高电平开路缺陷的测试向量。
  18. 根据权利要求12至17中任一项所述的装置，其特征在于，所述处理模块，具体用于确定所 述单元包括K对节点，所述K对节点中的每对节点包括两个不同的节点，K为大于或等于1的正整数；
    根据所述单元中的元件的坐标信息，从所述K对节点中确定出N3对节点，所述N3对节点中的每对节点包括两个相邻的节点；
    确定所述N个缺陷中包括N3个短路缺陷，其中所述N3个短路缺陷与所述N3对节点一一对应。
  19. 根据权利要求18所述的装置，其特征在于，所述处理模块，具体用于：
    从所述单元的无注错仿真结果中确定与第一节点对对应的第四电压值集合，其中所述第一节点对是所述N3对节点中的任一对节点，所述第四电压值包括的2M个子集与所述2M个输入向量一一对应，所述第四电压值集合包括的2M个子集中的每个子集包括在对应的输入向量下所述第一节点对中的两个节点的电压值；
    确定所述第四电压值包括的2M个子集中包括有不同电压值的子集对应的输入向量是第六测试向量，所述第六测试向量是用于测试所述第一节点对的短路缺陷的测试向量。
  20. 根据权利要求11至19中任一项所述的装置，其特征在于，所述仿真模块，还用于对所述单元进行注错仿真，得到所述单元的注错仿真结果；
    所述处理模块，还用于根据所述单元的无注错仿真结果和所述单元的注错仿真结果，确定所述N个缺陷中的每个缺陷的实际测试向量，其中，所述N个缺陷中的每个缺陷的实际测试向量的无注错仿真结果与注错仿真结果不同；
    所述处理模块，还用于根据所述N个缺陷中的每个缺陷的实际测试向量，生成所述单元的缺陷描述模型。
  21. 一种计算机可读介质，其特征在于，所述计算机可读介质存储有程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行如权利要求1至10中任一项所述的方法。
  22. 一种计算机程序产品，其特征在于，所述计算机程序产品包括计算机程序代码，当所述计算机程序代码在计算机上运行时，使得所述计算机执行如权利要求1至10中任一项所述的方法。
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