WO2024027405A1 - 芯片封装结构及其制作方法 - Google Patents

芯片封装结构及其制作方法 Download PDF

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Publication number
WO2024027405A1
WO2024027405A1 PCT/CN2023/104232 CN2023104232W WO2024027405A1 WO 2024027405 A1 WO2024027405 A1 WO 2024027405A1 CN 2023104232 W CN2023104232 W CN 2023104232W WO 2024027405 A1 WO2024027405 A1 WO 2024027405A1
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WO
WIPO (PCT)
Prior art keywords
packaging structure
substrate
conductive pillar
chip
cutting
Prior art date
Application number
PCT/CN2023/104232
Other languages
English (en)
French (fr)
Inventor
王旋
史坡
杨正得
李永胜
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2024027405A1 publication Critical patent/WO2024027405A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves

Definitions

  • the present application relates to the field of chip packaging technology, and in particular, to a chip packaging structure and a manufacturing method thereof.
  • SIP System-in-package
  • MEMS micro-electro-mechanical systems
  • EMI electromagnetic interference
  • Embodiments of the present application provide a chip packaging structure, a manufacturing method thereof, and electronic equipment.
  • the main purpose is to provide a chip packaging structure with reliable and superior electromagnetic self-shielding function, and a manufacturing method of the chip packaging structure.
  • the chip When the packaging structure is applied to electronic equipment, its electronic devices can effectively reduce electromagnetic interference and can also reduce the interference of electronic equipment to other electronic devices.
  • the chip packaging structure may be a standard SIP product or other types of chip packaging products.
  • the chip packaging structure includes a substrate, a chip and a shielding layer.
  • the substrate includes a plurality of metal layers arranged in a stack; the first conductive pillar penetrates at least two metal layers, and the first conductive pillar has a contact surface exposed to the outside of the substrate, and the contact surface It includes a first contact surface facing the top surface of the substrate; the chip is disposed on the top surface of the substrate and connected to the metal layer on the top surface of the substrate; the shielding layer is formed outside the chip and is connected to the first conductive pillar through the first contact surface, This shield is connected to ground.
  • the shielding layer is connected to the first conductive pillar through the first contact surface and is grounded, thereby forming an electromagnetic shielding cavity.
  • the chip is mounted in the electromagnetic shielding cavity, which can shield the electromagnetic radiation generated by the chip and shield external electromagnetic waves, thereby reducing interference to the chip.
  • the shielding layer formed on the first contact surface is thicker, so that the contact effect between the shielding layer and the first conductive pillar is better. Better, with lower resistance, less likely to cause disconnection, and thus less likely to cause electromagnetic leakage.
  • the shielding layer is grounded through one of the at least two metal layers penetrated by the first conductive pillar.
  • At least one metal layer penetrated by the first conductive pillar is connected to the metal layer on the bottom surface of the substrate, and the metal layer on the bottom surface is used for grounding. Since the metal layer on the underside of the substrate includes a ground circuit, the shield can be grounded through the ground circuit. For example, the ground circuit on the underside of the substrate is connected to the ground signal on the motherboard in the electronic device.
  • the metal layer on the bottom surface of the substrate and the metal layer on the top surface of the substrate include interconnection lines, and may specifically be metal wiring layers.
  • the above-mentioned contact surface further includes a second contact surface facing the outside of the substrate, and the second contact surface forms a gap with the first contact surface; the shielding layer passes through the first contact surface and the third contact surface.
  • the two contact surfaces are connected to the first conductive pillar.
  • the shielding layer will also be deposited on the second contact surface, that is, in contact with the two surfaces of the first conductive pillar, so the contact effect between the two can be further optimized. thereby, It can further reduce the possibility of electromagnetic leakage caused by poor contact between the two.
  • the chip packaging structure further includes a plastic sealing material layer formed on the top surface of the substrate, the chip is wrapped in the plastic sealing material layer; the shielding layer covers the outer surface of the plastic sealing material layer, the third A contact surface, and a side area of the substrate located between the first contact surface and the top surface of the substrate. That is, the shield does not cover all side areas of the substrate. Since the combination of the electromagnetic shielding material used in the shielding layer and the substrate material is usually less reliable during collision, only the outer surface of the plastic layer, the first contact surface, and the first contact surface to the top surface of the substrate are A shielding layer is formed on the side areas between them.
  • the metal layers penetrated by the first conductive pillars are all located inside the substrate; at least one metal layer penetrated by the first conductive pillars is connected to the metal layer on the bottom surface of the substrate through the second conductive pillars; and , in a direction parallel to the top surface of the substrate, the distance between the second conductive pillar and the side of the first conductive pillar away from the outside of the substrate is greater than the first distance. That is to say, the second conductive pillar is wrapped in the insulating material of the substrate, or in other words, the second conductive pillar is located inside the substrate.
  • the main purpose of this implementation is to provide a grounding method when the metal layer penetrated by the first conductive pillar is located inside the substrate. Specifically, the shielding layer is connected to the second conductive pillar through the metal layer penetrated by the first conductive pillar, and then through the third conductive pillar.
  • the two conductive pillars penetrate the metal layer on the bottom surface of the substrate to connect to the ground on the main board (PCB) of the electronic device through the metal layer on the bottom surface of the substrate.
  • the second conductive pillar serves as a part of forming a fully enclosed electromagnetic shielding cavity. Since it is located inside the substrate, it means that there is no need to form a shielding layer on all side areas of the substrate, thereby reducing the risk of shielding. Poor bonding reliability with the substrate may lead to the possibility of the shielding layer falling off, which enhances the reliability of the electromagnetic shielding function.
  • different metal layers are separated by an insulating layer made of insulating material.
  • the insulating material can specifically be polypropylene, ceramic and other substrate board materials.
  • the multiple metal layers further include a plurality of first metal layers and at least one second metal layer that are continuously arranged.
  • the difference between the first metal layer and the second metal layer is : In a direction parallel to the top surface of the substrate, the edge of the first metal layer extends to the outside edge of the substrate, and the distance between the edge of the second metal layer and the side of the first conductive pillar away from the outside of the substrate is greater than the second distance, The second distance is smaller than the first distance.
  • the first conductive pillar penetrates at least two first metal layers.
  • the surrounding edges of the second metal layer are not exposed to the outside of the substrate, but are isolated from the outside world by the insulating material of the substrate and are not penetrated by the first conductive pillars. Since the chip packaging structure provided in this application is cut from multiple integrally formed packaging structures, and the sides of the chip packaging structure are the cutting surfaces formed during cutting, in this implementation, the second metal The surrounding edges of the layer are not exposed to the outside of the substrate, which means that the second metal layer is not cut during cutting. Since the more metal layers are cut, the greater the wear on the cutting blade, so this implementation can save costs.
  • the number of second metal layers is multiple, and at least two second metal layers are continuously provided, and the second conductive pillar penetrates the continuous at least two second metal layers.
  • the second conductive pillar has two functions. One is to connect one of the metal layers penetrated by the first conductive pillar and the metal layer on the bottom surface of the substrate; the other is to realize the penetration of multiple metal layers. Electrical interconnection between second metal layers. Or it can be understood that in the embodiment of the present application, the second conductive pillar in the substrate is reused, and on the basis of realizing the original electrical interconnection function, it is used to realize the grounding of the shielding layer, or in other words, it is used as Form part of the electromagnetic shielding cavity.
  • the insulating layer includes a core plate; the first conductive pillar is located on a side of the core plate close to the chip, and the second metal layer is located on a side of the core plate away from the chip. That is to say, the core board divides the substrate into upper and lower parts, and the first conductive pillar is located on the upper part of the substrate.
  • This implementation method is to reduce the side area of the substrate that the shielding layer needs to cover as much as possible, thereby reducing the possibility of the shielding layer falling off due to poor bonding reliability between the shielding layer and the substrate, that is, to enhance the reliability of the electromagnetic shielding cavity. sex.
  • the shielding layer needs to cover the corresponding side area of the upper part of the substrate and the side area of the core board in order to extend to the exposed first contact surface of the first conductive pillar. If the first conductive pillar is located on the upper part of the substrate, the shielding layer does not need to cover the side area, so the side area of the substrate that the shielding layer needs to cover can be reduced.
  • the plurality of first conductive pillars provided on the first side of the substrate are distributed on a first straight line parallel to the boundary line of the first side; or, the plurality of first conductive pillars provided on the first side of the substrate are The distance between the plurality of first conductive pillars on the first side and the first straight line falls within a preset distance range; the first side is any side of the substrate.
  • the beneficial effects of this implementation please refer to the technical effects regarding the distribution type of the plurality of first conductive pillars in the second aspect below.
  • embodiments of the present application provide a method for manufacturing a chip packaging structure.
  • an integrated packaging structure to be cut is first obtained, wherein the integrated packaging structure includes a plurality of integrally formed substrates and a chip disposed on the top surface of each substrate; each substrate includes a plurality of first conductive pillars and a plurality of metal layers arranged in a stack, and each first conductive pillar penetrates at least two metal layers.
  • the integrated packaging structure is cut for the first time.
  • the purpose of the first cutting is to expose at least the first contact surface of the first conductive pillar facing the top surface of the substrate.
  • a shielding layer is formed outside the chip, and the shielding layer is connected to the first conductive pillar through the first contact surface.
  • the purpose of forming the shielding layer here is to form a fully enclosed electromagnetic shielding cavity.
  • the above-mentioned first cutting of the integrated packaging structure specifically includes: cutting the integrated packaging structure for the first time along a first preset cutting path.
  • the first preset cutting lane intersects with the area where the cross section of the first conductive pillar is located; the depth of the first preset cutting lane is greater than the distance between the top surface of the substrate and the first end surface of the first conductive pillar, and is smaller than the distance between the top surface of the substrate and the first end surface of the first conductive pillar.
  • the distance between the second end surfaces of a conductive pillar, the first end surface is the end surface of the first conductive pillar close to the top surface of the substrate, and the second end surface is the end surface of the first conductive pillar away from the top surface of the substrate.
  • the first conductive pillar can be cut at least to expose the first contact surface through the first cutting.
  • the above-mentioned second cutting of the integrated packaging structure specifically includes: cutting the integrated packaging structure for the second time along the second preset cutting path.
  • the first preset cutting lane and the second preset cutting lane located between two adjacent substrates have the same symmetry axis in the direction parallel to the edge of the cutting lane, that is, both sides of the first preset cutting lane
  • the symmetry axis of the edge is the same as the symmetry axis of both sides of the second preset cutting lane
  • the width of the first preset cutting lane is greater than the width of the second preset cutting lane.
  • the exposed contact surface of the first conductive pillar also includes a second contact surface facing the outside of the substrate, and the second contact surface forms a gap with the first contact surface; the above is for the first time
  • the cut integrated packaging structure forms a shielding layer outside the chip and connects the shielding layer to the first conductive pillar through the first contact surface, including: connecting the shielding layer to the first conductive pillar through the first contact surface and the second contact surface. column connection.
  • the edge of the first preset cutting lane intersects the cross-sectional area of the first conductive pillar.
  • the intersection of the first preset cutting lane and the cross-sectional area of the first conductive pillar can be divided into two situations. One is that the edge of the first preset cutting track intersects the cross-sectional area of the first conductive pillar. Not intersecting, this situation can be understood as the first conductive pillar is completely included in the first cutting lane. In this case, the first conductive pillar can be exposed with an end surface facing the top surface of the substrate. The second is that the edge of the first preset cutting lane intersects with the cross-sectional area of the first conductive pillar.
  • the first conductive pillar is not completely included in the first preset cutting lane.
  • the first conductive pillar can be exposed to a surface facing the top surface of the substrate and a surface facing the first preset cutting lane, and the two surfaces are connected to form a gap.
  • the metal layers penetrated by the first conductive pillars are all located inside the substrate; the substrate further includes second conductive pillars, and the metal layer on the bottom surface of the substrate is connected to the first conductive pillar through the second conductive pillars. Any metal layer that the column penetrates. In a direction parallel to the top surface of the substrate, a distance between an edge of a side of the first cutting track close to the second conductive pillar and the second conductive pillar is greater than the third distance.
  • a plastic sealing material layer is provided on the top surface of the substrate, and the chip is wrapped in the plastic sealing material layer; for the integrated packaging structure after the first cutting, a shielding layer is formed outside the chip, including : A shielding layer is formed on the upper surface of the plastic sealing material layer and the cutting surface produced by the first cutting.
  • the cutting surface includes the first contact surface, the exposed outer side of the plastic sealing material layer and the exposed surface of the substrate between the first contact surface and the substrate. The outer side between the top surfaces.
  • the deflection of the cutting knife means the deflection of the cutting track, and/or the position of the edge of the cutting track changes.
  • the direct impact of the offset of the cutting knife is that the first preset cutting lane does not intersect with the first conductive pillar, or the first The edge of the preset cutting track does not intersect with the area where the cross section of the first conductive pillar is located. Then, two situations may occur. One is that the first conductive pillar is not cut at all, so that after the cutting is completed, no surface of the first conductive pillar is exposed. The second method is to cut the first conductive pillar so that its complete end surface is exposed, but no gap is formed, and no gap will be formed after the second cutting.
  • a plurality of first conductive pillars provided on the first side of the substrate are distributed parallel to the boundary line of the first side. on the first straight line; or, the distance between the plurality of first conductive pillars arranged on the first side of the substrate and the first straight line falls within a preset distance range; the first side is any side of the substrate.
  • the plurality of first conductive pillars located on the same side of the substrate may not be completely located on the same straight line, or in other words, these first conductive pillars They can be arranged staggered relative to a certain straight line, and the distance between each first conductive pillar and the straight line is less than a certain distance threshold. That is to say, these first conductive pillars are distributed in a specified area. Then, even if the cutting tool deviates within this area, it is guaranteed to cut a part of the first conductive pillar.
  • embodiments of the present application provide a method for manufacturing a chip packaging structure, which method includes:
  • an integrated substrate is prepared. It should be understood that the integrated substrate here is the substrate of the integrated packaging structure mentioned in the second aspect, and the integrated substrate can be cut into multiple substrates.
  • the integrated substrate includes multiple groups of first conductive pillars and a plurality of metal layers arranged in a stack.
  • the first conductive pillars penetrate at least two metal layers.
  • the top surface of the integrated substrate includes each group of first conductive pillars on the top surface of the integrated substrate.
  • the integrated packaging structure is then cut for the first time so that each group of first conductive pillars exposes the first contact surface facing the top surface; after that, the plastic packaging material is A shielding layer is formed on the upper surface of the layer and the cutting surface produced by the first cutting, and the cutting surface includes the first contact surface; finally, the integrated packaging structure is cut for the second time to separate multiple chip packaging structures.
  • the shielding layer on the chip packaging structure is connected to the first conductive pillar through the first contact surface, and the first conductive pillar is used to ground the shielding layer.
  • the above-mentioned preparation of the integrated substrate specifically includes: first using an insulating material to prepare a core board; then forming a plurality of first metal layers on one side of the core board, and forming multiple groups of first conductive pillars penetrating at least two first metal layers; the plurality of first metal layers are stacked in the vertical direction of the top surface of the substrate and spaced by the first insulating layer; and, on the other side of the core board, forming Multiple sets of second metal layers; wherein each set of second metal layers are stacked in the vertical direction on the top surface of the substrate and separated by a second insulating layer; multiple second metal layers in the same set of second metal layers are formed respectively In multiple preset areas on the same surface, the distance between the edge of the second metal layer in any preset area and the edge of the preset area is greater than the fourth distance; the second insulating layer has an edge extending along the vertical direction of the surface.
  • the protrusions are separated by protrusions between the second metal layers on the same surface; the surface here includes the other side surface of the core plate and the surface of the second insulating layer away from the core plate, which is used to form the third
  • the plurality of preset areas on the surface are respectively the areas surrounded by the mapping positions of each group of first conductive pillars on the surface.
  • a set of first conductive pillars includes multiple parts, and the mapping positions of the first conductive pillars on the top surface of each part are respectively located on each side of the chip mounting area; wherein, the first part The mapping positions of the first conductive pillars on the top surface are distributed on a certain straight line or the distance from a certain straight line is within a preset distance range, and the first part is any one of the so-called plurality of parts.
  • the above-mentioned preparation of the integrated substrate further includes: forming multiple groups of second conductive pillars, the same group of second conductive pillars on the above-mentioned surface (that is, the surface on which a group of second metal layers are formed)
  • the mapping positions on the substrate are located in the same preset area; wherein the second conductive pillars penetrate a plurality of second metal layers and connect at least one first metal layer penetrated by the first conductive pillars and the metal layer located on the bottom surface of the substrate.
  • the distance between the mapping position of the second conductive pillar in a certain preset area and the edge of the preset area is greater than the fifth distance.
  • embodiments of the present application provide an electronic device, including a motherboard and the chip packaging structure described in the above embodiments.
  • the motherboard is located on the side surface of the substrate away from the chip in the chip packaging structure and is connected to the chip packaging structure. Since the chip packaging structure in the electronic device of the embodiment of the present application is the same as the chip packaging structure described in the above embodiment, both can solve the same technical problem and obtain the same technical effect, which will not be described again here.
  • Figure 1 is a schematic structural diagram of an electronic device in an embodiment of the present application.
  • Figure 2 is an exploded view of the electronic device according to the embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a motherboard assembly in an electronic device according to an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a chip packaging structure in an electronic device according to an embodiment of the present application.
  • Figure 5A is a top schematic diagram of an integrated packaging structure in the related art
  • Figure 5B is a cross-sectional view of the integrated packaging structure shown in Figure 5A based on the cutting direction and section line M1-N1;
  • Figure 6 is a schematic diagram of a chip packaging structure in related technologies
  • Figure 7A is a top schematic diagram of an integrated packaging structure in an embodiment of the present application.
  • Figure 7B is a cross-sectional view of the integrated packaging structure shown in Figure 7A based on the cutting direction and section line M2-N2;
  • Figure 8 is a cross-sectional view of another integrated packaging structure in an embodiment of the present application.
  • Figure 9 is a cross-sectional view of yet another integrated packaging structure in an embodiment of the present application.
  • Figure 10 is a schematic diagram when one of the metal layers in the embodiment of the present application is a metal wiring layer
  • FIGS 11A and 11B are schematic diagrams of cutting lanes in the manufacturing method of the chip packaging structure according to the embodiment of the present application, shown in conjunction with Figure 7A and Figure 7B;
  • Figure 12 is a schematic diagram of the integrated packaging structure obtained after the first cutting of the integrated packaging structure shown in Figures 7A and 7B using the manufacturing method of the packaging structure according to the embodiment of the present application;
  • Figure 13 is a schematic diagram of the exposed surface of the first conductive pillar after the first cutting
  • Figure 14 is a schematic diagram of the integrated packaging structure obtained after forming a shielding layer on the integrated packaging structure shown in Figure 13 using the manufacturing method of the packaging structure according to the embodiment of the present application;
  • Figure 15 is a schematic diagram of the chip packaging structure obtained after the second cutting of the integrated packaging structure shown in Figure 14 using the manufacturing method of the packaging structure according to the embodiment of the present application;
  • Figure 16 is a schematic diagram of the integrated packaging structure obtained after the first cutting of the integrated packaging structure shown in Figure 8 using the manufacturing method of the packaging structure according to the embodiment of the present application;
  • Figure 17 is a schematic diagram of the integrated packaging structure obtained after forming a shielding layer on the integrated packaging structure shown in Figure 16 using the manufacturing method of the packaging structure according to the embodiment of the present application;
  • Figure 18 is a schematic diagram of the chip packaging structure obtained after the integrated packaging structure shown in Figure 17 is cut for the second time using the manufacturing method of the packaging structure according to the embodiment of the present application;
  • Figure 19 is a schematic diagram of the integrated packaging structure obtained after the first cutting of the integrated packaging structure shown in Figure 9 using the manufacturing method of the packaging structure according to the embodiment of the present application;
  • Figure 20 is a schematic diagram of the integrated packaging structure obtained after forming a shielding layer on the integrated packaging structure shown in Figure 19 using the manufacturing method of the packaging structure according to the embodiment of the present application;
  • Figure 21 is a schematic diagram of the chip packaging structure obtained after the integrated packaging structure shown in Figure 20 is cut for the second time using the manufacturing method of the packaging structure according to the embodiment of the present application;
  • Figure 22 is a schematic diagram of a cutting scene in which the cutting knife is offset in an embodiment of the present application.
  • Figure 23 is a schematic diagram of the distribution pattern of the first conductive pillars in the embodiment of the present application.
  • Figure 24 is a flow chart of a method for manufacturing a chip packaging structure shown in an embodiment of the present application.
  • first, second, etc. are only used for descriptive purposes to distinguish the same or similar items with substantially the same functions and effects, and shall not be understood as indicating or implying relative importance or implicitly specifying what is indicated. Number of technical features. Thus, features defined by “first,” “second,” etc. may explicitly or implicitly include one or more of such features.
  • the side of the substrate used for placing the chip may be called its “top surface”, and the side of the substrate opposite to its “top surface” , that is, the side used to connect to the motherboard of the electronic device is called the “bottom side”, and the remaining surface of the substrate is its “side”.
  • a spatial rectangular coordinate system is established in some drawings of this application.
  • top surface and a bottom surface involved in the embodiments of the present application can be described as surfaces parallel to the X-Y plane shown in the drawings, and a certain “side surface” is a surface perpendicular to the X-Y plane, such as A surface parallel to the X-Y plane, or a surface parallel to the X-Y plane.
  • connection should be understood in a broad sense.
  • connection can be a mechanical connection, which can be a fixed connection, a detachable connection, or an integrated connection; it can also be an electrical connection.
  • sexual connection but also communication connection. It can be directly connected or indirectly connected through an intermediary.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or explanations. Any embodiment or design described as “exemplary” or “such as” in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner that is easier to understand.
  • ICT information and communication technologies
  • the main purpose of the embodiments of the present application is to provide a chip packaging structure and a method of manufacturing the chip packaging structure (hereinafter referred to as the manufacturing method).
  • the chip packaging structure can be a standard SIP product, or called a SIP standard part.
  • the chip packaging structure can be integrated into electronic equipment to realize multiple functions of the electronic equipment.
  • inventions of the present application also provide an electronic device including the chip packaging structure.
  • the electronic device can be an electronic device in the field of ICT technology, such as a server, optical communication equipment, mobile phone, tablet personal computer (tablet personal computer) , laptop computer, personal digital assistant (PDA), camera, personal computer, notebook computer, vehicle-mounted device, wearable device, augmented reality (AR) glasses, AR helmet, virtual Reality (virtual reality, VR) glasses or VR helmets and other devices that require data processing/storage/transmission and reception.
  • ICT technology such as a server, optical communication equipment, mobile phone, tablet personal computer (tablet personal computer) , laptop computer, personal digital assistant (PDA), camera, personal computer, notebook computer, vehicle-mounted device, wearable device, augmented reality (AR) glasses, AR helmet, virtual Reality (virtual reality, VR) glasses or VR helmets and other devices that require data processing/storage/transmission and reception.
  • AR augmented reality
  • VR virtual reality
  • VR virtual reality
  • FIG. 1 is a perspective view of an electronic device provided by some embodiments of the present application
  • FIG. 2 is an exploded view of the electronic device shown in FIG. 1
  • the electronic device 1000 is a mobile phone.
  • the electronic device 1000 may include a screen 100 as shown in FIG. 1 , a middle frame 200 , a rear case 300 , and a motherboard 400 fixed on the middle frame 200 .
  • FIG. 1 and FIG. 2 only illustrate some components included in the electronic device 1000 , and the actual shapes, actual sizes, actual positions and actual configurations of these components are not limited by FIGS. 1 and 2 .
  • the electronic device 1000 may not include the screen 100 .
  • the electronic device 1000 may also include a camera 500 as shown in FIG. 2 .
  • the electronic device 1000 further includes a chip packaging structure 600 as shown in FIG. 3 .
  • the chip packaging structure 600 is disposed on the motherboard 400 and connected to the motherboard 400 .
  • the chip packaging structure 600 can be connected to the motherboard 400 through a ball grid array (BGA) or multiple arrays of copper pillar bumps (CPB), so that the chip packaging structure 600 can be connected to the motherboard 400 .
  • BGA ball grid array
  • CPB copper pillar bumps
  • Other devices or device stack structures on the mainboard 400 implement signal transmission.
  • mainboard 400 can be a printed circuit board (PCB).
  • PCB printed circuit board
  • the number of chip packaging structures 600 on the motherboard 400 may be one, two, or more than two, which is not limited by this application.
  • the plane where the motherboard 400 is located is the XY plane.
  • the The range is approximately perpendicular to the direction of the motherboard 400 .
  • the two surfaces of the motherboard 400 along the Z axis can be the bottom surface and the top surface of the motherboard 400 respectively, and the two surfaces of the motherboard 400 along the X axis and its surface along the Y axis.
  • the two surfaces may be the four sides of the motherboard 400 .
  • the chip packaging structure 600 is disposed on the top surface of the motherboard 400 .
  • the mainboard 400 is a rectangular parallelepiped.
  • the mainboard 400 may also be in a square, polygon, or other shape.
  • the embodiment of the present application does not limit the shape of the mainboard 400 .
  • the chip packaging structure 600 may include a substrate (SUB) 1 , a chip 2 disposed on the substrate 1 , and a molding material layer (molding) 3 wrapping the chip 2 .
  • the plastic sealing material layer 3 here can also be called a plastic sealing structure.
  • the substrate 1 is used in a chip packaging process, it is used to carry chips or chip stack structures to form a chip packaging structure 600 .
  • the top surface, bottom surface and interior of the substrate 1 have high-density interconnection lines for realizing connections between different chips 2 or between the chips 2 and the motherboard 400 .
  • the interconnection may be a metal layer, such as a copper layer, a patterned interconnection/circuit structure, or a wiring layer and/or a rewiring layer.
  • the two surfaces of the substrate 1 along the Z-axis direction are the bottom surface and the top surface respectively, and the chip 2 is disposed on the top surface of the substrate 1 .
  • a solder ball array 11 is provided on the bottom surface of the substrate 1 for realizing the connection between the interconnection lines in the substrate and the mainboard 400 .
  • the number of chips 2 in the chip packaging structure 600 may be one or multiple, which is not limited in this application.
  • the above-mentioned chip 2 can be a processing chip with a data processing function, such as a central processing unit (CPU), a system on chip (SOC) or an image processor (graphics processing unit, GPU) that can process data. chip for processing.
  • a data processing function such as a central processing unit (CPU), a system on chip (SOC) or an image processor (graphics processing unit, GPU) that can process data. chip for processing.
  • the above-mentioned memory can be random access memory (RAM) or read-only memory (ROM).
  • the above-mentioned chip may include active electronic devices, passive electronic devices, and devices such as MEMS or optical devices.
  • circuit devices such as diodes, resistors, resistor networks, capacitors, inductors, transformers, relays, switches, etc.
  • pld programmable logic device
  • MPU microprocessor
  • MCU microcontroller
  • dsp device digital signal processor, DSP
  • the technology forms an electromagnetic shielding cavity by forming an electromagnetic shielding material film layer (hereinafter referred to as the shielding layer) on the outer surface of the chip packaging structure 600, and the electronic devices in the chip packaging structure 600 are enclosed in the electromagnetic shielding cavity.
  • the shielding layer an electromagnetic shielding material film layer
  • the electronic shielding function realized by the electromagnetic shielding cavity is the electromagnetic self-shielding function of the chip packaging structure 600 .
  • Integrated packaging structures usually include hundreds or thousands of integrally formed single-piece packaging structures.
  • the manufacturing process of the chip packaging structure 600 usually includes the step of cutting the integrated packaging structure to separate the single-piece packaging structures, and then making a shielding layer for each single-piece packaging structure to Form an electromagnetic shielding cavity.
  • FIG. 5A is a schematic diagram of the top surface (X-Y plane) of an integrated packaging structure to be cut in the related art.
  • FIG. 5A is a cross-sectional view of the top surface of the integrated packaging structure based on the cutting direction and the cross-section line M1-N1.
  • the integrated packaging structure includes four integrally formed single-piece packaging structures, namely packaging structure 510 , packaging structure 520 , packaging structure 530 and packaging structure 540 . Based on the cutting lines and cutting directions shown, the integrated packaging structure and the four single-piece packaging structures can be cut out.
  • the cutting line here refers to a linear mark used to indicate the cutting position or the edge position of the cutting track, rather than a linear cutting tool.
  • the cutting track is located between two adjacent single-piece packaging structures. It can be understood as a channel with a certain width and depth produced when a cutting tool is used to cut at the position indicated by the cutting line. Wherein, the width of the cutting track is the size of the cutting track in the X-axis direction, and the depth of the cutting track is the size of the cutting track in the Y-axis direction. Since the four single-piece packaging structures are exactly the same, the characteristics of the integrated packaging structure will be described using the packaging structure 510 as an example. It can be seen that in the packaging structure 510 , the substrate 1 includes a plurality of metal layers 12 arranged in a stack.
  • One of the plurality of metal layers 12 is formed on the top surface of the substrate 1 , one is formed on the bottom surface of the substrate 1 , and the rest are formed on the substrate 1 . internal. Except for the metal layer formed on the bottom surface, the other metal layers 12 all extend outward to the surrounding edges of the substrate 1, or in other words, extend to the cutting position.
  • the substrate 1 also includes conductive pillars 13 , and the conductive pillars 13 penetrate through the plurality of metal layers 12 .
  • the substrates of multiple single-piece packaging structures are integrally formed to form an integrated substrate.
  • the integrated substrate here is the substrate of the integrated packaging structure.
  • FIG. 5A the related art examples shown in FIG. 5A, FIG. 5B, and FIG. 6 have the following drawbacks.
  • Defect 1 The position of the cutting line causes multiple metal layers below the cutting line, and when cutting, it is cut from the top surface of the integrated packaging structure to the bottom surface of the integrated packaging structure, which means that it will be cut into the substrate 1 All metal layers 12. It is easy to understand that since the hardness of the metal layer is greater than the hardness of the substrate material, the more metal layers 12 are cut, the greater the wear of the cutting blade (such as the saw blade) and the higher the cost.
  • Defect 2 During the actual cutting process, the cutting knife (which can also be a laser) is likely to be offset in the left/right direction (the X-axis direction in Figure 5A), which will cause the actual cutting position to be different from that in the process design. There is a slight error compared to the expected cutting position. Once the cutting knife is offset, the conductive pillar 13 may be cut off as a whole, or the conductive pillar 13 may not be cut at all. No matter which situation occurs, the shielding layer will not be connected to the metal layer on the bottom of the substrate, and will not be grounded, making it impossible to achieve electromagnetic shielding.
  • Defect 3 After cutting is completed, a shielding layer needs to be formed on the side of each single-piece packaging structure, so the positions of multiple single-piece chip packaging structures need to be laid out. That is, multiple single-piece chip packaging structures are placed at a distance from each other at a location convenient for preparing the shielding layer.
  • the layout process increases the complexity of the overall production process.
  • the shielding layer is connected to the conductive pillar 13 by contacting the exposed side of the conductive pillar 13 . Based on the formation process of the shielding layer, such as the sputtering process, since the shielding layer that can be formed on the side is thin, the contact reliability between the shielding layer and the conductive pillar 13 is poor, and the contact resistance is poor, resulting in poor shielding effect.
  • Defect 5 Since film-forming processes such as sputtering, spraying and electroplating are generally used to form shielding layers on the upper surface and sides of the chip packaging structure, it is easy to splash the electromagnetic shielding material onto the solder balls 11 (or solder joints) on the bottom surface of the substrate 1 plate). In order to prevent the electromagnetic shielding material from being splashed onto the solder balls 11 on the bottom surface of the substrate 1, the distance between the solder balls 11 and the surrounding edges of the substrate 1 is required to be far enough, usually 150um. In some scenarios, it is necessary to increase the chip package size. Meeting this requirement is contrary to the requirements of electronic equipment for miniaturization of chip packaging structures.
  • Defect 6 Since the shielding layer covers the outermost area of the substrate, it is very easy to cause the shielding layer to fall off due to factors such as collision/vibration.
  • Embodiments of the present application provide a chip packaging structure and a manufacturing method thereof.
  • Each achievable design of the chip packaging structure and its manufacturing method can eliminate at least one of the above defects, or eliminate multiple of the above defects at the same time. indivual. That is, the chip packaging structure provided by the embodiment of the present application has reliable electromagnetic self-shielding function. In this way, when it is applied to electronic equipment, the electronic device can effectively reduce electromagnetic interference, and can also reduce the interference of the electronic device to other electronic devices.
  • the chip packaging structure provided by the embodiment of the present application is a standard chip packaging structure obtained by processing the integrated packaging structure provided by the present application using the manufacturing method provided by the present application.
  • the integrated packaging structure and the manufacturing method are first introduced below to facilitate readers to understand the inventive concept of the present application based on the causal relationship between the manufacturing method and the obtained product.
  • FIG. 7A is a schematic diagram of the top surface (X-Y plane) of an integrated packaging structure to be cut in the related art.
  • FIG. 7B is a cross-sectional view of the top surface of the integrated packaging structure based on the cutting direction and the cross-section line M2-N2.
  • the integrated packaging structure simulation can be divided into four single-piece packaging structures, namely packaging structure 710, packaging structure 720, packaging structure 730 and packaging structure 740.
  • the integrated packaging structure includes four integrally formed single-piece packaging structures, and the structures of the four single-piece packaging structures are exactly the same.
  • the integrated packaging structure may include more integrally formed single-piece packaging structures, and the structures of different single-piece packaging structures may also be different, which is not limited by this application.
  • any design is described When using an integrated packaging structure, one of the single-piece packaging structures will be taken as an example.
  • the packaging structure 710 includes a substrate 1 (the reference number of the substrate 1 is not shown in FIG. 7B ) and a chip 2 mounted on the top surface of the substrate 1 .
  • the chip 2 is wrapped in a plastic layer 3 .
  • the substrate 1 includes a plurality of insulating layers 14 and a plurality of metal layers 12 composed of insulating materials (such as polypropylene, ceramics and other substrate materials).
  • the plurality of metal layers 12 are shown as L1, L2, L3, L3, L4, L5 and L6.
  • the plurality of metal layers 12 are stacked in a direction perpendicular to the top surface of the substrate 1 (ie, the Z-axis direction). Two adjacent metal layers 12 are separated by an insulating layer 14 .
  • L1 is formed on the top surface of the substrate 1
  • L2 , L3 , L3 , L4 and L5 are formed inside the substrate 1
  • L6 is formed on the bottom surface of the substrate 1 .
  • any two adjacent single-piece packaging structures such as the above-mentioned packaging structure 710 and the packaging structure 720, or the above-mentioned packaging structure 710 and the packaging structure 730, are on the same layer.
  • the provided metal layers 12 may be integrally formed or may have gaps between them.
  • the metal layer L2 in the packaging structure 710 and the metal layer L2 in the packaging structure 120 are integrally formed, that is, there is no gap between them; and the metal layer L4 in the packaging structure 710 and the metal layer L4 in the packaging structure 120 are formed integrally.
  • the two are not integrally formed, that is, they are separated by insulating materials.
  • a part of the metal layer 12 extends outward to the cutting line and the cutting lane indicated by the cutting direction.
  • the other part of the metal layer 12 extends outward to a position away from the edge D of the cutting lane.
  • the purpose of this design is to ensure that all the metal layers 12 can be avoided during cutting. For example, only the metal layers extending to the cutting lanes will be cut, and the metal layers that do not extend will not be cut. At the same time, it can also be ensured that in the obtained chip packaging structure, a part of the metal layer 12 is still wrapped in insulating material.
  • the metal layer extending to the dicing lane is called the first metal layer (or first metal layer), and the metal layer that does not extend to the dicing lane is called the second metal layer ( Or called the first metal layer).
  • the substrate 1 further includes a plurality of first conductive pillars 15 , and the plurality of first conductive pillars 15 are distributed on four sides of the substrate 1 .
  • the first conductive pillar 15 penetrates at least two first-type metal layers.
  • the first conductive pillar 15 penetrates the metal layers L2 and L3.
  • the first conductive pillar 15 can also be connected to two different first-type metal layers through its two ends without penetrating the two first-type metal layers.
  • the substrate 1 also includes a plurality of second conductive pillars 16.
  • the second conductive pillars 16 are located on the side of the first conductive pillar 15 away from the cutting position (cutting lane), and two The distance between the two axes is greater than the sum of their radii. That is to say, relative to the first conductive pillars 15 , the second conductive pillars 16 are disposed close to the inside of the substrate. At least one of the plurality of metal layers 12 penetrated by the first conductive pillar 15 is connected to the metal layer on the bottom surface of the substrate through the second conductive pillar 16 . At the same time, the second conductive pillar 16 also penetrates multiple second metal layers. For example, in the package structure 710 shown in FIG. 7B , one end of the second conductive pillar 16 is connected to L3, and the other end is connected to L6 in the form of penetrating L6. In addition, the second conductive pillar 16 also penetrates L4 and L5 at the same time.
  • the second conductive pillar 16 has two functions. One is to connect one of the metal layers 12 penetrated by the first conductive pillar 15 and the metal layer 12 on the bottom surface of the substrate 1 . ; The second is used to achieve electrical interconnection between multiple second-type metal layers that it penetrates. Moreover, the position of the second conductive pillar 16 can ensure that it is still wrapped in insulating material after cutting.
  • the distance between the second conductive pillar 16 and the side of the first conductive pillar 15 away from the first cutting lane is D1, and D1 is greater than zero.
  • the distance between the edge of the second metal layer and the side of the first conductive pillar away from the first cutting lane is D2, D2 is greater than zero, and D1 is greater than D2.
  • the distance between the edge of the first cutting lane close to the second conductive pillar 16 and the second conductive pillar 16 is D3, and D3 is greater than D1.
  • the first conductive pillar 15 and the second conductive pillar 16 are ground holes filled with metal materials.
  • the first conductive pillar 15 is connected to the ground circuit on the bottom surface of the substrate 1 through the second conductive pillar 16.
  • the ground circuit here is It belongs to the circuit in the metal layer on the bottom surface of the substrate.
  • each first conductive pillar 15 penetrates the same number of metal layers 12, and the metal layers 12 penetrated/connected by it are all the above-mentioned first-type metal layers, and are all formed inside the substrate 1. Furthermore, among them A first metal layer needs to be connected to the ground circuit on the underside of the substrate through the second conductive pillar 16.
  • the metal layer inside the substrate may include and only include third elements such as L2 and L3 mentioned above.
  • a type of metal layer, the first conductive pillars can penetrate more first type metal layers, and/or the first conductive pillars located on different sides of the substrate can penetrate different numbers of the first metal layers.
  • metal-like layer For example, referring to FIG. 8 , a cross-sectional view in the cutting direction of a certain integrated packaging structure is shown. Among them, in the packaging structure 810 and the packaging structure 820, L1, L3, L3, L4 and L5 all extend to the cutting lane, that is, they all belong to the first type of metal layer defined above.
  • the first conductive pillar 15 on the left side of the substrate 1 penetrates L2 and L3, and the first conductive pillar 15 on the right side of the substrate 1 penetrates L1, L2, and L3.
  • the first conductive pillar 15 on the left side of the substrate 1 penetrates L1, L2 and L3, and the first conductive pillar 15 on the right side of the substrate 1 penetrates L2 and L3.
  • the substrate of the single-piece packaging structure may also include and only include second-type metal layers such as the above-mentioned L4 and L5.
  • the first conductive pillar penetrates at least two metal layers therein, and there are One is formed on the bottom surface of the substrate.
  • FIG. 9 a cross-sectional view of a certain integrated packaging structure in the cutting direction is shown.
  • the edges of L1, L3, L3, L4, L5 and L6 do not all extend to the dicing lane, that is, they all belong to the second type of metal layer defined above.
  • the first conductive pillar 15 penetrates L1, L3, L3, L4, L5 and L6.
  • one of the plurality of insulating layers 14 is the core plate 141 .
  • the first metal layer and the first conductive pillar 15 are both formed on the side of the core plate 141 close to the chip 2 .
  • a second-type metal layer is formed on the bottom surface of the substrate 1 , and the remaining second-type metal layers and the second conductive pillars 16 are formed on the side of the core plate 141 away from the chip 2 .
  • FIGS. 7A to 9 do not include all possible integrated packaging structures provided by the embodiments of the present application.
  • it may also include more or less metal layers, and may also include conductive pillars whose number, function and/or location are different from the above examples.
  • the metal layer mentioned in the above embodiments may be a metal film layer that completely covers one surface of the insulating structure, or it may be a metal wiring layer as shown in FIG. 10 .
  • an integrated packaging structure is obtained, such as the integrated packaging structure shown in FIGS. 7A to 9 above.
  • the integrated packaging structure is cut for the first time along the first cutting path.
  • the purpose of the first cutting is to expose at least the first contact surface of the first conductive pillar facing the top surface of the substrate.
  • the first conductive pillar is exposed to a first contact surface facing the top surface of the substrate, and a second contact surface facing the side of the substrate.
  • the second contact surface here and the first contact surface may form a gap, such as a "right angle shape" gap.
  • a shielding layer is formed on the top surface of the plastic sealing material layer and the cutting surface formed by the first cutting, and the shielding layer is passed through the exposed first conductive pillar.
  • the surface (the above-mentioned first contact surface, or the above-mentioned first contact surface and the second contact surface) is connected to the first conductive pillar.
  • the cutting surface formed by the first cutting includes the exposed outer side of the plastic layer, the first contact surface, and the exposed outer side of the substrate between the first contact surface and the top surface of the substrate.
  • the purpose of forming the shielding layer here is to form an electromagnetic shielding cavity, and the shielding layer and the first conductive pillar connected to it are all components of the electromagnetic shielding cavity.
  • the electronic devices in the single-piece packaging structure are wrapped in the electromagnetic shielding cavity.
  • the shielding layer can achieve the function of electromagnetic interference shielding. Since the first cutting process can ensure that at least one surface of the first conductive pillar is exposed, that is, the first contact surface, when forming the shielding layer, it can also be ensured that the shielding layer can be connected to the first conductive pillar through the first contact surface. .
  • the integrated packaging structure obtained in the above steps is cut for a second time along the second cutting lane to obtain multiple independent chip packaging structures.
  • the purpose of the second cutting is the same as the purpose of the first cutting, that is, to expose at least the first contact surface of the first conductive pillar, or to expose the first contact surface and the second contact surface. That is to say, the exposed first contact surface of the first conductive pillar, or the exposed first contact surface and the second contact surface, are formed through the process of the first cutting and the second cutting.
  • Another purpose of the second cutting is to completely separate multiple chip packaging structures connected together to obtain multiple independent chip packaging structures.
  • the first cutting lane represents the cutting lane of the first cutting process
  • the second cutting lane represents the cutting lane of the second cutting process.
  • the distance between the upper end surface of one conductive pillar 15 and the top surface of the substrate is smaller than the distance between the lower end surface of the first conductive pillar 15 and the top surface of the substrate.
  • the so-called upper end surface is the end surface of the first conductive pillar 15 close to the top surface of the substrate
  • the so-called lower end surface is the end surface of the first conductive pillar 15 away from the top surface of the substrate. That is to say, the first cutting lane intersects the first conductive pillar 15 , but the first conductive pillar is not completely included in the first cutting lane.
  • the first conductive pillar 15 can be exposed to a surface facing the top surface of the substrate and a surface facing the first cutting lane, and the two surfaces are connected to form a "right-angled" notch.
  • the symmetry axis of the two side edges of the first cutting tract is the same as the symmetry axis of the two side edges of the second cutting tract, that is, the two side edges of the first cutting tract and the two side edges of the second cutting tract are about the same
  • a straight line is symmetrical, and the width W1 of the first cutting track is greater than the width W2 of the second cutting track.
  • FIG. 12 shows the integrated packaging structure obtained after the first cutting of the integrated packaging structure shown in FIG. 7B along the above-mentioned first cutting path.
  • the first conductive pillar 15 exposes a surface S1 facing the top surface of the substrate, and a surface S2 facing the outside of the substrate.
  • the cutting surfaces produced by the first cutting process include: the exposed outer side of the plastic layer 3, the surface S1, and the exposed outer side of the substrate 1 between the surface S1 and the top surface of the substrate, where , the exposed outer side of the substrate 1 includes the surface S2.
  • first cutting process can also expose the third contact surface of the first conductive pillar 15, and the first contact surface and the second contact surface can be connected through the third contact surface. It should be understood that based on the shape of the cutting tool, different shapes of the third contact surface can be generated. For example, a plane S3 as shown in a in Figure 13 can be generated, or a curved surface as shown in b in Figure 13 can be generated. S3.
  • the first cutting track intersects the first conductive pillar 15 , but the edge of the first cutting track does not intersect with the area where the cross section of the first conductive pillar 15 is located. That is to say, the first conductive pillar is completely contained in the first cutting lane. In this case, the first conductive pillar can be exposed with an end surface facing the top surface of the substrate. For details, see Scenario 2 shown in FIG. 22 .
  • a shielding layer 4 is formed on the upper surface of the plastic layer 3 and the cutting surface produced by the first cutting, so that the shielding layer 4 covers the chip 2 outside, and is connected to the first conductive pillar 15 through the surface S1 and the surface S2, that is, an integrated packaging structure as shown in Figure 14. It can be seen that the shielding layer 4 is in contact with the first conductive pillar 15 through the exposed surfaces S1 and S2 of the first conductive pillar 15 .
  • a second cutting is performed on the integrated packaging structure as shown in Figure 14.
  • the second cutting lane since the symmetry axis of the two side edges of the first cutting lane is the same as the symmetry axis of the two side edges of the second cutting lane, and the width W1 of the first cutting lane is greater than the width W2 of the second cutting lane, therefore the second cutting lane
  • the sub-cutting can ensure that the surface S1 will not be lost, and can completely separate multiple single-piece packaging structures to obtain multiple chip packaging structures 600 as shown in FIG. 15 .
  • the above-mentioned surface S1 and surface S2 form a "step-shaped" notch.
  • the surface S1 and the surface S2 here are respectively the first contact surface and the second contact surface.
  • the shielding layer 4 is formed on the upper surface of the plastic encapsulation layer 3, the first contact surface (S1) and the substrate 1 between the first contact surface (S1) and the top surface of the substrate. and is connected to the first conductive pillar 15 through the first contact surface (S1) and the second contact surface (S2).
  • the metal layer penetrated by the first conductive pillar 15 is connected to the bottom surface of the substrate through the second conductive pillar 16
  • the ground circuit in the metal layer on the bottom surface of the substrate 1 is connected to the ground circuit in the motherboard 400 . In this way, an electromagnetic shielding cavity as shown by the black dotted line in Figure 15 is formed.
  • two cutting operations can be performed by wire cutting, saw blade cutting or laser cutting; the shielding layer can be formed through film forming processes such as sputtering, electroplating, spraying, etc.
  • the electromagnetic shielding material can be selected such as resin, dilution Composite materials composed of agents, additives and conductive fillers.
  • the first conductive pillar 15 can be exposed to the above-mentioned
  • the first contact surface ensures that the shielding layer can be connected to the first conductive pillar through the first contact surface, and then connected to the metal layer on the bottom of the substrate through the first conductive pillar to achieve grounding. That is, the above-mentioned manufacturing process can eliminate the above-mentioned "defect 2".
  • the first conductive pillar can be exposed to the first contact surface (S1). Since the shielding layer deposited on the first contact surface is thicker when the shielding layer is formed by sputtering, the contact reliability between the shielding layer and the first conductive pillar can be higher and the resistance lower, resulting in better shielding effect and reliability. Better. That is to say, compared with the contact between the shielding layer and the side surface facing the outside of the substrate, the contact between the shielding layer and the first contact surface (S1) facing the top surface of the substrate is better, that is, the contact between the two is less likely to occur.
  • a "step-shaped" gap can also be formed on the first conductive pillar 15, so that the shielding layer can also be formed on the "step-shaped” gap.
  • the other surface of the step-shaped notch that is, the second contact surface, allows the shielding layer to contact both surfaces of the first conductive pillar. It is easy to understand that a connection achieved by contact on two surfaces is more effective than a connection achieved by contact on one surface. That is, the above-mentioned manufacturing process can eliminate the above-mentioned "defect four".
  • the shielding layer 4 Since the cutting process is carried out in two times, and the shielding layer 4 is formed before the second cutting, that is, the shielding layer 4 is formed while multiple single-piece packaging structures are still connected together.
  • the substrate 1 The metal layer and solder balls 11 on the bottom surface will not be exposed to the process environment, so the electromagnetic shielding material will not be sputtered/sprayed onto the metal layer and solder balls 11 on the bottom surface of the substrate 1 . That is to say, the above-mentioned manufacturing process can eliminate the above-mentioned "defect five".
  • the shielding layer is formed only on the outer surface of the plastic encapsulation layer 3, the first contact surface (S1), and the side area of the substrate between the first contact surface and the top surface.
  • most of the outer surface of the substrate is not covered by the shielding layer, thereby reducing the risk of the shielding layer being detached due to collision and thus reducing the shielding performance. That is to say, the above-mentioned manufacturing process can eliminate the above-mentioned "defect six".
  • the first metal-like layer and the first conductive pillar 15 are located on the side of the core plate 141 close to the chip 2
  • the second metal-like layer and the second conductive pillar 16 are located on the core plate 141 .
  • the first metal layer and the first conductive pillars 15 are located on the upper part of the substrate, while the second metal layer and the second conductive pillars 16 are located on the lower part of the substrate.
  • the side area of the substrate 1 that the shielding layer 4 needs to cover can be reduced, thereby reducing the possibility that the shielding layer 4 will fall off due to poor bonding reliability between the shielding layer 4 and the substrate 1 , that is, the reliability of the electromagnetic shielding cover can be enhanced. sex.
  • the shielding layer 4 needs to cover the corresponding side area of the upper part of the substrate 1 and the side area of the core board 141 in order to extend to the first The first contact surface of the conductive pillar 15 is exposed. And if the first metal layer and the first conductive pillar 15 are located on the upper part of the substrate 1, the shielding layer 4 does not need to cover the above-mentioned side area, so the side area of the substrate 1 that the shielding layer 4 needs to cover can be reduced.
  • chip packaging structures with different structures will be obtained.
  • chip packaging structures 600 of the present application will be described below with reference to the integrated packaging structures shown in FIGS. 8 and 9 respectively.
  • FIG. 16 shows a schematic diagram of the cutting path when the integrated packaging structure shown in FIG. 8 is processed using the above manufacturing method.
  • FIG. 17 shows a schematic structural diagram of the integrated packaging structure after the first cutting and after the shielding layer 4 is formed thereon.
  • Figure 18 shows the chip packaging structure 600 obtained after the second cutting of the integrated packaging structure.
  • the shielding layer 4 is connected to the first conductive pillar 15 through the "step-shaped" gap exposed by the first conductive pillar 15, and the metal layer penetrated by the first conductive pillar 15 passes through the first conductive pillar 15.
  • the two conductive pillars 16 are connected to the metal layer on the bottom surface of the substrate, and the ground circuit in the metal layer on the bottom surface of the substrate is connected to the ground circuit in the motherboard 400 .
  • an electromagnetic shielding cavity as shown by the black dotted line in Figure 18 is formed. Chips and other electronic devices are installed in the electromagnetic shielding cavity.
  • each metal layer extends outward to the surrounding edges of the substrate, and the metal layers penetrated by the first conductive pillars 15 located on different sides of the substrate The number of layers varies.
  • Figure 19 shows a schematic diagram of a cutting path when the integrated packaging structure shown in Figure 9 is processed using the above manufacturing method.
  • Figure 20 shows the junction after the first cutting of the integrated packaging structure and the formation of the shielding layer 4 on it. Structure diagram.
  • FIG. 21 shows the chip packaging structure 600 obtained after the second cutting of the integrated packaging structure. As shown in FIG. 21 , each metal layer in the chip packaging structure 600 does not extend to the surrounding edges of the substrate.
  • the offset of the cutting blade means the offset of the cutting track, and/or the position of the edge of the cutting track changes.
  • the offset of the cutting knife (including offset to the left, hereinafter referred to as left shift, and offset to the right, hereinafter referred to as right shift), directly produces The impact is that the first cutting track does not intersect with the first conductive pillar, or the edge of the first cutting track does not intersect with the area where the cross-section of the first conductive pillar is located.
  • first conductive pillar is not cut at all, so that after the cutting is completed, the first conductive pillar does not expose any surface.
  • the second is to cut the first conductive pillar so that its complete end surface is exposed, but the "right-angle" gap introduced above is not formed, and the "step-shaped" gap will not be formed after the second cutting. .
  • the plurality of first conductive pillars located on the same side of the substrate may not be completely located on the same straight line, or in other words, these first conductive pillars may not be completely located on the same straight line.
  • the pillars can be arranged staggered relative to a certain straight line, and the distance between each first conductive pillar and the straight line is less than a certain distance threshold. That is to say, these first conductive pillars are distributed in a specified area. Then, even if the cutting tool deviates within this area, it is guaranteed to cut a part of the first conductive pillar.
  • Figure 23 is a schematic diagram of the distribution of the first conductive pillars in an integrated packaging structure according to an embodiment of the present application.
  • a plurality of first conductive pillars 15 located on the same side of the substrate 1 are distributed in an array and are spaced apart from each other, and are all located on the same straight line.
  • multiple first conductive pillars 15 located on the same side of the substrate 1 are staggered with respect to the same straight line, and the distance between each first conductive pillar 15 and the straight line is less than a certain distance. threshold.
  • Figure 24 shows a flow chart of a method for manufacturing a chip packaging structure provided by an embodiment of the present application. As shown in Figure 24, the method may include the following steps:
  • the integrated substrate includes a plurality of groups of first conductive pillars and a plurality of stacked metal layers.
  • the first conductive pillars penetrate at least two metal layers.
  • the top surface of the integrated substrate includes a plurality of groups of first conductive pillars.
  • a plurality of chip mounting areas are surrounded by mapping positions of a conductive pillar on the top surface.
  • the integrated substrate here is the substrate of the above-mentioned integrated packaging structure.
  • the integrated substrate includes four groups of first conductive pillars. The mapped positions of each group of first conductive pillars on the top surface of the integrated substrate form a rectangular area, which is the chip mounting area.
  • an insulating material is first used to prepare the core board 141 as shown in FIG. 7B. Then, a plurality of first metal layers are formed on one side of the core board 141, and a plurality of sets of first conductive pillars penetrating through at least two first metal layers are formed. The plurality of first metal layers are formed on the top surface of the integrated substrate. Stacked in the vertical direction and separated by the first insulating layer. As can be seen from FIG. 7B , in this example, a first metal layer L3 is formed on one side surface of the core plate 141 , and a first insulating layer is formed on a side surface of the first metal layer L3 away from the core plate 141 .
  • first metal layer L2 is formed on the side surface of the first insulating layer away from the first metal layer L3, and at the same time, four groups of first conductive pillars 15 are formed, each of which first conductive pillars 15 penetrate L2 and L3.
  • the mapping positions of each group of first conductive pillars 15 on the top surface of the integrated substrate form a chip mounting area, thereby forming four chip mounting areas.
  • each group of first conductive pillars 15 is divided into multiple parts, and the mapping positions of the first conductive pillars of each part on the top surface of the integrated substrate are respectively located on each side of the chip mounting area; wherein, the first part of the first conductive pillars The mapping positions of the columns on the top surface are distributed on a certain straight line or the distance from a certain straight line is within a preset distance range, and the first part is any one of the so-called multiple parts.
  • each group of first conductive pillars is divided into four parts.
  • the mapping positions of the first conductive pillars of the four parts on the top surface of the integrated substrate form the four sides of the rectangular chip mounting area. .
  • Each part of the first conductive pillars is strictly distributed along a straight line or staggered along a straight line.
  • each set of second metal layers is on the top surface of the substrate. Stacked in the vertical direction and separated by a second insulating layer; multiple second metal layers in the same group of second metal layers are respectively formed in multiple preset areas on the same surface, and the third metal layer in any preset area
  • the distance between the edges of the two metal layers and the edge of the preset area is the above-mentioned D2; the second insulating layer has a protrusion extending along the vertical direction of the surface, and the protrusions are between the second metal layers on the same surface.
  • the surface here includes the other side surface of the core board and the surface of the second insulating layer away from the core board, that is, the surface used to form the second metal layer.
  • the multiple preset areas on the surface are respectively for each group.
  • three groups of second metal layers are stacked in the vertical direction on the top surface of the substrate.
  • the first group of second metal layers is formed on the other side surface of the core plate 141
  • the second group of second metal layers is formed on the other side surface of the core plate 141 .
  • the metal layer is formed on the side surface of the second insulating layer away from the core plate 141
  • the third group of second metal layers is formed on the side surface of the second insulating layer away from the core plate 141 .
  • the second insulating layer has a protrusion by which respective second metal layers of the first, second and third sets of second metal layers are spaced apart.
  • the above S101 also includes: forming multiple groups of second conductive pillars. As shown in FIG. 7B , each of the plurality of sets of second conductive pillars penetrates a plurality of second metal layers, and connects at least one first metal layer penetrated by the first conductive pillars and the metal layer located on the bottom surface of the substrate.
  • the mapping positions of the same group of second conductive pillars on the above-mentioned surface are located in the same preset area.
  • the distance between the mapping position of the second conductive pillar in a certain preset area and the edge of the preset area is the above-mentioned D1.
  • each group of chips includes two chips 2 , and each chip 2 is electrically connected to the metal layer on the top surface of the integrated substrate.
  • S103 Use plastic packaging material to form a plastic packaging material layer on the top surface of the integrated substrate, so that the chip is wrapped by the plastic packaging material to obtain an integrated packaging structure.
  • the plastic encapsulating material layer 3 is formed on the top surface of the integrated substrate through the above S103.
  • the integrated packaging structure involved in the embodiment of the present application can be manufactured by S101, S102 and S103.
  • any integrated packaging structure shown in FIGS. 7A to 9 can be manufactured. That is to say, the multiple integrated substrates included in any integrated packaging structure can specifically be the integrated substrates produced in S101.
  • the integrated substrates are disposed on the top surface of each substrate. The chips may specifically be chips installed in each chip installation area through S102.
  • S101, S102 and S103 can be used as the pre-steps of "obtaining the integrated packaging structure" in the manufacturing method provided in the above embodiment, that is, the process steps that need to be performed before “obtaining the integrated packaging structure” ; It can also be used as a refinement step of "obtaining an integrated packaging structure", that is, the specific implementation process of "obtaining an integrated packaging structure” mentioned above includes S101, S102 and S103.
  • embodiments of the present application also provide a method for manufacturing an integrated packaging structure.
  • the manufacturing method of the integrated packaging structure includes the above-mentioned S101, S102, and S103. That is to say, in some embodiments, the above-mentioned S101, S102 and S103 may constitute a method for manufacturing an integrated packaging structure, and are not limited to the following S104, S105 and S106 together to constitute a method provided by the embodiments of the present application. Method for manufacturing chip packaging structure.
  • S106 Cut the integrated packaging structure for a second time to separate multiple chip packaging structures.
  • the shielding layer on each chip packaging structure is connected to the first conductive pillar through the first contact surface.
  • the first conductive pillar is used to connect the shield layer is grounded.

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Abstract

本申请实施例提供一种芯片封装结构及其制作方法，涉及芯片封装技术领域。主要目的在于提供一种具有可靠的电磁自屏蔽功能的芯片封装结构，包括基板、芯片和屏蔽层。其中，基板包括层叠设置的多个金属层，第一导电柱贯穿至少两个金属层，且具有暴露于基板外侧且朝向基板顶面的第一接触面；芯片设置在基板顶面上；屏蔽层形成在芯片外，且通过第一接触面与第一导电柱连接，该屏蔽层接地。该芯片封装结构中，屏蔽层通过与第一接触面接触而连接于第一导电柱并接地，从而形成电磁屏蔽腔。由于屏蔽层与第一接触面之间接触较好，因此形成的电磁屏蔽腔具有更高的可靠性。

Description

芯片封装结构及其制作方法
本申请要求于2022年07月30日提交国家知识产权局、申请号为202210911481.6、申请名称为“芯片封装结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片封装技术领域，尤其涉及一种芯片封装结构及其制作方法。
背景技术
随着半导体产品系统化、微小化的不断发展，在有限的体积内需要集成的电子器件越来越多。系统级封装结构(system in package，SIP)，即是将多个具有不同功能的有源电子器件、无源电子器件以及诸如微机电系统(micro-electro-mechanical system，MEMS)或者光学等器件组装到一起，得到的单个标准芯片封装结构。
由于SIP内部有可能存在电磁敏感器件或者电磁干扰源，因此需要在SIP上实现自屏蔽，从而保护SIP内部的电磁敏感器件受干扰程度大幅降低，以及降低SIP内部干扰源干扰SIP外部的电子器件。
相关技术一般通过在SIP的电子器件和互联电路外部形成电磁干扰(electromagnetic interference，EMI)屏蔽，来抑制SIP内电子器件的对外干扰，以及降低SIP外的干扰源对SIP内电子器件的干扰。然而，其形成屏蔽的各个部分(不同部分的金属物)的接触效果可靠性不良，从而在长期使用中影响屏蔽效果。
发明内容
本申请实施例提供一种芯片封装结构及其制作方法、电子设备，主要目的在于提供一种具有可靠且优越的电磁自屏蔽功能的芯片封装结构，以及该芯片封装结构的制作方法，当该芯片封装结构被应用于电子设备时，其电子器件能够有效地降低电磁干扰，也可以降低电子设备对其他电子器件的干扰。
第一方面，本申请实施例提供一种芯片封装结构，该芯片封装结构可以为标准SIP产品，也可以是其他类型的芯片封装产品。该芯片封装结构包括基板、芯片和屏蔽层，基板包括层叠设置的多个金属层；第一导电柱贯穿至少两个金属层，且第一导电柱具有暴露于基板外侧的接触面，该接触面包括朝向基板顶面的第一接触面；芯片设置在基板顶面上，且与基板顶面上的金属层连接；屏蔽层形成在芯片外，且通过第一接触面与第一导电柱连接，该屏蔽层接地。该芯片封装结构中，屏蔽层通过第一接触面连接第一导电柱，且接地，进而形成了电磁屏蔽腔。芯片贴片在该电磁屏蔽腔内，进而，可以屏蔽芯片产生的电磁辐射，以及屏蔽外部的电磁波，从而降低对芯片的干扰。
其中，基于屏蔽层的形成工艺，比如溅射工艺，由于第一接触面朝向基板顶面，因此在第一接触面上形成的屏蔽层更厚，使得屏蔽层与第一导电柱的的接触效果更好，电阻更低，不易发生断触，进而不易发生电磁泄露。
在第一方面的一种可能的实现方式中，屏蔽层通过第一导电柱贯穿的至少两个金属层中的一个接地。
在第一方面的一种可能的实现方式中，第一导电柱贯穿的至少一个金属层与基板底面上的金属层连接，底面上的金属层用于接地。由于基板底面的金属层包括接地电路，因此屏蔽层便可通过该接地电路接地。比如，基板底面的接地电路通过连接电子设备中主板上的地信号接地。
需要说明的是，上述基板底面上的金属层及基板顶面上的金属层包括互联线路，具体可以为金属布线层。
在第一方面的一种可能的实现方式中，上述接触面还包括朝向基板外侧的第二接触面，该第二接触面与该第一接触面形成缺口；屏蔽层通过第一接触面和第二接触面与第一导电柱连接。首先，由于在溅射形成屏蔽层时，第一接触面上沉积的屏蔽层更厚，因此可以使得屏蔽层与第一导电柱的接触可靠性更高，电阻更低，从而屏蔽效果更优、可靠性更佳。其次，屏蔽层还会被沉积在第二接触面上，即与第一导电柱的两个表面接触，因此可以进一步优化二者的接触效果。从而， 可以进一步降低因二者之间接触不良而导致电磁泄漏的可能性。
在第一方面的一种可能的实现方式中，该芯片封装结构还包括形成于基板顶面上的塑封料层，芯片包裹于塑封料层；上述屏蔽层覆盖于塑封料层的外表面、第一接触面，及基板的位于第一接触面至基板顶面之间的侧面区域上。也就是说，屏蔽层并未覆盖基板的所有侧面区域。由于屏蔽层所采用的电磁屏蔽材料与基板材料的结合在碰撞时可靠性通常较差，因此仅在塑封料层的外表面、第一接触面，及基板的位于第一接触面至基板顶面之间的侧面区域上形成屏蔽层，相对于在基板的所有侧面区域形成屏蔽层而言，基板的大部分外侧表面未被屏蔽层覆盖，从而降低因碰撞导致屏蔽层脱离而使得屏蔽性能降低的风险。
在第一方面的一种可能的实现方式中，第一导电柱贯穿的金属层均位于基板的内部；第一导电柱贯穿的至少一个金属层通过第二导电柱连接基板底面的金属层；并且，在平行于基板顶面的方向上，第二导电柱与第一导电柱远离基板外侧的一侧的距离大于第一距离。也就是说，第二导电柱包裹于基板的绝缘材料，或者说，第二导电柱位于基板内部。容易理解的是，当第一导电柱贯穿基板底面的金属层时，可直接通过该金属层接地。本实现方式主要目的是提供当第一导电柱贯穿的金属层均位于基板内部时的接地方式，具体而言，屏蔽层通过第一导电柱所贯穿的金属层连接第二导电柱，再通过第二导电柱贯穿基板底面上的金属层，以通过基板底面上的金属层连接电子设备中主板(PCB)上的地。另外值得注意的是，在这种实现方式中，第二导电柱作为形成全封闭电磁屏蔽腔的一部分，由于其位于基板内部，意味着无需在基板所有侧面区域形成屏蔽层，进而降低因屏蔽层与基板之间的结合可靠性差而导致屏蔽层脱落的可能性，也即增强该电磁屏蔽功能的可靠性。在第一方面的一种可能的实现方式中，不同金属层之间通过由绝缘材料构成的绝缘层间隔。绝缘材料具体可以为聚丙烯、陶瓷等基板板材材料。
在第一方面的一种可能的实现方式中，多个金属层还包括连续设置的多个第一金属层和至少一个第二金属层，这里，第一金属层与第二金属层的区别在于：在平行于基板顶面的方向上，第一金属层的边缘延伸至基板的外侧边缘，而第二金属层的边缘与第一导电柱远离基板外侧的一侧的距离大于第二距离，第二距离小于第一距离。其中，第一导电柱贯穿至少两个第一金属层。或者可以这样理解，第二金属层的四周边缘均未暴露于基板外侧，而是通过基板的绝缘材料与外界隔离，且未被第一导电柱所贯穿。由于本申请所提供的芯片封装结构是从多个一体成型的封装结构中切分出来的，而芯片封装结构的侧面即为切割时形成的切割面，因此在这种实现方式中，第二金属层的四周边缘均未暴露于基板外侧，意味着切割时并未切割到第二金属层。而由于切割到的金属层越多，对切割刀造成的磨损越大，因此这种实现方式可以节省成本。
在第一方面的一种可能的实现方式中，第二金属层的数量为多个，且至少两个第二金属层连续设置，第二导电柱贯穿连续的至少两个第二金属层。在本实现方式中，第二导电柱的作用有二，其一是用于连接第一导电柱所贯穿的金属层之一和基板底面的金属层；其二是用于实现其贯穿的多个第二金属层之间的电气互联。或者可以这样理解，本申请实施例对基板中的第二导电柱进行复用，在其实现原有的电气互联作用的基础上，将其用于实现屏蔽层的接地，或者说，将其作为形成电磁屏蔽腔的一部分。
在第一方面可能的实现方式中，绝缘层包括芯板；第一导电柱位于芯板的靠近芯片的一侧，第二金属层位于芯板的远离芯片的一侧。也就是说，芯板将基板划分为上下两部分，第一导电柱位于基板的上部。这种实现方式是为了尽可能地降低屏蔽层需要覆盖的基板侧面区域，进而降低因屏蔽层与基板之间的结合可靠性差而导致屏蔽层脱落的可能性，也即增强该电磁屏蔽腔的可靠性。
具体来说，假设第一导电柱位于基板的下部，那么意味着屏蔽层需要覆盖基板上部对应的侧面区域以及覆盖芯板的侧面区域，才能延伸到第一导电柱暴露的第一接触面。而若第一导电柱位于基板的上部，则屏蔽层无需覆盖上述侧面区域，因此可以降低屏蔽层需要覆盖的基板侧面区域。
在第一方面的一种可能的实现方式中，设置在基板的第一侧的多个第一导电柱，分布于与第一侧的边界线平行的第一直线上；或者，设置在基板的第一侧的多个第一导电柱，与第一直线的距离落在预设距离范围；第一侧为基板的任意一侧。这种实现方式的有益效果，请参见下述第二方面中关于多个第一导电柱的分布类型的技术效果。
第二方面，本申请实施例提供一种芯片封装结构的制作方法。该制作方法中，首先获得待切割的一体化封装结构，其中，一体化封装结构包括一体成型的多个基板和设置在每一基板顶面上的芯片；每一基板包括多个第一导电柱和层叠设置的多个金属层，每一第一导电柱贯穿至少两个金属层。然后对所述一体化封装结构进行第一次切割。第一次切割的目的是使得上述第一导电柱至少暴露出朝向基板顶面的第一接触面。再针对第一次切割后的一体化封装结构，在芯片外形成屏蔽层，并使屏蔽层通过第一接触面与第一导电柱连接。这里形成屏蔽层的目的是为了形成全封闭的电磁屏蔽腔。最后对一体化封装结构进行第二次切割。第二次切割的目的是在不丢失上述第一接触面的基础上，将连接于一体的多个芯片封装结构彻底分割，以获得多个独立的芯片封装结构。
在第二方面的一种可能的实现方式中，上述对一体化封装结构进行第一次切割具体包括：沿第一预设切割道对一体化封装结构进行第一次切割。第一预设切割道与第一导电柱的横截面所在区域相交；第一预设切割道的深度大于基板顶面与第一导电柱的第一端面之间的距离，小于基板顶面与第一导电柱的第二端面之间的距离，第一端面为第一导电柱靠近基板顶面的端面，第二端面为第一导电柱远离基板顶面的端面。这样的话，可以通过第一次切割，使得第一导电柱至少暴露出上述第一接触面。
在第二方面的一种可能的实现方式中，上述对一体化封装结构进行第二次切割具体包括：沿第二预设切割道对一体化封装结构进行第二次切割。其中，位于相邻两个基板之间的第一预设切割道和第二预设切割道，在平行于切割道的边缘的方向上的对称轴相同，即第一预设切割道的两侧边缘的对称轴与第二预设切割道的两侧边缘的对称轴相同，第一预设切割道的宽度大于第二预设切割道的宽度。这样的话，在第二次切割后，不会丢失上述第一接触面，且能够将连接于一体的多个芯片封装结构彻底分割，以获得多个独立的芯片封装结构。
在第二方面的一种可能的实现方式中，第一导电柱暴露出的接触面还包括朝向基板外侧的第二接触面，第二接触面与第一接触面形成缺口；上述针对第一次切割后的一体化封装结构，在芯片外形成屏蔽层，并使屏蔽层通过第一接触面与第一导电柱连接，包括：使屏蔽层通过第一接触面和第二接触面与第一导电柱连接。
在第二方面的一种可能的实现方式中，第一预设切割道的边缘与第一导电柱的横截面区域相交。这里需要说明的是，第一预设切割道与第一导电柱的横截面区域相交的情况可以分为两种，其一是第一预设切割道的边缘与第一导电柱的横截面区域不相交，这种情况可以理解为，第一导电柱被完全包含在第一切割道中。这样的话，可以使得第一导电柱暴露出一个朝向基板顶面的端面。其二是第一预设切割道的边缘与第一导电柱的横截面区域相交，这种情况可以理解为，第一导电柱未被完全包含在第一预设切割道中。这样的话，可以使得第一导电柱暴露出一个朝向基板顶面的表面和一个朝向第一预设切割道的表面，该两个表面相接，形成缺口。
在第二方面的一种可能的实现方式中，第一导电柱贯穿的金属层均位于基板的内部；基板还包括第二导电柱，基板的底面的金属层通过第二导电柱连接第一导电柱贯穿的任意一个金属层。在平行于基板顶面的方向上，第一切割道靠近第二导电柱的一侧的边缘与第二导电柱的距离大于第三距离。
在第二方面的一种可能的实现方式中，基板顶面上设有塑封料层，芯片包裹于塑封料层；针对第一次切割后的一体化封装结构，在芯片外形成屏蔽层，包括：在塑封料层的上表面和第一次切割产生的切割面上形成屏蔽层，切割面包括第一接触面、塑封料层暴露出的外侧面以及基板暴露出的位于第一接触面至基板顶面之间的外侧面。
考虑到实际切割过程中，切割刀会发生偏移，切割刀的偏移意味着切割道的偏移，和/或，切割道边缘的位置发生改变。对于本申请实施例提供的一体化封装结构，第一次切割时，切割刀的偏移，其直接产生的影响便是导致第一预设切割道与第一导电柱不相交，或者导致第一预设切割道的边缘与第一导电柱的横截面所在区域不相交。那么，可能会出现两种情况，其一是，完全没有切割到第一导电柱，从而切割完成后，第一导电柱并未暴露出任何表面。其二是，切割到第一导电柱并使得第一导电柱暴露出其完整端面，但并未形成缺口，进而第二次切割后也不会形成缺口。
所以，为了保证切割刀发生偏移后，实际的第一预设切割道仍然相交于第一导电柱，或者保证第一预设切割道的边缘仍然相交于第一导电柱的横截面所在区域，在第二方面的一种可能的实现方式中，对于一体化封装结构中任意一个基板而言，设置在基板的第一侧的多个第一导电柱，分布于与第一侧的边界线平行的第一直线上；或者，设置在基板的第一侧的多个第一导电柱，与第一直线的距离落在预设距离范围；第一侧为基板的任意一侧。也就是说，一体化封装结构中，对于某个单件封装结构而言，位于其基板的同一侧的多个第一导电柱可以不完全位于同一条直线上，或者说，这些第一导电柱可以相对于某一条直线交错设置，且每个第一导电柱距离这一条直线的距离都小于某个距离阈值，也就是说，这些第一导电柱分布于指定的区域范围。那么，即使切割刀具在该区域范围内偏移，也能保证切割到一部分第一导电柱。
基于上述任意一种制作方法所得到的芯片封装结构的特点及其技术效果，可参见第一方面中不同设计方式所带来的技术效果，此处不再赘述。
第三方面，本申请实施例提供一种芯片封装结构的制作方法，该方法包括：
首先制备一体化基板，应理解的是，这里的一体化基板，即上述第二方面中提及的一体化封装结构的基板，该一体化基板可以切割成多个基板。该一体化基板包括多组第一导电柱和层叠设置的多个金属层，第一导电柱贯穿至少两个金属层，一体化基板顶面包括由各组第一导电柱在一体化基板顶面上的映射位置所围成的多个芯片安装区域；然后在一体化基板顶面上的每一芯片安装区域内安装芯片；再采用塑封材料在一体化基板顶面上形成塑封料层，以使得芯片被塑封材料包裹，得到一体化封装结构；再对一体化封装结构进行第一次切割，以使得每组第一导电柱均暴露出朝向顶面的第一接触面；之后，再在塑封料层的上表面和第一次切割所产生的切割面上形成屏蔽层，切割面包括该第一接触面；最后对一体化封装结构进行第二次切割，以分离出多个芯片封装结构，每个芯片封装结构上的屏蔽层通过第一接触面连接第一导电柱，第一导电柱用于将屏蔽层接地。
在第三方面的一种可能的实现方式中，上述制备一体化基板具体包括：首先采用绝缘材料制备芯板；然后在芯板的一侧，形成多个第一金属层，以及，形成多组贯穿至少两个第一金属层的第一导电柱；该多个第一金属层在基板顶面的垂直方向上层叠，且通过第一绝缘层间隔；以及，在芯板的另一侧，形成多组第二金属层；其中，各组第二金属层在基板顶面的垂直方向上层叠，且通过第二绝缘层间隔；同一组第二金属层中的多个第二金属层，分别形成于同一表面上的多个预设区域内，任意预设区域内的第二金属层的边缘与该预设区域的边缘的距离大于第四距离；第二绝缘层具有沿表面的垂直方向延伸出的凸出部，同一表面上的第二金属层之间通过凸出部间隔；这里的表面，包括芯板的另一侧表面及第二绝缘层远离芯板的表面，也就是用于形成第二金属层的表面，表面上的多个预设区域分别为各组第一导电柱在表面上的映射位置围成的区域。
在第三方面的一种可能的实现方式中，一组第一导电柱包括多个部分，各部分第一导电柱在顶面上的映射位置分别位于芯片安装区域的各侧；其中，第一部分第一导电柱在顶面上的映射位置分布于某一条直线或者与某一条直线的距离络在预设距离范围内，第一部分为所谓多个部分中的任意一个。
在第三方面的一种可能的实现方式中，上述制备一体化基板还包括：形成多组第二导电柱，同一组第二导电柱在上述表面(即形成有一组第二金属层的表面)上的映射位置位于同一个预设区域内；其中，第二导电柱贯穿多个第二金属层，且连接第一导电柱贯穿的至少一个第一金属层和位于基板的底面的金属层。
在第三方面的一种可能的实现方式中，第二导电柱在某个预设区域中的映射位置与该预设区域的边缘的距离大于第五距离。
第四方面，本申请实施例提供了一种电子设备，包括主板、以及上述实施例所述的芯片封装结构。主板位于芯片封装结构中基板远离芯片的一侧表面、且与芯片封装结构连接。由于本申请实施例的电子设备中的芯片封装结构与上述实施例中所述的芯片封装结构相同，所以，两者能够解决相同的技术问题，并获得相同的技术效果，此处不再赘述。
其中，第二方面至第四方面中任一种设计方式所带来的技术效果可参见第一方面中不同设计方式所带来的技术效果，此处不再赘述。
附图说明
图1为本申请实施例中电子设备的结构示意图；
图2为本申请实施例电子设备的爆炸图；
图3为本申请实施例电子设备中主板组件的结构示意图；
图4为本申请实施例电子设备中芯片封装结构的结构示意图；
图5A为相关技术中一体化封装结构的顶面示意图；
图5B为图5A所示一体化封装结构基于切割方向和截面线M1-N1的断面图；
图6为相关技术中芯片封装结构示意图；
图7A为本申请实施例中的一种一体化封装结构的顶面示意图；
图7B为图7A所示一体化封装结构基于切割方向和截面线M2-N2的断面图；
图8为本申请实施例中的另一种一体化封装结构的断面图；
图9为本申请实施例中的又一种一体化封装结构的断面图；
图10为本申请实施例中的一种金属层为金属布线层时示意图；
图11A和图11B为结合7A和图7B示出的，本申请实施例芯片封装结构的制作方法中切割道示意图；
图12为采用本申请实施例封装结构的制作方法对图7A和图7B所示一体化封装结构进行第一次切割后得到的一体化封装结构示意图；
图13为第一次切割后第一导电柱暴露出的表面的示意图；
图14为采用本申请实施例封装结构的制作方法在图13所示一体化封装结构上形成屏蔽层后得到的一体化封装结构示意图；
图15为采用本申请实施例封装结构的制作方法对图14所示一体化封装结构进行第二次切割后得到的芯片封装结构示意图；
图16为采用本申请实施例封装结构的制作方法对图8所示一体化封装结构进行第一次切割后得到的一体化封装结构示意图；
图17为采用本申请实施例封装结构的制作方法在图16所示一体化封装结构上形成屏蔽层后得到的一体化封装结构示意图；
图18为采用本申请实施例封装结构的制作方法对图17所示一体化封装结构进行第二次切割后得到的芯片封装结构示意图；
图19为采用本申请实施例封装结构的制作方法对图9所示一体化封装结构进行第一次切割后得到的一体化封装结构示意图；
图20为采用本申请实施例封装结构的制作方法在图19所示一体化封装结构上形成屏蔽层后得到的一体化封装结构示意图；
图21为采用本申请实施例封装结构的制作方法对图20所示一体化封装结构进行第二次切割后得到的芯片封装结构示意图；
图22为本申请实施例中切割刀偏移的切割场景示意图；
图23为本申请实施例中第一导电柱的分布方式示意图；
图24为本申请实施例中示出的一种芯片封装结构的制作方法流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅出于描述目的对功能和作用基本相同的相同项或相似项进行区分，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。
并且，在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。
此外，本申请中，“上”、“下”、“左”、“右”、“水平”、“顶面”、“顶部”、“底面”、“底部”、“侧面”以及“竖直”、“外部”、“外侧”、“内部”等方位术语是相对于附图中的部件示意置放的方位来定义的。应当理解到，这些方向性术语是相对的概念，它们用于 相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
需要特别指出的是，本申请的大部分描述均涉及到基板，为便于说明，不妨将基板的用于设置芯片的一面称为其“顶面”，将基板的与其“顶面”相对的一面，即其用于与电子设备主板连接的一面称为“底面”，基板的其余表面则为其“侧面”。为了帮助理解和说明，本申请的部分附图中建立了空间直角坐标系。其中，本申请实施例中涉及的某个“顶面”和“底面”可以被描述附图中示出的平行于X-Y面的面，某个“侧面”则为垂直于X-Y面的面，如平行于X-Y面的面，或者平行于X-Y面的面。
除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是机械连接，机械连接可以是固定连接，也可以是可拆卸连接，或成一体；也可以是电性连接，还可以是通信连接。可以是直接相连，也可以通过中间媒介间接相连。
同时，在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念，便于理解。
SIP在涉及计算机工业、通讯网络、消费电子、航天工业、汽车工业等信息通信技术(information and communication technologies，ICT)技术领域中具有较大的应用。
本申请实施例的主要目的是提供一种芯片封装结构，以及制作这种芯片封装结构的方法(以下简称制作方法)。该芯片封装结构可以是标准的SIP产品，或者称为SIP标准件。该芯片封装结构可以集成于电子设备中，以实现电子设备的多种功能。
也就是说，本申请实施例还提供一种包含该芯片封装结构的电子设备，该电子设备可以为ICT技术领域中的电子设备，如服务器、光通信设备、手机、平板电脑(tablet personal computer)、膝上型电脑(laptop computer)、个人数码助理(personal digital assistant，PDA)、照相机、个人计算机、笔记本电脑、车载设备、可穿戴设备、增强现实(augmented reality，AR)眼镜、AR头盔、虚拟现实(virtual reality，VR)眼镜或者VR头盔等需要进行数据处理/存储/收发的设备。本申请实施例对上述电子设备的具体形式不做特殊限制。以下为了方便说明，均是以该电子设备为如图1所示的手机为例进行的举例说明。
图1为本申请一些实施例提供的电子设备的立体图，图2为图1所示电子设备的爆炸图。请参照图1和图2，电子设备1000为手机。电子设备1000可以包括如图1所示的屏幕100、中框200、后壳300及固定在中框200上的主板400。
可以理解的是，图1和图2仅示例性的示出了电子设备1000包括的一些部件，这些部件的实际形状、实际大小、实际位置和实际构造不受图1和图2的限制。例如，在其他一些示例中，电子设备1000也可以不包括屏幕100。或者，电子设备1000还可以包括如图2所示的摄像头500。
本申请实施例中，电子设备1000还包括如图3所示的芯片封装结构600。该芯片封装结构600设置于该主板400上、且与主板400连接。例如，芯片封装结构600可以通过焊球阵列(ball grid array，BGA)、或者多个阵列排布的铜柱凸块(copper pillar bump，CPB)与主板400连接，从而使得芯片封装结构600能够与主板400上其他器件或者器件堆叠结构实现信号传输。
需要说明的是，上述主板400可以为印刷电路板(printed circuit board，PCB)。主板400上的芯片封装结构600的数量可以为一个、两个或两个以上，本申请不予限制。
为了方便下文描述，本申请实施例的部分附图中示出了三维空间坐标系，即X、Y、Z坐标系。参照图3，主板400所在平面为XY平面。以图3中示出的主板400为长方形为例，X轴可以为主板400的长度方向，同时也可以为左右方向，Y轴可以为主板400的宽度方向，Z轴为垂直于或在制作公差范围内近似垂直于主板400的方向。继续以图3中示出的主板400为例，主板400的沿Z轴的两个表面可以分别为主板400的底面和顶面，主板400的沿X轴的两个表面及其沿Y轴的两个表面可以为主板400的四个侧面。芯片封装结构600设置在主板400的顶面上。
上述是以主板400为长方体为例进行的说明，主板400还可以为正方形、多边形等形状，本申请实施例对主板400的形状不做限定。
以下对上述芯片封装结构600的结构进行说明。请参照图4，芯片封装结构600可以包括基板(substrate，SUB)1、设置在基板1上的芯片2以及包裹芯片2的塑封料层(molding)3。这里的塑封料层3还可以称为塑封结构。该基板1应用于芯片封装工艺中时，用于承载芯片或者芯片堆叠结构，以形成芯片封装结构600。基板1的顶面、底面及内部具有高密度互联线路，用于实现不同的芯片2之间，或者芯片2与主板400之间的连接。该互联线路可以为金属层，如铜层、图案化互联线路/电路结构，还可以为布线层和/或重布线层。在图4所示示例中，基板1的沿Z轴方向的两个表面分别为其底面和顶面，芯片2设置在基板1的顶面上。基板1的底面上设有焊球阵列11，用于实现基板中互联线路与主板400之间的连接。芯片封装结构600中芯片2的数量可以为一个，也可以为多个，本申请不予限定。
上述芯片2可以为具有数据处理功能的处理芯片，例如为中央处理器(central processing unit，CPU)、片上系统(system on chip，SOC)或者图像处理器(graphics processing unit，GPU)等能够对数据进行处理的芯片。上述存储器可以为随机存取记忆体(random access memory，RAM)，也可以为只读存储器(read-only memory，ROM)。
上述芯片可以包括有源电子器件、无源电子器件以及诸如MEMS或者光学器件。例如，二极管(diode)、电阻器(resistor)、电阻排(resistor network)、电容器(capacitor)、电感(inductor)、变压器(transformer)、继电器(relay)、开关(switch)等电路类器件，又如集成运算放大器(operation amplifier)、比较器(comparator)、对数和指数放大器、模拟乘/除法器(multiplier/divider)、模拟开关电路(analog switch)、波形发生器(wave-form generator)、功率放大器(power amplifier)等模拟集成电路器件，又如基本逻辑门(logic gate circuit)、触发器(flip-flop)、寄存器(register)、译码器(decoder)、数据比较器(comparator)、驱动器(driver)、计数器(counter)、整形电路、可编程逻辑器件(pld)、微处理器(microprocessor，MPU)、单片机(microcontroller，MCU)、dsp器件(digital signal processor，DSP)等数字集成电路器件。
由于芯片封装结构600内部有可能存在电磁敏感器件或者电磁干扰源，因此为了保护芯片封装结构600内部的电磁敏感器件不受干扰，以及降低芯片封装结构600内部干扰源对外部电子器件的干扰，相关技术通过在芯片封装结构600外表面形成电磁屏蔽材料膜层(以下简称屏蔽层)，以形成电磁屏蔽腔，将芯片封装结构600中的电子器件都封闭在电磁屏蔽腔内。这样，能够屏蔽芯片封装结构600内部产生的电磁辐射，以及屏蔽外部的电磁波，从而降低对芯片封装结构600内部的电子器件的干扰。通过上述电磁屏蔽腔所实现的电子屏蔽功能即为芯片封装结构600的电磁自屏蔽功能。
一体化封装结构中，通常包括成百上千个一体成型的单件封装结构。相关技术中，芯片封装结构600的制作工艺，通常包括对一体化封装结构进行切割的环节，以将其中的单件封装结构切分出来，然后再针对每个单件封装结构制作屏蔽层，以形成电磁屏蔽腔。
图5A为相关技术中的一种待切割的一体化封装结构顶面(X-Y平面)示意图，图5A为该一体化封装结构顶面基于切割方向和截面线M1-N1的断面图。如图5A和图5B所示，该一体化封装结构包括4个一体成型的单件封装结构，即封装结构510、封装结构520、封装结构530和封装结构540。基于示出的切割线和切割方向，可以将该一体封装结构该四个单件封装结构切分出来。应理解，这里的切割线是指用于指示切割位置或者指示切割道边缘位置的线型标记，而非线型切割刀具。切割道位于相邻两个单件封装结构之间，其可以理解为，采用切割刀具在切割线所指示的位置处进行切割时，所产生的具有一定宽度和深度的通道。其中，切割道的宽度即为切割道在X轴方向上的尺寸，切割道的深度即为切割道在Y轴方向上的尺寸。由于该四个单件封装结构完全相同，因此以封装结构510为例对该一体化封装结构的特点进行说明。可以看出，封装结构510中，基板1包括层叠设置的多个金属层12，该多个金属层12的一个形成于基板1的顶面，一个形成于基板1的底面，其余形成在基板1的内部。除了形成于底面的金属层外，其余金属层12均向外延伸至基板1的四周边缘，或者说，均延伸至切割位置。请继续参阅图5A和图5B，基板1还包括导电柱13，导电柱13贯穿多个金属层12。
应理解的是，多个单件封装结构的基板一体成型，构成一体化基板。这里的一体化基板即为一体化封装结构的基板。
相关技术中，针对上述一体化封装结构，通常先按照图5A和图5B示出的预定的切割位置，自一体化封装结构的顶面向下，一次性地切割至一体化封装结构的底面，以将连接于一体的多个单件封装结构(如封装结构510/520/530/540)彻底分离。再在每个单件封装结构的外部，形成屏蔽层，进而得到如图6所示的具有自屏蔽功能的芯片封装结构。
由图6可以看出，通过切割，使得导电柱13暴露出一个表面，屏蔽层(如图6中虚线所示)通过该表面与导电柱13连接，由于导电柱13连接于基板底面上的接地电路，故可通过基板底面的接电电路连接主板400中的接地电路，最终实现接地，得到全封闭的电磁屏蔽腔。
然而图5A、图5B和图6示出的相关技术示例，具有下述缺陷。
缺陷一：切割线的位置，使得切割线下方具有多个金属层，并且切割时，是由一体化封装结构的顶面切割至一体化封装结构的底面，因此意味着，会切割到基板1内所有的金属层12。容易理解的是，由于金属层的硬度相比于基板材料的硬度更大，因此切割的金属层12越多，切割刀(如锯片)产生的磨损越大，成本较高。
缺陷二：由于实际切割过程中，切割刀(也可以是激光)很有可能会在左/右方向(图5A中X轴方向)上发生偏移，进而导致实际切割的位置，与工艺设计中期望切割的位置相比，稍有误差。一旦切割刀发生偏移，则可能会导致将导电柱13整体切掉，或者完全切不到导电柱13。无论出现哪一种情况，都会导致屏蔽层无法与基板底面的金属层连接，进而无法接地，也就无法实现电磁屏蔽作用。
缺陷三：切割完成后，针对每个单件封装结构，都需要在每个单件封装结构的的侧面上形成屏蔽层，因此需要对多个单件芯片封装结构的位置进行布局(layout)，也就是将多个单件芯片封装结构相互间隔地放置在便于制备屏蔽层的位置处。layout工序增加了整体制作工艺的繁杂程度。
缺陷四：屏蔽层通过与导电柱13暴露出的侧面接触，实现与导电柱13之间的连接。基于屏蔽层的形成工艺，如溅射工艺，由于在侧面上能够形成的屏蔽层较薄，因此使得屏蔽层与导电柱13的接触可靠性较差，且接触电阻，导致屏蔽效果差。
缺陷五：由于一般采用溅射、喷涂和电镀等成膜工艺在芯片封装结构的上表面及侧面上形成屏蔽层，因此很容易将电磁屏蔽材料喷溅到基板1底面的焊球11(或者焊盘)上。为了防止将电磁屏蔽材料喷溅到基板1底面的焊球11上，就要求焊球11与基板1的四周边缘距离足够远，通常为150um，在有些场景下，会需要增大芯片封装尺寸来满足这一要求，这与电子设备对芯片封装结构的微型化的要求相悖。
缺陷六：由于屏蔽层覆盖在基板的最外侧区域，极容易因碰撞/震动等因素影响，而导致屏蔽层发生脱落。
本申请实施例提供一种芯片封装结构及其制作方法，该芯片封装结构及其制作方法的每一种可实现的设计中，至少能够消除上述缺陷中的一个，或者同时消除上述缺陷中的多个。即，本申请实施例提供的芯片封装结构具有可靠的电磁自屏蔽功能。这样，当其被应用于电子设备时，其电子器件能够有效地降低电磁干扰，也可以降低电子设备对其他电子器件的干扰。
需要说明的是，本申请实施例提供的芯片封装结构，是采用本申请提供的制作方法，对本申请提供的一体化封装结构进行处理，所得到的标准的芯片封装结构。以下先行对该一体化封装结构和该制作方法进行介绍，从而便于读者基于制作方法与所得产品之间的因果关系，来理解本申请的发明构思。
首先，对本申请实施例提供的一体化封装结构进行介绍。
图7A为相关技术中的一种待切割的一体化封装结构顶面(X-Y平面)示意图，图7B为该一体化封装结构顶面基于切割方向和截面线M2-N2的断面图。
如图7A和图7B所示，基于示出的切割线和切割方向，可以将该一体封装结构模拟划分为四个单件封装结构，即封装结构710、封装结构720、封装结构730和封装结构740。在该示例中，一体化封装结构包括四个一体成型的单件封装结构，该四个单件封装结构的结构完全相同。而其他示例中，一体化封装结构可以包括更多个一体成型的单件封装结构，不同的单件封装结构之间，结构也可以不同，本申请不予限定。为了便于说明，本申请以下实施例中，在描述任意一种设计 的一体化封装结构时，都将以其中的一个单件封装结构为例进行说明。
以封装结构710为例，其包括基板1(基板1的附图标记在图7B中未示出)和贴装在基板1顶面上的芯片2，芯片2包裹在塑封料层3内。其中，基板1包括多个由绝缘材料(如聚丙烯、陶瓷等基板板材材料)构成的绝缘层14和多个金属层12，该多个金属层12分别为示出的L1、L2、L3、L3、L4、L5和L6。该多个金属层12沿垂直于基板1顶面(基板1底面)的方向(即Z轴方向)层叠设置，相邻两个金属层12之间通过绝缘层14间隔。其中，L1形成于基板1顶面，L2、L3、L3、L4和L5形成于基板1内部，L6形成于基板1底面。
值得注意的是，本申请的一体化封装结构中，任意相邻的两个单件封装结构，如上述的封装结构710与封装结构720，或者上述的封装结构710与封装结构730，其同层设置的金属层12之间可以一体成型，也可以具有间隔。比如，封装结构710中的金属层L2与封装结构120中的金属层L2一体成型，也即二者之间没有间隔；而封装结构710中的金属层L4与封装结构120中的金属层L4之间未一体成型，也即二者之间通过绝缘材料间隔开。
或者可以这样理解，对于如封装结构710这样的单件封装结构来说，其一部分金属层12向外延伸到了切割线和切割方向所指示的切割道。而另一部分金属层12向外延伸至距离切割道边缘D的位置处。这样设计的目的是，保证在切割时，可以免于对所有的金属层12进行切割，譬如只会切割到延伸至切割道的金属层，而不会切割到未延伸出的金属层。同时，还可以保证得到的芯片封装结构中，一部分金属层12仍然包裹于绝缘材料。为便于说明，本申请实施例将延伸至切割道的金属层称为第一类金属层(或称为第一金属层)，将未延伸至切割道的金属层称为第二类金属层(或称为第一金属层)。
请继续参阅图7B中的封装结构710，其基板1内还包括多个第一导电柱15，该多个第一导电柱15分布于基板1的四侧。并且，第一导电柱15贯穿至少两个第一类金属层。在图7B所示示例中，第一导电柱15贯穿金属层L2和L3。当然，第一导电柱15也可以通过其两端连接两个不同的第一类金属层，而不贯穿该两个第一类金属层。此外，图7B所示的封装结构710中，其基板1还包括多个第二导电柱16，第二导电柱16位于第一导电柱15的远离切割位置(切割道)的一侧，且二者轴线之间的距离大于二者的半径之和。也就是说，相对于第一导电柱15而言，第二导电柱16靠近基板内部设置。第一导电柱15所贯穿的多个金属层12中的至少一个，通过第二导电柱16与基板底面的金属层连接。同时，第二导电柱16还贯穿多个第二类金属层。比如，在图7B示出的封装结构710中，第二导电柱16的一端连接于L3，另一端以贯穿L6的形式连接L6。此外，第二导电柱16还同时贯穿L4和L5。
可以看出，在该一体化封装结构中，第二导电柱16的作用有二，其一是用于连接第一导电柱15所贯穿的金属层12之一，和基板1底面的金属层12；其二是用于实现其贯穿的多个第二类金属层之间的电气互联。并且，第二导电柱16的设置位置，可以保证其在切割后仍然包裹于绝缘材料。
上述封装结构710中，在平行于基板顶面的方向上，第二导电柱16与第一导电柱15远离第一切割道的一侧的距离为D1，D1大于零。在平行于基板顶面的方向上，第二金属层的边缘与第一导电柱远离第一切割道的一侧的距离为D2，D2大于零，D1大于D2。在平行于基板顶面的方向上，第一切割道靠近第二导电柱16的一侧的边缘与第二导电柱16的距离为D3，D3大于D1。上述封装结构710中，第一导电柱15和第二导电柱16均为灌注有金属材料的地孔，第一导电柱15通过第二导电柱16连接基板1底面的接地电路，这里的接地电路属于基板底面金属层中的电路。
由上述可知，在图7A和图7B示出的一体化封装结构中，对于其单件封装结构而言，其基板1内部既存在上述第一类金属层，也包括上述第二类金属层。同时，每个第一导电柱15均贯穿相同数量的金属层12，且被其贯穿/连接的金属层12均是上述第一类金属层，并均形成在基板1的内部，进而，其中的一个第一类金属层需通过第二导电柱16连接到基板底面的接地电路。
需要说明的是，在本申请一体化封装结构的另一些设计中，仍然以其中的某个单件封装结构为例，其基板内部的金属层可以包括且仅包括如上述L2和L3这样的第一类金属层，第一导电柱可以贯穿更多的第一类金属层，和/或，位于基板的不同侧的第一导电柱可以贯穿不同数量的第一 类金属层。例如，参阅图8，示出了某种一体化封装结构在切割方向上的断面图。其中，封装结构810和封装结构820中，L1、L3、L3、L4和L5均延伸至切割道，即均属于上述定义的第一类金属层。封装结构810中基板1左侧的第一导电柱15贯穿L2和L3，基板1右侧的第一导电柱15贯穿L1、L2和L3。封装结构820中基板1左侧的第一导电柱15贯穿L1、L2和L3，基板1右侧的第一导电柱15贯穿L2和L3。
在一体化封装结构的又一些设计中，单件封装结构的基板也可以包括且仅包括如上述L4和L5的第二类金属层，第一导电柱贯穿其中的至少两个金属层，且有一个形成于基板底面。例如，参阅图9，示出了某种一体化封装结构在切割方向上的断面图。其中，封装结构910和封装结构920中，L1、L3、L3、L4、L5和L6的边缘均未均延伸至切割道，也即均属于上述定义的第二类金属层。第一导电柱15贯穿L1、L3、L3、L4、L5和L6。
值得注意的是，在图7B示出的一体化封装结构中，多个绝缘层14中的一个为芯板141。第一类金属层和第一导电柱15均形成在芯板141的靠近芯片2的一侧。基板1底面上形成有一个第二类金属层，其余第二类金属层和第二导电柱16均形成在芯板141的远离芯片2的一侧。
容易理解的是，上述图7A至图9示出的一体化封装结构，并不包括本申请实施例所提供的所有可能的一体化封装结构。例如，其还可以包括更多或者更少的金属层，还可以包括数量、作用和/或设置位置不同于上述示例的导电柱。
另外，上述实施例所提及的金属层，可以是完全覆盖绝缘结构的一个表面的金属物膜层，也可以是如图10所示的金属布线层。
接下来结合上述示出的一体化封装结构，对本申请实施例的芯片封装结构的制作方法予以介绍。
首先，获得一体化封装结构，如上述图7A至图9示出的一体化封装结构。
其次，沿第一切割道对一体化封装结构进行第一次切割。第一次切割的目的，是使得上述第一导电柱至少暴露出朝向基板顶面的第一接触面。或者使得上述第一导电柱暴露出朝向基板顶面的第一接触面，和朝向基板侧面的第二接触面，这里的第二接触面与上述第一接触面可形成缺口，如“直角形”缺口。
然后，针对经过第一次切割后的一体化封装结构，在塑封料层的顶面及第一次切割所形成的切割面上形成屏蔽层，并使屏蔽层通过第一导电柱所暴露出的表面(上述第一接触面，或者，上述第一接触面和第二接触面)与第一导电柱连接。应理解的是，第一次切割所形成的切割面包括塑封料层暴露出的外侧面、第一接触面、和基板暴露出的在第一接触面与基板顶面之间的外侧面。这里形成屏蔽层的目的是为了形成电磁屏蔽腔，而屏蔽层及其连接的第一导电柱，均属于形成该电磁屏蔽腔的组成部分。电磁屏蔽腔形成后，单件封装结构中的电子器件都被包裹在该电磁屏蔽腔内，这样，屏蔽层可实现电磁干扰屏蔽的作用。由于第一次切割过程可以保证使得第一导电柱暴露出至少一个表面，即第一接触面，因此在形成屏蔽层时，同样可以保证屏蔽层能够通过该第一接触面与第一导电柱连接。
最后，沿第二切割道对上述步骤得到的一体化封装结构进行第二次切割，得到多个独立的芯片封装结构。第二次切割的目的与第一次切割的目的相同，即都是为了使得第一导电柱至少暴露出上述第一接触面，或者暴露出上述第一接触面和第二接触面。也就是说，第一导电柱暴露出的第一接触面，或者暴露出的第一接触面和第二接触面，是通过第一次切割和第二次切割的工艺配合而形成的。第二次切割的另一目的是，将连接于一体的多个芯片封装结构彻底分割，以获得多个独立的芯片封装结构。
以下结合图7B示出的一体化封装结构，依次对上述切割工艺中的第一次切割、形成屏蔽层以及第二次切割的具体工艺进行介绍。
在一些可能的实现方式中，如图11A和图11B所示，第一切割道代表第一次切割过程的切割道，第二切割道代表第二次切割过程的切割道。可以看出，本申请是通过两次切割操作，将一体化封装结构切割成多个独立的单件封装结构。其中，第一切割道的边缘与第一导电柱15的横截面所在区域相交，第一切割道的宽度W1大于第二切割道的宽度W2，第一切割道的深度H1大于第 一导电柱15的上端面与基板顶面的距离，小于第一导电柱15的下端面与基板顶面的距离。所谓上端面即为第一导电柱15靠近基板顶面的端面，所谓下端面为第一导电柱15远离基板顶面的端面。也就是说，第一切割道与第一导电柱15相交，但第一导电柱并未完全包含在第一切割道中。这样的话，可以使得第一导电柱15暴露出一个朝向基板顶面的表面和一个朝向第一切割道的表面，该两个表面相接，形成“直角形”缺口。此外，第一切割道的两侧边缘的的对称轴与第二切割道的两侧边缘的的对称轴相同，即第一切割道的两侧边缘和第二切割道的两侧边缘是关于同一条直线对称的，并且第一切割道的宽度W1大于第二切割道的宽度W2。
图12示出了沿上述第一切割道对图7B所示一体化封装结构进行第一次切割后得到的一体化封装结构。可以看出，第一导电柱15暴露出朝向基板顶面的表面S1，和朝向基板外侧的表面S2。还需注意的是，第一次切割过程产生的切割面包括：塑封料层3暴露出的外侧面、表面S1、以及基板1暴露出的位于表面S1与基板顶面之间的外侧面，其中，基板1暴露出的外侧面包括表面S2。
需要说明的是，上述第一次切割过程还可以使得第一导电柱15暴露出第三接触面，第一接触面和第二接触面之间可以通过第三接触面连接。应理解的是，基于切割刀具形状的不同，可以产生不同形态的第三接触面，比如，可以从产生如图13中a所示的平面S3，也可以产生如图13中b所示的曲面S3。
在另一些可能的实现方式中，第一切割道与第一导电柱15相交，但第一切割道道的边缘与第一导电柱15的横截面所在区域不相交。也就是说，第一导电柱被完全包含在第一切割道中。这样的话，可以使得第一导电柱暴露出一个朝向基板顶面的端面，具体可以参见图22示出的情况二。
请参阅图14，针对如图12所示的一体化封装结构，在塑封料层3的上表面和第一次切割产生的切割面上形成屏蔽层4，以使得屏蔽层4罩设在芯片2外，且通表面S1和表面S2与第一导电柱15连接，即如图14示出的一体化封装结构。可以看出，屏蔽层4通过第一导电柱15暴露出的表面S1和表面S2与第一导电柱15接触。
接着，针对如图14所示的一体化封装结构进行第二次切割。其中，由于第一切割道的两侧边缘的的对称轴与第二切割道的两侧边缘的的对称轴相同，并且第一切割道的宽度W1大于第二切割道的宽度W2，因此第二次切割可以保证不会丢失该表面S1，且可将多个单件封装结构彻底分离开，得到多个如图15所示的芯片封装结构600。容易理解的是，第二次切割后，上述表面S1与表面S2形成“台阶型”缺口。这里的表面S1与表面S2即分别为上述第一接触面和第二接触面。
如图15所示，本申请实施例提供的芯片封装结构600中，其关于金属层12的位置/延伸方式和数量，以及关于其第一导电柱15和第二导电柱16的数量和位置，均可参照针对图7B中封装结构710的介绍，此处不予赘述。值得强调的是，在该芯片封装结构600中，屏蔽层4形成在塑封料层3的上表面、第一接触面(S1)以及基板1的位于第一接触面(S1)至基板顶面之间的侧面区域，并通过第一接触面(S1)和第二接触面(S2)与第一导电柱15连接，第一导电柱15所贯穿的金属层通过第二导电柱16连接于基板底面的金属层，基板1底面的金属层中的接地电路与主板400中的接地电路连接。这样，便形成了如图15中黑色虚线所示的电磁屏蔽腔。
上述制作过程中，可以采用线切割、锯片切割或者激光切割等方式进行两次切割操作；可以通过溅射、电镀、喷涂等成膜工艺形成屏蔽层，电磁屏蔽材料可以选择如由树脂、稀释剂、添加剂以及导电性填料等所组成的复合材料。
上述制作工艺可以带来如下技术效果：
(1)基于上述一体化封装结构的设计，以及切割线位置的设计，使得切割线的下方仅具有基板的一部分金属层，因此并未切割到基板的所有金属层，进而降低刀具损耗，节省成本。即，上述制作工艺可以消除上述提及的“缺陷一”。
(2)由于切割过程分两次进行，且第一次切割时的切割深度在第一导电柱15的长度范围内，因此即使切割刀发生偏移，也能使得第一导电柱15暴露出上述第一接触面，从而保证屏蔽层一定能够通过第一接触面连接第一导电柱，进而通过第一导电柱连接到基板底面的金属层，实现接地。即，上述制作工艺可以消除上述提及的“缺陷二”。
(3)由于切割过程分两次进行，并且是在第二次切割之前形成屏蔽层4，也即是在多个单件封装结构仍连接于一体的情况下形成屏蔽层4，因此，无需对该多个单件封装结构重新布局。即，上述制作工艺可以消除上述提及的“缺陷三”。
(4)通过两次不同切割宽度的切割操作，以及对第一次切割时切割深度的控制，可以使得第一导电柱暴露出第一接触面(S1)。由于在溅射形成屏蔽层时，第一接触面上沉积的屏蔽层更厚，因此可以使得屏蔽层与第一导电柱的接触可靠性更高，电阻更低，从而屏蔽效果更优、可靠性更佳。也就是说，相对于屏蔽层与朝向基板外侧的侧面接触而言，屏蔽层与朝向基板顶面的第一接触面(S1)的接触更好，也即二者不易发生断触。并且，通过两次不同切割宽度的切割操作，以及对第一次切割时切割深度的控制，还可以在第一导电柱15上形成“台阶型”缺口，这样，屏蔽层还可以形成在该“台阶型”缺口的另一个表面，即第二接触面上，使得屏蔽层可以与第一导电柱的两个表面接触。容易理解的是，相比于通过在一个表面上的接触而实现的连接，通过在两个面上的接触所实现的连接，效果更优。即，上述制作工艺可以消除上述提及的“缺陷四”。
(5)由于切割过程分两次进行，并且是在第二次切割之前形成屏蔽层4，也即是在多个单件封装结构仍连接于一体的情况下形成屏蔽层4，此处基板1底面的金属层及焊球11不会暴露于该工艺环境中，因此电磁屏蔽材料不会被溅射/喷涂到基板1底面的金属层及焊球11上。即，上述制作工艺可以消除上述提及的“缺陷五”。
(6)仅在塑封料层3的外表面、第一接触面(S1)，及基板的位于第一接触面至顶面之间的侧面区域上形成屏蔽层，相对于在基板的所有侧面区域形成屏蔽层而言，基板的大部分外侧表面未被屏蔽层覆盖，从而降低因碰撞导致屏蔽层脱离而使得屏蔽性能降低的风险。即，上述制作工艺可以消除上述提及的“缺陷六”。
另外，在图15所示的芯片封装结构600中，第一类金属层和第一导电柱15位于芯板141的靠近芯片2的一侧，第二类金属层和第二导电柱16位于芯板141的远离芯片2的一侧。也就是说，芯板141将基板1划分为上下两部分，第一类金属层和第一导电柱15位于基板的上部，而第二类金属层和第二导电柱16则位于基板的下部。这样的话，可以降低屏蔽层4需要覆盖的基板1侧面区域，进而降低因屏蔽层4与基板1之间的结合可靠性差而导致屏蔽层4脱落的可能性，也即增强该电磁屏蔽罩的可靠性。
具体来说，假设第一类金属层和第一导电柱15位于基板的下部，那么意味着屏蔽层4需要覆盖基板1上部对应的侧面区域以及覆盖芯板141的侧面区域，才能延伸到第一导电柱15暴露的第一接触面。而若第一类金属层和第一导电柱15位于基板1的上部，则屏蔽层4无需覆盖上述侧面区域，因此可以降低屏蔽层4需要覆盖的基板1侧面区域。
容易理解的是，采用上述实施例提供的制作方法，对不同结构设计的一体化封装结构进行处理后，会得到不同结构的芯片封装结构。以下分别结合图8-图9示出的一体化封装结构，对本申请另外几种可能的芯片封装结构600进行说明。
图16示出了采用上述制作方法对如图8示出的一体化封装结构进行处理时的切割道示意图。其中，有关第一切割道和第二切割道的位置、宽度以及深度的描述，可以参照上述实施例，此处不予赘述。图17示出了对该一体化封装结构进行第一次切割后，以及在其上形成屏蔽层4后的结构示意图。其中，有关屏蔽层4的形成位置及其与第一导电柱15的接触方式的描述，可以参照上述实施例，此处不予赘述。图18出了对该一体化封装结构进行第二次切割后得到的芯片封装结构600。如图18所示，在该芯片封装结构600中，屏蔽层4通过第一导电柱15暴露出的“台阶型”缺口连接第一导电柱15，第一导电柱15所贯穿的金属层通过第二导电柱16连接于基板底面的金属层，基板底面的金属层中的接地电路与主板400中的接地电路连接。这样，便形成了如图18中黑色虚线所示的电磁屏蔽腔。芯片等电子器件均被安装在该电磁屏蔽腔内。与图15所示芯片封装结构600不同的是，在图18中，其中的每一金属层均向外延伸至基板的四周边缘，以及，位于基板不同侧的第一导电柱15所贯穿的金属层数量不同。
图19示出了采用上制作方法对如图9所示的一体化封装结构进行处理时的切割道示意图。其中，有关第一切割道和第二切割道的位置、宽度以及深度的描述，可以参照上述实施例，此处不予赘述。图20示出了对该一体化封装结构进行第一次切割后，以及在其上形成屏蔽层4后的结 构示意图。其中，有关屏蔽层4的形成位置及其与第一导电柱15的接触方式的描述，可以参照上述实施例，此处不予赘述。图21示出了对该一体化封装结构进行第二次切割后得到的芯片封装结构600。如图21所示，该芯片封装结构600中的每一个金属层均未外延伸至基板的四周边缘。
考虑到实际切割过程中，切割刀会发生偏移，进而导致实际的切割道与工艺设计中的切割道相比，稍有误差。如图22所示，容易理解的是，切割刀的偏移意味着切割道的偏移，和/或，切割道边缘的位置发生改变。对于本申请实施例提供的一体化封装结构，第一次切割时，切割刀的偏移(包括向左偏移，以下简称左移，和向右偏移，以下简称右移)，其直接产生的影响便是导致第一切割道与第一导电柱不相交，或者导致第一切割道的边缘与第一导电柱的横截面所在区域不相交。那么，可能会出现如图22示出的两种情况，其一是，完全没有切割到第一导电柱，从而切割完成后，第一导电柱并未暴露出任何表面。其二是，切割到第一导电柱并使得第一导电柱暴露出其完整端面，但并未形成上述介绍的“直角型”缺口，进而第二次切割后也不会形成“台阶型”缺口。
所以，为了保证切割刀发生偏移后，实际的第一切割道仍然相交于第一导电柱，或者保证第一切割道的边缘仍然相交于第一导电柱的横截面所在区域，在本申请的一些实施例中，一体化封装结构中，对于某个单件封装结构而言，位于其基板的同一侧的多个第一导电柱可以不完全位于同一条直线上，或者说，这些第一导电柱可以相对于某一条直线交错设置，且每个第一导电柱距离这一条直线的距离都小于某个距离阈值，也就是说，这些第一导电柱分布于指定的区域范围。那么，即使切割刀具在该区域范围内偏移，也能保证切割到一部分第一导电柱。
图23为本申请实施例给出的一种一体化封装结构中，第一导电柱的分布情况示意图。其中，图23中A示出的分布情况中，位于基板1的同一侧的多个第一导电柱15相互间隔的呈阵列分布，并均位于同一条直线上。图23中B示出的分布情况中，位于基板1的同一侧的多个第一导电柱15相对于同一条直线交错设置，每个第一导电柱15与该直线的距离都小于某个距离阈值。这样的话，即使切割刀发生一定程度的偏移，也能保证切割到第一导电柱，并保证至少一部分第一导电柱暴露出上述“台阶型”缺口。
图24给出了本申请实施例提供的一种芯片封装结构的制作方法流程图，如图24所示，该方法可以包括如下步骤：
S101，制备一体化基板，该一体化基板包括多组第一导电柱和层叠设置的多个金属层，第一导电柱贯穿至少两个金属层，该一体化基板的顶面包括由各组第一导电柱在顶面上的映射位置所围成的多个芯片安装区域。
容易理解的是，这里的一体化基板即为上述一体化封装结构的基板。可以参阅图7A，其中的一体化基板包括4组第一导电柱，每组第一导电柱在一体化基板的顶面上的映射位置围成一个矩形区域，即芯片安装区域。
在制备一体化基板的工艺过程中，首先采用绝缘材料制备如图7B所示的芯板141。然后在芯板141的一侧，形成多个第一金属层，以及，形成多组贯穿至少两个第一金属层的第一导电柱，该多个第一金属层在一体化基板顶面的垂直方向上层叠，且通过第一绝缘层间隔。由图7B可知，在该示例中，在芯板141的一侧表面上形成了一个第一金属层L3，在第一金属层L3远离芯板141的一侧表面上形成了一个第一绝缘层，在第一绝缘层远离第一金属层L3的一侧表面上形成了另一个第一金属层L2，同时，形成了4组第一导电柱15，其中的每一个第一导电柱15都贯穿L2和L3。每一组第一导电柱15在一体化基板顶面上的映射位置围成一个芯片安装区域，进而形成4个芯片安装区域。
并且，每一组第一导电柱15均被划分为多个部分，各部分第一导电柱在一体化基板顶面上的映射位置分别位于芯片安装区域的各侧；其中，第一部分第一导电柱在顶面上的映射位置分布于某一条直线或者与某一条直线的距离络在预设距离范围内，第一部分为所谓多个部分中的任意一个。在图7A所示示例中，每一组第一导电柱都被分为四个部分，该四个部分第一导电柱在一体化基板顶面上的映射位置，形成矩形芯片安装区域的四侧。每一部分第一导电柱都严格地沿一条直线分布或者沿一条直线交错分布。
除此之外，在芯板141的另一侧，形成多组第二金属层；其中，各组第二金属层在基板顶面 的垂直方向上层叠，且通过第二绝缘层间隔；同一组第二金属层中的多个第二金属层，分别形成于同一表面上的多个预设区域内，任意预设区域内的第二金属层的边缘与该预设区域的边缘的距离即为上述D2；第二绝缘层具有沿表面的垂直方向延伸出的凸出部，同一表面上的第二金属层之间通过凸出部间隔；这里的表面，包括芯板的另一侧表面及第二绝缘层远离芯板的表面，也就是用于形成第二金属层的表面，表面上的多个预设区域分别为各组第一导电柱在表面上的映射位置围成的区域。如图7B所述，3组第二金属层在在基板顶面的垂直方向上层叠设置，其中，第一组第二金属层形成在芯板141的另一侧表面上，第二组第二金属层形成在第二绝缘层远离芯板141的一侧表面上，第三组第二金属层形成在第二绝缘层远离芯板141的一侧表面上。第二绝缘层具有凸出部，第一组、第二组和第三组第二金属层中的各个第二金属层通过凸出部间隔。
在一种可能的实现方式中，上述S101还包括：形成多组第二导电柱。如图7B所示，多组第二导电柱中的每一个均贯穿多个第二金属层，且连接第一导电柱贯穿的至少一个第一金属层和位于基板的底面的金属层。同一组第二导电柱在上述表面(即形成有一组第二金属层的表面)上的映射位置位于同一个预设区域内。可选的，第二导电柱在某个预设区域中的映射位置与该预设区域的边缘的距离即为上述D1。
S102，在一体化基板的顶面上的每一芯片安装区域内安装芯片。
仍然可以参阅图7A，4组芯片分别安装在上述4组芯片安装区域内。在图7A示出的例子中，每组芯片包括2个芯片2，每个芯片2均与一体化基板的顶面上的金属层电连接。
S103，采用塑封材料在一体化基板的顶面上形成塑封料层，以使得芯片被塑封材料包裹，得到一体化封装结构。
请参阅图7B，通过上述S103在一体化基板的顶面上形成了塑封料层3。
由S101、S102及S103可制得本申请实施例涉及的一体化封装结构，比如，可以制得图7A至图9示出的任意一种一体化封装结构。也就是说，任意一种一体化封装结构所包括的一体成型的多个基板，具体可以为S101中制得的一体化基板，任意一种一体化封装结构中，设置在每一基板顶面上的芯片，具体可以为通过S102安装在每一芯片安装区域内的芯片。
或者可以这样理解，S101、S102及S103可以作为上述实施例提供的制作方法中，“获得一体化封装结构”的前置步骤，即在“获得一体化封装结构”之前，所需进行的工艺步骤；也可以作为“获得一体化封装结构”的细化步骤，即，上述“获得一体化封装结构”的具体实现过程包括S101、S102及S103。
基于此，本申请实施例还提供一种一体化封装结构的制作方法，该一体化封装结构的制作方法包括上述S101、S102及S103。也就是说，在一些实施例中，上述S101、S102及S103可以构成一种一体化封装结构的制作方法，而不局限于与下述S104、S105及S106共同构成本申请实施例提供的一种芯片封装结构的制作方法。
S104，对一体化封装结构进行第一次切割，以使得每个第一导电柱均暴露出朝向顶面的第一接触面。
S105，在塑封料层的上表面和第一次切割所产生的切割面上形成屏蔽层，切割面包括第一接触面。
S106，对一体化封装结构进行第二次切割，以分离出多个芯片封装结构，每个芯片封装结构上的屏蔽层通过第一接触面连接第一导电柱，第一导电柱用于将屏蔽层接地。
上述S104-S106的具体工艺过程可以参见上述实施例中的内容，此处不予赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种芯片封装结构，其特征在于，包括：
    基板，所述基板包括层叠设置的多个金属层；
    第一导电柱，所述第一导电柱贯穿至少两个所述金属层，所述第一导电柱具有暴露于所述基板外侧且朝向所述基板的顶面的第一接触面；
    芯片，设置在所述顶面上，且与所述顶面上的金属层电连接；
    屏蔽层，形成在所述芯片外，且通过所述第一接触面与所述第一导电柱电连接，所述屏蔽层接地。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述第一导电柱还具有暴露于所述基板外侧且朝向所述基板外侧的第二接触面，所述第二接触面与所述第一接触面形成缺口；所述屏蔽层通过所述第一接触面和所述第二接触面与所述第一导电柱电连接。
  3. 根据权利要求1或2所述的芯片封装结构，其特征在于，所述芯片封装结构还包括形成于所述顶面上的塑封料层，所述芯片包裹于所述塑封料层中；
    所述屏蔽层覆盖于所述塑封料层的表面、所述第一接触面，及所述基板的位于所述第一接触面至所述顶面之间的侧面区域上。
  4. 根据权利要求1-3任一项所述的芯片封装结构，其特征在于，所述屏蔽层通过所述第一导电柱贯穿的至少两个所述金属层中的一个接地。
  5. 根据权利要求4所述的芯片封装结构，其特征在于，所述至少两个所述金属层中的至少一个与所述底面上的金属层连接，所述底面上的金属层用于接地。
  6. 根据权利要求1-5任一项所述的芯片封装结构，其特征在于，所述第一导电柱贯穿的所述金属层均位于所述基板的内部；所述至少两个所述金属层中的一个通过第二导电柱连接所述基板的底面的金属层；
    其中，在平行于所述顶面的方向上，所述第二导电柱与所述第一导电柱远离所述基板外侧的一侧的距离大于第一距离。
  7. 根据权利要求6所述的芯片封装结构，其特征在于，不同所述金属层之间通过由绝缘材料构成的绝缘层间隔。
  8. 根据权利要求7所述的芯片封装结构，其特征在于，所述多个金属层包括连续设置的多个第一金属层和至少一个第二金属层；
    在平行于所述顶面的方向上，所述第一金属层的边缘延伸至所述基板的外侧边缘，所述第一导电柱贯穿至少两个所述第一金属层；
    在平行于所述顶面的方向上，所述第二金属层的边缘与所述第一导电柱远离所述基板外侧的一侧的距离大于第二距离，所述第二距离小于所述第一距离。
  9. 根据权利要求8所述的芯片封装结构，其特征在于，所述第二金属层的数量为多个，且至少两个所述第二金属层连续设置，所述第二导电柱贯穿连续的所述至少两个所述第二金属层。
  10. 根据权利要求6或7所述的芯片封装结构，其特征在于，所述绝缘层包括芯板；所述第一导电柱位于所述芯板的靠近所述芯片的一侧，所述第二金属层位于所述芯板的远离所述芯片的一侧。
  11. 根据权利要求1-9任一项所述的芯片封装结构，其特征在于，设置在所述基板的第一侧的多个所述第一导电柱分布于与所述第一侧的边界线平行的第一直线上；
    或者，设置在所述基板的第一侧的多个所述第一导电柱与所述第一直线的距离在预设距离范围内；所述第一侧为所述基板的任意一侧。
  12. 根据权利要求1-11任一项所述的芯片封装结构，其特征在于，所述底面上的金属层及所述顶面上的金属层包括金属布线层。
  13. 一种芯片封装结构的制作方法，其特征在于，所述方法包括：
    获得待切割的一体化封装结构，其中，所述一体化封装结构包括一体成型的多个基板和设置在每一所述基板的顶面上的芯片；每一所述基板包括多个第一导电柱和层叠设置的多个金属层，每一所述第一导电柱贯穿至少两个所述金属层；
    对所述一体化封装结构进行第一次切割，以在每一所述第一导电柱上形成暴露于所述基板外侧且朝向所述顶面的第一接触面；
    在所述芯片外形成屏蔽层，并使所述屏蔽层通过所述第一接触面与所述第一导电柱电连接；
    对所述一体化封装结构进行第二次切割，得到多个独立的芯片封装结构。
  14. 根据权利要求13所述的芯片封装结构的制作方法，其特征在于，所述对所述一体化封装结构进行第一次切割包括：
    沿第一预设切割道对所述一体化封装结构进行第一次切割；
    其中，所述第一预设切割道与所述第一导电柱的横截面所在区域相交；所述第一预设切割道的深度大于所述顶面与所述第一导电柱的第一端面之间的距离，小于所述顶面与所述第一导电柱的第二端面之间的距离，所述第一端面为所述第一导电柱靠近所述顶面的端面，所述第二端面为所述第一导电柱远离所述顶面的端面。
  15. 根据权利要求14所述的芯片封装结构的制作方法，其特征在于，所述对所述一体化封装结构进行第二次切割，包括：
    沿第二预设切割道对所述一体化封装结构进行第二次切割；
    其中，位于相邻两个所述基板之间的所述第一预设切割道和所述第二预设切割道，在平行于切割道的边缘的方向上的对称轴相同；所述第一预设切割道的宽度大于所述第二预设切割道的宽度。
  16. 根据权利要求14-15任一项所述的芯片封装结构的制作方法，其特征在于，所述第一次切割还使得在所述第一导电柱上形成暴露于所述基板外侧且朝向所述基板外侧的第二接触面，所述第二接触面与所述第一接触面形成缺口；
    所述在所述芯片外形成屏蔽层，并使所述屏蔽层通过所述第一接触面与所述第一导电柱连接，包括：
    在所述芯片外形成屏蔽层，并使所述屏蔽层通过所述第一接触面和所述第二接触面与所述第一导电柱连接。
  17. 根据权利要求16所述的芯片封装结构的制作方法，其特征在于，所述第一预设切割道的边缘与所述第一导电柱的横截面所在区域相交。
  18. 根据权利要求13-17任一项所述的芯片封装结构的制作方法，其特征在于，所述第一导电柱贯穿的所述金属层均位于所述基板的内部；
    所述基板还包括：
    第二导电柱，所述第一导电柱贯穿的任意一个所述金属层通过所述第二导电柱连接所述基板的底面的金属层；在平行于所述顶面的方向上，所述第一预设切割道靠近所述第二导电柱的一侧的边缘与所述第二导电柱的距离大于第三距离。
  19. 根据权利要求13-17任一项所述的芯片封装结构的制作方法，其特征在于，所述基板的所述顶面上设有塑封料层，所述芯片包裹于所述塑封料层；
    所述在所述芯片外形成屏蔽层，包括：
    在所述塑封料层的上表面和所述第一次切割产生的切割面上形成所述屏蔽层，所述切割面包括所述第一接触面、所述塑封料层暴露出的外侧面以及所述基板暴露出的位于所述第一接触面至所述顶面之间的外侧面。
  20. 一种芯片封装结构的制作方法，其特征在于，所述方法包括：
    制备一体化基板，所述一体化基板包括多组第一导电柱和层叠设置的多个金属层，所述第一导电柱贯穿至少两个所述金属层，所述一体化基板的顶面包括由各组所述第一导电柱在所述顶面上的映射位置所围成的多个芯片安装区域；
    在所述顶面上的每一所述芯片安装区域内安装芯片；
    采用塑封材料在所述顶面上形成塑封料层，以使得所述芯片被所述塑封材料包裹，得到一体化封装结构；
    对所述一体化封装结构进行第一次切割，以使得每组所述第一导电柱均暴露出朝向所述顶面的第一接触面；
    在所述塑封料层的上表面和所述第一次切割所产生的切割面上形成屏蔽层，所述切割面包括所述第一接触面；
    对所述一体化封装结构进行第二次切割，以分离出多个芯片封装结构，每个所述芯片封装结构上的屏蔽层通过所述第一接触面连接所述第一导电柱，所述第一导电柱用于将所述屏蔽层接地。
  21. 根据权利要求20所述的芯片封装结构的制作方法，其特征在于，所述制备一体化基板包括：
    采用绝缘材料制备芯板；
    在所述芯板的一侧，形成多个第一金属层，以及，形成多组贯穿至少两个所述第一金属层的所述第一导电柱；所述多个第一金属层在所述顶面的垂直方向上层叠，且通过第一绝缘层间隔；
    以及，在所述芯板的另一侧，形成多组第二金属层；
    其中，不同组所述第二金属层在所述顶面的垂直方向上层叠，且通过第二绝缘层间隔；
    同一组所述第二金属层分别形成于同一表面上的多个预设区域内，任意所述预设区域内的所述第二金属层的边缘与所述预设区域的边缘的距离大于第四距离；所述第二绝缘层具有沿所述表面的垂直方向延伸出的凸出部，所述同一表面上的所述第二金属层之间通过所述凸出部间隔；
    所述表面包括所述芯板的所述另一侧表面及所述第二绝缘层远离所述芯板的表面，所述多个预设区域分别为各组所述第一导电柱在表面上的映射位置所述围成的区域。
  22. 根据权利要求21所述的芯片封装结构的制作方法，其特征在于，一组所述第一导电柱包括多个部分，各部分第一导电柱在所述顶面上的映射位置分别位于所述芯片安装区域的各侧；
    其中，第一部分第一导电柱在所述顶面上的映射位置分布于同一条直线或者与所述同一条直线的距离在预设距离范围内，所述第一部分为所述多个部分中的任意一个。
  23. 根据权利要求21所述的芯片封装结构的制作方法，其特征在于，所述制备一体化基板还包括：
    形成多组第二导电柱，同一组所述第二导电柱在所述表面上的映射位置位于同一个所述预设区域内；
    其中，所述第二导电柱贯穿多个所述第二金属层，且连接所述第一导电柱贯穿的至少一个所述第一金属层和位于所述一体化基板的底面的金属层。
  24. 根据权利要求23所述的芯片封装结构的制作方法，其特征在于，所述预设区域中所述第二导电柱的映射位置与所述预设区域的边缘的距离大于第五距离。
PCT/CN2023/104232 2022-07-30 2023-06-29 芯片封装结构及其制作方法 WO2024027405A1 (zh)

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