WO2024027332A9 - 半导体结构的制备方法及半导体结构 - Google Patents

半导体结构的制备方法及半导体结构 Download PDF

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Publication number
WO2024027332A9
WO2024027332A9 PCT/CN2023/098676 CN2023098676W WO2024027332A9 WO 2024027332 A9 WO2024027332 A9 WO 2024027332A9 CN 2023098676 W CN2023098676 W CN 2023098676W WO 2024027332 A9 WO2024027332 A9 WO 2024027332A9
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WIPO (PCT)
Prior art keywords
semiconductor structure
semiconductor
structures
stacked
preparation
Prior art date
Application number
PCT/CN2023/098676
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English (en)
French (fr)
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WO2024027332A1 (zh
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唐怡
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长鑫存储技术有限公司
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Priority to US18/547,767 priority Critical patent/US20240170324A1/en
Publication of WO2024027332A1 publication Critical patent/WO2024027332A1/zh
Publication of WO2024027332A9 publication Critical patent/WO2024027332A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)

Abstract

本公开实施例提供一种半导体结构的制备方法及半导体结构，半导体结构的制备方法包括：提供基底；在基底上形成沿第一方向间隔排布的堆叠结构，堆叠结构包括沿竖直方向交替堆叠的第一牺牲层与半导体柱；形成隔离结构，隔离结构位于沿第一方向相邻的堆叠结构之间；对隔离结构进行刻蚀，形成通孔，通孔露出基底部分表面，且还露出每一堆叠结构侧面，在沿第二方向上，通孔的底部宽度大于通孔的顶部宽度，第二方向与第一方向垂直；对通孔露出的第一牺牲层进行横向刻蚀，去除部分第一牺牲层以露出每一半导体柱顶面和底面。本公开实施例至少有利于改善形成的半导体结构的形貌。
PCT/CN2023/098676 2022-08-02 2023-06-06 半导体结构的制备方法及半导体结构 WO2024027332A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/547,767 US20240170324A1 (en) 2022-08-02 2023-06-06 Method of fabrication for a semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210922714.2A CN117558677A (zh) 2022-08-02 2022-08-02 半导体结构的制备方法及半导体结构
CN202210922714.2 2022-08-02

Publications (2)

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WO2024027332A1 WO2024027332A1 (zh) 2024-02-08
WO2024027332A9 true WO2024027332A9 (zh) 2024-03-28

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ID=89817175

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US (1) US20240170324A1 (zh)
CN (1) CN117558677A (zh)
WO (1) WO2024027332A1 (zh)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324731B1 (en) * 2015-01-30 2016-04-26 Macronix International Co., Ltd. Method for fabricating memory device
KR20170103204A (ko) * 2016-03-03 2017-09-13 에스케이하이닉스 주식회사 반도체장치 제조 방법
CN113644061B (zh) * 2020-04-27 2023-08-22 长鑫存储技术有限公司 半导体结构及其形成方法、存储器及其形成方法
CN112071841A (zh) * 2020-09-17 2020-12-11 芯盟科技有限公司 半导体结构及其形成方法
CN114725018B (zh) * 2021-01-04 2024-06-21 长鑫存储技术有限公司 存储器及其制备方法

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WO2024027332A1 (zh) 2024-02-08
US20240170324A1 (en) 2024-05-23
CN117558677A (zh) 2024-02-13

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