Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits

Definitions

• the present invention relates to a wiring board and a mounting structure using the same.
• vias via holes formed in an insulating layer are filled with conductors (via hole conductors), as shown in Patent Document 1.
• a via hole conductor is usually connected to a via land at the bottom of the via.
• stress tends to concentrate at the connection portion between the via bottom and the via land. Therefore, if exposed to high temperature conditions, it may break.
• a wiring board includes a first insulating layer having a first surface, a second insulating layer located on the first surface and having a via hole, and a via conductor portion penetrating the second insulating layer.
• the via conductor portion includes a via land conductor located on the first surface and a via hole conductor that is in contact with the via land conductor and located in the via hole.
• the via land conductor has at least a first layer including a connection portion in contact with the via hole conductor, and a second layer in contact with the first insulating layer side of the first layer.
• the via conductor portion has a continuous crystal that spans the first layer and the via hole conductor via the connection portion.
• the first grain size of the first layer is different from the second grain size of the second layer.
• the mounting structure according to the present disclosure includes the above wiring board and an electronic component located in the mounting area of the wiring board.
• FIG. 1 is an explanatory diagram for explaining a wiring board according to an embodiment of the present disclosure.
• 2 is an electron micrograph showing an example of region X shown in FIG. 1.
• FIG. 3 is an explanatory diagram for explaining an example of a method of forming a via conductor portion in a wiring board according to an embodiment of the present disclosure.
• FIG. 3 is an explanatory diagram for explaining an example of a method of forming a via conductor portion in a wiring board according to an embodiment of the present disclosure.
• FIG. 3 is an explanatory diagram for explaining an example of a method of forming a via conductor portion in a wiring board according to an embodiment of the present disclosure.
• the wiring board according to the present disclosure has the configuration described in the column of means for solving the above problems, so that it has excellent connection strength between the via bottom and the via land, and has excellent connection strength in the vertical and horizontal directions in the via land. Wire breakage due to crack extension can be reduced.
• FIG. 1 is an explanatory diagram for explaining a wiring board 1 according to an embodiment of the present disclosure.
• a wiring board 1 according to one embodiment includes an insulating layer 2, a conductor layer 3, and a solder resist 4.
• the insulating layer 2 includes a first insulating layer 21 and a second insulating layer 22.
• the first insulating layer 21 has upper and lower surfaces (first surface 211), and is not particularly limited as long as it is made of an insulating material. Examples of the material having insulation properties include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. These resins may be used in combination of two or more.
• the first insulating layer 21 corresponds to a core insulating layer.
• the thickness of the first insulating layer 21 is not particularly limited, and when the first insulating layer 21 corresponds to a core insulating layer, it is, for example, 100 ⁇ m or more and 3000 ⁇ m or less.
• the first insulating layer 21 may include a reinforcing material.
• the reinforcing material include insulating cloth materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may be used in combination.
• an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, or titanium oxide may be dispersed in the first insulating layer 21 .
• a through-hole conductor 21a is located in the first insulating layer 21 in order to electrically connect the upper and lower surfaces of the first insulating layer 21.
• the through-hole conductor 21a is located in a through-hole that penetrates the first insulating layer 21 from the top surface to the bottom surface.
• the through-hole conductor 21a is formed of, for example, metal plating such as copper plating.
• the through-hole conductor 21a is connected to the conductor layer 3 formed on both sides of the first insulating layer 21.
• the through-hole conductor 21a may be located only on the inner wall surface of the through-hole 21a', or may be filled in the through-hole 21a'.
• a build-up layer in which conductor layers 3 and insulating layers 2 are alternately laminated is located on the first surface 211 of the first insulating layer 21 .
• the build-up layer at least two conductor layers 3 and one insulating layer 2 are laminated.
• the insulating layer 2 that is in contact with the first surface 211 of the first insulating layer 21 corresponds to the second insulating layer 22 .
• the conductor layer 3 is not limited as long as it is a conductor such as metal. Specifically, the conductor layer 3 is formed of metal foil such as copper foil, metal plating such as copper plating, or the like. The thickness of the conductor layer 3 is not particularly limited, and is, for example, 5 ⁇ m or more and 20 ⁇ m or less.
• the insulating layer 2 constituting the build-up layer is not particularly limited as long as it is made of an insulating material.
• examples include resins such as epoxy resins, bismaleimide-triazine resins, polyimide resins, and polyphenylene ether resins. These resins may be used in combination of two or more.
• the insulating layers 2 forming the buildup layer may be made of the same resin or different resins.
• the insulating layer 2 and the first insulating layer 21 constituting the build-up layer may be made of the same resin or may be made of different resins.
• the thickness of the insulating layer 2 constituting the build-up layer is not particularly limited, and is, for example, 10 ⁇ m or more and 50 ⁇ m or less.
• the insulating layers 2 constituting the build-up layer may have the same thickness, or may have different thicknesses.
• the insulating layer 2 constituting the build-up layer may contain a reinforcing material.
• the reinforcing material include insulating cloth materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may be used in combination.
• inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide may be dispersed in the insulating layer 2 constituting the build-up layer.
• a solder resist 4 may be located on the surface of the buildup layer.
• the solder resist 4 is made of resin, and examples of the resin include acrylic modified epoxy resin.
• An opening is provided in the solder resist 4 in order to electrically connect the conductor layer 3 and the electrode of the element via the solder 5.
• the element include a semiconductor integrated circuit element, an optoelectronic element, and the like.
• a via conductor portion 31 for electrically connecting the upper and lower surfaces of the second insulating layer 22 is formed in the second insulating layer 22 .
• the via conductor portion 31 is located in a via hole formed to penetrate the second insulating layer 22. That is, the via conductor portion 31 is located so as to penetrate the second insulating layer 22 .
• the via conductor portion 31 includes a via land conductor 3a and a via hole conductor 3b.
• FIG. 2 is an electron micrograph showing an example of region X shown in FIG.
• the via land conductor 3a is located on the first surface 211 of the first insulating layer 21.
• the via hole conductor 3b is filled in a via hole formed in the second insulating layer 22, and the bottom portion (the bottom surface on the side closer to the first surface 211) is in contact with the via land conductor 3a.
• Via land conductor 3a and via hole conductor 3b are part of conductor layer 3, and are made of metal such as copper.
• the via land conductor 3a includes a first layer 3a1, a second layer 3a2, and a third layer 3a3.
• the first layer 3a1 includes a connecting portion 3a1' that contacts the via hole conductor 3b.
• the first layer 3a1 and the via hole conductor 3b are connected via a connecting portion 3a1' by a straddling continuous crystal.
• the second layer three a2 is located closer to the first insulating layer 21 than the first layer three a1, and is in contact with the first layer three a1.
• the third layer three a3 is located closer to the first insulating layer 21 than the second layer three a2, and is in contact with the second layer three a2.
• Continuous crystals can be determined by observing, for example, a cross section of the via land conductor 3a and the via hole conductor 3b with a scanning electron microscope, and at least one crystal grain is located across the first layer 3a1 and the via hole conductor 3b. Just check.
• the crystal grain size of the crystals forming the first layer 3a1 (hereinafter referred to as “first crystal grain size”) is the same as the crystal grain size of the crystals forming the second layer 3a2 (hereinafter referred to as “first crystal grain size”). 2nd crystal grain size). That is, at the contact surface (connection part 3a1') between the first layer 3a1 and the via hole conductor 3b, not only the first layer 3a1 and the via hole conductor 3b are connected by continuous crystal, but also the first crystal grain size and the second The grain size is different.
• connection portion 3a1' At the contact surface (connection portion 3a1') between the first layer 3a1 and the via hole conductor 3b, the first layer 3a1 and the via hole conductor 3b are connected by a continuous crystal. Therefore, in the connection portion 3a1' between the first layer 3a1 and the via-hole conductor 3b where thermal stress tends to concentrate, the extension of cracks in the direction (lateral direction) along the upper surface of the via-land conductor 3a, for example, is reduced. Furthermore, since the first crystal grain size and the second crystal grain size are different, the interface between the crystal grains of the first layer three a1 and the interface between the crystal grains of the second layer three a2 become difficult to match. Therefore, the extension of cracks along the thickness direction (vertical direction) of the via land conductor 3a is reduced.
• the second crystal grain size is larger than the first crystal grain size, for example, when a crack occurs in the thickness direction along the interface of the crystal grains of the first layer 3a1, the The crack extension can be reduced in the area.
• the first crystal grain size and the crystal grain size of the crystal constituting the third layer 3a3 may be smaller than the second crystal grain size. That is, the second grain size is larger than the first grain size and the third grain size.
• the crystal grains in the second layer 3a2 It is possible to reduce crack extension in areas other than the interface.
• the first crystal grain size may be, for example, 1 ⁇ m or more and 2.8 ⁇ m or less, or 1.5 ⁇ m or more and 2.1 ⁇ m or less.
• the second crystal grain size may be, for example, 2.9 ⁇ m or more and 9 ⁇ m or less, or 3.1 ⁇ m or more and 3.6 ⁇ m or less.
• the third crystal grain size may be, for example, 1 ⁇ m or more and 2.1 ⁇ m or less, or 1.4 ⁇ m or more and 1.8 ⁇ m or less.
• the crystal grain size is measured, for example, in accordance with JIS H0501. Specifically, the number of crystal grains captured by a test line having a known length is counted. This measurement is performed at five arbitrary locations. Next, the arithmetic mean value is determined for the number of crystal grains obtained at the five locations. Next, the average line segment length per grain (ie, grain size) of the test line is determined.
• the thicknesses of the first layer 3a1, second layer 3a2, and third layer 3a3 are not limited.
• the thickness of the first layer 3a1 may be greater than the thickness of the second layer 3a2 and the thickness of the third layer 3a3.
• the first layer three a1 may have a thickness of, for example, 10 ⁇ m or more and 20 ⁇ m or less.
• the second layer 3a2 may have a thickness of, for example, 5 ⁇ m or more and 15 ⁇ m or less.
• the third layer 3a3 may have a thickness of, for example, 2 ⁇ m or more and 10 ⁇ m or less.
• the thickness of the first layer 3a1 is, for example, between a virtual line that includes many flat areas at the roots of the unevenness on the surface of the first layer 3a1 on the second insulating layer 22 side, and an interface between the first layer 3a1 and the second layer 3a2. It can be defined as distance.
• the thickness of the second layer 3a2 can be defined, for example, as the distance between the interface between the first layer 3a1 and the second layer 3a2 and the interface between the second layer 3a2 and the third layer 3a3.
• the thickness of the third layer 3a3 is, for example, the distance between an imaginary line that includes many flat parts at the roots of the unevenness on the surface of the third layer 3a3 on the first insulating layer 21 side and the interface between the second layer 3a2 and the third layer 3a3. It can be defined as
• the first crystal grain size of the first layer 3a1 is relatively small, thermal stress will occur. Even if the crystal expands, the directions of expansion tend to be dispersed. When the thickness of the first layer 3a1 is greater than the thickness of the second layer 3a2 and the thickness of the third layer 3a3, the directions of expansion become more easily dispersed. As a result, the occurrence of cracks and peeling can be further reduced.
• the arithmetic mean roughness of the upper and lower surfaces of the via land conductor 3a is not limited.
• the surface of the first layer three a1 on the second insulating layer 22 side means the surface that is in contact with the second insulating layer 22.
• the arithmetic mean roughness of the surface of the first layer three a1 on the second insulating layer 22 side may be smaller than the arithmetic mean roughness of the surface of the third layer three a3 on the first insulating layer 21 side. In such a case, it is possible to improve the adhesion between the first insulating layer 21 and the via land conductor 3a, and to maintain good electrical properties as a conductor.
• the arithmetic mean roughness of the surface of the first layer three a1 on the second insulating layer 22 side may be, for example, 50 nm or more and 500 nm or less.
• the arithmetic mean roughness of the surface of the third layer 3a3 on the first insulating layer 21 side may be, for example, 200 nm or more and 1000 nm or less.
• FIGS. 3 to 5 are explanatory diagrams for explaining an example of a method for forming via conductor portions 31 in wiring board 1 according to an embodiment of the present disclosure.
• metal foil 3' such as copper foil is attached to the upper and lower surfaces (first surface 211) of the first insulating layer 21.
• a double-sided metal-clad laminate such as a double-sided copper-clad laminate may be prepared.
• This metal foil 3' corresponds to the third layer 3a3 of the via land conductor 3a in the wiring board 1 according to one embodiment.
• through holes 21a' are formed so as to penetrate through the upper and lower surfaces of the first insulating layer 21 to which the metal foil 3' is attached.
• the size and number of through holes 21a' are appropriately set depending on the size of the wiring board 1 finally obtained.
• the through hole 21a' is formed using, for example, a drill. Desmear treatment or the like is performed as necessary to remove resin residue and the like.
• a seed layer is formed on the surface of the metal foil 3' and the inner wall surface of the formed through hole 21a'.
• metal can be efficiently deposited by electrolytic plating in the next step.
• the seed layer is made of metal such as copper.
• a metal such as copper is deposited on the surface of the seed layer by electrolytic plating to form a through-hole conductor 21a on the inner wall surface of the through-hole 21a'.
• a layer of the same conductor as the through-hole conductor 21a is also formed on the surface of the metal foil 3' located on the upper and lower surfaces of the first insulating layer 21.
• the same conductor layer as the through-hole conductor 21a corresponds to the second layer 3a2 of the via land conductor 3a in the wiring board 1 according to one embodiment.
• the crystal grain size of each layer forming the via land conductor 3a is different. Therefore, it is necessary to make the crystal grain size of the metal foil 3' different from the crystal grain size of the metal deposited by electrolytic plating.
• the crystal grain size of the deposited metal can be controlled, for example, by adjusting the current density and the amount of additives. Specifically, the crystal grain size of the precipitated metal can be increased by increasing the current density or decreasing the amount of brightener added. On the other hand, by reducing the current density or increasing the amount of brightener added, the crystal grain size of the precipitated metal can be reduced. Brightener suppresses crystal growth by adsorbing to the growth points of crystal nuclei. This generates new crystal nuclei on the plating surface, promoting finer crystals and forming a dense plating film. In other words, increasing the amount of brightener decreases the grain size, and decreasing brightener increases the grain size.
• the through hole 21a' is filled with resin.
• the resin filled in the through hole 21a' is not limited, and examples thereof include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin.
• the resin filled in the through hole 21a' and a layer of the same conductor as the through hole conductor 21a formed on the surface of the metal foil 3' are mixed. , polish it so that it is almost flush.
• a metal such as copper is deposited on the substantially flush surface in FIG. 4A by electroless plating and electrolytic plating.
• the layer formed by this plating process corresponds to the first layer 3a1 of the via land conductor 3a in the wiring board 1 according to one embodiment. Therefore, it is necessary to match the crystal grain size of the via hole conductor 3b to be formed later. By matching the crystal grain size of the via hole conductor 3b, it is possible to finally form a continuous crystal spanning the first layer 3a1 and the via hole conductor 3b via the connection portion 3a1'.
• the method for adjusting the crystal grain size in electrolytic plating is as described above, and detailed explanation will be omitted.
• a resist 6 is formed at the position where the via land conductor 3a is to be formed.
• an etching process is performed to remove the metal foil 3' and the plated metal in the area where the resist 6 is not formed, as shown in FIG. 4D.
• the resist 6 is removed to form a via land conductor 3a including a first layer 3a1, a second layer 3a2, and a third layer 3a3.
• the second insulating layer 22 is formed on the first surface 211 of the first insulating layer 21 so as to cover the via land conductor 3a.
• the material forming the second insulating layer 22 is as described above, and detailed description thereof will be omitted.
• a via hole having the via land conductor 3a as the bottom surface is formed in the second insulating layer 22.
• the via hole is formed using, for example, a laser. The size and number of via holes are appropriately set depending on the size of the wiring board 1 finally obtained.
• a metal such as copper is deposited in the formed via hole by electroless plating and electrolytic plating to fill the via hole with metal and form a via hole conductor 3b.
• the crystal grain size of the via hole conductor 3b may be made to match the crystal grain size of the first layer three a1 of the via land conductor 3a. In this way, via conductor portion 31 is formed.
• a mounting structure includes a wiring board 1 according to an embodiment and an element S located on the surface of the wiring board 1.
• the conductor layer 3 in the opening of the solder resist 4 and the electrode of the element S are connected via the solder 5.
• examples of the element S include a semiconductor integrated circuit element, an optoelectronic element, and the like. Elements may be located on both sides of the wiring board 1, and the element S may be located on one surface and, for example, a motherboard or the like may be located on the other surface.
• the via land conductor 3a has a three-layer structure of a first layer 3a1, a second layer 3a2, and a third layer 3a3.
• the via land conductor does not need to have a three-layer structure, and may have a two-layer structure of a first layer and a second layer.
• the arithmetic mean roughness of the surface of the first layer on the second insulating layer side may be smaller than the arithmetic mean roughness of the surface of the second layer on the first insulating layer side. In such a case, it is possible to improve the adhesion between the first insulating layer and the via land conductor, and to maintain good electrical properties as a conductor.
• the wiring board 1 has the first insulating layer 21 as the core insulating layer, and is in contact with the first surface 211 of the core insulating layer among the insulating layers 2 forming the buildup layer.
• the insulating layer 2 is a second insulating layer 22. Cracks and peeling are most likely to occur in the via conductor portion 31 located in the insulating layer 2 forming the build-up layer that is in contact with the core insulating layer. Therefore, in the wiring board 1 according to one embodiment, at least the via conductor portion 31 as described above may be located in the insulating layer 2 constituting the build-up layer that is in contact with the core insulating layer. . That is, the conventional via land and via hole conductors may be located in the other insulating layer 2 constituting the buildup layer, and the via conductor portion 31 as described above may be located therein.
• the buildup layer is Among the constituent insulating layers, even if one insulating layer is the "first insulating layer” and the insulating layer located on the first surface of this first insulating layer is the "second insulating layer”. good.
• a wiring board includes a first insulating layer having a first surface, a second insulating layer located on the first surface and having a via hole, and a via conductor portion penetrating the second insulating layer.
• the via conductor portion includes a via land conductor located on the first surface and a via hole conductor that is in contact with the via land conductor and located in the via hole.
• the via land conductor has at least a first layer including a connection portion in contact with the via hole conductor, and a second layer in contact with the first insulating layer side of the first layer.
• the via conductor portion has a continuous crystal that spans the first layer and the via hole conductor via the connection portion.
• the first grain size of the first layer is different from the second grain size of the second layer.
• the second crystal grain size is larger than the first crystal grain size.
• the via land conductor further includes a third layer in contact with the first insulating layer side of the second layer, and has a first crystal grain size and a third layer. The third grain size is smaller than the second grain size.
• the arithmetic mean roughness of the surface of the first layer on the second insulating layer side is smaller than the arithmetic mean roughness of the surface of the third layer on the first insulating layer side.
• the thickness of the first layer is greater than the thickness of the second layer and the thickness of the third layer.
• a mounting structure includes the wiring board according to any one of (1) to (5) above, and an electronic component located in a mounting area of the wiring board.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)

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• 2023
  • 2023-07-27 WO PCT/JP2023/027508 patent/WO2024024878A1/ja not_active Ceased
  • 2023-07-27 TW TW112128179A patent/TWI878995B/zh active
  • 2023-07-27 JP JP2024537219A patent/JPWO2024024878A1/ja active Pending

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