WO2024023967A1 - 構造体、量子ビット、量子演算装置及び構造体の製造方法 - Google Patents

構造体、量子ビット、量子演算装置及び構造体の製造方法 Download PDF

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WO2024023967A1
WO2024023967A1 PCT/JP2022/028919 JP2022028919W WO2024023967A1 WO 2024023967 A1 WO2024023967 A1 WO 2024023967A1 JP 2022028919 W JP2022028919 W JP 2022028919W WO 2024023967 A1 WO2024023967 A1 WO 2024023967A1
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layer
transition metal
hinge
metal dichalcogenide
helical channel
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French (fr)
Japanese (ja)
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淳一 山口
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to US18/948,638 priority patent/US20250081859A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H10N60/128—Junction-based devices having three or more electrodes, e.g. transistor-like structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H10N60/12—Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/85—Superconducting active materials

Definitions

  • the present disclosure relates to a structure, a quantum bit, a quantum operation device, and a method for manufacturing the structure.
  • An object of the present disclosure is to provide a structure, a quantum bit, a quantum operation device, and a method for manufacturing the structure that can obtain good crystallinity in a transition metal dichalcogenide layer.
  • FIG. 1 is a sectional view showing a structure according to a first embodiment.
  • FIG. 2 is a cross-sectional view (part 1) showing the method for manufacturing the structure according to the first embodiment.
  • FIG. 3 is a cross-sectional view (Part 2) showing the method for manufacturing the structure according to the first embodiment.
  • FIG. 4 is a cross-sectional view (Part 3) showing the method for manufacturing the structure according to the first embodiment.
  • FIG. 5 is a cross-sectional view (part 4) showing the method for manufacturing the structure according to the first embodiment.
  • FIG. 6 is a cross-sectional view (Part 5) showing the method for manufacturing the structure according to the first embodiment.
  • FIG. 7 is a diagram (part 1) showing the results of STEM observation.
  • FIG. 8 is a diagram (part 2) showing the results of STEM observation.
  • FIG. 9 is a diagram showing the results of Raman spectroscopy according to the first embodiment.
  • FIG. 10 is a top view showing a quantum bit according to the second embodiment.
  • FIG. 11 is a cross-sectional view (part 1) showing the quantum bit according to the second embodiment.
  • FIG. 12 is a cross-sectional view (part 2) showing the quantum bit according to the second embodiment.
  • FIG. 13 is a perspective view showing a higher order topological insulator layer.
  • FIG. 14 is a top view (part 1) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 15 is a top view (Part 2) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 16 is a top view (Part 3) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 17 is a top view (Part 4) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 18 is a top view (part 5) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 19 is a top view (Part 6) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 20 is a cross-sectional view (part 1) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 21 is a cross-sectional view (part 2) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 22 is a cross-sectional view (part 3) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 23 is a cross-sectional view (part 4) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 24 is a cross-sectional view (part 5) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 25 is a cross-sectional view (part 6) showing the method for manufacturing a quantum bit according to the second embodiment.
  • FIG. 26 is a diagram showing a quantum computing device according to the third embodiment.
  • the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are mutually orthogonal directions.
  • a plane including the X1-X2 direction and the Y1-Y2 direction is referred to as an XY plane
  • a plane including the Y1-Y2 direction and the Z1-Z2 direction is referred to as a YZ plane
  • a plane including the Z1-Z2 direction and the X1-X2 direction. is written as the ZX plane.
  • the Z1-Z2 direction is referred to as the vertical direction, with the Z1 side being the upper side and the Z2 side being the lower side.
  • planar view refers to viewing the object from the Z1 side
  • planar shape refers to the shape of the object viewed from the Z1 side.
  • FIG. 1 is a sectional view showing a structure according to a first embodiment.
  • the structure 100 includes a substrate 110, an s-wave superconductor layer 120, a first transition metal dichalcogenide layer 130, and a second transition metal dichalcogenide layer 140.
  • An s-wave superconductor layer 120 is formed on the substrate 110.
  • a first transition metal dichalcogenide layer 130 is formed on the s-wave superconductor layer 120.
  • the second transition metal dichalcogenide layer 140 is formed on the first transition metal dichalcogenide layer 130.
  • the substrate 110 is, for example, a single crystal substrate whose surface has a Miller index of (100).
  • the material of the substrate 110 is, for example, MgO.
  • the substrate 110 is an example of a base material.
  • the s-wave superconductor layer 120 is, for example, an Nb layer whose surface has a Miller index of (100).
  • the thickness of the s-wave superconductor layer 120 is, for example, about 40 nm.
  • the first transition metal dichalcogenide layer 130 includes a van der Waals layered material that is a two-dimensional material.
  • a van der Waals layered material is, for example, NbTe2 .
  • the first transition metal dichalcogenide layer 130 has multiple layers, for example, three layers, of NbTe 2 .
  • the thickness of the first transition metal dichalcogenide layer 130 is, for example, 1 nm to 5 nm.
  • the second transition metal dichalcogenide layer 140 includes, for example, a multilayer film of WTe 2 .
  • the second transition metal dichalcogenide layer 140 includes multiple layers of WTe 2 , which is a two-dimensional material.
  • the thickness of the second transition metal dichalcogenide layer 140 is, for example, 1 nm to 5 nm.
  • 2 to 6 are cross-sectional views showing a method of manufacturing the structure 100 according to the first embodiment.
  • an MgO single crystal substrate with a Miller index of (100) is used as the substrate 110
  • an Nb layer is formed as the s-wave superconductor layer 120
  • a NbTe double layer is formed as the first transition metal dichalcogenide layer 130.
  • the second transition metal dichalcogenide layer 140 a multilayer film of WTe 2 is formed.
  • a substrate 110 (MgO single crystal substrate) is prepared, and the substrate 110 is annealed at about 1200° C. for 3 to 4 hours in an oxygen atmosphere at atmospheric pressure.
  • the substrate 110 is immersed in methanol for 20 to 30 minutes, and rinsed with ultrapure water. These treatments can improve the flatness of the surface of the substrate 110.
  • the surface of the substrate 110 will have atomic level flatness.
  • an s-wave superconductor layer 120 (Nb layer) is formed on the substrate 110.
  • the S-wave superconductor layer 120 can be epitaxially grown, for example, by pulse laser deposition (PLD).
  • PLD pulse laser deposition
  • the thickness of the s-wave superconductor layer 120 is approximately 40 nm.
  • a pure Nb metal target can be used as the target.
  • the temperature of the substrate 110 is maintained at about 950° C.
  • the laser energy density is 2.0 J/cm 2
  • the irradiation frequency is 10 Hz
  • the temperature between the substrate 110 and the target is The distance between them is approximately 5 cm
  • the film formation rate is 1.0 nm/min.
  • the Nb layer is epitaxially grown on the substrate 110 maintained at about 950° C. while being oriented in the [100] direction.
  • post-annealing is preferably performed at 1100° C. to 1200° C. for 10 minutes. Post-annealing can improve the surface flatness of the s-wave superconductor layer 120.
  • the surface of the s-wave superconductor layer 120 will have flatness on an atomic level.
  • a chalcogen layer 131 is formed on the s-wave superconductor layer 120, and a metal layer 132 containing a transition metal is formed on the chalcogen layer 131.
  • a Te layer is formed as the chalcogen layer 131 and an Nb layer is formed as the metal layer 132.
  • the thickness of the chalcogen layer 131 is 20 nm, and the thickness of the metal layer 132 is 2 nm.
  • a Te pure metal target can be used as the target.
  • the temperature of the substrate 110 is maintained at room temperature, the laser energy density is 1.0 J/cm 2 , the irradiation frequency is 1 Hz, and the distance between the substrate 110 and the target is approximately 5 cm. , the film formation rate is 10.0 nm/min.
  • a pure Nb metal target can be used as the target.
  • the temperature of the substrate 110 is maintained at room temperature
  • the laser energy density is 2.0 J/cm 2
  • the irradiation frequency is 10 Hz
  • the distance between the substrate 110 and the target is approximately 5 cm.
  • the film formation rate is 1.0 nm/min.
  • NbTe 2 which is a van der Waals layered material, is generated from Te contained in the chalcogen layer 131 and Nb contained in the metal layer 132, and a first transition metal dichalcogenide containing NbTe 2 is generated.
  • Layer 130 ( two layers of NbTe) is formed. Nb contained in the s-wave superconductor layer 120 may also be used to form the first transition metal dichalcogenide layer 130.
  • a portion of the chalcogen layer 131 may remain after the first transition metal dichalcogenide layer 130 is formed.
  • the vapor pressure of Te is relatively low, since the metal layer 132 is formed on the chalcogen layer 131, the metal layer 132 functions as a cap layer, and rapid evaporation of Te in the chalcogen layer 131 due to heating is prevented. suppressed.
  • the first transition metal dichalcogenide layer 130 is formed in a layered manner on the S-wave superconductor layer 120, and the crystal structure of the first transition metal dichalcogenide layer 130 exhibits an 1T structure.
  • the thickness of the first transition metal dichalcogenide layer 130 is, for example, 1 nm to 5 nm.
  • a second transition metal dichalcogenide layer 140 (a multilayer film of WTe 2 ) is formed on the first transition metal dichalcogenide layer 130.
  • the second transition metal dichalcogenide layer 140 can be epitaxially grown by, for example, a PLD method.
  • the thickness of the second transition metal dichalcogenide layer 140 is approximately 1 nm to 5 nm.
  • a WTe 2 sintered body target can be used as the target.
  • the temperature of the substrate 110 is maintained at about 325° C.
  • the laser energy density is 1.0 J/cm 2
  • the irradiation frequency is 10 Hz
  • the substrate 110 and target are The distance between them is approximately 5 cm
  • the film formation rate is 1.0 nm/min.
  • a second transition metal dichalcogenide layer 140 is epitaxially grown on the first transition metal dichalcogenide layer 130 .
  • the crystal structure of the second transition metal dichalcogenide layer 140 shows a Td structure.
  • the s-wave superconductor layer 120 and the second transition metal dichalcogenide layer 140 can be epitaxially grown in situ, for example, in the same vacuum chamber.
  • the S-wave superconductor layer 120, the chalcogen layer 131, the metal layer 132, and the second transition metal dichalcogenide layer 140 can be formed by a physical vapor deposition method in an integrated vacuum process.
  • the method for forming the s-wave superconductor layer 120, the chalcogen layer 131, the metal layer 132, and the second transition metal dichalcogenide layer 140 is not limited to the PLD method. For example, it may be formed by a molecular beam epitaxy (MBE) method, a sputtering method, or a vapor deposition method.
  • MBE molecular beam epitaxy
  • the structure 100 according to the first embodiment can be manufactured.
  • the first transition metal dichalcogenide layer 130 functions as a seed layer when forming the second transition metal dichalcogenide layer 140. Therefore, good crystallinity can be obtained in the second transition metal dichalcogenide layer 140. That is, in this embodiment, the first transition metal dichalcogenide layer 130 includes a van der Waals layered material, and the upper surface of the first transition metal dichalcogenide layer 130 is an inactive surface with suppressed dangling bonds. Therefore, the second transition metal dichalcogenide layer 140 with good crystallinity can be grown heteroepitaxially.
  • post-annealing is preferably performed at about 300° C. for 30 minutes to 1 hour. This is because the crystallinity of the second transition metal dichalcogenide layer 140 is improved.
  • FIGS. 7 and 8 are diagrams showing the results of STEM observation.
  • FIG. 7 shows a wide-area image obtained by the high-angle annular dark field (HAADF) method
  • FIG. 8 shows a narrow-area image obtained by the high-resolution HAADF method.
  • “Nb (100)” in FIGS. 7 and 8 indicates that the s-wave superconductor layer 120 is an Nb layer whose surface (upper surface) has a Miller index of (100).
  • the second transition metal dichalcogenide layer 140 was observed to have grown uniformly over at least several tens of nanometers in a plane parallel to the surface of the s-wave superconductor layer 120. Further, as shown in FIG. 8, on the S-wave superconductor layer 120, a first transition metal dichalcogenide layer 130 (NbTe 2 layer) and a second transition metal dichalcogenide layer 140 (WTe 2 layer) was observed. The contrast between the first transition metal dichalcogenide layer 130 and the second transition metal dichalcogenide layer 140 is different. Note that the thickness of one layer of NbTe 2 and the thickness of one layer of WTe 2 are both about 0.7 nm.
  • FIG. 9 is a diagram showing the results of Raman spectroscopy according to the first embodiment.
  • the second embodiment relates to quantum bits.
  • the quantum bit according to the second embodiment is used, for example, in a quantum computing device such as a quantum computer.
  • FIG. 10 is a top view showing a quantum bit according to the second embodiment.
  • 11 and 12 are cross-sectional views showing the quantum bit according to the second embodiment.
  • FIG. 11 corresponds to a cross-sectional view taken along the line XI-XI in FIG.
  • FIG. 12 corresponds to a cross-sectional view taken along line XII-XII in FIG.
  • the quantum bit 1 includes a substrate 90, an s-wave superconductor layer 10, a transition metal dichalcogenide layer 70, a higher-order topological insulator layer 20, and a first ferromagnetic insulator layer 31. , a second ferromagnetic insulator layer 32 and a third ferromagnetic insulator layer 33.
  • the quantum bit 1 further includes a first gate electrode 41, a second gate electrode 42, a third gate electrode 43, a first superconducting quantum interference device (SQUID) 61, a second SQUID 62, It has a third SQUID 63.
  • SQUID superconducting quantum interference device
  • the substrate 90 is, for example, a single crystal substrate whose surface has a Miller index of (100).
  • Materials for the substrate 90 include MgO, mica, sapphire, and SiC.
  • the substrate 90 may be a Si substrate with a thermal oxide film.
  • the s-wave superconductor layer 10 is provided on a part of the surface of the substrate 90.
  • the s-wave superconductor layer 10 is, for example, an Nb layer whose surface has a Miller index of (100).
  • the thickness of the s-wave superconductor layer 10 is, for example, about 40 nm.
  • the planar shape of the s-wave superconductor layer 10 is a rectangle with two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction.
  • a transition metal dichalcogenide layer 70 is provided on the s-wave superconductor layer 10.
  • the transition metal dichalcogenide layer 70 includes a van der Waals layered material that is a two-dimensional material.
  • a van der Waals layered material is, for example, NbTe2 .
  • the transition metal dichalcogenide layer 70 has multiple layers of NbTe 2 .
  • the thickness of the transition metal dichalcogenide layer 70 is, for example, 2 nm.
  • the transition metal dichalcogenide layer 70 is also an example of a first transition metal dichalcogenide layer.
  • a higher order topological insulator layer 20 is provided on the transition metal dichalcogenide layer 70.
  • the higher-order topological insulator layer 20 includes, for example, a multilayer film of WTe2 .
  • the high-order topological insulator layer 20 includes multiple layers of WTe 2 , which is a two-dimensional material.
  • the thickness of the higher-order topological insulator layer 20 is, for example, 10 nm.
  • the higher-order topological insulator layer 20 is also an example of a second transition metal dichalcogenide layer.
  • FIG. 13 is a perspective view showing the higher-order topological insulator layer 20.
  • the shape of the higher-order topological insulator layer 20 is approximately a rectangular parallelepiped.
  • the a-axis direction of the higher-order topological insulator layer 20 is parallel to the Y1-Y2 direction, the b-axis direction is parallel to the X1-X2 direction, and the c-axis direction is parallel to the Z1-Z2 direction.
  • the Miller index of the upper surface of the higher-order topological insulator layer 20 is (001), the Miller index of the side surface on the Y2 side is (100), and the Miller index of the side surface on the X1 side is (010).
  • a T-shaped groove 50 is formed in the surface of the high-order topological insulator layer 20 when viewed from above.
  • the groove 50 has a first groove 51, a second groove 52, and a third groove 53.
  • the width of the first groove 51, the second groove 52, and the third groove 53 is 20 nm, and the depth is 5 nm.
  • the first groove 51 and the third groove 53 extend in parallel in the X1-X2 direction
  • the second groove 52 extends in parallel in the Y1-Y2 direction.
  • the first groove 51 is provided near the center of the high-order topological insulator layer 20 in the Y1-Y2 direction, and extends from the end of the high-order topological insulator layer 20 on the X2 side to the center in the X1-X2 direction.
  • the third groove 53 is provided near the center of the high-order topological insulator layer 20 in the Y1-Y2 direction, and extends from the end of the high-order topological insulator layer 20 on the X1 side to the center in the X1-X2 direction. Therefore, the first groove 51 and the third groove 53 are formed in a straight line.
  • the second groove 52 is provided near the center of the higher-order topological insulator layer 20 in the X1-X2 direction, and extends from the end of the higher-order topological insulator layer 20 on the Y1 side to the center in the Y1-Y2 direction. Therefore, the second groove 52 is orthogonal to the first groove 51 and the third groove 53.
  • the high-order topological insulator layer 20 has a first region 21 on the Y2 side from the first groove 51 and the third groove 53.
  • the high-order topological insulator layer 20 has a second region 22 on the Y1 side from the first groove 51 and on the X2 side from the second groove 52.
  • the higher-order topological insulator layer 20 has a third region 23 on the Y1 side from the third groove 53 and on the X1 side from the second groove 52.
  • the first region 21, the second region 22, and the third region 23 each include a hinge helical channel on one of two intersection lines of a plane perpendicular to the a-axis direction and a plane perpendicular to the c-axis direction.
  • the hinge helical channel is parallel to the b-axis direction.
  • the first region 21 includes the first hinge helical channel 11 at the intersection line (ridgeline) between the top surface and the side surface on the Y1 side.
  • the second region 22 includes a second hinge helical channel 12 at the intersection of the Y2 side surface and the bottom surface of the first groove 51 .
  • the third region 23 includes the third hinge helical channel 13 at the intersection of the Y2 side surface and the bottom surface of the third groove 53.
  • the first hinge helical channel 11 is located on the intersection line between the Y1 side surface of the first region 21 and the bottom surface of the groove 50
  • the second hinge helical channel 12 is located on the intersection line between the top surface of the second region 22 and the Y2 side surface.
  • the third hinge helical channel 13 may be located at the intersection line between the upper surface of the third region 23 and the side surface on the Y2 side.
  • the first ferromagnetic insulator layer 31 is provided on the first region 21 , the second region 22 and a portion of the groove 50 , and covers a portion of the first hinge helical channel 11 and the second hinge helical channel 12 . cover.
  • the second ferromagnetic insulator layer 32 is provided on the second region 22 , the third region 23 and a portion of the groove 50 , and covers a portion of the second hinge helical channel 12 and the third hinge helical channel 13 . cover.
  • the third ferromagnetic insulator layer 33 is provided on the third region 23 , the first region 21 and a portion of the groove 50 , and covers a portion of the third hinge helical channel 13 and the first hinge helical channel 11 . cover.
  • Examples of the material for the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 include Cr 2 Ga 2 Te 6 .
  • the materials of the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 may be other diluted magnetic semiconductors.
  • the thickness of the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 is, for example, about 30 nm.
  • the second ferromagnetic insulator layer 32 is separated from the first ferromagnetic insulator layer 31 on the second hinge helical channel 12 toward the X1 side in the X1-X2 direction.
  • the third ferromagnetic insulator layer 33 is spaced apart from the second ferromagnetic insulator layer 32 toward the X1 side on the third hinge helical channel 13 in the X1-X2 direction.
  • the third ferromagnetic insulator layer 33 is separated from the first ferromagnetic insulator layer 31 on the first hinge helical channel 11 toward the X1 side in the X1-X2 direction.
  • the first gate electrode 41 is provided on the first ferromagnetic insulator layer 31.
  • the second gate electrode 42 is provided on the second ferromagnetic insulator layer 32 .
  • the third gate electrode 43 is provided on the third ferromagnetic insulator layer 33.
  • Au can be used as a material for the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43.
  • the thickness of the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 is, for example, about 50 nm.
  • the first SQUID 61 includes a lower superconductor layer 61A, a lower superconductor layer 61B, a tunnel barrier layer 61C, and an upper superconductor layer 61D.
  • the lower superconductor layer 61A and the lower superconductor layer 61B protrude from the side surface of the s-wave superconductor layer 10 on the X2 side toward the X2 side.
  • the lower superconductor layer 61A is located closer to Y2 than the lower superconductor layer 61B.
  • the lower superconductor layer 61A protrudes from the first region 21 toward the X2 side
  • the lower superconductor layer 61B protrudes from the second region 22 toward the X2 side.
  • the lower superconductor layer 61A and the lower superconductor layer 61B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10.
  • the lower superconductor layer 61A and the lower superconductor layer 61B are connected to the s-wave superconductor layer 10.
  • the lower superconductor layer 61A and the lower superconductor layer 61B are, for example, Nb layers with a thickness of about 40 nm.
  • the tunnel barrier layer 61C and the upper superconductor layer 61D have a U-shaped planar shape.
  • Examples of the material for the tunnel barrier layer 61C include NbOx , and examples of the material for the upper superconductor layer 61D include Nb.
  • the thickness of the tunnel barrier layer 61C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 61D is, for example, about 40 nm.
  • One end of the tunnel barrier layer 61C contacts the lower superconductor layer 61A, and the other end contacts the lower superconductor layer 61B.
  • Upper superconductor layer 61D is provided on tunnel barrier layer 61C.
  • a tunnel barrier layer 61C is sandwiched between the lower superconductor layer 61A and the upper superconductor layer 61D, and between the lower superconductor layer 61B and the upper superconductor layer 61D.
  • the first SQUID 61 is constituted by such a Josephson junction.
  • the first SQUID 61 detects changes in magnetic flux between the first hinge helical channel 11 and the second hinge helical channel 12.
  • the second SQUID 62 includes a lower superconductor layer 62A, a lower superconductor layer 62B, a tunnel barrier layer 62C, and an upper superconductor layer 62D.
  • the lower superconductor layer 62A and the lower superconductor layer 62B protrude from the side surface of the s-wave superconductor layer 10 on the Y1 side toward the Y1 side.
  • the lower superconductor layer 62A is located closer to the X2 side than the lower superconductor layer 62B.
  • the lower superconductor layer 62A protrudes from the second region 22 toward the Y1 side
  • the lower superconductor layer 62B protrudes from the third region 23 toward the Y1 side.
  • the lower superconductor layer 62A and the lower superconductor layer 62B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10.
  • the lower superconductor layer 62A and the lower superconductor layer 62B are connected to the s-wave superconductor layer 10.
  • the lower superconductor layer 62A and the lower superconductor layer 62B are, for example, Nb layers with a thickness of about 40 nm.
  • the tunnel barrier layer 62C and the upper superconductor layer 62D have a U-shaped planar shape.
  • Examples of the material for the tunnel barrier layer 62C include NbOx , and examples of the material for the upper superconductor layer 62D include Nb.
  • the thickness of the tunnel barrier layer 62C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 62D is, for example, about 40 nm.
  • One end of the tunnel barrier layer 62C contacts the lower superconductor layer 62A, and the other end contacts the lower superconductor layer 62B.
  • Upper superconductor layer 62D is provided on tunnel barrier layer 62C.
  • a tunnel barrier layer 62C is sandwiched between the lower superconductor layer 62A and the upper superconductor layer 62D, and between the lower superconductor layer 62B and the upper superconductor layer 62D.
  • the second SQUID 62 is constituted by such a Josephson junction.
  • the second SQUID 62 detects changes in magnetic flux between the second hinge helical channel 12 and the third hinge helical channel 13.
  • the third SQUID 63 includes a lower superconductor layer 63A, a lower superconductor layer 63B, a tunnel barrier layer 63C, and an upper superconductor layer 63D.
  • the lower superconductor layer 63A and the lower superconductor layer 63B protrude from the side surface of the s-wave superconductor layer 10 on the X1 side toward the X1 side.
  • the lower superconductor layer 63A is located closer to Y1 than the lower superconductor layer 63B.
  • the lower superconductor layer 63A protrudes from the third region 23 toward the X1 side
  • the lower superconductor layer 63B protrudes from the first region 21 toward the X1 side.
  • the lower superconductor layer 63A and the lower superconductor layer 63B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10.
  • the lower superconductor layer 63A and the lower superconductor layer 63B are connected to the s-wave superconductor layer 10.
  • the lower superconductor layer 63A and the lower superconductor layer 63B are, for example, Nb layers with a thickness of about 40 nm.
  • the tunnel barrier layer 63C and the upper superconductor layer 63D have a U-shaped planar shape.
  • Examples of the material for the tunnel barrier layer 63C include NbOx , and examples of the material for the upper superconductor layer 63D include Nb.
  • the thickness of the tunnel barrier layer 63C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 63D is, for example, about 40 nm.
  • One end of the tunnel barrier layer 63C contacts the lower superconductor layer 63A, and the other end contacts the lower superconductor layer 63B.
  • Upper superconductor layer 63D is provided on tunnel barrier layer 63C.
  • a tunnel barrier layer 63C is sandwiched between the lower superconductor layer 63A and the upper superconductor layer 63D, and between the lower superconductor layer 63B and the upper superconductor layer 63D.
  • the third SQUID 63 is constituted by such a Josephson junction.
  • the third SQUID 63 detects changes in magnetic flux between the third hinge helical channel 13 and the first hinge helical channel 11.
  • Majorana particles ⁇ 1, ⁇ 2, ⁇ 3, and ⁇ 4 are expressed.
  • Majorana particles ⁇ 1 are stably expressed near the first gate electrode 41 of the first hinge helical channel 11
  • Majorana particles ⁇ 4 are stably expressed near the third gate electrode 43 of the first hinge helical channel 11. It appears.
  • Majorana particles ⁇ 2 are stably expressed between the first gate electrode 41 and the second gate electrode 42 of the second hinge helical channel 12
  • Majorana particles ⁇ 3 are stably expressed between the first gate electrode 41 and the second gate electrode 42 of the second hinge helical channel 13. It is stably expressed between the second gate electrode 42 and the third gate electrode 43.
  • the Majorana particles ⁇ 1 to ⁇ 4 are exchanged by changing the electrostatic potential due to the application of gate voltage to the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43.
  • a single layer film of WTe 2 which is a layered material of transition metal dichalcogenide, is easily oxidized and its properties change when exposed to the atmosphere. It is possible to suppress oxidation by sandwiching a single layer of WTe2 between chemically stable substances such as hexagonal boron nitride (h-BN) or graphene, but in that case, it is difficult to manufacture the quantum bit. The process becomes complicated. Furthermore, it is difficult to adjust the size of the WTe 2 single layer film. On the other hand, in this embodiment, since the higher-order topological insulator layer 20 including a multilayer film such as WTe 2 is used, a structure for suppressing oxidation is not required. Furthermore, adjusting the size of the higher-order topological insulator layer 20 is easier than adjusting the size of a single layer film of WTe2 .
  • 14 to 19 are top views showing a method for manufacturing the quantum bit 1 according to the second embodiment.
  • 20 to 25 are cross-sectional views showing a method for manufacturing the quantum bit 1 according to the second embodiment.
  • FIGS. 14 and 20 a substrate 90 is prepared, and the substrate 90 is annealed at approximately 1200° C. for 3 to 4 hours in an oxygen atmosphere at atmospheric pressure. Next, the substrate 90 is immersed in methanol for 20 to 30 minutes and rinsed with ultrapure water. These treatments can improve the flatness of the surface of the substrate 90.
  • FIG. 20 corresponds to a cross-sectional view taken along line XX-XX in FIG. 14.
  • an s-wave superconductor layer 19 is formed on the substrate 90, a first transition metal dichalcogenide layer 79 is formed on the s-wave superconductor layer 19, and a high-order A topological insulator layer 29 is formed.
  • an Nb layer is formed as the s-wave superconductor layer 19
  • two NbTe layers are formed as the first transition metal dichalcogenide layer 79
  • a multilayer film of WTe2 is formed as the higher-order topological insulator layer 29.
  • the s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29 are the s-wave superconductor layer 120, the first transition metal dichalcogenide layer 130, and the first transition metal dichalcogenide layer 130 in the first embodiment, respectively. It can be formed by the same method as the second transition metal dichalcogenide layer 140.
  • the s-wave superconductor layer 19 After forming the higher-order topological insulator layer 29, as shown in FIGS. 15 and 21, the s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29 are processed, From the s-wave superconductor layer 19, the s-wave superconductor layer 10, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A and a lower superconductor layer 63B are formed.
  • FIG. 21 corresponds to a cross-sectional view taken along line XXI-XXI in FIG. 15.
  • a first electron beam resist is spun on the higher-order topological insulator layer 29. coat.
  • a first mask pattern is formed from the first electron beam resist by electron beam lithography.
  • the first mask pattern includes the s-wave superconductor layer 19, the s-wave superconductor layer 10, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, and the lower superconductor layer 62B.
  • the portions where the lower superconductor layer 63A and the lower superconductor layer 63B are to be formed are covered from above the higher-order topological insulator layer 29, and the other portions are exposed.
  • the first electron beam resist for example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used.
  • the s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29 are processed by Ar ion milling.
  • Ar ion milling for example, the beam acceleration voltage is 280V and the beam current is 150mA.
  • FIG. 22 corresponds to a cross-sectional view taken along line XXII-XXII in FIG. 16.
  • a second electron beam resist is spin-coated on the higher-order topological insulator layer 29 and the substrate 90.
  • a second mask pattern is formed from the second electron beam resist by electron beam lithography.
  • the second mask pattern covers a portion of the high-order topological insulator layer 29 on the s-wave superconductor layer 10, and includes a lower superconductor layer 61A, a lower superconductor layer 61B, a lower superconductor layer 62A, and a lower superconductor layer 61B.
  • the second electron beam resist for example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used.
  • the higher-order topological insulator layer 29 and the first transition metal dichalcogenide layer 79 are processed by Ar ion milling.
  • the higher-order topological insulator layer 29A and the transition metal dichalcogenide layer 70 are formed, and the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, and the lower Superconductor layer 63A and lower superconductor layer 63B are exposed from higher-order topological insulator layer 29A and transition metal dichalcogenide layer 70.
  • the beam acceleration voltage is 280V and the beam current is 150mA.
  • FIG. 23 corresponds to a cross-sectional view taken along line XXIII-XXIII in FIG. 17.
  • the higher-order topological insulator layer 29A When processing the higher-order topological insulator layer 29A, first, the higher-order topological insulator layer 29A, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower A third electron beam resist is spin-coated on the conductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. Next, a third mask pattern is formed from the third electron beam resist by electron beam lithography. The third mask pattern exposes a portion of the high-order topological insulator layer 29A where the groove 50 is to be formed and covers the other portion.
  • the third electron beam resist for example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used.
  • the higher-order topological insulator layer 29A is processed by Ar ion milling. As a result, a groove 50 including a first groove 51, a second groove 52, and a third groove 53 is formed, and a high-order topological insulator layer 20 including a first region 21, a second region 22, and a third region 23 is formed. is obtained.
  • the first region 21 comprises a first hinge helical channel 11
  • the second region 22 comprises a second hinge helical channel 12
  • the third region 23 comprises a third hinge helical channel 13 (see FIG. 13).
  • the beam acceleration voltage is 280V and the beam current is 150mA.
  • FIG. 24 corresponds to a cross-sectional view taken along line XXIV-XXIV in FIG. 18.
  • the first ferromagnetic insulator layer 31 When forming the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43, , First, the higher-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower A fourth electron beam resist is spin-coated on the superconductor layer 63B. Next, a fourth mask pattern is formed from the fourth electron beam resist by electron beam lithography.
  • the fourth mask pattern includes a first ferromagnetic insulator layer 31, a second ferromagnetic insulator layer 32, a third ferromagnetic insulator layer 33, a first gate electrode 41, a second gate electrode 42, and a third gate electrode 43. Expose the part that will be formed and cover the other parts.
  • the fourth electron beam resist for example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used.
  • ZEP 520A manufactured by Zeon Corporation
  • ZEP-A manufactured by Zeon Corporation
  • the temperature of the substrate 90 is maintained at 200° C.
  • the laser energy density is 1.0 J/cm 2 to 2.0 J/cm 2
  • the irradiation frequency is is 1 Hz
  • the distance between the substrate 90 and the target is approximately 5 cm
  • the film formation rate is 1.0 nm/min to 2.0 nm/min.
  • the temperature of the substrate 90 is maintained at room temperature
  • the laser energy density is 1.0 J/cm 2 to 2.0 J/cm 2
  • the irradiation frequency is 5 Hz
  • the temperature of the substrate 90 is maintained at room temperature.
  • the distance to the target is approximately 5 cm
  • the film formation rate is 5.0 nm/min to 10.0 nm/min.
  • the fourth mask pattern is removed together with the Cr 2 Ga 2 Te 6 layer and the Au layer deposited thereon. In other words, perform liftoff.
  • the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are obtained.
  • four Majorana particles ⁇ 1, ⁇ 2, ⁇ 3 and ⁇ 4 are expressed.
  • FIG. 25 corresponds to a cross-sectional view taken along line XXV-XXV in FIG. 19.
  • the tunnel barrier layers 61C to 63C and the upper superconductor layers 61D to 63D first, the higher-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, and the lower
  • the fifth electron is formed on the superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, the lower superconductor layer 63B, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43.
  • a fifth mask pattern is formed from the fifth electron beam resist by electron beam lithography.
  • the fifth mask pattern exposes the portions where the tunnel barrier layers 61C to 63C and the upper superconductor layers 61D to 63D are to be formed, and covers the other portions.
  • the fifth electron beam resist for example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used.
  • an NbO x layer and a Nb layer are formed by a PLD method.
  • the temperature of the substrate 90 is maintained at room temperature, and the oxygen partial pressure in the vacuum chamber is adjusted to about 50 Pa to 55 Pa.
  • the Nb layer can be formed under the same conditions as the s-wave superconductor layer 19.
  • the fifth mask pattern is removed together with the NbO x layer and the Nb layer deposited thereon. In other words, perform liftoff.
  • tunnel barrier layers 61C to 63C and upper superconductor layers 61D to 63D are obtained, and a first SQUID 61, a second SQUID 62, and a third SQUID 63 are formed.
  • the quantum bit 1 according to the second embodiment can be manufactured.
  • the material of the s-wave superconductor layer is not limited to Nb.
  • the material of the s-wave superconductor layer may be Pb.
  • the material of the chalcogen layer is not limited to Te.
  • the material of the chalcogen layer may be S or Se.
  • the material of the chalcogen layer may be the same type of chalcogen element contained in the second transition metal dichalcogenide layer.
  • the material of the metal layer is not limited to Nb.
  • the material of the metal layer may be Pb.
  • the first transition metal dichalcogenide layer is likely to contain only one type of transition metal dichalcogenide.
  • the first transition metal dichalcogenide layer may contain two or more types of transition metal dichalcogenides. . Even if the first transition metal dichalcogenide layer contains two or more types of transition metal dichalcogenides, good crystallinity can be obtained in the second transition metal dichalcogenide layer.
  • the chalcogen element contained in the first transition metal dichalcogenide layer and the chalcogen element contained in the second transition metal dichalcogenide layer may be of the same type.
  • the material of the second transition metal dichalcogenide layer (including the higher-order topological insulator layer) is not limited to WTe2 .
  • the second transition metal dichalcogenide layer may include Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir or Pt or any combination thereof as a transition metal.
  • the layered material contained in the second transition metal dichalcogenide layer may be a single layer.
  • FIG. 26 is a diagram showing a quantum computing device according to the third embodiment.
  • the quantum computing device 2 includes a quantum bit chip 81, a signal generator 82, a signal demodulator 83, and a cryogenic dilution refrigerator 84.
  • the quantum bit chip 81 includes a plurality of quantum bits 1 according to the second embodiment.
  • the quantum bit chip 81 is housed in a cryogenic dilution refrigerator 84 and cooled to a temperature of 10 mK or less.
  • a signal generator 82 generates a microwave pulse signal, and the microwave pulse signal is input to the quantum bit chip 81 .
  • the quantum bit chip 81 outputs a signal according to the microwave pulse signal, and the signal demodulator 83 demodulates the signal output from the quantum bit chip 81.
  • the signal generator 82 and signal demodulator 83 are used, for example, at a temperature around room temperature.
  • the quantum calculation device 2 according to the third embodiment includes the quantum bit 1 according to the second embodiment, Majorana particles can be stably expressed and stable calculations can be performed.
  • Quantum operation device 10 S-wave superconductor layer 11: First hinge helical channel 12: Second hinge helical channel 13: Third hinge helical channel 20: Higher order topological insulator layer 21: First Region 22: Second region 23: Third region 31: First ferromagnetic insulator layer 32: Second ferromagnetic insulator layer 33: Third ferromagnetic insulator layer 41: First gate electrode 42: Second gate electrode 43: Third gate electrode 50: Groove 51: First groove 52: Second groove 53: Third groove 61: First SQUID 62: 2nd SQUID 63: 3rd SQUID 70: Transition metal dichalcogenide layer 100: Structure 110: Substrate 120: S-wave superconductor layer 130: First transition metal dichalcogenide layer 131: Chalcogen layer 132: Metal layer 140: Second transition metal dichalcogenide layer

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013247267A (ja) * 2012-05-28 2013-12-09 National Institute For Materials Science 縁マヨラナフェルミ粒子を使用したトポロジカル量子計算用デバイスユニット、及びその操作方法、並びにトポロジカル量子計算用デバイス、及びその操作方法
WO2018171823A1 (de) * 2017-03-20 2018-09-27 Forschungszentrum Jülich GmbH Verfahren zur in-situ herstellung von "majorana-materialien - supraleiter" hybridnetzwerken, sowie eine durch das verfahren hergestellte hybridstruktur
JP2020096107A (ja) * 2018-12-13 2020-06-18 株式会社日立製作所 量子ビット及びその制御方法
WO2022137421A1 (ja) * 2020-12-24 2022-06-30 富士通株式会社 量子ビット回路、量子コンピュータ及び量子ビット回路の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013247267A (ja) * 2012-05-28 2013-12-09 National Institute For Materials Science 縁マヨラナフェルミ粒子を使用したトポロジカル量子計算用デバイスユニット、及びその操作方法、並びにトポロジカル量子計算用デバイス、及びその操作方法
WO2018171823A1 (de) * 2017-03-20 2018-09-27 Forschungszentrum Jülich GmbH Verfahren zur in-situ herstellung von "majorana-materialien - supraleiter" hybridnetzwerken, sowie eine durch das verfahren hergestellte hybridstruktur
JP2020096107A (ja) * 2018-12-13 2020-06-18 株式会社日立製作所 量子ビット及びその制御方法
WO2022137421A1 (ja) * 2020-12-24 2022-06-30 富士通株式会社 量子ビット回路、量子コンピュータ及び量子ビット回路の製造方法

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