WO2024022058A1 - 显示面板以及显示装置 - Google Patents

显示面板以及显示装置 Download PDF

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Publication number
WO2024022058A1
WO2024022058A1 PCT/CN2023/105837 CN2023105837W WO2024022058A1 WO 2024022058 A1 WO2024022058 A1 WO 2024022058A1 CN 2023105837 W CN2023105837 W CN 2023105837W WO 2024022058 A1 WO2024022058 A1 WO 2024022058A1
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WO
WIPO (PCT)
Prior art keywords
light
emitting device
layer
electrode
pixel
Prior art date
Application number
PCT/CN2023/105837
Other languages
English (en)
French (fr)
Inventor
叶超
魏小丹
何宝生
杨堂
王霄熠
刘沛
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024022058A1 publication Critical patent/WO2024022058A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/128—Active-matrix OLED [AMOLED] displays comprising two independent displays, e.g. for emitting information from two major sides of the display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a display panel and a display device.
  • display panels are mainly single panels.
  • display panels are mainly single panels.
  • the traditional technical solution is to use a liquid crystal display (LCD) panel in one case. Since no light source can be placed on both sides of the panel, ambient light can only be used as the light source, causing the display The brightness of the panel is limited. Therefore, two independent LCD panels are usually used to achieve double-sided display. However, in this case, to ensure that the two LCD panels display the same picture, a more complex connection and driving relationship is required, which greatly increases the production cost of the display panel and increases the thickness of the display panel, which is not in line with the trend of thinner and lighter display panels. design.
  • LCD liquid crystal display
  • OLED organic electroluminescence display Due to its self-luminous characteristics, it can solve the problem of limited luminous brightness of LCD panels. However, to achieve double-sided display using OLED, it is still necessary to prepare two OLED panels separately and then fit them together, which is not conducive to achieving thinness and thinness and the preparation cost of the product is high.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a display panel and a display device.
  • an embodiment of the present disclosure provides a display panel, which includes a base substrate and a plurality of pixel unit groups disposed on the base substrate and arranged in an array.
  • Each of the pixel unit groups includes A first pixel unit and a second pixel unit provided on the base substrate; the first pixel unit includes a pixel drive circuit and a first light-emitting device electrically connected thereto, and the second pixel unit includes a second light-emitting device; in,
  • the second electrodes of each of the pixel driving circuits and each of the second light-emitting devices are connected to the same gate line;
  • each of the pixel driving circuits is connected to the same data line, and the first electrode of each of the second light-emitting devices is connected to the same data line.
  • the plurality of pixel unit groups arranged in an array include M rows and N columns of pixel unit groups; where M is a positive integer greater than or equal to 1, and N is a positive integer greater than or equal to 2. integer;
  • the pixel unit groups in N columns are arranged in sequence along the first direction, the N data lines are arranged in sequence along the first direction, and the pixel driving circuit in the i-th column is connected to the i-th data line; 0 ⁇ i ⁇ N, and i is a positive integer;
  • the first electrode of the second light-emitting device in the j-th column is connected to the (N-j+1)-th data line; 1 ⁇ j ⁇ N, and j is a positive integer.
  • the display panel further includes a connecting signal line
  • One of the data lines connected to the pixel driving circuit is connected to one of the connection signal lines, and the connection signal line passes through the wiring area and is connected to the first electrode of the second light-emitting device;
  • the display panel includes a driving circuit layer provided on the base substrate; the pixel driving circuit is located on the driving circuit layer;
  • the first light-emitting device is located on a side of the driving circuit layer facing away from the base substrate; the second light-emitting device is located on a side of the driving circuit layer close to the base substrate;
  • the orthographic projection of the first light-emitting device on the base substrate and/or the orthographic projection of the second light-emitting device on the base substrate are both consistent with the pixel drive Orthographic projections of the circuitry onto the base substrate at least partially overlap.
  • orthographic projections of any two of the first light-emitting device, the second light-emitting device and the pixel driving circuit on the base substrate overlap.
  • the pixel driving circuit includes a thin film transistor and a storage capacitor
  • the driving circuit layer includes a first semiconductor layer, a first conductive layer and a second conductive layer sequentially disposed on a side of the second light-emitting device facing away from the base substrate;
  • the active layer of the thin film transistor is located in the first semiconductor layer
  • the gate electrode of the thin film transistor, the first plate of the storage capacitor and the gate line are all located on the first conductive layer;
  • the source electrode and the drain electrode of the thin film transistor are both located on the second conductive layer.
  • the display panel further includes a buffer layer disposed on a side of the first semiconductor layer close to the base substrate, and a buffer layer disposed between the first semiconductor layer and the first conductive layer.
  • the second electrode of the second light-emitting device in the same pixel unit group is electrically connected to the gate line through a connection via hole; the connection via hole penetrates the second pixel definition layer and the buffer layer in sequence and the first insulating layer.
  • the display panel further includes a third conductive layer, a first pixel definition layer and a fourth conductive layer sequentially disposed on a side of the driving circuit layer facing away from the base substrate;
  • the first electrode of the first light-emitting device is located on the third conductive layer; the second electrode of the first light-emitting device is located on the fourth conductive layer; the first electrode of the first light-emitting device is a reflective electrode, The second electrode of the first light-emitting device is a transmission electrode;
  • the first evaporation layer of the first light-emitting device is located on the first pixel definition layer, and the orthographic projection of the second electrode of the first light-emitting device on the base substrate covers the first evaporation layer where Orthographic projection on the substrate.
  • the display panel further includes a fifth conductive layer, a second pixel definition layer and a sixth conductive layer sequentially disposed on a side of the driving circuit layer close to the base substrate;
  • the first electrode of the second light-emitting device is located on the fifth conductive layer; the second electrode of the second light-emitting device is located on the sixth conductive layer; the first electrode of the second light-emitting device is a reflective electrode, The second electrode of the second light-emitting device is a transmission electrode;
  • the second evaporation layer of the second light-emitting device is located on the second pixel definition layer, and the orthographic projection of the second electrode of the second light-emitting device on the base substrate covers the second evaporation layer where Orthographic projection on the substrate.
  • embodiments of the present disclosure also provide a display device, which includes any of the above display devices. panel.
  • Figure 1 is a schematic diagram of the connection structure between pixel units provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of a pixel unit group provided by an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of a connection structure between a first pixel unit and a second pixel unit provided by an embodiment of the present disclosure
  • Figure 4 is a circuit diagram of a double-sided display display panel provided by an embodiment of the present disclosure.
  • Figure 5 is a timing control principle diagram of a display panel provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • Figure 7a is a schematic diagram of the film structure of a display panel provided by an embodiment of the present disclosure.
  • Figure 7b is a film layer layout of a pixel driving circuit provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of the connection structure of a second electrode of a second light-emitting device provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of the film layer connection structure of the first pixel unit and the second pixel unit provided by an embodiment of the present disclosure.
  • the reference numbers are: display panel 100; substrate substrate 01; pixel unit group 10; first pixel unit 11; second pixel unit 12; pixel driving circuit 111; first light-emitting device OLED1; second light-emitting device OLED2; The first electrode 21 of the second light-emitting device; the second electrode 22 of the second light-emitting device; the second evaporation layer 23; the first electrode 31 of the first light-emitting device; the second electrode 32 of the first light-emitting device; the first evaporation layer 33 ; Switching thin film transistor T1; Driving thin film transistor T2; Gate 41 of the switching thin film transistor; Storage capacitor Cst; First plate Cst 1 of the storage capacitor; Second plate Cst 2 of the storage capacitor; Source 42 of the switching thin film transistor ; The drain electrode 43 of the switching thin film transistor; the active layer 44 of the switching thin film transistor; the gate electrode 51 of the driving thin film transistor; the source electrode 52 of the driving thin film transistor; the drain electrode 53 of the driving thin film transistor; the active
  • a plurality or several mentioned in this disclosure means two or more.
  • “And/or” describes the relationship between related objects, indicating that there can be three relationships. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character “/” generally indicates that the related objects are in an "or” relationship.
  • first direction X, the second direction Y and the third direction Z intersect in pairs.
  • first direction The first direction The first direction
  • a display panel that includes a plurality of pixel units arranged on a substrate and arranged in an array. Group. Each pixel unit group includes a first pixel unit and a second pixel unit disposed on the base substrate. The first pixel unit includes a pixel driving circuit and a first light-emitting device electrically connected thereto, and the second pixel unit includes a second light-emitting device.
  • the first light-emitting device and the second light-emitting device in this embodiment of the present disclosure are located For the same pixel unit group, there is no need to prepare two independent display panels and then laminated them together, which reduces the preparation cost and enables the display panel to be thinner and lighter.
  • each pixel driving circuit and the second electrode of each second light-emitting device are connected to the same gate line; for the pixel unit group located in the same column, each pixel driving circuit is connected to the same data line , the first electrodes of each second light-emitting device are connected to the same data line.
  • the pixel driving circuit is used to drive the first light-emitting device and the second light-emitting device in the display panel, so that the first light-emitting device and the second light-emitting device can emit light simultaneously, thereby realizing the display panel double-sided display.
  • a display module provided by an embodiment of the present disclosure will be described below with reference to the drawings in the embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of the connection structure between pixel units provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a pixel unit group provided by an embodiment of the present disclosure.
  • the display panel 100 includes a plurality of pixel unit groups 10 arranged on a base substrate 01 and arranged in an array.
  • Each pixel unit group 10 includes a first pixel unit 11 and a second pixel unit 12 provided on the base substrate 01 .
  • the first pixel unit 11 includes a pixel driving circuit 111 and the first light-emitting device OLED1 electrically connected thereto, the second pixel unit 12 includes the second light-emitting device OLED2.
  • the pixel driving circuit 111 is used to drive the first light-emitting device OLED1 to emit light.
  • the first light-emitting device OLED1 can realize front light emission of the display panel 100
  • the second light-emitting device OLED2 can realize back light emission of the display panel 100 .
  • the second electrodes 22 of each pixel driving circuit 111 and each second light-emitting device 112 are connected to the same gate line G. While driving the first light-emitting device OLED1 to emit light, the pixel driving circuit 111 can transmit signals to the second electrodes 22 of each second light-emitting device OLED2 connected thereto through the connected gate line G.
  • each pixel driving circuit 111 is connected to the same data line S, and the first electrode 21 of each second light-emitting device OLED2 is connected to the same data line S.
  • each pixel driving circuit 111 is connected to the same data line S, and the data line S may be connected to the third light-emitting device OLED2 of each second light-emitting device OLED2 located in the pixel unit group 10 located in the same column.
  • One electrode 21 is connected; alternatively, the data line S can also be connected to the first electrode 21 of each second light-emitting device OLED2 located in the pixel unit group 10 of different columns, and can be set according to the actual situation.
  • the pixel driving circuits 111 of multiple columns may be connected to the same data line S, or the pixel driving circuits 111 of each column may be connected to different data lines S.
  • the substrate substrate 01 of the present disclosure may be a flexible substrate prepared from a transparent material and capable of transmitting the light generated by the light-emitting device to the external environment.
  • different columns of pixel driving circuits 111 are connected to different data lines S.
  • the connection mode between the data lines S corresponding to the first pixel unit 11 and the second pixel unit 12 can be set according to the number of columns of the pixel unit groups 10 in the plurality of pixel unit groups 10 arranged in an array.
  • multiple pixel unit groups 10 arranged in an array include M rows and N columns of pixel unit groups 10; where M is greater than or equal to A positive integer of 1, N is a positive integer greater than or equal to 2.
  • N columns of pixel unit groups 10 are sequentially arranged along the first direction X, N data lines S are sequentially arranged along the first direction X, and the i-th column pixel driving circuit 111 is connected to the i-th data line S, that is Each column of pixel driving circuits 111 has data lines S connected in one-to-one correspondence. 0 ⁇ i ⁇ N, and i is a positive integer.
  • the first electrode 21 of the second light emitting device OLED2 in the jth column is connected to the (N-j+1)th data line S; 1 ⁇ j ⁇ N, j is a positive integer.
  • the first column pixel driving circuit 111 is connected to the first data line S1, and the first data line S1 is connected to the fourth column second light-emitting device OLED2
  • the first electrodes 21 are connected, that is, the pixel driving circuits 111 in the first column and the first electrodes 21 of the second light-emitting devices OLED2 in the fourth column are electrically connected through a data line (ie, the first data line S1).
  • each pixel driving circuit 111 in the second column and the first electrode 21 of each second light-emitting device OLED2 in the third column are electrically connected through the second data line S2.
  • Each pixel driving circuit 111 in the third column and the first electrode 21 of each second light-emitting device OLED2 in the second column are electrically connected through the third data line S3.
  • Each pixel driving circuit 111 in the fourth column and the first electrode 21 of each second light-emitting device OLED2 in the first column are electrically connected through the fourth data line S4.
  • M rows of pixel unit groups 10 are sequentially arranged along the second direction Y, M gate lines G are sequentially arranged along the second direction Y, and the k-th row pixel driving circuit 111 and the k-th gate Lines G are connected, that is, each row of pixel driving circuits 111 has gate lines G connected in one-to-one correspondence. 0 ⁇ k ⁇ M, and k is a positive integer.
  • the pixel unit group 10 located in the same row, each pixel driving circuit 111 and the second electrode 22 of each second light-emitting device OLED2 are connected to the same gate line G.
  • the display panel 100 of the present disclosure includes a display area DA (Display Area) and a peripheral area PA (Peripheral Area) arranged around the display area, wherein the pixel driving circuit is arranged in the display area DA,
  • the gate integrated driving circuit (Gate On Array, GOA) and the source driving chip (Chip, IC) are set in the peripheral area PA.
  • the GOA can provide gate driving signals to the first pixel units of each row through the gate lines.
  • the source driving chip IC Data signals may be provided to the first pixel units and the second pixel units of each column through data lines.
  • FIG. 3 is a schematic diagram of a connection structure between a first pixel unit and a second pixel unit provided by an embodiment of the present disclosure.
  • the display panel 100 also includes a connection signal line Y; a data line connected to the pixel driving circuit 111
  • the line S is connected to a connection signal line Y, which passes through the wiring area and is connected to the first electrode 21 of the second light-emitting device OLED2; the orthographic projection of each connection signal line Y on the substrate 01 does not overlap.
  • the first electrode 21 of the second light-emitting device OLED2 in the j-th column is connected to the (N-j+1)-th data line S.
  • connection signal line Y By arranging the connection signal line Y in the wiring area, the embodiment of the present disclosure can avoid the overlap of wiring connected between the data lines S, thereby reducing the interference of data signal transmission between the data lines S, improving the stability of the driving circuit, and thereby increasing the luminous brightness. consistency.
  • connection signal line Y and the data line S may have an integrated structure, that is, the connection signal line Y is the data line located in the wiring area.
  • the first data line S1 connects each pixel driving circuit 111 in the first column, and then passes through the wiring area (that is, through the first connection signal line Y1) , connecting the first electrodes 21 of each second light-emitting device OLED2 in the fourth column.
  • the connection structures of the other data lines S2, S3 and S4 are the same as those of the above-mentioned S1, and the embodiments of this disclosure will not be listed one by one.
  • Figure 4 is a circuit diagram of a double-sided display display panel provided by an embodiment of the present disclosure. As shown in Figure 4, it only shows the second row and second column, the second row and third column, and the third column in Figure 3. Circuit diagrams of the four pixel unit groups 10 corresponding to the second row and the third row and the third column. Taking the pixel driving circuit 111 as a 2T1C structure (ie, two thin film transistors and one capacitor) as an example, the gate line G2 in the third row is connected to the gate of the switching thin film transistor T1 in each first pixel unit 11 in the third row. 41 is electrically connected to the second electrode 22 (that is, the cathode) of the second light-emitting device OLED2 in each second pixel unit 12 of the third row.
  • the second electrode 22 that is, the cathode
  • the second data line S2 is electrically connected to the source electrode 42 of the switching thin film transistor T1 in the first pixel unit 11 in the second column, and passes through the wiring area to the first electrode of the second light-emitting device OLED2 in the third column. 12 (i.e. the anode) is electrically connected.
  • the gate line G2 connects the gate electrode 41 of the switching thin film transistor T1 in the first pixel unit A and the cathode 22 of the second light-emitting device OLED2 in the second pixel unit B'.
  • the data line S2 connects the source electrode 42 of the switching thin film transistor T1 in the first pixel unit A and the anode 21 of the second light emitting device OLED2 in the second pixel unit B'.
  • a pixel driving circuit with a 2T1C structure in which the first pixel unit 11 includes a switching thin film transistor T1 for switching control and a driving thin film transistor T2 for pixel driving.
  • the drain 43 of the switching thin film transistor T1 is electrically connected to the gate 51 of the driving thin film transistor T2 and the first plate Cst 1 of the storage capacitor Cst; the source 52 of the driving thin film transistor T2 is electrically connected to the first power signal line Vdd;
  • the drain electrode 53 of the driving thin film transistor T2 is electrically connected to the first electrode 31 (that is, the anode) of the first light-emitting device OLED1; the second electrode 32 (that is, the cathode) of the first light-emitting device OLED1 and the second electrode of the storage capacitor Cst
  • the board Cst 2 is electrically connected to the second power signal line Vss respectively.
  • FIG. 5 is a timing control principle diagram of a display panel provided by an embodiment of the present disclosure.
  • GOA scans rows by controlling gate lines.
  • each pixel driving circuit 111 in the first row is provided with a voltage signal pulse (i.e., gate driving signal);
  • each pixel driving circuit 111 in the second row is provided with a voltage signal pulse (i.e., gate driving signal).
  • gate drive signal the third time t3 provides a voltage signal pulse (that is, the gate drive signal) to each pixel drive circuit 111 of the third row;
  • the fourth time t4 provides each pixel drive circuit 111 of the fourth row.
  • a voltage signal pulse (ie, gate drive signal).
  • the above-mentioned voltage signal pulse can use either a low-potential signal or a high-potential signal, and can be set according to the actual situation.
  • the embodiments of the present disclosure are explained by taking the actual use of low-potential signals as an example.
  • the IC provides a voltage pulse signal (that is, a data signal) to the pixel driving circuit 111 of the first column at a certain time, such as time t2, by controlling the data line S of each column.
  • a voltage pulse signal that is, a data signal
  • the gate line G2 of the second row and the first data line S1 have voltage pulses at the same time
  • the pixel driving circuit 111 corresponding to the second row and the first column has gate driving signals and data signals at the same time, so that The first electrode 31 of the first light-emitting device OLED1 in the second row and the first column is at a high potential, thereby driving the first light-emitting device to emit light OLED1.
  • the gate line G2 of the second row and the first data line S1 have voltage pulses at the same time.
  • the gate line G2 of the second row corresponds to the second light-emitting device OLED2 of the second row and the fourth column.
  • the second electrode 22 provides voltage
  • the first data line S1 provides voltage to the first electrode 21 of the second light-emitting device OLED2 in the second row and fourth column.
  • the first electrode 21 and the second electrode 22 form a voltage difference, thereby driving the second light-emitting devices OLED2 in the second row and the fourth column to emit light.
  • second The data signal timing of the first light-emitting device OLED1 in the first row and the first column and the second light-emitting device OLED2 in the second row and the fourth column are consistent, enabling synchronous light emission and the same display screen.
  • the IC provides a voltage pulse signal (data signal) to the pixel driving circuit 111 of the fourth column at a certain time, such as time t4, by controlling the data lines of each column.
  • the gate line G4 of the fourth row and the fourth data line S4 have voltage pulses at the same time
  • the pixel driving circuit 111 corresponding to the fourth row and the fourth column has gate driving signals and data signals at the same time, so that The first electrode 31 of the first light-emitting device OLED1 in the fourth row and fourth column is at a high potential, thereby driving the first light-emitting device OLED1 to emit light.
  • the gate line G4 of the fourth row and the fourth data line S4 have voltage pulses at the same time.
  • the gate line G4 of the fourth row corresponds to the second light-emitting device OLED2 of the fourth row and the first column.
  • the second electrode 22 provides a voltage
  • the fourth data line S4 provides a voltage corresponding to the first electrode 21 of the second light-emitting device OLED2 in the fourth row and the first column.
  • the first electrode 21 and the second electrode 22 form a voltage difference, thereby driving the second light-emitting device OLED2 in the fourth row and the first column to emit light.
  • the data signal timing of the first light-emitting device OLED1 in the fourth row and the fourth column and the second light-emitting device OLED2 in the fourth row and the first column are consistent, enabling synchronous lighting and displaying the same screen.
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel 100 includes a driving circuit layer 02 disposed on the base substrate 01; the pixel driving circuit 111 is located on Driver circuit layer 02.
  • the first light-emitting device OLED1 is located on the side of the driving circuit layer 02 facing away from the base substrate 01; the second light-emitting device OLED2 is located on the side of the driving circuit layer 02 close to the base substrate 01.
  • double-sided display of the display panel 100 is achieved through the first light-emitting device OLED1 and the second light-emitting device OLED2 disposed on opposite sides of the driving circuit layer 02 .
  • the orthographic projection of the first light-emitting device OLED1 on the base substrate 01 and/or the orthographic projection of the second light-emitting device OLED2 on the base substrate 01 are both related to the pixel driving circuit.
  • the orthographic projection of 111 on the base substrate 01 at least partially overlaps. This method of overlapping the light-emitting device and the pixel driving circuit can reasonably utilize the thin film crystal in the pixel driving circuit.
  • the occupied area of the body tube is increased, thereby increasing the number of pixel units per unit area, thereby meeting the pixel requirements of the high-resolution (Pixels Per Inch, PPI) display panel 100 .
  • the orthographic projections of any two of the first light-emitting device OLED1, the second light-emitting device OLED2 and the pixel driving circuit 111 on the base substrate 01 overlap.
  • the pixel driving circuit 111 includes a thin film transistor and a storage capacitor Cst;
  • the driving circuit layer 02 includes a first semiconductor layer, a first conductive layer and a second conductive layer that are sequentially disposed on the side of the second light emitting device OLED2 facing away from the base substrate. layer;
  • the active layer of the thin film transistor is located on the first semiconductor layer;
  • the gate electrode of the thin film transistor, the first plate and the gate line of the storage capacitor are all located on the first conductive layer;
  • the source and drain electrodes of the thin film transistor are located on the second conductive layer. layer.
  • the pixel driving circuit may be a 2T1C structure, a 5T2C structure, a 6T1C structure, a 6T2C structure, a 7T1C structure, a 7T2C structure, or a 9T2C structure, etc., which are not limited in the embodiments of the present disclosure.
  • the following embodiments of the disclosure will only be described by taking the pixel driving circuit as a 2T1C structure as an example.
  • the thin film transistors include a switching thin film transistor T1 for switching control and a driving thin film transistor T2 for pixel driving.
  • Figure 7a is a schematic diagram of the film layer structure of a display panel provided by an embodiment of the present disclosure.
  • Figure 7b is a film layer layout of a pixel driving circuit provided by an embodiment of the present disclosure.
  • the switch film The active layer 44 of the transistor T1 and the active layer 54 of the driving thin film transistor T2 are both located on the first semiconductor layer; the gate electrode 41 of the switching thin film transistor T1 and the gate electrode 51 of the driving thin film transistor T2 are both located on the first conductive layer; the switching film The source electrode 42 and the drain electrode 43 of the transistor T1 and the source electrode 52 and the drain electrode 53 of the driving thin film transistor T2 are both located on the second conductive layer.
  • a first insulating layer 71 (that is, the first gate insulating layer GI1) is provided between the first semiconductor layer and the first conductive layer; between the first conductive layer and the second conductive layer and close to the first conductive layer
  • a second insulating layer 72 (that is, the second gate insulating layer GI2) is provided; an opening layer 73 is provided between the second insulating layer 72 and the second conductive layer; between the second conductive layer and the first light emitting device OLED1
  • a flat layer 74 is provided between them.
  • the source electrode 42 of the switching thin film transistor T1 is connected to the source electrode 44 of the active layer 44 of the switching thin film transistor T1 through the first connection via Via1 penetrating the opening layer 73, the first insulating layer 71 and the second insulating layer 72.
  • the drain electrode 43 of the switching thin film transistor T1 is electrically connected to the drain electrode 43 of the active layer 44 of the switching thin film transistor T1 through the second connection via Via2 that penetrates the opening layer 73, the first insulating layer 71 and the second insulating layer 72.
  • the source electrode 52 of the driving thin film transistor T2 is electrically connected to the source region of the active layer 54 of the driving thin film transistor T2 through the third connection via penetrating the opening layer 73, the first insulating layer 71 and the second insulating layer 72. Electrical connection; the drain electrode 53 of the driving thin film transistor T2 passes through the fourth connection via hole that penetrates the opening layer 73, the first insulating layer 71 and the second insulating layer 72, and is connected to the drain region of the active layer 54 of the driving thin film transistor T2. Electrical connection.
  • the first electrode 31 (ie, the anode) of the first light-emitting device OLED1 is electrically connected to the drain electrode 43 of the switching thin film transistor T1 through the fifth connection via Via5 that penetrates the planar layer 74 .
  • the drain 43 of the switching thin film transistor T1 or the gate 51 of the driving thin film transistor T2 is electrically connected to the first plate Cst 1 of the storage capacitor Cst through the sixth connection via Via6 penetrating the opening layer 73 and the second insulating layer 72 . connect.
  • the switching thin film transistor T1 and the driving thin film transistor T2 of the present disclosure may be P-type transistors or N-type transistors.
  • the embodiment of the present disclosure takes a P-type transistor as an example. That is to say, in the description of the present disclosure, the switching thin film transistor T1 and the driving thin film transistor T2 are The driving thin film transistors T2 are all P-type transistors. However, it should be understood that the thin film transistors in the embodiments of the present disclosure are not limited to P-type transistors. Those skilled in the art can also use N-type transistors according to actual needs to implement the functions of one or more thin film transistors in the embodiments of the present disclosure.
  • the display panel 100 further includes a buffer layer 75 disposed on the side of the first semiconductor layer close to the base substrate 01 , and a buffer layer 75 disposed between the first semiconductor layer and the first conductive layer. first insulating layer 71.
  • the buffer layer 75 can prevent or reduce the diffusion of metal atoms and/or impurities from the base substrate 01 into the first semiconductor layer.
  • the buffer layer 75 may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiON), and may be formed as a multi-layer or a single layer.
  • FIG. 8 is a schematic diagram of the connection structure of the second electrode of a second light-emitting device provided by an embodiment of the present disclosure. As shown in FIG.
  • the second light-emitting device in the same pixel unit group 10 Second electrode 22 of device OLED2 It is electrically connected to the gate electrode 41 of the switching thin film transistor T1 through the gate line G and through the connection via hole (ie, the seventh connection via hole Via7).
  • the gate electrodes 41 of each switching thin film transistor T1 in different pixel unit groups 10 in the same row are electrically connected through the gate line G.
  • the display panel 100 further includes a third conductive layer, a first pixel definition layer 77 and a fourth conductive layer sequentially disposed on the side of the driving circuit layer 02 facing away from the base substrate 01;
  • the light emitting device OLED1 includes a first electrode 31 , a second electrode 32 , and a first evaporated layer 33 sandwiched between the first electrode 31 and the second electrode 32 .
  • the first electrode 31 of the first light-emitting device OLED1 is located on the third conductive layer; the second electrode 32 of the first light-emitting device OLED1 is located on the fourth conductive layer; the first electrode 31 of the first light-emitting device OLED1 is a reflective electrode.
  • the second electrode 32 of OLED1 is a transmissive electrode.
  • the first evaporation layer 33 is located on the first pixel definition layer 77 , and the orthographic projection of the second electrode 32 of the first light-emitting device OLED1 on the base substrate 01 covers the orthographic projection of the first evaporation layer 33 on the base substrate 01 , so that The light emitted by the first evaporation layer 33 is transmitted through the transmission electrode 32 .
  • the first electrode is the anode and the second electrode is the cathode.
  • the transmissive electrode also known as the transparent cathode, can transmit the light emitted by the evaporated layer;
  • the reflective electrode also known as the reflective anode, can reflect the light emitted by the evaporated layer and reflect it out through the transparent cathode.
  • the source electrode 52 of the driving thin film transistor T2 is connected to the first power supply signal line Vdd and is loaded with voltage.
  • the active layer 44 of the switching thin film transistor T1 has a source region, a drain region, and a channel region sandwiched between the source region and the drain region.
  • the switching film When the gate electrode 41 of the switching thin film transistor T1 is at a low potential V negative , the switching film The channel region of the active layer 44 of the transistor T1 is turned on, that is, a carrier channel is formed; if the source 42 of the switching thin film transistor T1 is loaded with a high potential Vpositive , the data signal transmitted by the data line S passes through the channel region It is transmitted to the drain region of the switching thin film transistor T1, and then transmitted to the anode 31 of the first light emitting device OLED1 through the drain electrode 43 of the switching thin film transistor T1.
  • the anode 31 of the first light-emitting device OLED1 has a high potential V positive , and the potential of the cathode 32 of the first light-emitting device OLED1 is 0, acting on the first evaporated layer 33.
  • the first evaporated layer 33 emits light and is realized through the transparent cathode 32. Front light.
  • the voltage of the source 42 of the switching thin film transistor T1 is stored in the storage capacitor Cst, and the potential of the anode 31 of the first light-emitting device OLED1 is maintained, so that the first evaporated layer 33 can continue to emit light.
  • the display panel 100 further includes a fifth conductive layer, a second pixel definition layer 76 and a sixth conductive layer sequentially disposed on the side of the driving circuit layer 02 close to the base substrate 01;
  • the two light-emitting devices OLED2 include a first electrode 21, a second electrode 22, and a second evaporated layer 23 sandwiched between the first electrode and the second electrode.
  • the first electrode 21 of the second light-emitting device OLED2 is located on the fifth conductive layer; the second electrode 22 of the second light-emitting device OLED2 is located on the sixth conductive layer; the first electrode 21 of the second light-emitting device OLED2 is a reflective electrode.
  • the second electrode 22 of OLED2 is a transmission electrode; the second evaporation layer 23 is located on the second pixel definition layer 76, and the orthographic projection of the second electrode 22 of the second light-emitting device OLED2 on the base substrate 01 covers the second evaporation layer 23.
  • the orthographic projection on the base substrate 01 causes all the light emitted by the second evaporation layer 23 to be transmitted through the transmissive electrode 22 .
  • the luminescent material can be evaporated into the opening of the pixel definition layer to form an evaporated layer.
  • the evaporated layer contains three pixels of RGB (where R represents red, G represents green, and B represents blue). ).
  • the luminescent material has a certain luminescence threshold voltage V luminescence voltage .
  • the luminescence threshold voltage V luminescence voltage is designed such that V positive +
  • the source electrode 52 of the driving thin film transistor T2 is connected to the first power supply signal line Vdd and is loaded with voltage.
  • the active layer 44 of the switching thin film transistor T1 has a source region, a drain region, and a channel region sandwiched between the source region and the drain region.
  • the switching film When the gate electrode 41 of the switching thin film transistor T1 is at a low potential V negative , the switching film The channel region of the active layer 44 of the transistor T1 is turned on, that is, a carrier channel is formed; if the source 42 of the switching thin film transistor T1 is loaded with a high potential Vpositive , the data signal transmitted by the data line S passes through the channel region It is transmitted to the drain region of the switching thin film transistor T1, and then transmitted to the anode 31 of the first light emitting device OLED1 through the drain electrode 43 of the switching thin film transistor T1.
  • the anode 31 of the first light-emitting device OLED1 has a high potential V positive , and the potential of the cathode 32 of the first light-emitting device OLED1 is 0, acting on the first evaporated layer.
  • the first evaporated layer 33 emits light and realizes the front surface through the transparent cathode 32 sold out.
  • the gate 41 of the switching thin film transistor T1 is connected to the cathode 22 of the second light emitting device OLED2, the cathode 22 of the second light emitting device OLED2 is at a low potential V negative ; the data connected to the source 42 of the switching thin film transistor T1
  • the line S is electrically connected to the anode 21 of the second light-emitting device OLED2.
  • the anode 21 of the second light-emitting device OLED2 is located at the high potential Vpositive .
  • the second evaporation layer 23 emits light and passes through the transparent
  • the cathode 22 realizes light emission from the reverse side.
  • the first light emitting device OLED1 does not emit light.
  • the voltage of the electrodes on both sides of the second light-emitting device OLED3 is 0-V minus ⁇ V light-emitting voltage , so the second light-emitting device OLED2 does not emit light.
  • the first light emitting device OLED1 does not emit light.
  • the voltage of the electrodes on both sides of the second light-emitting device OLED2 is V + -0 ⁇ V light-emitting voltage , so the second light-emitting device OLED2 does not emit light.
  • the second light-emitting device OLED2 here may be located in the same pixel unit group 10 as the pixel driving circuit 111, or may be in other pixel unit groups 10 in the same row as the pixel driving circuit 111 and in different columns.
  • Figure 9 is a schematic diagram of the film layer connection structure of the first pixel unit and the second pixel unit provided by an embodiment of the present disclosure, wherein Figure 9 shows the first pixel unit A in the second row and second column shown in Figure 3 and part of the film layer of the second pixel unit B in the second row and third column.
  • the gate 41 of the switching transistor T1 of the first pixel unit A passes through the second gate line G2 and communicates with the second pixel unit B.
  • the reflective anode 21 of the second light-emitting device OLED2 of unit B is electrically connected; the source 42 of the switching thin film transistor T1 of the first pixel unit A is connected to the second light-emitting device OLED2 of the second pixel unit B through the second data line S2.
  • the transparent cathode 22 is electrically connected.
  • a spacer layer 78 is provided between the first pixel definition layer and the second electrode of the first light emitting device.
  • the spacer layer 78 can increase the path for external water vapor or oxygen to enter the display area DA, thereby protecting the light-emitting devices in the display area DA.
  • an encapsulation layer 79 is provided on a side of the first light emitting device facing away from the base substrate.
  • the encapsulation layer 79 may have a single-layer structure or a multi-layer structure.
  • the encapsulation layer 79 may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer arranged in sequence, such as silicon nitride SiN+ink+silicon nitride SiN.
  • the encapsulation layer 79 extends to the peripheral area to cover each film layer of the pixel unit.
  • embodiments of the present disclosure further provide a display device, which includes the display panel described in any one of the above first aspects.
  • the principle of solving the problem of the display panel included in the display device is similar to that of the display panel in the above embodiment.
  • the specific structure please refer to the above display panel, and the repeated details will not be repeated.
  • embodiments of the present disclosure also provide a method for manufacturing a display panel.
  • the structure of each film layer of the display panel can be seen in Figure 7a.
  • the specific preparation process of each film layer is as follows:
  • the process of forming the sixth conductive layer includes, but is not limited to, coating of photoresist - exposure - development - etching - stripping and other processes.
  • the first insulating layer 71 (can be the gate insulating layer GI1) on the side of the first semiconductor layer facing away from the base substrate 01.
  • a second plate Cst 2 of the storage capacitor Cst is formed on the side of the first plate Cst 1 facing the second insulating layer 72 and away from the base substrate 01 .

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Abstract

一种显示面板(100)以及显示装置，属于显示技术领域，其中，显示面板(100)包括衬底基板(01)，以及设置在衬底基板(01)上、呈阵列排布的多个像素单元组(10)，每一像素单元组(10)包括设置在衬底基板(01)上的第一像素单元(11)和第二像素单元(12)；第一像素单元(11)包括像素驱动电路(111)和与之电连接的第一发光器件(OLED1)，第二像素单元(12)包括第二发光器件(OLED2)；其中，对于位于同一行的像素单元组(10)，各个像素驱动电路(111)和各个第二发光器件(OLED2)的第二电极(22)连接同一栅线(G)；对于位于同一列的像素单元组(10)，各个像素驱动电路(111)连接同一数据线(S)，各个第二发光器件(OLED2)的第一电极(21)连接同一数据线(S)。

Description

显示面板以及显示装置 技术领域
本公开属于显示技术领域，具体涉及一种显示面板以及显示装置。
背景技术
目前显示面板主要以单面板为主，但在很多场景下，例如数字标牌、窗口询问设备，展览馆等公共场所的广告播放设备中往往需要正反两面显示相同画面，以方便相对位置的人员均能够观看到显示面板的画面。
传统技术方案为了实现显示面板的双面显示，一种情况下，采用液晶显示(Liquid Crystal Display，LCD)面板，由于该面板两侧均不能放置光源，只能用环境光来作为光源，导致显示面板发光亮度受限制。因此通常采用两个独立的LCD板实现双面显示。但这种情况下，若要确保两个LCD面板显示相同画面，需要较为复杂的连接及驱动关系，导致显示面板的制作成本大大提高，也使得显示面板的厚度增加，不符合显示面板轻薄化的设计。
另一种情况下，采用有机电致发光器件(Organic Electroluminescence Display，OLED)，由于其自发光的特性，因此可以解决LCD面板发光亮度受限的问题。但是采用OLED实现双面显示，仍需要单独制备两个OLED面板，再使其相互贴合，不利于实现轻薄化且产品的制备成本较高。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种显示面板以及显示装置。
第一方面，本公开实施例提供了一种显示面板，其包括衬底基板、以及设置在所述衬底基板上、呈阵列排布的多个像素单元组，每一所述像素单元组包括设置在所述衬底基板上的第一像素单元和第二像素单元；所述第一像素单元包括像素驱动电路和与之电连接的第一发光器件，第二像素单元包括第二发光器件；其中，
对于位于同一行的所述像素单元组，各个所述像素驱动电路和各个所述第二发光器件的第二电极连接同一栅线；
对于位于同一列的所述像素单元组，各个所述像素驱动电路连接同一数据线，各个所述第二发光器件的第一电极连接同一所述数据线。
在一些实施例中，所述呈阵列排布的多个像素单元组包括M行、N列所述像素单元组；其中，M为大于或者等于1的正整数，N为大于或者等于2的正整数；
N列所述像素单元组沿第一方向顺次排布，N条所述数据线沿第一方向顺次排布，且第i列所述像素驱动电路与第i条所述数据线连接；0＜i≤N，且所述i为正整数；
第j列所述第二发光器件的第一电极，连接第(N-j+1)条所述数据线；1≤j≤N，所述j为正整数。
在一些实施例中，所述显示面板还包括连接信号线；
所述像素驱动电路所连接的一条所述数据线与一条所述连接信号线连接，所述连接信号线经过走线区，与所述第二发光器件的第一电极连接；
各条所述连接信号线在所述衬底基板上的正投影无重叠。
在一些实施例中，所述显示面板包括设置在所述衬底基板上的驱动电路层；所述像素驱动电路位于所述驱动电路层；
所述第一发光器件位于所述驱动电路层背离所述衬底基板的一侧；所述第二发光器件位于所述驱动电路层靠近所述衬底基板的一侧；
对于一个所述像素单元组，所述第一发光器件在所述衬底基板上的正投影和/或所述第二发光器件在所述衬底基板上的正投影，均与所述像素驱动电路在所述衬底基板上的正投影至少部分重叠。
在一些实施例中，所述第一发光器件、所述第二发光器件和所述像素驱动电路中的任意两者，在所述衬底基板上的正投影重叠。
在一些实施例中，所述像素驱动电路包薄膜晶体管和存储电容；
所述驱动电路层包括依次设置在所述第二发光器件背离所述衬底基板一侧的第一半导体层、第一导电层和第二导电层；
所述薄膜晶体管的有源层位于所述第一半导体层；
所述薄膜晶体管的栅极、所述存储电容的第一极板和所述栅线均位于所述第一导电层；
所述薄膜晶体管的源极和漏极均位于所述第二导电层。
在一些实施例中，所述显示面板还包括设置在所述第一半导体层靠近所述衬底基板一侧的缓冲层、以及设置在所述第一半导体层和所述第一导电层之间的第一绝缘层；
在同一所述像素单元组中所述第二发光器件的第二电极，通过连接过孔与所述栅线电连接；所述连接过孔依次贯穿所述第二像素定义层、所述缓冲层和所述第一绝缘层。
在一些实施例中，所述显示面板还包括依次设置在所述驱动电路层背离所述衬底基板一侧的第三导电层、第一像素定义层和第四导电层；
所述第一发光器件的第一电极位于所述第三导电层；所述第一发光器件的第二电极位于所述第四导电层；所述第一发光器件的第一电极为反射电极，所述第一发光器件的第二电极为透射电极；
所述第一发光器件的第一蒸镀层位于所述第一像素定义层，且所述第一发光器件的第二电极在所述衬底基板上的正投影覆盖所述第一蒸镀层在所述衬底基板上的正投影。
在一些实施例中，所述显示面板还包括依次设置在所述驱动电路层靠近所述衬底基板的一侧的第五导电层、第二像素定义层和第六导电层；
所述第二发光器件的第一电极位于所述第五导电层；所述第二发光器件的第二电极位于所述第六导电层；所述第二发光器件的第一电极为反射电极，所述第二发光器件的第二电极为透射电极；
所述第二发光器件的第二蒸镀层位于所述第二像素定义层，且所述第二发光器件的第二电极在所述衬底基板上的正投影覆盖所述第二蒸镀层在所述衬底基板上的正投影。
第二方面，本公开实施例还提供了一种显示装置，其包括上述任一显示 面板。
附图说明
图1为本公开实施例提供的像素单元之间的连接结构示意图；
图2为本公开实施例提供的像素单元组的示意图；
图3为本公开实施例提供的一种第一像素单元和第二像素单元连接结构的示意图；
图4为本公开实施例提供的一种双面显示的显示面板的电路图；
图5为本公开实施例提供的一种显示面板的时序控制原理图；
图6为本公开实施例提供的一种显示面板的结构示意图；
图7a为本公开实施例提供的一种显示面板的膜层结构示意图；
图7b为本公开实施例提供的像素驱动电路的膜层版图；
图8为本公开实施例提供的一种第二发光器件的第二电极的连接结构示意图；
图9为本公开实施例提供的第一像素单元和第二像素单元的膜层连接结构示意图。
其中附图标记为：显示面板100；衬底基板01；像素单元组10；第一像素单元11；第二像素单元12；像素驱动电路111；第一发光器件OLED1；第二发光器件OLED2；第二发光器件的第一电极21；第二发光器件的第二电极22；第二蒸镀层23；第一发光器件的第一电极31；第一发光器件的第二电极32；第一蒸镀层33；开关薄膜晶体管T1；驱动薄膜晶体管T2；开关薄膜晶体管的栅极41；存储电容Cst；存储电容的第一极板Cst1；存储电容的第二极板Cst2；开关薄膜晶体管的源极42；开关薄膜晶体管的漏极43；开关薄膜晶体管的有源层44；驱动薄膜晶体管的栅极51；驱动薄膜晶体管的源极52；驱动薄膜晶体管的漏极53；驱动薄膜晶体管的有源层54；驱动电路层02；第一绝缘层71；第二绝缘层72；开孔层73；平坦层74；缓冲层75；第二像素定义层76；第一像素定义层77；隔垫层78；封装层79。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中提及的“多个或者若干个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
需要说明的是，本公开中，第一方向X、第二方向Y和第三方向Z三者两两相交，在本公开中，以第一方向X和第二方向Y在基底所在平面互相垂直，第一方向X为水平方向，第二方向Y为竖直方向，且第三方向Z为垂直方向，其垂直于基底所在平面为例进行说明，但不对本公开构成限制。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一 旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
经研究发现，由于OLED自发光的特性，因此采用有机电致发光器件OLED实现显示面板的双面显示，能够解决LCD面板发光亮度受限的问题。但是采用OLED实现双面显示，仍需要单独制备两个OLED面板，再使其相互贴合，由于实现两个独立面板的同步显示，需要较为复杂的连接及驱动，因此导致显示面板的制作成本大大提高，也使得显示面板的厚度增加，不符合显示面板轻薄化的设计。
为了实现OLED面板的双面显示，并使其显示结构轻薄化，降低制备成本，本公开实施例提供了一种显示面板，其包括设置在衬底基板上、呈阵列排布的多个像素单元组。每一像素单元组包括设置在衬底基板上的第一像素单元和第二像素单元。第一像素单元包括像素驱动电路和与之电连接的第一发光器件，第二像素单元包括第二发光器件，与现有技术相比，本公开实施例第一发光器件和第二发光器件位于同一像素单元组，无需制备两个独立的显示面板再贴合，在降低制备成本的同时，能够实现显示面板的轻薄化。另外，本公开实施例中位于同一行的像素单元组，各个像素驱动电路和各个第二发光器件的第二电极连接同一栅线；位于同一列的像素单元组，各个像素驱动电路连接同一数据线，各个第二发光器件的第一电极连接同一数据线。通过各条栅线和各条数据线的连接，利用像素驱动电路驱动显示面板中的第一发光器件和第二发光器件，能够实现第一发光器件和第二发光器件同步发光，进而实现显示面板的双面显示。
下面将结合本公开实施例中的附图，对本公开实施例提供的一种显示模组加以说明。
图1为本公开实施例提供的像素单元之间的连接结构示意图，图2为本公开实施例提供的像素单元组的示意图。
如图1和图2所示，显示面板100包括设置在衬底基板01上、呈阵列排布的多个像素单元组10。每一像素单元组10包括设置在衬底基板01上的第一像素单元11和第二像素单元12。第一像素单元11包括像素驱动电路 111和与之电连接的第一发光器件OLED1，第二像素单元12包括第二发光器件OLED2。像素驱动电路111用于驱动第一发光器件OLED1发光。第一发光器件OLED1可以实现显示面板100的正面发光，第二发光器件OLED2可以实现显示面板100的反面发光。
如图1所示，对于位于同一行的像素单元组10，各个像素驱动电路111和各个第二发光器件112的第二电极22连接同一栅线G。像素驱动电路111在驱动第一发光器件OLED1发光的同时，通过连接的栅线G，可以将信号传递给与之连接的各个第二发光器件OLED2的第二电极22。
如图1所示，对于位于同一列的像素单元组10，各个像素驱动电路111连接同一数据线S，各个第二发光器件OLED2的第一电极21连接同一数据线S。
需要说明的是，对于位于同一列的像素单元组10，各个像素驱动电路111连接同一数据线S，该数据线S可以与位于相同列的像素单元组10中的各个第二发光器件OLED2的第一电极21连接；或者，该数据线S也可以与位于不同列的像素单元组10中的各个第二发光器件OLED2的第一电极21连接，可以根据实际情况进行设定。
需要说明的是，对于位于不同列的像素单元组10，其中，多列各个像素驱动电路111可以连接同一数据线S，或者，每列像素驱动电路111也可以连接不同的数据线S。
示例性的，本公开的衬底基板01可以为柔性基底，该柔性基底通过透明材料进行制备，能够将发光器件产生的光透射至外部环境。
在一些示例中，不同列像素驱动电路111连接不同的数据线S。可以根据呈阵列排布的多个像素单元组10中像素单元组10的列数，设置第一像素单元11和第二像素单元12对应的数据线S之间的连接方式。
若同一像素单元组10中的第一发光器件OLED1和第二发光器件OLED2显示相同画面，则存在画面翻到的情况，比如正面观看数字为“IV”，反面观看为数字为“VI”。为了消除双面显示画面翻到的影响，本公开实施 例提供了一种数据线的连线方式，具体地，如图1所示，呈阵列排布的多个像素单元组10包括M行、N列像素单元组10；其中，M为大于或者等于1的正整数，N为大于或者等于2的正整数。N列像素单元组10沿第一方向X顺次排布，N条数据线S沿第一方向X顺次排布，且第i列像素驱动电路111与第i条数据线S连接，也即每列像素驱动电路111存在一一对应连接的数据线S。0＜i≤N，且i为正整数。第j列第二发光器件OLED2的第一电极21，连接第(N-j+1)条数据线S；1≤j≤N，j为正整数。
如图1所示，以4×4个像素单元组为例，其中，第一列像素驱动电路111与第一条数据线S1连接，第一条数据线S1与第四列第二发光器件OLED2的第一电极21连接，也即第一列各个像素驱动电路111与第四列各个第二发光器件OLED2的第一电极21，通过一条数据线(即第一条数据线S1)实现电连接。同理，第二列各个像素驱动电路111与第三列各个第二发光器件OLED2的第一电极21，通过第二条数据线S2实现电连接。第三列各个像素驱动电路111与第二列各个第二发光器件OLED2的第一电极21，通过第三条数据线S3实现电连接。第四列各个像素驱动电路111与第一列各个第二发光器件OLED2的第一电极21，通过第四条数据线S4实现电连接。
如图1所示，M行像素单元组10沿第二方向Y顺次排布，M条栅线G沿第二方向Y顺次排布，且第k行像素驱动电路111与第k条栅线G连接，也即每行像素驱动电路111存在一一对应连接的栅线G。0＜k≤M，且k为正整数。位于同一行的像素单元组10，各个像素驱动电路111和各个第二发光器件OLED2的第二电极22连接同一栅线G。
在一些示例中，如图1所示，本公开的显示面板100包括显示区DA(Display Area)和围绕显示区设置的周边区PA(Peripheral Area)，其中，像素驱动电路设置在显示区DA，栅极集成驱动电路(Gate On Array，GOA)和源极驱动芯片(Chip，IC)设置在周边区PA，GOA可以通过栅线为各行第一像素单元提供栅极驱动信号，源极驱动芯片IC可以通过数据线为各列第一像素单元和第二像素单元提供数据信号。
图3为本公开实施例提供的一种第一像素单元和第二像素单元连接结构的示意图，如图3所示，显示面板100还包括连接信号线Y；像素驱动电路111所连接的一条数据线S与一条连接信号线Y连接，连接信号线Y经过走线区，与第二发光器件OLED2的第一电极21连接；各条连接信号线Y在衬底基板01上的正投影无重叠。具体地，第j列第二发光器件OLED2的第一电极21，连接第(N-j+1)条数据线S。
本公开实施例通过在走线区设置连接信号线Y，能够避免数据线S之间连接的布线重叠，从而降低数据线S之间数据信号传输的干扰，提高驱动电路稳定性，进而提高发光亮度一致性。
这里，连接信号线Y与数据线S可以为一体结构，也即连接信号线Y即为位于走线区的数据线。如图3所示，以4×4个像素单元组为例，第一条数据线S1连接第一列的各个像素驱动电路111，之后经过走线区(也即通过第一连接信号线Y1)，连接第四列的各个第二发光器件OLED2的第一电极21。其他条数据线S2、S3和S4的连接结构与上述S1同理，本公开实施例不再一一列举。
图4为本公开实施例提供的一种双面显示的显示面板的电路图，如图4所示，其仅示出了图3中第二行第二列、第二行第三列、第三行第二列、以及第三行第三列对应的四个像素单元组10的电路图。以像素驱动电路111为2T1C结构(即2个薄膜晶体管和一个电容)为例，第3行的栅线G2，分别与第3行的各个第一像素单元11中的开关薄膜晶体管T1的栅极41电连接，并与第3行的各个第二像素单元12中的第二发光器件OLED2的第二电极22(也即阴极)电连接。第二条数据线S2，分别第二列的第一像素单元11中的开关薄膜晶体管T1的源极42电连接，并经过走线区，与第三列的第二发光器件OLED2的第一电极12(也即阳极)电连接。示例性的，如图4所示，栅线G2连接第一像素单元A中的开关薄膜晶体管T1的栅极41、以及第二像素单元B’中的第二发光器件OLED2的阴极22。数据线S2连接第一像素单元A中的开关薄膜晶体管T1的源极42、以及第二像素单元B’中的第二发光器件OLED2的阳极21。
2T1C结构的像素驱动电路，其中，第一像素单元11包括用于开关控制的开关薄膜晶体管T1和用于像素驱动的驱动薄膜晶体管T2。开关薄膜晶体管T1的漏极43与驱动薄膜晶体管T2的栅极51，以及存储电容Cst的第一极板Cst1电连接；驱动薄膜晶体管T2的源极52与第一电源信号线Vdd电连接；驱动薄膜晶体管T2的漏极53与第一发光器件OLED1的第一电极31(也即阳极)电连接；第一发光器件OLED1的第二电极32(也即阴极)和存储电容Cst的第二极板Cst2，分别与第二电源信号线Vss电连接。
图5为本公开实施例提供的一种显示面板的时序控制原理图，如图5所示，以4×4个像素单元组为例，GOA通过控制栅线按行扫描，在第一时刻t1时刻为第一行的各个像素驱动电路111提供一个电压信号脉冲(也即栅极驱动信号)；在第二时刻t2时刻为第二行的各个像素驱动电路111提供一个电压信号脉冲(也即栅极驱动信号)；第三时刻t3时刻为第三行的各个像素驱动电路111提供一个电压信号脉冲(也即栅极驱动信号)；第四时刻t4时刻为第四行的各个像素驱动电路111提供一个电压信号脉冲(也即栅极驱动信号)。上述电压信号脉冲既可以使用低电位信号，也可以使用高电位信号，可以根据实际情况进行设定。本公开实施例以实际使用低电位信号为例进行说明。
如图5所示，IC通过控制各列数据线S，在某一时刻，比如t2时刻，为第一列的像素驱动电路111提供一个电压脉冲信号(也即数据信号)。此时，在t2时刻，第二行的栅线G2与第一条数据线S1同时存在电压脉冲，对应第二行、第一列的像素驱动电路111同时存在栅极驱动信号和数据信号，使得第二行、第一列的第一发光器件OLED1的第一电极31处于高电位，进而驱动第一发光器件发光OLED1。同时，在t2时刻，第二行的栅线G2与第一条数据线S1同时存在电压脉冲，其中，第二行的栅线G2对应为第二行、第四列的第二发光器件OLED2的第二电极22提供电压，第一条数据线S1对应为第二行、第四列的第二发光器件OLED2的第一电极21提供电压，第二行、第四列的第二发光器件OLED2的第一电极21和第二电极22形成电压差，进而驱动第二行、第四列的第二发光器件OLED2发光。这里，第二 行、第一列的第一发光器件OLED1，与第二行、第四列的第二发光器件OLED2的数据信号时序保持一致，能够实现同步发光，且显示画面相同。
如图5所示，IC通过控制各列数据线，在某一时刻，比如t4时刻，为第四列的像素驱动电路111提供一个电压脉冲信号也即数据信号)。此时，在t4时刻，第四行的栅线G4与第四条数据线S4同时存在电压脉冲，对应第四行、第四列的像素驱动电路111同时存在栅极驱动信号和数据信号，使得第四行、第四列的第一发光器件OLED1的第一电极31处于高电位，进而驱动第一发光器件OLED1发光。同时，在t4时刻，第四行的栅线G4与第四条数据线S4同时存在电压脉冲，其中，第四行的栅线G4对应为第四行、第一列的第二发光器件OLED2的第二电极22提供电压，第四条数据线S4对应为第四行、第一列的第二发光器件OLED2的第一电极21提供电压，第四行、第一列的第二发光器件OLED2的第一电极21和第二电极22形成电压差，进而驱动第四行、第一列的第二发光器件OLED2发光。这里，第四行、第四列的第一发光器件OLED1，与第四行、第一列的第二发光器件OLED2的数据信号时序保持一致，能够实现同步发光，且显示画面相同。
需要说明的是，上述时序控制只有在栅线与数据线同时为第二发光器件OLED2提供电压，形成电压差，第二发光器件OLED2才会发光，实现显示面板100的双面显示。
在一些示例中，图6为本公开实施例提供的一种显示面板的结构示意图，如图6所示，显示面板100包括设置在衬底基板01上的驱动电路层02；像素驱动电路111位于驱动电路层02。第一发光器件OLED1位于驱动电路层02背离衬底基板01的一侧；第二发光器件OLED2位于驱动电路层02靠近衬底基板01的一侧。这里，通过设置在驱动电路层02相对侧面的第一发光器件OLED1和第二发光器件OLED2，实现显示面板100的双面显示。
如图6所示，对于一个像素单元组10，第一发光器件OLED1在衬底基板01上的正投影和/或第二发光器件OLED2在衬底基板01上的正投影，均与像素驱动电路111在衬底基板01上的正投影至少部分重叠，这种将发光器件与像素驱动电路重叠设置的方式，能够合理利用像素驱动电路中薄膜晶 体管的占用面积，从而提高单位面积下设置像素单元的数量，进而能够满足高分辨率(Pixels Per Inch，PPI)的显示面板100的像素需求。
优选地，第一发光器件OLED1、第二发光器件OLED2和像素驱动电路111中的任意两者，在衬底基板01上的正投影重叠。
在一些示例中，像素驱动电路111包括薄膜晶体管和存储电容Cst；驱动电路层02包括依次设置在第二发光器件OLED2背离衬底基板一侧的第一半导体层、第一导电层和第二导电层；薄膜晶体管的有源层位于第一半导体层；薄膜晶体管的栅极、存储电容的第一极板和栅线均位于第一导电层；薄膜晶体管的源极和漏极均位于第二导电层。
在实际产品中像素驱动电路可以是2T1C结构、5T2C结构、6T1C结构、6T2C结构、7T1C结构、7T2C结构、或者9T2C结构等，本公开实施例对此不作限定。下面本公开实施例仅以像素驱动电路为2T1C结构为例进行说明，具体地，薄膜晶体管包括用于开关控制的开关薄膜晶体管T1和用于像素驱动的驱动薄膜晶体管T2。
图7a为本公开实施例提供的一种显示面板的膜层结构示意图，图7b为本公开实施例提供的像素驱动电路的膜层版图，如图4、图7a和图7b所示，开关薄膜晶体管T1的有源层44和驱动薄膜晶体管T2的有源层54均位于第一半导体层；开关薄膜晶体管T1的栅极41和驱动薄膜晶体管T2的栅极51均位于第一导电层；开关薄膜晶体管T1的源极42和漏极43、以及驱动薄膜晶体管T2的源极52和漏极53均位于第二导电层。
在第一半导体层和第一导电层之间设置有第一绝缘层71(也即第一栅极绝缘层GI1)；在第一导电层和第二导电层之间、且靠近第一导电层设置有第二绝缘层72(也即第二栅极绝缘层GI2)；在第二绝缘层72和第二导电层之间设置有开孔层73；在第二导电层和第一发光器件OLED1之间设置有平坦层74。
开关薄膜晶体管T1的源极42通过贯穿开孔层73、第一绝缘层71和第二绝缘层72的第一连接过孔Via1，与开关薄膜晶体管T1的有源层44的源 区电连接；开关薄膜晶体管T1的漏极43通过贯穿开孔层73、第一绝缘层71和第二绝缘层72的第二连接过孔Via2，与开关薄膜晶体管T1的有源层44的漏区电连接；驱动薄膜晶体管T2的源极52通过贯穿开孔层73、第一绝缘层71和第二绝缘层72的第三连接过孔，与驱动薄膜晶体管T2的有源层54的源区电连接；驱动薄膜晶体管T2的漏极53通过贯穿开孔层73、第一绝缘层71和第二绝缘层72的的第四连接过孔，与驱动薄膜晶体管T2的有源层54的漏区电连接。第一发光器件OLED1的第一电极31(也即阳极)通过贯穿平坦层74的第五连接过孔Via5，与开关薄膜晶体管T1的漏极43电连接。开关薄膜晶体管T1的漏极43或驱动薄膜晶体管T2的栅极51，通过贯穿开孔层73和第二绝缘层72的第六连接过孔Via6，与存储电容Cst的第一极板Cst1电连接。
本公开的开关薄膜晶体管T1和驱动薄膜晶体管T2可以为P型晶体管或N型晶体管，本公开实施例以P型晶体管为例进行说明，也就是说，本公开的描述中，开关薄膜晶体管T1和驱动薄膜晶体管T2均为P型晶体管。但应当理解的是，本公开的实施例的薄膜晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管实现本公开的实施例中的一个或多个薄膜晶体管的功能。
在一些示例中，如图7a所示，显示面板100还包括设置在第一半导体层靠近衬底基板01一侧的缓冲层75、以及设置在述第一半导体层和第一导电层之间的第一绝缘层71。其中，缓冲层75可以防止或减少金属原子和/或杂质从衬底基板01扩散到第一半导体层中。本公开实施例中，缓冲层75可以包括诸如氧化硅(SiOx)、氮化硅(SiNx)和/或氮氧化硅(SiON)的无机材料，并且可以形成为多层或单层。
在同一像素单元组中第二发光器件OLED2的第二电极22，通过连接过孔与栅线电连接；连接过孔(也即第七连接过孔)依次贯穿第一绝缘层71、缓冲层75和第二像素定义层76。图8为本公开实施例提供的一种第二发光器件的第二电极的连接结构示意图，如图8所示，以像素驱动电路111为2T1C结构为例，同一像素单元组10中第二发光器件OLED2的第二电极22 和开关薄膜晶体管T1的栅极41，通过栅线G，并经过连接过孔(也即第七连接过孔Via7)实现电连接。同一行的不同像素单元组10中各个开关薄膜晶体管T1的栅极41通过栅线G实现电连接。
在一些示例中，如图7a所示，显示面板100还包括依次设置在驱动电路层02背离衬底基板01一侧的第三导电层、第一像素定义层77和第四导电层；第一发光器件OLED1包括第一电极31、第二电极32以及夹设在第一电极31和第二电极32之间的第一蒸镀层33。第一发光器件OLED1的第一电极31位于第三导电层；第一发光器件OLED1的第二电极32位于第四导电层；第一发光器件OLED1的第一电极31为反射电极，第一发光器件OLED1的第二电极32为透射电极。第一蒸镀层33位于第一像素定义层77，且第一发光器件OLED1的第二电极32在衬底基板01上的正投影覆盖第一蒸镀层33在衬底基板01上的正投影，使得第一蒸镀层33所发出的光均经过透射电极32进行透射。
本公开实施例中均以第一电极为阳极，第二电极为阴极为例进行说明。透射电极也即透明阴极，其能够透射蒸镀层发出的光；反射电极也即反射阳极能够反射蒸镀层发出的光，并经过透明阴极反射出去。
如图4、图7a和图7b所示，驱动薄膜晶体管T2的源极52连接第一电源信号线Vdd，并加载电压。开关薄膜晶体管T1的有源层44具有源区、漏区、以及夹设在源区和漏区之间的沟道区，当开关薄膜晶体管T1的栅极41处于低电位V负时，开关薄膜晶体管T1的有源层44的沟道区开启，也即形成载流子沟道；若给开关薄膜晶体管T1的源极42加载高电位V正，则数据线S传输的数据信号通过沟道区传输至开关薄膜晶体管T1的漏区，进而通过开关薄膜晶体管T1的漏极43传输至第一发光器件OLED1的阳极31。此时，第一发光器件OLED1的阳极31为高电位V正，与第一发光器件OLED1的阴极32电位为0作用在第一蒸镀层33，第一蒸镀层33发光并通过透明的阴极32实现正面出光。同时，开关薄膜晶体管T1的源极42的电压存储至存储电容Cst，并维持第一发光器件OLED1阳极31的电位，使得第一蒸镀层33能够持续发光。
在一些示例中，如图7a所示，显示面板100还包括依次设置在驱动电路层02靠近衬底基板01的一侧的第五导电层、第二像素定义层76和第六导电层；第二发光器件OLED2包括第一电极21、第二电极22、以及夹设在第一电极和第二电极之间的第二蒸镀层23。第二发光器件OLED2的第一电极21位于第五导电层；第二发光器件OLED2的第二电极22位于第六导电层；第二发光器件OLED2的第一电极21为反射电极，第二发光器件OLED2的第二电极22为透射电极；第二蒸镀层23位于第二像素定义层76，且第二发光器件OLED2的第二电极22在衬底基板01上的正投影覆盖第二蒸镀层23在衬底基板01上的正投影，使得第二蒸镀层23所发出的光均经过透射电极22进行透射。
针对蒸镀层，在制备过程中，可以将发光材料蒸镀到像素定义层的开口内，形成蒸镀层，该蒸镀层包含RGB三种像素(其中，R表示红色，G表示绿色，B表示蓝色)。
发光材料存在一定的发光阈值电压V发光电压，设计该发光阈值电压V发光电压，令V正+|V负|＞V发光电压＞V正或|V负|，当发光器件的两侧电极加载的电压大于该V发光电压时，发光材料发光。
如图4、图7a和图7b所示，驱动薄膜晶体管T2的源极52连接第一电源信号线Vdd，并加载电压。开关薄膜晶体管T1的有源层44具有源区、漏区、以及夹设在源区和漏区之间的沟道区，当开关薄膜晶体管T1的栅极41处于低电位V负时，开关薄膜晶体管T1的有源层44的沟道区开启，也即形成载流子沟道；若给开关薄膜晶体管T1的源极42加载高电位V正，则数据线S传输的数据信号通过沟道区传输至开关薄膜晶体管T1的漏区，进而通过开关薄膜晶体管T1的漏极43传输至第一发光器件OLED1的阳极31。此时，第一发光器件OLED1的阳极31为高电位V正，与第一发光器件OLED1的阴极32电位为0作用在第一蒸镀层，第一蒸镀层33发光并通过透明的阴极32实现正面出光。与此同时，由于开关薄膜晶体管T1的栅极41连接第二发光器件OLED2的阴极22，因此第二发光器件OLED2的阴极22处于低电位V负；开关薄膜晶体管T1的源极42所连接的数据线S与第二发光器件OLED2的阳极21电连接，第二发光器件OLED2的阳极21位于高电位V正，第二发光器件OLED的阳极21和阴极22产生电压差V正-V负＝V正+|V负|＞V发光电压，并作用在第二蒸镀层23，第二蒸镀层23发光并通过透明的 阴极22实现反面出光。
当开关薄膜晶体管T1的栅极41接通，也即处于低电位V负，开关薄膜晶体管T1的源极42不接通，也即电压为0时，第一发光器件OLED1不发光。同时，第二发光器件OLED3两侧电极的电压为0-V负＜V发光电压，因此第二发光器件OLED2不发光。
当开关薄膜晶体管T1的栅极41不接通，也即电压为0，开关薄膜晶体管T1的源极42接通，也即电压为V正时，第一发光器件OLED1不发光。同时，第二发光器件OLED2两侧电极的电压为V正-0＜V发光电压，因此第二发光器件OLED2不发光。
需要注意的是，这里的第二发光器件OLED2与可以是与该像素驱动电路111位于同一像素单元组10，也可以与该像素驱动电路111同行不同列的其他像素单元组10，具体可以参见上述图3的电路连接关系。
图9为本公开实施例提供的第一像素单元和第二像素单元的膜层连接结构示意图，其中，图9示出了图3所示的第二行、第二列的第一像素单元A和第二行、第三列的第二像素单元B的部分膜层，如图9所示，第一像素单元A的开关晶体管T1的栅极41通过第二条栅线G2，与第二像素单元B的第二发光器件OLED2的反射阳极21电连接；第一像素单元A的开关薄膜晶体管T1的源极42通过第二条数据线S2，与第二像素单元B的第二发光器件OLED2的透明阴极22电连接。
在一些示例中，如图7a所示，在第一像素定义层和第一发光器件的第二电极之间设置有隔垫层78。该隔垫层78可以增加外界的水汽或氧气进入显示区DA的路径，从而保护显示区DA中的发光器件。
在一些示例中，如图7a所示，在第一发光器件背离衬底基板的一侧设置封装层79。封装层79可以为单层结构，也可以为多层结构。在封装层79为多层结构时，封装层79可以包括依次设置的第一无机封装层、有机封装层、第二无机封装层，例如氮化硅SiN+油墨+氮化硅SiN。
进一步，封装层79延伸到外围区以覆盖像素单元的各个膜层。
第二方面，基于同一发明构思，本公开实施例还提供了一种显示装置，其包括上述第一方面中任一项所述的显示面板。
显示装置中包含的显示面板解决问题的原理与上述实施例中显示面板相似，具体结构可以参见上述显示面板，重复之处不再赘述。
第三方面，基于同一发明构思，本公开实施例还提供了一种显示面板的制备方法。显示面板的各个膜层结构可以参见图7a所示，各个膜层的具体制备过程如下：
S1、在衬底基板01上形成第六导电层(也即第二发光器件OLED2的透射阴极22)。
形成第六导电层的工艺包括但不仅限于涂覆光刻胶-曝光-显影-刻蚀-剥离等工艺。
S2、在第六导电层背离衬底基板01的一侧形成第二像素定义层76，并在第二像素定义层76上的预设位置开口。
S3、在第二像素定义层76的开口处蒸镀发光材料，形成第二蒸镀层23。
S4、在第二蒸镀层23背离衬底基板01的一侧形成第五导电层(也即第二发光器件OLED2的反射阳极21)。
S5、在第五导电层背离衬底基板01的一侧形成缓冲层75。
S6、在缓冲层75背离衬底基板01的一侧形成半导体层，并通过在半导体层上进行涂覆光刻胶-曝光-显影-刻蚀-剥离等工艺，制备得到薄膜晶体管的有源层(也即第一半导体层)。
S7、在第一半导体层背离衬底基板01的一侧第一绝缘层71(可以为栅极绝缘层GI1)。
S8、在第一绝缘层71背离衬底基板01的一侧形成第一导电层(包括薄膜晶体管的栅极、各行栅线、以及存储电容的第一极板)。
S9、在第一导电层背离衬底基板01的一侧形成第二绝缘层72(可以为栅极绝缘层GI2)。
S10、对于存储电容Cst的第一极板Cst1，在该第一极板Cst1正对第二绝缘层72，且背离衬底基板01的一侧形成存储电容Cst的第二极板Cst2。
S11、在第二绝缘层72背离衬底基板01的一侧、以及第二极板Cst2背离衬底基板01的一侧形成开孔层73。
S12、在开孔层73背离衬底基板01的一侧形成第二导电层(包括薄膜晶体管的源极和漏极)。
S13、在第二导电层背离衬底基板01的一侧形成平坦层74。
S14、在平坦层背74离衬底基板01的一侧形成第三导电层(包括第一发光器件OLED1的反射阳极31)。
S15、在第三导电层背离衬底基板01的一侧形成第一像素定义层77，并在第一像素定义层77上的预设位置开口。
S16、在第一像素定义层77的开口处蒸镀发光材料，形成第一蒸镀层33；在第一像素定义层77的边缘区域形成隔垫层78。
S17、在第一像素定义层77和隔垫层78背离衬底基板01的一侧形成第四导电层(也即第一发光器件OLED1的透射阴极32)。
S18、在第四导电层背离衬底基板01的一侧形成封装层79。
针对上述步骤S1～S18，在需要打孔的膜层位置进行打孔，以形成第一连接过孔Via1、第二连接过孔Via2、第三连接过孔、第四连接过孔、第五连接过孔Via5、第六连接过孔Via6和第七连接过孔Via7。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (10)

  1. 一种显示面板，其包括衬底基板，以及设置在所述衬底基板上、呈阵列排布的多个像素单元组，每一所述像素单元组包括设置在所述衬底基板上的第一像素单元和第二像素单元；所述第一像素单元包括像素驱动电路和与之电连接的第一发光器件，第二像素单元包括第二发光器件；其中，
    对于位于同一行的所述像素单元组，各个所述像素驱动电路和各个所述第二发光器件的第二电极连接同一栅线；
    对于位于同一列的所述像素单元组，各个所述像素驱动电路连接同一数据线，各个所述第二发光器件的第一电极连接同一所述数据线。
  2. 根据权利要求1所述的显示面板，其中，所述呈阵列排布的多个像素单元组包括M行、N列所述像素单元组；其中，M为大于或者等于1的正整数，N为大于或者等于2的正整数；
    N列所述像素单元组沿第一方向顺次排布，N条所述数据线沿第一方向顺次排布，且第i列所述像素驱动电路与第i条所述数据线连接；0＜i≤N，且所述i为正整数；
    第j列所述第二发光器件的第一电极，连接第(N-j+1)条所述数据线；1≤j≤N，所述j为正整数。
  3. 根据权利要求1所述的显示面板，其中，所述显示面板还包括连接信号线；
    所述像素驱动电路所连接的一条所述数据线与一条所述连接信号线连接，所述连接信号线经过走线区，与所述第二发光器件的第一电极连接；
    各条所述连接信号线在所述衬底基板上的正投影无重叠。
  4. 根据权利要求1所述的显示面板，其中，所述显示面板包括设置在所述衬底基板上的驱动电路层；所述像素驱动电路位于所述驱动电路层；
    所述第一发光器件位于所述驱动电路层背离所述衬底基板的一侧；所述第二发光器件位于所述驱动电路层靠近所述衬底基板的一侧；
    对于一个所述像素单元组，所述第一发光器件在所述衬底基板上的正投影和/或所述第二发光器件在所述衬底基板上的正投影，均与所述像素驱动电路在所述衬底基板上的正投影至少部分重叠。
  5. 根据权利要求4所述的显示面板，其中，所述第一发光器件、所述第二发光器件和所述像素驱动电路中的任意两者，在所述衬底基板上的正投影重叠。
  6. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包薄膜晶体管和存储电容；
    所述驱动电路层包括依次设置在所述第二发光器件背离所述衬底基板一侧的第一半导体层、第一导电层和第二导电层；
    所述薄膜晶体管的有源层位于所述第一半导体层；
    所述薄膜晶体管的栅极、所述存储电容的第一极板和所述栅线均位于所述第一导电层；
    所述薄膜晶体管的源极和漏极均位于所述第二导电层。
  7. 根据权利要求6所述的显示面板，其中，所述显示面板还包括设置在所述第一半导体层靠近所述衬底基板一侧的缓冲层、以及设置在所述第一半导体层和所述第一导电层之间的第一绝缘层；
    在同一所述像素单元组中所述第二发光器件的第二电极，通过连接过孔与所述栅线电连接；所述连接过孔依次贯穿所述第二像素定义层、所述缓冲层和所述第一绝缘层。
  8. 根据权利要求4所述的显示面板，其中，所述显示面板还包括依次设置在所述驱动电路层背离所述衬底基板一侧的第三导电层、第一像素定义层和第四导电层；
    所述第一发光器件的第一电极位于所述第三导电层；所述第一发光器件的第二电极位于所述第四导电层；所述第一发光器件的第一电极为反射电极，所述第一发光器件的第二电极为透射电极；
    所述第一发光器件的第一蒸镀层位于所述第一像素定义层，且所述第一 发光器件的第二电极在所述衬底基板上的正投影覆盖所述第一蒸镀层在所述衬底基板上的正投影。
  9. 根据权利要求4所述的显示面板，其中，所述显示面板还包括依次设置在所述驱动电路层靠近所述衬底基板的一侧的第五导电层、第二像素定义层和第六导电层；
    所述第二发光器件的第一电极位于所述第五导电层；所述第二发光器件的第二电极位于所述第六导电层；所述第二发光器件的第一电极为反射电极，所述第二发光器件的第二电极为透射电极；
    所述第二发光器件的第二蒸镀层位于所述第二像素定义层，且所述第二发光器件的第二电极在所述衬底基板上的正投影覆盖所述第二蒸镀层在所述衬底基板上的正投影。
  10. 一种显示装置，其包括如权利要求1～9中任一项所述的显示面板。
PCT/CN2023/105837 2022-07-25 2023-07-05 显示面板以及显示装置 WO2024022058A1 (zh)

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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060081508A (ko) * 2005-01-07 2006-07-13 삼성에스디아이 주식회사 발광표시장치
CN103794179A (zh) * 2014-03-06 2014-05-14 四川虹视显示技术有限公司 一种oled驱动方法及装置
CN105140260A (zh) * 2015-07-23 2015-12-09 京东方科技集团股份有限公司 有机发光二极管阵列基板及其制作方法、显示装置
CN106252383A (zh) * 2016-09-30 2016-12-21 京东方科技集团股份有限公司 双面显示面板及其制作方法、显示装置
KR20180078793A (ko) * 2016-12-30 2018-07-10 엘지디스플레이 주식회사 플렉서블 양면형 표시장치 및 그 제조방법
CN109599057A (zh) * 2017-09-29 2019-04-09 乐金显示有限公司 双面显示器
CN111403454A (zh) * 2020-03-26 2020-07-10 武汉华星光电半导体显示技术有限公司 显示面板
CN112150970A (zh) * 2020-09-21 2020-12-29 Oppo广东移动通信有限公司 显示组件及其制备方法、显示模组和电子设备
CN113571560A (zh) * 2021-07-15 2021-10-29 Tcl华星光电技术有限公司 双面显示面板及显示装置
CN115207071A (zh) * 2022-07-25 2022-10-18 京东方科技集团股份有限公司 显示面板以及显示装置

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060081508A (ko) * 2005-01-07 2006-07-13 삼성에스디아이 주식회사 발광표시장치
CN103794179A (zh) * 2014-03-06 2014-05-14 四川虹视显示技术有限公司 一种oled驱动方法及装置
CN105140260A (zh) * 2015-07-23 2015-12-09 京东方科技集团股份有限公司 有机发光二极管阵列基板及其制作方法、显示装置
CN106252383A (zh) * 2016-09-30 2016-12-21 京东方科技集团股份有限公司 双面显示面板及其制作方法、显示装置
KR20180078793A (ko) * 2016-12-30 2018-07-10 엘지디스플레이 주식회사 플렉서블 양면형 표시장치 및 그 제조방법
CN109599057A (zh) * 2017-09-29 2019-04-09 乐金显示有限公司 双面显示器
CN111403454A (zh) * 2020-03-26 2020-07-10 武汉华星光电半导体显示技术有限公司 显示面板
CN112150970A (zh) * 2020-09-21 2020-12-29 Oppo广东移动通信有限公司 显示组件及其制备方法、显示模组和电子设备
CN113571560A (zh) * 2021-07-15 2021-10-29 Tcl华星光电技术有限公司 双面显示面板及显示装置
CN115207071A (zh) * 2022-07-25 2022-10-18 京东方科技集团股份有限公司 显示面板以及显示装置

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