WO2024021912A1 - 采样保持电路及方法 - Google Patents

采样保持电路及方法 Download PDF

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Publication number
WO2024021912A1
WO2024021912A1 PCT/CN2023/099805 CN2023099805W WO2024021912A1 WO 2024021912 A1 WO2024021912 A1 WO 2024021912A1 CN 2023099805 W CN2023099805 W CN 2023099805W WO 2024021912 A1 WO2024021912 A1 WO 2024021912A1
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WIPO (PCT)
Prior art keywords
emitter follower
hold
transistor
circuit
emitter
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PCT/CN2023/099805
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English (en)
French (fr)
Inventor
严波
罗浚洲
王悦
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普源精电科技股份有限公司
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Publication of WO2024021912A1 publication Critical patent/WO2024021912A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

Definitions

  • the present application belongs to the field of signal processing technology, and for example, relates to a sample and hold circuit and method.
  • the sample and hold circuit is connected in front of the Analog to Digital Converter (ADC). It holds the level of the input signal at the beginning of the analog/digital conversion to ensure the accuracy of the conversion. At the same time, during the analog/digital conversion After the end, it can track the changes in the input signal to receive the input at the next moment. It is indispensable for the ADC of high-speed broadband input signals, and its performance directly affects the performance of the ADC.
  • ADC Analog to Digital Converter
  • the use of SEF can meet the high bandwidth requirements of the input signal.
  • the hold stage in order to make the circuit linear High degree requires the SEF to be completely turned off, which requires the current source to be as high as possible.
  • the sample and hold circuit generally uses a fixed current source to control the current in the two stages. The high current corresponds to the track stage, and the size of the SEF changes. larger, the bandwidth becomes smaller, and there is a contradiction between bandwidth and linearity restricting each other.
  • Embodiments of the present application provide a sample and hold circuit and method, which can solve the contradiction between bandwidth and linearity that mutually restricts existing sample and hold circuits.
  • An embodiment of the present application provides a sample and hold circuit.
  • the circuit includes an input unit, a track/hold switch unit and an output unit.
  • the input unit is configured to receive a differential input signal and amplify the differential input signal before inputting it.
  • the track/hold switch unit; the track/hold switch unit is configured to track or maintain the amplified differential input signal, the track/hold switch unit includes a first emitter follower, a holding capacitor, and a shunt circuit subunit and a first current source, wherein the emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to the power supply voltage, and the first emitter
  • the base of the follower is connected to the first output terminal of the input unit, the first output terminal is configured to output one of the two amplified differential input signals, and the first emitter follower is configured to control
  • the circuit switches between a tracking state and a holding state, and the shunt circuit subunit is configured to shunt the current of the first
  • An embodiment of the present application provides a sample and hold method, which method is applied to the above-mentioned sample and hold circuit.
  • the method includes: receiving a differential input signal through an input unit, amplifying the differential input signal and then inputting it into the tracking/ Hold switch unit; track or hold the amplified differential input signal through the track/hold switch unit, wherein the track/hold switch unit includes a first emitter follower, a hold capacitor, a shunt circuit subunit and a third A current source, the emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to the power supply voltage, and the base of the first emitter follower is connected to the power supply voltage.
  • the first output terminal of the input unit is connected, the first output terminal is configured to output one of two amplified differential input signals, and the first emitter follower is configured to control the circuit in a tracking state and the holding state, the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state; output the differential output signal corresponding to the differential input signal through the output unit, which is a subsequent circuit Driving capability is provided, wherein the output unit is connected to the holding capacitor.
  • An embodiment of the present application provides a sample and hold device, which is configured to implement the above-mentioned sample and hold method.
  • the device includes: an input module configured to receive a differential input signal and amplify the differential input signal.
  • Input track/hold switch unit track/hold switch module, configured to track or maintain the amplified differential input signal, the track/hold switch unit includes a first emitter follower, a holding capacitor, a shunt circuit subunit and A first current source, wherein the emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to the power supply voltage, and the collector of the first emitter follower is connected to the power supply voltage.
  • the base is connected to a first output terminal of the input unit, the first output terminal is configured to output one of two amplified differential input signals, and the first emitter follower is configured to control the circuit Switching between the tracking state and the holding state, the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state; the output module is connected to the holding capacitor and is configured to output the The differential output signal corresponding to the differential input signal provides driving capability for subsequent circuits.
  • An embodiment of the present application provides an electronic device.
  • the electronic device includes a processor, a memory, and a program or instructions stored on the memory and executable on the processor.
  • the program or instructions are executed by the processor.
  • the steps to implement the sample-and-hold method described above are executed.
  • Embodiments of the present application provide a readable storage medium. Programs or instructions are stored on the readable storage medium. When the programs or instructions are executed by a processor, the steps of the sample and hold method as described above are implemented.
  • An embodiment of the present application provides a chip.
  • the chip includes a processor and a communication interface.
  • the communication interface is coupled to the processor.
  • the processor is configured to run a program or instructions to implement the sample and hold method as described above. A step of.
  • Figure 1 is a schematic structural diagram of a sample and hold circuit provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of another sample and hold circuit provided by an embodiment of the present application.
  • Figure 3 is a schematic flow chart of a sampling and holding method provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a sampling and holding device provided by an embodiment of the present application.
  • Figure 5 is a schematic structural diagram of an electronic device provided by this application.
  • first, second, etc. in the description and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It is to be understood that the figures so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in orders other than those illustrated or described herein, and that "first,” “second,” etc. are distinguished Objects are usually of one type, and the number of objects is not limited. For example, the first object can be one or multiple.
  • “and/or” in the description and claims indicates at least one of the connected objects, and the character “/" generally indicates that the related objects are in an "or” relationship.
  • FIG. 1 is a schematic structural diagram of a sample and hold circuit provided by an embodiment of the present application.
  • the sample and hold circuit 100 includes: an input unit 110, a track/hold switch unit 120 and an output unit 130.
  • the input unit 110 is configured to receive a differential input signal, amplify the differential input signal and then input it into the track/hold switch unit.
  • Hold switch unit; the track/hold switch unit 120 is configured to track or hold the amplified differential input signal.
  • the track/hold switch unit includes a first emitter follower, a hold capacitor, a shunt circuit subunit and A first current source, wherein the emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to the power supply voltage, and the collector of the first emitter follower is connected to the power supply voltage.
  • the base is connected to a first output terminal of the input unit, the first output terminal is configured to output one of the two amplified differential input signals, and the first emitter follower is configured to control the
  • the circuit switches between the tracking state and the holding state, and the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state;
  • the output unit 130 is connected to the holding capacitor, It is configured to output a differential output signal corresponding to the differential input signal to provide driving capability for subsequent circuits.
  • the input unit 110 receives two differential input signals VIN and VIP, amplifies them and outputs them to the track/hold switch unit 120 through ports A and B.
  • the track/hold switch unit 120 passes through the third
  • the emitters of an emitter follower Q10 and Q14 are connected to the holding capacitors C1 and C2, the collector of the first emitter follower is connected to the power supply voltage, and the base of the first emitter follower is connected to the
  • the output terminal A or B of the input unit 110 is connected to realize tracking or maintaining the two amplified differential input signals.
  • the output unit 130 is connected to the holding capacitors C1 and C2 respectively and is configured to output the The differential output signals VON and VOP corresponding to the differential input signals VIN and VIP provide driving capabilities for subsequent circuits, and in the tracking state, the currents of the first current sources I1 and I3 are shunted through the shunt circuit unit and then flow through the The first emitter followers Q10, Q14, thereby reducing the current flowing through the first emitter followers Q10, Q14.
  • the circuit size of the first emitter followers Q10, Q14 can be relatively small, relative to the port A
  • the equivalent capacitance of B and B is also reduced, which can improve the linearity of the circuit while increasing the bandwidth of the sample and hold circuit.
  • the sample and hold circuit provided in this application can achieve independent control of the two stages of tracking and holding by adding a shunt circuit subunit to the track/hold switch unit, that is, it can achieve optimal bandwidth and linearity at the same time.
  • a sample and hold circuit uses an input unit, a track/hold switch unit and an output unit.
  • the input unit is configured to receive a differential input signal, amplify the differential input signal and then input it into the tracking /hold switch unit;
  • the track/hold switch unit is configured to track or maintain the amplified differential input signal,
  • the track/hold switch unit includes a first emitter follower, a holding capacitor, a shunt circuit subunit and A first current source, wherein the emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to the power supply voltage, and the collector of the first emitter follower is connected to the power supply voltage.
  • the base is connected to a first output terminal of the input unit, the first output terminal is configured to output one of the two amplified differential input signals, and the first emitter follower is configured to control the
  • the circuit switches between the tracking state and the holding state, and the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state;
  • the output unit is connected to the holding capacitor, It is configured to output a differential output signal corresponding to the differential input signal, provide driving capability for subsequent circuits, and can solve the conflict between bandwidth and linearity that exists in the sample and hold circuit in related technologies.
  • FIG. 2 is a schematic structural diagram of another sample and hold circuit provided by an embodiment of the present application.
  • the sample and hold circuit 200 includes: an input unit 210, a track/hold switch unit 220 and an output unit 230.
  • the input unit 210 is configured to receive a differential input signal, amplify the differential input signal and then input it into the track/hold switch unit.
  • Hold switch unit; the track/hold switch unit 220 is configured to track or hold the amplified differential input signal.
  • the track/hold switch unit includes a first emitter follower, a hold capacitor, a shunt circuit subunit and A first current source, wherein the emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to the power supply voltage, and the third emitter follower is connected to the power supply voltage.
  • the base of an emitter follower is connected to the first output terminal of the input unit.
  • the first output terminal is configured to output one of the two amplified differential input signals.
  • the first emitter is configured to control the circuit to switch between the tracking state and the holding state, and the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state; the output unit 230, and The connection of the holding capacitor is configured to output a differential output signal corresponding to the differential input signal to provide driving capability for subsequent circuits.
  • the shunt circuit subunit includes two switching transistors Q5, Q6 or Q16, Q18 and two cascade transistors Q8, Q9 or Q15, Q17, wherein the collector of the first switching transistor Q5 or Q16 is connected to the first cascade transistor.
  • the emitter of Q8 or Q15 is connected, and the collector of the second switching transistor Q6 or Q18 is connected to the emitter of the second cascade transistor Q9 or Q17 to form two branches respectively.
  • the bases of the two switching transistors are connected to the clock input.
  • the terminal CKN is connected, the emitters of the two switching transistors are connected to the first current source I1 or I3, the bases of the two cascade transistors are connected to the bias voltage Vb2, and the first cascade transistor Q8 Or the collector of Q15 is connected to the emitter of the first emitter follower Q10 or Q14, and the collector of the second cascade transistor Q9 or Q17 is connected to the power supply voltage Vcc;
  • the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state, including:
  • the shunt circuit subunit is configured to control the current of the first current source to flow through the two shunts respectively when the signal at the clock input terminal is high level.
  • controlling the current of the first current source to flow through the two branches respectively includes:
  • the first switching transistors Q5 and Q6, the first cascade transistors Q8 and Q9, the second switching transistors Q18 and Q16, the second cascade transistors Both Q15 and Q17 are turned on respectively, and the current I1 or I3 of the first current source flows through the two branches respectively, wherein one current in the two branches flows through the first emitter follower.
  • the first emitter follower Q10 or Q14 is turned on to track the amplified differential input signal.
  • the first emitter follower is configured to control the circuit to switch between a tracking state and a holding state, including:
  • the track/hold switch unit 220 also includes a third switching transistor Q4 or Q13 and a third cascade transistor Q7 or Q12, wherein the base of the third switching transistor Q4 or Q13 is connected to The clock input terminal CKP, the emitter of the third switching transistor Q4 or Q13 and The first current source I1 or I3 is connected, the collector of the third switching transistor Q4 or Q13 is connected with the emitter of the third cascade transistor Q7 or Q12, and the third cascade transistor Q7 or Q12 The base is connected to the bias voltage Vb2, and the collector of the third cascade transistor Q7 or Q12 is connected to the base of the first emitter follower Q10 or Q14;
  • the circuit is in the holding state, including:
  • the third switching transistor Q4 or Q13 and the third cascade transistor Q7 or Q12 are respectively turned on, and the first emitter follower Q10 or Q14 is turned off.
  • the circuit is in the holding state.
  • I1 flows through the main switch Q10 through Q5 and Q8, and I3 flows through the main switch Q14 through Q16 and Q15.
  • the switching tubes Q10 and Q14 work in the emitter-following state, the potentials of point C and point D follow the potential changes of points A and B, the circuit is in the sampling state, and due to the shunting effect of Q6, Q9, Q17, Q18, the flow through the main circuit can be reduced.
  • the current of switch tubes Q10 and Q14 also ensures the symmetry of the two branches of CKP and CKN.
  • the circuit size of Q10 and Q14 can be relatively small, and the equivalent capacitance of nodes A and B is also reduced, which can effectively Increase the sample-and-hold bandwidth.
  • both the input unit and the output unit in the embodiment of the present application include corresponding current sources to provide appropriate currents for their circuits, such as I0, I5, I2 and I4 in Figure 2.
  • the currents provided by these current sources The values can be the same or different, and can be set depending on the situation.
  • the input unit in the above embodiment includes multiple components for amplifying the differential input signal. It may have a structure as shown in Figure 2, or may be composed of other more or less components than this structure. structure, the output unit in the above embodiment includes an emitter follower Q11 or Q19, which is connected to the holding capacitor C1 or C2 to isolate the holding capacitor from the subsequent load to provide a certain driving capability for the subsequent load. .
  • This application also provides a sample and hold method, which is applied to the sample and hold circuit as shown in Figure 1 and Figure 2, including: receiving a differential input signal through an input unit, and converting the differential input signal
  • the amplified input track/hold switch unit tracks or maintains the amplified differential input signal through the track/hold switch unit, wherein the track/hold switch unit includes a first emitter follower, a holding capacitor, a shunt
  • the circuit subunit and the first current source the emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to the power supply voltage, and the first emitter follower
  • the base of the device is connected to the first output terminal of the input unit, the first output terminal is configured to output one of the two amplified differential input signals, and the first emitter follower is configured to
  • the circuit is controlled to switch between the tracking state and the holding state, and the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state; outputting the corresponding
  • Figure 3 shows a sample and hold method provided by an embodiment of the present application. This method can be applied to the sample and hold circuit described in FIGS. 1 and 2 above, or the method can be performed by multiple functional units in the sample and hold circuit described above. In other words, the method can be executed by software or hardware of multiple functional units installed in the sample and hold circuit, and the method includes the following steps.
  • S: 301 Receive a differential input signal through the input unit, amplify the differential input signal and then input it into the track/hold switch unit.
  • the signal input terminal of the input module receives the clock source signal.
  • S302 Track or maintain the amplified differential input signal through the track/hold switch unit.
  • the track/hold switch unit includes a first emitter follower, a holding capacitor, a shunt circuit subunit and a first current source.
  • the emitter of the first emitter follower is connected to the holding capacitor.
  • the first The collector of the emitter follower is connected to the power supply voltage
  • the base of the first emitter follower is connected to the first output terminal of the input unit, and the first output terminal is configured to output two of the amplified one of the differential input signals
  • the first emitter follower is configured to control the circuit to switch between the tracking state and the hold state
  • the shunt circuit subunit is configured to switch the Current shunting of the first current source.
  • S303 Output the differential output signal corresponding to the differential input signal through an output unit to provide driving capability for subsequent circuits, where the output unit is connected to the holding capacitor.
  • the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state, including:
  • the shunt circuit subunit controls the current of the first current source to flow through two branches respectively, wherein the two branches are connected by the first switching transistor.
  • the collector is connected to the emitter of the first cascade transistor, and the collector of the second switching transistor is connected to the emitter of the second cascade transistor.
  • the shunt circuit subunit includes the two switching transistors and the Two cascaded transistors, the bases of the two switching transistors are connected to the clock input terminal, the emitters of the two switching transistors are connected to the current source, and the bases of the two cascaded transistors are connected to the bias The voltage is set, the collector of the first cascade transistor is connected to the emitter of the first emitter follower, and the collector of the second cascade transistor is connected to the power supply voltage.
  • the shunt circuit subunit controls the current of the first current source to flow through two branches respectively, including:
  • the first switching transistor, the first cascade transistor, the second switching transistor, and the second cascade transistor are all turned on respectively, and the current source Current flows through the two branches respectively, wherein one current in the two branches flows through the first emitter follower, causing the first emitter follower to conduct to track the amplification differential input signal.
  • the first emitter follower is configured to control the circuit to switch between a tracking state and a holding state, including:
  • the circuit is controlled to be in the holding state.
  • controlling the circuit to be in the holding state when the first emitter follower is turned off includes:
  • the track/hold switch unit further includes a third switching transistor and a third cascade transistor, the base of the third switching transistor is connected to the clock input terminal, and the emitter of the third switching transistor is connected to the clock input terminal.
  • the first current source is connected, the collector of the third switching transistor is connected to the emitter of the third cascade transistor, the base of the third cascade transistor is connected to the bias voltage, and the third cascade transistor has a base connected to the bias voltage.
  • the collector of the three-cascode transistor is connected to the base of the first emitter follower.
  • a sample and hold method provided by an embodiment of the present application includes receiving a differential input signal through an input unit, amplifying the differential input signal and inputting it into a track/hold switch unit; tracking or maintaining the amplified signal through the track/hold switch unit
  • the differential input signal after Keep the capacitor connected and connect the collector of the first emitter follower to the power supply voltage, the base of the first emitter follower is connected to the first output terminal of the input unit, and the first output terminal is configured to output one of the two amplified differential input signals, so
  • the first emitter follower is configured to control the circuit to switch between a tracking state and a holding state, and the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state; through the output
  • the unit outputs a differential output signal corresponding to the differential input signal to provide driving capability for subsequent circuits.
  • the output unit is connected to the holding capacitor, which can solve the mutual constraints between bandwidth and linearity of the sampling and holding circuit in related technologies. contradiction.
  • the execution subject may be a sampling and holding device, or a control module in the sampling and holding device configured to execute the sampling and holding method.
  • the sampling and holding device performing the sampling and holding method is taken as an example to illustrate the sampling and holding device provided by the embodiment of the present application.
  • Figure 4 shows a schematic structural diagram of a sampling and holding device provided by an embodiment of the present application.
  • the sample and hold device 400 includes: an input module 410, configured to receive a differential input signal, amplify the differential input signal and input it into the track/hold switch unit; a track/hold switch module 420, configured to Track or maintain the amplified differential input signal, the track/hold switch unit includes a first emitter follower, a holding capacitor, a shunt circuit subunit and a first current source, wherein the first emitter follower The emitter is connected to the holding capacitor, the collector of the first emitter follower is connected to the power supply voltage, and the base of the first emitter follower is connected to the first output end of the input unit, so
  • the first output terminal is configured to output one of the two amplified differential input signals, the first emitter follower is configured to control the circuit to switch between a tracking state and a hold state, and the shunt The circuit subunit is configured to shunt the current of the first current source in the
  • the shunt circuit subunit includes two switching transistors and two cascaded transistors.
  • the two switching transistors are a first switching transistor and a second switching transistor respectively.
  • the two cascaded transistors They are a first cascade transistor and a second cascade transistor respectively, wherein the collector of the first switching transistor is connected to the emitter of the first cascade transistor, and the collector of the second switching transistor is connected to the emitter of the second cascade transistor.
  • the connections form two branches respectively, the bases of the two switching transistors are connected to the clock input terminals, the emitters of the two switching transistors are connected to the first current source, and the bases of the two cascade transistors are connected to each other.
  • the collector of the first cascade transistor is connected to the emitter of the first emitter follower, and the collector of the second cascade transistor is connected to the power supply voltage;
  • the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state, including:
  • the shunt circuit subunit is configured to control when the signal at the clock input terminal is high level.
  • the current of the first current source flows through the two branches respectively.
  • controlling the current of the first current source to flow through the two branches respectively includes:
  • the first switching transistor, the first cascade transistor, the second switching transistor, and the second cascade transistor are all turned on respectively, and the first The current of the current source flows through the two branches respectively, wherein one current in the two branches flows through the first emitter follower, causing the first emitter follower to conduct to track The amplified differential input signal.
  • the first emitter follower is configured to control the circuit to switch between tracking and holding states, including:
  • the track/hold switch unit further includes a third switching transistor and a third cascade transistor, wherein the base of the third switching transistor is connected to the clock input terminal, and the third switching transistor The emitter of the switching transistor is connected to the first current source, the collector of the third switching transistor is connected to the emitter of the third cascade transistor, and the base of the third cascade transistor is connected to the Bias voltage, the collector of the third cascade transistor is connected to the base of the first emitter follower;
  • the circuit is in the holding state, including:
  • the third switching transistor and the third cascade transistor are respectively turned on, the first emitter follower is turned off, and the circuit is in the holding state.
  • sampling and holding device in the embodiment of the present application may be a device, or may be a component, integrated circuit, or chip in a terminal, which is not limited in the embodiment of the present application.
  • sampling and holding device in the embodiment of the present application may be a device with an operating system, or may be other possible operating systems, which are not limited by the embodiment of the present application.
  • sample and hold device provided by the embodiment of the present application can realize the functions of corresponding multiple units in the sample and hold circuit of Figures 1 to 2, or implement multiple processes implemented in the sample and hold method embodiment of Figure 3. To avoid duplication, no details are included here. Again.
  • this embodiment of the present application also provides an electronic device 500, including a processor 501, a memory 502, and programs or instructions stored on the memory 502 and executable on the processor 501.
  • the program or instructions are executed by the processor 501: receiving differential input signals through the input unit and amplify the differential input signal and input it into the track/hold switch unit; track or maintain the amplified differential input signal through the track/hold switch unit, wherein the track/hold switch unit includes a first Emitter follower, holding capacitor, shunt circuit subunit and first current source, the emitter of the first emitter follower is connected to the holding capacitor, and the collector of the first emitter follower is connected to the power supply voltage, the base of the first emitter follower is connected to the first output terminal of the input unit, and the first output terminal is configured to output one of the two amplified differential input signals, so
  • the first emitter follower is configured to control the circuit to switch between a tracking state and a holding state, and the shunt circuit subunit is configured
  • Embodiments of the present application also provide a readable storage medium. Programs or instructions are stored on the readable storage medium. When the program or instructions are executed by a processor, the multiple processes of the above sample and hold method embodiments are implemented. In order to avoid duplication , we won’t go into details here.
  • the processor is the processor in the electronic device described in the above embodiment.
  • the readable storage media includes computer-readable storage media, such as computer read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disks or optical disks, etc.
  • An embodiment of the present application also provides a chip.
  • the chip includes a processor and a communication interface.
  • the communication interface is coupled to the processor.
  • the processor is configured to run a program or instructions to implement the above embodiment of the sample and hold method.
  • chips mentioned in the embodiments of this application may also be called system-on-chip, system-on-a-chip, system-on-a-chip or system-on-chip, etc.
  • embodiments of the present application may be provided as methods, devices, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Moreover, this application may use one or more computer-usable storage media (including but not limited to magnetic disk storage, read-only compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical memory) containing computer-usable program code. etc.) in the form of a computer program product implemented on.
  • computer-usable storage media including but not limited to magnetic disk storage, read-only compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical memory
  • CD-ROM Compact Disc Read-Only Memory
  • optical memory containing computer-usable program code. etc.
  • These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions
  • the device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.
  • the electronic device includes one or more central processing units (CPUs), input/output interfaces, network interfaces, and memory.
  • CPUs central processing units
  • input/output interfaces input/output interfaces
  • network interfaces network interfaces
  • memory volatile and non-volatile memory
  • Memory may include non-permanent storage in computer-readable media, RAM and/or non-volatile memory in the form of ROM or flash RAM. Memory is an example of computer-readable media.
  • Computer-readable media includes both persistent and non-volatile, removable and non-removable media that can be implemented by any method or technology for storage of information.
  • Information may be computer-readable instructions, data structures, modules of programs, or other data.
  • Examples of computer storage media include, but are not limited to, Phase-change Random Access Memory (PRAM), Static Random Access Memory (Static Random Access Memory, SRAM), Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM), other types of RAM, ROM, Electrically-Erasable Programmable Read-Only Memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc ( Digital Video Disc, DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage device or any other non-transmission medium may be used to store information that can be accessed by a computing device.
  • computer-readable media does not include transitory media, such as modulated data signals and carrier waves.

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Abstract

本申请公开了一种采样保持电路及方法，属于信号处理技术领域。所述电路包括输入单元、跟踪/保持开关单元和输出单元，所述输入单元，设置为接收差分输入信号，并将所述差分输入信号放大后输入所述跟踪/保持开关单元；所述跟踪/保持开关单元，设置为跟踪或保持所述放大后的差分输入信号，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，其中，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个放大后的差分输入信号中的一者。

Description

采样保持电路及方法
本申请要求在2022年07月27日提交中国专利局、申请号为202210893948.9的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于信号处理技术领域，例如涉及一种采样保持电路及方法。
背景技术
采样保持电路连接在模拟数字转换器(Analog to Digital Converter，ADC)前，其在模/数转换开始时，将输入信号的电平保持住，以保证转换的准确性，同时在模/数转换结束后又能跟踪输入信号的变化，以接收下一时刻的输入，它对于高速宽带输入信号的ADC是不可或缺的，其性能直接影响了ADC的性能。
具有开关射极跟随器(Switched Emitter Follower，SEF)结构的采样保持电路在跟踪(track)阶段，SEF的使用可以满足输入信号高带宽的需求，而在保持(hold)阶段，为了使电路的线性度高，需要将SEF彻底关断，这就需要电流源的电流尽量高，而采样保持电路一般使用一个固定的电流源来控制两个阶段的电流，高的电流对应track阶段，SEF的尺寸变大，带宽变小，存在带宽和线性度相互制约的矛盾。
发明内容
本申请实施例提供了一种采样保持电路及方法，能够解决现有采样保持电路存在的带宽与线性度相互制约的矛盾。
本申请实施例提供了一种采样保持电路，所述电路包括输入单元、跟踪/保持开关单元和输出单元，所述输入单元，设置为接收差分输入信号，并将所述差分输入信号放大后输入所述跟踪/保持开关单元；所述跟踪/保持开关单元，设置为跟踪或保持所述放大后的差分输入信号，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，其中，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；所述输出单元，与所述保持电容的连接，设置为输出所述差分输入信号对应的差分输出信号，为后 续电路提供驱动能力。
本申请实施例提供了一种采样保持方法，所述方法应用于上述所述的采样保持电路，所述方法包括：通过输入单元接收差分输入信号，并将所述差分输入信号放大后输入跟踪/保持开关单元；通过所述跟踪/保持开关单元跟踪或保持所述放大后的差分输入信号，其中，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；通过输出单元输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力，其中，所述输出单元与所述保持电容连接。
本申请实施例提供了一种采样保持装置，所述装置设置为实现上述所述的采样保持方法，所述装置包括：输入模块，设置为接收差分输入信号，并将所述差分输入信号放大后输入跟踪/保持开关单元；跟踪/保持开关模块，设置为跟踪或保持所述放大后的差分输入信号，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，其中，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；输出模块，与所述保持电容的连接，设置为输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力。
本申请实施例提供了一种电子设备，该电子设备包括处理器、存储器及存储在所述存储器上并可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如上所述的采样保持方法的步骤。
本申请实施例提供了一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如上所述的采样保持方法的步骤。
本申请实施例提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器设置为运行程序或指令，实现如上所述的采样保持方法的步骤。
附图说明
图1是本申请实施例提供的一种采样保持电路的结构示意图；
图2是本申请实施例提供的另一种采样保持电路的结构示意图；
图3是本申请实施例提供的一种采样保持方法的示意性流程图；
图4是本申请实施例提供的一种采样保持装置的结构示意图；
图5是本申请提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例是本申请一部分实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
下面结合附图，通过实施例及其应用场景对本申请实施例提供的一种采样保持电路及方法进行说明。
图1为本申请实施例提供的一种采样保持电路的结构示意图。所述采样保持电路100包括：输入单元110、跟踪/保持开关单元120和输出单元130，所述输入单元110，设置为接收差分输入信号，并将所述差分输入信号放大后输入所述跟踪/保持开关单元；所述跟踪/保持开关单元120，设置为跟踪或保持所述放大后的差分输入信号，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，其中，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个所述放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；所述输出单元130，与所述保持电容连接，设置为输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力。
如图1所示，输入单元110接收两个差分输入信号VIN和VIP，并将其放大后通过端口A和B输出至跟踪/保持开关单元120，所述跟踪/保持开关单元120通过所述第一射极跟随器Q10、Q14的发射极与所述保持电容C1、C2连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元110的输出端A或B连接，实现对两个所述放大后的差分输入信号进行跟踪或保持，所述输出单元130与所述保持电容C1、C2分别连接，设置为输出所述差分输入信号VIN和VIP对应的差分输出信号VON和VOP，为后续电路提供驱动能力，且在跟踪状态下，通过分流电路单元将所述第一电流源I1、I3的电流分流后流过所述第一射极跟随器Q10、Q14，从而减小流过所述第一射极跟随器Q10、Q14的电流，所述第一射极跟随器Q10、Q14电路尺寸可以比较小，相对于端口A和B的等效电容也减小，能够在提高采样保持电路带宽的同时提高电路的线性度。
本申请提供的采样保持电路，通过在跟踪/保持开关单元增加分流电路子单元，能够实现跟踪和保持两个阶段的独立控制，即可以同时兼顾带宽和线性度这两个性能都达到较优。
本申请实施例提供的一种采样保持电路，通过输入单元、跟踪/保持开关单元和输出单元，所述输入单元，设置为接收差分输入信号，并将所述差分输入信号放大后输入所述跟踪/保持开关单元；所述跟踪/保持开关单元，设置为跟踪或保持所述放大后的差分输入信号，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，其中，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个所述放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；所述输出单元，与所述保持电容的连接，设置为输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力，能够解决相关技术中采样保持电路存在的带宽与线性度相互制约的矛盾。
如图2所示的本申请实施例提供的另一种采样保持电路的结构示意图。所述采样保持电路200包括：输入单元210、跟踪/保持开关单元220和输出单元230，所述输入单元210，设置为接收差分输入信号，并将所述差分输入信号放大后输入所述跟踪/保持开关单元；所述跟踪/保持开关单元220，设置为跟踪或保持所述放大后的差分输入信号，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，其中，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第 一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个所述放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；所述输出单元230，与所述保持电容的连接，设置为输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力。
所述分流电路子单元包括两个开关晶体管Q5、Q6或Q16、Q18和两个级联晶体管Q8、Q9或Q15、Q17，其中，第一开关晶体管Q5或Q16的集电极与第一级联晶体管Q8或Q15的发射极连接，第二开关晶体管Q6或Q18的集电极与第二级联晶体管Q9或Q17的发射极连接分别形成两个分路，所述两个开关晶体管的基极与时钟输入端CKN连接，所述两个开关晶体管的发射极与所述第一电流源I1或I3连接，所述两个级联晶体管的基极接入偏置电压Vb2，所述第一级联晶体管Q8或Q15的集电极与所述第一射极跟随器Q10或Q14的发射极连接，所述第二级联晶体管Q9或Q17的集电极接入电源电压Vcc；
所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流，包括：
所述分流电路子单元，设置为在所述时钟输入端的信号为高电平时，控制所述第一电流源的电流分别流过所述两个分路。
在一种实现方式中，所述在所述时钟输入端的信号为高电平时，控制所述第一电流源的电流分别流过所述两个分路，包括：
在所述时钟输入端的信号为高电平时，所述第一开关晶体管Q5、Q6、所述第一级联晶体管Q8、Q9、所述第二开关晶体管Q18、Q16、所述第二级联晶体管Q15、Q17都分别导通，所述第一电流源的电流I1或I3分别流过所述两个分路，其中，所述两个分路中的一路电流流过所述第一射极跟随器Q10或Q14，使所述第一射极跟随器Q10或Q14导通以跟踪所述放大后的差分输入信号。
在一种实现方式中，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，包括：
在所述第一射极跟随器导通的情况下，所述电路处于所述跟踪状态；
和/或，
在所述第一射极跟随器关断的情况下，所述电路处于所述保持状态。
在一种实现方式中，所述跟踪/保持开关单元220，还包括第三开关晶体管Q4或Q13和第三级联晶体管Q7或Q12，其中，所述第三开关晶体管Q4或Q13的基极连接所述时钟输入端CKP，所述第三开关晶体管Q4或Q13的发射极与 所述第一电流源I1或I3连接，所述第三开关晶体管Q4或Q13的集电极与所述第三级联晶体管Q7或Q12的发射极连接，所述第三级联晶体管Q7或Q12的基极接入所述偏置电压Vb2，所述第三级联晶体管Q7或Q12的集电极与所述第一射极跟随器Q10或Q14的基极连接；
所述在所述第一射极跟随器关断的情况下，所述电路处于所述保持状态，包括：
在所述时钟输入端的信号为低电平时，所述第三开关晶体管Q4或Q13、所述第三级联晶体管Q7或Q12分别导通，所述第一射极跟随器Q10或Q14关断，所述电路处于所述保持状态。
当CKP的信号为高电平，CKN的信号为低电平时，Q4、Q7、Q12、Q13导通，I1和I3分别流过R0和R1，使得A、B点电位变得更低，同时Q8、Q5、Q15、Q16关断，由于电容C1和C2的保持作用，C点和D点的电位保持不变，从而Q10、Q14关断，电路处于保持状态；当CKP的信号为低电平，CKN的信号为高电平时，Q4、Q7、Q12、Q13截止，A点和B节点恢复正常高电位，I1通过Q5、Q8流过主开关管Q10，I3通过Q16、Q15流过主开关管Q14，开关管Q10、Q14工作在射随状态，C点和D点电位跟随A和B点电位变化，电路处于采样状态，并且由于Q6、Q9、Q17、Q18的分流作用，可以减小流过主开关管Q10、Q14的电流，同时又保证CKP和CKN的两条支路的对称性，Q10、Q14的电路尺寸可以比较小，相对于节点A和节点B的等效电容也减小，能有效提高采样保持器的带宽。
需要说明的是，本申请实施例中的输入单元和输出单元都包含有相应的电流源为其电路提供合适的电流，如图2中的I0、I5、I2和I4，这些电流源提供的电流值可以相同或不同，也可以根据情况设置。
另外，上述实施例中的输入单元包含用于将差分输入信号放大的多个部件，可以是如图2中示出的结构，也可以是由其他比该结构更多或更少的部件组成的结构，上述实施例中的输出单元包含一个射极跟随器Q11或Q19，其通过与保持电容C1或C2连接，能够实现将所述保持电容与后续负载的隔离，以为后续负载提供一定的驱动能力。
还需说明的是，由于第一射极跟随器Q10和Q14中结电容的存在，开关再开启和关断瞬间会产生电压馈通，故可以使用如图2所示的补偿电容Cf1和Cf2进行馈通前馈补偿，能够抵消馈通所带来的干扰，使采样保持的波形更加理想。
本申请另提供一种采样保持方法，所述方法应用于如图1和图2所述的采样保持电路，包括：通过输入单元接收差分输入信号，并将所述差分输入信号 放大后输入跟踪/保持开关单元；通过所述跟踪/保持开关单元跟踪或保持所述放大后的差分输入信号，其中，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个所述放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；通过输出单元输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力，其中，所述输出单元与所述保持电容连接。
下面结合附图，通过实施例及其应用场景对本申请实施例提供的一种采样保持方法进行说明。
图3示出了本申请实施例提供的一种采样保持方法。该方法可以应用于上述图1和图2所述的采样保持电路，或该方法可以由上述采样保持电路中的多个功能单元执行。换言之，该方法可以由安装在该采样保持电路中的多个功能单元的软件或硬件来执行，该方法包括如下步骤。
S:301：通过输入单元接收差分输入信号，并将所述差分输入信号放大后输入跟踪/保持开关单元。
所述输入模块的信号输入端接收所述时钟源信号。
S302：通过所述跟踪/保持开关单元跟踪或保持所述放大后的差分输入信号。
所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个所述放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流。
S303：通过输出单元输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力，其中，所述输出单元与所述保持电容连接。
在一种实现方式中，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流，包括：
通过所述分流电路子单元在所述时钟输入端的信号为高电平时，控制所述第一电流源的电流分别流过两个分路，其中，所述两个分路由第一开关晶体管 的集电极与第一级联晶体管的发射极连接、第二开关晶体管的集电极与第二级联晶体管的发射极连接分别形成，所述分流电路子单元包括所述两个开关晶体管和所述两个级联晶体管，所述两个开关晶体管的基极与时钟输入端连接，所述两个开关晶体管的发射极与所述电流源连接，所述两个级联晶体管的基极接入偏置电压，所述第一级联晶体管的集电极与所述第一射极跟随器的发射极连接，所述第二级联晶体管的集电极接入电源电压。
在一种实现方式中，所述通过所述分流电路子单元在所述时钟输入端的信号为高电平时，控制所述第一电流源的电流分别流过两个分路，包括：
在所述时钟输入端的信号为高电平时，所述第一开关晶体管、所述第一级联晶体管、所述第二开关晶体管、所述第二级联晶体管都分别导通，所述电流源电流分别流过所述两个分路，其中，所述两个分路中的一路电流流过所述第一射极跟随器，使所述第一射极跟随器导通以跟踪所述放大后的差分输入信号。
在一种实现方式中，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，包括：
在所述第一射极跟随器导通的情况下，控制所述电路处于所述跟踪状态；
和/或，
在所述第一射极跟随器关断的情况下，控制所述电路里处于所述保持状态。
在一种实现方式中，所述在所述第一射极跟随器关断的情况下，控制所述电路处于所述保持状态，包括：
在所述时钟输入端的信号为低电平时，所述第三开关晶体管、所述第三级联晶体管分别导通，所述第一射极跟随器关断，控制所述电路处于所述保持状态，其中，所述跟踪/保持开关单元还包括第三开关晶体管和第三级联晶体管，所述第三开关晶体管的基极连接所述时钟输入端，所述第三开关晶体管的发射极与所述第一电流源连接，所述第三开关晶体管的集电极与所述第三级联晶体管的发射极连接，所述第三级联晶体管的基极接入所述偏置电压，所述第三级联晶体管的集电极与所述第一射极跟随器的基极连接。
上述步骤的实施可参见图1和图2采样保持电路相关功能单元的描述，为避免重复，这里不再赘述。
本申请实施例提供的一种采样保持方法，通过输入单元接收差分输入信号，并将所述差分输入信号放大后输入跟踪/保持开关单元；通过所述跟踪/保持开关单元跟踪或保持所述放大后的差分输入信号，其中，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源 电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个所述放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；通过输出单元输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力，其中，所述输出单元与所述保持电容连接，能够解决相关技术中采样保持电路存在的带宽与线性度相互制约的矛盾。
需要说明的是，本申请实施例提供的采样保持方法，执行主体可以为采样保持装置，或者该采样保持装置中的设置为执行采样保持方法的控制模块。本申请实施例中以采样保持装置执行采样保持方法为例，说明本申请实施例提供的采样保持装置。
图4示出本申请的一个实施例提供的一种采样保持装置的结构示意图。如图4所示，采样保持装置400包括：输入模块410，设置为接收差分输入信号，并将所述差分输入信号放大后输入所述跟踪/保持开关单元；跟踪/保持开关模块420，设置为跟踪或保持所述放大后的差分输入信号，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，其中，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个所述放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；输出模块430，与所述保持电容的连接，设置为输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力。
在一种实现方式中，所述分流电路子单元包括两个开关晶体管和两个级联晶体管，所述两个开关晶体管分别为第一开关晶体管和第二开关晶体管，所述两个级联晶体管分别为第一级联晶体管和第二级联晶体管，其中，第一开关晶体管的集电极与第一级联晶体管的发射极连接和第二开关晶体管的集电极与第二级联晶体管的发射极连接分别形成两个分路，所述两个开关晶体管的基极与时钟输入端连接，所述两个开关晶体管的发射极与所述第一电流源连接，所述两个级联晶体管的基极接入偏置电压，所述第一级联晶体管的集电极与所述第一射极跟随器的发射极连接，所述第二级联晶体管的集电极接入电源电压；
所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流，包括：
所述分流电路子单元，设置为在所述时钟输入端的信号为高电平时，控制 所述第一电流源的电流分别流过所述两个分路。
在一种实现方式中，所述在所述时钟输入端的信号为高电平时，控制所述第一电流源的电流分别流过所述两个分路，包括：
在所述时钟输入端的信号为高电平时，所述第一开关晶体管、所述第一级联晶体管、所述第二开关晶体管、所述第二级联晶体管都分别导通，所述第一电流源的电流分别流过所述两个分路，其中，所述两个分路中的一路电流流过所述第一射极跟随器，使所述第一射极跟随器导通以跟踪所述放大后的差分输入信号。
在一种实现方式中，所述第一射极跟随器设置为控制所述电路在跟踪和保持两个状态之间切换，包括：
在所述第一射极跟随器导通的情况下，所述电路处于所述跟踪状态；
和/或，
在所述第一射极跟随器关断的情况下，所述电路处于所述保持状态。
在一种实现方式中，所述跟踪/保持开关单元，还包括第三开关晶体管和第三级联晶体管，其中，所述第三开关晶体管的基极连接所述时钟输入端，所述第三开关晶体管的发射极与所述第一电流源连接，所述第三开关晶体管的集电极与所述第三级联晶体管的发射极连接，所述第三级联晶体管的基极接入所述偏置电压，所述第三级联晶体管的集电极与所述第一射极跟随器的基极连接；
所述在所述第一射极跟随器关断的情况下，所述电路处于所述保持状态，包括：
在所述时钟输入端的信号为低电平时，所述第三开关晶体管、所述第三级联晶体管分别导通，所述第一射极跟随器关断，所述电路处于所述保持状态。
本申请实施例中的采样保持装置可以是装置，也可以是终端中的部件、集成电路、或芯片，本申请实施例不作限定。
本申请实施例中的采样保持装置可以为具有操作系统的装置，还可以为其他可能的操作系统，本申请实施例不作限定。
本申请实施例提供的采样保持装置能够实现图1至2的采样保持电路中相应多个单元的功能，或实现图3的采样保持方法实施例中实现的多个过程，为避免重复，这里不再赘述。
可选的，如图5所示，本申请实施例还提供一种电子设备500，包括处理器501，存储器502，存储在存储器502上并可在所述处理器501上运行的程序或指令，该程序或指令被处理器501执行时实现：通过输入单元接收差分输入信 号，并将所述差分输入信号放大后输入跟踪/保持开关单元；通过所述跟踪/保持开关单元跟踪或保持所述放大后的差分输入信号，其中，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个所述放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；通过输出单元输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力，其中，所述输出单元与所述保持电容连接。
需要说明的是，本说明书中关于电子设备的实施例与本说明书中关于采样保持电路的实施例基于同一发明构思，因此该实施例的实施可以参见前述对应的采样保持电路的实施，重复之处不再赘述。
本申请实施例还提供一种可读存储介质，所述可读存储介质上存储有程序或指令，该程序或指令被处理器执行时实现上述采样保持方法实施例的多个过程，为避免重复，这里不再赘述。
所述处理器为上述实施例中所述的电子设备中的处理器。所述可读存储介质，包括计算机可读存储介质，如计算机只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等。
本申请实施例还提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器设置为运行程序或指令，实现上述采样保持方法实施例的多个过程，或实现上述采样保持电路或采样保持装置实施例的多个模块的功能，为避免重复，这里不再赘述。
应理解，本申请实施例提到的芯片还可以称为系统级芯片、系统芯片、芯片系统或片上系统芯片等。
本领域内的技术人员应明白，本申请的实施例可提供为方法、装置、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用包含有计算机可用程序代码的一个或多个计算机可用存储介质(包括但不限于磁盘存储器、只读光盘只读存储器(Compact Disc Read-Only Memory，CD-ROM)、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框 图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生设置为实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
在一个配置中，电子设备包括一个或多个中央处理器(Central Processing Unit，CPU)、输入/输出接口、网络接口和内存。
内存可能包括计算机可读介质中的非永久性存储器，RAM和/或非易失性内存等形式，如ROM或闪存(flash RAM)。内存是计算机可读介质的示例。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(Phase-change Random Access Memory，PRAM)、静态随机存取存储器(Static Random Access Memory，SRAM)、动态随机存取存储器(Dynamic Random Access Memory，DRAM)、其他类型的RAM、ROM、电可擦除可编程只读存储器(Electrically-Erasable Programmable Read-Only Memory，EEPROM)、快闪记忆体或其他内存技术、CD-ROM、数字多功能光盘(Digital Video Disc，DVD)或其他光学存储、磁盒式磁带，磁带磁磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。

Claims (10)

  1. 一种采样保持电路，包括输入单元、跟踪/保持开关单元和输出单元，所述输入单元，设置为接收差分输入信号，并将所述差分输入信号放大后输入所述跟踪/保持开关单元；
    所述跟踪/保持开关单元，设置为跟踪或保持所述放大后的差分输入信号，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，其中，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；
    所述输出单元，与所述保持电容连接，设置为输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力。
  2. 根据权利要求1所述的采样保持电路，其中，所述分流电路子单元包括两个开关晶体管和两个级联晶体管，所述两个开关晶体管分别为第一开关晶体管和第二开关晶体管，所述两个级联晶体管分别为第一级联晶体管和第二级联晶体管，其中，所述第一开关晶体管的集电极与所述第一级联晶体管的发射极连接和所述第二开关晶体管的集电极与所述第二级联晶体管的发射极连接，并分别形成两个分路，所述两个开关晶体管的基极与时钟输入端连接，所述两个开关晶体管的发射极与所述第一电流源连接，所述两个级联晶体管的基极接入偏置电压，所述第一级联晶体管的集电极与所述第一射极跟随器的发射极连接，所述第二级联晶体管的集电极接入所述电源电压；
    所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流，包括：
    所述分流电路子单元，设置为在所述时钟输入端的信号为高电平的情况下，控制所述第一电流源的电流分别流过所述两个分路。
  3. 根据权利要求2所述的采样保持电路，其中，所述在所述时钟输入端的信号为高电平的情况下，控制所述第一电流源的电流分别流过所述两个分路，包括：
    在所述时钟输入端的信号为高电平的情况下，所述第一开关晶体管、所述第一级联晶体管、所述第二开关晶体管、所述第二级联晶体管都分别导通，所述第一电流源的电流分别流过所述两个分路，其中，所述两个分路中的一路电流流过所述第一射极跟随器，使所述第一射极跟随器导通以跟踪所述放大后的 差分输入信号。
  4. 根据权利要求1所述的采样保持电路，其中，所述第一射极跟随器设置为控制所述电路在跟踪和保持两个状态之间切换，包括以下至少之一：
    在所述第一射极跟随器导通的情况下，所述电路处于所述跟踪状态；
    在所述第一射极跟随器关断的情况下，所述电路处于所述保持状态。
  5. 根据权利要求4所述的采样保持电路，其中，所述跟踪/保持开关单元，还包括第三开关晶体管和第三级联晶体管，其中，所述第三开关晶体管的基极连接时钟输入端，所述第三开关晶体管的发射极与所述第一电流源连接，所述第三开关晶体管的集电极与所述第三级联晶体管的发射极连接，所述第三级联晶体管的基极接入偏置电压，所述第三级联晶体管的集电极与所述第一射极跟随器的基极连接；
    所述在所述第一射极跟随器关断的情况下，所述电路处于所述保持状态，包括：
    在所述时钟输入端的信号为低电平的情况下，所述第三开关晶体管、所述第三级联晶体管分别导通，所述第一射极跟随器关断，所述采样保持电路处于所述保持状态。
  6. 一种采样保持方法，应用于如权利要求1-5中任一项所述的采样保持电路，包括：
    通过输入单元接收差分输入信号，并将所述差分输入信号放大后输入跟踪/保持开关单元；
    通过所述跟踪/保持开关单元跟踪或保持所述放大后的差分输入信号，其中，所述跟踪/保持开关单元包括第一射极跟随器、保持电容、分流电路子单元和第一电流源，所述第一射极跟随器的发射极与所述保持电容连接，所述第一射极跟随器的集电极接入电源电压，所述第一射极跟随器的基极与所述输入单元的第一输出端连接，所述第一输出端设置为输出两个放大后的差分输入信号中的一者，所述第一射极跟随器设置为控制所述电路在跟踪状态和保持状态之间切换，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流；
    通过输出单元输出所述差分输入信号对应的差分输出信号，为后续电路提供驱动能力，其中，所述输出单元与所述保持电容连接。
  7. 根据权利要求6所述的采样保持方法，其中，所述分流电路子单元设置为在所述跟踪状态下将所述第一电流源的电流分流，包括：
    通过所述分流电路子单元在时钟输入端的信号为高电平的情况下，控制所述第一电流源的电流分别流过两个分路，其中，所述两个分路由第一开关晶体管的集电极与第一级联晶体管的发射极连接、第二开关晶体管的集电极与第二级联晶体管的发射极连接分别形成，所述分流电路子单元包括所述两个开关晶体管和所述两个级联晶体管，所述两个开关晶体管的基极与所述时钟输入端连接，所述两个开关晶体管的发射极与所述电流源连接，所述两个级联晶体管的基极接入偏置电压，所述第一级联晶体管的集电极与所述第一射极跟随器的发射极连接，所述第二级联晶体管的集电极接入所述电源电压。
  8. 根据权利要求7所述的采样保持方法，其中，所述通过所述分流电路子单元在时钟输入端的信号为高电平的情况下，控制所述第一电流源的电流分别流过两个分路，包括：
    在所述时钟输入端的信号为高电平的情况下，所述第一开关晶体管、所述第一级联晶体管、所述第二开关晶体管、所述第二级联晶体管都分别导通，所述电流源的电流分别流过所述两个分路，其中，所述两个分路中的一路电流流过所述第一射极跟随器，使所述第一射极跟随器导通以跟踪所述放大后的差分输入信号。
  9. 根据权利要求6所述的采样保持方法，其中，所述第一射极跟随器设置为控制所述电路在跟踪和保持两个状态之间切换，包括以下至少之一：
    在所述第一射极跟随器导通的情况下，控制所述电路处于所述跟踪状态；
    在所述第一射极跟随器关断的情况下，控制所述电路里处于所述保持状态。
  10. 根据权利要求9所述的采样保持方法，其中，所述在所述第一射极跟随器关断的情况下，控制所述电路处于所述保持状态，包括：
    在时钟输入端的信号为低电平的情况下，第三开关晶体管、第三级联晶体管分别导通，所述第一射极跟随器关断，控制所述电路处于所述保持状态，其中，所述跟踪/保持开关单元还包括所述第三开关晶体管和所述第三级联晶体管，所述第三开关晶体管的基极连接时钟输入端，所述第三开关晶体管的发射极与所述第一电流源连接，所述第三开关晶体管的集电极与所述第三级联晶体管的发射极连接，所述第三级联晶体管的基极接入偏置电压，所述第三级联晶体管的集电极与所述第一射极跟随器的基极连接。
PCT/CN2023/099805 2022-07-27 2023-06-13 采样保持电路及方法 WO2024021912A1 (zh)

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