WO2024016792A1 - 记忆芯片防误写控制方法、装置及用电设备 - Google Patents

记忆芯片防误写控制方法、装置及用电设备 Download PDF

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Publication number
WO2024016792A1
WO2024016792A1 PCT/CN2023/092506 CN2023092506W WO2024016792A1 WO 2024016792 A1 WO2024016792 A1 WO 2024016792A1 CN 2023092506 W CN2023092506 W CN 2023092506W WO 2024016792 A1 WO2024016792 A1 WO 2024016792A1
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Prior art keywords
memory chip
data
writing
main control
chip
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PCT/CN2023/092506
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English (en)
French (fr)
Inventor
黄健
杨华生
邹宏亮
李志逢
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珠海格力电器股份有限公司
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Publication of WO2024016792A1 publication Critical patent/WO2024016792A1/zh

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3468Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3481Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming

Definitions

  • the present disclosure relates to a memory chip anti-miswriting control method, device and electrical equipment.
  • EEPROM Electrically Erasable Programmable Read Only Memory
  • Electrical equipment such as air conditioners, washing machines, etc.
  • EEPROM Electrical equipment
  • Miswriting to the memory chip and writing incorrect data will cause the equipment to operate abnormally.
  • the device controller motherboard is powered off and in a low-voltage state, it is easy to cause erroneous writing operations to the memory chip.
  • the minimum operating voltage of the main control chip is higher than the minimum operating voltage of the memory chip (EEPROM).
  • EEPROM the minimum operating voltage of the memory chip
  • the main control chip causes abnormality in its RAM (Random Access Memory) data due to low voltage, but the memory chip can still be written normally, causing the memory chip to be damaged. Wrong writing.
  • Embodiments of the present disclosure provide a memory chip anti-miswriting control method, device and electrical equipment, so as to at least solve the problem that the main control chip of the device may miswrite the memory chip when the power is off.
  • a memory chip anti-accidental writing control method which includes:
  • the memory chip When there is a new writing requirement, after a first preset time delay, the memory chip is updated according to the recorded page number. perform write operations;
  • the first preset time is greater than or equal to the time required for the lowest operating voltage of the main control chip to drop to the lowest operating voltage of the memory chip after power-off.
  • the method further includes:
  • the second preset time is less than the first preset time.
  • the method further includes:
  • the writing operation is directly performed on the memory chip according to the recorded page number.
  • determining whether the main control chip has writing requirements for the memory chip includes:
  • the data update area is used to store data that needs to be written into the memory chip
  • the data backup area is used to back up the data written into the memory chip.
  • the data update area is used to store data that needs to be written into the memory chip
  • the data backup area is used to back up the data written into the memory chip.
  • recording the page number of the memory chip corresponding to the writing requirement includes:
  • the first preset time is N update cycles of the memory chip.
  • the second preset time is an update cycle of the memory chip.
  • Embodiments of the present disclosure also provide a memory chip anti-accidental writing control device, which includes:
  • the first judgment module is used to judge whether the main control chip has writing requirements for the memory chip
  • a recording module used to record the page number of the memory chip corresponding to the writing requirement when there is a writing requirement
  • the first delay module is used to delay the first preset time
  • the second judgment module is used to judge again whether the main control chip has new writing requirements for the memory chip after delaying the first preset time;
  • the second delay module is used to delay the first preset time when there is a new writing requirement
  • An execution module configured to perform a write operation on the memory chip according to the recorded page number after a first preset time delay
  • the first preset time is greater than or equal to the time required for the lowest operating voltage of the main control chip to drop to the lowest operating voltage of the memory chip after power-off.
  • the device further includes:
  • the third delay module is used to determine whether the main control chip has a writing requirement for the memory chip, and when there is no writing requirement, delay the second preset time and then return to execute the determination of whether the main control chip has a writing requirement.
  • the execution module is also configured to: after once again determining whether the main control chip has a new writing requirement for the memory chip, when there is no new writing requirement, directly based on the recorded page number Perform a write operation on the memory chip.
  • the first judgment module or the second judgment module includes:
  • a judgment unit used to judge whether the data in the data update area and the data backup area of the main control chip are consistent
  • the first determination unit is used to determine that there is no writing requirement if the data is consistent
  • the second determination unit is used to determine that there is a writing requirement if the data is inconsistent
  • the data update area is used to store data that needs to be written into the memory chip
  • the data backup area is used to back up the data written into the memory chip.
  • the recording module is configured to: add the page number of the memory chip corresponding to the writing requirement into a delay queue, and write the data in the data update area into the data backup area.
  • the first preset time is N update cycles of the memory chip.
  • the second preset time is an update cycle of the memory chip.
  • the embodiment of the present disclosure provides a main control chip, which is characterized in that it includes: the memory chip anti-miswriting control device described in the embodiment of the present disclosure.
  • the embodiment of the present disclosure provides an electrical equipment, which is characterized in that it includes: the recorder described in the embodiment of the present disclosure. Memory chip anti-accidental writing control device.
  • the electrical equipment includes: air conditioners, washing machines, refrigerators, water heaters, fans, dryers, air purifiers, water purifiers or pure water machines.
  • An embodiment of the present disclosure provides a non-volatile computer-readable storage medium on which a computer program is stored. The feature is that when the computer program is executed by a processor, the steps of the method described in the embodiment of the present disclosure are implemented.
  • An embodiment of the present disclosure provides a computer device, including:
  • the processor is configured to execute the computer program stored on the memory to implement the steps of the method described in the above embodiments of the present disclosure.
  • the technical solution of the present disclosure is applied to determine whether the main control chip has a writing requirement for the memory chip.
  • the page number of the memory chip corresponding to the writing requirement is recorded.
  • the write operation is performed on the memory chip according to the recorded page number after a delay of the first preset time, where the first preset time is greater than or equal to the lowest operating voltage drop of the slave master chip after power outage. The time required to reach the minimum operating voltage of the memory chip.
  • the power supply voltage of the controller motherboard can be reduced to the minimum operating voltage of the memory chip before the write operation is performed, avoiding the need for the main controller to write the memory chip.
  • the write operation is performed during the period when the minimum operating voltage of the chip drops to the minimum operating voltage of the memory chip, thereby avoiding the possibility of the memory chip being mistakenly written in the low voltage range, ensuring stable operation of the device, and solving the problem of the main control chip of the device being The memory chip may be mistakenly written when the power is turned off.
  • Figure 1 is a graph showing the power supply voltage drop curve of the controller mainboard after the air conditioning unit is powered off according to some embodiments of the present disclosure
  • Figure 2 is a flow chart of a memory chip anti-accidental writing control method provided by some embodiments of the present disclosure
  • Figure 3 is a control flow chart of a dual-delay write memory chip provided by some embodiments of the present disclosure
  • Figure 4 is a structural block diagram of a memory chip anti-accidental writing control device provided by some embodiments of the present disclosure.
  • the inventor knows a method to prevent device parameters from being overwritten, which can be used to determine whether the data of the memory chip is normal after powering on. If it is normal, use it. If it is not normal, use the backup data from the last power outage. The inventor noticed that although this method can restore the data in the memory chip to the normal state data of the last backup, it cannot prevent the memory chip from being accidentally written, which will cause more updated parameters to not be memorized.
  • the power supply voltage drop curve of the controller mainboard after the air conditioning unit is powered off in some embodiments is disclosed.
  • the unit is powered off, but the main control chip and memory chip can still work normally.
  • the main control chip cannot work normally, but the memory chip can still work normally.
  • the main control chip may generate abnormal data. Due to the difference in the working voltages of the main control chip and the memory chip, Causes the memory chip to be mistakenly written. In a time period greater than t2, neither the main control chip nor the memory chip can work normally.
  • Embodiments of the present disclosure provide a memory chip anti-accidental writing control method, which is executed, for example, by a main control chip.
  • Figure 2 is a flow chart of a memory chip anti-miswriting control method provided by some embodiments of the present disclosure. As shown in Figure 2, the method includes the following steps.
  • the first preset time is greater than or equal to the time required for the minimum operating voltage of the main control chip to drop to the minimum operating voltage of the memory chip after power failure (i.e., the time length t2-t1 corresponding to the t1 ⁇ t2 time period in Figure 1 ).
  • the memory chip is internally divided into several pages, and each page can store several bytes of data.
  • the data of the memory chip is updated in units of pages.
  • the write operation is performed on the memory chip according to the method described in the embodiment of the present disclosure. Specifically, the process of performing two judgments is cyclically performed.
  • the write operation is avoided during the t1 to t2 time period through two delays.
  • the data will be discarded. This is mainly to prevent the memory chip from being mistakenly written during power outage and discard some normal data.
  • the device can also operate normally according to the previous data in the memory chip. However, if the memory chip is mistakenly written, when the device uses the mistaken data that has been mistakenly written, it will cause the device to fail to operate normally.
  • Some embodiments of the present disclosure determine whether the main control chip has a writing requirement for the memory chip. When there is a writing requirement, the page number of the memory chip corresponding to the writing requirement is recorded. After delaying the first preset time, judge again whether the main control chip is correct. Memory chips have new writing requirements. When there is a new writing requirement, the write operation is performed on the memory chip according to the recorded page number after a delay of a first preset time, where the first preset time is greater than or equal to the minimum operating voltage drop of the slave master chip after power outage. The time required to reach the minimum operating voltage of the memory chip.
  • the power supply voltage of the controller motherboard can be reduced to the minimum operating voltage of the memory chip before the write operation is performed, thus avoiding the need for the main controller to write the memory chip.
  • the write operation is performed during the period when the minimum working voltage of the chip drops to the minimum working voltage of the memory chip, thereby avoiding the possibility of the memory chip being mistakenly written in the low voltage range, ensuring stable operation of the device, and solving the problem of the main control chip of the device being The memory chip may be mistakenly written when the power is turned off.
  • the control method after S201 determines whether the main control chip has a writing requirement for the memory chip, the control method also includes: when there is no writing requirement, after delaying for a second preset time, return to execute S201 to determine whether the main control chip has a writing requirement for the memory chip.
  • the memory chip has a writing requirement step; wherein the second preset time is less than the first preset time. That is to say, for the first judgment, if it is judged that there is no writing requirement, the first judgment will be re-executed after a short delay. This ensures that the entire control process of writing the memory chip continues to execute, and the writing needs can be discovered in a timely manner.
  • the control method further includes: when there is no new writing requirement, directly perform a writing operation on the memory chip based on the recorded page number. That is to say, for the second judgment, if it is judged that there is no new writing demand, the write operation will be directly performed on the memory chip according to the writing demand judged for the first time. As mentioned before, if the first judgment that there is a write requirement occurs before time t1 in Figure 1, after the first delay, it may fall into the time period t1 ⁇ t2, and the write operation will not be performed at this time.
  • the main control chip includes a data update area and a data backup area.
  • the data update area is used to store data that needs to be written to the memory chip
  • the data backup area is used to back up the data that needs to be written to the memory chip.
  • S201 determines whether the main control chip has a writing requirement for the memory chip, including: determining whether the data in the data update area and the data backup area of the main control chip are consistent; if the data is consistent, it is determined that there is no writing requirement; if the data If they are inconsistent, it is determined that there is a writing requirement. By comparing the data update area and the data backup area, it can be quickly and accurately determined whether the main control chip has a write requirement.
  • S203 again determines whether the main control chip has new writing requirements for the memory chip, including: determining whether the data in the data update area and the data backup area of the main control chip are consistent; if the data are consistent, it is determined that there is no new Write requirements; if the data is inconsistent, it is determined that there are new write requirements.
  • the data update area and data backup area By comparison, it can quickly and accurately determine whether the main control chip generates new writing requirements.
  • recording the page number of the memory chip corresponding to the write request includes: adding the page number of the memory chip corresponding to the write request to the delay queue, and writing the data in the data update area to the data backup area.
  • the page number of the memory chip corresponding to the write request refers to the page number corresponding to the area where the data in the data update area and the data backup area are inconsistent. At this time, writing the data in the data update area to the data backup area can ensure the accuracy of the second judgment. Delayed write operations can be effectively implemented through delay queues.
  • performing a write operation on the memory chip according to the recorded page number includes: reading the page number of the memory chip from the delay queue, and performing a write operation on the memory chip according to the page number of the memory chip.
  • the memory chip is internally divided into several pages. Each page can store several bytes of data.
  • the data update of the memory chip is in units of pages. Each page is scanned sequentially according to a fixed time interval. This time interval is recorded as the update cycle of the memory chip. T.
  • the first preset time is N update cycles of the memory chip.
  • the second preset time is an update cycle of the memory chip. N>0, the value of N needs to ensure that the time corresponding to the N update cycles of the memory chip is greater than or equal to the time required for the minimum operating voltage of the main control chip to drop to the minimum operating voltage of the memory chip after power failure.
  • the data update area is used to store the data that needs to be written to the memory chip.
  • the data backup area is suitable for writing to the memory chip.
  • Memory chip data is backed up. During the operation of the equipment, after the memory parameters are updated, the data will be written into the data update area.
  • control flow of a dual-delay write memory chip includes the following steps.
  • S302 Determine for the first time whether the data in the data update area and the data backup area are consistent. If they are consistent, go to S303; if they are not consistent, go to S304.
  • the purpose of the first data comparison in this step is to determine whether the device has memory parameter updates during operation, that is, whether there is a need to write to the memory chip.
  • delay T represents the update cycle of the memory chip, and return to execute S302.
  • S305 Write the data in the data update area into the data backup area.
  • S307 After the first delay, determine again whether the data in the data update area and the data backup area are consistent. If they are consistent, go to S308; if they are not consistent, go to S309.
  • S308 Perform a write operation on the memory chip according to the page number of the memory chip recorded in the delay queue, and then return to S302 to enter the next round of judgment.
  • the main control chip After the main control chip generates a write demand under normal power supply status, the normal data corresponding to the write demand will be delayed to be written to the memory chip, but due to the write The real-time requirements of the memory chip are not very high, so delayed writing to the memory chip will not affect the normal operation of the device.
  • the main purpose is to avoid miswriting to the memory chip and ensure the accuracy of the memory chip data.
  • the timing of the main control chip to perform the write operation is controlled after the t2 moment in Figure 1.
  • the control method of the dual-delay write memory chip in some embodiments of the present disclosure adopts a dual-delay strategy after the demand for writing the memory chip is generated to cause the power supply voltage of the controller mainboard to attenuate below the minimum operating voltage of the memory chip, thus avoiding the problem of The main control chip miswrites the memory chip during power-off and low-voltage conditions, avoiding the possibility of the memory chip being miswritten in the low-voltage range, preventing low-voltage miswriting of the memory chip during power-off, and ensuring stable operation of the equipment.
  • some embodiments of the present disclosure provide a memory chip anti-accidental writing control device for implementing the memory chip anti-accidental writing control method described in the above embodiments.
  • the device is implemented by software and/or hardware, and the device is integrated into a main control chip, for example.
  • Figure 4 is a structural block diagram of a memory chip anti-miswriting control device provided by an embodiment of the present disclosure. As shown in Figure 4, the device includes a first judgment module 41, a recording module 42, a first delay module 43, and a second judgment module. 44. The second delay module 45 and the execution module 46.
  • the first judgment module 41 is used to judge whether the main control chip has writing requirements for the memory chip.
  • the recording module 42 is used to record the page number of the memory chip corresponding to the writing requirement when there is a writing requirement.
  • the first delay module 43 is used to delay the first preset time.
  • the second judgment module 44 is used to judge again whether the main control chip has a new writing requirement for the memory chip after delaying the first preset time.
  • the second delay module 45 is used to delay the first preset time when there is a new writing requirement.
  • the execution module 46 is configured to perform a write operation on the memory chip according to the recorded page number after a first preset time delay.
  • the first preset time is greater than or equal to the time required for the lowest operating voltage of the main control chip to drop to the lowest operating voltage of the memory chip after a power outage.
  • the above device further includes: a third delay module, configured to, after determining whether the main control chip has a writing requirement for the memory chip, delay for a second preset time and return to execution when there is no writing requirement. The step of determining whether the main control chip has writing requirements for the memory chip; wherein the second preset time is less than the first preset time.
  • the execution module 46 is also configured to: after once again determining whether the main control chip has a new writing requirement for the memory chip, when there is no new writing requirement, directly write the memory chip according to the recorded page number.
  • the memory chip performs write operations.
  • the first judgment module 41 or the second judgment module 44 includes a judgment unit, a first determination unit and a second determination unit.
  • the judgment unit is used to judge whether the data in the data update area and the data backup area of the main control chip are consistent.
  • the first determination unit is used to determine that there is no writing requirement if the data is consistent.
  • the second determination unit is used to determine that there is a writing requirement if the data is inconsistent.
  • the data update area is used to store data that needs to be written into the memory chip
  • the data backup area is used to back up the data written into the memory chip.
  • the recording module 42 is specifically configured to: add the memory chip page number corresponding to the write request into the delay queue, and write the data in the data update area into the data backup area.
  • the first preset time is N update cycles of the memory chip.
  • the second preset time is an update cycle of the memory chip.
  • the above memory chip anti-accidental writing control device can execute the memory chip anti-accidental writing control method provided by the embodiments of the present disclosure, and has corresponding functional modules and beneficial effects of the execution method.
  • Disclosed embodiments provide a memory chip anti-accidental writing control method.
  • Embodiments of the present disclosure also provide a main control chip, including: the memory chip anti-accidental writing control described in the above embodiments. control device.
  • An embodiment of the present disclosure also provides an electrical device, including: the memory chip accidental writing prevention control device described in the above embodiment.
  • electrical equipment includes: air conditioners, washing machines, refrigerators, water heaters, fans, dryers, air purifiers, water purifiers or pure water machines.
  • Embodiments of the present disclosure also provide a non-volatile computer-readable storage medium on which a computer program is stored.
  • a computer program is stored on which a computer program is stored.
  • the steps of the method described in the above embodiments are implemented.
  • An embodiment of the present disclosure also provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor.
  • the processor executes the computer program, it implements the method described in the above embodiment. A step of.
  • the device embodiments described above are only illustrative.
  • the units described as separate components may or may not be physically separated.
  • the components shown as units may or may not be physical units, that is, they may be located in One location, or it can be distributed across multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each embodiment can be implemented by software plus a necessary general hardware platform, and of course, it can also be implemented by hardware.
  • the computer software products can be stored in computer-readable storage media, such as ROM/RAM, disks. , optical disk, etc., including a number of instructions to cause a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments.

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Abstract

本公开提供一种记忆芯片防误写控制方法、装置及用电设备。其中,该方法包括:判断主控芯片是否对记忆芯片有写需求;当有写需求时,将写需求对应的记忆芯片的页码进行记录;延时第一预设时间后,再次判断主控芯片是否对记忆芯片有新的写需求;当有新的写需求时,延时第一预设时间后,根据记录的页码对记忆芯片执行写操作;其中,第一预设时间大于或等于掉电后从主控芯片的最低工作电压下降到记忆芯片的最低工作电压所需的时间。

Description

记忆芯片防误写控制方法、装置及用电设备
相关申请的交叉引用
本公开是以CN申请号为202210843267.1,申请日为2022年7月18日的申请为基础,并主张其优先权,该CN申请的公开内容在此作为整体引入本公开中。
技术领域
本公开涉及一种记忆芯片防误写控制方法、装置及用电设备。
背景技术
EEPROM(Electrically Erasable Programmable Read Only Memory,带电可擦可编程只读存储器)是一种掉电后数据不丢失的存储芯片。用电设备(如空调、洗衣机等)采用EEPROM作为记忆芯片,用来存储设备运行的重要参数,对记忆芯片进行误写操作,写入错误数据,将会导致设备运行失常。设备控制器主板在设备掉电低电压状态下,容易对记忆芯片产生误写操作。
主控芯片(MCU)的最低工作电压高于记忆芯片(EEPROM)的最低工作电压,控制器主板掉电后,供电电压下降,存在一段低电压区间,该区间低于主控芯片最低工作电压且高于记忆芯片最低工作电压,此时,主控芯片因低电压导致其RAM(Random Access Memory,随机存取存储器)数据出现异常,但记忆芯片仍然可以被正常写入,从而导致记忆芯片可能被误写。
发明内容
本公开实施例提供一种记忆芯片防误写控制方法、装置及用电设备,以至少解决设备的主控芯片在掉电时可能对记忆芯片进行误写的问题。
为解决上述技术问题,本公开实施例提供了一种记忆芯片防误写控制方法,包括:
判断主控芯片是否对所述记忆芯片有写需求;
当有写需求时,将所述写需求对应的所述记忆芯片的页码进行记录;
延时第一预设时间后,再次判断所述主控芯片是否对所述记忆芯片有新的写需求;以及
当有新的写需求时,延时第一预设时间后,根据记录的所述页码对所述记忆芯片 执行写操作;
其中,所述第一预设时间大于或等于掉电后从所述主控芯片的最低工作电压下降到所述记忆芯片的最低工作电压所需的时间。
在一些实施例中,在判断主控芯片是否对记忆芯片有写需求之后,所述方法还包括:
当没有写需求时,延时第二预设时间后,返回执行所述判断主控芯片是否对记忆芯片有写需求的步骤;
其中,所述第二预设时间小于所述第一预设时间。
在一些实施例中,在再次判断所述主控芯片是否对所述记忆芯片有新的写需求之后,所述方法还包括:
当没有新的写需求时,直接根据记录的所述页码对所述记忆芯片执行写操作。
在一些实施例中,判断主控芯片是否对记忆芯片有写需求,包括:
判断所述主控芯片的数据更新区与数据备份区的数据是否一致;
若数据一致,则确定没有写需求;
若数据不一致,则确定有写需求;
其中,所述数据更新区用于存储需要写入所述记忆芯片的数据,所述数据备份区用于对写入所述记忆芯片的数据进行备份。
在一些实施例中,再次判断所述主控芯片是否对所述记忆芯片有新的写需求,包括:
判断所述主控芯片的数据更新区与数据备份区的数据是否一致;
若数据一致,则确定没有新的写需求;
若数据不一致,则确定有新的写需求;
其中,所述数据更新区用于存储需要写入所述记忆芯片的数据,所述数据备份区用于对写入所述记忆芯片的数据进行备份。
在一些实施例中,将所述写需求对应的记忆芯片的页码进行记录,包括:
将所述写需求对应的记忆芯片的页码加入延时队列,并将所述数据更新区的数据写入所述数据备份区。
在一些实施例中,所述第一预设时间为所述记忆芯片的N个更新周期。
在一些实施例中,所述第二预设时间为所述记忆芯片的一个更新周期。
本公开实施例还提供了一种记忆芯片防误写控制装置,包括:
第一判断模块,用于判断主控芯片是否对所述记忆芯片有写需求;
记录模块,用于当有写需求时,将所述写需求对应的记忆芯片的页码进行记录;
第一延时模块,用于延时第一预设时间;
第二判断模块,用于在延时第一预设时间后,再次判断所述主控芯片是否对所述记忆芯片有新的写需求;
第二延时模块,用于当有新的写需求时,延时第一预设时间;以及
执行模块,用于在延时第一预设时间后,根据记录的所述页码对所述记忆芯片执行写操作;
其中,所述第一预设时间大于或等于掉电后从所述主控芯片的最低工作电压下降到所述记忆芯片的最低工作电压所需的时间。
在一些实施例中,所述的装置还包括:
第三延时模块,用于在判断所述主控芯片是否对所述记忆芯片有写需求之后,当没有写需求时,延时第二预设时间后,返回执行所述判断主控芯片是否对记忆芯片有写需求的步骤;其中,所述第二预设时间小于所述第一预设时间。
在一些实施例中,所述执行模块还用于:在再次判断所述主控芯片是否对所述记忆芯片有新的写需求之后,当没有新的写需求时,直接根据记录的所述页码对所述记忆芯片执行写操作。
在一些实施例中,所述第一判断模块或所述第二判断模块包括:
判断单元,用于判断所述主控芯片的数据更新区与数据备份区的数据是否一致;
第一确定单元,用于若数据一致,则确定没有写需求;
第二确定单元,用于若数据不一致,则确定有写需求;
其中,所述数据更新区用于存储需要写入所述记忆芯片的数据,所述数据备份区用于对写入所述记忆芯片的数据进行备份。
在一些实施例中,所述记录模块用于:将所述写需求对应的所述记忆芯片的所述页码加入延时队列,并将所述数据更新区的数据写入所述数据备份区。
在一些实施例中,所述第一预设时间为所述记忆芯片的N个更新周期。
在一些实施例中,所述第二预设时间为所述记忆芯片的一个更新周期。
本公开实施例提供了一种主控芯片,其特征在于,包括:本公开实施例所述的记忆芯片防误写控制装置。
本公开实施例提供了一种用电设备,其特征在于,包括:本公开实施例所述的记 忆芯片防误写控制装置。
在一些实施例中,所述用电设备包括:空调、洗衣机、冰箱、热水器、风扇、烘干机、空气净化器、净水器或纯水机。
本公开实施例提供了一种非易失性计算机可读存储介质,其上存储有计算机程序,其特征在于,所述计算机程序被处理器执行时实现本公开实施例所述方法的步骤。
本公开实施例提供了一种计算机设备,包括:
存储器;以及
处理器,被配置为执行存储在所述存储器上的计算机程序,以实现上述本公开实施例所述方法的步骤。
应用本公开的技术方案,判断主控芯片是否对记忆芯片有写需求,当有写需求时,将写需求对应的记忆芯片的页码进行记录。延时第一预设时间后,再次判断主控芯片是否对记忆芯片有新的写需求。当有新的写需求时,延时第一预设时间后,根据记录的页码对记忆芯片执行写操作,其中,第一预设时间大于或等于掉电后从主控芯片最低的工作电压下降到记忆芯片的最低工作电压所需的时间。在产生写记忆芯片需求后,通过双延时策略,在发生掉电的情况下能够使控制器主板的供电电压衰减至记忆芯片的最低工作电压之下才执行写操作,避免了在由主控芯片的最低工作电压下降到记忆芯片的最低工作电压的这个时间段内执行写操作,从而规避记忆芯片在低电压区间被误写的可能性,保证设备稳定运行,解决了设备的主控芯片在掉电时可能对记忆芯片进行误写的问题。
附图说明
图1是本公开一些实施例提供的空调机组掉电后控制器主板供电电压下降曲线图;
图2是本公开一些实施例提供的记忆芯片防误写控制方法的流程图;
图3是本公开一些实施例提供的双延时写记忆芯片的控制流程图;
图4是本公开一些实施例提供的记忆芯片防误写控制装置的结构框图。
应当明白,附图中所示出的各个部分的尺寸并不必然是按照实际的比例关系绘制的。此外,相同或类似的参考标号表示相同或类似的构件。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚,下面将结合附图对本公开作进 一步地详细描述,显然,所描述的实施例仅仅是本公开一部分实施例,而不是全部的实施例。基于本公开中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本公开保护的范围。
需要说明的是,本公开的说明书和权利要求书及附图中的术语“第一”、“第二”等是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换,以便这里描述的本公开的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外,术语“包括”和“具有”以及他们的任何变形,意图在于覆盖不排他的包含,例如,包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元,而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
需要说明的是,在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行,并且,虽然在流程图中示出了逻辑顺序,但是在某些情况下,可以以不同于此处的顺序执行所示出或描述的步骤。
发明人知晓的一种设备参数防改写方法,可以通过上电后判断记忆芯片的数据是否正常,若正常,则使用,若不正常,则采用上一次掉电的备份数据。发明人注意到,虽然该方法能够将记忆芯片中的数据恢复到上一次备份的正常状态数据,但是不能防止记忆芯片被误写,会造成较多的已更新参数没有被记忆。
针对设备主控芯片在掉电时可能对记忆芯片进行误写的问题,目前尚未提出有效的解决方案。
下面结合附图详细说明本公开的可选实施例。
如图1所示,为公开一些实施例的空调机组掉电后控制器主板供电电压下降曲线图,在t0~t1时间段,机组掉电,但主控芯片和记忆芯片仍然可以正常工作。在t1~t2时间段,主控芯片不能正常工作,记忆芯片仍然可以正常工作,在t1~t2时间段,主控芯片可能会产生异常数据,由于主控芯片和记忆芯片工作电压的差异性,导致误写记忆芯片。在大于t2的时间段,主控芯片和记忆芯片均不能正常工作。当控制器主板处于t1~t2时间段时,由于此时间段的电压低于主控芯片最低工作电压而高于记忆芯片最低工作电压,容易触发误写记忆芯片的操作。
本公开实施例提供一种记忆芯片防误写控制方法,该方法例如由主控芯片执行。图2是本公开一些实施例提供的记忆芯片防误写控制方法的流程图,如图2所示,该方法包括以下步骤。
S201,判断主控芯片是否对记忆芯片有写需求。
S202,当有写需求时,将写需求对应的记忆芯片的页码进行记录。
S203,延时第一预设时间后,再次判断主控芯片是否对记忆芯片有新的写需求。
S204,当有新的写需求时,延时第一预设时间后,根据记录的页码对记忆芯片执行写操作。
其中,第一预设时间大于或等于掉电后从主控芯片的最低工作电压下降到记忆芯片的最低工作电压所需的时间(即图1中t1~t2时间段所对应的时长t2-t1)。记忆芯片内部分为若干个页,每一页可以存储若干个字节数据,记忆芯片的数据更新以页为单位。
主控芯片工作过程中,无论主控芯片处于正常供电状态还是掉电状态,都按照本公开实施例所述的方法来对记忆芯片执行写操作,具体是循环执行两次判断的过程。
第一次判断出有写需求,经过第一次延时后,若供电电压降至记忆芯片最低工作电压之下,即图1中t2以后的时间段,此时记忆芯片已经无法正常工作,任何数据都无法写入记忆芯片中。进而无论第二次判断结果如何,都无法将数据写入记忆芯片。也就是说,如果第一次判断出的写需求是由掉电低电压导致主控芯片RAM出现异常变化而引起,通过第一次延时,避开了在t1~t2时间段执行写操作,异常数据(或称为错误数据)不会被写入记忆芯片。
若第一次判断出有写需求是发生在图1中t1时刻之前,在第一次延时后,可能会落入t1~t2时间段,此时并不执行写操作。若第二次判断出有新的写需求,表示在t1~t2时间段产生异常数据,经过第二次延时后,会进入图1中t2以后的时间段,此时针对第一次判断出的写需求执行写操作,但记忆芯片已经无法正常工作,任何数据都无法写入记忆芯片中,即,通过两次延时避开了在t1~t2时间段执行写操作。
上述两种情况下,如果第一次判断出的写需求是正常数据,无法被写入记忆芯片,该数据将被舍弃,主要是为了防止掉电时记忆芯片被误写,舍弃一点正常数据,设备也能按照记忆芯片中之前的数据正常运行,但若记忆芯片被误写,当设备使用被误写的错误数据时,会导致无法正常运行。
通过上述双延时策略,能够保证在t1~t2时间段不会对记忆芯片进行写操作,从而防止掉电时对记忆芯片进行误写。
本公开一些实施例判断主控芯片是否对记忆芯片有写需求,当有写需求时,将写需求对应的记忆芯片页码进行记录。延时第一预设时间后,再次判断主控芯片是否对 记忆芯片有新的写需求。当有新的写需求时,延时第一预设时间后,根据记录的页码对记忆芯片执行写操作,其中,第一预设时间大于或等于掉电后从主控芯片的最低工作电压下降到记忆芯片的最低工作电压所需的时间。在产生写记忆芯片需求后,通过双延时策略,在发生掉电的情况下能够使控制器主板的供电电压衰减至记忆芯片的最低工作电压之下才执行写操作,避免了在由主控芯片的最低工作电压下降到记忆芯片的最低工作电压的这个时间段内执行写操作,从而规避记忆芯片在低电压区间被误写的可能性,保证设备稳定运行,解决了设备的主控芯片在掉电时可能对记忆芯片进行误写的问题。
在一些实施例中,在S201判断主控芯片是否对记忆芯片有写需求之后,控制方法还包括:当没有写需求时,延时第二预设时间后,返回执行S201判断主控芯片是否对记忆芯片有写需求的步骤;其中,第二预设时间小于第一预设时间。也就是说,对于第一次判断,若判断出没有写需求,则延时较短的时间后,再重新执行第一次判断。由此能够保证整个写记忆芯片的控制流程的继续执行,并能够及时发现写需求。
在一些实施例中,在S203再次判断主控芯片是否对记忆芯片有新的写需求之后,控制方法还包括:当没有新的写需求时,直接根据记录的页码对记忆芯片执行写操作。也就是说,对于第二次判断,若判断出没有新的写需求,则直接针对第一次判断出来的写需求对记忆芯片执行写操作。如前所述,若第一次判断出有写需求是发生在图1中t1时刻之前,在第一次延时后,可能会落入t1~t2时间段,此时并不执行写操作,若第二次判断出没有新的写需求,表示在t1~t2时间段没有产生异常数据,无需延时,直接针对第一次判断出的写需求执行写操作,也不会导致记忆芯片误写。
在一些实施例中,主控芯片包括数据更新区和数据备份区,数据更新区用于存储需要写入记忆芯片的数据,数据备份区用于对写入记忆芯片的数据进行备份。设备运行过程中,记忆参数更新后,数据会写入数据更新区。
在一些实施例中,S201判断主控芯片是否对记忆芯片有写需求,包括:判断主控芯片的数据更新区与数据备份区的数据是否一致;若数据一致,则确定没有写需求;若数据不一致,则确定有写需求。通过数据更新区和数据备份区的比较,能够快速准确判断出主控芯片是否产生写需求。
在一些实施例中,S203再次判断主控芯片是否对记忆芯片有新的写需求,包括:判断主控芯片的数据更新区与数据备份区的数据是否一致;若数据一致,则确定没有新的写需求;若数据不一致,则确定有新的写需求。通过数据更新区和数据备份区的 比较,能够快速准确判断出主控芯片是否产生新的写需求。
在一些实施例中,将写需求对应的记忆芯片的页码进行记录,包括:将写需求对应的记忆芯片的页码加入延时队列,并将数据更新区的数据写入数据备份区。其中,写需求对应的记忆芯片的页码是指数据更新区与数据备份区中数据不一致的区域所对应的页码。此时将数据更新区的数据写入数据备份区,能够保证第二次判断的准确性。通过延时队列可以有效实现延时写操作。
在一些实施例中,根据记录的页码对记忆芯片执行写操作,包括:从延时队列中读取记忆芯片的页码,并根据记忆芯片的页码对记忆芯片进行写操作。
记忆芯片内部分为若干个页,每一页可以存储若干个字节数据,记忆芯片的数据更新以页为单位,根据固定的时间间隔依次扫描各个页,记该时间间隔为记忆芯片的更新周期T。
在一些实施例中,第一预设时间是记忆芯片的N个更新周期。在一些实施例中,第二预设时间是记忆芯片的一个更新周期。N>0,N的取值需要保证记忆芯片的N个更新周期所对应的时间大于或等于掉电后从主控芯片的最低工作电压下降到记忆芯片的最低工作电压所需的时间。
下面结合一些实施例对上述记忆芯片防误写控制方法进行说明,然而值得注意的是,这些实施例仅是为了更好地说明本公开,并不构成对本公开的不当限定。与上述实施例相同或相应的术语解释,下面的实施例不再赘述。
在主控芯片的RAM中开辟两个存储空间用于存储写记忆芯片的数据,即数据更新区和数据备份区,数据更新区用于存储需要写入记忆芯片的数据,数据备份区对写入记忆芯片的数据进行备份。设备运行过程中,记忆参数更新后,数据会写入数据更新区。
如图3所示,本公开一些实施例的双延时写记忆芯片的控制流程包括以下步骤。
S301,开始。
S302,首次判断数据更新区与数据备份区的数据是否一致。若一致,进入S303;若不一致,进入S304。本步骤中首次进行数据对比的目的是为了判断设备在运行过程中是否有记忆参数更新,即是否产生对记忆芯片的写需求。
S303,延时T,T表示记忆芯片的更新周期,并返回执行S302。
S304,将数据不一致的区域所对应的记忆芯片的页码加入延时队列。
S305,将数据更新区的数据写入数据备份区。
S306,首次延时记忆芯片的N个更新周期T(即延时N×T),其中,N取值的依据是保证N×T≥t2-t1。在经过首次延时后,若供电电压下降至记忆芯片的最低工作电压之下,即图1中t2之后的时间段,此时记忆芯片无法正常工作,不会被写入。若数据更新区与数据备份区的数据不一致是由于低电压导致主控芯片的RAM出现异常变化而引起的,经过本步骤的延时写操作,异常数据不会被写入记忆芯片。
S307,进行首次延时之后,再次判断数据更新区与数据备份区的数据是否一致。若一致,进入S308;若不一致,进入S309。
S308,根据延时队列记录的记忆芯片的页码对记忆芯片执行写操作,然后返回S302进入下一轮判断。
S309,再次延时记忆芯片的N个更新周期T(即延时N×T),结束延时后,进入S308以对记忆芯片执行写操作。若首次出现数据更新区与数据备份区的数据不一致是发生在图1中的t1时刻之前,在首次延时之后,可能会落入t1~t2时间段,因此进行再次延时,以保证在t1~t2时间段不会对记忆芯片进行写操作,以规避误写操作。
通过本公开一些实施例的双延时写记忆芯片的控制方法,主控芯片在正常供电状态下,产生写需求后,该写需求对应的正常数据,会延时写入记忆芯片,但由于写记忆芯片的实时性需求并不是很高,所以延时写入记忆芯片,也并不会影响设备正常运行。主要是为了避免对记忆芯片误写,保证记忆芯片数据的准确性,在掉电状态下将主控芯片执行写操作的时机控制在图1中t2时刻之后。
本公开一些实施例的双延时写记忆芯片的控制方法,在产生写记忆芯片需求后,采用双延时策略,使控制器主板的供电电压衰减至记忆芯片的最低工作电压之下,规避了主控芯片在掉电低电压状态下对记忆芯片的误写操作,规避记忆芯片在低电压区间被误写的可能性,防止掉电时低电压误写记忆芯片,保证了设备稳定运行。
基于同一发明构思,本公开一些实施例提供了一种记忆芯片防误写控制装置,用于实现上述实施例所述的记忆芯片防误写控制方法。在一些实施例中,该装置通过软件和/或硬件实现,该装置例如集成于主控芯片中。
图4是本公开实施例提供的记忆芯片防误写控制装置的结构框图,如图4所示,该装置包括第一判断模块41、记录模块42、第一延时模块43、第二判断模块44、第二延时模块45和执行模块46。
第一判断模块41用于判断主控芯片是否对记忆芯片有写需求。
记录模块42用于当有写需求时,将所述写需求对应的记忆芯片的页码进行记录。
第一延时模块43用于延时第一预设时间。
第二判断模块44用于在延时第一预设时间后,再次判断所述主控芯片是否对所述记忆芯片有新的写需求。
第二延时模块45用于当有新的写需求时,延时第一预设时间。
执行模块46用于在延时第一预设时间后,根据记录的页码对所述记忆芯片执行写操作。
其中,所述第一预设时间大于或等于掉电后从主控芯片的最低工作电压下降到记忆芯片的最低工作电压所需的时间。
在一些实施例中,上述装置还包括:第三延时模块,用于在判断主控芯片是否对记忆芯片有写需求之后,当没有写需求时,延时第二预设时间后,返回执行所述判断主控芯片是否对记忆芯片有写需求的步骤;其中,所述第二预设时间小于所述第一预设时间。
在一些实施例中,执行模块46还用于:在再次判断所述主控芯片是否对所述记忆芯片有新的写需求之后,当没有新的写需求时,直接根据记录的页码对所述记忆芯片执行写操作。
在一些实施例中,第一判断模块41或第二判断模块44包括判断单元、第一确定单元和第二确定单元。
判断单元用于判断所述主控芯片的数据更新区与数据备份区的数据是否一致。
第一确定单元用于若数据一致,则确定没有写需求。
第二确定单元用于若数据不一致,则确定有写需求。
其中,所述数据更新区用于存储需要写入所述记忆芯片的数据,所述数据备份区用于对写入所述记忆芯片的数据进行备份。
在一些实施例中,记录模块42具体用于:将所述写需求对应的记忆芯片页码加入延时队列,并将所述数据更新区的数据写入所述数据备份区。
在一些实施例中,所述第一预设时间为记忆芯片的N个更新周期。
在一些实施例中,所述第二预设时间为记忆芯片的一个更新周期。
上述记忆芯片防误写控制装置可执行本公开实施例所提供的记忆芯片防误写控制方法,具备执行方法相应的功能模块和有益效果未在这些实施例中详尽描述的技术细节,可参见本公开实施例提供的记忆芯片防误写控制方法。
本公开实施例还提供一种主控芯片,包括:上述实施例所述的记忆芯片防误写控 制装置。
本公开实施例还提供一种用电设备,包括:上述实施例所述的记忆芯片防误写控制装置。
在一些实施例中,用电设备包括:空调、洗衣机、冰箱、热水器、风扇、烘干机、空气净化器、净水器或纯水机。
本公开实施例还提供一种非易失性计算机可读存储介质,其上存储有计算机程序,所述计算机程序被处理器执行时实现上述实施例所述方法的步骤。
本公开实施例还提供一种计算机设备,包括:存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序,所述处理器执行所述计算机程序时实现上述实施例所述方法的步骤。
以上所描述的装置实施例仅仅是示意性的,其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
通过以上的实施方式的描述,本领域的技术人员可以清楚地了解到各实施方式可借助软件加必需的通用硬件平台的方式来实现,当然也可以通过硬件。基于这样的理解,上述技术方案本质上或者说对相关技术做出贡献的部分可以以软件产品的形式体现出来,该计算机软件产品可以存储在计算机可读存储介质中,如ROM/RAM、磁碟、光盘等,包括若干指令用以使得一台计算机设备(可以是个人计算机,服务器,或者网络设备等)执行各个实施例或者实施例的某些部分所述的方法。
最后应说明的是:以上实施例仅用以说明本公开的技术方案,而非对其限制;尽管参照前述实施例对本公开进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (20)

  1. 一种记忆芯片防误写控制方法,其特征在于,包括:
    判断主控芯片是否对所述记忆芯片有写需求;
    当有写需求时,将所述写需求对应的所述记忆芯片的页码进行记录;
    延时第一预设时间后,再次判断所述主控芯片是否对所述记忆芯片有新的写需求;以及
    当有新的写需求时,延时第一预设时间后,根据记录的所述页码对所述记忆芯片执行写操作;
    其中,所述第一预设时间大于或等于掉电后从所述主控芯片的最低工作电压下降到所述记忆芯片的最低工作电压所需的时间。
  2. 根据权利要求1所述的方法,其特征在于,在判断主控芯片是否对记忆芯片有写需求之后,还包括:
    当没有写需求时,延时第二预设时间后,返回执行所述判断主控芯片是否对记忆芯片有写需求的步骤;
    其中,所述第二预设时间小于所述第一预设时间。
  3. 根据权利要求1所述的方法,其特征在于,在再次判断所述主控芯片是否对所述记忆芯片有新的写需求之后,还包括:
    当没有新的写需求时,直接根据记录的所述页码对所述记忆芯片执行写操作。
  4. 根据权利要求1所述的方法,其特征在于,判断主控芯片是否对记忆芯片有写需求,包括:
    判断所述主控芯片的数据更新区与数据备份区的数据是否一致;
    若数据一致,则确定没有写需求;
    若数据不一致,则确定有写需求;
    其中,所述数据更新区用于存储需要写入所述记忆芯片的数据,所述数据备份区用于对写入所述记忆芯片的数据进行备份。
  5. 根据权利要求1所述的方法,其特征在于,再次判断所述主控芯片是否对所述记忆芯片有新的写需求,包括:
    判断所述主控芯片的数据更新区与数据备份区的数据是否一致;
    若数据一致,则确定没有新的写需求;
    若数据不一致,则确定有新的写需求;
    其中,所述数据更新区用于存储需要写入所述记忆芯片的数据,所述数据备份区用于对写入所述记忆芯片的数据进行备份。
  6. 根据权利要求4或5所述的方法,其特征在于,将所述写需求对应的记忆芯片的页码进行记录,包括:
    将所述写需求对应的记忆芯片的页码加入延时队列,并将所述数据更新区的数据写入所述数据备份区。
  7. 根据权利要求1至6中任一项所述的方法,其特征在于,所述第一预设时间为所述记忆芯片的N个更新周期。
  8. 根据权利要求2所述的方法,其特征在于,所述第二预设时间为所述记忆芯片的一个更新周期。
  9. 一种记忆芯片防误写控制装置,其特征在于,包括:
    第一判断模块,用于判断主控芯片是否对所述记忆芯片有写需求;
    记录模块,用于当有写需求时,将所述写需求对应的记忆芯片的页码进行记录;
    第一延时模块,用于延时第一预设时间;
    第二判断模块,用于在延时第一预设时间后,再次判断所述主控芯片是否对所述记忆芯片有新的写需求;
    第二延时模块,用于当有新的写需求时,延时第一预设时间;以及
    执行模块,用于在延时第一预设时间后,根据记录的所述页码对所述记忆芯片执行写操作;
    其中,所述第一预设时间大于或等于掉电后从所述主控芯片的最低工作电压下降到所述记忆芯片的最低工作电压所需的时间。
  10. 根据权利要求9所述的装置,其特征在于,还包括:
    第三延时模块,用于在判断所述主控芯片是否对所述记忆芯片有写需求之后,当没有写需求时,延时第二预设时间后,返回执行所述判断主控芯片是否对记忆芯片有写需求的步骤;其中,所述第二预设时间小于所述第一预设时间。
  11. 根据权利要求9所述的装置,其特征在于,所述执行模块还用于:在再次判断所述主控芯片是否对所述记忆芯片有新的写需求之后,当没有新的写需求时,直接根据记录的所述页码对所述记忆芯片执行写操作。
  12. 根据权利要求9所述的装置,其特征在于,所述第一判断模块或所述第二判 断模块包括:
    判断单元,用于判断所述主控芯片的数据更新区与数据备份区的数据是否一致;
    第一确定单元,用于若数据一致,则确定没有写需求;
    第二确定单元,用于若数据不一致,则确定有写需求;
    其中,所述数据更新区用于存储需要写入所述记忆芯片的数据,所述数据备份区用于对写入所述记忆芯片的数据进行备份。
  13. 根据权利要求9所述的装置,其特征在于,所述记录模块用于:将所述写需求对应的所述记忆芯片的所述页码加入延时队列,并将所述数据更新区的数据写入所述数据备份区。
  14. 根据权利要求9所述的装置,其特征在于,所述第一预设时间为所述记忆芯片的N个更新周期。
  15. 根据权利要求10所述的装置,其特征在于,所述第二预设时间为所述记忆芯片的一个更新周期。
  16. 一种主控芯片,其特征在于,包括:权利要求9-15任意一项所述的记忆芯片防误写控制装置。
  17. 一种用电设备,其特征在于,包括:权利要求9-15任意一项所述的记忆芯片防误写控制装置。
  18. 根据权利要求17所述的用电设备,其特征在于,所述用电设备包括:空调、洗衣机、冰箱、热水器、风扇、烘干机、空气净化器、净水器或纯水机。
  19. 一种非易失性计算机可读存储介质,其上存储有计算机程序,其特征在于,所述计算机程序被处理器执行时实现权利要求1至8中任一项所述方法的步骤。
  20. 一种计算机设备,包括:
    存储器;以及
    处理器,被配置为执行存储在所述存储器上的计算机程序,以实现权利要求1至8中任一项所述方法的步骤。
PCT/CN2023/092506 2022-07-18 2023-05-06 记忆芯片防误写控制方法、装置及用电设备 WO2024016792A1 (zh)

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