WO2024011533A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2024011533A1
WO2024011533A1 PCT/CN2022/105801 CN2022105801W WO2024011533A1 WO 2024011533 A1 WO2024011533 A1 WO 2024011533A1 CN 2022105801 W CN2022105801 W CN 2022105801W WO 2024011533 A1 WO2024011533 A1 WO 2024011533A1
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WIPO (PCT)
Prior art keywords
electrode
substrate
via holes
orthographic projection
overlapping
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PCT/CN2022/105801
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English (en)
French (fr)
Inventor
柳泉洲
钱海蛟
陈亮
刘泽旭
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002206.0A priority Critical patent/CN117916884A/zh
Priority to PCT/CN2022/105801 priority patent/WO2024011533A1/zh
Publication of WO2024011533A1 publication Critical patent/WO2024011533A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present application relates to the field of display technology, and in particular to an array substrate and a display device.
  • Liquid crystal displays (English: Liquid Crystal Display, abbreviated as: LCD) have the advantages of good picture quality, small size, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost. They have been widely used in tablet computers, In electronic products such as TVs, mobile phones and car monitors.
  • an array substrate in a display device has a display area and a non-display area located around the display area.
  • the display area has a plurality of sub-pixels arranged in an array and a plurality of gate lines.
  • One gate line is electrically connected to one row of sub-pixels.
  • the GOA circuit can be electrically connected to multiple gate lines, and the GOA circuit is used to provide gate driving signals to the multiple gate lines.
  • the GOA circuit in the array substrate is prone to disconnection when electrically connected to multiple gate lines, resulting in poor display effects of the display device.
  • Embodiments of the present application provide an array substrate and a display device, which can improve the display effect of the display device.
  • the technical solution is as follows:
  • an array substrate including:
  • a first insulating layer and a second insulating layer are sequentially stacked in a direction perpendicular to and away from the substrate;
  • a first electrode located on the side of the first insulating layer close to the substrate
  • a second electrode located between the first insulating layer and the second insulating layer
  • an overlapping electrode located on the side of the second insulating layer facing away from the substrate;
  • the array substrate has a plurality of first via holes and a plurality of second via holes, the overlapping electrode is electrically connected to the first electrode through the plurality of first via holes, and the overlapping electrode passes through The plurality of second via holes are electrically connected to the second electrode;
  • the plurality of first via holes are arranged in at least one row
  • the plurality of second via holes are arranged in at least one row
  • the at least one row of first via holes and at least one row of second via holes are arranged in multiple columns.
  • the orthographic projection of the first electrode on the substrate covers: at least part of the area between an adjacent row of first via holes and a row of adjacent second via holes.
  • both the first electrode and the second electrode are strip electrodes, the width of the first electrode is greater than the width of the second electrode, and the orthographic projection of the second electrode on the substrate is Located within the orthographic projection of the first electrode on the substrate.
  • the first electrode has at least one hollow hole
  • the orthographic projection of the at least one hollow hole on the substrate is located between the orthographic projection of the at least one row of first via holes on the substrate and the orthogonal projection of the at least one hollow hole on the substrate.
  • the at least one row of second via holes is between orthogonal projections on the substrate, and the area of the at least one hollow hole on the substrate is smaller than the area of the at least one row of first via holes on the substrate.
  • the total area of the orthographic projection on the substrate is smaller than the total area of the orthographic projection of a row of second via holes on the substrate.
  • the first electrode includes: a first electrode strip and a second electrode strip arranged in parallel, and at least one first connecting arm located between the first electrode strip and the second electrode strip;
  • the orthographic projections of the plurality of first via holes on the substrate are all located within the orthographic projection of the first electrode strip on the substrate, and at least some of the second via holes in the plurality of second via holes are located within the orthographic projection of the first electrode strip on the substrate.
  • the orthographic projection of the via hole on the substrate is located within the orthographic projection of the second electrode strip on the substrate, and is located within the orthographic projection of the second electrode on the substrate.
  • the orthographic projection of the first connecting arm on the substrate covers: the entire area between the first target via hole and the second target via hole, and the first target via hole is located in the plurality of Any first via hole among the first via holes, the second target via hole is an orthographic projection of the plurality of second via holes that overlaps with the second electrode strip and is adjacent to the first target via hole of the second via.
  • the plurality of second via holes include: at least one first overlapping via hole and a plurality of second overlapping via holes;
  • the second electrode includes: a second electrode body, and the at least one At least one second connecting arm corresponding to the first overlapping via hole, the second connecting arm is electrically connected to the second electrode body;
  • the orthographic projection of the at least one first overlapping via hole on the substrate is located within the orthographic projection of the first electrode strip on the substrate, and is located on the corresponding second connection arm on the substrate. within the orthographic projection on the bottom;
  • the orthographic projections of the plurality of second overlapping vias on the substrate are all located within the orthographic projection of the second electrode strips on the substrate, and are located on the second electrode body on the substrate. within the orthographic projection on the substrate.
  • the plurality of first via holes are arranged in at least one row, and one first overlapping via hole is located between two adjacent first via holes in the row of first via holes;
  • a plurality of second overlapping via arrays are arranged in at least one row.
  • first connecting arms and the number of the second connecting arms are multiple, multiple first connecting arms and multiple second connecting arms alternate one by one. distributed, and there is a gap between the adjacent first connecting arms and the second connecting arms.
  • the boundary of the orthographic projection of the first connecting arm on the substrate coincides with the boundary of the orthographic projection of the second connecting arm on the substrate.
  • the plurality of first via holes are arranged in multiple rows and columns
  • the plurality of second via holes are arranged in multiple rows and columns
  • the first via holes in the multiple rows are connected to the plurality of rows.
  • the second vias correspond one to one
  • a row of first vias and a corresponding row of second vias are arranged in one row
  • the orthographic projection of the first electrode on the substrate covers: the first via in an adjacent column At least a portion of the area between the electrode and a row of second electrodes.
  • the first electrode has at least one first strip hole, and the orthographic projection of the first strip hole on the substrate is located on the substrate in two adjacent rows of the first via holes. between the orthographic projections on the substrate, and between the orthographic projections of two adjacent rows of second via holes on the substrate.
  • the orthographic projection of the second electrode on the substrate is located within the orthographic projection of the first electrode on the substrate, and the second electrode has at least one second strip hole, so The at least one second strip hole corresponds to the at least one first strip hole, and the partial boundary of the orthographic projection of the second strip hole on the substrate is consistent with the corresponding first strip hole.
  • the partial boundaries of the orthographic projections on the substrate coincide with each other.
  • the plurality of first via holes are arranged in at least two rows, and the plurality of second via holes include: at least one row of first overlapping via holes, and one row of the first overlapping via holes is distributed in two rows. Between the first via holes in adjacent rows, the orthographic projection of the first electrode on the substrate covers: the first overlapping via holes in one row and the first via holes in two adjacent rows. All areas between holes.
  • the plurality of second vias also include: a plurality of second overlapping vias, one of the second overlapping vias is located between two adjacent first vias in a row of the first vias. between vias;
  • the second electrode includes: a strip-shaped second electrode body, and a plurality of electrode blocks corresponding to the plurality of second overlapping via holes.
  • the second electrode body is electrically connected to the electrode block,
  • the orthographic projection of the second electrode body on the substrate is located within the orthographic projection of the at least one row of first overlapping via holes on the substrate, and the orthographic projection of the electrode block on the substrate Located within the orthographic projection of the corresponding second overlapping via hole on the substrate.
  • some of the second overlapping vias among the plurality of second overlapping vias are arranged in one row with one row of the first vias in two adjacent rows of the first vias, and the other part of the first vias are arranged in one row.
  • the first via holes in the other row of the two adjacent rows of the two overlapping via holes are arranged in one row.
  • the substrate has a display area and a non-display area located at the periphery of the display area;
  • the array substrate further includes: a plurality of gate lines located in the display area, and a gate drive GOA circuit located in the non-display area, the GOA circuit having a plurality of gate lines corresponding to the plurality of gate lines.
  • the GOA unit includes: the first electrode and the second electrode, the first electrode in the GOA unit is electrically connected to the corresponding gate line, and the second electrode in the GOA unit is connected to the corresponding signal output terminal. Electrical connection.
  • an array substrate including:
  • a first insulating layer and a second insulating layer are sequentially stacked in a direction perpendicular to and away from the substrate;
  • a first electrode located on the side of the first insulating layer close to the substrate
  • a second electrode located between the first insulating layer and the second insulating layer
  • an overlapping electrode located on the side of the second insulating layer facing away from the substrate;
  • the array substrate has a plurality of first via holes and a plurality of second via holes, the overlapping electrode is electrically connected to the first electrode through the plurality of first via holes, and the overlapping electrode passes through The plurality of second via holes are electrically connected to the second electrode;
  • the orthographic projection of the first electrode on the substrate does not coincide with the orthographic projection of the second electrode on the substrate.
  • the first electrode includes: a plurality of first connection arms, and a first electrode body for connecting the plurality of first connection arms, the plurality of first via holes on the substrate
  • the orthographic projection of is located within the orthographic projection of the plurality of first connecting arms on the substrate;
  • the second electrode includes: a plurality of second connection arms, and a second electrode body for connecting the plurality of second connection arms, and the orthographic projection of the plurality of second via holes on the substrate is located at The plurality of second connecting arms are within an orthographic projection on the substrate;
  • the plurality of first connecting arms and the plurality of second connecting arms are distributed alternately one by one.
  • both the first electrode and the second electrode are in a strip shape, the extension direction of the first electrode is parallel to the extension direction of the second electrode, and the first electrode is on the substrate. There is a gap between the orthographic projection of the second electrode and the orthographic projection of the second electrode on the substrate.
  • a display device which device includes: an array substrate and a color filter substrate arranged oppositely, and a liquid crystal layer located between the array substrate and the color filter substrate; the array substrate is the above-mentioned array substrate.
  • An embodiment of the present application provides an array substrate, including: a substrate, a first insulating layer, a second insulating layer, a first electrode, a second electrode and a bonding electrode.
  • the orthographic projection of the first electrode on the substrate covers: the area between at least one first via hole and at least one second via hole, there is a stacked arrangement in the area between the first via hole and the second via hole.
  • the first electrode, the first insulating layer and the second insulating layer are arranged in a stack, and the first electrode, the first insulating layer, the second electrode and the second insulating layer are stacked in the area around the second via hole.
  • the height difference between the portion of the overlapping electrode located between the first via hole and the second via hole and the portion of the overlapping electrode located around the second via hole is small, and this height difference is the second electrode thickness of.
  • the climbing height of the overlapping electrode is smaller, which effectively reduces the probability of circuit breakage in the overlapping electrode and improves the electrical connection effect between the first electrode and the second electrode.
  • Figure 1 is a top view of a currently common array substrate
  • Figure 2 is a top view of a single GOA unit in the array substrate shown in Figure 1;
  • Figure 3 is a cross-sectional view of the GOA unit shown in Figure 2 at A-A';
  • Figure 4 is a schematic diagram of the film structure of an array substrate provided by an embodiment of the present application.
  • Figure 5 is a top view of an array substrate provided by an embodiment of the present application.
  • Figure 6 is a top view of a single GOA unit in an array substrate provided by an embodiment of the present application.
  • Figure 7 is a top view of a single GOA unit in another array substrate provided by the embodiment of the present application.
  • Figure 8 is a top view of a single GOA unit in another array substrate provided by the embodiment of the present application.
  • Figure 9 is a top view of a single GOA unit in another array substrate provided by the embodiment of the present application.
  • Figure 10 is a schematic diagram of the overlapping resistance value of the overlapping electrode 600 in the GOA unit shown in Figure 9;
  • Figure 11 is a top view of a single GOA unit in another array substrate provided by the embodiment of the present application.
  • Figure 12 is a top view of a single GOA unit in another array substrate provided by the embodiment of the present application.
  • Figure 13 is a top view of a single GOA unit in another array substrate provided by the embodiment of the present application.
  • Figure 14 is a top view of a single GOA unit in another array substrate provided by the embodiment of the present application.
  • Figure 15 is a top view of a single GOA unit in another array substrate provided by an embodiment of the present application.
  • Figure 16 is a cross-sectional view of the array substrate shown in Figure 15 at position B-B';
  • Figure 17 is an equivalent circuit schematic diagram of the overlapping resistance value of the overlapping electrode 600 in the GOA unit shown in Figure 15;
  • FIG. 18 is a top view of a single GOA unit in another array substrate provided by an embodiment of the present application.
  • the array substrate 00 may have a display area 0a and a non-display area 0b located at the periphery of the display area 0a.
  • a plurality of gate lines 01 arranged in parallel are provided in the display area 0a, and a GOA circuit 02 is provided in the non-display area 0b.
  • the GOA circuit 02 can be electrically connected to multiple gate lines 01 .
  • the GOA circuit 02 may have a plurality of GOA units 021 corresponding to the plurality of gate lines 01 , and the GOA units 021 may be electrically connected to the corresponding gate lines 01 .
  • FIG. 2 is a top view of a single GOA unit in the array substrate shown in Figure 1
  • Figure 3 is a cross-sectional view of the GOA unit shown in Figure 2 at A-A'.
  • the GOA unit 021 may include: a first electrode 03, a second electrode 04, and an overlapping electrode 05.
  • the first electrode 03 in the GOA unit 021 may be electrically connected to the gate line 01 in the display area 0a
  • the second electrode 04 in the GOA unit 021 may be electrically connected to the signal output terminal in the GOA circuit 021.
  • the first electrode 03 and the second electrode 04 can be overlapped through the overlapping electrode 05.
  • the signal output end in the GOA circuit 021 can be transmitted to the gate through the second electrode 04, the overlapping electrode 05 and the first electrode 03 in sequence.
  • Line 01 enables gate line 01 to receive the gate drive signal output from the signal output terminal.
  • the GOA unit 021 may be disposed on the substrate 06 in the array substrate 00 , and the array substrate 00 may further include: a first insulating layer 07 and a second insulating layer 08 .
  • the first electrode 01 may be located on the substrate 06
  • the first insulating layer 07 may be located on a side of the first electrode 03 facing away from the substrate 06
  • the second electrode 04 is located on a side of the first insulating layer 07 facing away from the substrate 06.
  • the two insulating layers 08 are located on the side facing away from the substrate 06
  • the overlapping electrode 05 is located on the side of the second insulating layer 08 facing away from the substrate 06 .
  • the array substrate 00 has a first via hole V01 penetrating the first insulating layer 07 and the second insulating layer 08 , and a second via hole V02 penetrating the second insulating layer 08 .
  • the orthographic projection of the first via hole V01 on the substrate 06 is located within the orthographic projection of the first electrode 03 on the substrate, so that the overlapping electrode 05 can overlap the first electrode 03 through the first via hole V01;
  • the orthographic projection of the two via holes V02 on the substrate 06 is located within the orthographic projection of the second electrode 04 on the substrate 06 , so that the overlapping electrode 05 can also overlap the second electrode 04 through the second via hole V02 . In this way, it can be ensured that the first electrode 03 and the second electrode 04 can be electrically connected through the overlapping electrode 05 .
  • the array substrate 00 generally also includes: a third electrode 09 .
  • the third electrode 09 is arranged in the same layer as the first electrode 03 and has the same material, and the orthographic projection of the second electrode 04 on the substrate 06 is located within the orthographic projection of the third electrode 09 on the substrate 06.
  • the third electrode 09 There is a gap d0 between the substrate 06 and the first electrode 03 .
  • the height difference H between the part of the overlapping electrode 05 located in the area where the gap d0 is located and the part of the overlapping electrode 05 located around the second via hole V02 is relatively large.
  • This height difference H is the third electrode 09
  • the sum of the thickness and the thickness of the second electrode 04 causes the overlapping electrode 05 to climb steeply before it can overlap with the second electrode 05 .
  • the climbing height of the overlapping electrode 05 is large, the overlapping electrode 05 is prone to circuit breakage, resulting in poor electrical connection between the first electrode 03 and the second electrode 04 , which in turn causes the GOA circuit 02 and
  • the electrical connection effect between the multiple gate lines 01 is poor, which will seriously affect the display effect of the display device integrated with the array substrate 00 .
  • FIG. 4 is a schematic diagram of the film structure of an array substrate provided by an embodiment of the present application.
  • the array substrate 000 includes: a substrate 100, a first insulating layer 200, a second insulating layer 300, a first electrode 400, a second electrode 500 and a bonding electrode 600.
  • the first insulating layer 200 and the second insulating layer 300 in the array substrate 000 are stacked sequentially in a direction vertical and away from the substrate 100 .
  • the first electrode 400 in the array substrate 000 is located on the side of the first insulating layer 200 close to the substrate 100, the second electrode 500 is located between the first insulating layer 200 and the second insulating layer 300, and the overlapping electrode 600 is located on the second insulating layer. 300 is the side facing away from the substrate 100 .
  • the array substrate 000 may have a plurality of first via holes V1 and a plurality of second via holes V2.
  • the overlapping electrode 600 can overlap with the first electrode 400 through a plurality of first via holes V1, and the overlapping electrode 600 can also overlap with the second electrode 500 through a plurality of second via holes V2. In this way, the second electrode 500 can overlap the first electrode 400 through the overlapping electrode 600 .
  • the first via hole V1 in the array substrate 000 is a via hole that penetrates both the second insulation layer 300 and the first insulation layer 200
  • the second via hole V2 in the array substrate 000 is a via hole that only penetrates the second insulation layer 300 Vias.
  • the orthographic projection of the plurality of first via holes V1 on the substrate 100 is located within the orthographic projection of the first electrode 400 on the substrate 100
  • the orthographic projection of the first electrode 400 on the substrate 100 is located within the orthographic projection of the overlapping electrode 600 on the substrate 100 .
  • the orthographic projection on the bottom 100 it is ensured that the overlapping electrode 600 can overlap the first electrode 400 through the plurality of first via holes V1 .
  • the orthographic projection of the plurality of second via holes V2 on the substrate 100 is located within the orthographic projection of the second electrode 500 on the substrate 100
  • the orthographic projection of the second electrode 500 on the substrate 100 is located on the overlapping electrode. 600 is within the orthographic projection on the substrate 100. In this way, it can be ensured that the overlapping electrode 600 can overlap with the second electrode 500 through the plurality of second via holes V2.
  • the orthographic projection of the first electrode 400 on the substrate 100 covers: the area between at least one first via hole V1 and at least one second via hole V2, the area located at the first via hole V1
  • the first electrode 400, the first insulating layer 200 and the second insulating layer 300 are stacked in the area between the second via hole V2 and the first electrode 400, the first insulating layer 200 and the second insulating layer 300 are stacked in the area around the second via hole V2.
  • the height difference h1 between the portion of the overlapping electrode 600 located between the first via hole V1 and the second via hole V2 and the portion of the overlapping electrode 600 located around the second via hole V2 is small.
  • This height The difference h1 is the thickness of the second electrode 500 .
  • the climbing height of the overlapping electrode 600 is small, which effectively reduces the probability of an open circuit in the overlapping electrode 600, so that the first electrode 400 and the second electrode 500 The electrical connection between them is better.
  • Figure 5 is a top view of an array substrate provided by an embodiment of the present application.
  • the array substrate 000 has a display area 00a and a non-display area 00b located at the periphery of the display area 00a.
  • the array substrate 000 may further include: a plurality of gate lines 700 located in the display area 00a, and a GOA circuit 800 located in the non-display area 00b.
  • the GOA circuit 800 may have a plurality of GOA units 801 corresponding to a plurality of gate lines 700, and a plurality of signal output terminals (not shown in the figure) corresponding to the plurality of GOA units 801 one-to-one.
  • the GOA unit 801 may include: a first electrode 400 and a second electrode 500.
  • the first electrode 400 in the GOA unit 801 may be electrically connected to the corresponding gate line 700
  • the second electrode 500 in the GOA unit 801 may be electrically connected to the corresponding signal output terminal.
  • the GOA unit 801 usually also includes a bonding electrode 600, and the signal output end can send the gate driving signal to the gate line 700 through the bonding electrode 600, the second electrode 500 and the first electrode 400 in sequence.
  • the electrical connection effect between the first electrode 400 and the second electrode 500 is good, it can be ensured that the electrical connection effect between the GOA unit 801 and the gate line 700 is good, so that the GOA circuit 800 can communicate with multiple gate lines.
  • the electrical connection between lines 700 is better.
  • an array substrate including: a substrate, a first insulating layer, a second insulating layer, a first electrode, a second electrode and a bonding electrode.
  • the orthographic projection of the first electrode on the substrate covers: the area between at least one first via hole and at least one second via hole, there is a stacked arrangement in the area between the first via hole and the second via hole.
  • the first electrode, the first insulating layer and the second insulating layer are arranged in a stack, and the first electrode, the first insulating layer, the second electrode and the second insulating layer are stacked in the area around the second via hole.
  • the height difference between the portion of the overlapping electrode located between the first via hole and the second via hole and the portion of the overlapping electrode located around the second via hole is small, and this height difference is the second electrode thickness of.
  • the climbing height of the overlapping electrode is smaller, which effectively reduces the probability of circuit breakage in the overlapping electrode and improves the electrical connection effect between the first electrode and the second electrode.
  • the GOA unit 801 in the GOA circuit 800 in the array substrate 000 has various structures.
  • the embodiment of the present application takes the following four optional implementation methods as examples for schematic description:
  • FIG. 6 is a top view of a single GOA unit in an array substrate provided by an embodiment of the present application.
  • the plurality of first via holes V1 in the array substrate 000 are arranged in at least one row
  • the plurality of second via holes V2 in the array substrate 000 are arranged in at least one row.
  • At least one row of first via holes V1 and at least one row of second via holes V2 are arranged in multiple columns.
  • the orthographic projection of the first electrode 400 on the substrate covers: the adjacent row of first via holes V1 and the adjacent row of second via holes. At least part of the area between V2. It should be noted that for the schematic diagram of the film layer taken at position A-A’ in Figure 6, reference can be made to Figure 4.
  • a plurality of first via holes V1 are arranged in a row, and a plurality of second via holes V2 are also arranged in a row.
  • the orthographic projection of the first electrode 400 on the substrate 100 covers: at least part of the area between the adjacent row of first via holes V1 and the row of second via holes V2, the row of first via holes V1 and the row of second via holes V2 At least part of the area between the via holes V2 has a stacked first electrode 400, a first insulating layer 200 and a second insulating layer 300.
  • An area around the second via hole V2 has a stacked first electrode 400, a first insulating layer 200 and a second insulating layer 300.
  • An insulating layer 200, a second electrode 500 and a second insulating layer 300 In this way, it can be ensured that the height difference h1 between at least the portion of the overlapping electrode 600 located between the first via hole V1 and the second via hole V2 and the portion of the overlapping electrode 600 located around the second via hole V2 is small. , effectively reducing the probability of an open circuit in the overlapping electrode 600.
  • both the first electrode 400 and the second electrode 500 are strip electrodes, the width of the first electrode 400 is greater than the width of the second electrode 500, and the orthographic projection of the second electrode 500 on the substrate 100 is located where the first electrode 400 is. within the orthographic projection on substrate 100.
  • the orthographic coverage of the first electrode 400 on the substrate 100 can be ensured: The entire area d1 located between the adjacent row of first via holes V1 and the adjacent row of second via holes V2. In this way, it can be ensured that the height difference h1 between the portion of the overlapping electrode 600 located between the first via hole V1 and the second via hole V2 and the portion of the overlapping electrode 600 located around the second via hole V2 is small. , thereby further reducing the probability of an open circuit in the overlapping electrode 600 .
  • FIG. 7 is a top view of a single GOA unit in another array substrate provided by an embodiment of the present application.
  • the first electrode 400 may have at least one hollow hole M, at least The orthographic projection of one hollow hole M on the substrate 100 is located between the orthographic projection of at least one row of first via holes V1 on the substrate 100 and the orthographic projection of at least one row of second via holes V2 on the substrate 100, and at least one The area of the orthographic projection of the hollow hole M on the substrate 100 is smaller than the total area of the orthographic projection of a row of first via holes V1 on the substrate 100 , and is smaller than the orthographic projection of a row of second via holes V2 on the substrate 100 of total area.
  • the first electrode 400 has a hollow hole M.
  • the area of the orthogonal projection of a hollow hole M on the substrate 100 is both smaller than the total area of the orthogonal projection of a row of first via holes V1 on the substrate 100 and smaller than the area of a row of second via holes V2 on the substrate 100 .
  • the total area of the orthographic projection on the substrate 100 can ensure that the orthographic projection of the first electrode 400 on the substrate 100 can cover the partial area between the adjacent row of first electrodes 400 and the adjacent row of second electrodes 500, and thus The probability of an open circuit in the overlapping electrode 600 can be reduced.
  • the first electrode 400 is generally made of a metal conductor material.
  • the area of the orthographic projection of the first electrode 400 on the substrate 100 can be reduced, thereby reducing the During the manufacturing process of the array substrate 000, the probability of electrostatic breakdown occurring due to charge accumulation at the position of the first electrode 400 is improved, thereby improving the display effect of the display device integrated with the array substrate.
  • the first electrode 400 includes: a first electrode strip 401 and a second electrode strip 402 arranged in parallel, and at least one first connecting arm 403 located between the first electrode strip 401 and the second electrode strip 402 .
  • the number of first connecting arms 403 in the first electrode 400 may be multiple, one end of each first connecting arm 403 may be connected to the first electrode strip 401, and the other end of each first connecting arm 403 may be connected to the first electrode strip 401.
  • One end may be connected to the second electrode strip 402 , and the extending direction of each first connecting arm 403 is perpendicular to the extending direction of the first electrode strip 401 .
  • the orthographic projections of the plurality of first via holes V1 in the array substrate 000 on the substrate 100 are all located within the orthographic projection of the first electrode strips 401 on the substrate 100, and the plurality of second via holes V2 in the array substrate 000 are located in The orthographic projection of at least part of the second via hole V2 on the substrate 100 is located within the orthographic projection of the second electrode strip 402 on the substrate, and is located within the orthographic projection of the second electrode 500 on the substrate 100 .
  • the schematic diagram of the film layer in the cross-section at position A-A’ in Figure 8 can be referred to Figure 4 .
  • the first connecting arm 403 between the first electrode strip 401 and the second electrode strip 402
  • the first connecting arm 403, the first insulating layer 200 and the second insulating layer 300 are provided, and the first electrode 400, the first insulating layer 200, the second electrode 500 and the first electrode 500 are stacked in the area around the second via hole V2.
  • Two insulation layers 300 In this way, it can be ensured that the height difference h1 between at least the portion of the overlapping electrode 600 located on the first connecting arm 403 and the portion of the overlapping electrode 600 located around the second via hole V2 is small, effectively reducing the risk of overlapping. The probability that the electrode 600 is disconnected.
  • the orthographic projection of the first connecting arm 403 on the substrate 100 covers: the entire area between the first target via hole P1 and the second target via hole P2.
  • the first target via P1 is located in any first via V1 among the plurality of first vias V1
  • the second target via P2 is an orthographic projection of the plurality of second vias V2 that overlaps with the second electrode strip 402 , and the second via hole V2 adjacent to the first target via hole P1.
  • the part of the overlapping electrode 600 located on the first connecting arm 403 can be directly electrically connected to the part of the overlapping electrode 600 located around the second via hole V2, and the first electrode can be further improved.
  • 300 is electrically connected to the second electrode 400.
  • FIG. 9 is a top view of a single GOA unit in another array substrate provided by an embodiment of the present application.
  • the plurality of second vias V2 include: at least one first overlapping via V21 and a plurality of second overlapping vias V22;
  • the second electrode 500 includes: a second electrode body 501, and at least one first overlapping via
  • the holes V21 correspond to at least one second connecting arm 501, and the second connecting arm 501 is electrically connected to the second electrode body 501.
  • the extending direction of the first connecting arm 403 is parallel to the extending direction of the second connecting arm 502 .
  • the orthographic projection of at least one first overlapping via V21 on the substrate 100 is located within the orthographic projection of the first electrode strip 401 on the substrate 100 and is located in the orthographic projection of the corresponding second connection arm 502 on the substrate.
  • the orthographic projections of the plurality of second overlapping vias V22 on the substrate 100 are all located within the orthographic projection of the second electrode strip 500 on the substrate, and are located within the orthographic projection of the second electrode body 501 on the substrate 100 . It should be noted that the schematic diagram of the film layer in the cross-section at position A-A’ in Figure 9 can be referred to Figure 4 .
  • the first electrode 400 , the first insulating layer 200 and the second insulating layer 300 are stacked in the area between the first via V1 and the first overlapping via V21 .
  • the first electrode 400, the first insulating layer 200, the second electrode 500 and the second insulating layer 300 are stacked in the area around the hole V21.
  • the height difference h1 between the portion of the overlapping electrode 600 located between the first via hole V1 and the first overlapping via hole V21 and the portion of the overlapping electrode 600 located around the first overlapping via hole V21 is relatively large. is small, and this height difference h1 is the thickness of the second electrode 500 . In this way, when the overlapping electrode 600 overlaps the second electrode 500, the climbing height of the overlapping electrode 600 is also small.
  • FIG. 10 is a schematic diagram of the overlapping resistance value of the overlapping electrode 600 in the GOA unit shown in FIG. 9 .
  • the overlapping resistance value of the first via hole V1 and the first overlapping via hole V21 in the overlapping electrode 600 includes: the resistance value R1 of the overlapping electrode 600 located in the first via hole V1, the resistance value R1 located in the first overlapping via hole V1, The resistance value R2 of the overlapping electrode 600 in the via hole V21 and the resistance value R3 between the first overlapping via hole V21 and the first via hole V1.
  • the first via hole V1 and the first overlapping via hole V21 have the same shape and size. In this way, in different GOA units, the resistance value R1 of the overlapping electrode 600 located in the first via hole V1 is the same; the resistance value R2 of the overlapping electrode 600 located in the first overlapping via hole V21 is also the same.
  • R0 is the unit resistance of the overlapping electrode 600
  • W is the width of the overlapping electrode 600 along the extension direction of the first electrode strip 401.
  • the unit resistance R0 is only related to the thickness and material of the overlapping electrode 600 .
  • the overlapping electrode 600 overlaps the first via hole V1 through the first overlapping via hole V21
  • the distance X between the first overlapping via hole V21 and the first via hole V1 is smaller.
  • the climbing height h1 of the overlapping electrode 600 is also small. Therefore, the resistance value R3 between the first overlapping via hole V21 and the first via hole V1 is also small; thereby reducing the risk that the overlapping electrode 600 overlaps the first via hole V1 through the first overlapping via hole V21
  • the overlapping resistance value reduces the interference to the signal transmitted in the overlapping electrode 600 and improves the overlapping efficiency of the overlapping electrode 600.
  • a plurality of first via holes V1 are arranged in at least one row, and a first overlapping via hole V21 is located between two adjacent first via holes V1 in a row of first via holes V1. space; a plurality of second overlapping via V21 arrays are arranged in at least one row.
  • the distance between the first overlapping via hole V1 and the first overlapping via hole V21 can be improved.
  • the hole V21 connects the first electrode 400 and the second electrode 500 uniformly, ensuring effective electrical connection between the first electrode 400 and the second electrode 500 .
  • first connecting arms 403 and the number of the second connecting arms 502 are both multiple, the plurality of first connecting arms 403 and the plurality of second connecting arms 502 are connected together. They are distributed alternately, and there are gaps between adjacent first connecting arms 403 and second connecting arms 502 .
  • the overlapping electrode 600 located between the first via hole V1 and the first overlapping via hole V21, but also the portion of the overlapping electrode 600 located around the first overlapping via hole V21
  • the height difference h1 is small; and the height difference h1 between the area of the overlapping electrode 600 where the first connecting arm 403 is located and the part of the overlapping electrode 600 located around the second via hole V2 is also small.
  • the overlapping electrode 600 overlaps the second electrode 500, the area of the area with a smaller climbing height in the overlapping electrode 600 is increased, thereby further reducing the probability of an open circuit in the overlapping electrode 600.
  • the boundary of the orthographic projection of the first connecting arm 403 on the substrate 100 coincides with the boundary of the orthographic projection of the second connecting arm 502 on the substrate 101 .
  • the area of the area with a smaller climbing height in the overlapping electrode 600 is the largest, and the probability of an open circuit in the overlapping electrode 600 is minimized.
  • FIG. 11 is a top view of a single GOA unit in another array substrate provided by an embodiment of the present application.
  • a plurality of first vias V1 are arranged in multiple rows and columns
  • a plurality of second vias V2 are arranged in multiple rows and columns
  • the first vias V1 in multiple rows correspond to the second vias V2 in multiple rows.
  • a row of first via holes V1 and a corresponding row of second via holes V2 are arranged in one row
  • the orthographic projection of the first electrode 400 on the substrate covers: located between the adjacent column of first electrodes 400 and the adjacent column of second electrodes 500 at least part of the area.
  • first via hole V1 and the second via hole V2 are located in the first row.
  • the first electrode 400, the first insulating layer 200 and the second insulating layer 300 are stacked in the area between the via hole V1 and the second via hole V2, and the first electrode 400, the first insulating layer 200 and the second insulating layer 300 are stacked in the area around the second via hole V2.
  • the electrode 400, the first insulating layer 200, the second electrode 500 and the second insulating layer 300 are stacked in the first row.
  • Figure 12 is a top view of a single GOA unit in another array substrate provided by an embodiment of the present application.
  • the first electrode 400 has at least one first strip hole L1, and the orthographic projection of the first strip hole L1 on the substrate 100 is located between the orthographic projections of two adjacent rows of first via holes V1 on the substrate 100. And is located between the orthographic projections of two adjacent rows of second via holes V2 on the substrate.
  • the orthographic projection of the second electrode 500 on the substrate is located within the orthographic projection of the first electrode 400 on the substrate, and the second electrode 500 has at least one second strip hole L2, at least A second strip hole L2 corresponds one-to-one to at least one first strip hole L1, and the partial boundary of the orthographic projection of the second strip hole L2 on the substrate 100 is the same as the corresponding first strip hole L1 on the substrate 100.
  • the partial boundaries of the orthographic projection coincide with each other.
  • the area of the orthogonal projection of the first electrode 400 on the substrate 100 can be further reduced. , further reducing the probability of electrostatic breakdown occurring due to charge accumulation at the position of the first electrode 400 during the manufacturing process of the array substrate 000 .
  • FIG. 13 is a top view of a single GOA unit in another array substrate provided by an embodiment of the present application.
  • the plurality of first vias V1 are arranged in at least two rows.
  • the plurality of second vias V2 include: at least one row of first overlapping vias V21.
  • One row of first overlapping vias V21 is distributed in two adjacent rows of first overlapping vias.
  • the orthographic projection of the first electrode 400 on the substrate 100 covers: the entire area between one row of first overlapping via holes V21 and two adjacent rows of first via holes V1.
  • the schematic diagram of the film layer in the cross-section at position A-A' in Figure 13 can be referred to Figure 4.
  • one row of first overlapping vias V21 can overlap with two adjacent rows of first vias V1 through the overlapping electrodes 600, thereby increasing the number of overlapping with the first overlapping vias V21.
  • the height difference h1 between the portion of the overlapping electrode 600 located between the first via hole V1 and the first overlapping via hole V21 and the portion of the overlapping electrode 600 located around the first overlapping via hole V21 is small. , therefore, the area of the area with a smaller climbing height in the overlapping electrode 600 is increased, thereby further reducing the probability of an open circuit in the overlapping electrode 600 .
  • FIG. 14 is a top view of a single GOA unit in another array substrate provided by an embodiment of the present application.
  • the plurality of second via holes V2 also include: a plurality of second overlapping via holes V22, and one second overlapping via hole V22 is located between two adjacent first via holes V1 in a row of first via holes V1.
  • the second electrode 500 includes: a strip-shaped second electrode body 501 and a plurality of electrode blocks 503 corresponding to a plurality of second overlapping via holes V22.
  • the second electrode body 501 is electrically connected to the electrode blocks 503.
  • the orthographic projection of the electrode body 501 on the substrate 100 is located within the orthographic projection of at least one row of first overlapping vias V21 on the substrate 100, and the orthographic projection of the electrode block 503 on the substrate 100 is located on the corresponding second overlapping via.
  • Hole V22 is in the orthographic projection on substrate 100 .
  • the second via hole V2 not only includes a plurality of first overlapping via holes V21 located on the strip-shaped second electrode body 501 , but also includes a plurality of second via holes V21 corresponding to the plurality of electrode blocks 503 one-to-one.
  • the overlapping via holes V22 thus increase the number of the second via holes V2, thereby further increasing the area of the area of the overlapping electrode 600 with a smaller climbing height.
  • a part of the second overlapping vias V22 among the plurality of second overlapping vias V22 and one row of the first vias V1 among the two adjacent rows of the first vias V1 are arranged as One row, the other part of the second overlapping via holes V22 and the other row of the first via holes V1 in the two adjacent rows of the first via holes V1 are arranged in one row. In this way, the effectiveness of the electrical connection between the first electrode 400 and the second electrode 500 is improved.
  • the first electrode 400 also has a plurality of hollow structures U. Because the first electrode 400 is generally made of metal conductor material. Therefore, when a plurality of hollow structures U are provided in the first electrode 400, the area of the orthographic projection of the first electrode 400 on the substrate 100 can be reduced, thereby reducing the amount of charge generated during the manufacturing process of the array substrate 000. The probability of electrostatic breakdown occurring due to accumulation at the position of the first electrode 400 improves the display effect of the display device integrated with the array substrate.
  • an array substrate including: a substrate, a first insulating layer, a second insulating layer, a first electrode, a second electrode and a bonding electrode.
  • the orthographic projection of the first electrode on the substrate covers: the area between at least one first via hole and at least one second via hole, there is a stacked arrangement in the area between the first via hole and the second via hole.
  • the first electrode, the first insulating layer and the second insulating layer are arranged in a stack, and the first electrode, the first insulating layer, the second electrode and the second insulating layer are stacked in the area around the second via hole.
  • the height difference between the portion of the overlapping electrode located between the first via hole and the second via hole and the portion of the overlapping electrode located around the second via hole is small, and this height difference is the second electrode thickness of.
  • the climbing height of the overlapping electrode is smaller, which effectively reduces the probability of circuit breakage in the overlapping electrode and improves the electrical connection effect between the first electrode and the second electrode.
  • FIG. 15 is a top view of a single GOA unit in another array substrate provided by an embodiment of the present application.
  • Fig. 16 is a cross-sectional view of the array substrate shown in Fig. 15 at position B-B'.
  • the array substrate 000 may include a substrate 100, a first insulating layer 200, a second insulating layer 300, a first electrode 400, a second electrode 500, and a bonding electrode 600.
  • the first insulating layer 200 and the second insulating layer 300 in the array substrate 000 are stacked sequentially in a direction vertical and away from the substrate 100 .
  • the first electrode 400 in the array substrate 000 is located on the side of the first insulating layer 200 close to the substrate 100
  • the second electrode 500 is located between the first insulating layer 200 and the second insulating layer 300
  • the overlapping electrode 600 is located on the second insulating layer.
  • 300 is the side facing away from the substrate 100 .
  • the array substrate 000 may have a plurality of first via holes V1 and a plurality of second via holes V2.
  • the overlapping electrode 600 can overlap with the first electrode 400 through a plurality of first via holes V1, and the overlapping electrode 600 can also overlap with the second electrode 500 through a plurality of second via holes V2. In this way, the second electrode 500 can overlap the first electrode 400 through the overlapping electrode 600 .
  • the orthographic projection of the first electrode 400 on the substrate 100 does not coincide with the orthographic projection of the second electrode 500 on the substrate 100 .
  • the first electrode 400 and the second electrode 500 here both belong to the GOA unit 801 in the GOA circuit 800, and the first electrode 400 in this GOA unit 801 is electrically connected to the gate line in the array substrate 000. , the second electrode 400 in this GOA unit 801 is electrically connected to the signal output terminal in the GOA circuit 800.
  • the position between the first via hole V1 and the second via hole V2 The first insulating layer 200 and the second insulating layer 300 are stacked in the area between them, and the first insulating layer 200, the second electrode 500 and the second insulating layer 300 are stacked in the area around the second via hole V2.
  • the height difference h1 between the portion of the overlapping electrode 600 located between the first via hole V1 and the second via hole V2 and the portion of the overlapping electrode 600 located around the second via hole V2 is also small.
  • This The height difference h1 is the thickness of the second electrode 500 .
  • the climbing height of the overlapping electrode 600 is small, which effectively reduces the probability of an open circuit in the overlapping electrode 600, so that the first electrode 400 and the second electrode 500 The electrical connection between them is better.
  • the first insulating layer 200 and the first electrode 400 that are stacked are present in the area around the first via hole V1.
  • the height difference h2 between the portion of the overlapping electrode 600 located around the first via hole V1 and the portion of the overlapping electrode 600 located around the second via hole V2 is also small, thus improving the performance of the array substrate 000 Flatness.
  • the tightness of the bonding between the array substrate 000 and the color filter substrate in the display device can be improved, and the probability of water vapor entering the display device can be reduced.
  • the first electrode 400 includes: a plurality of first connecting arms 403, and a first electrode body 401 for connecting the plurality of first connecting arms 403, a plurality of first connecting arms 403.
  • the orthographic projection of the via V1 on the substrate 100 is located within the orthographic projection of the plurality of first connection arms 403 on the substrate.
  • the second electrode 500 includes: a plurality of second connection arms 502, and a second electrode body 501 for connecting the plurality of second connection arms 502.
  • the orthographic projections of the plurality of second via holes V2 on the substrate 100 are located at a plurality of The second connecting arm 502 is in the orthographic projection on the substrate 100 .
  • a plurality of first connecting arms 403 and a plurality of second connecting arms 502 are alternately distributed one by one.
  • the overlapping electrode 600 can realize overlapping the first electrode 400 and the second electrode 500 through the first via hole V1 on the first connecting arm 403 and the second via hole V2 on the second connecting arm 502. are connected together, and the plurality of first connecting arms 403 and the plurality of second connecting arms 502 are alternately distributed one by one, which improves the uniformity of overlapping in various areas, thereby improving the electrical conductivity of the first electrode 400 and the second electrode 500. Availability of the connection.
  • FIG. 17 is an equivalent circuit schematic diagram of the overlapping resistance value of the overlapping electrode 600 in the GOA unit shown in FIG. 15 .
  • the calculation method of the overlapping resistance value of the first via hole V1 and the second via hole V2 in the overlapping electrode 600 and the above-mentioned overlapping resistance value of the first via hole V1 and the first overlapping via hole V21 in the overlapping electrode 600 The calculation method of the value is the same and will not be described again here.
  • the resistance value R1 of the overlapping electrode 600 located in the first via hole V1 is connected in parallel, and the resistance value R1 located in the first overlapping via hole V1 is connected in parallel.
  • the resistance value R2 of the overlapping electrode 600 in V21 is connected in parallel. In this way, the greater the number of the first vias V1 and the second vias V2, the smaller the total resistance of R1 when connected in parallel, and the smaller the total resistance of R2 when connected in parallel.
  • the overlapping resistance value of the overlapping electrode 600 includes: the total resistance after 8 R1 are connected in parallel, and 8 R2 are connected in parallel.
  • the total resistance after the first via hole V1 and the second via hole V2 is the resistance value R3.
  • the overlapping resistance value of the overlapping electrode 600 is:
  • the number of the first via holes V1 and the second via holes V2 can be increased, and the number of the overlapping electrodes 600 can be reduced.
  • Lap resistance value the height difference h1 between the portion of the overlapping electrode 600 located between the first via hole V1 and the second via hole V2 and the portion of the overlapping electrode 600 located around the second via hole V2 is also small, so that , the resistance value between the first via hole V1 and the second via hole V2 is also small, thereby further reducing the overlap resistance value of the overlap electrode 600 .
  • Figure 18 is a top view of a single GOA unit in another array substrate provided by an embodiment of the present application.
  • the first electrode 400 and the second electrode 500 are both strip-shaped.
  • the extending direction of the first electrode 400 is parallel to the extending direction of the second electrode 500.
  • the orthographic projection of the first electrode 400 on the substrate is the same as the orthographic projection of the second electrode 500 on the substrate. There is a gap between the orthographic projections on.
  • the orthographic projection of the first electrode 400 on the substrate there is a gap between the orthographic projection of the first electrode 400 on the substrate and the orthographic projection of the second electrode 500 on the substrate, thereby improving the flatness of the array substrate 000 while reducing the cost of the first electrode 400 .
  • the area of the orthographic projection of the first electrode 400 and the second electrode 500 on the substrate 100 can thereby reduce the occurrence of electrostatic shock due to charge accumulation at the positions of the first electrode 400 and the second electrode 500 during the manufacturing process of the array substrate 000 The probability of wearing defects.
  • an array substrate including: a substrate, a first insulating layer, a second insulating layer, a first electrode, a second electrode and a bonding electrode.
  • the area between the first via hole and the second via hole has a stacked first insulating layer and a first insulating layer.
  • the height difference between the portion of the overlapping electrode located between the first via hole and the second via hole and the portion of the overlapping electrode located around the second via hole is also small, and this height difference is the second via hole.
  • the thickness of the electrode In this way, when the overlapping electrode overlaps with the second electrode, the climbing height of the overlapping electrode is smaller, which effectively reduces the probability of circuit breakage in the overlapping electrode and improves the electrical connection effect between the first electrode and the second electrode. better.
  • the first insulating layer and the first electrode that are stacked are present in the area around the first via hole.
  • the height difference between the portion of the overlapping electrode located around the first via hole and the portion of the overlapping electrode located around the second via hole is also smaller, thus improving the flatness of the array substrate.
  • the tightness of the bonding between the array substrate and the color filter substrate in the display device can be improved, and the probability of water vapor entering the display device can be reduced.
  • An embodiment of the present application also provides a display device, which includes: an array substrate 000 and a color filter substrate arranged oppositely, and a liquid crystal layer located between the array substrate 000 and the color filter substrate; the array substrate 000 is the above-mentioned array Substrate000.
  • the display device can be: a monitor, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
  • plurality refers to two or more than two, unless expressly limited otherwise.

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Abstract

本申请公开了一种驱动背板及显示面板，属于显示技术领域。驱动背板包括：衬底，衬底具有多个透光区域和多个子像素区域；位于子像素区域内的像素驱动电路和阳极块，像素驱动电路和阳极块电连接；以及，位于透光区域内修复线和修复电极，修复线的端部与修复电极之间存在空隙；其中，对于任一透光区域内的修复线和修复电极，修复线背离修复电极的一端与第一子像素区域内的阳极块电连接，修复电极与第二子像素区域内的阳极块电连接，第一子像素区域为多个子像素区域中位于这个透光区域一侧的子像素区域，第二子像素区域为多个子像素区域中位于这个透光区域另一侧的子像素区域。该驱动背板可以提高集成有这个驱动背板的显示面板的良率。

Description

阵列基板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板及显示装置。
背景技术
液晶显示器(英文：Liquid Crystal Display，简称：LCD)具有画质好、体积小、重量轻、低驱动电压、低功耗、无辐射和制造成本相对较低等优点，已广泛应用在平板电脑、电视、手机和车载显示器等电子产品中。
相关技术中，显示装置中的阵列基板具有显示区，以及位于显示区周围的非显示区。显示区内具有阵列排布的多个子像素以及多条栅线，一条栅线与一行子像素电连接。非显示区内具有栅极驱动(英文：Gate Driver On Array，中文：GOA)电路。其中，GOA电路可以与多条栅线电连接，且GOA电路用于向多条栅线提供栅极驱动信号。
然而，阵列基板中的GOA电路在与多条栅线电连接时容易发生断路，导致显示装置的显示效果较差。
发明内容
本申请实施例提供了一种阵列基板及显示装置，可以提高显示装置的显示效果，所述技术方案如下：
一方面，提供了一种阵列基板，包括：
衬底；
沿垂直且远离所述衬底的方向依次层叠设置的第一绝缘层和第二绝缘层；
位于所述第一绝缘层靠近所述衬底一侧的第一电极；
位于所述第一绝缘层与所述第二绝缘层之间的第二电极；
以及，位于所述第二绝缘层背离所述衬底一侧的搭接电极；
其中，所述阵列基板具有多个第一过孔和多个第二过孔，所述搭接电极通过所述多个第一过孔与所述第一电极电连接，所述搭接电极通过所述多个第二 过孔与所述第二电极电连接；
所述第一电极在所述衬底上的正投影与所述第二电极在所述衬底上的正投影存在交叠区域，所述第一电极在所述衬底上的正投影覆盖：位于至少一个所述第一过孔与至少一个第二过孔之间的区域。
可选的，所述多个第一过孔排布为至少一行，所述多个第二过孔排布为至少一行，至少一行第一过孔与至少一行第二过孔排布为多列，所述第一电极在所述衬底上的正投影覆盖：位于相邻的一行第一过孔与一行第二过孔之间的至少部分区域。
可选的，所述第一电极与所述第二电极均为条状电极，所述第一电极的宽度大于所述第二电极宽度，所述第二电极在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影内。
可选的，所述第一电极具有至少一个镂空孔，所述至少一个镂空孔在所述衬底上的正投影位于所述至少一行第一过孔在所述衬底上的正投影与所述至少一行第二过孔在所述衬底上的正投影之间，且所述至少一个镂空孔的在所述衬底上的正投影的面积，小于一行所述第一过孔在所述衬底上的正投影的总面积，且小于一行所述第二过孔在所述衬底上的正投影的总面积。
可选的，所述第一电极包括：平行排布的第一电极条和第二电极条，以及位于所述第一电极条与所述第二电极条之间的至少一个第一连接臂；
所述多个第一过孔在所述衬底上的正投影均位于所述第一电极条在所述衬底上的正投影内，所述多个第二过孔中的至少部分第二过孔在所述衬底上的正投影位于所述第二电极条在所述衬底上的正投影内，且位于所述第二电极在所述衬底上的正投影内。
可选的，所述第一连接臂在所述衬底上的正投影覆盖：第一目标过孔与第二目标过孔之间的全部区域，所述第一目标过孔位于所述多个第一过孔中的任一第一过孔，所述第二目标过孔为所述多个第二过孔中正投影与所述第二电极条交叠，且与所述第一目标过孔相邻的第二过孔。
可选的，所述多个第二过孔包括：至少一个第一搭接过孔和多个第二搭接过孔，所述第二电极包括：第二电极本体，以及与所述至少一个第一搭接过孔一一对应的至少一个第二连接臂，所述第二连接臂与所述第二电极本体电连接；
所述至少一个第一搭接过孔在所述衬底上的正投影均位于所述第一电极条 在所述衬底上的正投影内，且位于对应的第二连接臂在所述衬底上的正投影内；
所述多个第二搭接过孔在所述衬底上的正投影均位于所述第二电极条在所述衬底上的正投影内，且均位于所述第二电极本体在所述衬底上的正投影内。
可选的，所述多个第一过孔排布为至少一行，一个所述第一搭接过孔位于一行所述第一过孔中相邻的两个第一过孔之间；所述多个第二搭接过孔阵列排布为至少一行。
可选的，当所述第一连接臂的个数与所述第二连接臂的个数均为多个时，多个所述第一连接臂与多个所述第二连接臂一一交替分布，且相邻的所述第一连接臂与所述第二连接臂之间存在空隙。
可选的，所述第一连接臂在所述衬底上的正投影的边界与所述第二连接臂在所述衬底上的正投影的边界重合。
可选的，所述多个第一过孔排布为多行和多列，所述多个第二过孔排布为多行和多列，多行所述第一过孔与多行所述第二过孔一一对应，一行第一过孔与对应的一行第二过孔排布为一行，所述第一电极在所述衬底上的正投影覆盖：位于相邻的一列第一电极与一列第二电极之间的至少部分区域。
可选的，所述第一电极具有至少一个第一条形孔，所述第一条形孔在所述衬底上的正投影位于两行相邻的所述第一过孔在所述衬底上的正投影之间，且位于两行相邻的所述第二过孔在所述衬底上的正投影之间。
可选的，所述第二电极在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影内，所述第二电极具有至少一个第二条形孔，所述至少一个第二条形孔与所述至少一个第一条形孔一一对应，所述第二条形孔在所述衬底上的正投影的部分边界与对应的第一条形孔在所述衬底上的正投影的部分边界重合。
可选的，所述多个第一过孔排布为至少两行，所述多个第二过孔包括：至少一行第一搭接过孔，一行所述第一搭接过孔分布在两行相邻的所述第一过孔之间，所述第一电极在所述衬底上的正投影覆盖：位于一行所述第一搭接过孔与相邻的两行所述第一过孔之间的全部区域。
可选的，所述多个第二过孔还包括：多个第二搭接过孔，一个所述第二搭接过孔位于一行所述第一过孔中的两个相邻的第一过孔之间；
所述第二电极包括：条状的第二电极本体，以及与所述多个第二搭接过孔 一一对应的多个电极块，所述第二电极本体与所述电极块电连接，所述第二电极本体在所述衬底上的正投影位于所述至少一行第一搭接过孔在所述衬底上的正投影内，所述电极块在所述衬底上的正投影位于对应的第二搭接过孔在所述衬底上的正投影内。
可选的，所述多个第二搭接过孔中的一部分第二搭接过孔与相邻的两行所述第一过孔中的一行第一过孔排布为一行，另一部分第二搭接过孔相邻的两行所述第一过孔中的另一行第一过孔排布为一行。
可选的，所述衬底具有显示区，以及位于所述显示区外围的非显示区；
所述阵列基板还包括：位于所述显示区内的多条栅线，以及位于所述非显示区内的栅极驱动GOA电路，所述GOA电路具有与所述多条栅线对应的多个GOA单元，以及与所述多个GOA单元一一对应的信号输出端；
所述GOA单元包括：所述第一电极和所述第二电极，所述GOA单元中的第一电极与对应的栅线电连接，所述GOA单元中的第二电极与对应的信号输出端电连接。
另一方面，提供了一种阵列基板，包括：
衬底；
沿垂直且远离所述衬底的方向依次层叠设置的第一绝缘层和第二绝缘层；
位于所述第一绝缘层靠近所述衬底一侧的第一电极；
位于所述第一绝缘层与所述第二绝缘层之间的第二电极；
以及，位于所述第二绝缘层背离所述衬底一侧的搭接电极；
其中，所述阵列基板具有多个第一过孔和多个第二过孔，所述搭接电极通过所述多个第一过孔与所述第一电极电连接，所述搭接电极通过所述多个第二过孔与所述第二电极电连接；
所述第一电极在所述衬底上的正投影与所述第二电极在所述衬底上的正投影不重合。
可选的，所述第一电极包括：多个第一连接臂，以及用于连接所述多个第一连接臂的第一电极本体，所述多个第一过孔在所述衬底上的正投影位于所述多个第一连接臂在所述衬底上的正投影内；
所述第二电极包括：多个第二连接臂，以及用于连接所述多个第二连接臂 的第二电极本体，所述多个第二过孔在所述衬底上的正投影位于所述多个第二连接臂在所述衬底上的正投影内；
其中，所述多个第一连接臂与所述多个第二连接臂一一交替分布。
可选的，所述第一电极与所述第二电极均呈条状，所述第一电极的延伸方向与所述第二电极的延伸方向平行，所述第一电极在所述衬底上的正投影与所述第二电极在所述衬底上的正投影之间存在空隙。
另一方面，提供了一种显示装置，所述装置包括：相对设置的阵列基板和彩膜基板，以及位于所述阵列基板和所述彩膜基板之间的液晶层；所述阵列基板为上述的阵列基板。
本申请实施例提供的技术方案带来的有益效果至少包括：
本申请实施例提供的一种阵列基板，包括：衬底、第一绝缘层、第二绝缘层、第一电极、第二电极和搭接电极。当第一电极在衬底上的正投影覆盖：位于至少一个第一过孔与至少一个第二过孔之间的区域时，位于第一过孔与第二过孔之间的区域存在层叠设置的第一电极、第一绝缘层和第二绝缘层，第二过孔周围的区域同时存在层叠设置的第一电极、第一绝缘层、第二电极和第二绝缘层。如此，搭接电极中位于第一过孔与第二过孔之间的部分，和搭接电极中位于第二过孔周围的部分之间的高度差较小，这个高度差即为第二电极的厚度。这样，搭接电极在与第二电极搭接时，搭接电极的爬坡高度较小，有效的降低了搭接电极出现断路的概率，使得第一电极与第二电极之间的电连接效果较好，进而使得阵列基板中的GOA电路与多条栅线之间的电连接效果较好，有效的提高了集成这种阵列基板的显示装置的显示效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是目前常见的一种阵列基板的俯视图；
图2是图1示出的阵列基板中的单个GOA单元的俯视图；
图3是图2示出的GOA单元在在A-A’处的截面图；
图4是本申请实施例提供的一种阵列基板的膜层结构示意图；
图5是本申请实施例提供的一种阵列基板的俯视图；
图6本申请实施例提供的一种阵列基板中的单个GOA单元的俯视图；
图7本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图；
图8本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图；
图9本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图；
图10是图9示出的GOA单元中搭接电极600的搭接电阻值的示意图；
图11本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图；
图12本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图；
图13本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图；
图14本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图；
图15是本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图；
图16是图15示出的阵列基板在B-B’位置处的截面图；
图17是图15示出的GOA单元中搭接电极600的搭接电阻值的等效电路示意图；
图18是本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
请参考图1，图1是目前常见的一种阵列基板的俯视图。阵列基板00可以具有：显示区0a，以及位于显示区0a外围的非显示区0b。显示区0a内设置有多条平行排布的栅线01，非显示区0b内设置有GOA电路02。
其中，GOA电路02可以与多条栅线01电连接。例如，GOA电路02可以具有与多条栅线01对应的多个GOA单元021，GOA单元021可以与对应的栅线01电连接。
为了更清楚的看出GOA单元021的结构。请参考图2和图3，图2是图1示出的阵列基板中的单个GOA单元的俯视图，图3是图2示出的GOA单元在 在A-A’处的截面图。GOA单元021可以包括：第一电极03、第二电极04和搭接电极05。其中，GOA单元021中的第一电极03可以与显示区0a内的栅线01电连接，GOA单元021中的第二电极04可以与GOA电路021中的信号输出端电连接。这里，第一电极03与第二电极04可以通过搭接电极05搭接，这样，GOA电路021中的信号输出端可以依次通过第二电极04、搭接电极05和第一电极03传输给栅线01，使得栅线01能够接收到信号输出端输出的栅极驱动信号。
例如，GOA单元021可以设置的阵列基板00中的衬底06上，阵列基板00还可以包括：第一绝缘层07和第二绝缘层08。第一电极01可以位于衬底06上，且第一绝缘层07可以位于第一电极03背离衬底06的一侧，第二电极04位于第一绝缘层07背离衬底06的一侧，第二绝缘层08位于背离衬底06的一侧，搭接电极05位于第二绝缘层08背离衬底06的一侧。阵列基板00具有贯穿第一绝缘层07和第二绝缘层08的第一过孔V01，以及贯穿第二绝缘层08的第二过孔V02。这里，第一过孔V01在衬底06上的正投影位于第一电极03在衬底上的正投影内，使得搭接电极05可以通过第一过孔V01与第一电极03搭接；第二过孔V02在衬底06上的正投影位于第二电极04在衬底06上的正投影内，使得搭接电极05还可以通过第二过孔V02与第二电极04搭接。这样，可以保证第一电极03与第二电极04之间可以通过搭接电极05电连接。
然而，阵列基板00通常还包括：第三电极09。该第三电极09与第一电极03同层设置且材料相同，且第二电极04在衬底06上的正投影位于第三电极09在衬底06上的正投影内，该第三电极09与第一电极03在衬底06之间存在空隙d0。这样，第一电极04与第三电极09之间的空隙d0所在区域内仅存在第一绝缘层07和第二绝缘层08，而第二过孔V02周围的区域同时存在层叠设置的第三电极09、第一绝缘层07、第二电极06和第二绝缘层08。
如此，搭接电极05中位于空隙d0所在区域内的部分，与搭接电极05中位于第二过孔V02周围的部分之间的高度差H较大，这个高度差H即为第三电极09的厚度与第二电极04的厚度之和，导致搭接电极05需要进行较陡的爬坡后才能够与第二电极05搭接。而当搭接电极05的爬坡高度较大时，搭接电极05极易出现断路的问题，导致第一电极03与第二电极04之间的电连接效果较差，进而导致GOA电路02与多条栅线01之间电连接效果较差，这样会严重影响集 成了这种阵列基板00的显示装置的显示效果。
请参考图4，图4是本申请实施例提供的一种阵列基板的膜层结构示意图。阵列基板000包括：衬底100、第一绝缘层200、第二绝缘层300、第一电极400、第二电极500和搭接电极600。
阵列基板000中的第一绝缘层200和第二绝缘层300沿垂直且远离衬底100的方向依次层叠设置。
阵列基板000中的第一电极400位于第一绝缘层200靠近衬底100一侧，第二电极500位于第一绝缘层200与第二绝缘层300之间，搭接电极600位于第二绝缘层300背离衬底100的一侧。
其中，阵列基板000可以具有多个第一过孔V1和多个第二过孔V2。搭接电极600可以通过多个第一过孔V1与第一电极400搭接，搭接电极600还可以通过多个第二过孔V2与第二电极500搭接。这样，第二电极500可以通过搭接电极600与第一电极400搭接。
示例的，阵列基板000中的第一过孔V1为同时贯穿第二绝缘层300和第一绝缘层200的过孔，阵列基板000中的第二过孔V2为仅贯穿第二绝缘层300的过孔。多个第一过孔V1在衬底100上的正投影位于第一电极400在衬底100上的正投影内，且第一电极400在衬底100上的正投影位于搭接电极600在衬底100上的正投影内，这样，可以保证搭接电极600可以通过多个第一过孔V1与第一电极400搭接。同样的，多个第二过孔V2在衬底100上的正投影位于第二电极500在衬底100上的正投影内，且第二电极500在衬底100上的正投影位于搭接电极600在衬底100上的正投影内，这样，可以保证搭接电极600可以通过多个第二过孔V2与第二电极500搭接。
在本申请中，第一电极400在衬底100上的正投影与第二电极500在衬底100上的正投影存在交叠区域，且第一电极400在衬底100上的正投影覆盖：位于至少一个第一过孔V1与至少一个第二过孔V2之间的区域。
在本申请实施例中，当第一电极400在衬底100上的正投影覆盖：位于至少一个第一过孔V1与至少一个第二过孔V2之间的区域时，位于第一过孔V1与第二过孔V2之间的区域存在层叠设置的第一电极400、第一绝缘层200和第二绝缘层300，第二过孔V2周围的区域同时存在层叠设置的第一电极400、第 一绝缘层200、第二电极500和第二绝缘层300。如此，搭接电极600中位于第一过孔V1与第二过孔V2之间的部分，和搭接电极600中位于第二过孔V2周围的部分之间的高度差h1较小，这个高度差h1即为第二电极500的厚度。这样，搭接电极600在与第二电极500搭接时，搭接电极600的爬坡高度较小，有效的降低了搭接电极600出现断路的概率，使得第一电极400与第二电极500之间的电连接效果较好。
在一种使用场景中，如图5所示，图5是本申请实施例提供的一种阵列基板的俯视图。阵列基板000具有显示区00a，以及位于显示区00a外围的非显示区00b。阵列基板000还可以包括：位于显示区00a内的多条栅线700，以及位于非显示区00b内的GOA电路800。GOA电路800可以具有与多条栅线700对应的多个GOA单元801，以及与多个GOA单元801一一对应的多个信号输出端(图中未画出)。
其中，GOA单元801可以包括：第一电极400和第二电极500。GOA单元801中的第一电极400可以与对应的栅线700电连接，GOA单元801中的第二电极500可以与对应信号输出端电连接。这里，GOA单元801通常还包括搭接电极600，信号输出端可以依次通过搭接电极600、第二电极500和第一电极400将栅极驱动信号发送给栅线700。在本申请中，当第一电极400与第二电极500之间的电连接效果较好时，可以保证GOA单元801与栅线700之间电连接效果较好，使得GOA电路800与多条栅线700之间的电连接效果较好。
综上所述，本申请实施例提供的一种阵列基板，包括：衬底、第一绝缘层、第二绝缘层、第一电极、第二电极和搭接电极。当第一电极在衬底上的正投影覆盖：位于至少一个第一过孔与至少一个第二过孔之间的区域时，位于第一过孔与第二过孔之间的区域存在层叠设置的第一电极、第一绝缘层和第二绝缘层，第二过孔周围的区域同时存在层叠设置的第一电极、第一绝缘层、第二电极和第二绝缘层。如此，搭接电极中位于第一过孔与第二过孔之间的部分，和搭接电极中位于第二过孔周围的部分之间的高度差较小，这个高度差即为第二电极的厚度。这样，搭接电极在与第二电极搭接时，搭接电极的爬坡高度较小，有效的降低了搭接电极出现断路的概率，使得第一电极与第二电极之间的电连接效果较好，进而使得阵列基板中的GOA电路与多条栅线之间的电连接效果较好，有效的提高了集成这种阵列基板的显示装置的显示效果。
在本申请实施例中，阵列基板000中的GOA电路800中的GOA单元801的结构有多种，本申请实施例以以下四种可选的实现方式为例进行示意性的说明书：
第一种可选的实现方式，请参考图6，图6本申请实施例提供的一种阵列基板中的单个GOA单元的俯视图。阵列基板000中的多个第一过孔V1排布为至少一行，阵列基板000中的多个第二过孔V2排布为至少一行。至少一行第一过孔V1与至少一行第二过孔V2排布为多列，第一电极400在衬底上的正投影覆盖：位于相邻的一行第一过孔V1与一行第二过孔V2之间的至少部分区域。需要说明的是，图6在位置A-A’处的截面的膜层示意图可以参考图4。
示例的，多个第一过孔V1排布为一行，多个第二过孔V2也排布为一行。当第一电极400在衬底100上的正投影覆盖：位于相邻的一行第一过孔V1与一行第二过孔V2之间的至少部分区域时，一行第一过孔V1与一行第二过孔V2之间的至少部分区域同时存在层叠设置的第一电极400、第一绝缘层200和第二绝缘层300，第二过孔V2周围的区域同时存在层叠设置的第一电极400、第一绝缘层200、第二电极500和第二绝缘层300。如此，能够确保搭接电极600中位于第一过孔V1与第二过孔V2之间的至少部分，和搭接电极600中位于第二过孔V2周围的部分之间的高度差h1较小，有效的降低了搭接电极600出现断路的概率。
可选的，第一电极400与第二电极500均为条状电极，第一电极400的宽度大于第二电极500宽度，第二电极500在衬底100上的正投影位于第一电极400在衬底100上的正投影内。
在本申请中，当第二电极500在衬底100上的正投影位于第一电极400在衬底100上的正投影内时，能够确保第一电极400在衬底100上的正投影覆盖：位于相邻的一行第一过孔V1与一行第二过孔V2之间的全部区域d1。如此，能够确保搭接电极600中位于第一过孔V1与第二过孔V2之间的部分，和搭接电极600中位于第二过孔V2周围的部分之间的高度差h1均较小，从而进一步降低了搭接电极600出现断路的概率。
可选的，请参考图7，图7本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图。当第一电极400在衬底100上的正投影覆盖：位于相邻的一行第一电极400与一行第二电极500之间的部分区域时，第一电极400可以 具有至少一个镂空孔M，至少一个镂空孔M在衬底100上的正投影位于至少一行第一过孔V1在衬底100上的正投影与至少一行第二过孔V2在衬底100上的正投影之间，且至少一个镂空孔M的在衬底100上的正投影的面积，小于一行第一过孔V1在衬底100上的正投影的总面积，且小于一行第二过孔V2在衬底100上的正投影的总面积。示例性的，第一电极400具有一个镂空孔M。
在这种情况下，一个镂空孔M的在衬底100上的正投影的面积既小于一行第一过孔V1在衬底100上的正投影的总面积，又小于一行第二过孔V2在衬底100上的正投影的总面积，可以确保第一电极400在衬底100上的正投影，能够覆盖位于相邻的一行第一电极400与一行第二电极500之间的部分区域，进而可以降低搭接电极600出现断路的概率。并且，第一电极400一般采用金属导体材料制成，当在第一电极400内设置至少一个镂空孔M时，可以减小第一电极400在衬底100上的正投影的面积，进而能够降低在阵列基板000的制造过程中，因电荷在第一电极400位置处聚集而发生静电击穿的不良现象的概率，从而提高了集成了该阵列基板的显示装置的显示效果。
第二种可选的实现方式，请参见图8，图8本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图。第一电极400包括：平行排布的第一电极条401和第二电极条402，以及位于第一电极条401与第二电极条402之间的至少一个第一连接臂403。示例性的，第一电极400中的第一连接臂403的个数可以为多个，每个第一连接臂403的一端可以与第一电极条401连接，每个第一连接臂403的另一端可以与第二电极条402连接，且每个第一连接臂403的延伸方向垂直于第一电极条401的延伸方向。
阵列基板000中的多个第一过孔V1在衬底100上的正投影均位于第一电极条401在衬底100上的正投影内，阵列基板000中的多个第二过孔V2中的至少部分第二过孔V2在衬底100上的正投影位于第二电极条402在衬底上的正投影内，且位于第二电极500在衬底100上的正投影内。需要说明的是，图8在位置A-A’处的截面的膜层示意图可以参考图4。
在这种情况下，通过在第一电极条401与第二电极条402之间设置第一连接臂403，可以保证多个第一过孔V1与多个第二过孔V2之间同时存在叠设置的第一连接臂403、第一绝缘层200和第二绝缘层300，第二过孔V2周围的区域同时存在层叠设置的第一电极400、第一绝缘层200、第二电极500和第二绝 缘层300。如此，能够确保搭接电极600中位于第一连接臂403上的至少部分，和搭接电极600中位于第二过孔V2周围的部分之间的高度差h1较小，有效的降低了搭接电极600出现断路的概率。
可选的，如图8所示，第一连接臂403在衬底100上的正投影覆盖：第一目标过孔P1与第二目标过孔P2之间的全部区域。这里，第一目标过孔P1位于多个第一过孔V1中的任一第一过孔V1，第二目标过孔P2为多个第二过孔V2中正投影与第二电极条402交叠，且与第一目标过孔P1相邻的第二过孔V2。
在这种情况下，可以确保搭接电极600中位于第一连接臂403上的部分，能够直接与搭接电极600中位于第二过孔V2周围的部分电连接，可以进一步的提高第一电极300与第二电极400电连接的效果。
可选的，请参见图9，图9本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图。多个第二过孔V2包括：至少一个第一搭接过孔V21和多个第二搭接过孔V22，第二电极500包括：第二电极本体501，以及与至少一个第一搭接过孔V21一一对应的至少一个第二连接臂501，第二连接臂501与第二电极本体501电连接。第一连接臂403的延伸方向与第二连接臂502的延伸方向平行。
至少一个第一搭接过孔V21在衬底100上的正投影均位于第一电极条401在衬底100上的正投影内，且位于对应的第二连接臂502在衬底上的正投影内。多个第二搭接过孔V22在衬底100上的正投影均位于第二电极条500在衬底上的正投影内，且均位于第二电极本体501在衬底100上的正投影内。需要说明的是，图9在位置A-A’处的截面的膜层示意图可以参考图4。
在这种情况下，位于第一过孔V1与第一搭接过孔V21之间的区域存在层叠设置的第一电极400、第一绝缘层200和第二绝缘层300，第一搭接过孔V21周围的区域同时存在层叠设置的第一电极400、第一绝缘层200、第二电极500和第二绝缘层300。如此，搭接电极600中位于第一过孔V1与第一搭接过孔V21之间的部分，和搭接电极600中位于第一搭接过孔V21周围的部分之间的高度差h1较小，这个高度差h1即为第二电极500的厚度。这样，搭接电极600在与第二电极500搭接时，搭接电极600的爬坡高度也较小。
需要说明的是，请参考图10，图10是图9示出的GOA单元中搭接电极600的搭接电阻值的示意图。其中，搭接电极600中第一过孔V1与第一搭接过孔 V21的搭接电阻值，包括：位于第一过孔V1中的搭接电极600的电阻值R1、位于第一搭接过孔V21中的搭接电极600的电阻值R2、以及位于第一搭接过孔V21与第一过孔V1之间的电阻值R3。对于不同的GOA单元，第一过孔V1和第一搭接过孔V21的形状和尺寸一致。这样，在不同的GOA单元中，位于第一过孔V1中的搭接电极600的电阻值R1相同；位于第一搭接过孔V21中的搭接电极600的电阻值R2也相同。
在不同的GOA单元中，第一搭接过孔V21与第一过孔V1之间的距离不同，位于第一搭接过孔V21与第一过孔V1之间的电阻值R3也不同。其中，第一搭接过孔V21与第一过孔V1之间的电阻值R3，包括：平面电阻Ra，以及斜坡电阻Rb，也即R3＝Ra+Rb。平面电阻Ra的电阻值与第一搭接过孔V21与第一过孔V1之间的距离X成正比，也即，Ra＝R0*X/W。斜坡电阻Rb的电阻值与爬坡高度h1成正比，也即，Rb＝R0*h1/W。其中，R0为搭接电极600的单位电阻，W为搭接电极600沿第一电极条401的延伸方向上的宽度。单位电阻R0只与搭接电极600的厚度和材质相关。
在这种情况下，当搭接电极600通过第一搭接过孔V21与第一过孔V1进行搭接时，第一搭接过孔V21与第一过孔V1之间的距离X较小；并且，由于搭接电极600的爬坡高度h1也较小。因此，第一搭接过孔V21与第一过孔V1之间的电阻值R3也较小；进而降低了该搭接电极600通过第一搭接过孔V21与第一过孔V1进行搭接的搭接电阻值，降低了对搭接电极600内传输的信号的干扰，提高了搭接电极600的搭接效率。
可选的，如图9所示，多个第一过孔V1排布为至少一行，一个第一搭接过孔V21位于一行第一过孔V1中相邻的两个第一过孔V1之间；多个第二搭接过孔V21阵列排布为至少一行。
在这种情况下，当第一搭接过孔V21位于一行第一过孔V1中相邻的两个第一过孔V1之间时，可以提高通过第一过孔V1与第一搭接过孔V21，连接第一电极400和第二电极500的均一性，确保第一电极400和第二电极500之间的有效电连接。
需要说明的是，继续参见图9，当第一连接臂403的个数与第二连接臂502的个数均为多个时，多个第一连接臂403与多个第二连接臂502一一交替分布，且相邻的第一连接臂403与第二连接臂502之间存在空隙。
在这种情况下，不仅搭接电极600中位于第一过孔V1与第一搭接过孔V21之间的部分，和搭接电极600中位于第一搭接过孔V21周围的部分之间的高度差h1较小；而且搭接电极600中位于第一连接臂403所在的区域，和搭接电极600中位于第二过孔V2周围的部分之间的高度差h1也较小。这样，搭接电极600在与第二电极500搭接时，增加了搭接电极600中爬坡高度较小的区域的面积，从而进一步降低了搭接电极600出现断路的概率。
可选的，第一连接臂403在衬底100上的正投影的边界与第二连接臂502在衬底101上的正投影的边界重合。这样，搭接电极600中爬坡高度较小的区域的面积最大，搭接电极600出现断路的概率最小。
第三种可选的实现方式，请参见图11，图11本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图。多个第一过孔V1排布为多行和多列，多个第二过孔V2排布为多行和多列，多行第一过孔V1与多行第二过孔V2一一对应，一行第一过孔V1与对应的一行第二过孔V2排布为一行，第一电极400在衬底上的正投影覆盖：位于相邻的一列第一电极400与一列第二电极500之间的至少部分区域。
在这种情况下，当多行第一过孔V1与多行第二过孔V2一一对应时，对于每一行中相邻的第一过孔V1和第二过孔V2，位于该第一过孔V1与第二过孔V2之间的区域存在层叠设置的第一电极400、第一绝缘层200和第二绝缘层300，而第二过孔V2周围的区域同时存在层叠设置的第一电极400、第一绝缘层200、第二电极500和第二绝缘层300。如此，可以确保在每一行第一过孔V1与第二过孔V2中，搭接电极600中位于第一过孔V1与第二过孔V2之间的部分，和搭接电极600中位于第二过孔V2周围的部分之间的高度差h1较小。
可选的，请参见图12，图12本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图。第一电极400具有至少一个第一条形孔L1，第一条形孔L1在衬底100上的正投影位于两行相邻的第一过孔V1在衬底100上的正投影之间，且位于两行相邻的第二过孔V2在衬底上的正投影之间。
在这种情况下，在确保在每一行第一过孔V1与第二过孔V2中，搭接电极600中位于第一过孔V1与第二过孔V2之间的部分，和搭接电极600中位于第二过孔V2周围的部分之间的高度差h1较小的前提下，减小了第一电极400在衬底100上的正投影的面积，进而能够降低在阵列基板000的制造过程中，因 电荷在第一电极400位置处聚集而发生静电击穿的不良现象的概率。
可选的，如图12所示，第二电极500在衬底上的正投影位于第一电极400在衬底上的正投影内，第二电极500具有至少一个第二条形孔L2，至少一个第二条形孔L2与至少一个第一条形孔L1一一对应，第二条形孔L2在衬底100上的正投影的部分边界与对应的第一条形孔L1在衬底100上的正投影的部分边界重合。
在这种情况下，当第一电极400具有第一条形孔L1，第二电极500具有第二条形孔L2时，能够进一步减小第一电极400在衬底100上的正投影的面积，进一步降低了在阵列基板000的制造过程中，因电荷在第一电极400位置处聚集而发生静电击穿的不良现象的概率。
第四种可选的实现方式，请参见图13，图13本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图。多个第一过孔V1排布为至少两行，多个第二过孔V2包括：至少一行第一搭接过孔V21，一行第一搭接过孔V21分布在两行相邻的第一过孔V1之间，第一电极400在衬底100上的正投影覆盖：位于一行第一搭接过孔V21与相邻的两行第一过孔V1之间的全部区域。需要说明的是，图13在位置A-A’处的截面的膜层示意图可以参考图4。
在这种情况下，一行第一搭接过孔V21可以与两行相邻的第一过孔V1，通过搭接电极600搭接，从而了增加了与第一搭接过孔V21搭接的第一过孔V1的数量。而搭接电极600中位于第一过孔V1与第一搭接过孔V21之间的部分，和搭接电极600中位于第一搭接过孔V21周围的部分之间的高度差h1较小，因此，增加了搭接电极600中爬坡高度较小的区域的面积，从而进一步降低了搭接电极600出现断路的概率。
可选的，请参见图14，图14本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图。多个第二过孔V2还包括：多个第二搭接过孔V22，一个第二搭接过孔V22位于一行第一过孔V1中的两个相邻的第一过孔V1之间。
第二电极500包括：条状的第二电极本体501，以及与多个第二搭接过孔V22一一对应的多个电极块503，第二电极本体501与电极块503电连接，第二电极本体501在衬底100上的正投影位于至少一行第一搭接过孔V21在衬底100上的正投影内，电极块503在衬底100上的正投影位于对应的第二搭接过孔V22在衬底100上的正投影内。
在这种情况下，第二过孔V2不仅包括位于条状的第二电极本体501上的多个第一搭接过孔V21，还包括与多个电极块503一一对应的多个第二搭接过孔V22，如此，增加了第二过孔V2的数量，从而进一步增加了搭接电极600中爬坡高度较小的区域的面积。
示例性的，继续参见图14，多个第二搭接过孔V22中的一部分第二搭接过孔V22与相邻的两行第一过孔V1中的一行第一过孔V1排布为一行，另一部分第二搭接过孔V22相邻的两行第一过孔V1中的另一行第一过孔V1排布为一行。如此，提高了第一电极400与第二电极500电连接的有效性。
可选的，继续参见图14，第一电极400还具有多个镂空结构U。由于第一电极400一般采用金属导体材料制成。因此，当在第一电极400内设置多个镂空结构U时，可以减小第一电极400在衬底100上的正投影的面积，进而能够降低在阵列基板000的制造过程中，因电荷在第一电极400位置处聚集而发生静电击穿的不良现象的概率，从而提高了集成了该阵列基板的显示装置的显示效果。
综上所述，本申请实施例提供的一种阵列基板，包括：衬底、第一绝缘层、第二绝缘层、第一电极、第二电极和搭接电极。当第一电极在衬底上的正投影覆盖：位于至少一个第一过孔与至少一个第二过孔之间的区域时，位于第一过孔与第二过孔之间的区域存在层叠设置的第一电极、第一绝缘层和第二绝缘层，第二过孔周围的区域同时存在层叠设置的第一电极、第一绝缘层、第二电极和第二绝缘层。如此，搭接电极中位于第一过孔与第二过孔之间的部分，和搭接电极中位于第二过孔周围的部分之间的高度差较小，这个高度差即为第二电极的厚度。这样，搭接电极在与第二电极搭接时，搭接电极的爬坡高度较小，有效的降低了搭接电极出现断路的概率，使得第一电极与第二电极之间的电连接效果较好，进而使得阵列基板中的GOA电路与多条栅线之间的电连接效果较好，有效的提高了集成这种阵列基板的显示装置的显示效果。
请参考图15，图15是本申请实施例提供的另一种阵列基板中的单个GOA单元的俯视图。图16是图15示出的阵列基板在B-B’位置处的截面图。阵列基板000可以包括：衬底100、第一绝缘层200、第二绝缘层300、第一电极400、第二电极500和搭接电极600。
阵列基板000中的第一绝缘层200和第二绝缘层300沿垂直且远离衬底100的方向依次层叠设置。阵列基板000中的第一电极400位于第一绝缘层200靠近衬底100一侧，第二电极500位于第一绝缘层200与第二绝缘层300之间，搭接电极600位于第二绝缘层300背离衬底100的一侧。
其中，阵列基板000可以具有多个第一过孔V1和多个第二过孔V2。搭接电极600可以通过多个第一过孔V1与第一电极400搭接，搭接电极600还可以通过多个第二过孔V2与第二电极500搭接。这样，第二电极500可以通过搭接电极600与第一电极400搭接。
在本申请中，第一电极400在衬底100上的正投影与第二电极500在衬底100上的正投影不重合。
在一种使用场景中，这里的第一电极400与第二电极500均属于GOA电路800中的GOA单元801，且这个GOA单元801中的第一电极400与阵列基板000中的栅线电连接，这个GOA单元801中的第二电极400与GOA电路800中的信号输出端电连接。
在本申请实施例中，当第一电极400在衬底100上的正投影与第二电极500在衬底100上的正投影不重合时，位于第一过孔V1与第二过孔V2之间的区域存在层叠设置的第一绝缘层200和第二绝缘层300，第二过孔V2周围的区域同时存在层叠设置的第一绝缘层200、第二电极500和第二绝缘层300。如此，搭接电极600中位于第一过孔V1与第二过孔V2之间的部分，和搭接电极600中位于第二过孔V2周围的部分之间的高度差h1也较小，这个高度差h1即为第二电极500的厚度。这样，搭接电极600在与第二电极500搭接时，搭接电极600的爬坡高度较小，有效的降低了搭接电极600出现断路的概率，使得第一电极400与第二电极500之间的电连接效果较好。并且，第一过孔V1周围的区域同时存在层叠设置的第一绝缘层200和第一电极400。如此，搭接电极600中位于第一过孔V1周围的部分，和搭接电极600中位于第二过孔V2周围的部分之间的高度差h2也较小，因此提高了该阵列基板000的平坦性。这样，在组装集成了该阵列基板000的显示装置时，可以提高显示装置中阵列基板000与彩膜基板之间贴合的紧密度，降低水气进入显示装置的概率。
在一种可能的情况中，如图15所示，第一电极400包括：多个第一连接臂403，以及用于连接多个第一连接臂403的第一电极本体401，多个第一过孔V1 在衬底100上的正投影位于多个第一连接臂403在衬底上的正投影内。
第二电极500包括：多个第二连接臂502，以及用于连接多个第二连接臂502的第二电极本体501，多个第二过孔V2在衬底100上的正投影位于多个第二连接臂502在衬底100上的正投影内。其中，多个第一连接臂403与多个第二连接臂502一一交替分布。
在这种情况下，搭接电极600可以通过第一连接臂403上的第一过孔V1和第二连接臂502上的第二过孔V2，实现将第一电极400与第二电极500搭接在一起，而多个第一连接臂403与多个第二连接臂502一一交替分布，提高了在各个区域进行搭接的均一性，进而提高了第一电极400与第二电极500电连接的有效性。
需要说明的是，请参考图17，图17是图15示出的GOA单元中搭接电极600的搭接电阻值的等效电路示意图。其中，搭接电极600中第一过孔V1与第二过孔V2的搭接电阻值的计算方法和上述搭接电极600中第一过孔V1与第一搭接过孔V21的搭接电阻值的计算方法相同，在此不再进行赘述。
如图16所示，当第一过孔V1与第二过孔V2的数量为多个时，位于第一过孔V1中的搭接电极600的电阻值R1并联，位于第一搭接过孔V21中的搭接电极600的电阻值R2并联。这样，第一过孔V1与第二过孔V2的数量越多，R1并联后的总电阻越小，R2并联后的总电阻也越小。
示例性的，第一过孔V1的数量为8个，第二过孔V2的数量为8个，搭接电极600的搭接电阻值包括：8个R1并联后的总电阻，8个R2并联后的总电阻，以及第一过孔V1与第二过孔V2之间的电阻值R3。
也即，搭接电极600的搭接电阻值为：
Figure PCTCN2022105801-appb-000001
在这种情况下，当多个第一连接臂403与多个第二连接臂502一一交替分布时，可以增加第一过孔V1与第二过孔V2的数量，降低搭接电极600的搭接电阻值。并且，搭接电极600中位于第一过孔V1与第二过孔V2之间的部分，和搭接电极600中位于第二过孔V2周围的部分之间的高度差h1也较小，这样，第一过孔V1与第二过孔V2之间的电阻值也较小，从而进一步降低了搭接电极600的搭接电阻值。
在另一种可能的情况中，如图18所示，图18是本申请实施例提供的另一 种阵列基板中的单个GOA单元的俯视图。第一电极400与第二电极500均呈条状，第一电极400的延伸方向与第二电极500的延伸方向平行，第一电极400在衬底上的正投影与第二电极500在衬底上的正投影之间存在空隙。
在这种情况下，第一电极400在衬底上的正投影与第二电极500在衬底上的正投影之间存在空隙，从而能够在提高阵列基板000的平坦性的同时，降低了第一电极400和第二电极500在衬底100上的正投影的面积，进而能够降低在阵列基板000的制造过程中，因电荷在第一电极400和第二电极500位置处聚集而发生静电击穿的不良现象的概率。
综上所述，本申请实施例提供的一种阵列基板，包括：衬底、第一绝缘层、第二绝缘层、第一电极、第二电极和搭接电极。当第一电极在衬底上的正投影与第二电极在衬底上的正投影不重合时，位于第一过孔与第二过孔之间的区域存在层叠设置的第一绝缘层和第二绝缘层，第二过孔周围的区域同时存在层叠设置的第一绝缘层、第二电极和第二绝缘层。如此，搭接电极中位于第一过孔与第二过孔之间的部分，和搭接电极中位于第二过孔周围的部分之间的高度差也较小，这个高度差即为第二电极的厚度。这样，搭接电极在与第二电极搭接时，搭接电极的爬坡高度较小，有效的降低了搭接电极出现断路的概率，使得第一电极与第二电极之间的电连接效果较好。并且，第一过孔周围的区域同时存在层叠设置的第一绝缘层和第一电极。如此，搭接电极中位于第一过孔周围的部分，和搭接电极中位于第二过孔周围的部分之间的高度差也较小，因此提高了该阵列基板的平坦性。这样，在组装集成了该阵列基板的显示装置时，可以提高显示装置中阵列基板与彩膜基板之间贴合的紧密度，降低水气进入显示装置的概率。
本申请实施例还提供的一种显示装置，该显示装置包括：相对设置的阵列基板000和彩膜基板，以及位于阵列基板000和彩膜基板之间的液晶层；阵列基板000为上述的阵列基板000。该显示装置可以为：显示器、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其 他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本申请中，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
以上所述仅为本申请的可选的实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (21)

  1. 一种阵列基板，其特征在于，包括：
    衬底；
    沿垂直且远离所述衬底的方向依次层叠设置的第一绝缘层和第二绝缘层；
    位于所述第一绝缘层靠近所述衬底一侧的第一电极；
    位于所述第一绝缘层与所述第二绝缘层之间的第二电极；
    以及，位于所述第二绝缘层背离所述衬底一侧的搭接电极；
    其中，所述阵列基板具有多个第一过孔和多个第二过孔，所述搭接电极通过所述多个第一过孔与所述第一电极电连接，所述搭接电极通过所述多个第二过孔与所述第二电极电连接；
    所述第一电极在所述衬底上的正投影与所述第二电极在所述衬底上的正投影存在交叠区域，所述第一电极在所述衬底上的正投影覆盖：位于至少一个所述第一过孔与至少一个第二过孔之间的区域。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述多个第一过孔排布为至少一行，所述多个第二过孔排布为至少一行，至少一行第一过孔与至少一行第二过孔排布为多列，所述第一电极在所述衬底上的正投影覆盖：位于相邻的一行第一过孔与一行第二过孔之间的至少部分区域。
  3. 根据权利要求2所述的阵列基板，其特征在于，所述第一电极与所述第二电极均为条状电极，所述第一电极的宽度大于所述第二电极宽度，所述第二电极在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影内。
  4. 根据权利要求2所述的阵列基板，其特征在于，所述第一电极具有至少一个镂空孔，所述至少一个镂空孔在所述衬底上的正投影位于所述至少一行第一过孔在所述衬底上的正投影与所述至少一行第二过孔在所述衬底上的正投影之间，且所述至少一个镂空孔的在所述衬底上的正投影的面积，小于一行所述第一过孔在所述衬底上的正投影的总面积，且小于一行所述第二过孔在所述衬底上的正投影的总面积。
  5. 根据权利要求1所述的阵列基板，其特征在于，所述第一电极包括：平行排布的第一电极条和第二电极条，以及位于所述第一电极条与所述第二电极条之间的至少一个第一连接臂；
    所述多个第一过孔在所述衬底上的正投影均位于所述第一电极条在所述衬底上的正投影内，所述多个第二过孔中的至少部分第二过孔在所述衬底上的正投影位于所述第二电极条在所述衬底上的正投影内，且位于所述第二电极在所述衬底上的正投影内。
  6. 根据权利要求5所述的阵列基板，其特征在于，所述第一连接臂在所述衬底上的正投影覆盖：第一目标过孔与第二目标过孔之间的全部区域，所述第一目标过孔位于所述多个第一过孔中的任一第一过孔，所述第二目标过孔为所述多个第二过孔中正投影与所述第二电极条交叠，且与所述第一目标过孔相邻的第二过孔。
  7. 根据权利要求5所述的阵列基板，其特征在于，所述多个第二过孔包括：至少一个第一搭接过孔和多个第二搭接过孔，所述第二电极包括：第二电极本体，以及与所述至少一个第一搭接过孔一一对应的至少一个第二连接臂，所述第二连接臂与所述第二电极本体电连接；
    所述至少一个第一搭接过孔在所述衬底上的正投影均位于所述第一电极条在所述衬底上的正投影内，且位于对应的第二连接臂在所述衬底上的正投影内；
    所述多个第二搭接过孔在所述衬底上的正投影均位于所述第二电极条在所述衬底上的正投影内，且均位于所述第二电极本体在所述衬底上的正投影内。
  8. 根据权利要求7所述的阵列基板，其特征在于，所述多个第一过孔排布为至少一行，一个所述第一搭接过孔位于一行所述第一过孔中相邻的两个第一过孔之间；所述多个第二搭接过孔阵列排布为至少一行。
  9. 根据权利要求7所述的阵列基板，其特征在于，当所述第一连接臂的个数与所述第二连接臂的个数均为多个时，多个所述第一连接臂与多个所述第二连 接臂一一交替分布，且相邻的所述第一连接臂与所述第二连接臂之间存在空隙。
  10. 根据权利要求7所述的阵列基板，其特征在于，所述第一连接臂在所述衬底上的正投影的边界与所述第二连接臂在所述衬底上的正投影的边界重合。
  11. 根据权利要求1所述的阵列基板，其特征在于，所述多个第一过孔排布为多行和多列，所述多个第二过孔排布为多行和多列，多行所述第一过孔与多行所述第二过孔一一对应，一行第一过孔与对应的一行第二过孔排布为一行，所述第一电极在所述衬底上的正投影覆盖：位于相邻的一列第一电极与一列第二电极之间的至少部分区域。
  12. 根据权利要求11所述的阵列基板，其特征在于，所述第一电极具有至少一个第一条形孔，所述第一条形孔在所述衬底上的正投影位于两行相邻的所述第一过孔在所述衬底上的正投影之间，且位于两行相邻的所述第二过孔在所述衬底上的正投影之间。
  13. 根据权利要求12所述的阵列基板，其特征在于，所述第二电极在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影内，所述第二电极具有至少一个第二条形孔，所述至少一个第二条形孔与所述至少一个第一条形孔一一对应，所述第二条形孔在所述衬底上的正投影的部分边界与对应的第一条形孔在所述衬底上的正投影的部分边界重合。
  14. 根据权利要求1所述的阵列基板，其特征在于，所述多个第一过孔排布为至少两行，所述多个第二过孔包括：至少一行第一搭接过孔，一行所述第一搭接过孔分布在两行相邻的所述第一过孔之间，所述第一电极在所述衬底上的正投影覆盖：位于一行所述第一搭接过孔与相邻的两行所述第一过孔之间的全部区域。
  15. 根据权利要求14所述的阵列基板，其特征在于，所述多个第二过孔还包括：多个第二搭接过孔，一个所述第二搭接过孔位于一行所述第一过孔中的两 个相邻的第一过孔之间；
    所述第二电极包括：条状的第二电极本体，以及与所述多个第二搭接过孔一一对应的多个电极块，所述第二电极本体与所述电极块电连接，所述第二电极本体在所述衬底上的正投影位于所述至少一行第一搭接过孔在所述衬底上的正投影内，所述电极块在所述衬底上的正投影位于对应的第二搭接过孔在所述衬底上的正投影内。
  16. 根据权利要求15所述的阵列基板，其特征在于，所述多个第二搭接过孔中的一部分第二搭接过孔与相邻的两行所述第一过孔中的一行第一过孔排布为一行，另一部分第二搭接过孔相邻的两行所述第一过孔中的另一行第一过孔排布为一行。
  17. 根据权利要求1至16任一所述的阵列基板，其特征在于，所述衬底具有显示区，以及位于所述显示区外围的非显示区；
    所述阵列基板还包括：位于所述显示区内的多条栅线，以及位于所述非显示区内的栅极驱动GOA电路，所述GOA电路具有与所述多条栅线对应的多个GOA单元，以及与所述多个GOA单元一一对应的信号输出端；
    所述GOA单元包括：所述第一电极和所述第二电极，所述GOA单元中的第一电极与对应的栅线电连接，所述GOA单元中的第二电极与对应的信号输出端电连接。
  18. 一种阵列基板，其特征在于，包括：
    衬底；
    沿垂直且远离所述衬底的方向依次层叠设置的第一绝缘层和第二绝缘层；
    位于所述第一绝缘层靠近所述衬底一侧的第一电极；
    位于所述第一绝缘层与所述第二绝缘层之间的第二电极；
    以及，位于所述第二绝缘层背离所述衬底一侧的搭接电极；
    其中，所述阵列基板具有多个第一过孔和多个第二过孔，所述搭接电极通过所述多个第一过孔与所述第一电极电连接，所述搭接电极通过所述多个第二过孔与所述第二电极电连接；
    所述第一电极在所述衬底上的正投影与所述第二电极在所述衬底上的正投影不重合。
  19. 根据权利要求18所述的阵列基板，其特征在于，所述第一电极包括：多个第一连接臂，以及用于连接所述多个第一连接臂的第一电极本体，所述多个第一过孔在所述衬底上的正投影位于所述多个第一连接臂在所述衬底上的正投影内；
    所述第二电极包括：多个第二连接臂，以及用于连接所述多个第二连接臂的第二电极本体，所述多个第二过孔在所述衬底上的正投影位于所述多个第二连接臂在所述衬底上的正投影内；
    其中，所述多个第一连接臂与所述多个第二连接臂一一交替分布。
  20. 根据权利要求18所述的阵列基板，其特征在于，所述第一电极与所述第二电极均呈条状，所述第一电极的延伸方向与所述第二电极的延伸方向平行，所述第一电极在所述衬底上的正投影与所述第二电极在所述衬底上的正投影之间存在空隙。
  21. 一种显示装置，其特征在于，所述显示装置包括：相对设置的阵列基板和彩膜基板，以及位于所述阵列基板和所述彩膜基板之间的液晶层；所述阵列基板为权利要求1至20任一所述的阵列基板。
PCT/CN2022/105801 2022-07-14 2022-07-14 阵列基板及显示装置 WO2024011533A1 (zh)

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CN109270754A (zh) * 2017-07-17 2019-01-25 京东方科技集团股份有限公司 阵列基板和显示装置
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