WO2024009753A1 - Semiconductor device and semiconductor device unit - Google Patents

Semiconductor device and semiconductor device unit Download PDF

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Publication number
WO2024009753A1
WO2024009753A1 PCT/JP2023/022739 JP2023022739W WO2024009753A1 WO 2024009753 A1 WO2024009753 A1 WO 2024009753A1 JP 2023022739 W JP2023022739 W JP 2023022739W WO 2024009753 A1 WO2024009753 A1 WO 2024009753A1
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WIPO (PCT)
Prior art keywords
switching element
semiconductor device
resin
main
control terminals
Prior art date
Application number
PCT/JP2023/022739
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French (fr)
Japanese (ja)
Inventor
大勝 梅上
裕太 大河内
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ローム株式会社
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Publication of WO2024009753A1 publication Critical patent/WO2024009753A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present disclosure relates to a semiconductor device and a semiconductor device unit.
  • Patent Document 1 discloses a conventional semiconductor device.
  • the semiconductor device described in Patent Document 1 includes a plurality of semiconductor elements (10) and a sealing resin (70) that covers these semiconductor elements.
  • Each of the plurality of semiconductor elements (10) is a switching element made of SiC.
  • the plurality of semiconductor elements (10) include a plurality of semiconductor elements 10A (first switching element) and a plurality of semiconductor elements 10B (second switching element).
  • the plurality of semiconductor elements 10A constitute an upper arm circuit
  • the plurality of semiconductor elements 10B constitute a lower arm circuit.
  • the plurality of semiconductor elements 10A are connected in parallel with each other
  • the plurality of semiconductor elements 10B are connected in parallel with each other.
  • the plurality of semiconductor elements 10A and the plurality of semiconductor elements 10B are connected in series. Since it is difficult to increase the area of a semiconductor element using SiC as a constituent material, as in the semiconductor device described in Patent Document 1, a plurality of semiconductor elements 10A are required depending on the current capacity required for the semiconductor device. , 10B are built in parallel.
  • An object of the present disclosure is to provide a semiconductor device that is improved over the conventional semiconductor device. Particularly, in view of the above-mentioned circumstances, one object of the present disclosure is to provide a semiconductor device that improves heat dissipation and is suitable for accommodating various current capacities.
  • a semiconductor device provided by the first aspect of the present disclosure includes only two switching elements and a sealing resin that covers the only two switching elements.
  • One of the only two switching elements is a first switching element and the other is a second switching element.
  • Each of the first switching element and the second switching element includes SiC as a constituent material.
  • the first switching element and the second switching element are connected in series, with the first switching element serving as an upper arm and the second switching element serving as a lower arm.
  • a semiconductor device unit provided by the second aspect of the present disclosure includes a plurality of semiconductor devices according to the first aspect of the present disclosure.
  • the plurality of semiconductor devices are combined with each other.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a perspective view of the semiconductor device according to the first embodiment of the present disclosure, viewed from the back side.
  • FIG. 3 is a plan view showing the semiconductor device according to the first embodiment of the present disclosure, in which the sealing resin is shown with imaginary lines.
  • FIG. 4 is a plan view of FIG. 3 with the third conductive member omitted.
  • FIG. 5 is a front view showing the semiconductor device according to the first embodiment of the present disclosure, in which the sealing resin is shown with imaginary lines.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • FIG. 7 is a diagram showing a circuit configuration of a semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a perspective view of the semiconductor device according to the first embodiment of the present disclosure, viewed from the
  • FIG. 8 is a perspective view showing a semiconductor device unit including a plurality of semiconductor devices according to the first embodiment of the present disclosure.
  • FIG. 9 is a perspective view showing a semiconductor device according to a first modification of the first embodiment.
  • FIG. 10 is a front view showing the semiconductor device according to the first modification of the first embodiment, and shows the sealing resin with imaginary lines.
  • FIG. 11 is a perspective view showing a semiconductor device according to a second modification of the first embodiment.
  • FIG. 12 is a front view showing a semiconductor device according to a second modification of the first embodiment, and shows the sealing resin with imaginary lines.
  • FIG. 13 is a perspective view showing a semiconductor device according to a third modification of the first embodiment.
  • FIG. 9 is a perspective view showing a semiconductor device unit including a plurality of semiconductor devices according to the first embodiment of the present disclosure.
  • FIG. 9 is a perspective view showing a semiconductor device according to a first modification of the first embodiment.
  • FIG. 10 is a front view showing the semiconductor device according to
  • FIG. 14 is a front view showing a semiconductor device according to a third modification of the first embodiment, and shows the sealing resin with imaginary lines.
  • FIG. 15 is a perspective view showing a semiconductor device unit including a plurality of semiconductor devices according to a third modification of the first embodiment.
  • FIG. 16 is a perspective view showing a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 17 is a right side view showing a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 18 is a perspective view showing a semiconductor device unit including a plurality of semiconductor devices according to the second embodiment of the present disclosure.
  • FIG. 19 is a perspective view showing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 15 is a perspective view showing a semiconductor device unit including a plurality of semiconductor devices according to a third modification of the first embodiment.
  • FIG. 16 is a perspective view showing a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 17 is a right side view showing
  • FIG. 20 is a perspective view showing a semiconductor device unit including a plurality of semiconductor devices according to a third embodiment of the present disclosure.
  • FIG. 21 is a perspective view showing a semiconductor device according to a fourth embodiment of the present disclosure.
  • FIG. 22 is a perspective view showing an example of a semiconductor device unit including a plurality of semiconductor devices according to the fourth embodiment of the present disclosure.
  • FIG. 23 is a perspective view showing another example of a semiconductor device unit including a plurality of semiconductor devices according to the fourth embodiment of the present disclosure.
  • FIG. 24 is a perspective view showing a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 25 is a perspective view of a semiconductor device according to a fifth embodiment of the present disclosure, viewed from the back side.
  • FIG. 26 is a perspective view showing a semiconductor device according to a modification of the fifth embodiment.
  • FIG. 27 shows a semiconductor device according to a modification of the fifth embodiment, and is a perspective view seen from the back side.
  • FIG. 28 is a circuit configuration diagram showing another configuration example of a semiconductor device according to the present disclosure.
  • a thing A is formed on a thing B and "a thing A is formed on a thing B” mean “a thing A is formed on a thing B” unless otherwise specified.
  • "something A is placed on something B” and “something A is placed on something B” mean "something A is placed on something B” unless otherwise specified.
  • First embodiment 1 to 7 show a semiconductor device according to a first embodiment of the present disclosure.
  • the semiconductor device A10 of this embodiment includes two switching elements 10, a conductive support 2, a support substrate 3, a plurality of control terminals 4, a first conduction member 51, a second conduction member 52, and a third conduction member 51. It includes a conductive member 53, a fourth conductive member 54, a sealing resin 7, a first joint shape J1, and a second joint shape J2.
  • FIG. 1 is a perspective view showing the semiconductor device A10.
  • FIG. 2 is a perspective view of the semiconductor device A10, viewed from the back side.
  • FIG. 3 is a plan view showing the semiconductor device A10, in which the sealing resin 7 is shown with imaginary lines.
  • FIG. 4 is a plan view of FIG. 3 with the third conductive member 53 omitted.
  • FIG. 5 is a front view of the semiconductor device A10, in which the sealing resin 7 is shown with imaginary lines.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • FIG. 7 is a diagram showing the circuit configuration of the semiconductor device A10.
  • the x direction is the left-right direction in the plan view of the semiconductor device A10 (see FIG. 3).
  • the y direction is the vertical direction in the plan view of the semiconductor device A10 (see FIG. 3).
  • One of the x directions is called the x1 direction, and the other x direction is called the x2 direction.
  • one of the y-directions is the y1 direction
  • the other of the y-directions is the y2-direction
  • one of the z-directions is the z1-direction
  • the other z-direction is the z2-direction.
  • plane view refers to when viewed in the z direction.
  • the z1 direction is sometimes referred to as top
  • the z2 direction is sometimes referred to as bottom.
  • the z direction corresponds to the "thickness direction” of the present disclosure
  • the x direction corresponds to the "first direction” of the present disclosure
  • the y direction corresponds to the "second direction” of the present disclosure.
  • the x1 direction corresponds to "one side of the first direction” of the present disclosure
  • the x2 direction corresponds to “the other side of the first direction” of the present disclosure
  • the y1 direction corresponds to "one side of the second direction” of the present disclosure
  • the y2 direction corresponds to the "other side in the second direction” of the present disclosure
  • the z1 direction corresponds to "one side in the thickness direction” of the present disclosure
  • the z2 direction corresponds to the "other side in the thickness direction” of the present disclosure. corresponds to "the other side in the horizontal direction”.
  • Each of the two switching elements 10 is an electronic component that becomes the functional center of the semiconductor device A10.
  • the semiconductor device A10 includes only two switching elements 10.
  • the constituent material of each switching element 10 is a semiconductor material mainly composed of SiC (silicon carbide).
  • Each switching element 10 is, for example, a power semiconductor chip having a switching function, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the two switching elements 10 are the same element.
  • Each switching element 10 is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.
  • Each switching element 10 has an element main surface 101 and an element back surface 102, as shown in FIG.
  • the element main surface 101 and the element back surface 102 are separated in the z direction.
  • the element main surface 101 faces the z1 direction
  • the element back surface 102 faces the z2 direction.
  • the semiconductor device A10 is configured as a half-bridge switching circuit.
  • the first switching element 10A serves as an upper arm
  • the second switching element 10B serves as a lower arm, which are connected in series.
  • the first switching element 10A is mounted on the conductive support 2, as shown in FIGS. 3 to 6.
  • the first switching element 10A is conductively bonded to the conductive support 2 (first conductive portion 2A to be described later) via a conductive bonding material 19.
  • the element back surface 102 faces the first conductive part 2A.
  • the second switching element 10B is mounted on the conductive support 2.
  • the second switching element 10B is conductively bonded to the conductive support 2 (second conductive portion 2B to be described later) via a conductive bonding material 19.
  • the element back surface 102 faces the second conductive part 2B.
  • the two switching elements 10 each have a first main surface electrode 11, a second main surface electrode 12, and a back electrode 13.
  • the configurations of the first main surface electrode 11, second main surface electrode 12, and back surface electrode 13 described below are common to each switching element 10.
  • the first main surface electrode 11 and the second main surface electrode 12 are provided on the element main surface 101.
  • the first main surface electrode 11 and the second main surface electrode 12 are insulated by an insulating film (not shown).
  • the back electrode 13 is provided on the back surface 102 of the element.
  • the first principal surface electrode 11 is, for example, a gate electrode, and a drive signal (eg, gate voltage) for driving the switching element 10 is input thereto.
  • the second main surface electrode 12 is, for example, a source electrode, through which a source current flows.
  • the back electrode 13 is, for example, a drain electrode, through which a drain current flows.
  • the back electrode 13 covers substantially the entire area of the back surface 102 of the element.
  • the back electrode 13 is made of, for example, Ag (silver) plating.
  • each switching element 10 switches between a conductive state and a cutoff state in accordance with this drive signal.
  • a current flows from the back electrode 13 (drain electrode) to the second main surface electrode 12 (source electrode), and in a cutoff state, this current does not flow.
  • Each switching element 10 performs a switching operation.
  • the semiconductor device A10 converts, for example, a DC voltage input to a first main terminal 512 and a third main terminal 532, which will be described later, into an AC voltage using the switching functions of the first switching element 10A and the second switching element 10B. AC voltage is output from the second main terminal 522.
  • the conductive support 2 supports two switching elements 10 (first switching element 10A and second switching element 10B).
  • the conductive support body 2 is bonded onto the support substrate 3 with a conductive bonding material 29 interposed therebetween.
  • the conductive support 2 together with the first conductive member 51, the second conductive member 52, the third conductive member 53, and the fourth conductive member 54, constitutes a path for the main current switched by the two switching elements 10.
  • the conductive support 2 includes a first conductive part 2A and a second conductive part 2B.
  • the first conductive part 2A and the second conductive part 2B are each plate-shaped block members made of metal. This metal is, for example, Cu (copper) or a Cu alloy.
  • the first conductive portion 2A and the second conductive portion 2B constitute a conduction path to the two switching elements 10.
  • the first conductive part 2A and the second conductive part 2B are each bonded onto the support substrate 3 via a conductive bonding material 29, as shown in FIG.
  • a first switching element 10A is bonded to the first conductive portion 2A via a conductive bonding material 19.
  • a second switching element 10B is bonded to the second conductive portion 2B via a conductive bonding material 19.
  • the constituent materials of the conductive bonding material 19 and the conductive bonding material 29 are not particularly limited, and include, for example, solder, metal paste material, or sintered metal.
  • the first conductive part 2A and the second conductive part 2B are spaced apart from each other in the x direction, as shown in FIGS. 3 to 6. In the examples shown in these figures, the first conductive part 2A is located further in the x1 direction than the second conductive part 2B.
  • the first conductive portion 2A and the second conductive portion 2B each have, for example, a rectangular shape in plan view.
  • the thickness (dimension in the z direction) of each of the first conductive part 2A and the second conductive part 2B is, for example, 2.0 mm to 5.0 mm (preferably about 3.0 mm).
  • the conductive support 2 has a main surface 201 and a back surface 202.
  • the main surface 201 and the back surface 202 are separated in the z direction, as shown in FIGS. 4 and 5.
  • the main surface 201 faces in the z1 direction, and the back surface 202 faces in the z2 direction.
  • the main surface 201 is the sum of the upper surface of the first conductive part 2A and the upper surface of the second conductive part 2B.
  • the back surface 202 is a combination of the lower surface of the first conductive section 2A and the lower surface of the second conductive section 2B.
  • the back surface 202 is joined to the support substrate 3 so as to face the support substrate 3.
  • the support substrate 3 supports the conductive support 2.
  • the support substrate 3 is composed of, for example, an AMB (Active Metal Brazing) substrate.
  • Support substrate 3 includes an insulating layer 31, a first metal layer 32, and a second metal layer 33.
  • the insulating layer 31 is made of, for example, ceramics with excellent thermal conductivity. Such ceramics include, for example, SiN (silicon nitride).
  • the insulating layer 31 is not limited to ceramics, and may be an insulating resin sheet or the like.
  • the insulating layer 31 has, for example, a rectangular shape in plan view.
  • the first metal layer 32 is formed on the upper surface of the insulating layer 31 (the surface facing the z1 direction).
  • the constituent material of the first metal layer 32 includes, for example, Cu.
  • the constituent material may include Al (aluminum) instead of Cu.
  • the first metal layer 32 includes a first portion 32A and a second portion 32B.
  • the first portion 32A and the second portion 32B are spaced apart in the x direction.
  • the first portion 32A is located further in the x1 direction than the second portion 32B.
  • the first portion 32A is joined to the first conductive portion 2A and supports the first conductive portion 2A.
  • the second portion 32B is joined to the second conductive portion 2B and supports the second conductive portion 2B.
  • the first portion 32A and the second portion 32B each have a rectangular shape in plan view.
  • the first portion 32A and the second portion 32B have shapes corresponding to the first conductive portion 2A and the second conductive portion 2B, respectively.
  • the second metal layer 33 is formed on the lower surface of the insulating layer 31 (the surface facing the z2 direction).
  • the constituent material of the second metal layer 33 is the same as that of the first metal layer 32.
  • the lower surface (bottom surface 302 described below) of the second metal layer 33 is exposed from the sealing resin 7, for example.
  • the lower surface may not be exposed from the sealing resin 7 and may be covered with the sealing resin 7.
  • the second metal layer 33 overlaps both the first portion 32A and the second portion 32B in plan view.
  • the support substrate 3 has a support surface 301 and a bottom surface 302, as shown in FIG.
  • the support surface 301 and the bottom surface 302 are separated from each other in the z direction.
  • the support surface 301 faces the z1 direction, and the bottom surface 302 faces the z2 direction.
  • the bottom surface 302 is exposed from the sealing resin 7.
  • the support surface 301 is the upper surface of the first metal layer 32, and is the sum of the upper surface of the first portion 32A and the upper surface of the second portion 32B.
  • the support surface 301 faces the conductive support 2, and the conductive support 2 (back surface 202) is joined to the support surface 301.
  • the bottom surface 302 is the lower surface of the second metal layer 33.
  • a heat dissipating member for example, a heat sink), etc. (not shown) can be attached to the bottom surface 302.
  • the dimension of the support substrate 3 in the z direction is, for example, 0.01 mm to 2.0 mm.
  • Each of the first conductive member 51, the second conductive member 52, the third conductive member 53, and the fourth conductive member 54 constitutes a path for the main current switched by the two switching elements 10.
  • the first conductive member 51 has a connecting portion 511 and a first main terminal 512.
  • the connecting portion 511 is bonded to the first conductive portion 2A via a conductive bonding material 59.
  • the first main terminal 512 is exposed from the sealing resin 7 and is located in the x1 direction with respect to the sealing resin 7.
  • the second conductive member 52 has a connecting portion 521 and a second main terminal 522.
  • the connecting portion 521 is bonded to the second conductive portion 2B via a conductive bonding material 59.
  • the second main terminal 522 is exposed from the sealing resin 7 and is located in the x2 direction with respect to the sealing resin 7.
  • the third conductive member 53 has a connecting portion 531 and a third main terminal 532.
  • the connecting portion 531 is bonded to the second main surface electrode 12 (source electrode) of the second switching element 10B via a conductive bonding material 59.
  • the third main terminal 532 is exposed from the sealing resin 7 and is located in the x1 direction with respect to the sealing resin 7. Further, the third main terminal 532 is located in the y1 direction with respect to the first main terminal 512, and overlaps with the first main terminal 512 when viewed in the y direction.
  • the fourth conductive member 54 is connected to the second main surface electrode 12 (source electrode) of the first switching element 10A and the second conductive part 2B, and is connected to the second main surface electrode 12 of the first switching element 10A and the second conductive part 2B.
  • the section 2B is electrically connected.
  • the fourth conductive member 54 and the second main surface electrode 12 of the first switching element 10A are bonded via a conductive bonding material 59.
  • the constituent material of the conductive bonding material 59 is not particularly limited, and may be, for example, solder, metal paste material, or sintered metal.
  • a DC voltage to be subjected to power conversion is input to the first main terminal 512 and the third main terminal 532 described above.
  • the first main terminal 512 is a positive electrode (P terminal), and the third main terminal 532 is a negative electrode (N terminal).
  • P terminal positive electrode
  • N terminal negative electrode
  • From the second main terminal 522 an AC voltage whose power has been converted by the first switching element 10A and the second switching element 10B is output.
  • the first main terminal 512 is electrically connected to the back electrode 13 (drain electrode) of the first switching element 10A via the first conductive portion 2A.
  • the second main terminal 522 is electrically connected to the back electrode 13 (drain electrode) of the second switching element 10B via the second conductive portion 2B.
  • the third main terminal 532 is electrically connected to the second main surface electrode 12 (source electrode) of the second switching element 10B.
  • the first main terminal 512, the second main terminal 522, and the third main terminal 532 are examples of components of "a plurality of main terminals.”
  • Each of the plurality of control terminals 4 is a pin-shaped terminal for controlling the first switching element 10A and the second switching element 10B.
  • the plurality of control terminals 4 include a plurality of first control terminals 41A, 41B and a plurality of second control terminals 42A, 42B.
  • the plurality of first control terminals 41A, 41B are used for controlling the first switching element 10A, etc.
  • the plurality of second control terminals 42A, 42B are used for controlling the second switching element 10B.
  • each of the plurality of control terminals 4 partially protrudes from the sealing resin 7 in the y2 direction and extends in the z1 direction.
  • the plurality of first control terminals 41A, 41B are located in the x1 direction with respect to the plurality of second control terminals 42A, 42B.
  • the plurality of first control terminals 41A, 41B are arranged at intervals in the x direction.
  • the first control terminal 41A is a terminal (gate terminal) for inputting a drive signal to the first switching element 10A.
  • the first control terminal 41A is connected to a wire 61 and is electrically connected to the first main surface electrode 11 (gate electrode) of the first switching element 10A via the wire 61.
  • a drive signal for driving the first switching element 10A is input to the first control terminal 41A (for example, a gate voltage is applied).
  • the first control terminal 41B is a source signal detection terminal (source sense terminal) of the first switching element 10A.
  • the first control terminal 41B is connected to a wire 62 and is electrically connected to the second main surface electrode 12 (source electrode) of the first switching element 10A via the wire 62.
  • the voltage (voltage corresponding to the source current) applied to the second main surface electrode 12 (source electrode) of the first switching element 10A is detected from the first control terminal 41B.
  • the plurality of second control terminals 42A, 42B are arranged at intervals in the x direction.
  • the second control terminal 42A is a terminal (gate terminal) for inputting a drive signal to the second switching element 10B.
  • the second control terminal 42A is connected to a wire 61 and is electrically connected to the first main surface electrode 11 (gate electrode) of the second switching element 10B via the wire 61.
  • a drive signal for driving the second switching element 10B is input to the second control terminal 42A (for example, a gate voltage is applied).
  • the second control terminal 42B is a source signal detection terminal (source sense terminal) of the second switching element 10B.
  • the second control terminal 42B is connected to a wire 62 and is electrically connected to the second main surface electrode 12 (source electrode) of the second switching element 10B via the wire 62.
  • a voltage (voltage corresponding to the source current) applied to the second main surface electrode 12 (source electrode) of the second switching element 10B is detected from the second control terminal 42B.
  • Each of the wires 61 and 62 described above is, for example, a bonding wire.
  • the constituent material of each wire 61, 62 includes, for example, Au (gold), Al, or Cu.
  • the sealing resin 7 seals the two switching elements 10, the conductive support 2 (the first conductive part 2A and the second conductive part 2B), the support substrate 3 (excluding the bottom surface 302), and one of the plurality of control terminals 4. It covers each portion of the first conductive member 51, the second conductive member 52, and the third conductive member 53, the fourth conductive member 54, and the plurality of wires 61, 62, respectively.
  • the sealing resin 7 is made of, for example, black epoxy resin.
  • the sealing resin 7 is formed by, for example, molding.
  • the sealing resin 7 has a resin main surface 71 , a resin back surface 72 , a first resin side surface 73 , a second resin side surface 74 , a third resin side surface 75 , and a fourth resin side surface 76 .
  • the main resin surface 71 faces the z1 direction
  • the resin back surface 72 faces the z2 direction.
  • the main resin surface 71 and the resin back surface 72 are separated from each other in the z direction.
  • the resin back surface 72 has a frame shape that surrounds the bottom surface 302 of the support substrate 3 (the lower surface of the second metal layer 33) in plan view.
  • the bottom surface 302 of the support substrate 3 is exposed from the resin back surface 72 and is flush with the resin back surface 72, for example.
  • the first resin side surface 73 and the second resin side surface 74 are separated from each other in the x direction.
  • Each of the first resin side surface 73 and the second resin side surface 74 is connected to both the resin main surface 71 and the resin back surface 72, and is sandwiched between them in the z direction.
  • the first resin side surface 73 faces in the x1 direction.
  • the second resin side surface 74 is located in the x2 direction with respect to the first resin side surface 73 and faces in the x2 direction.
  • the first main terminal 512 of the first conductive member 51 and the third main terminal 532 of the third conductive member 53 protrude from the first resin side surface 73 in the x1 direction.
  • the second main terminal 522 of the second conductive member 52 protrudes from the second resin side surface 74 in the x2 direction.
  • the third resin side surface 75 and the fourth resin side surface 76 are separated from each other in the y direction.
  • Each of the third resin side surface 75 and the fourth resin side surface 76 is connected to both the resin main surface 71 and the resin back surface 72, and is sandwiched between them in the z direction.
  • the third resin side surface 75 faces in the y1 direction.
  • the fourth resin side surface 76 is located in the y2 direction with respect to the third resin side surface 75 and faces in the y2 direction.
  • the sealing resin 7 has a plurality of (two in this embodiment) side recesses 751.
  • Each of the plurality of side surface recesses 751 is recessed from the third resin side surface 75 in the y2 direction.
  • each of the plurality of side recesses 751 is also recessed from the main resin surface 71 in the z2 direction.
  • the plurality of side recesses 751 are spaced apart from each other in the x direction.
  • Each of the plurality of control terminals 4 protrudes from the fourth resin side surface 76 in the y2 direction. As shown in FIG. 5, each of the plurality of control terminals 4 overlaps with one of the plurality of side recesses 751 when viewed in the y direction.
  • each of the plurality of first control terminals 41A, 41B overlaps with one side recess 751 (the side recess 751 located in the x1 direction) when viewed in the y direction
  • the plurality of second control terminals 42A, 42B Each overlaps with the other side recess 751 (the side recess 751 located in the x2 direction) when viewed in the y direction.
  • the first bonding shape J1 is arranged in the y1 direction in the semiconductor device A10.
  • the second bond shape J2 is arranged in the y2 direction in the semiconductor device A10.
  • the first joint shape J1 and the second joint shape J2 can be combined with each other.
  • the plurality of side recesses 751 in the sealing resin 7 are included in the first joint shape J1.
  • the plurality of control terminals 4 are included in the second joint shape J2.
  • FIG. 8 shows a semiconductor device unit B10 including a plurality of semiconductor devices A10.
  • a plurality of semiconductor devices A10 are lined up in the y direction.
  • semiconductor devices A10 adjacent to each other in the y direction a portion of each of the plurality of control terminals 4 of one semiconductor device A10 is accommodated in a side recess 751 of the other semiconductor device A10.
  • the plurality of control terminals 4 second coupling shape J2
  • side recesses 751 first coupling shape J1
  • the semiconductor device A10 includes only two switching elements 10.
  • One of the two switching elements 10 is a first switching element 10A, and the other is a second switching element 10B.
  • Each of the first switching element 10A and the second switching element 10B includes SiC as a constituent material.
  • the first switching element 10A and the second switching element 10B are connected in series with the first switching element 10A as an upper arm and the second switching element 10B as a lower arm. According to such a configuration in which only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, unlike a configuration in which a plurality of switching elements connected in parallel are built-in, heat The occurrence of interference can be avoided and heat dissipation can be improved. Furthermore, by using a plurality of semiconductor devices A10 connected in parallel like the semiconductor device unit B10 shown in FIG. 8, it is possible to easily accommodate various required current capacities.
  • the semiconductor device A10 has a first main terminal 512 located in the x1 direction with respect to the sealing resin 7. Further, the semiconductor device A10 includes a first bonding shape J1 and a second bonding shape J2. The first coupling shape J1 is arranged in the y1 direction in the switching element 10. The second bond shape J2 is arranged in the y2 direction in the semiconductor device A10, and the first bond shape J1 and the second bond shape J2 can be combined with each other. According to such a configuration, by arranging the plurality of semiconductor devices A10 in the y direction and combining them with each other, it is possible to handle the plurality of semiconductor devices A10 as one semiconductor device unit B10.
  • the semiconductor device A10 has a plurality of side recesses 751 and a plurality of control terminals 4.
  • the plurality of side recesses 751 are recessed from the third resin side surface 75 in the y2 direction, and the plurality of control terminals 4 protrude from the fourth resin side surface 76 in the y2 direction.
  • Each of the plurality of control terminals 4 overlaps with one of the plurality of side recesses 751 when viewed in the y direction.
  • FIG. 9 and 10 show a semiconductor device according to a first modification of the first embodiment.
  • FIG. 9 is a perspective view showing a semiconductor device A11 of this modification.
  • FIG. 10 is a front view of the semiconductor device A11, in which the sealing resin 7 is shown with imaginary lines.
  • elements that are the same as or similar to those of the semiconductor device A10 of the embodiment described above are given the same reference numerals as those of the embodiment described above, and the description thereof will be omitted as appropriate.
  • the configurations of the respective parts in the modifications shown in FIG. 9 and onwards can be appropriately combined with each other within a range that does not cause technical contradiction.
  • the positional relationship between the first conductive member 51 (first main terminal 512) and the third conductive member 53 (third main terminal 532) is different from the semiconductor device A10 of the above embodiment.
  • the first main terminal 512 and the third main terminal 532 are arranged at different positions in the z direction.
  • the third main terminal 532 is located in the z1 direction with respect to the first main terminal 512.
  • the semiconductor device A11 of this modification since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A11 connected in parallel, it is possible to easily accommodate various required current capacities.
  • the third main terminal 532 is located above (in the z1 direction) with respect to the first main terminal 512.
  • the vertical height is It is possible to efficiently connect two external terminals that each extend in the y direction at once due to the difference.
  • the same effects as those of the above embodiment are achieved.
  • FIG. 11 and 12 show a semiconductor device according to a second modification of the first embodiment.
  • FIG. 11 is a perspective view showing a semiconductor device A12 of this modification.
  • FIG. 12 is a front view of the semiconductor device A12, in which the sealing resin 7 is shown with imaginary lines.
  • the positional relationship between the first conductive member 51 (first main terminal 512) and the third conductive member 53 (third main terminal 532) is different from the semiconductor device A10 of the above embodiment.
  • the first main terminal 512 and the third main terminal 532 are arranged at different positions in the z direction.
  • the third main terminal 532 is located in the z1 direction with respect to the first main terminal 512. Further, the third main terminal 532 is located in the x2 direction with respect to the first main terminal 512, and overlaps with the first main terminal 512 in a plan view.
  • the semiconductor device A12 of this modification since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided, and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A12 connected in parallel, it is possible to easily accommodate various required current capacities.
  • the third main terminal 532 is located in the x2 direction with respect to the first main terminal 512, and is also located above the first main terminal 512 (in the z1 direction). According to such a configuration, for example, when a plurality of semiconductor devices A12 are arranged in the y direction and connected in parallel, the vertical height is It is possible to efficiently connect two external terminals that each extend in the y direction at once due to the difference. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
  • FIG. 13 and 14 show a semiconductor device according to a third modification of the first embodiment.
  • FIG. 13 is a perspective view showing a semiconductor device A13 of this modification.
  • FIG. 14 is a front view of the semiconductor device A13, in which the sealing resin 7 is shown with imaginary lines.
  • the semiconductor device A13 of this modification differs from the semiconductor device A10 of the above embodiment mainly in the arrangement of the second conductive member 52 (second main terminal 522) and the third conductive member 53 (third main terminal 532). .
  • the third main terminal 532 is located in the x2 direction with respect to the sealing resin 7.
  • the third main terminal 532 of the third conductive member 53 protrudes from the second resin side surface 74 in the x2 direction.
  • the second main terminal 522 is located in the y2 direction with respect to the sealing resin 7.
  • the second main terminal 522 of the second conductive member 52 protrudes from the fourth resin side surface 76 in the y2 direction and extends in the z1 direction.
  • the second main terminal 522 is located between the plurality of first control terminals 41A, 41B and the plurality of second control terminals 42A, 42B in the x direction.
  • the sealing resin 7 has three side recesses 751.
  • the three side recesses 751 are spaced apart from each other in the x direction.
  • Each of the plurality of first control terminals 41A, 41B overlaps with one side recess 751 (side recess 751 located in the x1 direction) when viewed in the y direction, and each of the plurality of second control terminals 42A, 42B It overlaps with another side recess 751 (the side recess 751 located in the x2 direction) when viewed in the direction.
  • the second main terminal 522 overlaps with another side recess 751 (the side recess 751 located at the center in the x direction) when viewed in the y direction.
  • a plurality (three) of side recesses 751 in the sealing resin 7 are included in the first joint shape J1.
  • the plurality of control terminals 4 and the second main terminal 522 are included in the second joint shape J2.
  • FIG. 15 shows a semiconductor device unit B11 including a plurality of semiconductor devices A13.
  • the plurality of semiconductor devices A13 are lined up in the y direction.
  • the semiconductor devices A13 adjacent in the y direction a portion of each of the plurality of control terminals 4 of one semiconductor device A10 and a portion of the second main terminal 522 are accommodated in the side recess 751 of the other semiconductor device A10. has been done.
  • the plurality of control terminals 4 and second main terminals 522 second coupling shape J2
  • side recess 751 first coupling shape J1
  • the semiconductor device A13 of this modification since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A13 connected in parallel, it is possible to easily accommodate various required current capacities. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
  • FIG. 16 and 17 show a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 16 is a perspective view showing the semiconductor device A20 of this embodiment.
  • FIG. 17 is a right side view of the semiconductor device A20.
  • the semiconductor device A20 of this embodiment differs from the semiconductor device A10 of the above embodiment mainly in that it includes a first engagement portion 752 and a second engagement portion 762.
  • the first engaging portion 752 is provided on the third resin side surface 75 and protrudes from the third resin side surface 75 in the y1 direction.
  • the first engaging portion 752 has an L-shaped cross section and extends a predetermined length from the second resin side surface 74 in the x1 direction.
  • the second engaging portion 762 is a groove recessed from the fourth resin side surface 76 in the y1 direction.
  • the second engaging portion 762 has an L-shaped cross section and extends a predetermined length from the second resin side surface 74 in the x1 direction.
  • the first engaging portion 752 and the second engaging portion 762 are capable of engaging with each other.
  • the side recess 751 is formed continuously from the first resin side surface 73 to the second resin side surface 74.
  • the side recess 751 and the first engaging portion 752 in the sealing resin 7 are included in the first joint shape J1.
  • the plurality of control terminals 4 and the second engaging portions 762 in the sealing resin 7 are included in the second joint shape J2.
  • FIG. 18 shows a semiconductor device unit B20 including a plurality of semiconductor devices A20.
  • the plurality of semiconductor devices A20 are lined up in the y direction.
  • semiconductor devices A20 adjacent to each other in the y direction a portion of each of the plurality of control terminals 4 of one semiconductor device A20 is accommodated in a side recess 751 of the other semiconductor device A20. Further, the second engaging portion 762 of one semiconductor device A20 and the first engaging portion 752 of the other semiconductor device A20 are engaged with each other.
  • the plurality of control terminals 4 and the second engagement portions 762 (second coupling shape J2) are connected to the side recess 751 and the first engagement. portion 752 (first joint shape J1).
  • the first engaging portion 752 and the second engaging portion 762 engage with each other, thereby mechanically connecting the plurality of semiconductor devices A20.
  • the semiconductor device A20 of the present embodiment since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided, and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A20 connected in parallel, it is possible to easily accommodate various required current capacities.
  • the semiconductor device A20 has a first engagement portion 752 included in the first coupling shape J1 and a second engagement portion 762 included in the second coupling shape J2.
  • the first engaging portion 752 and the second engaging portion 762 are capable of engaging with each other. According to such a configuration, by arranging the plurality of semiconductor devices A20 in the y direction and combining them with each other, it is possible to handle the plurality of semiconductor devices A20 as one mechanically connected semiconductor device unit B20. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
  • FIG. 19 shows a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 19 is a perspective view showing the semiconductor device A30 of this embodiment.
  • the semiconductor device A30 of this embodiment differs greatly from the semiconductor device A10 of the above embodiment in that it includes a first engagement portion 753 and a second engagement portion 763.
  • the sealing resin 7 does not have a side recess 751.
  • the plurality of control terminals 4 protrude from the main resin surface 71 of the sealing resin 7 and extend in the z1 direction.
  • the first engaging portion 753 is provided on the third resin side surface 75 and is a groove recessed from the third resin side surface 75 in the y2 direction.
  • the first engaging portion 753 has a trapezoidal cross section and is formed continuously in the z direction from the main resin surface 71 to the resin back surface 72.
  • the second engaging portion 763 is provided on the fourth resin side surface 76 and protrudes from the fourth resin side surface 76 in the y2 direction.
  • the second engaging portion 763 has a trapezoidal cross section and is formed continuously in the z direction from the resin main surface 71 to the resin back surface 72.
  • the first engaging portion 753 and the second engaging portion 763 are capable of engaging with each other.
  • the first engaging portion 753 in the sealing resin 7 is included in the first joint shape J1.
  • the second engaging portion 763 in the sealing resin 7 is included in the second joint shape J2.
  • FIG. 20 shows a semiconductor device unit B30 including a plurality of semiconductor devices A30.
  • the plurality of semiconductor devices A30 are lined up in the y direction.
  • the first engaging portion 753 of one semiconductor device A30 and the second engaging portion 763 of the other semiconductor device A30 are engaged with each other.
  • the first engaging portion 753 first joint shape J1
  • the second engaging portion 763 second joint shape J2
  • the semiconductor device A30 of the present embodiment only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, so that generation of thermal interference is avoided and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A30 connected in parallel, it is possible to easily accommodate various required current capacities.
  • the semiconductor device A30 has a first engagement portion 753 included in the first coupling shape J1 and a second engagement portion 763 included in the second coupling shape J2.
  • the first engaging portion 753 and the second engaging portion 763 are capable of engaging with each other. According to such a configuration, by arranging a plurality of semiconductor devices A30 in the y direction and combining them with each other, it is possible to handle the plurality of semiconductor devices A30 as one mechanically connected semiconductor device unit B30. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
  • FIG. 21 shows a semiconductor device according to a fourth embodiment of the present disclosure.
  • FIG. 21 is a perspective view showing the semiconductor device A40 of this embodiment.
  • the semiconductor device A40 of this embodiment is significantly different from the semiconductor device A30 of the above embodiment in that it includes a first alignment section 758, a second alignment section 768, a first connection section 43, and a second connection section 44. . Further, unlike the semiconductor device A30 of the above embodiment, a plurality of control terminals 4 are not provided.
  • the first positioning portion 758 is provided on the third resin side surface 75 and is a recessed portion recessed from the third resin side surface 75 in the y2 direction.
  • the first positioning portion 758 is also recessed from the main resin surface 71 .
  • the first positioning portions 758 are provided at two locations separated in the x direction.
  • the second positioning portion 768 is a convex portion that is provided on the fourth resin side surface 76 and protrudes from the fourth resin side surface 76 in the y2 direction.
  • the second positioning portions 768 are provided at two locations separated in the x direction.
  • the second alignment part 768 can be fitted into the corresponding first alignment part 758, whereby the first alignment part 758 and the second alignment part 768 are aligned.
  • first alignment part 758 and the second alignment part 768 are aligned, the first engagement part 753 and the second engagement part 763 engage with each other.
  • first engaging portion 753 and the first positioning portion 758 in the sealing resin 7 are included in the first joint shape J1.
  • second engaging portion 763 and the second positioning portion 768 in the sealing resin 7 are included in the second joint shape J2.
  • the first connecting portion 43 is arranged on the main resin surface 71 of the sealing resin 7.
  • the first connection portion 43 is electrically connected to either the first switching element 10A or the second switching element 10B.
  • four first connection parts 43 are provided.
  • the four first connecting portions 43 are arranged closer to the y2 direction on the resin main surface 71 and are arranged along the x direction.
  • two first connecting parts 43 are arranged closer to the x1 direction, and the other two first connecting parts 43 are arranged closer to the x2 direction.
  • the two first connection portions 43 closer to the x1 direction are electrically connected to the first switching element 10A.
  • One of the first connection parts 43 is electrically connected to the first main surface electrode 11 (gate electrode) of the first switching element 10A, and the other first connection part 43 is electrically connected to the second main surface electrode 12 (gate electrode) of the first switching element 10A. source electrode). Further, the two first connection portions 43 closer to the x2 direction are electrically connected to the second switching element 10B. One of the first connection parts 43 is electrically connected to the first main surface electrode 11 (gate electrode) of the second switching element 10B, and the other first connection part 43 is electrically connected to the second main surface electrode 12 (gate electrode) of the second switching element 10B. source electrode).
  • the second connecting portion 44 is arranged on the main resin surface 71 of the sealing resin 7.
  • the second connection portion 44 is electrically connected to either the first switching element 10A or the second switching element 10B.
  • four second connections 44 are provided.
  • the second connecting portion 44 is arranged apart from the corresponding first connecting portion 43 in the y direction.
  • the four second connecting portions 44 are arranged closer to the y1 direction on the main resin surface 71 and are arranged along the x direction.
  • two second connecting portions 44 are arranged closer to the x1 direction, and the other two second connecting portions 44 are arranged closer to the x2 direction.
  • the two second connection portions 44 closer to the x1 direction are electrically connected to the first switching element 10A.
  • One of the second connection parts 44 is electrically connected to the first main surface electrode 11 (gate electrode) of the first switching element 10A, and the other second connection part 44 is electrically connected to the second main surface electrode 12 (gate electrode) of the first switching element 10A. source electrode). Furthermore, the two second connecting portions 44 closer to the x2 direction are electrically connected to the second switching element 10B. One of the second connection parts 44 is electrically connected to the first main surface electrode 11 (gate electrode) of the second switching element 10B, and the other second connection part 44 is electrically connected to the second main surface electrode 12 (gate electrode) of the second switching element 10B. source electrode).
  • a configuration including a plurality of control terminals 4 may be used.
  • a pin-shaped control terminal is attached to each of the four first connection portions 43 shown in FIG. 21, for example.
  • FIG. 22 shows an example of a semiconductor device unit B40 including a plurality of semiconductor devices A40.
  • the plurality of semiconductor devices A40 are lined up in the y direction.
  • the first engaging portion 753 of one semiconductor device A40 and the second engaging portion 763 of the other semiconductor device A40 engage with each other, and A second alignment portion 768 of the other semiconductor device A40 is fitted into the first alignment portion 758.
  • the first engaging portion 753 and the first positioning portion 758 (first joint shape J1), the second engaging portion 763, and A second positioning portion 768 (second joint shape J2) is combined.
  • the first engaging portion 753 and the second engaging portion 763 engage with each other, thereby mechanically connecting the plurality of semiconductor devices A30.
  • the first connection portion 43 of one semiconductor device A40 and the corresponding second connection portion 44 of the other semiconductor device A40 are connected. , are electrically connected by a pin-shaped connecting member 47.
  • control terminal 4 is attached to each of the four first connection parts 43 in one semiconductor device A40. According to such a configuration, when a plurality of semiconductor devices A40 are connected in parallel, the control terminal 4 is provided for only one semiconductor device A40 to connect it to the outside, so that each of the plurality of semiconductor devices A40 can be connected in parallel. Drive control of the first switching element 10A and the second switching element 10B is possible.
  • FIG. 23 shows another example of a semiconductor device unit B41 including a plurality of semiconductor devices A40.
  • the first connection portion 43 of one semiconductor device A40 and the corresponding second connection portion 44 of the other semiconductor device A40 are connected. , are electrically connected by a plate-shaped connecting member 48.
  • the control terminal 4 is attached to each of the four first connection parts 43 in one semiconductor device A40.
  • the control terminal 4 is connected to a drive board 80 (represented by imaginary lines in FIG. 23) arranged in the z1 direction with respect to the plurality of semiconductor devices A40.
  • each of the plurality of semiconductor devices A40 can be connected in parallel. It is possible to drive and control the first switching element 10A and the second switching element 10B.
  • the semiconductor device A40 of the present embodiment since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A40 connected in parallel, it is possible to easily accommodate various required current capacities.
  • the first engaging portion 753 and the second engaging portion 763 are capable of engaging with each other. According to such a configuration, by arranging a plurality of semiconductor devices A40 in the y direction and combining them with each other, it is possible to handle the plurality of semiconductor devices A40 as one mechanically connected semiconductor device unit B40 (B41). It is. Furthermore, in this embodiment, when the first alignment part 758 and the second alignment part 768 are aligned, the first engagement part 753 and the second engagement part 763 engage with each other. According to such a configuration, it is possible to accurately connect the plurality of semiconductor devices A40. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
  • FIG. 24 and 25 show a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 24 is a perspective view showing the semiconductor device A50 of this embodiment.
  • FIG. 25 is a perspective view of the semiconductor device A50, viewed from the back side.
  • the semiconductor device A50 of this embodiment differs greatly from the semiconductor device A30 of the above embodiment in that it includes a first engaging portion 754, a second engaging portion 764, a third connecting portion 45, and a fourth connecting portion 46. There is.
  • the first engaging portion 754 is provided on the third resin side surface 75 and has a concave connector shape recessed from the third resin side surface 75 in the y2 direction. In the illustrated example, the first engaging portions 754 are provided at two locations separated in the x direction.
  • the second engaging portion 764 is provided on the fourth resin side surface 76 and has a convex connector shape that protrudes in the y2 direction. In the illustrated example, the second engaging portions 764 are provided at two locations separated in the x direction.
  • the second engaging part 764 can be fitted into the corresponding first engaging part 754, so that the first engaging part 754 and the second engaging part 764 can be engaged with each other.
  • the first engaging portion 754 is included in the first coupling shape J1. Further, the second engaging portion 764 is included in the second joint shape J2. Note that the first engaging portion 754 and the second engaging portion 764 are configured by a separate member from the sealing resin 7, for example, but may be configured by a portion of the sealing resin 7.
  • the third connection portion 45 is arranged in the y1 direction in the semiconductor device A50.
  • the third connection portion 45 is electrically connected to either the first switching element 10A or the second switching element 10B.
  • four third connecting portions 45 are provided.
  • Each of the third connecting parts 45 is a pin-shaped terminal, and two third connecting parts 45 are arranged in one first engaging part 754, and the other two third connecting parts 45 are arranged in the other first engaging part 754. 754.
  • the two third connecting portions 45 disposed in the first engaging portion 754 closer to the x1 direction are electrically connected to the first switching element 10A.
  • One of the third connection parts 45 is electrically connected to the first main surface electrode 11 (gate electrode) of the first switching element 10A, and the other third connection part 45 is electrically connected to the second main surface electrode 12 (gate electrode) of the first switching element 10A. source electrode). Further, the two third connecting portions 45 arranged in the first engaging portion 754 closer to the x2 direction are electrically connected to the second switching element 10B. One of the third connection parts 45 is electrically connected to the first main surface electrode 11 (gate electrode) of the second switching element 10B, and the other third connection part 45 is electrically connected to the second main surface electrode 12 (gate electrode) of the second switching element 10B. source electrode).
  • the fourth connection portion 46 is arranged in the y2 direction in the semiconductor device A50.
  • the fourth connection portion 46 is electrically connected to either the first switching element 10A or the second switching element 10B.
  • four fourth connection parts 46 are provided.
  • Each fourth connection part 46 is a concave terminal, and two fourth connection parts 46 are arranged in one second engagement part 764, and the other two fourth connection parts 46 are arranged in the other second engagement part 764. 764.
  • the two fourth connecting portions 46 disposed on the second engaging portion 764 closer to the x1 direction are electrically connected to the first switching element 10A.
  • One of the fourth connection parts 46 is electrically connected to the first main surface electrode 11 (gate electrode) of the first switching element 10A, and the other fourth connection part 46 is electrically connected to the second main surface electrode 12 (gate electrode) of the first switching element 10A. source electrode). Further, the two fourth connecting portions 46 arranged in the second engaging portion 764 closer to the x2 direction are electrically connected to the second switching element 10B. One of the fourth connection parts 46 is electrically connected to the first main surface electrode 11 (gate electrode) of the second switching element 10B, and the other fourth connection part 46 is electrically connected to the second main surface electrode 12 (gate electrode) of the second switching element 10B. source electrode). When the first engaging portion 754 and the second engaging portion 764 are engaged, the third connecting portion 45 and the corresponding fourth connecting portion 46 are electrically connected.
  • the semiconductor device A50 of the present embodiment since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A50 connected in parallel, it is possible to easily accommodate various required current capacities.
  • the semiconductor device A50 has a first engagement portion 754 included in the first coupling shape J1 and a second engagement portion 764 included in the second coupling shape J2.
  • the first engaging portion 754 and the second engaging portion 764 are capable of engaging with each other. According to such a configuration, by arranging the plurality of semiconductor devices A50 in the y direction and combining them with each other, it is possible to handle the plurality of semiconductor devices A50 as one mechanically connected semiconductor device unit. Further, in this embodiment, when the first engaging portion 754 and the second engaging portion 764 engage, the third connecting portion 45 and the corresponding fourth connecting portion 46 are electrically connected.
  • the first switching element of each of the plurality of semiconductor devices A50 10A and the second switching element 10B can be controlled.
  • the same effects as those of the above embodiment are achieved.
  • a configuration may be adopted in which the plurality of control terminals 4 are not provided.
  • 26 and 27 show a semiconductor device A51 according to this modification.
  • the semiconductor device A50 and the semiconductor device A51 can be mixed and connected in parallel to be used as one semiconductor device unit.
  • the semiconductor device according to the present disclosure is not limited to the embodiments described above.
  • the specific configuration of each part of the semiconductor device according to the present disclosure can be changed in design in various ways.
  • the semiconductor device of the present disclosure may be configured to further include, for example, a diode (such as a Schottky barrier diode) as a rectifying element.
  • a diode such as a Schottky barrier diode
  • FIG. 28 a configuration is adopted in which two Schottky barrier diodes SBD1 and SBD2 are individually connected in parallel to two first switching elements 10A and second switching elements 10B connected in series. Good too.
  • the present disclosure includes configurations related to the following additional notes.
  • Additional note 1 comprising only two switching elements and a sealing resin that covers the only two switching elements, Of the only two switching elements, one is a first switching element and the other is a second switching element, Each of the first switching element and the second switching element includes SiC as a constituent material, The first switching element and the second switching element are connected in series, with the first switching element serving as an upper arm and the second switching element serving as a lower arm.
  • Appendix 2. Further comprising a plurality of main terminals through which main current flows, The semiconductor device according to appendix 1, wherein the plurality of main terminals include a first main terminal located on one side in a first direction with respect to the sealing resin.
  • the sealing resin has a resin main surface facing one side in a thickness direction perpendicular to the first direction and the second direction, and a first resin side surface and a second resin side surface facing one side and the other side in the first direction.
  • the semiconductor device according to appendix 3 comprising a resin side surface, and a third resin side surface and a fourth resin side surface facing one side and the other side in the second direction. Appendix 5.
  • the plurality of main terminals include a second main terminal located on the other side in the first direction with respect to the sealing resin, and a third main terminal located on one side in the first direction with respect to the sealing resin.
  • the semiconductor device according to appendix 4 comprising a terminal. Appendix 6.
  • the sealing resin has at least one side recess that is recessed from the third resin side surface to the other side in the second direction, The plurality of control terminals protrude from the fourth resin side surface and overlap the at least one side recess when viewed in the second direction, the at least one side recess is included in the first coupling shape;
  • the semiconductor device according to appendix 4 wherein the plurality of control terminals are included in the second coupling shape. Appendix 7.
  • the plurality of main terminals include a second main terminal protruding from the fourth resin side surface, The second main terminal overlaps the at least one side recess when viewed in the second direction,
  • Appendix 8 A first engaging portion is provided on the third resin side surface, and a second engaging portion is provided on the fourth resin side surface, The first engaging portion and the second engaging portion are capable of engaging with each other, the first engagement part is included in the first coupling shape, The semiconductor device according to appendix 4, wherein the second engaging portion is included in the second coupling shape.
  • the sealing resin has a first alignment portion provided on the third resin side surface and a second alignment portion provided on the fourth resin side surface, the first alignment part is included in the first joint shape, the second alignment part is included in the second joint shape,
  • the semiconductor device according to appendix 8 wherein the first engaging part and the second engaging part engage with each other when the first positioning part and the second positioning part are aligned.
  • Appendix 10. further comprising a plurality of control terminals for controlling the first switching element and the second switching element, The semiconductor device according to appendix 8, wherein the plurality of control terminals protrude from the resin main surface.
  • the semiconductor device according to appendix 8 wherein a first connection portion electrically connected to at least one of the first switching element and the second switching element is disposed on the resin main surface.
  • Appendix 12. A second connection portion that is electrically connected to at least one of the first switching element and the second switching element is disposed on the resin main surface, The semiconductor device according to appendix 11, wherein the second connection portion is spaced apart from the first connection portion in the second direction.
  • Appendix 13 further comprising a plurality of control terminals for controlling the first switching element and the second switching element, The semiconductor device according to appendix 11, wherein each of the plurality of control terminals is connected to the first connection portion.
  • a third connecting portion is provided on one side in the second direction, and a fourth connecting portion is provided on the other side in the second direction, Each of the third connection part and the fourth connection part is electrically connected to at least one of the first switching element and the second switching element, The semiconductor device according to appendix 8, wherein when the first engaging portion and the second engaging portion engage with each other, the third connecting portion and the fourth connecting portion are electrically connected.
  • Appendix 15. further comprising a plurality of control terminals for controlling the first switching element and the second switching element, The semiconductor device according to appendix 14, wherein the plurality of control terminals protrude from the resin main surface.
  • Appendix 16. comprising a plurality of semiconductor devices according to any one of appendices 1 to 15, A semiconductor device unit in which the plurality of semiconductor devices are combined with each other.
  • Switching element 10A First switching element 10B: Second switching Element 101: Element principal surface 102: Element back surface 11: First principal surface electrode 12: Second principal surface electrode 13: Back electrode 19: Conductive bonding material 2: Conductive support 2A: First conductive part 2B: Second conductive Part 201: Main surface 202: Back surface 29: Conductive bonding material 3: Support substrate 301: Support surface 302: Bottom surface 31: Insulating layer 32: First metal layer 32A: First portion 32B: Second portion 33: Second metal Layer 4: Control terminals 41A, 41B: First control terminals 42A, 42B: Second control terminals 43: First connection section 44: Second connection section 45: Third connection section 46: Fourth connection section 47, 48: Connection Member 51: First conductive member 511: Connection portion 512: First main terminal 52:

Abstract

This semiconductor device and this semiconductor device unit comprise: two switching elements; and a sealing resin that covers the two switching elements. One of the two switching elements is a first switching element and the other is a second switching element. The first switching element and the second switching element each contain SiC as a constituent material. The first switching element and the second switching element are connected in series so that the first switching element serves as an upper arm and the second switching element serves as a lower arm.

Description

半導体装置および半導体装置ユニットSemiconductor equipment and semiconductor equipment units
　本開示は、半導体装置および半導体装置ユニットに関する。 The present disclosure relates to a semiconductor device and a semiconductor device unit.
　従来、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）などの電力用スイッチング素子を備える半導体装置が知られている。このような半導体装置は、産業機器から家電や情報端末、自動車用機器まであらゆる電子機器に搭載される。特許文献１には、従来の半導体装置が開示されている。特許文献１に記載の半導体装置は、複数の半導体素子（１０）、およびこれら半導体素子を覆う封止樹脂（７０）を備えている。複数の半導体素子（１０）の各々は、ＳｉＣを構成材料とするスイッチング素子である。複数の半導体素子（１０）は、複数の半導体素子１０Ａ（第１スイッチング素子）および複数の半導体素子１０Ｂ（第２スイッチング素子）を含んでいる。上記従来の半導体装置において、複数の半導体素子１０Ａは上アーム回路を構成し、複数の半導体素子１０Ｂは下アーム回路を構成する。上アーム回路において、複数の半導体素子１０Ａは互いに並列に接続され、下アーム回路において、複数の半導体素子１０Ｂは互いに並列に接続される。複数の半導体素子１０Ａと複数の半導体素子１０Ｂとは、直列に接続されている。ＳｉＣを構成材料とする半導体素子は大面積化が困難であるため、特許文献１に記載された半導体装置のように、当該半導体装置に要求される電流容量に応じて、複数ずつの半導体素子１０Ａ，１０Ｂがそれぞれ並列して内蔵される。 Conventionally, semiconductor devices including power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are known. Such semiconductor devices are installed in all kinds of electronic equipment, from industrial equipment to home appliances, information terminals, and automobile equipment. Patent Document 1 discloses a conventional semiconductor device. The semiconductor device described in Patent Document 1 includes a plurality of semiconductor elements (10) and a sealing resin (70) that covers these semiconductor elements. Each of the plurality of semiconductor elements (10) is a switching element made of SiC. The plurality of semiconductor elements (10) include a plurality of semiconductor elements 10A (first switching element) and a plurality of semiconductor elements 10B (second switching element). In the conventional semiconductor device described above, the plurality of semiconductor elements 10A constitute an upper arm circuit, and the plurality of semiconductor elements 10B constitute a lower arm circuit. In the upper arm circuit, the plurality of semiconductor elements 10A are connected in parallel with each other, and in the lower arm circuit, the plurality of semiconductor elements 10B are connected in parallel with each other. The plurality of semiconductor elements 10A and the plurality of semiconductor elements 10B are connected in series. Since it is difficult to increase the area of a semiconductor element using SiC as a constituent material, as in the semiconductor device described in Patent Document 1, a plurality of semiconductor elements 10A are required depending on the current capacity required for the semiconductor device. , 10B are built in parallel.
　しかしながら、上記従来の半導体装置の構成によれば、並列された複数ずつの半導体素子１０Ａ，１０Ｂそれぞれにおいて熱干渉が生じるおそれがあり、放熱性の低下が懸念される。また、半導体装置において要求される電流容量に応じて、内蔵する半導体素子１０Ａ，１０Ｂの数量を変える必要がある。これに対応するには、半導体装置の製品種類を増やす必要があり、製造コストの上昇を招くことになる。 However, according to the configuration of the conventional semiconductor device described above, there is a risk that thermal interference may occur in each of the plurality of semiconductor elements 10A and 10B arranged in parallel, and there is a concern that heat dissipation performance may deteriorate. Furthermore, it is necessary to change the number of built-in semiconductor elements 10A and 10B depending on the current capacity required of the semiconductor device. To cope with this, it is necessary to increase the number of semiconductor device products, which leads to an increase in manufacturing costs.
国際公開第２０２０／１０５４７６号International Publication No. 2020/105476
　本開示は、従来より改良が施された半導体装置を提供することを一の課題とする。特に本開示は、上記した事情に鑑み、放熱性を改善するとともに、様々な電流容量に対応させるのに適した半導体装置を提供することをその一の課題とする。 An object of the present disclosure is to provide a semiconductor device that is improved over the conventional semiconductor device. Particularly, in view of the above-mentioned circumstances, one object of the present disclosure is to provide a semiconductor device that improves heat dissipation and is suitable for accommodating various current capacities.
　本開示の第１の側面によって提供される半導体装置は、２つのみのスイッチング素子と、前記２つのみのスイッチング素子を覆う封止樹脂と、を備える。前記２つのみのスイッチング素子は、一方が第１スイッチング素子、他方が第２スイッチング素子である。前記第１スイッチング素子および前記第２スイッチング素子の各々は、ＳｉＣを構成材料として含む。前記第１スイッチング素子と前記第２スイッチング素子とは、前記第１スイッチング素子を上アーム、前記第２スイッチング素子を下アームとして、直列に接続されている。 A semiconductor device provided by the first aspect of the present disclosure includes only two switching elements and a sealing resin that covers the only two switching elements. One of the only two switching elements is a first switching element and the other is a second switching element. Each of the first switching element and the second switching element includes SiC as a constituent material. The first switching element and the second switching element are connected in series, with the first switching element serving as an upper arm and the second switching element serving as a lower arm.
　本開示の第２の側面によって提供される半導体装置ユニットは、本開示の第１の側面に係る複数の半導体装置を備える。前記複数の半導体装置は互いに組み合わされている。 A semiconductor device unit provided by the second aspect of the present disclosure includes a plurality of semiconductor devices according to the first aspect of the present disclosure. The plurality of semiconductor devices are combined with each other.
　上記構成によれば、放熱性を改善するとともに、様々な電流容量に対応することが可能である。 According to the above configuration, it is possible to improve heat dissipation and support various current capacities.
　本開示のその他の特徴および利点は、添付図面を参照して以下に行う詳細な説明によって、より明らかとなろう。 Other features and advantages of the present disclosure will become more apparent from the detailed description given below with reference to the accompanying drawings.
図１は、本開示の第１実施形態に係る半導体装置を示す斜視図である。FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. 図２は、本開示の第１実施形態に係る半導体装置を示し、背面側から見た斜視図である。FIG. 2 is a perspective view of the semiconductor device according to the first embodiment of the present disclosure, viewed from the back side. 図３は、本開示の第１実施形態に係る半導体装置を示す平面図であり、封止樹脂を想像線で示した図である。FIG. 3 is a plan view showing the semiconductor device according to the first embodiment of the present disclosure, in which the sealing resin is shown with imaginary lines. 図４は、図３の平面図において、第３導通部材を省略した図である。FIG. 4 is a plan view of FIG. 3 with the third conductive member omitted. 図５は、本開示の第１実施形態に係る半導体装置を示す正面図であり、封止樹脂を想像線で示した図である。FIG. 5 is a front view showing the semiconductor device according to the first embodiment of the present disclosure, in which the sealing resin is shown with imaginary lines. 図６は、図３のＶＩ－ＶＩ線に沿う断面図である。FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 図７は、本開示の第１実施形態に係る半導体装置の回路構成を示す図である。FIG. 7 is a diagram showing a circuit configuration of a semiconductor device according to the first embodiment of the present disclosure. 図８は、本開示の第１実施形態に係る半導体装置を複数備えた半導体装置ユニットを示す斜視図である。FIG. 8 is a perspective view showing a semiconductor device unit including a plurality of semiconductor devices according to the first embodiment of the present disclosure. 図９は、第１実施形態の第１変形例に係る半導体装置を示す斜視図である。FIG. 9 is a perspective view showing a semiconductor device according to a first modification of the first embodiment. 図１０は、第１実施形態の第１変形例に係る半導体装置を示す正面図であり、封止樹脂を想像線で示した図である。FIG. 10 is a front view showing the semiconductor device according to the first modification of the first embodiment, and shows the sealing resin with imaginary lines. 図１１は、第１実施形態の第２変形例に係る半導体装置を示す斜視図である。FIG. 11 is a perspective view showing a semiconductor device according to a second modification of the first embodiment. 図１２は、第１実施形態の第２変形例に係る半導体装置を示す正面図であり、封止樹脂を想像線で示した図である。FIG. 12 is a front view showing a semiconductor device according to a second modification of the first embodiment, and shows the sealing resin with imaginary lines. 図１３は、第１実施形態の第３変形例に係る半導体装置を示す斜視図である。FIG. 13 is a perspective view showing a semiconductor device according to a third modification of the first embodiment. 図１４は、第１実施形態の第３変形例に係る半導体装置を示す正面図であり、封止樹脂を想像線で示した図である。FIG. 14 is a front view showing a semiconductor device according to a third modification of the first embodiment, and shows the sealing resin with imaginary lines. 図１５は、第１実施形態の第３変形例に係る半導体装置を複数備えた半導体装置ユニットを示す斜視図である。FIG. 15 is a perspective view showing a semiconductor device unit including a plurality of semiconductor devices according to a third modification of the first embodiment. 図１６は、本開示の第２実施形態に係る半導体装置を示す斜視図である。FIG. 16 is a perspective view showing a semiconductor device according to a second embodiment of the present disclosure. 図１７は、本開示の第２実施形態に係る半導体装置を示す右側面図である。FIG. 17 is a right side view showing a semiconductor device according to a second embodiment of the present disclosure. 図１８は、本開示の第２実施形態に係る半導体装置を複数備えた半導体装置ユニットを示す斜視図である。FIG. 18 is a perspective view showing a semiconductor device unit including a plurality of semiconductor devices according to the second embodiment of the present disclosure. 図１９は、本開示の第３実施形態に係る半導体装置を示す斜視図である。FIG. 19 is a perspective view showing a semiconductor device according to a third embodiment of the present disclosure. 図２０は、本開示の第３実施形態に係る半導体装置を複数備えた半導体装置ユニットを示す斜視図である。FIG. 20 is a perspective view showing a semiconductor device unit including a plurality of semiconductor devices according to a third embodiment of the present disclosure. 図２１は、本開示の第４実施形態に係る半導体装置を示す斜視図である。FIG. 21 is a perspective view showing a semiconductor device according to a fourth embodiment of the present disclosure. 図２２は、本開示の第４実施形態に係る半導体装置を複数備えた半導体装置ユニットの一例を示す斜視図である。FIG. 22 is a perspective view showing an example of a semiconductor device unit including a plurality of semiconductor devices according to the fourth embodiment of the present disclosure. 図２３は、本開示の第４実施形態に係る半導体装置を複数備えた半導体装置ユニットの他の例を示す斜視図である。FIG. 23 is a perspective view showing another example of a semiconductor device unit including a plurality of semiconductor devices according to the fourth embodiment of the present disclosure. 図２４は、本開示の第５実施形態に係る半導体装置を示す斜視図である。FIG. 24 is a perspective view showing a semiconductor device according to a fifth embodiment of the present disclosure. 図２５は、本開示の第５実施形態に係る半導体装置を示し、背面側から見た斜視図である。FIG. 25 is a perspective view of a semiconductor device according to a fifth embodiment of the present disclosure, viewed from the back side. 図２６は、第５実施形態の変形例に係る半導体装置を示す斜視図である。FIG. 26 is a perspective view showing a semiconductor device according to a modification of the fifth embodiment. 図２７は、第５実施形態の変形例に係る半導体装置を示し、背面側から見た斜視図である。FIG. 27 shows a semiconductor device according to a modification of the fifth embodiment, and is a perspective view seen from the back side. 図２８は、本開示に係る半導体装置の他の構成例を示す回路構成図である。FIG. 28 is a circuit configuration diagram showing another configuration example of a semiconductor device according to the present disclosure.
　以下、本開示の好ましい実施の形態につき、図面を参照して具体的に説明する。 Hereinafter, preferred embodiments of the present disclosure will be specifically described with reference to the drawings.
　本開示における「第１」、「第２」、「第３」等の用語は、単にラベルとして用いたものであり、必ずしもそれらの対象物に順列を付することを意図していない。 Terms such as "first," "second," and "third" in the present disclosure are merely used as labels and are not necessarily intended to attach any permutation to those objects.
　本開示において、「ある物Ａがある物Ｂに形成されている」および「ある物Ａがある物Ｂ上に形成されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接形成されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに形成されていること」を含む。同様に、「ある物Ａがある物Ｂに配置されている」および「ある物Ａがある物Ｂ上に配置されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接配置されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに配置されていること」を含む。同様に、「ある物Ａがある物Ｂ上に位置している」とは、特段の断りのない限り、「ある物Ａがある物Ｂに接して、ある物Ａがある物Ｂ上に位置していること」、および、「ある物Ａとある物Ｂとの間に他の物が介在しつつ、ある物Ａがある物Ｂ上に位置していること」を含む。また、「ある物Ａがある物Ｂにある方向に見て重なる」とは、特段の断りのない限り、「ある物Ａがある物Ｂのすべてに重なること」、および、「ある物Ａがある物Ｂの一部に重なること」を含む。また、本開示において「ある面Ａが方向Ｂ（の一方側または他方側）を向く」とは、面Ａの方向Ｂに対する角度が９０°である場合に限定されず、面Ａが方向Ｂに対して傾いている場合を含む。また「ある物Ａがある物Ｂに支持されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接支持されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに支持されていること」を含む。 In this disclosure, "a thing A is formed on a thing B" and "a thing A is formed on a thing B" mean "a thing A is formed on a thing B" unless otherwise specified. "It is formed directly on object B," and "It is formed on object B, with another object interposed between object A and object B." Similarly, "something A is placed on something B" and "something A is placed on something B" mean "something A is placed on something B" unless otherwise specified. This includes ``directly placed on object B'' and ``placed on object B with another object interposed between object A and object B.'' Similarly, "a certain object A is located on a certain object B" means, unless otherwise specified, "a certain object A is in contact with a certain object B, and a certain object A is located on a certain object B." ``The fact that a certain thing A is located on a certain thing B while another thing is interposed between the certain thing A and the certain thing B.'' In addition, "a certain object A overlaps a certain object B when viewed in a certain direction" means, unless otherwise specified, "a certain object A overlaps all of a certain object B" and "a certain object A overlaps with a certain object B". This includes "overlapping a part of something B." Furthermore, in the present disclosure, "a certain surface A faces (one side or the other side of) the direction B" is not limited to the case where the angle of the surface A with respect to the direction B is 90 degrees; Including cases where it is tilted to the opposite direction. Furthermore, "something A is supported by something B" means "something A is directly supported by something B," and "something A is supported by something B," unless otherwise specified. This includes "an object A being supported by an object B while another object is interposed between it and object B."
　第１実施形態：
　図１～図７は、本開示の第１実施形態に係る半導体装置を示している。本実施形態の半導体装置Ａ１０は、２つのスイッチング素子１０と、導電支持体２と、支持基板３と、複数の制御端子４と、第１導通部材５１と、第２導通部材５２と、第３導通部材５３と、第４導通部材５４と、封止樹脂７と、第１結合形状Ｊ１と、第２結合形状Ｊ２と、を備えている。 First embodiment:
1 to 7 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A10 of this embodiment includes two switching elements 10, a conductive support 2, a support substrate 3, a plurality of control terminals 4, a first conduction member 51, a second conduction member 52, and a third conduction member 51. It includes a conductive member 53, a fourth conductive member 54, a sealing resin 7, a first joint shape J1, and a second joint shape J2.
　図１は、半導体装置Ａ１０を示す斜視図である。図２は、半導体装置Ａ１０を示す斜視図であり、背面側から見た図である。図３は、半導体装置Ａ１０を示す平面図であり、封止樹脂７を想像線で示した図である。図４は、図３の平面図において、第３導通部材５３を省略した図である。図５は、半導体装置Ａ１０を示す正面図であり、封止樹脂７を想像線で示した図である。図６は、図３のＶＩ－ＶＩ線に沿う断面図である。図７は、半導体装置Ａ１０の回路構成を示す図である。 FIG. 1 is a perspective view showing the semiconductor device A10. FIG. 2 is a perspective view of the semiconductor device A10, viewed from the back side. FIG. 3 is a plan view showing the semiconductor device A10, in which the sealing resin 7 is shown with imaginary lines. FIG. 4 is a plan view of FIG. 3 with the third conductive member 53 omitted. FIG. 5 is a front view of the semiconductor device A10, in which the sealing resin 7 is shown with imaginary lines. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. FIG. 7 is a diagram showing the circuit configuration of the semiconductor device A10.
　説明の便宜上、互いに直交する３つの方向を、ｘ方向、ｙ方向、ｚ方向とする。ｚ方向は、半導体装置Ａ１０の厚さ方向である。ｘ方向は、半導体装置Ａ１０の平面図（図３参照）における左右方向である。ｙ方向は、半導体装置Ａ１０の平面図（図３参照）における上下方向である。ｘ方向の一方をｘ１方向、ｘ方向の他方をｘ２方向とする。同様に、ｙ方向の一方をｙ１方向、ｙ方向の他方をｙ２方向とし、ｚ方向の一方をｚ１方向、ｚ方向の他方をｚ２方向とする。以下の説明において、「平面視」とは、ｚ方向に見たときをいう。また、ｚ１方向を上、ｚ２方向を下という場合がある。ｚ方向が、本開示の「厚さ方向」に相当し、ｘ方向が、本開示の「第１方向」に相当し、ｙ方向が、本開示の「第２方向」に相当する。また、ｘ１方向が本開示の「第１方向の一方側」に相当し、ｘ２方向が本開示の「第１方向の他方側」に相当し、ｙ１方向が本開示の「第２方向の一方側」に相当し、ｙ２方向が本開示の「第２方向の他方側」に相当し、ｚ１方向が本開示の「厚さ方向の一方側」に相当し、ｚ２方向が本開示の「厚さ方向の他方側」に相当する。 For convenience of explanation, the three directions that are orthogonal to each other are referred to as the x direction, the y direction, and the z direction. The z direction is the thickness direction of the semiconductor device A10. The x direction is the left-right direction in the plan view of the semiconductor device A10 (see FIG. 3). The y direction is the vertical direction in the plan view of the semiconductor device A10 (see FIG. 3). One of the x directions is called the x1 direction, and the other x direction is called the x2 direction. Similarly, one of the y-directions is the y1 direction, the other of the y-directions is the y2-direction, one of the z-directions is the z1-direction, and the other z-direction is the z2-direction. In the following description, "planar view" refers to when viewed in the z direction. Further, the z1 direction is sometimes referred to as top, and the z2 direction is sometimes referred to as bottom. The z direction corresponds to the "thickness direction" of the present disclosure, the x direction corresponds to the "first direction" of the present disclosure, and the y direction corresponds to the "second direction" of the present disclosure. Further, the x1 direction corresponds to "one side of the first direction" of the present disclosure, the x2 direction corresponds to "the other side of the first direction" of the present disclosure, and the y1 direction corresponds to "one side of the second direction" of the present disclosure. The y2 direction corresponds to the "other side in the second direction" of the present disclosure, the z1 direction corresponds to "one side in the thickness direction" of the present disclosure, and the z2 direction corresponds to the "other side in the thickness direction" of the present disclosure. corresponds to "the other side in the horizontal direction".
　２つのスイッチング素子１０はそれぞれ、半導体装置Ａ１０の機能中枢となる電子部品である。半導体装置Ａ１０は、２つのみのスイッチング素子１０を内蔵している。各スイッチング素子１０の構成材料は、ＳｉＣ（炭化ケイ素）を主とする半導体材料である。各スイッチング素子１０は、たとえば、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）などのスイッチング機能を有するパワー半導体チップである。半導体装置Ａ１０の説明においては、２つのスイッチング素子１０は、同一素子である。各スイッチング素子１０は、たとえばｎチャネル型のＭＯＳＦＥＴであるが、ｐチャネル型のＭＯＳＦＥＴであってもよい。 Each of the two switching elements 10 is an electronic component that becomes the functional center of the semiconductor device A10. The semiconductor device A10 includes only two switching elements 10. The constituent material of each switching element 10 is a semiconductor material mainly composed of SiC (silicon carbide). Each switching element 10 is, for example, a power semiconductor chip having a switching function, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In the description of the semiconductor device A10, the two switching elements 10 are the same element. Each switching element 10 is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.
　各スイッチング素子１０は、図６に示すように、素子主面１０１および素子裏面１０２を有する。各スイッチング素子１０において、素子主面１０１と素子裏面１０２とはｚ方向に離隔する。素子主面１０１は、ｚ１方向を向き、素子裏面１０２は、ｚ２方向を向く。 Each switching element 10 has an element main surface 101 and an element back surface 102, as shown in FIG. In each switching element 10, the element main surface 101 and the element back surface 102 are separated in the z direction. The element main surface 101 faces the z1 direction, and the element back surface 102 faces the z2 direction.
　２つのスイッチング素子１０は、一方が第１スイッチング素子１０Ａであり、他方が第２スイッチング素子１０Ｂである。半導体装置Ａ１０は、図７に示すように、ハーフブリッジ型のスイッチング回路として構成される。当該スイッチング回路において、第１スイッチング素子１０Ａを上アーム、第２スイッチング素子１０Ｂを下アームとして、直列に接続されている。 One of the two switching elements 10 is the first switching element 10A, and the other is the second switching element 10B. As shown in FIG. 7, the semiconductor device A10 is configured as a half-bridge switching circuit. In the switching circuit, the first switching element 10A serves as an upper arm, and the second switching element 10B serves as a lower arm, which are connected in series.
　第１スイッチング素子１０Ａは、図３～図６に示すように、導電支持体２に搭載されている。第１スイッチング素子１０Ａは、導電性接合材１９を介して、導電支持体２（後述の第１導電部２Ａ）に導通接合されている。第１スイッチング素子１０Ａは、第１導電部２Ａに接合された際、素子裏面１０２が第１導電部２Ａに対向する。第２スイッチング素子１０Ｂは、導電支持体２に搭載されている。第２スイッチング素子１０Ｂは、導電性接合材１９を介して、導電支持体２（後述の第２導電部２Ｂ）に導通接合されている。第２スイッチング素子１０Ｂは、第２導電部２Ｂに接合された際、素子裏面１０２が第２導電部２Ｂに対向する。 The first switching element 10A is mounted on the conductive support 2, as shown in FIGS. 3 to 6. The first switching element 10A is conductively bonded to the conductive support 2 (first conductive portion 2A to be described later) via a conductive bonding material 19. When the first switching element 10A is joined to the first conductive part 2A, the element back surface 102 faces the first conductive part 2A. The second switching element 10B is mounted on the conductive support 2. The second switching element 10B is conductively bonded to the conductive support 2 (second conductive portion 2B to be described later) via a conductive bonding material 19. When the second switching element 10B is joined to the second conductive part 2B, the element back surface 102 faces the second conductive part 2B.
　２つのスイッチング素子１０（第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂ）はそれぞれ、第１主面電極１１、第２主面電極１２および裏面電極１３を有する。以下で説明する第１主面電極１１、第２主面電極１２および裏面電極１３の構成は、各スイッチング素子１０において共通する。第１主面電極１１および第２主面電極１２は、素子主面１０１に設けられている。第１主面電極１１および第２主面電極１２は、図示しない絶縁膜により絶縁されている。裏面電極１３は、素子裏面１０２に設けられている。 The two switching elements 10 (first switching element 10A and second switching element 10B) each have a first main surface electrode 11, a second main surface electrode 12, and a back electrode 13. The configurations of the first main surface electrode 11, second main surface electrode 12, and back surface electrode 13 described below are common to each switching element 10. The first main surface electrode 11 and the second main surface electrode 12 are provided on the element main surface 101. The first main surface electrode 11 and the second main surface electrode 12 are insulated by an insulating film (not shown). The back electrode 13 is provided on the back surface 102 of the element.
　第１主面電極１１は、たとえばゲート電極であって、スイッチング素子１０を駆動させるための駆動信号（たとえばゲート電圧）が入力される。各スイッチング素子１０において、第２主面電極１２は、たとえばソース電極であって、ソース電流が流れる。裏面電極１３、たとえばドレイン電極であって、ドレイン電流が流れる。裏面電極１３は、素子裏面１０２の略全域を覆っている。裏面電極１３、たとえばＡｇ（銀）めっきにより構成される。 The first principal surface electrode 11 is, for example, a gate electrode, and a drive signal (eg, gate voltage) for driving the switching element 10 is input thereto. In each switching element 10, the second main surface electrode 12 is, for example, a source electrode, through which a source current flows. The back electrode 13 is, for example, a drain electrode, through which a drain current flows. The back electrode 13 covers substantially the entire area of the back surface 102 of the element. The back electrode 13 is made of, for example, Ag (silver) plating.
　各スイッチング素子１０は、第１主面電極１１（ゲート電極）に駆動信号（ゲート電圧）が入力されると、この駆動信号に応じて、導通状態と遮断状態とが切り替わる。導通状態では、裏面電極１３（ドレイン電極）から第２主面電極１２（ソース電極）に電流が流れ、遮断状態では、この電流が流れない。各スイッチング素子１０は、スイッチング動作を行う。半導体装置Ａ１０は、第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂのスイッチング機能により、後述の第１主端子５１２と第３主端子５３２とに入力される直流電圧をたとえば交流電圧に変換して、第２主端子５２２から交流電圧を出力する。 When a drive signal (gate voltage) is input to the first main surface electrode 11 (gate electrode), each switching element 10 switches between a conductive state and a cutoff state in accordance with this drive signal. In a conductive state, a current flows from the back electrode 13 (drain electrode) to the second main surface electrode 12 (source electrode), and in a cutoff state, this current does not flow. Each switching element 10 performs a switching operation. The semiconductor device A10 converts, for example, a DC voltage input to a first main terminal 512 and a third main terminal 532, which will be described later, into an AC voltage using the switching functions of the first switching element 10A and the second switching element 10B. AC voltage is output from the second main terminal 522.
　導電支持体２は、２つのスイッチング素子１０（第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂ）を支持する。導電支持体２は、支持基板３上に導電性接合材２９を介して接合されている。導電支持体２は、第１導通部材５１、第２導通部材５２、第３導通部材５３および第４導通部材５４とともに、２つのスイッチング素子１０によってスイッチングされる主電流の経路を構成する。 The conductive support 2 supports two switching elements 10 (first switching element 10A and second switching element 10B). The conductive support body 2 is bonded onto the support substrate 3 with a conductive bonding material 29 interposed therebetween. The conductive support 2, together with the first conductive member 51, the second conductive member 52, the third conductive member 53, and the fourth conductive member 54, constitutes a path for the main current switched by the two switching elements 10.
　導電支持体２は、第１導電部２Ａおよび第２導電部２Ｂを含む。第１導電部２Ａおよび第２導電部２Ｂはそれぞれ、金属製の板状ブロック部材である。この金属は、たとえばＣｕ（銅）あるいはＣｕ合金である。第１導電部２Ａおよび第２導電部２Ｂは、２つのスイッチング素子１０への導通経路を構成している。第１導電部２Ａおよび第２導電部２Ｂはそれぞれが、図６に示すように、導電性接合材２９を介して支持基板３上に接合されている。第１導電部２Ａには、導電性接合材１９を介して第１スイッチング素子１０Ａが接合されている。第２導電部２Ｂには、導電性接合材１９を介して第２スイッチング素子１０Ｂが接合されている。導電性接合材１９および導電性接合材２９の構成材料は特に限定されず、たとえばはんだ、金属ペースト材、あるいは、焼結金属などである。 The conductive support 2 includes a first conductive part 2A and a second conductive part 2B. The first conductive part 2A and the second conductive part 2B are each plate-shaped block members made of metal. This metal is, for example, Cu (copper) or a Cu alloy. The first conductive portion 2A and the second conductive portion 2B constitute a conduction path to the two switching elements 10. The first conductive part 2A and the second conductive part 2B are each bonded onto the support substrate 3 via a conductive bonding material 29, as shown in FIG. A first switching element 10A is bonded to the first conductive portion 2A via a conductive bonding material 19. A second switching element 10B is bonded to the second conductive portion 2B via a conductive bonding material 19. The constituent materials of the conductive bonding material 19 and the conductive bonding material 29 are not particularly limited, and include, for example, solder, metal paste material, or sintered metal.
　第１導電部２Ａおよび第２導電部２Ｂは、図３～図６に示すように、ｘ方向に互いに離隔する。これらの図に示す例では、第１導電部２Ａは、第２導電部２Ｂよりもｘ１方向に位置する。第１導電部２Ａおよび第２導電部２Ｂはそれぞれ、たとえば平面視矩形状である。第１導電部２Ａおよび第２導電部２Ｂそれぞれの厚さ（ｚ方向の寸法）は、たとえば２．０ｍｍ～５．０ｍｍ（好ましくは３．０ｍｍ程度）である。 The first conductive part 2A and the second conductive part 2B are spaced apart from each other in the x direction, as shown in FIGS. 3 to 6. In the examples shown in these figures, the first conductive part 2A is located further in the x1 direction than the second conductive part 2B. The first conductive portion 2A and the second conductive portion 2B each have, for example, a rectangular shape in plan view. The thickness (dimension in the z direction) of each of the first conductive part 2A and the second conductive part 2B is, for example, 2.0 mm to 5.0 mm (preferably about 3.0 mm).
　導電支持体２は、主面２０１および裏面２０２を有する。主面２０１および裏面２０２は、図４、図５に示すように、ｚ方向に離隔する。主面２０１は、ｚ１方向を向き、裏面２０２は、ｚ２方向を向く。主面２０１は、第１導電部２Ａの上面と第２導電部２Ｂの上面とを合わせたものである。裏面２０２は、第１導電部２Ａの下面と第２導電部２Ｂの下面とを合わせたものである。裏面２０２は、支持基板３に対向するように支持基板３に接合されている。 The conductive support 2 has a main surface 201 and a back surface 202. The main surface 201 and the back surface 202 are separated in the z direction, as shown in FIGS. 4 and 5. The main surface 201 faces in the z1 direction, and the back surface 202 faces in the z2 direction. The main surface 201 is the sum of the upper surface of the first conductive part 2A and the upper surface of the second conductive part 2B. The back surface 202 is a combination of the lower surface of the first conductive section 2A and the lower surface of the second conductive section 2B. The back surface 202 is joined to the support substrate 3 so as to face the support substrate 3.
　支持基板３は、導電支持体２を支持する。支持基板３は、たとえばＡＭＢ（Active Metal Brazing）基板で構成される。支持基板３は、絶縁層３１、第１金属層３２および第２金属層３３を含む。 The support substrate 3 supports the conductive support 2. The support substrate 3 is composed of, for example, an AMB (Active Metal Brazing) substrate. Support substrate 3 includes an insulating layer 31, a first metal layer 32, and a second metal layer 33.
　絶縁層３１は、たとえば熱伝導性の優れたセラミックスである。このようなセラミックスとしては、たとえばＳｉＮ（窒化ケイ素）がある。絶縁層３１は、セラミックスに限定されず、絶縁樹脂シートなどであってもよい。絶縁層３１は、たとえば平面視矩形状である。 The insulating layer 31 is made of, for example, ceramics with excellent thermal conductivity. Such ceramics include, for example, SiN (silicon nitride). The insulating layer 31 is not limited to ceramics, and may be an insulating resin sheet or the like. The insulating layer 31 has, for example, a rectangular shape in plan view.
　第１金属層３２は、絶縁層３１の上面（ｚ１方向を向く面）に形成されている。第１金属層３２の構成材料は、たとえばＣｕを含む。当該構成材料はＣｕではなくＡｌ（アルミニウム）を含んでいてもよい。第１金属層３２は、第１部分３２Ａおよび第２部分３２Ｂを含む。第１部分３２Ａおよび第２部分３２Ｂは、ｘ方向に離隔する。第１部分３２Ａは、第２部分３２Ｂよりもｘ１方向に位置する。第１部分３２Ａは、第１導電部２Ａが接合され、第１導電部２Ａを支持する。第２部分３２Ｂは、第２導電部２Ｂが接合され、第２導電部２Ｂを支持する。第１部分３２Ａおよび第２部分３２Ｂはそれぞれ、平面視矩形状である。第１部分３２Ａおよび第２部分３２Ｂはそれぞれ、第１導電部２Ａおよび第２導電部２Ｂに対応した形状とされている。 The first metal layer 32 is formed on the upper surface of the insulating layer 31 (the surface facing the z1 direction). The constituent material of the first metal layer 32 includes, for example, Cu. The constituent material may include Al (aluminum) instead of Cu. The first metal layer 32 includes a first portion 32A and a second portion 32B. The first portion 32A and the second portion 32B are spaced apart in the x direction. The first portion 32A is located further in the x1 direction than the second portion 32B. The first portion 32A is joined to the first conductive portion 2A and supports the first conductive portion 2A. The second portion 32B is joined to the second conductive portion 2B and supports the second conductive portion 2B. The first portion 32A and the second portion 32B each have a rectangular shape in plan view. The first portion 32A and the second portion 32B have shapes corresponding to the first conductive portion 2A and the second conductive portion 2B, respectively.
　第２金属層３３は、絶縁層３１の下面（ｚ２方向を向く面）に形成されている。第２金属層３３の構成材料は、第１金属層３２の構成材料と同じである。第２金属層３３の下面（後述の底面３０２）は、図６に示す例では、たとえば封止樹脂７から露出する。当該下面は、封止樹脂７から露出せず、封止樹脂７に覆われていてもよい。第２金属層３３は、平面視において、第１部分３２Ａおよび第２部分３２Ｂの双方に重なる。 The second metal layer 33 is formed on the lower surface of the insulating layer 31 (the surface facing the z2 direction). The constituent material of the second metal layer 33 is the same as that of the first metal layer 32. In the example shown in FIG. 6, the lower surface (bottom surface 302 described below) of the second metal layer 33 is exposed from the sealing resin 7, for example. The lower surface may not be exposed from the sealing resin 7 and may be covered with the sealing resin 7. The second metal layer 33 overlaps both the first portion 32A and the second portion 32B in plan view.
　支持基板３は、図６に示すように、支持面３０１および底面３０２を有する。支持面３０１と底面３０２とは、ｚ方向に離隔する。支持面３０１は、ｚ１方向を向き、底面３０２は、ｚ２方向を向く。底面３０２は、封止樹脂７から露出する。支持面３０１は、第１金属層３２の上面であり、第１部分３２Ａの上面と第２部分３２Ｂの上面とをあわせたものである。支持面３０１は、導電支持体２に対向し、導電支持体２（裏面２０２）が接合されている。底面３０２は、第２金属層３３の下面である。底面３０２には、図示しない放熱部材（たとえばヒートシンク）などが取り付け可能である。支持基板３のｚ方向の寸法（支持面３０１から底面３０２までのｚ方向に沿う距離）は、たとえば０．０１ｍｍ～２．０ｍｍである。 The support substrate 3 has a support surface 301 and a bottom surface 302, as shown in FIG. The support surface 301 and the bottom surface 302 are separated from each other in the z direction. The support surface 301 faces the z1 direction, and the bottom surface 302 faces the z2 direction. The bottom surface 302 is exposed from the sealing resin 7. The support surface 301 is the upper surface of the first metal layer 32, and is the sum of the upper surface of the first portion 32A and the upper surface of the second portion 32B. The support surface 301 faces the conductive support 2, and the conductive support 2 (back surface 202) is joined to the support surface 301. The bottom surface 302 is the lower surface of the second metal layer 33. A heat dissipating member (for example, a heat sink), etc. (not shown) can be attached to the bottom surface 302. The dimension of the support substrate 3 in the z direction (the distance along the z direction from the support surface 301 to the bottom surface 302) is, for example, 0.01 mm to 2.0 mm.
　第１導通部材５１、第２導通部材５２、第３導通部材５３、第４導通部材５４の各々は、２つのスイッチング素子１０によってスイッチングされる主電流の経路を構成する。 Each of the first conductive member 51, the second conductive member 52, the third conductive member 53, and the fourth conductive member 54 constitutes a path for the main current switched by the two switching elements 10.
　図３～図６に示すように、第１導通部材５１は、接続部５１１および第１主端子５１２を有する。接続部５１１は、導電性接合材５９を介して第１導電部２Ａに接合されている。第１主端子５１２は、封止樹脂７から露出しており、封止樹脂７に対してｘ１方向に位置する。第２導通部材５２は、接続部５２１および第２主端子５２２を有する。接続部５２１は、導電性接合材５９を介して第２導電部２Ｂに接合されている。第２主端子５２２は、封止樹脂７から露出しており、封止樹脂７に対してｘ２方向に位置する。 As shown in FIGS. 3 to 6, the first conductive member 51 has a connecting portion 511 and a first main terminal 512. The connecting portion 511 is bonded to the first conductive portion 2A via a conductive bonding material 59. The first main terminal 512 is exposed from the sealing resin 7 and is located in the x1 direction with respect to the sealing resin 7. The second conductive member 52 has a connecting portion 521 and a second main terminal 522. The connecting portion 521 is bonded to the second conductive portion 2B via a conductive bonding material 59. The second main terminal 522 is exposed from the sealing resin 7 and is located in the x2 direction with respect to the sealing resin 7.
　第３導通部材５３は、接続部５３１および第３主端子５３２を有する。接続部５３１は、導電性接合材５９を介して、第２スイッチング素子１０Ｂの第２主面電極１２（ソース電極）に接合されている。第３主端子５３２は、封止樹脂７から露出しており、封止樹脂７に対してｘ１方向に位置する。また、第３主端子５３２は、第１主端子５１２に対してｙ１方向に位置し、ｙ方向に見て第１主端子５１２と重なっている。 The third conductive member 53 has a connecting portion 531 and a third main terminal 532. The connecting portion 531 is bonded to the second main surface electrode 12 (source electrode) of the second switching element 10B via a conductive bonding material 59. The third main terminal 532 is exposed from the sealing resin 7 and is located in the x1 direction with respect to the sealing resin 7. Further, the third main terminal 532 is located in the y1 direction with respect to the first main terminal 512, and overlaps with the first main terminal 512 when viewed in the y direction.
　第４導通部材５４は、第１スイッチング素子１０Ａの第２主面電極１２（ソース電極）と第２導電部２Ｂとに接続され、第１スイッチング素子１０Ａの第２主面電極１２と第２導電部２Ｂとを導通させる。第４導通部材５４と第１スイッチング素子１０Ａの第２主面電極１２とは、導電性接合材５９を介して接合される。なお、上記の導電性接合材５９の構成材料は特に限定されず、たとえばはんだ、金属ペースト材、あるいは、焼結金属などである。 The fourth conductive member 54 is connected to the second main surface electrode 12 (source electrode) of the first switching element 10A and the second conductive part 2B, and is connected to the second main surface electrode 12 of the first switching element 10A and the second conductive part 2B. The section 2B is electrically connected. The fourth conductive member 54 and the second main surface electrode 12 of the first switching element 10A are bonded via a conductive bonding material 59. Note that the constituent material of the conductive bonding material 59 is not particularly limited, and may be, for example, solder, metal paste material, or sintered metal.
　上記の第１主端子５１２および第３主端子５３２には、電力変換対象となる直流電圧が入力される。第１主端子５１２は正極（Ｐ端子）であり、第３主端子５３２は負極（Ｎ端子）である。第２主端子５２２から、第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂにより電力変換された交流電圧が出力される。第１主端子５１２は、第１導電部２Ａを介して第１スイッチング素子１０Ａの裏面電極１３（ドレイン電極）に導通する。第２主端子５２２は、第２導電部２Ｂを介して第２スイッチング素子１０Ｂの裏面電極１３（ドレイン電極）に導通する。第３主端子５３２は、第２スイッチング素子１０Ｂの第２主面電極１２（ソース電極）に導通する。第１主端子５１２、第２主端子５２２および第３主端子５３２は、「複数の主端子」の構成要素の一例である。 A DC voltage to be subjected to power conversion is input to the first main terminal 512 and the third main terminal 532 described above. The first main terminal 512 is a positive electrode (P terminal), and the third main terminal 532 is a negative electrode (N terminal). From the second main terminal 522, an AC voltage whose power has been converted by the first switching element 10A and the second switching element 10B is output. The first main terminal 512 is electrically connected to the back electrode 13 (drain electrode) of the first switching element 10A via the first conductive portion 2A. The second main terminal 522 is electrically connected to the back electrode 13 (drain electrode) of the second switching element 10B via the second conductive portion 2B. The third main terminal 532 is electrically connected to the second main surface electrode 12 (source electrode) of the second switching element 10B. The first main terminal 512, the second main terminal 522, and the third main terminal 532 are examples of components of "a plurality of main terminals."
　複数の制御端子４はそれぞれ、第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂを制御するためのピン状の端子である。複数の制御端子４は、複数の第１制御端子４１Ａ，４１Ｂおよび複数の第２制御端子４２Ａ，４２Ｂを含む。複数の第１制御端子４１Ａ，４１Ｂは、第１スイッチング素子１０Ａの制御などに用いられる。複数の第２制御端子４２Ａ，４２Ｂは、第２スイッチング素子１０Ｂの制御などに用いられる。 Each of the plurality of control terminals 4 is a pin-shaped terminal for controlling the first switching element 10A and the second switching element 10B. The plurality of control terminals 4 include a plurality of first control terminals 41A, 41B and a plurality of second control terminals 42A, 42B. The plurality of first control terminals 41A, 41B are used for controlling the first switching element 10A, etc. The plurality of second control terminals 42A, 42B are used for controlling the second switching element 10B.
　図１、図３～図５に示すように、複数の制御端子４の各々は、一部が封止樹脂７からｙ２方向に突出し、且つｚ１方向に延びている。複数の第１制御端子４１Ａ,４１Ｂは、複数の第２制御端子４２Ａ，４２Ｂに対して、ｘ１方向に位置する。 As shown in FIGS. 1 and 3 to 5, each of the plurality of control terminals 4 partially protrudes from the sealing resin 7 in the y2 direction and extends in the z1 direction. The plurality of first control terminals 41A, 41B are located in the x1 direction with respect to the plurality of second control terminals 42A, 42B.
　複数の第１制御端子４１Ａ，４１Ｂは、ｘ方向に間隔を隔てて配置されている。第１制御端子４１Ａは、第１スイッチング素子１０Ａの駆動信号入力用の端子（ゲート端子）である。第１制御端子４１Ａは、ワイヤ６１が接合されており、ワイヤ６１を介して第１スイッチング素子１０Ａの第１主面電極１１（ゲート電極）に導通する。第１制御端子４１Ａには、第１スイッチング素子１０Ａを駆動させるための駆動信号が入力される（たとえばゲート電圧が印加される）。第１制御端子４１Ｂは、第１スイッチング素子１０Ａのソース信号検出用の端子（ソースセンス端子）である。第１制御端子４１Ｂは、ワイヤ６２が接合されており、ワイヤ６２を介して第１スイッチング素子１０Ａの第２主面電極１２（ソース電極）に導通する。第１制御端子４１Ｂから、第１スイッチング素子１０Ａの第２主面電極１２（ソース電極）に印加される電圧（ソース電流に対応した電圧）が検出される。 The plurality of first control terminals 41A, 41B are arranged at intervals in the x direction. The first control terminal 41A is a terminal (gate terminal) for inputting a drive signal to the first switching element 10A. The first control terminal 41A is connected to a wire 61 and is electrically connected to the first main surface electrode 11 (gate electrode) of the first switching element 10A via the wire 61. A drive signal for driving the first switching element 10A is input to the first control terminal 41A (for example, a gate voltage is applied). The first control terminal 41B is a source signal detection terminal (source sense terminal) of the first switching element 10A. The first control terminal 41B is connected to a wire 62 and is electrically connected to the second main surface electrode 12 (source electrode) of the first switching element 10A via the wire 62. The voltage (voltage corresponding to the source current) applied to the second main surface electrode 12 (source electrode) of the first switching element 10A is detected from the first control terminal 41B.
　複数の第２制御端子４２Ａ，４２Ｂは、ｘ方向に間隔を隔てて配置されている。第２制御端子４２Ａは、第２スイッチング素子１０Ｂの駆動信号入力用の端子（ゲート端子）である。第２制御端子４２Ａは、ワイヤ６１が接合されており、ワイヤ６１を介して第２スイッチング素子１０Ｂの第１主面電極１１（ゲート電極）に導通する。第２制御端子４２Ａには、第２スイッチング素子１０Ｂを駆動させるための駆動信号が入力される（たとえばゲート電圧が印加される）。第２制御端子４２Ｂは、第２スイッチング素子１０Ｂのソース信号検出用の端子（ソースセンス端子）である。第２制御端子４２Ｂは、ワイヤ６２が接合されており、ワイヤ６２を介して第２スイッチング素子１０Ｂの第２主面電極１２（ソース電極）に導通する。第２制御端子４２Ｂから、第２スイッチング素子１０Ｂの第２主面電極１２（ソース電極）に印加される電圧（ソース電流に対応した電圧）が検出される。上記の各ワイヤ６１，６２は、たとえばボンディングワイヤである。各ワイヤ６１，６２の構成材料は、たとえばＡｕ（金）、ＡｌあるいはＣｕのいずれかを含む。 The plurality of second control terminals 42A, 42B are arranged at intervals in the x direction. The second control terminal 42A is a terminal (gate terminal) for inputting a drive signal to the second switching element 10B. The second control terminal 42A is connected to a wire 61 and is electrically connected to the first main surface electrode 11 (gate electrode) of the second switching element 10B via the wire 61. A drive signal for driving the second switching element 10B is input to the second control terminal 42A (for example, a gate voltage is applied). The second control terminal 42B is a source signal detection terminal (source sense terminal) of the second switching element 10B. The second control terminal 42B is connected to a wire 62 and is electrically connected to the second main surface electrode 12 (source electrode) of the second switching element 10B via the wire 62. A voltage (voltage corresponding to the source current) applied to the second main surface electrode 12 (source electrode) of the second switching element 10B is detected from the second control terminal 42B. Each of the wires 61 and 62 described above is, for example, a bonding wire. The constituent material of each wire 61, 62 includes, for example, Au (gold), Al, or Cu.
　封止樹脂７は、２つのスイッチング素子１０と、導電支持体２（第１導電部２Ａおよび第２導電部２Ｂ）と、支持基板３（底面３０２を除く）と、複数の制御端子４の一部ずつと、第１導通部材５１、第２導通部材５２および第３導通部材５３の一部ずつと、第４導通部材５４と、複数のワイヤ６１，６２と、をそれぞれ覆っている。封止樹脂７は、たとえば黒色のエポキシ樹脂で構成される。封止樹脂７は、たとえばモールド成形により形成される。封止樹脂７は、樹脂主面７１、樹脂裏面７２、第１樹脂側面７３、第２樹脂側面７４、第３樹脂側面７５、第４樹脂側面７６を有する。 The sealing resin 7 seals the two switching elements 10, the conductive support 2 (the first conductive part 2A and the second conductive part 2B), the support substrate 3 (excluding the bottom surface 302), and one of the plurality of control terminals 4. It covers each portion of the first conductive member 51, the second conductive member 52, and the third conductive member 53, the fourth conductive member 54, and the plurality of wires 61, 62, respectively. The sealing resin 7 is made of, for example, black epoxy resin. The sealing resin 7 is formed by, for example, molding. The sealing resin 7 has a resin main surface 71 , a resin back surface 72 , a first resin side surface 73 , a second resin side surface 74 , a third resin side surface 75 , and a fourth resin side surface 76 .
　図１、図２、図５、図６などに示すように、樹脂主面７１は、ｚ１方向を向き、樹脂裏面７２は、ｚ２方向を向く。樹脂主面７１と樹脂裏面７２とは、ｚ方向に離隔する。樹脂裏面７２は、平面視において支持基板３の底面３０２（第２金属層３３の下面）を囲む枠状である。支持基板３の底面３０２は、樹脂裏面７２から露出し、たとえば樹脂裏面７２と面一である。 As shown in FIGS. 1, 2, 5, 6, etc., the main resin surface 71 faces the z1 direction, and the resin back surface 72 faces the z2 direction. The main resin surface 71 and the resin back surface 72 are separated from each other in the z direction. The resin back surface 72 has a frame shape that surrounds the bottom surface 302 of the support substrate 3 (the lower surface of the second metal layer 33) in plan view. The bottom surface 302 of the support substrate 3 is exposed from the resin back surface 72 and is flush with the resin back surface 72, for example.
　図３、図５、図６などに示すように、第１樹脂側面７３および第２樹脂側面７４は、ｘ方向に離隔する。第１樹脂側面７３および第２樹脂側面７４の各々は、樹脂主面７１と樹脂裏面７２との双方につながり、且つ、ｚ方向においてこれらに挟まれている。第１樹脂側面７３は、ｘ１方向を向く。第２樹脂側面７４は、第１樹脂側面７３に対してｘ２方向に位置し、ｘ２方向を向く。第１導通部材５１の第１主端子５１２および第３導通部材５３の第３主端子５３２は、第１樹脂側面７３からｘ１方向に突出している。第２導通部材５２の第２主端子５２２は、第２樹脂側面７４からｘ２方向に突出している。 As shown in FIGS. 3, 5, 6, etc., the first resin side surface 73 and the second resin side surface 74 are separated from each other in the x direction. Each of the first resin side surface 73 and the second resin side surface 74 is connected to both the resin main surface 71 and the resin back surface 72, and is sandwiched between them in the z direction. The first resin side surface 73 faces in the x1 direction. The second resin side surface 74 is located in the x2 direction with respect to the first resin side surface 73 and faces in the x2 direction. The first main terminal 512 of the first conductive member 51 and the third main terminal 532 of the third conductive member 53 protrude from the first resin side surface 73 in the x1 direction. The second main terminal 522 of the second conductive member 52 protrudes from the second resin side surface 74 in the x2 direction.
　図１～図３などに示すように、第３樹脂側面７５および第４樹脂側面７６は、ｙ方向に離隔する。第３樹脂側面７５および第４樹脂側面７６の各々は、樹脂主面７１と樹脂裏面７２との双方につながり、且つ、ｚ方向においてこれらに挟まれている。第３樹脂側面７５は、ｙ１方向を向く。第４樹脂側面７６は、第３樹脂側面７５に対してｙ２方向に位置し、ｙ２方向を向く。 As shown in FIGS. 1 to 3, the third resin side surface 75 and the fourth resin side surface 76 are separated from each other in the y direction. Each of the third resin side surface 75 and the fourth resin side surface 76 is connected to both the resin main surface 71 and the resin back surface 72, and is sandwiched between them in the z direction. The third resin side surface 75 faces in the y1 direction. The fourth resin side surface 76 is located in the y2 direction with respect to the third resin side surface 75 and faces in the y2 direction.
　本実施形態において、封止樹脂７は、複数（本実施形態では２つ）の側面凹部７５１を有する。複数の側面凹部７５１の各々は、第３樹脂側面７５からｙ２方向に凹む。図示した例では、複数の側面凹部７５１の各々はまた、樹脂主面７１からｚ２方向にも凹んでいる。複数の側面凹部７５１は、ｘ方向において互いに離隔する。 In this embodiment, the sealing resin 7 has a plurality of (two in this embodiment) side recesses 751. Each of the plurality of side surface recesses 751 is recessed from the third resin side surface 75 in the y2 direction. In the illustrated example, each of the plurality of side recesses 751 is also recessed from the main resin surface 71 in the z2 direction. The plurality of side recesses 751 are spaced apart from each other in the x direction.
　複数の制御端子４（複数の第１制御端子４１Ａ，４１Ｂおよび複数の第２制御端子４２Ａ，４２Ｂ）の各々は、第４樹脂側面７６からｙ２方向に突出している。図５に示すように、複数の制御端子４の各々は、ｙ方向に見て、複数の側面凹部７５１のいずれかと重なっている。本実施形態において、複数の第１制御端子４１Ａ，４１Ｂの各々は、ｙ方向に見て一方の側面凹部７５１（ｘ１方向に位置する側面凹部７５１）と重なり、複数の第２制御端子４２Ａ，４２Ｂの各々は、ｙ方向に見て他方の側面凹部７５１（ｘ２方向に位置する側面凹部７５１）と重なる。 Each of the plurality of control terminals 4 (the plurality of first control terminals 41A, 41B and the plurality of second control terminals 42A, 42B) protrudes from the fourth resin side surface 76 in the y2 direction. As shown in FIG. 5, each of the plurality of control terminals 4 overlaps with one of the plurality of side recesses 751 when viewed in the y direction. In this embodiment, each of the plurality of first control terminals 41A, 41B overlaps with one side recess 751 (the side recess 751 located in the x1 direction) when viewed in the y direction, and the plurality of second control terminals 42A, 42B Each overlaps with the other side recess 751 (the side recess 751 located in the x2 direction) when viewed in the y direction.
　図１、図２に示すように、第１結合形状Ｊ１は、半導体装置Ａ１０においてｙ１方向に配置されている。第２結合形状Ｊ２は、半導体装置Ａ１０においてｙ２方向に配置されている。第１結合形状Ｊ１と第２結合形状Ｊ２とは、互いに組み合わせることが可能である。本実施形態において、封止樹脂７における複数の側面凹部７５１は、第１結合形状Ｊ１に含まれる。複数の制御端子４は、第２結合形状Ｊ２に含まれる。 As shown in FIGS. 1 and 2, the first bonding shape J1 is arranged in the y1 direction in the semiconductor device A10. The second bond shape J2 is arranged in the y2 direction in the semiconductor device A10. The first joint shape J1 and the second joint shape J2 can be combined with each other. In this embodiment, the plurality of side recesses 751 in the sealing resin 7 are included in the first joint shape J1. The plurality of control terminals 4 are included in the second joint shape J2.
　図８は、複数の半導体装置Ａ１０を備えた半導体装置ユニットＢ１０を示している。半導体装置ユニットＢ１０において、複数の半導体装置Ａ１０はｙ方向に並んでいる。ｙ方向に隣接する半導体装置Ａ１０において、一方の半導体装置Ａ１０の複数の制御端子４の各々の一部は、他方の半導体装置Ａ１０の側面凹部７５１に収容されている。このように、ｙ方向に並んだ複数の半導体装置Ａ１０（半導体装置ユニットＢ１０）において、複数の制御端子４（第２結合形状Ｊ２）と側面凹部７５１（第１結合形状Ｊ１）とが、組み合わされている。 FIG. 8 shows a semiconductor device unit B10 including a plurality of semiconductor devices A10. In the semiconductor device unit B10, a plurality of semiconductor devices A10 are lined up in the y direction. In semiconductor devices A10 adjacent to each other in the y direction, a portion of each of the plurality of control terminals 4 of one semiconductor device A10 is accommodated in a side recess 751 of the other semiconductor device A10. In this way, in the plurality of semiconductor devices A10 (semiconductor device units B10) lined up in the y direction, the plurality of control terminals 4 (second coupling shape J2) and side recesses 751 (first coupling shape J1) are combined. ing.
　次に、本実施形態の半導体装置Ａ１０の作用について説明する。 Next, the operation of the semiconductor device A10 of this embodiment will be explained.
　半導体装置Ａ１０は、２つのみのスイッチング素子１０を備える。２つのスイッチング素子１０は、一方が第１スイッチング素子１０Ａであり、他方が第２スイッチング素子１０Ｂである。第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂの各々は、ＳｉＣを構成材料として含む。第１スイッチング素子１０Ａと第２スイッチング素子１０Ｂとは、第１スイッチング素子１０Ａを上アーム、第２スイッチング素子１０Ｂを下アームとして、直列に接続されている。このような２つのみのスイッチング素子１０（第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂ）が直列に接続された構成によれば、並列接続された複数のスイッチング素子を内蔵する構成と異なり、熱干渉の発生は回避され、放熱性を改善することができる。また、図８に示した半導体装置ユニットＢ１０のように、複数の半導体装置Ａ１０を並列接続して使用することにより、要求される様々な電流容量に対し、容易に対応させることが可能である。 The semiconductor device A10 includes only two switching elements 10. One of the two switching elements 10 is a first switching element 10A, and the other is a second switching element 10B. Each of the first switching element 10A and the second switching element 10B includes SiC as a constituent material. The first switching element 10A and the second switching element 10B are connected in series with the first switching element 10A as an upper arm and the second switching element 10B as a lower arm. According to such a configuration in which only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, unlike a configuration in which a plurality of switching elements connected in parallel are built-in, heat The occurrence of interference can be avoided and heat dissipation can be improved. Furthermore, by using a plurality of semiconductor devices A10 connected in parallel like the semiconductor device unit B10 shown in FIG. 8, it is possible to easily accommodate various required current capacities.
　半導体装置Ａ１０は、封止樹脂７に対してｘ１方向に位置する第１主端子５１２を有する。また、半導体装置Ａ１０は、第１結合形状Ｊ１および第２結合形状Ｊ２を備える。第１結合形状Ｊ１は、スイッチング素子１０においてｙ１方向に配置されている。第２結合形状Ｊ２は、半導体装置Ａ１０においてｙ２方向に配置されており、第１結合形状Ｊ１と第２結合形状Ｊ２とは、互いに組み合わせることが可能である。このような構成によれば、複数の半導体装置Ａ１０をｙ方向に並べて互いに組み合わせることで、当該複数の半導体装置Ａ１０を１つの半導体装置ユニットＢ１０として取り扱うことが可能である。 The semiconductor device A10 has a first main terminal 512 located in the x1 direction with respect to the sealing resin 7. Further, the semiconductor device A10 includes a first bonding shape J1 and a second bonding shape J2. The first coupling shape J1 is arranged in the y1 direction in the switching element 10. The second bond shape J2 is arranged in the y2 direction in the semiconductor device A10, and the first bond shape J1 and the second bond shape J2 can be combined with each other. According to such a configuration, by arranging the plurality of semiconductor devices A10 in the y direction and combining them with each other, it is possible to handle the plurality of semiconductor devices A10 as one semiconductor device unit B10.
　半導体装置Ａ１０は、複数の側面凹部７５１と、複数の制御端子４と、を有する。複数の側面凹部７５１は、第３樹脂側面７５からｙ２方向に凹み、複数の制御端子４は、第４樹脂側面７６からｙ２方向に突出している。複数の制御端子４の各々は、ｙ方向に見て、複数の側面凹部７５１のいずれかと重なっている。このような構成によれば、ｙ方向に並べられた複数の半導体装置Ａ１０のうち、ｙ方向に隣接する半導体装置Ａ１０において、一方の半導体装置Ａ１０の複数の制御端子４の各々の一部を、他方の半導体装置Ａ１０の側面凹部７５１に収容させることができる。したがって、複数の半導体装置Ａ１０を効率よくｙ方向に並べつつ、１つの半導体装置ユニットＢ１０として取り扱うことができる。 The semiconductor device A10 has a plurality of side recesses 751 and a plurality of control terminals 4. The plurality of side recesses 751 are recessed from the third resin side surface 75 in the y2 direction, and the plurality of control terminals 4 protrude from the fourth resin side surface 76 in the y2 direction. Each of the plurality of control terminals 4 overlaps with one of the plurality of side recesses 751 when viewed in the y direction. According to such a configuration, among the plurality of semiconductor devices A10 arranged in the y direction, in the semiconductor devices A10 adjacent in the y direction, a part of each of the plurality of control terminals 4 of one semiconductor device A10 is It can be accommodated in the side recess 751 of the other semiconductor device A10. Therefore, the plurality of semiconductor devices A10 can be efficiently arranged in the y direction and handled as one semiconductor device unit B10.
　第１実施形態の第１変形例：
　図９および図１０は、第１実施形態の第１変形例に係る半導体装置を示している。図９は、本変形例の半導体装置Ａ１１を示す斜視図である。図１０は、半導体装置Ａ１１を示す正面図であり、封止樹脂７を想像線で示した図である。なお、図９以降の図面において、上記実施形態の半導体装置Ａ１０と同一または類似の要素には、上記実施形態と同一の符号を付しており、適宜説明を省略する。また、図９以降の各変形例等における各部の構成は、技術的な矛盾を生じない範囲において相互に適宜組み合わせ可能である。 First modification of the first embodiment:
9 and 10 show a semiconductor device according to a first modification of the first embodiment. FIG. 9 is a perspective view showing a semiconductor device A11 of this modification. FIG. 10 is a front view of the semiconductor device A11, in which the sealing resin 7 is shown with imaginary lines. In the drawings after FIG. 9, elements that are the same as or similar to those of the semiconductor device A10 of the embodiment described above are given the same reference numerals as those of the embodiment described above, and the description thereof will be omitted as appropriate. In addition, the configurations of the respective parts in the modifications shown in FIG. 9 and onwards can be appropriately combined with each other within a range that does not cause technical contradiction.
　本変形例の半導体装置Ａ１１において、第１導通部材５１（第１主端子５１２）および第３導通部材５３（第３主端子５３２）の位置関係が上記実施形態の半導体装置Ａ１０と異なっている。本変形例において、第１主端子５１２および第３主端子５３２は、ｚ方向において異なる位置に配置されている。第３主端子５３２は、第１主端子５１２に対してｚ１方向に位置する。 In the semiconductor device A11 of this modification, the positional relationship between the first conductive member 51 (first main terminal 512) and the third conductive member 53 (third main terminal 532) is different from the semiconductor device A10 of the above embodiment. In this modification, the first main terminal 512 and the third main terminal 532 are arranged at different positions in the z direction. The third main terminal 532 is located in the z1 direction with respect to the first main terminal 512.
　本変形例の半導体装置Ａ１１によれば、２つのみのスイッチング素子１０（第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂ）が直列に接続されることにより、熱干渉の発生は回避され、放熱性を改善することができる。また、複数の半導体装置Ａ１１を並列接続して使用することにより、要求される様々な電流容量に対し、容易に対応させることが可能である。 According to the semiconductor device A11 of this modification, since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A11 connected in parallel, it is possible to easily accommodate various required current capacities.
　半導体装置Ａ１１において、第３主端子５３２は、第１主端子５１２に対して上方（ｚ１方向）に位置する。このような構成によれば、たとえば複数の半導体装置Ａ１１をｙ方向に並べて並列接続する場合、複数の半導体装置Ａ１１の各々の第１主端子５１２および第３主端子５３２に対して、上下高さ違いでそれぞれｙ方向に延びる２つの外部端子を、一括して効率よく接続することが可能である。その他にも、上記実施形態の半導体装置Ａ１０と同様の構成の範囲において、上記実施形態と同様の作用効果を奏する。 In the semiconductor device A11, the third main terminal 532 is located above (in the z1 direction) with respect to the first main terminal 512. According to such a configuration, for example, when a plurality of semiconductor devices A11 are arranged in the y direction and connected in parallel, the vertical height is It is possible to efficiently connect two external terminals that each extend in the y direction at once due to the difference. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
　第１実施形態の第２変形例：
　図１１および図１２は、第１実施形態の第２変形例に係る半導体装置を示している。図１１は、本変形例の半導体装置Ａ１２を示す斜視図である。図１２は、半導体装置Ａ１２を示す正面図であり、封止樹脂７を想像線で示した図である。 Second modification of the first embodiment:
11 and 12 show a semiconductor device according to a second modification of the first embodiment. FIG. 11 is a perspective view showing a semiconductor device A12 of this modification. FIG. 12 is a front view of the semiconductor device A12, in which the sealing resin 7 is shown with imaginary lines.
　本変形例の半導体装置Ａ１２において、第１導通部材５１（第１主端子５１２）および第３導通部材５３（第３主端子５３２）の位置関係が上記実施形態の半導体装置Ａ１０と異なっている。本変形例において、第１主端子５１２および第３主端子５３２は、ｚ方向において異なる位置に配置されている。第３主端子５３２は、第１主端子５１２に対してｚ１方向に位置する。また、第３主端子５３２は、第１主端子５１２に対してｘ２方向に位置し、且つ平面視において第１主端子５１２と重なる。 In the semiconductor device A12 of this modification, the positional relationship between the first conductive member 51 (first main terminal 512) and the third conductive member 53 (third main terminal 532) is different from the semiconductor device A10 of the above embodiment. In this modification, the first main terminal 512 and the third main terminal 532 are arranged at different positions in the z direction. The third main terminal 532 is located in the z1 direction with respect to the first main terminal 512. Further, the third main terminal 532 is located in the x2 direction with respect to the first main terminal 512, and overlaps with the first main terminal 512 in a plan view.
　本変形例の半導体装置Ａ１２によれば、２つのみのスイッチング素子１０（第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂ）が直列に接続されることにより、熱干渉の発生は回避され、放熱性を改善することができる。また、複数の半導体装置Ａ１２を並列接続して使用することにより、要求される様々な電流容量に対し、容易に対応させることが可能である。 According to the semiconductor device A12 of this modification, since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided, and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A12 connected in parallel, it is possible to easily accommodate various required current capacities.
　半導体装置Ａ１２において、第３主端子５３２は、第１主端子５１２に対してｘ２方向に位置し、また、第１主端子５１２よりも上方（ｚ１方向）に位置する。このような構成によれば、たとえば複数の半導体装置Ａ１２をｙ方向に並べて並列接続する場合、複数の半導体装置Ａ１２の各々の第１主端子５１２および第３主端子５３２に対して、上下高さ違いでそれぞれｙ方向に延びる２つの外部端子を、一括して効率よく接続することが可能である。その他にも、上記実施形態の半導体装置Ａ１０と同様の構成の範囲において、上記実施形態と同様の作用効果を奏する。 In the semiconductor device A12, the third main terminal 532 is located in the x2 direction with respect to the first main terminal 512, and is also located above the first main terminal 512 (in the z1 direction). According to such a configuration, for example, when a plurality of semiconductor devices A12 are arranged in the y direction and connected in parallel, the vertical height is It is possible to efficiently connect two external terminals that each extend in the y direction at once due to the difference. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
　第１実施形態の第３変形例：
　図１３および図１４は、第１実施形態の第３変形例に係る半導体装置を示している。図１３は、本変形例の半導体装置Ａ１３を示す斜視図である。図１４は、半導体装置Ａ１３を示す正面図であり、封止樹脂７を想像線で示した図である。 Third modification of the first embodiment:
13 and 14 show a semiconductor device according to a third modification of the first embodiment. FIG. 13 is a perspective view showing a semiconductor device A13 of this modification. FIG. 14 is a front view of the semiconductor device A13, in which the sealing resin 7 is shown with imaginary lines.
　本変形例の半導体装置Ａ１３において、主に第２導通部材５２（第２主端子５２２）および第３導通部材５３（第３主端子５３２）の配置が上記実施形態の半導体装置Ａ１０と異なっている。本変形例において、第３主端子５３２は、封止樹脂７に対してｘ２方向に位置する。第３導通部材５３の第３主端子５３２は、第２樹脂側面７４からｘ２方向に突出している。その一方、第２主端子５２２は、封止樹脂７対してｙ２方向に位置する。第２導通部材５２の第２主端子５２２は、第４樹脂側面７６からｙ２方向に突出し、且つｚ１方向に延びている。第２主端子５２２は、ｘ方向において、複数の第１制御端子４１Ａ，４１Ｂと、複数の第２制御端子４２Ａ，４２Ｂとの間に位置する。 The semiconductor device A13 of this modification differs from the semiconductor device A10 of the above embodiment mainly in the arrangement of the second conductive member 52 (second main terminal 522) and the third conductive member 53 (third main terminal 532). . In this modification, the third main terminal 532 is located in the x2 direction with respect to the sealing resin 7. The third main terminal 532 of the third conductive member 53 protrudes from the second resin side surface 74 in the x2 direction. On the other hand, the second main terminal 522 is located in the y2 direction with respect to the sealing resin 7. The second main terminal 522 of the second conductive member 52 protrudes from the fourth resin side surface 76 in the y2 direction and extends in the z1 direction. The second main terminal 522 is located between the plurality of first control terminals 41A, 41B and the plurality of second control terminals 42A, 42B in the x direction.
　本変形例において、封止樹脂７は、３つの側面凹部７５１を有する。３つの側面凹部７５１は、ｘ方向において互いに離隔する。複数の第１制御端子４１Ａ，４１Ｂの各々は、ｙ方向に見て１つの側面凹部７５１（ｘ１方向に位置する側面凹部７５１）と重なり、複数の第２制御端子４２Ａ，４２Ｂの各々は、ｙ方向に見て他の１つの側面凹部７５１（ｘ２方向に位置する側面凹部７５１）と重なる。第２主端子５２２は、ｙ方向に見て、さらに他の１つの側面凹部７５１（ｘ方向の中央に位置する側面凹部７５１）と重なる。本変形例において、封止樹脂７における複数（３つ）の側面凹部７５１は、第１結合形状Ｊ１に含まれる。複数の制御端子４、および第２主端子５２２は、第２結合形状Ｊ２に含まれる。 In this modification, the sealing resin 7 has three side recesses 751. The three side recesses 751 are spaced apart from each other in the x direction. Each of the plurality of first control terminals 41A, 41B overlaps with one side recess 751 (side recess 751 located in the x1 direction) when viewed in the y direction, and each of the plurality of second control terminals 42A, 42B It overlaps with another side recess 751 (the side recess 751 located in the x2 direction) when viewed in the direction. The second main terminal 522 overlaps with another side recess 751 (the side recess 751 located at the center in the x direction) when viewed in the y direction. In this modification, a plurality (three) of side recesses 751 in the sealing resin 7 are included in the first joint shape J1. The plurality of control terminals 4 and the second main terminal 522 are included in the second joint shape J2.
　図１５は、複数の半導体装置Ａ１３を備えた半導体装置ユニットＢ１１を示している。半導体装置ユニットＢ１１において、複数の半導体装置Ａ１３はｙ方向に並んでいる。ｙ方向に隣接する半導体装置Ａ１３において、一方の半導体装置Ａ１０の複数の制御端子４の各々の一部と、第２主端子５２２の一部とは、他方の半導体装置Ａ１０の側面凹部７５１に収容されている。このように、ｙ方向に並んだ複数の半導体装置Ａ１３（半導体装置ユニットＢ１１）において、複数の制御端子４および第２主端子５２２（第２結合形状Ｊ２）と側面凹部７５１（第１結合形状Ｊ１）とが、組み合わされている。 FIG. 15 shows a semiconductor device unit B11 including a plurality of semiconductor devices A13. In the semiconductor device unit B11, the plurality of semiconductor devices A13 are lined up in the y direction. In the semiconductor devices A13 adjacent in the y direction, a portion of each of the plurality of control terminals 4 of one semiconductor device A10 and a portion of the second main terminal 522 are accommodated in the side recess 751 of the other semiconductor device A10. has been done. In this way, in the plurality of semiconductor devices A13 (semiconductor device unit B11) lined up in the y direction, the plurality of control terminals 4 and second main terminals 522 (second coupling shape J2) and side recess 751 (first coupling shape J1 ) are combined.
　本変形例の半導体装置Ａ１３によれば、２つのみのスイッチング素子１０（第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂ）が直列に接続されることにより、熱干渉の発生は回避され、放熱性を改善することができる。また、複数の半導体装置Ａ１３を並列接続して使用することにより、要求される様々な電流容量に対し、容易に対応させることが可能である。その他にも、上記実施形態の半導体装置Ａ１０と同様の構成の範囲において、上記実施形態と同様の作用効果を奏する。 According to the semiconductor device A13 of this modification, since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A13 connected in parallel, it is possible to easily accommodate various required current capacities. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
　第２実施形態：
　図１６および図１７は、本開示の第２実施形態に係る半導体装置を示している。図１６は、本実施形態の半導体装置Ａ２０を示す斜視図である。図１７は、半導体装置Ａ２０の右側面図である。 Second embodiment:
16 and 17 show a semiconductor device according to a second embodiment of the present disclosure. FIG. 16 is a perspective view showing the semiconductor device A20 of this embodiment. FIG. 17 is a right side view of the semiconductor device A20.
　本実施形態の半導体装置Ａ２０において、主に、第１係合部７５２および第２係合部７６２を有する点が上記実施形態の半導体装置Ａ１０と異なっている。第１係合部７５２は、第３樹脂側面７５に設けられており、第３樹脂側面７５からｙ１方向に突出している。第１係合部７５２は、断面Ｌ字状であり、第２樹脂側面７４からｘ１方向に所定長さ延びている。第２係合部７６２は、第４樹脂側面７６からｙ１方向に凹む凹溝である。第２係合部７６２は、断面Ｌ字状であり、第２樹脂側面７４からｘ１方向に所定長さ延びている。第１係合部７５２と第２係合部７６２とは、互いに係合可能である。本実施形態において、側面凹部７５１は、第１樹脂側面７３から第２樹脂側面７４まで一連に形成されている。 The semiconductor device A20 of this embodiment differs from the semiconductor device A10 of the above embodiment mainly in that it includes a first engagement portion 752 and a second engagement portion 762. The first engaging portion 752 is provided on the third resin side surface 75 and protrudes from the third resin side surface 75 in the y1 direction. The first engaging portion 752 has an L-shaped cross section and extends a predetermined length from the second resin side surface 74 in the x1 direction. The second engaging portion 762 is a groove recessed from the fourth resin side surface 76 in the y1 direction. The second engaging portion 762 has an L-shaped cross section and extends a predetermined length from the second resin side surface 74 in the x1 direction. The first engaging portion 752 and the second engaging portion 762 are capable of engaging with each other. In this embodiment, the side recess 751 is formed continuously from the first resin side surface 73 to the second resin side surface 74.
　本実施形態において、封止樹脂７における側面凹部７５１および第１係合部７５２は、第１結合形状Ｊ１に含まれる。複数の制御端子４および封止樹脂７における第２係合部７６２は、第２結合形状Ｊ２に含まれる。 In this embodiment, the side recess 751 and the first engaging portion 752 in the sealing resin 7 are included in the first joint shape J1. The plurality of control terminals 4 and the second engaging portions 762 in the sealing resin 7 are included in the second joint shape J2.
　図１８は、複数の半導体装置Ａ２０を備えた半導体装置ユニットＢ２０を示している。半導体装置ユニットＢ２０において、複数の半導体装置Ａ２０はｙ方向に並んでいる。ｙ方向に隣接する半導体装置Ａ２０において、一方の半導体装置Ａ２０の複数の制御端子４の各々の一部は、他方の半導体装置Ａ２０の側面凹部７５１に収容されている。また、一方の半導体装置Ａ２０の第２係合部７６２と他方の半導体装置Ａ２０の第１係合部７５２とが互いに係合している。このように、ｙ方向に並んだ複数の半導体装置Ａ２０（半導体装置ユニットＢ２０）において、複数の制御端子４および第２係合部７６２（第２結合形状Ｊ２）と側面凹部７５１および第１係合部７５２（第１結合形状Ｊ１）とが、組み合わされている。そして、第１係合部７５２と第２係合部７６２とが係合することにより、複数の半導体装置Ａ２０が機械的に連結されている。 FIG. 18 shows a semiconductor device unit B20 including a plurality of semiconductor devices A20. In the semiconductor device unit B20, the plurality of semiconductor devices A20 are lined up in the y direction. In semiconductor devices A20 adjacent to each other in the y direction, a portion of each of the plurality of control terminals 4 of one semiconductor device A20 is accommodated in a side recess 751 of the other semiconductor device A20. Further, the second engaging portion 762 of one semiconductor device A20 and the first engaging portion 752 of the other semiconductor device A20 are engaged with each other. In this way, in the plurality of semiconductor devices A20 (semiconductor device units B20) lined up in the y direction, the plurality of control terminals 4 and the second engagement portions 762 (second coupling shape J2) are connected to the side recess 751 and the first engagement. portion 752 (first joint shape J1). The first engaging portion 752 and the second engaging portion 762 engage with each other, thereby mechanically connecting the plurality of semiconductor devices A20.
　本実施形態の半導体装置Ａ２０によれば、２つのみのスイッチング素子１０（第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂ）が直列に接続されることにより、熱干渉の発生は回避され、放熱性を改善することができる。また、複数の半導体装置Ａ２０を並列接続して使用することにより、要求される様々な電流容量に対し、容易に対応させることが可能である。 According to the semiconductor device A20 of the present embodiment, since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided, and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A20 connected in parallel, it is possible to easily accommodate various required current capacities.
　半導体装置Ａ２０においては、第１結合形状Ｊ１に含まれる第１係合部７５２と、第２結合形状Ｊ２に含まれる第２係合部７６２とを有する。第１係合部７５２と第２係合部７６２とは、互いに係合可能である。このような構成によれば、複数の半導体装置Ａ２０をｙ方向に並べて互いに組み合わせることで、当該複数の半導体装置Ａ２０を、機械的に連結した１つの半導体装置ユニットＢ２０として取り扱うことが可能である。その他にも、上記実施形態の半導体装置Ａ１０と同様の構成の範囲において、上記実施形態と同様の作用効果を奏する。 The semiconductor device A20 has a first engagement portion 752 included in the first coupling shape J1 and a second engagement portion 762 included in the second coupling shape J2. The first engaging portion 752 and the second engaging portion 762 are capable of engaging with each other. According to such a configuration, by arranging the plurality of semiconductor devices A20 in the y direction and combining them with each other, it is possible to handle the plurality of semiconductor devices A20 as one mechanically connected semiconductor device unit B20. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
　第３実施形態：
　図１９は、本開示の第３実施形態に係る半導体装置を示している。図１９は、本実施形態の半導体装置Ａ３０を示す斜視図である。本実施形態の半導体装置Ａ３０において、第１係合部７５３および第２係合部７６３を有する点が上記実施形態の半導体装置Ａ１０と大きく異なっている。また、上記実施形態の半導体装置Ａ１０と異なり、封止樹脂７は側面凹部７５１を有さない。複数の制御端子４は、封止樹脂７の樹脂主面７１から突出しており、ｚ１方向に延びている。 Third embodiment:
FIG. 19 shows a semiconductor device according to a third embodiment of the present disclosure. FIG. 19 is a perspective view showing the semiconductor device A30 of this embodiment. The semiconductor device A30 of this embodiment differs greatly from the semiconductor device A10 of the above embodiment in that it includes a first engagement portion 753 and a second engagement portion 763. Further, unlike the semiconductor device A10 of the above embodiment, the sealing resin 7 does not have a side recess 751. The plurality of control terminals 4 protrude from the main resin surface 71 of the sealing resin 7 and extend in the z1 direction.
　第１係合部７５３は、第３樹脂側面７５に設けられており、第３樹脂側面７５からｙ２方向に凹む凹溝である。第１係合部７５３は、断面台形状であり、樹脂主面７１から樹脂裏面７２までｚ方向に一連に形成されている。第２係合部７６３は、第４樹脂側面７６に設けられており、第４樹脂側面７６からｙ２方向に突出している。第２係合部７６３は、断面台形状であり、樹脂主面７１から樹脂裏面７２までｚ方向に一連に形成されている。第１係合部７５３と第２係合部７６３とは、互いに係合可能である。本実施形態において、封止樹脂７における第１係合部７５３は、第１結合形状Ｊ１に含まれる。また、封止樹脂７における第２係合部７６３は、第２結合形状Ｊ２に含まれる。 The first engaging portion 753 is provided on the third resin side surface 75 and is a groove recessed from the third resin side surface 75 in the y2 direction. The first engaging portion 753 has a trapezoidal cross section and is formed continuously in the z direction from the main resin surface 71 to the resin back surface 72. The second engaging portion 763 is provided on the fourth resin side surface 76 and protrudes from the fourth resin side surface 76 in the y2 direction. The second engaging portion 763 has a trapezoidal cross section and is formed continuously in the z direction from the resin main surface 71 to the resin back surface 72. The first engaging portion 753 and the second engaging portion 763 are capable of engaging with each other. In this embodiment, the first engaging portion 753 in the sealing resin 7 is included in the first joint shape J1. Further, the second engaging portion 763 in the sealing resin 7 is included in the second joint shape J2.
　図２０は、複数の半導体装置Ａ３０を備えた半導体装置ユニットＢ３０を示している。半導体装置ユニットＢ３０において、複数の半導体装置Ａ３０はｙ方向に並んでいる。ｙ方向に隣接する半導体装置Ａ３０において、一方の半導体装置Ａ３０の第１係合部７５３と他方の半導体装置Ａ３０の第２係合部７６３とが互いに係合している。このように、ｙ方向に並んだ複数の半導体装置Ａ３０（半導体装置ユニットＢ３０）において、第１係合部７５３（第１結合形状Ｊ１）と第２係合部７６３（第２結合形状Ｊ２）とが、組み合わされている。そして、第１係合部７５３と第２係合部７６３とが係合することにより、複数の半導体装置Ａ３０が機械的に連結されている。 FIG. 20 shows a semiconductor device unit B30 including a plurality of semiconductor devices A30. In the semiconductor device unit B30, the plurality of semiconductor devices A30 are lined up in the y direction. In the semiconductor devices A30 adjacent in the y direction, the first engaging portion 753 of one semiconductor device A30 and the second engaging portion 763 of the other semiconductor device A30 are engaged with each other. In this way, in the plurality of semiconductor devices A30 (semiconductor device units B30) lined up in the y direction, the first engaging portion 753 (first joint shape J1) and the second engaging portion 763 (second joint shape J2) are combined. The first engaging portion 753 and the second engaging portion 763 engage with each other, thereby mechanically connecting the plurality of semiconductor devices A30.
　本実施形態の半導体装置Ａ３０によれば、２つのみのスイッチング素子１０（第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂ）が直列に接続されることにより、熱干渉の発生は回避され、放熱性を改善することができる。また、複数の半導体装置Ａ３０を並列接続して使用することにより、要求される様々な電流容量に対し、容易に対応させることが可能である。 According to the semiconductor device A30 of the present embodiment, only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, so that generation of thermal interference is avoided and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A30 connected in parallel, it is possible to easily accommodate various required current capacities.
　半導体装置Ａ３０においては、第１結合形状Ｊ１に含まれる第１係合部７５３と、第２結合形状Ｊ２に含まれる第２係合部７６３とを有する。第１係合部７５３と第２係合部７６３とは、互いに係合可能である。このような構成によれば、複数の半導体装置Ａ３０をｙ方向に並べて互いに組み合わせることで、当該複数の半導体装置Ａ３０を、機械的に連結した１つの半導体装置ユニットＢ３０として取り扱うことが可能である。その他にも、上記実施形態の半導体装置Ａ１０と同様の構成の範囲において、上記実施形態と同様の作用効果を奏する。 The semiconductor device A30 has a first engagement portion 753 included in the first coupling shape J1 and a second engagement portion 763 included in the second coupling shape J2. The first engaging portion 753 and the second engaging portion 763 are capable of engaging with each other. According to such a configuration, by arranging a plurality of semiconductor devices A30 in the y direction and combining them with each other, it is possible to handle the plurality of semiconductor devices A30 as one mechanically connected semiconductor device unit B30. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
　第４実施形態：
　図２１は、本開示の第４実施形態に係る半導体装置を示している。図２１は、本実施形態の半導体装置Ａ４０を示す斜視図である。本実施形態の半導体装置Ａ４０において、第１位置合わせ部７５８、第２位置合わせ部７６８、第１接続部４３、第２接続部４４を有する点が上記実施形態の半導体装置Ａ３０と大きく異なっている。また、上記実施形態の半導体装置Ａ３０と異なり、複数の制御端子４が設けられていない。 Fourth embodiment:
FIG. 21 shows a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 21 is a perspective view showing the semiconductor device A40 of this embodiment. The semiconductor device A40 of this embodiment is significantly different from the semiconductor device A30 of the above embodiment in that it includes a first alignment section 758, a second alignment section 768, a first connection section 43, and a second connection section 44. . Further, unlike the semiconductor device A30 of the above embodiment, a plurality of control terminals 4 are not provided.
　第１位置合わせ部７５８は、第３樹脂側面７５に設けられており、第３樹脂側面７５からｙ２方向に凹む凹部である。第１位置合わせ部７５８は、樹脂主面７１からも凹んでいる。第１位置合わせ部７５８は、ｘ方向に離隔する２箇所に設けられている。第２位置合わせ部７６８は、第４樹脂側面７６に設けられており、第４樹脂側面７６からｙ２方向に突出する凸部である。第２位置合わせ部７６８は、ｘ方向に離隔する２箇所に設けられている。第２位置合わせ部７６８はこれに対応する第１位置合わせ部７５８に嵌入可能であり、これにより、第１位置合わせ部７５８と第２位置合わせ部７６８とが位置合わせされる。また、第１位置合わせ部７５８と第２位置合わせ部７６８とが位置合わせされたときに、第１係合部７５３と第２係合部７６３とが互いに係合する。本実施形態において、封止樹脂７における第１係合部７５３および第１位置合わせ部７５８は、第１結合形状Ｊ１に含まれる。また、封止樹脂７における第２係合部７６３および第２位置合わせ部７６８は、第２結合形状Ｊ２に含まれる。 The first positioning portion 758 is provided on the third resin side surface 75 and is a recessed portion recessed from the third resin side surface 75 in the y2 direction. The first positioning portion 758 is also recessed from the main resin surface 71 . The first positioning portions 758 are provided at two locations separated in the x direction. The second positioning portion 768 is a convex portion that is provided on the fourth resin side surface 76 and protrudes from the fourth resin side surface 76 in the y2 direction. The second positioning portions 768 are provided at two locations separated in the x direction. The second alignment part 768 can be fitted into the corresponding first alignment part 758, whereby the first alignment part 758 and the second alignment part 768 are aligned. Moreover, when the first alignment part 758 and the second alignment part 768 are aligned, the first engagement part 753 and the second engagement part 763 engage with each other. In this embodiment, the first engaging portion 753 and the first positioning portion 758 in the sealing resin 7 are included in the first joint shape J1. Further, the second engaging portion 763 and the second positioning portion 768 in the sealing resin 7 are included in the second joint shape J2.
　第１接続部４３は、封止樹脂７の樹脂主面７１に配置されている。第１接続部４３は、第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂのいずれかと導通する。図示した例では、４つの第１接続部４３が設けられている。４つの第１接続部４３は、樹脂主面７１においてｙ２方向寄りに配置されており、ｘ方向に沿って配列されている。また、２つの第１接続部４３は、ｘ１方向寄りに配置されており、他の２つの第１接続部４３は、ｘ２方向寄りに配置されている。詳細な図示説明は省略するが、たとえば、ｘ１方向寄りの２つの第１接続部４３は第１スイッチング素子１０Ａに導通している。そのうち一方の第１接続部４３は第１スイッチング素子１０Ａの第１主面電極１１（ゲート電極）に導通し、他方の第１接続部４３は第１スイッチング素子１０Ａの第２主面電極１２（ソース電極）に導通する。また、ｘ２方向寄りの２つの第１接続部４３は第２スイッチング素子１０Ｂに導通している。そのうち一方の第１接続部４３は第２スイッチング素子１０Ｂの第１主面電極１１（ゲート電極）に導通し、他方の第１接続部４３は第２スイッチング素子１０Ｂの第２主面電極１２（ソース電極）に導通する。 The first connecting portion 43 is arranged on the main resin surface 71 of the sealing resin 7. The first connection portion 43 is electrically connected to either the first switching element 10A or the second switching element 10B. In the illustrated example, four first connection parts 43 are provided. The four first connecting portions 43 are arranged closer to the y2 direction on the resin main surface 71 and are arranged along the x direction. Moreover, two first connecting parts 43 are arranged closer to the x1 direction, and the other two first connecting parts 43 are arranged closer to the x2 direction. Although detailed illustrations and explanations are omitted, for example, the two first connection portions 43 closer to the x1 direction are electrically connected to the first switching element 10A. One of the first connection parts 43 is electrically connected to the first main surface electrode 11 (gate electrode) of the first switching element 10A, and the other first connection part 43 is electrically connected to the second main surface electrode 12 (gate electrode) of the first switching element 10A. source electrode). Further, the two first connection portions 43 closer to the x2 direction are electrically connected to the second switching element 10B. One of the first connection parts 43 is electrically connected to the first main surface electrode 11 (gate electrode) of the second switching element 10B, and the other first connection part 43 is electrically connected to the second main surface electrode 12 (gate electrode) of the second switching element 10B. source electrode).
　第２接続部４４は、封止樹脂７の樹脂主面７１に配置されている。第２接続部４４は、第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂのいずれかと導通する。図示した例では、４つの第２接続部４４が設けられている。第２接続部４４は、対応する第１接続部４３に対してｙ方向に離隔して配置されている。４つの第２接続部４４は、樹脂主面７１においてｙ１方向寄りに配置されており、ｘ方向に沿って配列されている。また、２つの第２接続部４４は、ｘ１方向寄りに配置されており、他の２つの第２接続部４４は、ｘ２方向寄りに配置されている。詳細な図示説明は省略するが、たとえば、ｘ１方向寄りの２つの第２接続部４４は第１スイッチング素子１０Ａに導通している。そのうち一方の第２接続部４４は第１スイッチング素子１０Ａの第１主面電極１１（ゲート電極）に導通し、他方の第２接続部４４は第１スイッチング素子１０Ａの第２主面電極１２（ソース電極）に導通する。また、ｘ２方向寄りの２つの第２接続部４４は第２スイッチング素子１０Ｂに導通している。そのうち一方の第２接続部４４は第２スイッチング素子１０Ｂの第１主面電極１１（ゲート電極）に導通し、他方の第２接続部４４は第２スイッチング素子１０Ｂの第２主面電極１２（ソース電極）に導通する。 The second connecting portion 44 is arranged on the main resin surface 71 of the sealing resin 7. The second connection portion 44 is electrically connected to either the first switching element 10A or the second switching element 10B. In the illustrated example, four second connections 44 are provided. The second connecting portion 44 is arranged apart from the corresponding first connecting portion 43 in the y direction. The four second connecting portions 44 are arranged closer to the y1 direction on the main resin surface 71 and are arranged along the x direction. Further, two second connecting portions 44 are arranged closer to the x1 direction, and the other two second connecting portions 44 are arranged closer to the x2 direction. Although detailed illustrations and explanations are omitted, for example, the two second connection portions 44 closer to the x1 direction are electrically connected to the first switching element 10A. One of the second connection parts 44 is electrically connected to the first main surface electrode 11 (gate electrode) of the first switching element 10A, and the other second connection part 44 is electrically connected to the second main surface electrode 12 (gate electrode) of the first switching element 10A. source electrode). Furthermore, the two second connecting portions 44 closer to the x2 direction are electrically connected to the second switching element 10B. One of the second connection parts 44 is electrically connected to the first main surface electrode 11 (gate electrode) of the second switching element 10B, and the other second connection part 44 is electrically connected to the second main surface electrode 12 (gate electrode) of the second switching element 10B. source electrode).
　なお、詳細な図示説明は省略するが、図２１に示した例と異なり、複数の制御端子４を備える構成としてもよい。複数の制御端子４を備える場合、たとえば図２１に示した４つ第１接続部４３の各々にピン状の制御端子が取り付けられる。 Although detailed illustrations and explanations are omitted, unlike the example shown in FIG. 21, a configuration including a plurality of control terminals 4 may be used. When a plurality of control terminals 4 are provided, a pin-shaped control terminal is attached to each of the four first connection portions 43 shown in FIG. 21, for example.
　図２２は、複数の半導体装置Ａ４０を備えた半導体装置ユニットＢ４０の一例を示している。半導体装置ユニットＢ４０において、複数の半導体装置Ａ４０はｙ方向に並んでいる。ｙ方向に隣接する半導体装置Ａ４０において、一方の半導体装置Ａ４０の第１係合部７５３と他方の半導体装置Ａ４０の第２係合部７６３とが互いに係合し、且つ一方の半導体装置Ａ４０の第１位置合わせ部７５８に他方の半導体装置Ａ４０の第２位置合わせ部７６８が嵌入している。このように、ｙ方向に並んだ複数の半導体装置Ａ４０（半導体装置ユニットＢ４０）において、第１係合部７５３および第１位置合わせ部７５８（第１結合形状Ｊ１）と第２係合部７６３および第２位置合わせ部７６８（第２結合形状Ｊ２）とが、組み合わされている。そして、第１係合部７５３と第２係合部７６３とが係合することにより、複数の半導体装置Ａ３０が機械的に連結されている。図２２に示した例では、ｙ方向に隣接する２つの半導体装置Ａ４０において、一方の半導体装置Ａ４０の第１接続部４３と、これに対応する他方の半導体装置Ａ４０の第２接続部４４とが、ピン状の接続部材４７で導通接続されている。また、１つの半導体装置Ａ４０における４つの第１接続部４３の各々には、制御端子４が取り付けられている。このような構成によれば、複数の半導体装置Ａ４０を並列接続する際、１つの半導体装置Ａ４０についてのみに制御端子４を設けて外部との接続を図ることで、複数の半導体装置Ａ４０それぞれの第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂの駆動制御が可能である。 FIG. 22 shows an example of a semiconductor device unit B40 including a plurality of semiconductor devices A40. In the semiconductor device unit B40, the plurality of semiconductor devices A40 are lined up in the y direction. In semiconductor devices A40 adjacent in the y direction, the first engaging portion 753 of one semiconductor device A40 and the second engaging portion 763 of the other semiconductor device A40 engage with each other, and A second alignment portion 768 of the other semiconductor device A40 is fitted into the first alignment portion 758. In this way, in the plurality of semiconductor devices A40 (semiconductor device units B40) lined up in the y direction, the first engaging portion 753 and the first positioning portion 758 (first joint shape J1), the second engaging portion 763, and A second positioning portion 768 (second joint shape J2) is combined. The first engaging portion 753 and the second engaging portion 763 engage with each other, thereby mechanically connecting the plurality of semiconductor devices A30. In the example shown in FIG. 22, in two semiconductor devices A40 adjacent in the y direction, the first connection portion 43 of one semiconductor device A40 and the corresponding second connection portion 44 of the other semiconductor device A40 are connected. , are electrically connected by a pin-shaped connecting member 47. Moreover, the control terminal 4 is attached to each of the four first connection parts 43 in one semiconductor device A40. According to such a configuration, when a plurality of semiconductor devices A40 are connected in parallel, the control terminal 4 is provided for only one semiconductor device A40 to connect it to the outside, so that each of the plurality of semiconductor devices A40 can be connected in parallel. Drive control of the first switching element 10A and the second switching element 10B is possible.
　図２３は、複数の半導体装置Ａ４０を備えた半導体装置ユニットＢ４１の他の例を示している。図２３に示した例では、ｙ方向に隣接する２つの半導体装置Ａ４０において、一方の半導体装置Ａ４０の第１接続部４３と、これに対応する他方の半導体装置Ａ４０の第２接続部４４とが、プレート状の接続部材４８で導通接続されている。また、１つの半導体装置Ａ４０における４つの第１接続部４３の各々には、制御端子４が取り付けられている。制御端子４は、複数の半導体装置Ａ４０に対してｚ１方向に配置された駆動基板８０（図２３では想像線で表す）に接続されている。このような構成によれば、複数の半導体装置Ａ４０を並列接続する際、１つの半導体装置Ａ４０についてのみに制御端子４を設けて駆動基板８０との接続を図ることで、複数の半導体装置Ａ４０それぞれの第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂの駆動制御が可能である。 FIG. 23 shows another example of a semiconductor device unit B41 including a plurality of semiconductor devices A40. In the example shown in FIG. 23, in two semiconductor devices A40 adjacent to each other in the y direction, the first connection portion 43 of one semiconductor device A40 and the corresponding second connection portion 44 of the other semiconductor device A40 are connected. , are electrically connected by a plate-shaped connecting member 48. Moreover, the control terminal 4 is attached to each of the four first connection parts 43 in one semiconductor device A40. The control terminal 4 is connected to a drive board 80 (represented by imaginary lines in FIG. 23) arranged in the z1 direction with respect to the plurality of semiconductor devices A40. According to such a configuration, when connecting a plurality of semiconductor devices A40 in parallel, by providing the control terminal 4 only for one semiconductor device A40 and connecting it to the drive board 80, each of the plurality of semiconductor devices A40 can be connected in parallel. It is possible to drive and control the first switching element 10A and the second switching element 10B.
　本実施形態の半導体装置Ａ４０によれば、２つのみのスイッチング素子１０（第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂ）が直列に接続されることにより、熱干渉の発生は回避され、放熱性を改善することができる。また、複数の半導体装置Ａ４０を並列接続して使用することにより、要求される様々な電流容量に対し、容易に対応させることが可能である。 According to the semiconductor device A40 of the present embodiment, since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A40 connected in parallel, it is possible to easily accommodate various required current capacities.
　半導体装置Ａ４０においては、第１結合形状Ｊ１に含まれる第１係合部７５３および第１位置合わせ部７５８と、第２結合形状Ｊ２に含まれる第２係合部７６３および第２位置合わせ部７６８とを有する。第１係合部７５３と第２係合部７６３とは、互いに係合可能である。このような構成によれば、複数の半導体装置Ａ４０をｙ方向に並べて互いに組み合わせることで、当該複数の半導体装置Ａ４０を、機械的に連結した１つの半導体装置ユニットＢ４０（Ｂ４１）として取り扱うことが可能である。また、本実施形態では、第１位置合わせ部７５８と第２位置合わせ部７６８とが位置合わせされたときに、第１係合部７５３と第２係合部７６３とが互いに係合する。このような構成によれば、複数の半導体装置Ａ４０を正確に連結することが可能である。その他にも、上記実施形態の半導体装置Ａ１０と同様の構成の範囲において、上記実施形態と同様の作用効果を奏する。 In the semiconductor device A40, the first engagement part 753 and the first alignment part 758 included in the first coupling shape J1, and the second engagement part 763 and the second alignment part 768 included in the second coupling shape J2. and has. The first engaging portion 753 and the second engaging portion 763 are capable of engaging with each other. According to such a configuration, by arranging a plurality of semiconductor devices A40 in the y direction and combining them with each other, it is possible to handle the plurality of semiconductor devices A40 as one mechanically connected semiconductor device unit B40 (B41). It is. Furthermore, in this embodiment, when the first alignment part 758 and the second alignment part 768 are aligned, the first engagement part 753 and the second engagement part 763 engage with each other. According to such a configuration, it is possible to accurately connect the plurality of semiconductor devices A40. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
　第５実施形態：
　図２４および図２５は、本開示の第５実施形態に係る半導体装置を示している。図２４は、本実施形態の半導体装置Ａ５０を示す斜視図である。図２５は、半導体装置Ａ５０を示す斜視図であり、背面側から見た図である。 Fifth embodiment:
24 and 25 show a semiconductor device according to a fifth embodiment of the present disclosure. FIG. 24 is a perspective view showing the semiconductor device A50 of this embodiment. FIG. 25 is a perspective view of the semiconductor device A50, viewed from the back side.
　本実施形態の半導体装置Ａ５０において、第１係合部７５４、第２係合部７６４、第３接続部４５および第４接続部４６を有する点が、上記実施形態の半導体装置Ａ３０と大きく異なっている。 The semiconductor device A50 of this embodiment differs greatly from the semiconductor device A30 of the above embodiment in that it includes a first engaging portion 754, a second engaging portion 764, a third connecting portion 45, and a fourth connecting portion 46. There is.
　本実施形態において、第１係合部７５４は、第３樹脂側面７５に設けられており、第３樹脂側面７５からｙ２方向に凹む凹型コネクタ状である。図示した例では、第１係合部７５４は、ｘ方向に離隔する２箇所に設けられている。第２係合部７６４は、第４樹脂側面７６に設けられており、ｙ２方向に突出する凸型コネクタ状である。図示した例では、第２係合部７６４は、ｘ方向に離隔する２箇所に設けられている。第２係合部７６４は、これに対応する第１係合部７５４に嵌入可能であり、これにより、第１係合部７５４と第２係合部７６４とは係合可能である。本実施形態において、第１係合部７５４は、第１結合形状Ｊ１に含まれる。また、第２係合部７６４は、第２結合形状Ｊ２に含まれる。なお、第１係合部７５４および第２係合部７６４は、たとえば封止樹脂７とは別部材により構成されるが、封止樹脂７の一部分により構成されてもよい。 In the present embodiment, the first engaging portion 754 is provided on the third resin side surface 75 and has a concave connector shape recessed from the third resin side surface 75 in the y2 direction. In the illustrated example, the first engaging portions 754 are provided at two locations separated in the x direction. The second engaging portion 764 is provided on the fourth resin side surface 76 and has a convex connector shape that protrudes in the y2 direction. In the illustrated example, the second engaging portions 764 are provided at two locations separated in the x direction. The second engaging part 764 can be fitted into the corresponding first engaging part 754, so that the first engaging part 754 and the second engaging part 764 can be engaged with each other. In this embodiment, the first engaging portion 754 is included in the first coupling shape J1. Further, the second engaging portion 764 is included in the second joint shape J2. Note that the first engaging portion 754 and the second engaging portion 764 are configured by a separate member from the sealing resin 7, for example, but may be configured by a portion of the sealing resin 7.
　図２５に示すように、第３接続部４５は、半導体装置Ａ５０において、ｙ１方向に配置されている。第３接続部４５は、第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂのいずれかと導通する。図２５に示した例では、４つの第３接続部４５が設けられている。各第３接続部４５はピン状端子であり、２つの第３接続部４５が一方の第１係合部７５４に配置され、他の２つの第３接続部４５が他方の第１係合部７５４に配置されている。詳細な図示説明は省略するが、たとえば、ｘ１方向寄りの第１係合部７５４に配置された２つの第３接続部４５は、第１スイッチング素子１０Ａに導通している。そのうち一方の第３接続部４５は第１スイッチング素子１０Ａの第１主面電極１１（ゲート電極）に導通し、他方の第３接続部４５は第１スイッチング素子１０Ａの第２主面電極１２（ソース電極）に導通する。また、ｘ２方向寄りの第１係合部７５４に配置された２つの第３接続部４５は、第２スイッチング素子１０Ｂに導通している。そのうち一方の第３接続部４５は第２スイッチング素子１０Ｂの第１主面電極１１（ゲート電極）に導通し、他方の第３接続部４５は第２スイッチング素子１０Ｂの第２主面電極１２（ソース電極）に導通する。 As shown in FIG. 25, the third connection portion 45 is arranged in the y1 direction in the semiconductor device A50. The third connection portion 45 is electrically connected to either the first switching element 10A or the second switching element 10B. In the example shown in FIG. 25, four third connecting portions 45 are provided. Each of the third connecting parts 45 is a pin-shaped terminal, and two third connecting parts 45 are arranged in one first engaging part 754, and the other two third connecting parts 45 are arranged in the other first engaging part 754. 754. Although detailed illustrations and explanations are omitted, for example, the two third connecting portions 45 disposed in the first engaging portion 754 closer to the x1 direction are electrically connected to the first switching element 10A. One of the third connection parts 45 is electrically connected to the first main surface electrode 11 (gate electrode) of the first switching element 10A, and the other third connection part 45 is electrically connected to the second main surface electrode 12 (gate electrode) of the first switching element 10A. source electrode). Further, the two third connecting portions 45 arranged in the first engaging portion 754 closer to the x2 direction are electrically connected to the second switching element 10B. One of the third connection parts 45 is electrically connected to the first main surface electrode 11 (gate electrode) of the second switching element 10B, and the other third connection part 45 is electrically connected to the second main surface electrode 12 (gate electrode) of the second switching element 10B. source electrode).
　図２４に示すように、第４接続部４６は、半導体装置Ａ５０において、ｙ２方向に配置されている。第４接続部４６は、第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂのいずれかと導通する。図２４に示した例では、４つの第４接続部４６が設けられている。各第４接続部４６は、凹状端子であり、２つの第４接続部４６が一方の第２係合部７６４に配置され、他の２つの第４接続部４６が他方の第２係合部７６４に配置されている。詳細な図示説明は省略するが、たとえば、ｘ１方向寄りの第２係合部７６４に配置された２つの第４接続部４６は、第１スイッチング素子１０Ａに導通している。そのうち一方の第４接続部４６は第１スイッチング素子１０Ａの第１主面電極１１（ゲート電極）に導通し、他方の第４接続部４６は第１スイッチング素子１０Ａの第２主面電極１２（ソース電極）に導通する。また、ｘ２方向寄りの第２係合部７６４に配置された２つの第４接続部４６は、第２スイッチング素子１０Ｂに導通している。そのうち一方の第４接続部４６は第２スイッチング素子１０Ｂの第１主面電極１１（ゲート電極）に導通し、他方の第４接続部４６は第２スイッチング素子１０Ｂの第２主面電極１２（ソース電極）に導通する。上記の第１係合部７５４と第２係合部７６４とが係合するとき、第３接続部４５と、これに対応する第４接続部４６とが導通接続される。 As shown in FIG. 24, the fourth connection portion 46 is arranged in the y2 direction in the semiconductor device A50. The fourth connection portion 46 is electrically connected to either the first switching element 10A or the second switching element 10B. In the example shown in FIG. 24, four fourth connection parts 46 are provided. Each fourth connection part 46 is a concave terminal, and two fourth connection parts 46 are arranged in one second engagement part 764, and the other two fourth connection parts 46 are arranged in the other second engagement part 764. 764. Although detailed illustrations and explanations are omitted, for example, the two fourth connecting portions 46 disposed on the second engaging portion 764 closer to the x1 direction are electrically connected to the first switching element 10A. One of the fourth connection parts 46 is electrically connected to the first main surface electrode 11 (gate electrode) of the first switching element 10A, and the other fourth connection part 46 is electrically connected to the second main surface electrode 12 (gate electrode) of the first switching element 10A. source electrode). Further, the two fourth connecting portions 46 arranged in the second engaging portion 764 closer to the x2 direction are electrically connected to the second switching element 10B. One of the fourth connection parts 46 is electrically connected to the first main surface electrode 11 (gate electrode) of the second switching element 10B, and the other fourth connection part 46 is electrically connected to the second main surface electrode 12 (gate electrode) of the second switching element 10B. source electrode). When the first engaging portion 754 and the second engaging portion 764 are engaged, the third connecting portion 45 and the corresponding fourth connecting portion 46 are electrically connected.
　本実施形態の半導体装置Ａ５０によれば、２つのみのスイッチング素子１０（第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂ）が直列に接続されることにより、熱干渉の発生は回避され、放熱性を改善することができる。また、複数の半導体装置Ａ５０を並列接続して使用することにより、要求される様々な電流容量に対し、容易に対応させることが可能である。 According to the semiconductor device A50 of the present embodiment, since only two switching elements 10 (first switching element 10A and second switching element 10B) are connected in series, occurrence of thermal interference is avoided and heat dissipation is improved. can be improved. Furthermore, by using a plurality of semiconductor devices A50 connected in parallel, it is possible to easily accommodate various required current capacities.
　半導体装置Ａ５０においては、第１結合形状Ｊ１に含まれる第１係合部７５４と、第２結合形状Ｊ２に含まれる第２係合部７６４とを有する。第１係合部７５４と第２係合部７６４とは、互いに係合可能である。このような構成によれば、複数の半導体装置Ａ５０をｙ方向に並べて互いに組み合わせることで、当該複数の半導体装置Ａ５０を、機械的に連結した１つの半導体装置ユニットとして取り扱うことが可能である。また、本実施形態では、第１係合部７５４と第２係合部７６４とが係合するとき、第３接続部４５と、これに対応する第４接続部４６とが導通接続される。このような構成によれば、複数の半導体装置Ａ５０を並列接続する際、１つの半導体装置Ａ５０についてのみ制御端子４を外部との接続を図ることで、複数の半導体装置Ａ５０それぞれの第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂの駆動制御が可能である。その他にも、上記実施形態の半導体装置Ａ１０と同様の構成の範囲において、上記実施形態と同様の作用効果を奏する。 The semiconductor device A50 has a first engagement portion 754 included in the first coupling shape J1 and a second engagement portion 764 included in the second coupling shape J2. The first engaging portion 754 and the second engaging portion 764 are capable of engaging with each other. According to such a configuration, by arranging the plurality of semiconductor devices A50 in the y direction and combining them with each other, it is possible to handle the plurality of semiconductor devices A50 as one mechanically connected semiconductor device unit. Further, in this embodiment, when the first engaging portion 754 and the second engaging portion 764 engage, the third connecting portion 45 and the corresponding fourth connecting portion 46 are electrically connected. According to such a configuration, when connecting a plurality of semiconductor devices A50 in parallel, by connecting the control terminal 4 of only one semiconductor device A50 to the outside, the first switching element of each of the plurality of semiconductor devices A50 10A and the second switching element 10B can be controlled. In addition, within the range of the same configuration as the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment are achieved.
　なお、上記の半導体装置Ａ５０の変形例として、複数の制御端子４を具備しない構成としてもよい。図２６および図２７は、当該変形例に係る半導体装置Ａ５１を示している。たとえば複数の半導体装置Ａ５１を並列接続する際、第３接続部４５あるいは第４接続部４６に駆動基板のコネクタ端子を接続することで、複数の半導体装置Ａ５１それぞれの第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂの駆動制御が可能である。また、半導体装置Ａ５０と半導体装置Ａ５１とを混在させて並列接続し、１つの半導体装置ユニットとして使用することもできる。 Note that as a modification of the semiconductor device A50 described above, a configuration may be adopted in which the plurality of control terminals 4 are not provided. 26 and 27 show a semiconductor device A51 according to this modification. For example, when connecting a plurality of semiconductor devices A51 in parallel, by connecting the connector terminal of the drive board to the third connection portion 45 or the fourth connection portion 46, the first switching element 10A and the second switching element of each of the plurality of semiconductor devices A51 can be connected. Drive control of the switching element 10B is possible. Further, the semiconductor device A50 and the semiconductor device A51 can be mixed and connected in parallel to be used as one semiconductor device unit.
　本開示に係る半導体装置は、上述した実施形態に限定されるものではない。本開示に係る半導体装置の各部の具体的な構成は、種々に設計変更自在である。 The semiconductor device according to the present disclosure is not limited to the embodiments described above. The specific configuration of each part of the semiconductor device according to the present disclosure can be changed in design in various ways.
　上記実施形態において、図７に示したように２つのスイッチング素子１０（第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂ）のみを具備する構成について説明したが、本開示はこれに限定されない。本開示の半導体装置は、たとえば整流素子としてのダイオード（ショットキーバリアダイオードなど）をさらに備えた構成でもよい。たとえば図２８に示すように、直列に接続された２つの第１スイッチング素子１０Ａおよび第２スイッチング素子１０Ｂに対し、２つのショットキーバリアダイオードＳＢＤ１，ＳＢＤ２が個別に並列接続された構成を採用してもよい。 In the above embodiment, a configuration including only two switching elements 10 (first switching element 10A and second switching element 10B) as shown in FIG. 7 has been described, but the present disclosure is not limited thereto. The semiconductor device of the present disclosure may be configured to further include, for example, a diode (such as a Schottky barrier diode) as a rectifying element. For example, as shown in FIG. 28, a configuration is adopted in which two Schottky barrier diodes SBD1 and SBD2 are individually connected in parallel to two first switching elements 10A and second switching elements 10B connected in series. Good too.
　本開示は、以下の付記に関する構成を含む。 The present disclosure includes configurations related to the following additional notes.
　　付記１．
　２つのみのスイッチング素子と、前記２つのみのスイッチング素子を覆う封止樹脂と、を備え、
　前記２つのみのスイッチング素子は、一方が第１スイッチング素子、他方が第２スイッチング素子であり、
　前記第１スイッチング素子および前記第２スイッチング素子の各々は、ＳｉＣを構成材料として含み、
　前記第１スイッチング素子と前記第２スイッチング素子とは、前記第１スイッチング素子を上アーム、前記第２スイッチング素子を下アームとして、直列に接続されている、半導体装置。
　　付記２．
　主電流が流れる複数の主端子をさらに備え、
　前記複数の主端子は、前記封止樹脂に対して第１方向の一方側に位置する第１主端子を含む、付記１に記載の半導体装置。
　　付記３．
　前記第１方向に対して直交する第２方向の一方側に配置された第１結合形状と、
　前記第２方向の他方側に配置された第２結合形状と、をさらに備え、
　前記第１結合形状と前記第２結合形状とは、組み合わせることが可能である、付記２に記載の半導体装置。
　　付記４．
　前記封止樹脂は、前記第１方向および前記第２方向に直交する厚さ方向の一方側を向く樹脂主面と、前記第１方向の一方側および他方側を向く第１樹脂側面および第２樹脂側面と、前記第２方向の一方側および他方側を向く第３樹脂側面および第４樹脂側面と、を有する、付記３に記載の半導体装置。
　　付記５．
　前記複数の主端子は、前記封止樹脂に対して前記第１方向の他方側に位置する第２主端子と、前記封止樹脂に対して前記第１方向の一方側に位置する第３主端子と、を含む、付記４に記載の半導体装置。
　　付記６．
　前記第１スイッチング素子および前記第２スイッチング素子を制御するための複数の制御端子をさらに備え、
　前記封止樹脂は、前記第３樹脂側面から前記第２方向の他方側に凹む少なくとも１つの側面凹部を有し、
　前記複数の制御端子は、前記第４樹脂側面から突出し、且つ前記第２方向に見て前記少なくとも１つの側面凹部と重なり、
　前記少なくとも１つの側面凹部は、前記第１結合形状に含まれ、
　前記複数の制御端子は、前記第２結合形状に含まれる、付記４に記載の半導体装置。
　　付記７．
　前記複数の主端子は、前記第４樹脂側面から突出する第２主端子を含み、
　前記第２主端子は、前記第２方向に見て前記少なくとも１つの側面凹部と重なり、
　前記第２主端子は、前記第２結合形状に含まれる、付記６に記載の半導体装置。
　　付記８．
　前記第３樹脂側面には、第１係合部が設けられ、且つ前記第４樹脂側面には、第２係合部が設けられており、
　前記第１係合部と前記第２係合部とは、互いに係合可能であり、
　前記第１係合部は、前記第１結合形状に含まれ、
　前記第２係合部は、前記第２結合形状に含まれる、付記４に記載の半導体装置。
　　付記９．
　前記封止樹脂は、前記第３樹脂側面に設けられた第１位置合わせ部と、前記第４樹脂側面に設けられた第２位置合わせ部と、を有し、
　前記第１位置合わせ部は、前記第１結合形状に含まれ、
　前記第２位置合わせ部は、前記第２結合形状に含まれ、
　前記第１位置合わせ部と前記第２位置合わせ部が位置合わせされたときに、前記第１係合部と前記第２係合部とが互いに係合する、付記８に記載の半導体装置。
　　付記１０．
　前記第１スイッチング素子および前記第２スイッチング素子を制御するための複数の制御端子をさらに備え、
　前記複数の制御端子は、前記樹脂主面から突出する、付記８に記載の半導体装置。
　　付記１１．
　前記樹脂主面には、前記第１スイッチング素子および前記第２スイッチング素子の少なくともいずれかと導通する第１接続部が配置されている、付記８に記載の半導体装置。
　　付記１２．
　前記樹脂主面には、前記第１スイッチング素子および前記第２スイッチング素子の少なくともいずれかと導通する第２接続部が配置されており、
　前記第２接続部は、前記第１接続部に対して前記第２方向に離隔して配置される、付記１１に記載の半導体装置。
　　付記１３．
　前記第１スイッチング素子および前記第２スイッチング素子を制御するための複数の制御端子をさらに備え、
　前記複数の制御端子の各々は、前記第１接続部に取りけられている、付記１１に記載の半導体装置。
　　付記１４．
　前記第２方向の一方側には第３接続部が設けられ、且つ前記第２方向の他方側には第４接続部が設けられており、
　前記第３接続部および前記第４接続部の各々は、前記第１スイッチング素子および前記第２スイッチング素子の少なくともいずれかと導通しており、
　前記第１係合部と前記第２係合部とが互いに係合するときに、前記第３接続部と前記第４接続部とが導通接続される、付記８に記載の半導体装置。
　　付記１５．
　前記第１スイッチング素子および前記第２スイッチング素子を制御するための複数の制御端子をさらに備え、
　前記複数の制御端子は、前記樹脂主面から突出する、付記１４に記載の半導体装置。
　　付記１６．
　付記１ないし１５のいずれかに記載の複数の半導体装置を備え、
　前記複数の半導体装置が互いに組み合わされている、半導体装置ユニット。 Additional note 1.
comprising only two switching elements and a sealing resin that covers the only two switching elements,
Of the only two switching elements, one is a first switching element and the other is a second switching element,
Each of the first switching element and the second switching element includes SiC as a constituent material,
The first switching element and the second switching element are connected in series, with the first switching element serving as an upper arm and the second switching element serving as a lower arm.
Appendix 2.
Further comprising a plurality of main terminals through which main current flows,
The semiconductor device according to appendix 1, wherein the plurality of main terminals include a first main terminal located on one side in a first direction with respect to the sealing resin.
Appendix 3.
a first joint shape disposed on one side of a second direction perpendicular to the first direction;
further comprising a second joint shape disposed on the other side of the second direction,
The semiconductor device according to appendix 2, wherein the first bond shape and the second bond shape can be combined.
Appendix 4.
The sealing resin has a resin main surface facing one side in a thickness direction perpendicular to the first direction and the second direction, and a first resin side surface and a second resin side surface facing one side and the other side in the first direction. The semiconductor device according to appendix 3, comprising a resin side surface, and a third resin side surface and a fourth resin side surface facing one side and the other side in the second direction.
Appendix 5.
The plurality of main terminals include a second main terminal located on the other side in the first direction with respect to the sealing resin, and a third main terminal located on one side in the first direction with respect to the sealing resin. The semiconductor device according to appendix 4, comprising a terminal.
Appendix 6.
further comprising a plurality of control terminals for controlling the first switching element and the second switching element,
The sealing resin has at least one side recess that is recessed from the third resin side surface to the other side in the second direction,
The plurality of control terminals protrude from the fourth resin side surface and overlap the at least one side recess when viewed in the second direction,
the at least one side recess is included in the first coupling shape;
The semiconductor device according to appendix 4, wherein the plurality of control terminals are included in the second coupling shape.
Appendix 7.
The plurality of main terminals include a second main terminal protruding from the fourth resin side surface,
The second main terminal overlaps the at least one side recess when viewed in the second direction,
The semiconductor device according to appendix 6, wherein the second main terminal is included in the second coupling shape.
Appendix 8.
A first engaging portion is provided on the third resin side surface, and a second engaging portion is provided on the fourth resin side surface,
The first engaging portion and the second engaging portion are capable of engaging with each other,
the first engagement part is included in the first coupling shape,
The semiconductor device according to appendix 4, wherein the second engaging portion is included in the second coupling shape.
Appendix 9.
The sealing resin has a first alignment portion provided on the third resin side surface and a second alignment portion provided on the fourth resin side surface,
the first alignment part is included in the first joint shape,
the second alignment part is included in the second joint shape,
The semiconductor device according to appendix 8, wherein the first engaging part and the second engaging part engage with each other when the first positioning part and the second positioning part are aligned.
Appendix 10.
further comprising a plurality of control terminals for controlling the first switching element and the second switching element,
The semiconductor device according to appendix 8, wherein the plurality of control terminals protrude from the resin main surface.
Appendix 11.
8. The semiconductor device according to appendix 8, wherein a first connection portion electrically connected to at least one of the first switching element and the second switching element is disposed on the resin main surface.
Appendix 12.
A second connection portion that is electrically connected to at least one of the first switching element and the second switching element is disposed on the resin main surface,
The semiconductor device according to appendix 11, wherein the second connection portion is spaced apart from the first connection portion in the second direction.
Appendix 13.
further comprising a plurality of control terminals for controlling the first switching element and the second switching element,
The semiconductor device according to appendix 11, wherein each of the plurality of control terminals is connected to the first connection portion.
Appendix 14.
A third connecting portion is provided on one side in the second direction, and a fourth connecting portion is provided on the other side in the second direction,
Each of the third connection part and the fourth connection part is electrically connected to at least one of the first switching element and the second switching element,
The semiconductor device according to appendix 8, wherein when the first engaging portion and the second engaging portion engage with each other, the third connecting portion and the fourth connecting portion are electrically connected.
Appendix 15.
further comprising a plurality of control terminals for controlling the first switching element and the second switching element,
The semiconductor device according to appendix 14, wherein the plurality of control terminals protrude from the resin main surface.
Appendix 16.
comprising a plurality of semiconductor devices according to any one of appendices 1 to 15,
A semiconductor device unit in which the plurality of semiconductor devices are combined with each other.
Ａ１０，Ａ１１，Ａ１２，Ａ１３，Ａ２０，Ａ３０，Ａ４０，Ａ５０，Ａ５１：半導体装置
Ｂ１０，Ｂ１１，Ｂ２０，Ｂ３０，Ｂ４０，Ｂ４１：半導体装置ユニット
１０：スイッチング素子　　　１０Ａ：第１スイッチング素子
１０Ｂ：第２スイッチング素子　　　１０１：素子主面
１０２：素子裏面　　　１１：第１主面電極
１２：第２主面電極　　　１３：裏面電極
１９：導電性接合材　　　２：導電支持体
２Ａ：第１導電部　　　２Ｂ：第２導電部
２０１：主面　　　２０２：裏面
２９：導電性接合材　　　３：支持基板
３０１：支持面　　　３０２：底面
３１：絶縁層　　　３２：第１金属層
３２Ａ：第１部分　　　３２Ｂ：第２部分
３３：第２金属層　　　４：制御端子
４１Ａ，４１Ｂ：第１制御端子　　　４２Ａ，４２Ｂ：第２制御端子
４３：第１接続部　　　４４：第２接続部
４５：第３接続部　　　４６：第４接続部
４７，４８：接続部材　　　５１：第１導通部材
５１１：接続部　　　５１２：第１主端子
５２：第２導通部材　　　５２１：接続部
５２２：第２主端子　　　５３：第３導通部材
５３１：接続部　　　５３２：第３主端子
５４：第４導通部材　　　５９：導電性接合材
６１，６２：ワイヤ　　　７：封止樹脂
７１：樹脂主面　　　７２：樹脂裏面
７３：第１樹脂側面　　　７４：第２樹脂側面
７５：第３樹脂側面　　　７５１：側面凹部
７５２，７５３，７５４：第１係合部　　　７５８：第１位置合わせ部
７６：第４樹脂側面　　　７６２，７６３，７６４：第２係合部
７６８：第２位置合わせ部　　　８０：駆動基板
Ｊ１：第１結合形状　　　Ｊ２：第２結合形状 A10, A11, A12, A13, A20, A30, A40, A50, A51: Semiconductor device B10, B11, B20, B30, B40, B41: Semiconductor device unit 10: Switching element 10A: First switching element 10B: Second switching Element 101: Element principal surface 102: Element back surface 11: First principal surface electrode 12: Second principal surface electrode 13: Back electrode 19: Conductive bonding material 2: Conductive support 2A: First conductive part 2B: Second conductive Part 201: Main surface 202: Back surface 29: Conductive bonding material 3: Support substrate 301: Support surface 302: Bottom surface 31: Insulating layer 32: First metal layer 32A: First portion 32B: Second portion 33: Second metal Layer 4: Control terminals 41A, 41B: First control terminals 42A, 42B: Second control terminals 43: First connection section 44: Second connection section 45: Third connection section 46: Fourth connection section 47, 48: Connection Member 51: First conductive member 511: Connection portion 512: First main terminal 52: Second conductive member 521: Connection portion 522: Second main terminal 53: Third conductive member 531: Connection portion 532: Third main terminal 54 : Fourth conductive member 59: Conductive bonding material 61, 62: Wire 7: Sealing resin 71: Resin main surface 72: Resin back surface 73: First resin side surface 74: Second resin side surface 75: Third resin side surface 751: Side recesses 752, 753, 754: First engaging portion 758: First positioning portion 76: Fourth resin side surface 762, 763, 764: Second engaging portion 768: Second positioning portion 80: Drive board J1: 1st joint shape J2: 2nd joint shape

Claims (16)

  1. 　２つのみのスイッチング素子と、前記２つのみのスイッチング素子を覆う封止樹脂と、を備え、
    　前記２つのみのスイッチング素子は、一方が第１スイッチング素子、他方が第２スイッチング素子であり、
    　前記第１スイッチング素子および前記第２スイッチング素子の各々は、ＳｉＣを構成材料として含み、
    　前記第１スイッチング素子と前記第２スイッチング素子とは、前記第１スイッチング素子を上アーム、前記第２スイッチング素子を下アームとして、直列に接続されている、半導体装置。     comprising only two switching elements and a sealing resin that covers the only two switching elements,
    Of the only two switching elements, one is a first switching element and the other is a second switching element,
    Each of the first switching element and the second switching element includes SiC as a constituent material,
    The first switching element and the second switching element are connected in series, with the first switching element serving as an upper arm and the second switching element serving as a lower arm.
  2. 　主電流が流れる複数の主端子をさらに備え、
    　前記複数の主端子は、前記封止樹脂に対して第１方向の一方側に位置する第１主端子を含む、請求項１に記載の半導体装置。     Further comprising a plurality of main terminals through which main current flows,
    The semiconductor device according to claim 1, wherein the plurality of main terminals include a first main terminal located on one side in a first direction with respect to the sealing resin.
  3. 　前記第１方向に対して直交する第２方向の一方側に配置された第１結合形状と、
    　前記第２方向の他方側に配置された第２結合形状と、をさらに備え、
    　前記第１結合形状と前記第２結合形状とは、組み合わせることが可能である、請求項２に記載の半導体装置。     a first joint shape disposed on one side of a second direction perpendicular to the first direction;
    further comprising a second joint shape disposed on the other side of the second direction,
    3. The semiconductor device according to claim 2, wherein the first bond shape and the second bond shape can be combined.
  4. 　前記封止樹脂は、前記第１方向および前記第２方向に直交する厚さ方向の一方側を向く樹脂主面と、前記第１方向の一方側および他方側を向く第１樹脂側面および第２樹脂側面と、前記第２方向の一方側および他方側を向く第３樹脂側面および第４樹脂側面と、を有する、請求項３に記載の半導体装置。 The sealing resin has a resin main surface facing one side in a thickness direction perpendicular to the first direction and the second direction, and a first resin side surface and a second resin side surface facing one side and the other side in the first direction. 4. The semiconductor device according to claim 3, comprising a resin side surface, and a third resin side surface and a fourth resin side surface facing one side and the other side in the second direction.
  5. 　前記複数の主端子は、前記封止樹脂に対して前記第１方向の他方側に位置する第２主端子と、前記封止樹脂に対して前記第１方向の一方側に位置する第３主端子と、を含む、請求項４に記載の半導体装置。 The plurality of main terminals include a second main terminal located on the other side in the first direction with respect to the sealing resin, and a third main terminal located on one side in the first direction with respect to the sealing resin. The semiconductor device according to claim 4, comprising: a terminal.
  6. 　前記第１スイッチング素子および前記第２スイッチング素子を制御するための複数の制御端子をさらに備え、
    　前記封止樹脂は、前記第３樹脂側面から前記第２方向の他方側に凹む少なくとも１つの側面凹部を有し、
    　前記複数の制御端子は、前記第４樹脂側面から突出し、且つ前記第２方向に見て前記少なくとも１つの側面凹部と重なり、
    　前記少なくとも１つの側面凹部は、前記第１結合形状に含まれ、
    　前記複数の制御端子は、前記第２結合形状に含まれる、請求項４に記載の半導体装置。     further comprising a plurality of control terminals for controlling the first switching element and the second switching element,
    The sealing resin has at least one side recess that is recessed from the third resin side surface to the other side in the second direction,
    The plurality of control terminals protrude from the fourth resin side surface and overlap the at least one side recess when viewed in the second direction,
    the at least one side recess is included in the first coupling shape;
    5. The semiconductor device according to claim 4, wherein the plurality of control terminals are included in the second coupling shape.
  7. 　前記複数の主端子は、前記第４樹脂側面から突出する第２主端子を含み、
    　前記第２主端子は、前記第２方向に見て前記少なくとも１つの側面凹部と重なり、
    　前記第２主端子は、前記第２結合形状に含まれる、請求項６に記載の半導体装置。     The plurality of main terminals include a second main terminal protruding from the fourth resin side surface,
    The second main terminal overlaps the at least one side recess when viewed in the second direction,
    7. The semiconductor device according to claim 6, wherein the second main terminal is included in the second coupling shape.
  8. 　前記第３樹脂側面には、第１係合部が設けられ、且つ前記第４樹脂側面には、第２係合部が設けられており、
    　前記第１係合部と前記第２係合部とは、互いに係合可能であり、
    　前記第１係合部は、前記第１結合形状に含まれ、
    　前記第２係合部は、前記第２結合形状に含まれる、請求項４に記載の半導体装置。     A first engaging portion is provided on the third resin side surface, and a second engaging portion is provided on the fourth resin side surface,
    The first engaging portion and the second engaging portion are capable of engaging with each other,
    the first engagement part is included in the first coupling shape,
    5. The semiconductor device according to claim 4, wherein the second engaging portion is included in the second joint shape.
  9. 　前記封止樹脂は、前記第３樹脂側面に設けられた第１位置合わせ部と、前記第４樹脂側面に設けられた第２位置合わせ部と、を有し、
    　前記第１位置合わせ部は、前記第１結合形状に含まれ、
    　前記第２位置合わせ部は、前記第２結合形状に含まれ、
    　前記第１位置合わせ部と前記第２位置合わせ部が位置合わせされたときに、前記第１係合部と前記第２係合部とが互いに係合する、請求項８に記載の半導体装置。     The sealing resin has a first alignment portion provided on the third resin side surface and a second alignment portion provided on the fourth resin side surface,
    the first alignment part is included in the first joint shape,
    the second alignment part is included in the second joint shape,
    9. The semiconductor device according to claim 8, wherein when the first alignment part and the second alignment part are aligned, the first engagement part and the second engagement part engage with each other.
  10. 　前記第１スイッチング素子および前記第２スイッチング素子を制御するための複数の制御端子をさらに備え、
    　前記複数の制御端子は、前記樹脂主面から突出する、請求項８に記載の半導体装置。     further comprising a plurality of control terminals for controlling the first switching element and the second switching element,
    9. The semiconductor device according to claim 8, wherein the plurality of control terminals protrude from the resin main surface.
  11. 　前記樹脂主面には、前記第１スイッチング素子および前記第２スイッチング素子の少なくともいずれかと導通する第１接続部が配置されている、請求項８に記載の半導体装置。 9. The semiconductor device according to claim 8, wherein a first connection portion electrically connected to at least one of the first switching element and the second switching element is arranged on the resin main surface.
  12. 　前記樹脂主面には、前記第１スイッチング素子および前記第２スイッチング素子の少なくともいずれかと導通する第２接続部が配置されており、
    　前記第２接続部は、前記第１接続部に対して前記第２方向に離隔して配置される、請求項１１に記載の半導体装置。     A second connection portion that is electrically connected to at least one of the first switching element and the second switching element is disposed on the resin main surface,
    12. The semiconductor device according to claim 11, wherein the second connection portion is spaced apart from the first connection portion in the second direction.
  13. 　前記第１スイッチング素子および前記第２スイッチング素子を制御するための複数の制御端子をさらに備え、
    　前記複数の制御端子の各々は、前記第１接続部に取りけられている、請求項１１に記載の半導体装置。     further comprising a plurality of control terminals for controlling the first switching element and the second switching element,
    12. The semiconductor device according to claim 11, wherein each of the plurality of control terminals is connected to the first connection portion.
  14. 　前記第２方向の一方側には第３接続部が設けられ、且つ前記第２方向の他方側には第４接続部が設けられており、
    　前記第３接続部および前記第４接続部の各々は、前記第１スイッチング素子および前記第２スイッチング素子の少なくともいずれかと導通しており、
    　前記第１係合部と前記第２係合部とが互いに係合するときに、前記第３接続部と前記第４接続部とが導通接続される、請求項８に記載の半導体装置。     A third connecting portion is provided on one side in the second direction, and a fourth connecting portion is provided on the other side in the second direction,
    Each of the third connection part and the fourth connection part is electrically connected to at least one of the first switching element and the second switching element,
    9. The semiconductor device according to claim 8, wherein when the first engaging part and the second engaging part engage with each other, the third connecting part and the fourth connecting part are electrically connected.
  15. 　前記第１スイッチング素子および前記第２スイッチング素子を制御するための複数の制御端子をさらに備え、
    　前記複数の制御端子は、前記樹脂主面から突出する、請求項１４に記載の半導体装置。     further comprising a plurality of control terminals for controlling the first switching element and the second switching element,
    15. The semiconductor device according to claim 14, wherein the plurality of control terminals protrude from the resin main surface.
  16. 　請求項１ないし１５のいずれかに記載の複数の半導体装置を備え、
    　前記複数の半導体装置が互いに組み合わされている、半導体装置ユニット。     comprising a plurality of semiconductor devices according to any one of claims 1 to 15,
    A semiconductor device unit in which the plurality of semiconductor devices are combined with each other.
PCT/JP2023/022739 2022-07-05 2023-06-20 Semiconductor device and semiconductor device unit WO2024009753A1 (en)

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