WO2024007914A1 - Sram控制系统、方法、fpga芯片及电子设备 - Google Patents

Sram控制系统、方法、fpga芯片及电子设备 Download PDF

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Publication number
WO2024007914A1
WO2024007914A1 PCT/CN2023/103247 CN2023103247W WO2024007914A1 WO 2024007914 A1 WO2024007914 A1 WO 2024007914A1 CN 2023103247 W CN2023103247 W CN 2023103247W WO 2024007914 A1 WO2024007914 A1 WO 2024007914A1
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module
control
sram
bus
signal
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PCT/CN2023/103247
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English (en)
French (fr)
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贝宇
刘蒲霞
傅启攀
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深圳市紫光同创电子有限公司
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Publication of WO2024007914A1 publication Critical patent/WO2024007914A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of integrated circuit technology, and more specifically, to an SRAM control system, method, FPGA chip and electronic equipment.
  • SRAM Static Random Access Memory
  • DRAM dynamic random access memory
  • this application proposes a SRAM control system, method, FPGA chip and electronic equipment.
  • inventions of the present application provide an SRAM control system.
  • the system includes: a main control module, at least one SRAM control module and a bus module; the bus module is used to connect the main control module and at least one SRAM control module; wherein at least one SRAM control module and the main control module perform data transmission through the main line module.
  • the SRAM control system can have the ability to expand subsequent devices while realizing the ability to control multiple SRAM control circuits, so that it can be more widely used in various scenarios.
  • embodiments of the present application provide a control method for an SRAM control system. Should The method includes: at least one SRAM control module receives a bus signal from the bus module; the bus signal is sent from the main control module to the bus module; and based on the bus signal, data is transmitted through the bus module and the main control module. Through the transmission of bus signals in the bus module, the access and control of one main control module to at least one SRAM control module is realized.
  • embodiments of the present application also provide a control method for an SRAM control system.
  • the method includes: the main control module sends a bus signal to the bus module; at least one SRAM control module receives the bus signal transmitted by the bus module; at least one SRAM control module transmits data through the bus module and the main control module based on the bus signal. Data transmission is carried out through the bus module and the main control module. Through the transmission of bus signals in the bus module, the access and control of one main control module to at least one SRAM control module is realized.
  • embodiments of the present application provide an FPGA chip, which includes the above control system.
  • embodiments of the present application provide an electronic device, which includes a device body and the above-mentioned FPGA chip disposed on the device body.
  • the SRAM control system includes: a main control module, at least one SRAM control module and a bus module; the bus module is used to connect the main control module and at least one SRAM control module; wherein, at least one SRAM control module and the main control module The module transmits data through the mainline module.
  • the SRAM control system can control multiple SRAM control circuits, and has the ability to expand subsequent devices, so that it can be more widely used in various application scenarios.
  • Figure 1 shows a schematic structural diagram of an SRAM control system proposed in an embodiment of the present application.
  • FIG. 2 shows a schematic structural diagram of an SRAM control module proposed in an embodiment of the present application.
  • Figure 3 shows the flow of a control method for an SRAM control system proposed by the embodiment of the present application. Schematic diagram.
  • FIG. 4 shows a schematic flowchart of another control method of an SRAM control system proposed by an embodiment of the present application.
  • Figure 5 shows a timing diagram of a bus signal proposed in an embodiment of the present application.
  • Figure 6 shows a timing diagram of another bus signal provided by an embodiment of the present application.
  • FIG. 7 shows a schematic structural diagram of an FPGA chip proposed in an embodiment of the present application.
  • FIG. 8 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • SRAM Static Random Access Memory; static random access memory
  • DRAM Dynamic Random Access Memory; dynamic random access memory
  • the data stored in SRAM can be maintained constantly when it is powered on. At the same operating frequency, the data stored in SRAM can be processed much faster than DRAM. Much speed is read. Therefore, SRAM is widely used in areas of integrated circuits (such as FPGA chips) and electronic equipment that require high-speed reading and writing of data.
  • the main control module directly accesses the single SRAM control circuit through the control signal specified by the SRAM control circuit.
  • the main control module accesses each SRAM control circuit through multiple control signals.
  • the main control module adds an arbitration module between the main control module and the SRAM control circuit to arbitrate and distribute the control signals output from the main control module, and then access each SRAM control circuit. .
  • the inventor of the present application found that the existing access method of the SRAM control circuit is not suitable for the FPGA chip field where the update and iteration speed is accelerating.
  • the first method of accessing SRAM control circuits has the disadvantage that it is not suitable for access scenarios of multiple SRAM control circuits and is difficult to expand subsequent devices.
  • the second access to the SRAM control circuit The question method has the disadvantages of increasing the difficulty of top-level integration and making it difficult to expand subsequent devices.
  • the third access method to the SRAM control circuit has the disadvantage of increasing the complexity of the arbitration module and making it inconvenient to expand.
  • the SRAM control system includes: a main control module, at least one SRAM control module and a bus module.
  • the bus module is used for Connect the main control module and at least one SRAM control module; wherein, at least one SRAM control module and the main control module perform data transmission through the main line module.
  • an embodiment of the present application provides an SRAM control system 100 .
  • the SRAM control system 100 includes: a main control module 110 , a bus module 120 and at least one SRAM control module 130 .
  • the bus module 120 is used to connect the main control module 110 and at least one SRAM control module 130 .
  • the bus module 120 can perform data transmission between the main control module 110 and at least the SRAM control module 130 . That is, the bus module 120 can transmit the data sent by the main control module 110 to the corresponding SRAM control module 120, and the bus module 120 can also transmit the data sent by the SRAM control module 120 to the main control module 110.
  • the bus protocol corresponding to the bus module 120 can be set in advance, and the bus module 120 performs data transmission according to the bus protocol.
  • the bus module 120 may include an address bus, a data bus and a control bus.
  • the address bus is used to transmit address signals, for example, to transmit the address of the SRAM control module 130 that the main control module 110 needs to perform data transmission.
  • the data bus is used to transmit data signals, such as read data signals obtained from the SRAM control module 120; and write data signals written to the SRAM control module 120.
  • a control bus is used to transmit control signals.
  • the control signal is, for example, a read/write control signal, used to determine the data transmission direction; and a write data valid signal, used to determine the validity of the written data.
  • the SRAM control module 130 is connected to the bus module 120; the number of the SRAM control module 130 is at least one. It can be understood that the bus module 120 can be connected to multiple SRAM control modules 130, and each The SRAM control modules 130 work independently of each other; the SRAM control module 130 is used to receive bus signals, complete relevant data reading and writing according to the bus signals, and feed back the reading and writing results to the bus module 120 .
  • the number of SRAM control modules 130 can be increased or decreased according to actual usage needs, and the main control module 110 can interact with the target SRAM control module 130 through the bus module 120.
  • the main control module 110 can interact with the target SRAM control module 130 through the bus module 120.
  • the interface connected to the bus module 120 sends signals (such as address signals, control signals, data signals, etc. of the target SRAM control module).
  • the bus module 120 transmits signals according to the bus protocol.
  • the SRAM control module 130 includes: an interface sub-module 131 , a main control sub-module 132 and an SRAM control circuit 133 .
  • the interface sub-module 131 is connected to the bus module 120, and the interface sub-module 131 is also connected to the main control sub-module 132.
  • the interface sub-module 131 is used to receive bus signals transmitted by the bus module 120 and transmit the corresponding bus signals to the main control sub-module 132 .
  • the main control sub-module 132 is also connected to the SRAM control circuit 133; the main control sub-module 132 is used to control the SRAM control circuit 133 to complete corresponding operations according to the bus signal. For example, reading data or writing data, etc.
  • the SRAM control circuit 133 is connected to the main control sub-module 132, and the SRAM control circuit 133 is used to access the SRAM and complete read and write operations.
  • a method for controlling an SRAM control module provided by an embodiment of the present application can be applied to the above-mentioned SRAM control module 100.
  • This embodiment describes a step process on the SRAM control module 100 side. The method includes: steps 210 to step 220.
  • Step 210 At least one SRAM control module receives the bus signal transmitted by the bus module, and the bus signal is sent to the bus module by the main control module.
  • the SRAM control module includes: an interface sub-module, a main control sub-module and an SRAM control circuit; wherein the interface sub-module is connected to the bus module, the main control sub-module is connected to the interface sub-module, and the SRAM control circuit is connected to in the main control submodule.
  • the bus signals include: control address signals, control signals and data signals.
  • control address signal may include a propagation type field segment used to mark the propagation type of the bus signal.
  • the byte length of the propagation type field segment can be set according to actual usage needs, and this application does not limit this.
  • the propagation type may include point-to-point transmission, that is, a single main control module controls a single SRAM control module.
  • the propagation type may also include a broadcast propagation method, that is, a single main control module controls multiple (or all) SRAM control modules.
  • the propagation type may also include a multicast propagation method, that is, a single main control module controls the SRAM control module belonging to the target group.
  • SRAM control modules can be assigned to multiple groups in advance. Different groups can be identified by setting group numbers. SRAM control modules in the same group can be controlled uniformly.
  • control address signal may include an ID (Identity document identification number) address field segment, which is used to mark the address of the SRAM control module that needs to be controlled. It can be understood that each SRAM control module has unique corresponding ID address information, and the SRAM control module can be controlled through the ID address information corresponding to the SRAM control module. Specifically, the byte length of the ID address field segment can be set according to actual usage needs, and this application does not limit this.
  • ID Identity document identification number
  • control address signal may include register address field segment information used to mark the address of a target register of the SRAM control module that needs to be controlled. It can be understood that the register of each SRAM control module has a unique corresponding register address, and the register can be accessed through the register address corresponding to the register. Specifically, the byte length of the register address can be set according to actual usage needs, and this application does not limit this.
  • control signals may include read and write control signals.
  • the read and write control signals are used to mark the current data transmission direction, that is, the current read operation or write operation is performed on the SRAM.
  • the transmission directions of the read and write control signals can be distinguished through different level values. For example, when the level value of the read-write control signal is high level, it represents a write operation; when the level value of the read-write control signal is low level, it represents a read operation.
  • main control module when the main control module needs to perform a data read operation on the SRAM, it outputs a low-level read Write control signal; when the main control module needs to perform a write data operation on the SRAM, it outputs a high-level read and write control signal.
  • control signal may also include a read data valid signal, and the read data valid signal is used to identify whether the currently transmitted read data is valid. For example, when the read data valid signal is high level, it is used to identify that the currently transmitted read data is valid. When the read data valid signal is low level, it is used to identify that the currently transmitted read data is invalid. The details can be adjusted according to actual use needs, and this application does not limit this.
  • control signal may also include a write data valid signal, and the write data valid signal is used to identify whether the currently transmitted write data is valid. For example, when the write data valid signal is high level, it is used to identify that the currently transmitted write data is valid. When the write data valid signal is low level, it is used to identify that the currently transmitted write data is invalid. The details can be adjusted according to actual use needs, and this application does not limit this.
  • the data signal may include a read data signal.
  • the read data signal represents the data read by the main control module from the SRAM control module.
  • the data signal may also include a write data signal.
  • the write data signal represents the data written by the main control module to the SRAM control module.
  • the main control module can output corresponding signals to the bus module through different interfaces, and changes in the number of SRAM control modules will not affect the structure or interface settings of the main control module.
  • the addition or deletion of SRAM control modules only affects It needs to be connected or disconnected from the bus module, and the main control module can be distinguished by a specific ID address.
  • the structure of the SRAM control module changes, it will not affect the main control module, which facilitates the upgrade of each module and facilitates the design and expansion of systems of different sizes.
  • Step 220 Based on the bus signal, perform data transmission through the bus module and the main control module.
  • step 220 data is transmitted between the bus module and the main control module based on the bus signal.
  • the control method of the SRAM control module provided by the embodiment of the present application may also include the following steps:
  • the interface submodule determines the control address based on the control address signal.
  • the interface submodule determines the control address according to the ID address field segment in the control address signal.
  • the main control submodule determines the transmission address according to the control address signal.
  • the above-mentioned main control sub-module determines the transmission address according to the register address field segment information in the control address signal.
  • the main control submodule determines the data transmission type according to the read and write control signals.
  • the main control submodule determines the SRAM control circuit to perform a data writing operation based on the read/write control signal.
  • the data transmission type can be point-to-point or broadcast.
  • the main control sub-module determines the SRAM control circuit to perform a data read operation based on the read-write control signal.
  • the data transmission type can be point-to-point transmission.
  • the main control sub-module controls the SRAM control circuit and the main control module to transmit data according to the data transmission type and transmission address.
  • data transmission between the SRAM control circuit and the main control module can include two transmission modes: read data and write data, and in the two data transmission modes, the main control module and the SRAM control module follow the Bus protocol for data transmission.
  • the main control module when performing a data read operation on the SRAM control circuit, sends a bus signal and a read data signal to the bus module, and the bus module transmits the bus signal and the read data signal to the corresponding module according to the control address signal in the bus signal.
  • the read and write control signals in the bus signal are in a low level state; when the SRAM control module receives the bus signal, it finds the corresponding register in the SRAM based on the register address field segment information in the control address signal in the bus signal.
  • the main control submodule then sends the read data valid signal used to indicate whether the currently transmitted data is valid and the read data signal used to mark the read data, and the read data is sent to the main control module via the bus module. control module.
  • the main control module when performing a write data operation on the SRAM control circuit, sends the bus signal and the data to be written and the write data signal used to mark the currently transmitted write data to the bus module, and the bus module
  • the control address signal in the signal transmits the bus signal, write data and write data signal to the corresponding SRAM control module.
  • the read and write control signal in the bus signal is in a high level state; when the SRAM control module receives the bus signal, it Control address signal in bus signal
  • the register address field segment information in the SRAM finds the corresponding register and performs the write data operation; the main control submodule then sends the write data valid signal used to indicate whether the currently transmitted data is valid to the main control module via the bus module.
  • step 220 data is transmitted between the bus module and the main control module based on the bus signal.
  • the control method of the SRAM control module provided by the embodiment of the present application may also include the following steps.
  • the transmission address is determined based on the control address signal.
  • the interface sub-module can determine the control address of the SRAM control module to be controlled by the main control module according to the control address signal transmitted by the bus module, and match the control address with the local address.
  • the local address is the ID address of the SRAM control module corresponding to the interface submodule, which is to determine whether the main control module wants to control the current SRAM control module.
  • the transmission address that is, the register address that needs to be controlled, is determined based on the control address signal.
  • the data transmission type includes read data type and write data type. Different data transmission types represent different data transmission methods and directions.
  • the data transmission type is a read data type, it means that the main control module reads data from the register corresponding to the transmission address.
  • the data transmission type is a write data type, it means that the main control module writes data into the register corresponding to the transmission address.
  • control method of the SRAM control system provided by the embodiment of the present application further includes: receiving the first data signal transmitted by the bus module.
  • the first data signal is sent to the bus module by the main control module.
  • the first data signal includes a write valid signal and a write data signal.
  • the main control module performs a data writing operation, it sends the first data signal to the corresponding SRAM control through the bus module module.
  • the step is to perform data transmission with the main control module according to the data transmission type and transmission address, including the following steps.
  • the write data is determined according to the first data signal.
  • the step is to perform data transmission with the main control module according to the data transmission type and transmission address, and also includes the following steps.
  • the data transfer type is a read data type
  • the data stored in the storage area corresponding to the transfer address is obtained as read data.
  • SRAM control module control method provided by an embodiment of the present application can be applied to the above-mentioned SRAM control module 100.
  • This embodiment describes the step process on the SRAM control module 100 side. The method includes: Step 210 to step 230.
  • Step 210 The main control module sends the bus signal to the bus module.
  • Step 220 At least one SRAM control module receives the bus signal transmitted by the bus module.
  • Step 230 At least one SRAM control module transmits data through the bus module and the main control module based on the bus signal.
  • FIG. 5 shows a timing diagram of a bus signal provided by an embodiment of the present application.
  • CLK represents a clock signal.
  • addr[12:11] represents the propagation type in the control address signal
  • addr[10:6] represents the ID address field segment in the control address signal
  • addr[5:0] represents the register address field segment in the control address signal
  • wdata represents writing data
  • wvalid represents a valid signal for writing data.
  • the main control module controls the read and write control signal to be 1 (high level) to indicate that the current operation is a write data operation, and the output control address signal matches the SRAM control module to be configured and the corresponding Internal register.
  • the write data valid signal is 1 (high level), indicating that the current transmission data is valid, and the configuration data (ie, write data) is output synchronously.
  • the SRAM control module will currently transmit The data is stored into the corresponding internal register.
  • FIG. 6 shows a timing diagram of another bus signal provided by an embodiment of the present application.
  • CLK represents a clock signal.
  • addr[12:11] represents the propagation type in the control address signal
  • addr[10:6] represents the ID address field segment in the control address signal
  • addr[5:0] represents the register address field segment in the control address signal
  • rdata [127:0] represents read data
  • rvalid represents the valid signal of read data.
  • the main control module controls the read and write control signal to be 0 (low level) to indicate that the current operation is a readback operation.
  • the output control address signal matches the SRAM control module to be read back and the corresponding internal register, SRAM
  • the control module outputs the readback data rdata and the readback data valid signal rvalid according to the information on the address bus.
  • An rvalid of 1 indicates that the current readback data is valid.
  • the main control module determines whether the data on the current data bus is valid data based on the rvalid signal.
  • an embodiment of the present application also provides an FPGA chip 300.
  • the FPGA chip 300 includes the above-mentioned SRAM control system.
  • At least one SRAM control module is used in the control method of the SRAM control system of the embodiment corresponding to FIG. 3 .
  • At least one SRAM control module is used in the control method of the SRAM control system of the embodiment corresponding to FIG. 4 .
  • an embodiment of the present application further provides an electronic device 400 .
  • the electronic device 400 includes a device body 410 and the above-mentioned FPGA chip 300 disposed on the device body 410 .
  • the electronic device 400 may be a mobile phone, a computer, a router, a camera device, etc., which is not limited by the present application.
  • inventions of the present application provide an SRAM control system, method, FPGA chip and electronic device.
  • the SRAM control system includes a main control module, at least one SRAM control module and a bus module.
  • the bus module is used to connect the main control module and At least one SRAM control module; wherein, at least one SRAM control module and the main control module perform data transmission through the main line module.

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Abstract

本申请公开了一种SRAM控制系统、方法、FPGA芯片及电子设备，该SRAM控制系统包括主控模块，至少一个SRAM控制模块和总线模块，总线模块用于连接主控模块与至少一个SRAM控制模块；其中，至少一个SRAM控制模块与主控模块通过主线模块进行数据传输。通过设置总线模块与SRAM控制模块，可以使SRAM控制系统实现对多个SRAM控制电路进行控制，且具备后续器件的扩展能力，从而可以更广泛地应用于各种应用场景中。

Description

SRAM控制系统、方法、FPGA芯片及电子设备
相关申请的交叉引用
本申请要求于2022年07月04日提交的申请号为2022107804770的中国申请的优先权，其在此处于所有目的通过引用将其全部内容并入本文。
技术领域
本申请涉及集成电路技术领域，更具体地，涉及一种SRAM控制系统、方法、FPGA芯片及电子设备。
背景技术
SRAM(Static Random Access Memory，静态随机存取存储器)是随机存取存储器的一种。相比较动态随机存取内存(DRAM)，SRAM具备只要保持通电通电，里面存储的数据就可以恒常保持的特性，在同样的运行频率下，在SRAM中存储的数据能以比DRAM快得多的速度被读取。
然而，现有的SRAM控制系统使用采集单一、顶层集成难度困难且后续器件不易扩展等缺陷。
申请内容
鉴于上述问题，本申请提出了一种SRAM控制系统、方法、FPGA芯片及电子设备。
第一方面，本申请实施例提供了一种SRAM控制系统。该系统包括：主控模块，至少一个SRAM控制模块和总线模块；总线模块用于连接主控模块与至少一个SRAM控制模块；其中，至少一个SRAM控制模块与主控模块通过主线模块进行数据传输。通过设置总线模块与SRAM控制模块，可以使该SRAM控制系统在实现控制多个SRAM控制电路的能力的前提下具备后续器件的扩展能力，从而可以更广泛地应用于各种场景中。
第二方面，本申请实施例提供了一种SRAM控制系统的控制方法。该 方法包括：至少一个SRAM控制模块接收总线模块的总线信号；总线信号由主控模块发送至总线模块；基于总线信号，通过总线模块与主控模块进行数据传输。通过总线信号在总线模块中的传输，实现了一个主控模块对至少一个SRAM控制模块的访问与控制。
第三方面，本申请实施例还提供了一种SRAM控制系统的控制方法。该方法包括：主控模块发送总线信号至总线模块；至少一个SRAM控制模块接收总线模块传输的总线信号；至少一个SRAM控制模块基于总线信号，通过总线模块与主控模块进行数据传输。通过总线模块与主控模块进行数据传输。通过总线信号在总线模块中的传输，实现了一个主控模块对至少一个SRAM控制模块的访问与控制。
第四方面，本申请实施例提供了一种FPGA芯片，该芯片包括上述控制系统。
第五方面，本申请实施例提供了一种电子设备，该电子设备包括设备本体以及设置于设备本体的上述FPGA芯片。
本申请提供的技术方案，SRAM控制系统包括：主控模块，至少一个SRAM控制模块和总线模块；总线模块用于连接主控模块与至少一个SRAM控制模块；其中，至少一个SRAM控制模块与主控模块通过主线模块进行数据传输。通过设置总线模块与SRAM控制模块，可以使SRAM控制系统实现对多个SRAM控制电路进行控制，且具备后续器件的扩展能力，从而可以更广泛地应用于各种应用场景中。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本申请实施例提出的一种SRAM控制系统的结构示意图。
图2示出了本申请实施例提出的一种SRAM控制模块的结构示意图。
图3示出了本申请实施例提出的一种SRAM控制系统的控制方法的流程 示意图。
图4示出了本申请实施例提出的另一种SRAM控制系统的控制方法的流程示意图。
图5示出了本申请实施例提出的一种总线信号的时序图。
图6示出了本申请实施例提供的另一种总线信号的时序图。
图7示出了本申请实施例提出的一种FPGA芯片的结构示意图。
图8示出了本申请实施例提出的一种电子设备的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
SRAM(Static Random Access Memory；静态随机存取存储器)是随机存取存储器的一种。相比较DRAM(Dynamic Random Access Memory；动态随机存取内存储器)，SRAM在保持通电时，存储的数据就可以恒常保持，在同样的运行频率下，在SRAM中存储的数据能以比DRAM快得多的速度被读取。因此，SRAM被广泛用于集成电路(如FPGA芯片)与电子设备中需要高速读写数据的区域。
目前对SRAM控制电路的访问主要有以下三种方式。
其一，对于单一SRAM控制电路的访问，主控模块直接通过SRAM控制电路规定的控制信号访问该单一SRAM控制电路。
其二，对于多SRAM控制电路的访问，主控模块通过多路控制信号访问各SRAM控制电路。
其三，对于多SRAM控制电路的访问，主控模块通过在主控模块及SRAM控制电路之间增加仲裁模块，对从主控模块输出的控制信号进行仲裁分发，进而对各SRAM控制电路进行访问。
但是本申请的发明人发现现有的SRAM控制电路的访问方式无法适用于更新迭代的速度日益加快的FPGA芯片领域。
具体而言，第一种对SRAM控制电路的访问方式存在不适用于多SRAM控制电路的访问场景且后续器件不易拓展的缺陷。第二种对SRAM控制电路的访 问方式存在顶层集成难度增加、后续器件不易拓展的缺陷。第三种对SRAM控制电路的访问方式存在仲裁模块复杂度增加的不便拓展的缺陷。
为了改善上述问题，发明人提出了本申请提出的一种SRAM控制系统、方法、FPGA芯片及电子设备，该SRAM控制系统包括：主控模块，至少一个SRAM控制模块和总线模块，总线模块用于连接主控模块与至少一个SRAM控制模块；其中，至少一个SRAM控制模块与主控模块通过主线模块进行数据传输。通过设置总线模块与SRAM控制模块，可以使SRAM控制系统实现对多个SRAM控制电路进行控制，且具备后续器件的扩展能力，从而可以更广泛地应用于各种应用场景中。
下面将通过具体实施例对本申请实施例提供的SRAM控制系统、方法、FPGA芯片及电子设备进行详细说明。
请参阅图1，本申请实施例提供一种SRAM控制系统100，该SRAM控制系统100包括：主控模块110、总线模块120与至少一个SRAM控制模块130。
在本申请的实施例中，总线模块120用于连接主控模块110与至少一个SRAM控制模块130。总线模块120可以为主控模块110与至少也SRAM控制模块130进行数据传输。即总线模块120可以将主控模块110发送的数据传输给对应的SRAM控制模块120，总线模块120也可以将SRAM控制模块120发送的数据传输给主控模块110
在本申请的实施例中，可以预先设置总线模块120对应的总线协议，总线模块120根据总线协议进行数据传输。
在本申请的实施例中，总线模块120可以包括地址总线、数据总线和控制总线。
在一些实施方式中，地址总线用于传输地址信号，例如用于传输主控模块110需要进行数据传输的SRAM控制模块130的地址。
在一些实施方式中，数据总线用于传输数据信号，数据信号例如从SRAM控制模块120获取的读数据信号；又如写入SRAM控制模块120的写数据信号。
在一些实施方式中，控制总线用于传输控制信号。控制信号例如是读写控制信号，以用于确定数据传输方向；又如写数据有效信号，以用于确定写数据的有效性。
在本申请的实施例中，SRAM控制模块130连接于总线模块120；SRAM控制模块130的数量至少为一个，可以理解的是，总线模块120可与多个SRAM控制模块130相连接，且每个SRAM控制模块130工作时相互独立；SRAM控制模块130用于接收总线信号，根据总线信号完成相关数据读写，并将读写结果反馈至总线模块120。
在本申请的实施例中，SRAM控制模块130的数量可以根据实际使用需要进行增减，而主控模块110通过总线模块120可以与目标SRAM控制模块130进行数据交互，主控模块110可以通过与总线模块120连接的接口发送信号(例如目标SRAM控制模块的地址信号、控制信号、数据信号等)，总线模块120根据总线协议进行信号的传输，SRAM控制模块130变化时(如数量的增减，结构的改变等)，也不会对主控模块110造成影响，方便后续的器件拓展。
在一些实施方式中，如图2所示，SRAM控制模块130包括：接口子模块131、主控子模块132及SRAM控制电路133。
在本申请的实施例中，接口子模块131与总线模块120连接，接口子模块131还连接于主控子模块132。接口子模块131用于接收总线模块120传输的总线信号，并将对应的总线信号传输至主控子模块132。
在本申请的实施例中，主控子模块132还连接于SRAM控制电路133；主控子模块132用于根据总线信号控制SRAM控制电路133完成对应操作。例如数据的读取或者数据的写入等。
在本申请的实施例中，SRAM控制电路133连接于主控子模块132，SRAM控制电路133用于访问SRAM并完成读写操作。
请参阅图3，本申请实施例提供的一种SRAM控制模块的控制方法，可以应用于上述的SRAM控制模块100，本实施例描述的是SRAM控制模块100侧的步骤流程，该方法包括：步骤210至步骤220。
步骤210、至少一个SRAM控制模块接收总线模块传输的总线信号，总线信号由主控模块发送至总线模块。
在本申请的实施例中，SRAM控制模块包括：接口子模块、主控子模块以及SRAM控制电路；其中，接口子模块连接于总线模块，主控子模块连接于接口子模块，SRAM控制电路连接于主控子模块。
在本申请的实施例中，总线信号包括：控制地址信号、控制信号和数据信号。
在一些实施方式中，控制地址信号可以包括传播类型域段，传播类型域段用于标记该总线信号的传播类型。具体地，传播类型域段的字节长度可以根据实际使用需要进行设置，本申请对此不作限制。
可选地，传播类型可以包括点对点传输方式，即单个主控模块对单个SRAM控制模块进行控制。
可选地，传播类型还可以包括广播传播方式，即单个主控模块对多个(或所有)SRAM控制模块进行控制。
可选地，传播类型还可以包括组播传播方式，即单个主控模块对归属于目标组别的SRAM控制模块进行控制。SRAM控制模块可以预先被分配为多个组别，通过设置组别号识别不同的组别，同一组别的SRAM控制模块可以统一进行控制。
在一些实施方式中，控制地址信号可以包括ID(Identity document标识号)地址域段，ID地址域段用于标记需要进行控制的SRAM控制模块的地址。可以理解的是，每个SRAM控制模块具有唯一对应的ID地址信息，可以通过与SRAM控制模块对应的ID地址信息对SRAM控制模块进行控制。具体地，ID地址域段的字节长度可以根据实际使用需要进行设置，本申请对此不作限制。
在一些实施方式中，控制地址信号可以包括寄存器地址域段信息用于标记需要进行控制的SRAM控制模块的目标寄存器的地址。可以理解的是，每个SRAM控制模块的寄存器具有唯一对应的寄存器地址，可以通过与寄存器对应的寄存器地址对寄存器进行访问。具体地寄存器地址的字节长度可以根据实际使用需要进行设置，本申请对此不作限制。
在一些实施方式中，控制信号可以包括读写控制信号。
在一些实施方式中，读写控制信号用于标记当前数据的传输方向，即当前对SRAM执行读操作或写操作。可选地，可以通过不同的电平值区分读写控制信号的传输方向。例如读写控制信号的电平值为高电平时表征写操作；读写控制信号的电平值为低电平时，表征读操作。
也就是说，当主控模块需要对SRAM执行读数据操作时，输出低电平的读 写控制信号；当主控模块需要对SRAM执行写数据操作时，输出高电平的读写控制信号。
在一些实施方式中，控制信号还可以包括读数据有效信号，读数据有效信号用于标识当前传输的读数据是否有效。示例性地，读数据有效信号为高电平时用于标识当前传输的读数据有效。读数据有效信号为低电平时用于标识当前传输的读数据无效，具体可以根据实际使用需要进行调整，本申请对此不作限制。
在一些实施方式中，控制信号还可以包括写数据有效信号，写数据有效信号用于标识当前传输的写数据是否有效。示例性地，写数据有效信号为高电平时用于标识当前传输的写数据有效。写数据有效信号为低电平时用于标识当前传输的写数据无效，具体可以根据实际使用需要进行调整，本申请对此不作限制。
在一些实施方式中，数据信号可以包括读数据信号。读数据信号表征主控模块从SRAM控制模块读取的数据。
在一些实施方式中，数据信号还可以包括写数据信号。写数据信号表征主控模块写入SRAM控制模块的数据。
在一些实施方式中，主控模块可以通过不同的接口向总线模块输出对应的信号，而SRAM控制模块的数量改变不会影响主控模块的结构或者接口设置，SRAM控制模块增加或删减，只需与总线模块连接或者断开，主控模块可以通过具体的ID地址区分。SRAM控制模块的结构发生变动时，也不会影响主控模块，方便各个模块的升级，也方便不同规模的系统的设计和扩展。
步骤220、基于总线信号，通过总线模块与主控模块进行数据传输。
在本申请的实施例中，在步骤220基于总线信号，通过总线模块与主控模块进行数据传输中，本申请实施例提供的SRAM控制模块的控制方法还可以包括以下步骤：
(1)接口子模块根据控制地址信号确定控制地址。
在本申请的实施例中，接口子模块通过根据控制地址信号中的ID地址域段确定控制地址。
(2)当控制地址与本地地址匹配时，接口子模块将控制地址信号以及读 写控制信号发送至主控子模块。
(3)主控子模块根据控制地址信号确定传输地址。
在本申请的实施例中，上述主控子模块通过根据控制地址信号中的寄存器地址域段信息确定传输地址。
(4)主控子模块根据读写控制信号确定数据传输类型。
当读写控制信号为高电平时，主控子模块根据读写控制信号确定SRAM控制电路执行写数据操作，此时，数据传输类型可以为点对点或广播的传播方式。
当读写控制信号为低电平时，主控子模块根据读写控制信号确定SRAM控制电路执行读数据操作，此时，数据传输类型可以是点对点的传播方式。
(5)主控子模块根据数据传输类型和传输地址控制SRAM控制电路与主控模块进行数据传输。
在本申请的实施例中，SRAM控制电路与主控模块进行数据传输时，可以包括读数据与写数据两种传输模式，且在两种数据传输模式中，主控模块与SRAM控制模块均依照总线协议进行数据传输。
示例性地，当对SRAM控制电路执行读数据操作时，主控模块发送总线信号与读数据信号至总线模块，且总线模块依据总线信号中的控制地址信号传输总线信号与读数据信号至对应的SRAM控制模块，此时总线信号中的读写控制信号处于低电平状态；SRAM控制模块接收到总线信号时，依据总线信号中的控制地址信号中的寄存器地址域段信息找到SRAM中对应的寄存器，并执行读数据操作；主控子模块再将用于表示当前传输数据是否有效的读数据有效信号与用于标记所读取数据的读数据信号和所读取的数据经总线模块发送至主控模块。
可以理解的是，当读取数据成功时，也就是说，当前传输的数据有效时，读数据有效信号为高电平。
示例性地，当对SRAM控制电路执行写数据操作时，主控模块发送总线信号与需要写入的数据和用于标记当前传输的写入数据的写数据信号至总线模块，且总线模块依据总线信号中的控制地址信号传输总线信号与写入数据和写数据信号至对应的SRAM控制模块，此时总线信号中的读写控制信号处于高电平状态；SRAM控制模块接收到总线信号时，依据总线信号中的控制地址信号 中的寄存器地址域段信息找到SRAM中对应的寄存器，并执行写数据操作；主控子模块再将用于表示当前传输数据是否有效的写数据有效信号经总线模块发送至主控模块。
可以理解的是，当写入数据成功时，也就是说，当前传输的数据有效时，写数据有效信号为高电平。
在本申请的实施例中，在步骤220基于总线信号，通过总线模块与主控模块进行数据传输中，本申请实施例提供的SRAM控制模块的控制方法还可以包括以下步骤。
(1)根据控制地址信号确定控制地址。
(2)当控制地址与本地地址匹配时，根据控制地址信号确定传输地址。
(3)根据读写控制信号确定数据传输类型。
(4)根据数据传输类型和传输地址与主控模块进行数据传输。
在本申请的实施例中，接口子模块可以根据总线模块传输的控制地址信号确定主控模块要控制的SRAM控制模块的控制地址，并将控制地址与本地地址进行匹配。本地地址即接口子模块对应的SRAM控制模块的ID地址，也就是确定主控模块是否要对当前的SRAM控制模块进行控制。
进一步地，若控制地址与本地地址匹配时，再进一步根据控制地址信号确定传输地址，即需要进行控制的寄存器地址。
进一步地，数据传输类型包括读数据类型和写数据类型。不同的数据传输类型表征不同的数据传输方式和方向，数据传输类型为读数据类型时，表征主控制模块从传输地址对应的寄存器中读取数据。数据传输类型为写数据类型时，表征主控制模块将数据写入传输地址对应的寄存器中。
在一些实施方式中，本申请实施例提供的SRAM控制系统的控制方法还包括：接收总线模块传输的第一数据信号。第一数据信号由主控模块发送至总线模块。
在本申请的实施例中，第一数据信号包括写有效信号和写数据信号。主控模块执行写数据操作时，通过总线模块发送第一数据信号至对应的SRAM控制 模块。
进一步地，步骤根据数据传输类型和传输地址与主控模块进行数据传输，包括下述步骤。
(1)当数据传输类型为写数据类型时，根据第一数据信号确定写数据。
(2)将写数据写入与传输地址对应的存储区域。
进一步地，步骤根据数据传输类型和传输地址与主控模块进行数据传输，还包括下述步骤。
(1)当数据传输类型为读数据类型时，获取传输地址对应的存储区域所存储的数据作为读数据。
(2)根据读数据生成第二数据信号。
(3)通过总线模块将第二数据信号发送至主控模块。
请参阅图4，本申请实施例提供的另一种SRAM控制模块的控制方法，可以应用于上述的SRAM控制模块100，本实施例描述的是SRAM控制模块100侧的步骤流程，该方法包括：步骤210至步骤230。
步骤210、主控模块发送总线信号至总线模块。
步骤220、至少一个SRAM控制模块接收总线模块传输的总线信号。
步骤230、至少一个SRAM控制模块基于总线信号，通过总线模块与主控模块进行数据传输。
下面继续通过具体的实施例对本申请的实施例提供的SRAM控制系统的控制方法进行详细阐述。
请参阅图5，图5示出了本申请实施例提供的一种总线信号的时序图。在本申请的实施例中，CLK代表时钟信号。addr[12:11]代表控制地址信号中的传播类型，addr[10:6]代表控制地址信号中的ID地址域段，addr[5:0]代表控制地址信号中的寄存器地址域段，wdata代表写数据，wvalid代表写数据有效信号。
当进行数据配置(写数据操作)时，主控制模块控制读写控制信号为1(高电平)，以指示当前操作为写数据操作，输出控制地址信号匹配待配置的SRAM控制模块以及对应的内部寄存器。写数据有效信号为1(高电平)表示当前传输数据有效，并同步输出配置数据(即写数据)。SRAM控制模块将当前传输 的数据存储至对应的内部寄存器。
请参阅图6，图6示出了本申请实施例提供的另一种总线信号的时序图。在本申请的实施例中，CLK代表时钟信号。addr[12:11]代表控制地址信号中的传播类型，addr[10:6]代表控制地址信号中的ID地址域段，addr[5:0]代表控制地址信号中的寄存器地址域段，rdata[127:0]代表读数据，rvalid代表读数据有效信号。
当进行读数据操作，主控制模块控制读写控制信号为0(低电平)，以指示当前操作为回读操作，输出控制地址信号匹配待回读的SRAM控制模块以及对应的内部寄存器，SRAM控制模块根据地址总线上的信息输出回读数据rdata以及回读数据有效信号rvalid，rvalid为1表示当前回读数据有效。主控制模块根据rvalid信号判断当前数据总线上的数据是否为有效数据。
请参阅图7，本申请实施例还提供一种FPGA芯片300，FPGA芯片300包括上述的SRAM控制系统。
在本申请的实施例中，至少一个SRAM控制模块用于图3对应的实施例的SRAM控制系统的控制方法。
在本申请的实施例中，至少一个SRAM控制模块用于图4对应的实施例的SRAM控制系统的控制方法。
请参阅图8，本申请实施例还提供一种电子设备400，电子设备400包括设备本体410以及设置于设备本体410的上述的FPGA芯片300。
在本申请的实施例中，电子设备400可以为手机、电脑、路由器、摄像设备等，本申请对此不作限制。
综上，本申请实施例提供的一种SRAM控制系统、方法、FPGA芯片及电子设备，该SRAM控制系统包括主控模块，至少一个SRAM控制模块和总线模块，总线模块用于连接主控模块与至少一个SRAM控制模块；其中，至少一个SRAM控制模块与主控模块通过主线模块进行数据传输。通过设置总线模块与SRAM控制模块，可以使SRAM控制系统实现对多个SRAM控制电路进行控制，且具备后续器件的扩展能力，从而可以更广泛地应用于各种应用场景中。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限 制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不驱使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (13)

  1. 一种SRAM控制系统，其特征在于，所述系统包括：
    主控模块；
    至少一个SRAM控制模块；
    总线模块，所述总线模块用于连接所述主控模块与所述至少一个SRAM控制模块；
    其中，所述至少一个SRAM控制模块与所述主控模块通过所述总线模块进行数据传输。
  2. 根据权利要求1所述的系统，其特征在于，所述SRAM控制模块包括：
    接口子模块，所述接口子模块与所述总线模块连接；
    主控子模块，所述主控子模块与所述接口子模块连接；
    SRAM控制电路，所述SRAM控制电路与所述主控子模块连接。
  3. 一种SRAM控制系统的控制方法，其特征在于，应用于权利要求1所述的SRAM控制系统，所述方法包括：
    所述至少一个SRAM控制模块接收总线模块传输的总线信号，所述总线信号由主控模块发送至总线模块；
    基于所述总线信号，通过所述总线模块与所述主控模块进行数据传输。
  4. 根据权利要求3所述的方法，其特征在于，所述SRAM控制模块包括：接口子模块、主控子模块以及SRAM控制电路；其中，所述接口子模块与所述总线模块连接；所述主控子模块与所述接口子模块连接；所述SRAM控制电路与所述主控子模块连接；
    所述总线信号包括：控制地址信号以及读写控制信号；
    所述基于所述总线信号、通过所述总线模块与所述主控模块进行数据传输，包括：
    所述接口子模块根据所述控制地址信号确定控制地址；
    当控制地址与本地地址匹配时，所述接口子模块将所述控制地址信号以及所述读写控制信号发送至所述主控子模块；
    所述主控子模块根据所述控制地址信号确定传输地址；
    所述主控子模块根据所述读写控制信号确定数据传输类型；
    所述主控子模块根据所述数据传输类型和所述传输地址控制所述SRAM控制电路与所述主控模块进行数据传输。
  5. 根据权利要求3所述的方法，其特征在于，所述总线信号还包括：控制地址信号以及读写控制信号；
    所述基于所述总线信号，通过所述总线模块与所述主控模块进行数据传输，包括：
    根据所述控制地址信号确定控制地址；
    当控制地址与本地地址匹配时，根据所述控制地址信号确定传输地址；
    根据所述读写控制信号确定数据传输类型；
    根据所述数据传输类型和所述传输地址与所述主控模块进行数据传输。
  6. 根据权利要求5所述的方法，其特征在于，所述方法还包括：接收所述总线模块传输的第一数据信号；所述第一数据信号由所述主控模块发送至所述总线模块；
    所述根据所述数据传输类型和所述传输地址与所述主控模块进行数据传输，包括：
    当所述数据传输类型为写数据类型时，根据所述第一数据信号确定写数据；
    将所述写数据写入与所述传输地址对应的存储区域。
  7. 根据权利要求5所述的方法，其特征在于，所述根据所述数据传输类型和所述传输地址与所述主控模块进行数据传输，包括：
    当所述数据传输类型为读数据类型时，获取所述传输地址对应的存储 区域所存储的数据作为读数据；
    根据所述读数据生成第二数据信号；
    通过所述总线模块将所述第二数据信号发送至所述主控模块。
  8. 根据权利要求5所述的方法，其特征在于，所述根据控制地址信号确定控制地址，包括：
    根据控制地址信号确定传播类型；
    当所述传播类型为点传播类型时，根据所述控制地址信号确定控制地址。
  9. 一种SRAM控制系统的控制方法，其特征在于，应用于权利要求1所述的SRAM控制系统，所述方法包括：
    主控模块发送总线信号至总线模块；
    至少一个SRAM控制模块接收所述总线模块传输的总线信号；
    所述至少一个SRAM控制模块基于所述总线信号，通过所述总线模块与所述主控模块进行数据传输。
  10. 一种FPGA芯片，其特征在于，所述芯片包括权利要求1所述的SRAM控制系统。
  11. 根据权利要求10所述的FPGA芯片，其特征在于，至少一个SRAM控制模块用于执行权利要求3至8任一项所述的SRAM控制系统的控制方法。
  12. 根据权利要求10所述的FPGA芯片，其特征在于，所述SRAM控制系统用于执行权利要求9所述的SRAM控制系统的控制方法。
  13. 一种电子设备，其特征在于，所述电子设备包括设备本体，以及设置于设备本体的权利要求10至12任一项所述的FPGA芯片。
PCT/CN2023/103247 2022-07-04 2023-06-28 Sram控制系统、方法、fpga芯片及电子设备 WO2024007914A1 (zh)

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