WO2024007386A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2024007386A1
WO2024007386A1 PCT/CN2022/108680 CN2022108680W WO2024007386A1 WO 2024007386 A1 WO2024007386 A1 WO 2024007386A1 CN 2022108680 W CN2022108680 W CN 2022108680W WO 2024007386 A1 WO2024007386 A1 WO 2024007386A1
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WIPO (PCT)
Prior art keywords
gate
layer
quasi
ohmic contact
semiconductor layer
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PCT/CN2022/108680
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English (en)
French (fr)
Inventor
谭燕兰
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Tcl华星光电技术有限公司
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Publication of WO2024007386A1 publication Critical patent/WO2024007386A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • LCD liquid crystal display
  • Each pixel in the LCD panel is distributed in a matrix.
  • Liquid crystal display devices in which thin film transistors are formed are now widely used.
  • thin film transistors are switched by applying scan pulses and the voltage applied by the data line is applied to the pixel electrode to achieve the flipping of the liquid crystal in the liquid crystal layer at the corresponding position to achieve the purpose of display.
  • the source voltage of the thin film transistor is equivalent to a positive voltage.
  • a large turn-on voltage needs to be applied to the gate of the thin film transistor.
  • the voltage difference between the gate and the source exceeds the conduction threshold of the thin film transistor. Since thin film transistors generally require a large gate turn-on voltage, a large amount of power consumption will occur in the thin film transistor.
  • the existing display panel has a problem of increased power consumption due to the large gate turn-on voltage of the thin film transistor. Therefore, it is necessary to provide an array substrate and a display panel to improve this defect.
  • Embodiments of the present application provide an array substrate and a display panel, which can reduce the gate turn-on voltage of the thin film transistor, thereby reducing the power consumption of the display panel.
  • An embodiment of the present application provides an array substrate, including:
  • a thin film transistor is provided on one side of the substrate, and the thin film transistor includes:
  • An active layer is provided on one side of the gate
  • a source electrode is disposed on a side of the active layer facing away from the gate electrode and in contact with the active layer;
  • a drain electrode is provided on a side of the active layer facing away from the gate electrode, and is in contact with the active layer, with a gap between the source electrode and the drain electrode;
  • a quasi-ohmic contact layer is provided on a side of the active layer facing away from the gate electrode, and the quasi-ohmic contact layer is electrically connected to the drain electrode;
  • a photosensitive semiconductor layer is provided on a side of the active layer away from the gate electrode, and the photosensitive semiconductor layer is electrically connected to the source electrode and the quasi-ohmic contact layer respectively.
  • one end of the quasi-ohmic contact layer is overlapped on a side of the drain electrode away from the active layer, and opposite ends of the photosensitive semiconductor layer are respectively overlapped on the source A side of the pole facing away from the ohmic contact layer, and a side of the quasi-ohmic contact layer facing away from the active layer.
  • the two ends of the photosensitive semiconductor layer overlap the source electrode and the quasi-ohmic contact layer respectively, and one end of the quasi-ohmic contact layer overlaps the drain of the thin film transistor.
  • the light-sensitive semiconductor layer, the quasi-ohmic contact layer, the source electrode, the drain electrode, the active layer, and the gate electrode form a Schottky diode.
  • the Schottky diode utilizes the current hysteresis under forward-biased conditions in the current-voltage characteristics of the Schottky diode under light conditions.
  • the minimum voltage to turn on the thin film transistor can be reduced, and the output current of the thin film transistor can be controlled by the voltage applied to the gate and the light applied to the photosensitive semiconductor layer, thereby realizing the control of the thin film transistor. Control of logic states of thin film transistors.
  • the material of the quasi-ohmic contact layer is graphite
  • the material of the photosensitive semiconductor layer is indium selenide
  • Indium selenide is a typical two-dimensional layered semiconductor material with excellent electrical properties and a moderate and adjustable direct band gap. The spectral response covers the range from near-infrared to ultraviolet. Indium selenide is selected as the photosensitive semiconductor layer. material, which can improve the photoresponsivity and response speed of thin film transistors; graphite has an electron affinity similar to that of indium selenide.
  • the quasi-ohmic contact layer made of graphite material is overlapped on the drain of the thin film transistor to build a quasi-ohmic contact layer. Contact can weaken the Fermi level pinning at the interface, which is beneficial to the input and output of current.
  • the thickness of the quasi-ohmic contact layer is between 20 nanometers and 30 nanometers
  • the thickness of the photosensitive semiconductor layer is between 20 nanometers and 30 nanometers.
  • both the quasi-ohmic contact layer and the photosensitive semiconductor layer By limiting the thickness of both the quasi-ohmic contact layer and the photosensitive semiconductor layer to between 20 nanometers and 30 nanometers, it is possible to avoid the occurrence of fragmentation due to too thin thickness of the quasi-ohmic contact layer or the photosensitive semiconductor layer.
  • the photosensitive semiconductor layer and the quasi-ohmic contact layer are disposed on a side of the gate away from the substrate.
  • Embodiments of the present application further define that the thin film transistor has a bottom-gate structure.
  • the light-sensing semiconductor layer in the thin-film transistor with the bottom-gate structure can receive light from an internal light source or an external light source and reduce the minimum required time to turn on the thin film transistor. voltage effect.
  • the photosensitive semiconductor layer and the quasi-ohmic contact layer are disposed on a side of the gate close to the substrate.
  • Embodiments of the present application further define that the thin film transistor has a top-gate structure.
  • the photosensitive semiconductor layer in the top-gate structure thin film transistor can receive light from an internal light source or an external light source and reduce the minimum voltage required to turn on the thin film transistor. Effect.
  • the gate electrode is made of a transparent conductive metal oxide material.
  • Choosing a transparent conductive metal oxide as the material of the gate can prevent the gate from blocking the light hitting the photosensitive semiconductor layer.
  • the light from the side of the photosensitive semiconductor layer close to the gate and the light from the side far from the gate can be blocked. received by the photosensitive semiconductor layer.
  • the metal oxide material includes an oxide of any one of indium, tin, zinc and cadmium; or a composite multi-component oxide composed of at least two metal oxides.
  • Selecting an oxide of any metal among indium, tin, zinc and cadmium; or a composite multi-component oxide composed of at least two metal oxides as the gate material can ensure the transmittance of the gate and avoid The gate blocks light irradiating the photosensitive semiconductor layer.
  • the gate electrode is made of metal.
  • the photosensitive semiconductor layer can only receive light from the side away from the gate, thereby achieving the effect of reducing the minimum voltage required to turn on the thin film transistor.
  • the lowest voltage for turning on the thin film transistor when the light-sensitive semiconductor layer receives specific light is a first voltage.
  • the minimum voltage for turning on the thin film transistor is The lowest voltage is a second voltage, and the first voltage is lower than the second voltage.
  • the output current of the thin film transistor can be controlled by the voltage applied to the gate and the light applied to the photosensitive semiconductor layer, thereby controlling the logic state of the thin film transistor.
  • the array substrate includes a gate control line, and the gate control line is connected to the gate;
  • the light-sensing semiconductor layer continues to receive the specific illumination, and when the gate control line applies a first turn-on voltage to the gate, the thin film transistor is turned on, and the first turn-on voltage is turned on.
  • the voltage is greater than or equal to the first voltage and less than the second voltage.
  • the minimum voltage required to turn on the thin film transistor can be reduced.
  • the gate control line applies a first turn-on voltage to the gate of the thin film transistor, the thin film transistor can be turned on. Thin film transistors achieve the effect of reducing power consumption.
  • the array substrate includes a gate control line, and the gate control line is connected to the gate;
  • the gate control line When executing the writing demonstration mode, the gate control line applies a second turn-on voltage to the gate that is insufficient to turn on the thin film transistor until the light-sensitive semiconductor layer receives the specific illumination to turn on the thin film transistor. ;
  • the second turn-on voltage is greater than or equal to the first voltage and less than the second voltage.
  • the gate control line When executing the writing demonstration mode, the gate control line continues to apply a second turn-on voltage that is insufficient to turn on the thin film transistor to the gate of the thin film transistor until receiving specific light, the minimum voltage required to turn on the thin film transistor is reduced, thereby turning on the thin film transistor.
  • the thin film transistor realizes the function of writing demonstration mode.
  • embodiments of the present application further provide a display panel, where the display panel includes:
  • An opposing substrate arranged opposite to the array substrate
  • a backlight module is disposed on a side of the array substrate away from the opposite substrate, and the array substrate includes:
  • a thin film transistor is provided on one side of the substrate, and the thin film transistor includes:
  • An active layer is provided on one side of the gate
  • a source electrode is disposed on a side of the active layer facing away from the gate electrode and in contact with the active layer;
  • a drain electrode is provided on a side of the active layer away from the gate electrode and is in contact with the active layer; there is a gap between the source electrode and the drain electrode;
  • a quasi-ohmic contact layer is provided on a side of the active layer facing away from the gate electrode, and the quasi-ohmic contact layer is electrically connected to the drain electrode;
  • a photosensitive semiconductor layer is provided on a side of the active layer away from the gate electrode, and the photosensitive semiconductor layer is electrically connected to the source electrode and the quasi-ohmic contact layer respectively.
  • the display panel is a liquid crystal display panel, and the light emitted by the backlight module of the display panel is used to illuminate the thin film transistor, thereby reducing the minimum voltage required to turn on the thin film transistor, thereby achieving the effect of reducing power consumption.
  • one end of the quasi-ohmic contact layer is overlapped on a side of the drain electrode away from the active layer, and opposite ends of the photosensitive semiconductor layer are respectively overlapped on the source A side of the electrode facing away from the active layer, and a side of the quasi-ohmic contact layer facing away from the active layer.
  • the material of the quasi-ohmic contact layer is graphite
  • the material of the photosensitive semiconductor layer is indium selenide
  • the thickness of the quasi-ohmic contact layer is between 20 nanometers and 30 nanometers
  • the thickness of the photosensitive semiconductor layer is between 20 nanometers and 30 nanometers.
  • the photosensitive semiconductor layer and the quasi-ohmic contact layer are disposed on a side of the gate away from the substrate.
  • the photosensitive semiconductor layer and the quasi-ohmic contact layer are disposed on a side of the gate close to the substrate.
  • the gate electrode is made of metal or a transparent conductive metal oxide material.
  • the metal oxide material includes an oxide of any one of indium, tin, zinc and cadmium; or a composite multi-component oxide composed of at least two metal oxides.
  • Embodiments of the present application provide an array substrate and a display panel including the array substrate.
  • the array substrate includes a substrate and a thin film transistor disposed on one side of the substrate.
  • the thin film transistor includes A quasi-ohmic contact layer provided on one side of the active layer and connected to the drain electrode, and a photosensitive semiconductor layer connected to the source electrode and the quasi-ohmic contact layer can be reduced by irradiating the photosensitive semiconductor layer with external or internal light.
  • the gate turn-on voltage of the thin film transistor is reduced, thereby reducing the power consumption of the display panel.
  • Figure 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • Figure 2 is a schematic diagram of the first lighting mode of the display panel provided by the embodiment of the present application.
  • Figure 3 is a schematic diagram of the second lighting mode of the display panel provided by the embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • Embodiments of the present application provide an array substrate and a display panel, which can be used to reduce the gate turn-on voltage of the thin film transistor in the display panel and reduce the power consumption of the display panel.
  • the array substrate includes a substrate 10 and a plurality of thin film transistors 20 distributed in an array and pixel electrodes 30 disposed on the substrate 10 .
  • the thin film transistor 20 includes a gate electrode 21, an active layer 22, a source electrode 23, and a drain electrode 24.
  • the source electrode 23 is disposed on a side of the active layer 22 away from the gate electrode 21 and is connected to the gate electrode 21.
  • the active layer 22 is in contact with the drain electrode 24.
  • the drain electrode 24 is disposed on a side of the active layer 22 away from the gate electrode 21 and is in contact with the active layer 22.
  • the source electrode 23 is in contact with the drain electrode 24. There is a gap between the poles 24 .
  • the active layer 22 includes a semiconductor layer 221 and an ohmic contact layer 222.
  • the semiconductor layer 221 is provided on one side of the gate 21, and the ohmic contact layer 222 is provided on the semiconductor layer 221.
  • the source electrode 23 is provided at one end of the opposite ends of the layer 221 on the side facing away from the gate electrode 21 and the drain electrode 24 is provided on the side of the ohmic contact layer 222 facing away from the semiconductor layer 221 .
  • the pixel electrode 30 is electrically connected to the drain electrode 24 .
  • the thin film transistor 20 further includes a quasi-ohmic contact layer 25 and a photosensitive semiconductor layer 26.
  • the quasi-ohmic contact layer 25 is disposed in the gap between the source electrode 23 and the drain electrode 24 and is located on the semiconductor layer 221. On the side away from the gate electrode 21 , the quasi-ohmic contact layer 25 is electrically connected to the drain electrode 24 .
  • the photosensitive semiconductor layer 26 is disposed in the gap between the source electrode 23 and the drain electrode 24 and is located on a side of the semiconductor layer 221 away from the gate electrode 21 . Opposite ends are electrically connected to the source electrode 23 and the quasi-ohmic contact layer 25 respectively. The quasi-ohmic contact layer 25 and the photosensitive semiconductor layer 26 connect the source electrode 23 and the drain electrode 24 . fill the gap.
  • the output current of the thin film transistor 20 device is controlled by the voltage applied to the gate electrode 21 and illumination, The control of the logic state of the thin film transistor 20 and the optical storage function can be realized.
  • the thin film transistor 20 has a bottom gate structure, and the quasi-ohmic contact layer 25 and the photosensitive semiconductor layer 26 are both disposed on a side of the gate electrode 21 away from the substrate 10 .
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • the substrate 10 is a transparent glass substrate so that light can illuminate the photosensitive semiconductor layer 26 from one side of the substrate 10 .
  • the material of the substrate 10 may also be a transparent organic material.
  • the organic material may include but is not limited to polyimide (PI), polyamide (PA), polycarbonate (PC), Polyphenylene ether sulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymethyl methacrylate (PMMA), cyclic olefin copolymer (COC) one or a mixture of more.
  • the gate 21 is disposed on one side of the substrate 10 . It should be noted that the gate electrode 21 is disposed on one side of the substrate 10 , which may mean that the gate electrode 21 is in direct contact with the surface of the substrate 10 , or may be in indirect contact with the substrate 10 .
  • the gate insulating layer 27 is laid flat on one side of the substrate 10 and covers a surface of the gate 21 facing away from the substrate 10 .
  • the gate insulating layer 27 is made of a transparent inorganic material, and the inorganic material may include at least one or a mixture of at least one of silicon nitride, silicon oxide, and silicon oxynitride.
  • the gate insulating layer 27 may be a single-layer structure formed by any one of the above-mentioned inorganic materials, or may be a double-layer or multi-layer structure formed by superimposing one or more of the above-mentioned inorganic materials.
  • the semiconductor layer 221 is disposed on a side of the gate insulating layer 27 away from the gate 21 .
  • the material of the semiconductor layer 221 is amorphous silicon ( ⁇ -Si).
  • the ohmic contact layer 222 is disposed on opposite ends of the semiconductor layer 221 on the side facing away from the gate electrode 21 .
  • the material of the ohmic contact layer 222 is amorphous silicon ( ⁇ -Si).
  • the ion doping concentration of 222 is greater than that of the semiconductor layer 221 .
  • the source electrode 23 is disposed on a side of the ohmic contact layer 222 away from the semiconductor layer 221
  • the drain electrode 24 is disposed on a side of the ohmic contact layer 222 away from the semiconductor layer 221 .
  • the source electrode 23 and the drain electrode 24 are arranged in the same layer, and are made of the same material as the drain electrode 24 .
  • the source electrode 23 and the drain electrode 24 are both made of copper.
  • the material of the source electrode 23 and the drain electrode 24 is not limited to copper, but may also include any one or a combination of aluminum, molybdenum, copper, chromium, tungsten, tantalum and titanium.
  • the source electrode 23 and the drain electrode 24 may also be a single-layer metal film structure, or may be a two-layer or multi-layer metal film structure.
  • the source electrode 23 and the drain electrode 24 are spaced apart from each other.
  • One end of the quasi-ohmic contact layer 25 overlaps a side of the drain electrode 24 away from the ohmic contact layer 222.
  • the photosensitive semiconductor layer The opposite ends of 26 are respectively overlapped with the side of the source electrode 23 away from the ohmic contact layer 222 and the side of the quasi-ohmic contact layer 25 away from the semiconductor layer 221 .
  • the insulating protective layer 28 is disposed on the side of the quasi-ohmic contact layer 25 and the photosensitive semiconductor layer 26 away from the substrate 10 , and covers the source electrode 23 and the drain electrode 24 , and the pixel electrode 30 is disposed on The side of the insulating protective layer 28 away from the substrate 10 is connected to the drain electrode 24 through a via hole penetrating the insulating protective layer 28 .
  • the material of the pixel electrode 30 may be a conductive transparent metal oxide.
  • the metal oxide material may include an oxide of any one of indium, tin, zinc and cadmium; or a composite multi-component oxide composed of at least two metal oxides.
  • the metal oxide material may be indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), cadmium oxide (CdO), and Any of aluminum doped zinc oxide (AZO).
  • the material of the photosensitive semiconductor layer 26 is two-dimensional indium selenide
  • the material of the quasi-ohmic contact layer 25 is graphite.
  • Two-dimensional indium selenide is a typical two-dimensional layered semiconductor material. It has excellent electrical properties and a moderate and adjustable direct band gap. The spectral response covers the range from near-infrared to ultraviolet.
  • Indium selenide is selected as the photosensitive semiconductor.
  • the material of the layer can improve the light response rate and response speed of the thin film transistor.
  • Graphite has an electron affinity similar to that of indium selenide.
  • the quasi-ohmic contact layer 25 made of graphite material is overlapped on the drain electrode 24 to construct a quasi-ohmic contact layer 25. Ohmic contact can weaken the Fermi level pinning at the interface, which is beneficial to the input and output of current.
  • the thin film transistor 20 composed of the photosensitive semiconductor layer 26, the quasi-ohmic contact layer 25, the source electrode 23, the drain electrode 24, etc. is a metal copper-two-dimensional indium selenide-graphite Schottky diode, using The output current of the thin film transistor is controlled by the voltage applied to the gate 21 and the light applied to the photosensitive semiconductor layer 26 due to the current hysteresis effect under the forward bias condition in the current-voltage characteristics of the thin film transistor under illumination conditions. , thereby achieving control of the logic state of the thin film transistor.
  • the thickness of the quasi-ohmic contact layer 25 is greater than or equal to 20 nanometers and less than or equal to 30 nanometers
  • the thickness of the photosensitive semiconductor layer 26 is greater than or equal to 20 nanometers and less than or equal to 30 nanometers.
  • the thickness of the layer 25 and the photosensitive semiconductor layer 26 may be equal or different.
  • the thickness of the quasi-ohmic contact layer 25 may also be greater than the thickness of the photosensitive semiconductor layer 26 or smaller than the thickness of the photosensitive semiconductor layer 25 .
  • the thickness of layer 26 is not limited here.
  • the thickness of the quasi-ohmic contact layer 25 may be 20 nanometers, 22 nanometers, 25 nanometers, 27 nanometers, or 30 nanometers
  • the photosensitive semiconductor layer 26 may be 20 nanometers, 23 nanometers, 26 nanometers, 27 nanometers, or 30 nanometers, etc., so as to avoid the occurrence of fragmentation caused by the film thickness of the photosensitive semiconductor layer 26 and the quasi-ohmic contact layer 25 being too thin.
  • the lowest voltage at which the thin film transistor 20 is turned on when the light-sensitive semiconductor layer 26 receives specific light is a first voltage.
  • the lowest voltage at which the thin film transistor 20 is turned on when the light-sensitive semiconductor layer 26 does not receive the specific light is a third voltage. Two voltages, the first voltage is smaller than the second voltage.
  • the display panel has a low power consumption mode.
  • the data line of the display panel applies a forward voltage to the source electrode 23 of the thin film transistor 20
  • the gate control line applies a forward voltage to the gate electrode 21
  • Low potential voltage the low potential voltage is lower than the first voltage, and the thin film transistor 20 cannot be turned on normally because the potential of the gate electrode 21 is too low.
  • the condition that triggers the thin film transistor 20 to turn on is the first turn-on voltage.
  • the gate control line applies a first turn-on voltage to the gate 21, since the first turn-on voltage is greater than or equal to the first voltage and less than the second voltage, , the thin film transistor 20 is turned on.
  • the thin film transistor 20 can be turned on with a smaller first turn-on voltage when it receives the specific illumination.
  • the thin film transistor 20 can thereby reduce the power consumption of the display panel.
  • the light source of the specific illumination may be a light source in the external environment or a light source inside the display panel.
  • Figure 2 is a schematic diagram of the first illumination mode of the display panel provided by the embodiment of the present application.
  • the display panel shown in Figure 2 is a liquid crystal display panel.
  • the display panel can It includes an array substrate 100, a counter substrate 200, a liquid crystal layer 300 and a backlight module 400.
  • the array substrate 100 can be any array substrate provided in the embodiments of the present application.
  • the array substrate 100 and the counter substrate 200 are arranged opposite each other, the liquid crystal layer 300 is arranged between the array substrate 100 and the opposite substrate 200, and the backlight module 400 is arranged on a side of the array substrate 100 away from the opposite substrate 200. .
  • the array substrate 100 may include the substrate 10 and the thin film transistor 20 in the embodiment shown in FIG. 1
  • the counter substrate 200 may include a glass substrate and a substrate disposed on the glass
  • the color filter layer is on the side of the substrate close to the array substrate 100 .
  • the gate electrode 21 is made of a transparent conductive metal oxide material, and the light emitted by the backlight module 400 can penetrate the gate electrode 21 in the direction shown by the arrow in the figure, and illuminate to the photosensitive semiconductor layer 26 , thereby reducing the turn-on voltage of the thin film transistor 20 .
  • the metal oxide material may include an oxide of any one of indium, tin, zinc and cadmium; or a composite multi-component oxide composed of at least two metal oxides.
  • the metal oxide material may be indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), cadmium oxide (CdO), and Any of aluminum doped zinc oxide (AZO).
  • the material of the gate 21 may also be metal.
  • the light source of the specific illumination may be a light source in the external environment.
  • the external ambient light source is sufficient, such as a strong light environment, the light in the external environment can also be used to illuminate the photosensitive semiconductor layer 26 of the thin film transistor 20 to reduce the turn-on voltage of the thin film transistor 20, thereby reducing the display Panel power consumption.
  • the material of the gate 21 may be any one or a combination of multiple metal materials such as aluminum, molybdenum, copper, chromium, tungsten, tantalum, and titanium.
  • the gate 21 may also be a single-layer metal film structure formed by any one of the above-mentioned multiple metal materials, or may be a multi-layer metal film structure formed by superimposing two or more of the above-mentioned materials.
  • the display panel may also have a writing demonstration mode.
  • the writing demonstration mode is executed, the condition that triggers the turning on of the thin film transistor 20 is specific illumination instead of the second turning on voltage.
  • the gate control line can continuously apply a second turn-on voltage to the gate 21 , and the second turn-on voltage is smaller than the light-sensing semiconductor.
  • the minimum voltage (i.e., the second voltage) for turning on the thin film transistor 20 when the layer 26 does not receive light is greater than or equal to the minimum voltage (i.e., the first voltage) for turning on the thin film transistor 20 when receiving specific illumination, so that all the thin film transistors 20 cannot be turned on.
  • the thin film transistor 20 is turned on until the photosensitive semiconductor layer 26 receives specific light, and the minimum voltage required to turn on the thin film transistor decreases and is less than or equal to the second turn-on voltage, so that the thin film transistor 20 can be turned on.
  • the light source of the specific illumination is an external light source.
  • the illumination intensity of the specific illumination when the low power consumption mode is executed may be different from the illumination intensity of the specific illumination when the writing demonstration mode is executed. All the illumination intensity when the low power consumption mode is executed is different.
  • the magnitude of the first voltage may be different from the magnitude of the first voltage when the writing demonstration mode is executed.
  • Figure 3 is a schematic diagram of the second lighting mode of the display panel provided by the embodiment of the present application.
  • the external light source can be an infrared pen or a laser pen.
  • the infrared pen or laser pen and other external light sources emit
  • the strong beam can penetrate the opposite substrate 200 in the direction of the arrow in the figure and irradiate the thin film transistor 20 to reduce the minimum voltage required to turn on the thin film transistor 20 and turn on the thin film transistor 20 to achieve the desired lighting conditions.
  • the function of writing demonstration under front beam irradiation can be realized on the display panel.
  • the thin film transistor 20 may also have a top gate structure.
  • Figure 4 is a schematic structural diagram of another array substrate provided by an embodiment of the present application. Its structure is roughly the same as that of the array substrate shown in Figure 1. The difference is that: the photosensitive semiconductor layer 26 and The quasi-ohmic contact layer 25 is disposed on a side of the gate 21 close to the substrate 10 .
  • the photosensitive semiconductor layer 26 is disposed on one side of the substrate 10 . It should be noted that being disposed on one side of the substrate 10 may refer to direct contact with one side surface of the substrate 10 , or may refer to indirect contact with the substrate 10 .
  • the quasi-ohmic contact layer 25 is disposed on one side of the substrate 10 , and one end of the quasi-ohmic contact layer 25 overlaps a side of the photosensitive semiconductor layer 26 away from the substrate 10 .
  • the source The electrode 23 is disposed on the side of the photosensitive semiconductor layer 26 away from the substrate 10 and is in direct contact with the surface of the photosensitive semiconductor layer 26 on the side facing away from the substrate 10 .
  • the drain electrode 24 is disposed on The side of the quasi-ohmic contact layer 25 facing away from the substrate 10 is in direct contact with the surface of the side of the quasi-ohmic contact layer 25 facing away from the substrate 10 .
  • the ohmic contact layer 222 is respectively disposed on a side of the source electrode 23 away from the substrate 10 and a side of the drain electrode 24 away from the substrate 10 , and the semiconductor layer 221 is disposed on the ohmic contact layer 222 .
  • a side of the contact layer 222 facing away from the substrate 10 covers the surface of the quasi-ohmic contact layer 25 and a side of the photosensitive semiconductor layer 26 facing away from the substrate 10 .
  • the gate insulating layer 27 is disposed on a side of the semiconductor layer 221 facing away from the substrate 10 , and the gate 21 is disposed on a side of the gate insulating layer 27 facing away from the substrate 10 , and is connected to The semiconductor layers 221 are disposed facing each other.
  • the material of the gate 21 can be a transparent conductive metal oxide material, and the strong light beam outside the display panel can penetrate the gate 21 , and irradiate to the photosensitive semiconductor layer 26 .
  • the metal oxide material may include an oxide of any one of indium, tin, zinc, and cadmium; or a composite multi-component oxide formed by combining the oxides of at least two metals.
  • the metal oxide material may be indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), cadmium oxide (CdO), and Any of aluminum doped zinc oxide (AZO).
  • the material of the gate 21 can be either the transparent conductive metal oxide material in the above embodiment or a metal material.
  • the metal material may be any one or a combination of more metal materials such as aluminum, molybdenum, copper, chromium, tungsten, tantalum and titanium.
  • the embodiment of the present application also provides a display device.
  • the display device includes a housing, a circuit board, a power supply and the display panel provided in the above embodiment.
  • the circuit board and the The power supply can be installed in the housing, and the display panel can be installed on the housing.
  • the display device may be a mobile terminal, such as color electronic paper, color e-books, smart phones, etc.
  • the display device may also be a wearable terminal, such as a smart watch, a smart bracelet, etc.
  • the display device may also be a fixed terminal, such as Color electronic billboards, color electronic posters, etc.
  • Embodiments of the present application provide an array substrate and a display panel including the array substrate.
  • the array substrate includes a substrate and a thin film transistor disposed on one side of the substrate.
  • the thin film transistor includes A quasi-ohmic contact layer disposed on one side of the semiconductor layer and connected to the drain, and a photosensitive semiconductor layer connected to the source and the quasi-ohmic contact layer, using external or internal light to illuminate the quasi-ohmic contact layer and the photosensitive semiconductor layer, the gate turn-on voltage of the thin film transistor can be reduced, thereby reducing the power consumption of the display panel.

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Abstract

本申请提供一种阵列基板及显示面板，该阵列基板包括基底以及设置于所述基底一侧的薄膜晶体管，通过薄膜晶体管对于外部或者内部光线的感应作用，可以减小薄膜晶体管的栅极开启电压，从而可以降低显示面板的功耗。

Description

阵列基板及显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及显示面板。
 背景技术
近年来，液晶显示面板（liquid crystal display, LCD）近年来，液晶显示设备在诸多领域都有着广泛的应用，并继续呈现着快速的增长趋势，以矩阵式分布在液晶显示面板中的每个像素中形成有薄膜晶体管的液晶显示装置现在被广泛使用。在这种有源矩阵型液晶显示面板中，通过施加扫描脉冲实现薄膜晶体管开关并配合数据线施加的电压到像素电极上，实现对应位置液晶层内液晶的翻转，达到显示的目的。
 技术问题
在薄膜晶体管的源极连接的数据线输入正电压时，相当于薄膜晶体管的源极电压为正电压，为了实现薄膜晶体管的导通，需要在薄膜晶体管的栅极上施加较大的开启电压以满足栅极与源极之间的压差超过薄膜晶体管的导通阈值。由于薄膜晶体管一般需要较大的栅极开启电压，导致薄膜晶体管内会产生大量的功率消耗。
综上所述，现有显示面板存在由于薄膜晶体管的栅极开启电压较大导致功耗增加的问题。故，有必要提供一种阵列基板及显示面板来改善这一缺陷。
 技术解决方案
本申请实施例提供一种阵列基板及显示面板，可以降低薄膜晶体管的栅极开启电压，从而降低显示面板的功耗。
本申请实施例提供一种阵列基板，包括：
基底；
薄膜晶体管，设置于所述基底的一侧，所述薄膜晶体管包括：
栅极；
有源层，设置于所述栅极的一侧；
源极，设置于所述有源层的背离所述栅极的一侧，且与所述有源层接触；
漏极，设置于所述有源层背离所述栅极的一侧，且与所述有源层接触，所述源极与所述漏极之间具有间隔；
准欧姆接触层，设置于所述有源层的背离所述栅极的一侧，所述准欧姆接触层电性连接于所述漏极；以及
光感半导体层，设置于所述有源层的背离所述栅极一侧，所述光感半导体层分别电性连接所述源极和所述准欧姆接触层。
根据本申请一实施例，所述准欧姆接触层的一端搭接在所述漏极的背离所述有源层的一侧，所述光感半导体层的相对两端分别搭接在所述源极的背离所述欧姆接触层的一侧、以及所述准欧姆接触层的背离所述有源层的一侧。
通过在薄膜晶体管上增设光感半导体层和准欧姆接触层，光感半导体层的两端分别搭接在源极和准欧姆接触层上，准欧姆接触层的一端搭接在薄膜晶体管的漏极上，光感半导体层与准欧姆接触层、源极、漏极、有源层、栅极构成肖特基二极管，利用肖特基二极管在光照条件下电流-电压特性中正偏条件下的电流迟滞效应，在接收光照时，可降低开启薄膜晶体管的最低电压，并通过施加在栅极的电压、以及施加在光感半导体层的光照对所述薄膜晶体管的输出电流进行控制，进而实现对所述薄膜晶体管的逻辑状态的控制。
根据本申请一实施例，所述准欧姆接触层的材料为石墨，所述光感半导体层的材料为硒化铟。
硒化铟是典型的二维层状半导体材料，具有优异的电学性能以及适中且可调的直接带隙，光谱响应覆盖了从近红外到紫外的范围，选用硒化铟作为光感半导体层的材料，可以提高薄膜晶体管的光响应率以及响应速度；石墨具有与硒化铟相近的电子亲和势，将石墨材料制成的准欧姆接触层搭接在薄膜晶体管的漏极上，构筑准欧姆接触，可以减弱界面处的费米能级钉扎，有利于电流的输入和输出。
根据本申请一实施例，所述准欧姆接触层的厚度介于20纳米至30纳米之间，所述光感半导体层的厚度介于20纳米至30纳米之间。
通过将准欧姆接触层和光感半导体层的厚度都限制在20纳米至30纳米之间，可以避免由于准欧姆接触层或者光感半导体层的厚度过薄导致破片的情况发生。
根据本申请一实施例，所述光感半导体层和所述准欧姆接触层设置于所述栅极的背离所述基底的一侧。
本申请实施例进一步限定了所述薄膜晶体管为底栅结构，底栅结构的薄膜晶体管中的光感半导体层可以接收来自内部光源或者外部光源发出的光线，并实现降低开启所述薄膜晶体管的最低电压的效果。
根据本申请一实施例，所述光感半导体层和所述准欧姆接触层设置于所述栅极的靠近所述基底的一侧。
本申请实施例进一步限定了薄膜晶体管为顶栅结构，顶栅结构的薄膜晶体管中的光感半导体层可以接收来自内部光源或者外部光源发出的光线，并实现降低开启所述薄膜晶体管的最低电压的效果。
根据本申请一实施例，所述栅极的材料为透明导电的金属氧化物材料。
选用透明导电的金属氧化物作为栅极的材料，可以避免栅极阻挡照射至光感半导体层的光线，来自光感半导体层靠近栅极一侧的光线以及远离栅极一侧的光线都可以被光感半导体层所接收。
根据本申请一实施例，所述金属氧化物材料包括铟、锡、锌和镉中任意一种金属的氧化物；或者，至少两种金属的氧化物复合而成的复合多元氧化物。
选用铟、锡、锌和镉中任意一种金属的氧化物；或者，至少两种金属的氧化物复合而成的复合多元氧化物作为栅极的材料，可以确保栅极的透过率，避免栅极遮挡照射至光感半导体层的光线。
根据本申请一实施例，所述栅极的材料为金属。
当栅极的材料为金属时，光感半导体层只能接收来自远离栅极一侧的光线，以实现降低开启所述薄膜晶体管的最低电压的效果。
根据本申请一实施例，所述光感半导体层接受特定光照时开启所述薄膜晶体管的最低电压为第一电压，所述光感半导体层未接受所述特定光照时，开启所述薄膜晶体管的最低电压为第二电压，所述第一电压小于所述第二电压。
利用所述薄膜晶体管的上述特性，可以通过施加在栅极的电压、以及施加在光感半导体层的光照对所述薄膜晶体管的输出电流进行控制，进而实现对所述薄膜晶体管的逻辑状态的控制。
根据本申请一实施例，所述阵列基板包括栅极控制线，所述栅极控制线连接于所述栅极；
执行低功耗模式时，所述光感半导体层持续接受所述特定光照，当所述栅极控制线向所述栅极施加第一开启电压时，开启所述薄膜晶体管，所述第一开启电压大于或等于所述第一电压，且小于所述第二电压。
通过外部光源或者内部光源提供特定光照持续照射薄膜晶体管的光感半导体层，可以降低开启所述薄膜晶体管的最低电压，当栅极控制线向薄膜晶体管的栅极施加第一开启电压时，可以开启薄膜晶体管，实现降低功耗的效果。
根据本申请一实施例，所述阵列基板包括栅极控制线，所述栅极控制线连接于所述栅极；
执行书写演示模式时，所述栅极控制线向所述栅极施加不足以开启所述薄膜晶体管的第二开启电压，直至所述光感半导体层接受所述特定光照时，开启所述薄膜晶体管；
所述第二开启电压大于或等于所述第一电压，且小于所述第二电压。
在执行书写演示模式时，栅极控制线可持续向薄膜晶体管的栅极施加不足以开启薄膜晶体管的第二开启电压，直至接收特定光照时，开启薄膜晶体管所需的最低电压降低，以此开启所述薄膜晶体管，实现书写演示模式的功能。
根据本申请上述实施例提供的阵列基板，本申请实施例还提供一种显示面板，所述显示面板包括：
阵列基板；
对置基板，与所述阵列基板相对设置；
液晶层，设置于所述阵列基板与所述对置基板之间；以及
背光模组，设置于所述阵列基板的背离所述对置基板的一侧，所述阵列基板包括：
基底；
薄膜晶体管，设置于所述基底的一侧，所述薄膜晶体管包括：
栅极；
有源层，设置于所述栅极的一侧；
源极，设置于所述有源层的背离所述栅极的一侧，且与所述有源层接触；
漏极，设置于所述有源层的背离所述栅极的一侧，且与所述有源层接触；所述源极与所述漏极之间具有间隔；
准欧姆接触层，设置于所述有源层的背离所述栅极的一侧，所述准欧姆接触层电性连接于所述漏极；以及
光感半导体层，设置于所述有源层的背离所述栅极一侧，所述光感半导体层分别电性连接所述源极和所述准欧姆接触层。
所述显示面板为液晶显示面板，利用所述显示面板的背光模组发出的光线照射薄膜晶体管，可以降低开启薄膜晶体管的最低电压，以实现降低功耗的效果。
根据本申请一实施例，所述准欧姆接触层的一端搭接在所述漏极的背离所述有源层的一侧，所述光感半导体层的相对两端分别搭接在所述源极的背离所述有源层的一侧、以及所述准欧姆接触层的背离所述有源层的一侧。
根据本申请一实施例，所述准欧姆接触层的材料为石墨，所述光感半导体层的材料为硒化铟。
根据本申请一实施例，所述准欧姆接触层的厚度介于20纳米至30纳米之间，所述光感半导体层的厚度介于20纳米至30纳米之间。
根据本申请一实施例，所述光感半导体层和所述准欧姆接触层设置于所述栅极的背离所述基底的一侧。
根据本申请一实施例，所述光感半导体层和所述准欧姆接触层设置于所述栅极的靠近所述基底的一侧。
根据本申请一实施例，所述栅极的材料为金属或者透明导电的金属氧化物材料。
根据本申请一实施例，所述金属氧化物材料包括铟、锡、锌和镉中任意一种金属的氧化物；或者，至少两种金属的氧化物复合而成的复合多元氧化物。
 有益效果
本揭示实施例的有益效果：本申请实施例提供一种阵列基板以及包括所述阵列基板的显示面板，所述阵列基板包括基底以及设置于所述基底一侧的薄膜晶体管，所述薄膜晶体管包括设置于有源层一侧并连接于漏极的准欧姆接触层、以及连接于源极和准欧姆接触层的光感半导体层，利用外部或者内部的光线照射所述光感半导体层，可以减小所述薄膜晶体管的栅极开启电压，从而可以降低显示面板的功耗。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的结构示意图；
图2为本申请实施例提供的显示面板的第一种光照模式的示意图；
图3为本申请实施例提供的显示面板的第二种光照模式的示意图；
图4为本申请实施例提供的另一种阵列基板的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
本申请实施例提供一种阵列基板及显示面板，可以用于减小所述显示面板内的薄膜晶体管的栅极开启电压，降低所述显示面板的功耗。
所述阵列基板包括基底10和设置于所述基底10之上的多个呈阵列分布的薄膜晶体管20、以及像素电极30。所述薄膜晶体管20包括栅极21、有源层22、源极23、漏极24，所述源极23设置于所述有源层22的背离所述栅极21的一侧，且与所述有源层22接触，所述漏极24设置于所述有源层22的背离所述栅极21的一侧，且与所述有源层22接触，所述源极23与所述漏极24之间具有间隔。
在本申请实施例中，所述有源层22包括半导体层221和欧姆接触层222，所述半导体层221设置于所述栅极21的一侧，所述欧姆接触层222设置于所述半导体层221的背离所述栅极21一侧的相对两端，所述源极23设置于其中一端所述欧姆接触层222的背离所述半导体层221的一侧，所述漏极24设置于其中另一端所述欧姆接触层222的背离所述半导体层221的一侧，所述像素电极30电性连接于所述漏极24。
所述薄膜晶体管20还包括准欧姆接触层25和光感半导体层26，所述准欧姆接触层25设置于所述源极23与所述漏极24之间的间隙，且位于所述半导体层221远离所述栅极21的一侧，所述准欧姆接触层25电性连接于所述漏极24。
所述光感半导体层26设置于所述源极23与所述漏极24之间的间隙，且位于所述半导体层221远离所述栅极21的一侧，所述光感半导体层26的相对两端分别电性连接于所述源极23和所述准欧姆接触层25，所述准欧姆接触层25和所述光感半导体层26将所述源极23与所述漏极24之间的间隙填满。
利用所述薄膜晶体管20在光照条件下，电流-电压特性中正偏条件下的电流迟滞效应，通过施加在所述栅极21上的电压和光照对所述薄膜晶体管20器件的输出电流进行控制，可以实现对所述薄膜晶体管20的逻辑状态的控制和光存储功能。
在其中一个实施例中，所述薄膜晶体管20为底栅结构，所述准欧姆接触层25和所述光感半导体层26均设置于所述栅极21的背离所述基底10的一侧。
如图1所示，图1为本申请实施例提供的阵列基板的结构示意图，所述基底10为透明的玻璃基板，以便于光线可以从基底10一侧照射至所述光感半导体层26。
在其他一些实施例中，所述基底10的材料也可以透明的有机材料，所述有机材料可以包括但不限于聚酰亚胺（PI）、聚酰胺(PA)、聚碳酸酯(PC)、聚苯醚砜(PES)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、聚甲基丙烯酸甲酯(PMMA)、环烯烃共聚物(COC)中的一种或者多种的混合物。
所述栅极21设置于所述基底10的一侧。需要说明的是，所述栅极21设置于所述基底10的一侧，可以指的是所述栅极21与所述基底10的表面直接接触，也可以是与所述基底10间接接触。
所述栅极绝缘层27平铺设置于所述基底10的一侧，并且覆盖所述栅极21的背离所述基底10的一侧表面。所述栅极绝缘层27的材料为透明的无机材料，所述无机材料可以包括氮化硅、氧化硅以及氮氧化硅中的至少一种或者多种的混合物。所述栅极绝缘层27可以是由上述任意一种无机材料所形成的单层结构，也可以是由上述一种或者多种无机材料叠加形成的双层或者多层结构。
所述半导体层221设置于所述栅极绝缘层27的背离所述栅极21的一侧，所述半导体层221的材料为非晶硅（α-Si）。所述欧姆接触层222设置于所述半导体层221的背离所述栅极21一侧的相对两端，所述欧姆接触层222的材料为非晶硅（α-Si），所述欧姆接触层222的离子掺杂浓度大于所述半导体层221。
所述源极23设置于所述欧姆接触层222的背离所述半导体层221的一侧，所述漏极24设置于所述欧姆接触层222的背离所述半导体层221的一侧。所述源极23与所述漏极24同层设置，并且与所述漏极24的材料相同。
在本申请实施例中，所述源极23和所述漏极24的材料均为铜。
在其他一些实施例中，所述源极23和所述漏极24的材料不仅限于铜，也可以包括铝、钼、铜、铬、钨、钽以及钛中的任意一种或多种的组合，所述源极23和所述漏极24还可以是单层金属薄膜结构，也可以是两层或多层金属薄膜结构。
所述源极23与所述漏极24相互间隔设置，所述准欧姆接触层25的一端搭接在所述漏极24的背离所述欧姆接触层222的一侧，所述光感半导体层26的相对两端分别搭接在所述源极23的背离所述欧姆接触层222的一侧、以及所述准欧姆接触层25远离所述半导体层221的一侧。绝缘保护层28设置在所述准欧姆接触层25以及光感半导体层26的背离所述基底10的一侧，并且覆盖所述源极23和所述漏极24，所述像素电极30设置于所述绝缘保护层28的背离所述基底10的一侧，并通过贯穿所述绝缘保护层28的过孔与所述漏极24连接。
在本申请实施例中，所述像素电极30的材料可以是导电的透明金属氧化物。所述金属氧化物材料可以包括铟、锡、锌和镉中任意一种金属的氧化物；或者，至少两种金属的氧化物复合而成的复合多元氧化物。例如，所述金属氧化物材料可以是铟锡氧化物（ITO）、铟锌氧化物（IZO）、氧化铟（In2O3）、氧化锡（SnO2）、氧化锌（ZnO）、氧化镉（CdO）以及铝掺杂的氧化锌（AZO）中的任意一种。
在本申请实施例中，所述光感半导体层26的材料为二维硒化铟，所述准欧姆接触层25的材料为石墨。二维硒化铟为典型的二维层状半导体材料，具有优异的电学性能以及适中且可调的直接带隙，光谱响应覆盖了从近红外到紫外的范围，选用硒化铟作为光感半导体层的材料，可以提高薄膜晶体管的光响应率以及响应速度，石墨具有与硒化铟相近的电子亲和势，将石墨材料制成的准欧姆接触层25搭接在漏极24上，构筑准欧姆接触，可以减弱界面处的费米能级钉扎，有利于电流的输入和输出。
所述光感半导体层26与所述准欧姆接触层25、所述源极23、所述漏极24等构成的薄膜晶体管20为金属铜-二维硒化铟-石墨肖特基二极管，利用所述薄膜晶体管在光照条件下电流-电压特性中正偏条件下的电流迟滞效应，通过施加在栅极21的电压、以及施加在光感半导体层26的光照对所述薄膜晶体管的输出电流进行控制，进而实现对所述薄膜晶体管的逻辑状态的控制。
进一步的，所述准欧姆接触层25的厚度大于或等于20纳米且小于或等于30纳米，所述光感半导体层26的厚度大于后等于20纳米且小于或等于30纳米，所述准欧姆接触层25与所述光感半导体层26的厚度可以相等，也可以不等，所述准欧姆接触层25的厚度也可以大于所述光感半导体层26的厚度，也可以小于所述光感半导体层26的厚度，此处不做限制。
例如，所述准欧姆接触层25的厚度可以是20纳米、22纳米、25纳米、27纳米或者30纳米等，所述光感半导体层26可以是20纳米、23纳米、26纳米、27纳米或者30纳米等，以此避免所述光感半导体层26和所述准欧姆接触层25的膜层厚度过薄导致破片的情况发生。
所述光感半导体层26接受特定光照时开启所述薄膜晶体管20的最低电压为第一电压，所述光感半导体层26未接受所述特定光照时开启所述薄膜晶体管20的最低电压为第二电压，所述第一电压小于所述第二电压。
通过在薄膜晶体管上增设光感半导体层26和准欧姆接触层25，并将准欧姆接触层25与漏极24连接，同时将光感半导体层26分别与源极23和准欧姆接触层25连接，以利用光线照射光感半导体层26，减小开启所述薄膜晶体管20的最低电压。
在本申请实施例中，所述显示面板具有低功耗模式。在执行所述低功耗模式时，在特定光照下，所述显示面板的数据线向所述薄膜晶体管20的源极23施加正向电压，所述栅极控制线向所述栅极21施加低电位电压，所述低电位电压小于所述第一电压，所述薄膜晶体管20由于栅极21的电位过低而无法正常开启。
在执行所述低功耗模式时，触发所述薄膜晶体管20开启的条件为第一开启电压。在所述特定光照下，当所述栅极控制线向所述栅极21施加第一开启电压时，由于所述第一开启电压大于或等于所述第一电压，且小于所述第二电压，所述薄膜晶体管20开启。
相较于未接受所述特定光照时开启所述薄膜晶体管20的第二电压，本申请实施例中，能够在所述薄膜晶体管20接受所述特定光照时，以更小的第一开启电压开启所述薄膜晶体管20，从而可以减小所述显示面板的功耗。
需要说明的是，所述特定光照的光源可以是外部环境中的光源，也可以是显示面板内部的光源。
在其中一个实施例中，如图2所示，图2为本申请实施例提供的显示面板的第一种光照模式的示意图，图2所示的显示面板为液晶显示面板，所述显示面板可以包括阵列基板100、对置基板200、液晶层300以及背光模组400，所述阵列基板100可以为本申请实施例所提供的任意一种阵列基板，所述阵列基板100与所述对置基板200相对设置，所述液晶层300设置于所述阵列基板100与所述对置基板200之间，所述背光模组400设置于所述阵列基板100的背离所述对置基板200的一侧。
在图2所示的实施例中，所述阵列基板100可以包括如图1所示的实施例中的基底10以及薄膜晶体管20，所述对置基板200可以包括玻璃基板以及设置于所述玻璃基板靠近所述阵列基板100一侧的彩色滤光层。
在其中一个实施例中，所述栅极21的材料是透明导电的金属氧化物材料，所述背光模组400发出的光线可以沿图中箭头所示方向穿透所述栅极21，并照射至所述光感半导体层26，以此减小所述薄膜晶体管20的开启电压。
所述金属氧化物材料可以包括铟、锡、锌和镉中任意一种金属的氧化物；或者，至少两种金属的氧化物复合而成的复合多元氧化物。例如，所述金属氧化物材料可以是铟锡氧化物（ITO）、铟锌氧化物（IZO）、氧化铟（In2O3）、氧化锡（SnO2）、氧化锌（ZnO）、氧化镉（CdO）以及铝掺杂的氧化锌（AZO）中的任意一种。
在其中一个实施例中，所述栅极21的材料也可以是金属，这种情况下，所述特定光照的光源可以是外部环境中的光源。在外部环境光源充足，例如强光环境下，也可以利用外部环境中的光线照射所述薄膜晶体管20的光感半导体层26，以降低所述薄膜晶体管20的开启电压，从而可以降低所述显示面板的功耗。
具体的，所述栅极21的材料可以是铝、钼、铜、铬、钨、钽以及钛等金属材料中的任意一种或多种的组合。所述栅极21也可以是由上述多种金属材料中的任意一种所形成的单层金属薄膜结构，也可以是由上述两种或者多种材料叠加形成的多层金属薄膜结构。
进一步的，所述显示面板还可以具有书写演示模式，在执行所述书写演示模式时，触发所述薄膜晶体管20开启的条件为特定光照，而不是第二开启电压。
在执行所述书写演示模式时，在没有特定光照的条件下，所述栅极控制线可以持续向所述栅极21施加一第二开启电压，所述第二开启电压小于所述光感半导体层26未接受光照时开启所述薄膜晶体管20的最小电压（即第二电压），且大于或等于接受特定光照时开启所述薄膜晶体管20的最小电压（即第一电压），从而无法开启所述薄膜晶体管20，直至所述光感半导体层26接受特定光照时，开启所述薄膜晶体管的最低电压降低，并且小于或等于所述第二开启电压，从而可以开启所述薄膜晶体管20。
在执行所述书写演示模式时，所述特定光照的光源是外部光源。
需要说明的是，执行所述低功耗模式时的所述特定光照的光照强度可以与执行所述书写演示模式时的所述特定光照的光照强度不同，执行所述低功耗模式时的所述第一电压的大小可以与执行所述书写演示模式时的所述第一电压的大小不同。
例如图3所示，图3为本申请实施例提供的显示面板的第二种光照模式的示意图，所述外部光源可以使红外线笔或激光笔，所述红外线笔或激光笔等外部光源发出的强光束可以沿图示箭头方向穿透所述对置基板200，并照射至所述薄膜晶体管20，以降低开启所述薄膜晶体管20的最低电压，开启所述薄膜晶体管20，从而实现通过光照条件对于所述薄膜晶体管20开启和关闭的控制，在显示面板上，可以实现在前光束照射下书写演示的功能。
在其中一个实施例中，所述薄膜晶体管20也可以是顶栅结构。
如图4所示，图4为本申请实施例提供的另一种阵列基板的结构示意图，其结构与图1所示的阵列基板的结构大致相同，区别在于：所述光感半导体层26和所述准欧姆接触层25设置于所述栅极21靠近所述基底10的一侧。
如图4所示，所述光感半导体层26设置于所述基底10的一侧。需要说明的是，设置于所述基底10的一侧，可以指的是与所述基底10的一侧表面直接接触，也可以指的是与所述基底10间接接触。
所述准欧姆接触层25设置于所述基底10的一侧，所述准欧姆接触层25的一端搭接在所述光感半导体层26的背离所述基底10的一侧上，所述源极23设置于所述光感半导体层26的背离所述基底10的一侧，并与所述光感半导体层26的背离所述基底10的一侧表面直接接触，所述漏极24设置于所述准欧姆接触层25的背离所述基底10的一侧，并且与所述准欧姆接触层25的背离所述基底10的一侧表面直接接触。
所述欧姆接触层222分别设置于所述源极23的背离所述基底10的一侧、以及所述漏极24的背离所述基底10的一侧，所述半导体层221设置于所述欧姆接触层222的背离所述基底10的一侧，并且覆盖所述准欧姆接触层25以及所述光感半导体层26的背离所述基底10的一侧表面。所述栅极绝缘层27设置于所述半导体层221的背离所述基底10的一侧，所述栅极21设置于所述栅极绝缘层27的背离所述基底10的一侧，并且与所述半导体层221正对设置。
在图4所示的实施例中，若需要实现书写演示模式的功能，所述栅极21的材料可以是透明导电的金属氧化物材料，显示面板外部的强光束可以穿透所述栅极21，并照射至所述光感半导体层26。
具体的，所述金属氧化物材料可以包括铟、锡、锌和镉中任意一种金属的氧化物；或者，至少两种金属的氧化物复合而成的复合多元氧化物。例如，所述金属氧化物材料可以是铟锡氧化物（ITO）、铟锌氧化物（IZO）、氧化铟（In2O3）、氧化锡（SnO2）、氧化锌（ZnO）、氧化镉（CdO）以及铝掺杂的氧化锌（AZO）中的任意一种。
在图4所示的实施例中，若仅需要减小显示面板的功耗，所述栅极21的材料既可以为上述实施例中透明导电的金属氧化物材料，也可以为金属材料。所述金属材料可以是铝、钼、铜、铬、钨、钽以及钛等金属材料中的任意一种或多种的组合。
依据本申请上述实施例提供的显示面板，本申请实施例还提供一种显示装置，所述显示装置包括壳体、电路板、电源以及如上述实施例提供的显示面板，所述电路板以及所述电源可以安装于所述壳体内，所述显示面板可以安装于所述壳体上。所述显示装置可以是移动终端，例如彩色电子纸、彩色电子书、智能手机等，显示装置也可以是可穿戴式终端，例如智能手表、智能手环等，显示装置也可以是固定终端，例如彩色电子广告牌、彩色电子海报等。
本申请实施例的有益效果：本申请实施例提供一种阵列基板以及包括所述阵列基板的显示面板，所述阵列基板包括基底以及设置于所述基底一侧的薄膜晶体管，所述薄膜晶体管包括设置于半导体层一侧并连接于漏极的准欧姆接触层、以及连接于源极和准欧姆接触层的光感半导体层，利用外部或者内部的光线照射所述准欧姆接触层以及光感半导体层，可以减小所述薄膜晶体管的栅极开启电压，从而可以降低显示面板的功耗。
综上所述，虽然本申请以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为基准。

Claims (20)

  1. 一种阵列基板，包括：
    基底；
    薄膜晶体管，设置于所述基底的一侧，所述薄膜晶体管包括：
    栅极；
    有源层，设置于所述栅极的一侧；
    源极，设置于所述有源层的背离所述栅极的一侧，且与所述有源层接触；
    漏极，设置于所述有源层的背离所述栅极的一侧，且与所述有源层接触；所述源极与所述漏极之间具有间隔；
    准欧姆接触层，设置于所述有源层的背离所述栅极的一侧，所述准欧姆接触层电性连接于所述漏极；以及
    光感半导体层，设置于所述有源层的背离所述栅极一侧，所述光感半导体层分别电性连接所述源极和所述准欧姆接触层。
  2. 如权利要求1所述的阵列基板，其中，所述准欧姆接触层的一端搭接在所述漏极的背离所述有源层的一侧，所述光感半导体层的相对两端分别搭接在所述源极的背离所述有源层的一侧、以及所述准欧姆接触层的背离所述有源层的一侧。
  3. 如权利要求1所述的阵列基板，其中，所述准欧姆接触层的材料为石墨，所述光感半导体层的材料为硒化铟。
  4. 如权利要求1所述的阵列基板，其中，所述准欧姆接触层的厚度介于20纳米至30纳米之间，所述光感半导体层的厚度介于20纳米至30纳米之间。
  5. 如权利要求1所述的阵列基板，其中，所述光感半导体层和所述准欧姆接触层设置于所述栅极的背离所述基底的一侧。
  6. 如权利要求1所述的阵列基板，其中，所述光感半导体层和所述准欧姆接触层设置于所述栅极的靠近所述基底的一侧。
  7. 如权利要求1所述的阵列基板，其中，所述栅极的材料为透明导电的金属氧化物材料。
  8. 如权利要求7所述的阵列基板，其中，所述金属氧化物材料包括铟、锡、锌和镉中任意一种金属的氧化物；或者，至少两种金属的氧化物复合而成的复合多元氧化物。
  9. 如权利要求1所述的阵列基板，其中，所述栅极的材料为金属。
  10. 如权利要求1所述的阵列基板，其中，所述光感半导体层接受特定光照时开启所述薄膜晶体管的最低电压为第一电压，所述光感半导体层未接受所述特定光照时开启所述薄膜晶体管的最低电压为第二电压，所述第一电压小于所述第二电压。
  11. 如权利要求10所述的阵列基板，其中，所述阵列基板包括栅极控制线，所述栅极控制线连接于所述栅极；
    执行低功耗模式时，所述光感半导体层持续接受所述特定光照，当所述栅极控制线向所述栅极施加第一开启电压时，开启所述薄膜晶体管，所述第一开启电压大于或等于所述第一电压，且小于所述第二电压。
  12. 如权利要求10所述的阵列基板，其中，所述阵列基板包括栅极控制线，所述栅极控制线连接于所述栅极；
    执行书写演示模式时，所述栅极控制线向所述栅极施加不足以开启所述薄膜晶体管的第二开启电压，直至所述光感半导体层接受所述特定光照时，开启所述薄膜晶体管所述第二开启电压大于或等于所述第一电压，且小于所述第二电压。
  13. 一种显示面板，所述显示面板包括：
    阵列基板；
    对置基板，与所述阵列基板相对设置；
    液晶层，设置于所述阵列基板与所述对置基板之间；以及
    背光模组，设置于所述阵列基板的背离所述对置基板的一侧，所述阵列基板包括：
    基底；
    薄膜晶体管，设置于所述基底的一侧，所述薄膜晶体管包括：
    栅极；
    有源层，设置于所述栅极的一侧；
    源极，设置于所述有源层的背离所述栅极的一侧，且与所述有源层接触；
    漏极，设置于所述有源层的背离所述栅极的一侧，且与所述有源层接触；所述源极与所述漏极之间具有间隔；
    准欧姆接触层，设置于所述有源层的背离所述栅极的一侧，所述准欧姆接触层电性连接于所述漏极；以及
    光感半导体层，设置于所述有源层的背离所述栅极一侧，所述光感半导体层分别电性连接所述源极和所述准欧姆接触层。
  14. 如权利要求13所述的显示面板，其中，所述准欧姆接触层的一端搭接在所述漏极的背离所述有源层的一侧，所述光感半导体层的相对两端分别搭接在所述源极的背离所述有源层的一侧、以及所述准欧姆接触层的背离所述有源层的一侧。
  15. 如权利要求13所述的显示面板，其中，所述准欧姆接触层的材料为石墨，所述光感半导体层的材料为硒化铟。
  16. 如权利要求13所述的显示面板，其中，所述准欧姆接触层的厚度介于20纳米至30纳米之间，所述光感半导体层的厚度介于20纳米至30纳米之间。
  17. 如权利要求13所述的显示面板，其中，所述光感半导体层和所述准欧姆接触层设置于所述栅极的背离所述基底的一侧。
  18. 如权利要求13所述的显示面板，其中，所述光感半导体层和所述准欧姆接触层设置于所述栅极的靠近所述基底的一侧。
  19. 如权利要求13所述的显示面板，其中，所述栅极的材料为金属或者透明导电的金属氧化物材料。
  20. 如权利要求19所述的显示面板，其中，所述金属氧化物材料包括铟、锡、锌和镉中任意一种金属的氧化物；或者，至少两种金属的氧化物复合而成的复合多元氧化物。
PCT/CN2022/108680 2022-07-06 2022-07-28 阵列基板及显示面板 WO2024007386A1 (zh)

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