WO2024001394A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2024001394A1
WO2024001394A1 PCT/CN2023/086693 CN2023086693W WO2024001394A1 WO 2024001394 A1 WO2024001394 A1 WO 2024001394A1 CN 2023086693 W CN2023086693 W CN 2023086693W WO 2024001394 A1 WO2024001394 A1 WO 2024001394A1
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Prior art keywords
region
isolation
voltage
conductivity type
power device
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PCT/CN2023/086693
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English (en)
French (fr)
Inventor
刘腾
何乃龙
顾力晖
张森
章文通
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无锡华润上华科技有限公司
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Publication of WO2024001394A1 publication Critical patent/WO2024001394A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Definitions

  • the present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method of the semiconductor device.
  • High-voltage integrated circuits usually include high-voltage integrated circuits, low-voltage integrated circuits and high-voltage power devices.
  • high-voltage power devices usually adopt a "source-pack-drain" racetrack structure.
  • the way that the source terminal of this high-voltage power device is connected to low voltage and its drain terminal is connected to high voltage will cause the high-voltage cross-line to pass through the drift region of the device, thereby affecting the withstand voltage of the device.
  • there are also shortcomings such as leakage between the high-voltage integrated circuit and the drain terminal and the excessive area of the high-voltage integrated circuit device.
  • the present application provides a semiconductor device and a manufacturing method thereof to solve at least one of the above technical problems.
  • a semiconductor device includes a high-voltage device area, a low-voltage device area and an isolation area between the high-voltage device area and the low-voltage device area, and also includes:
  • a drift region is located in the high-voltage device region and has a first conductivity type
  • a second conductivity type well region is provided in the isolation region and extends to the low voltage device region, and the first conductivity type is opposite to the second conductivity type;
  • An isolation well region having the second conductivity type, is provided in the drift region and separates the drift region into a high voltage drift region and a power device drift region;
  • An isolation structure located in the isolation well region, includes a conductive structure and a dielectric layer surrounding the bottom and side surfaces of the conductive structure;
  • a power device source region is provided in the isolation region and located in the second conductivity type well region, and has the first conductivity type
  • a power device drain region is provided in the power device drift region and has the first conductivity type.
  • the power device drift region is completely surrounded by a region surrounded by the isolation well region and the second conductivity type well region.
  • the isolation well region is provided with a plurality of trenches arranged at intervals, and the trenches extend from the upper surface of the isolation well region into the isolation well region.
  • the isolation structure is provided.
  • the grooves are arranged at equal intervals.
  • the trench further extends to the bottom of the isolation well region.
  • the isolation well region is provided with a trench extending from an upper surface of the isolation well region into the isolation well region, and the depth of the trench is equal to the depth of the isolation well region.
  • the isolation structure is disposed in the trench.
  • the dielectric layer is made of silicon oxide; and/or the conductive structure is made of polysilicon.
  • the conductive structure is connected to an external potential.
  • the power device is a laterally diffused metal oxide semiconductor field effect transistor LDMOS.
  • the power device further includes:
  • a field oxide layer is provided on the drift region of the power device
  • a gate electrode is provided on the field oxide layer and extends to cover a part of the source region of the power device;
  • the substrate lead-out area has a second conductivity type, is provided in the low-voltage device area and is located in the second conductivity type well area.
  • a method for manufacturing a semiconductor device including:
  • drift region in the high-voltage device region, the drift region having a first conductivity type
  • a second conductivity type well region is formed in the isolation region, the second conductivity type well region also extends to the low voltage device region, and an isolation well region is formed in the drift region to separate the drift region into a high voltage drift region and a power device drift region, the first conductivity type is opposite to the second conductivity type;
  • the isolation structure including a conductive structure and a dielectric layer surrounding the bottom and side surfaces of the conductive structure;
  • the power device source region is located in the isolation region and located in the second conductivity type well region, and forming a power device drain region located in the power device drift region, the power device Both the source region and the power device drain region have the first conductivity type.
  • forming an isolation structure in the isolation well region includes:
  • a conductive structure filling the trench is formed.
  • the dielectric layer of the isolation structure plays an electrical isolation role, which can reduce the The leakage current from the high-voltage device region flows to the power device through the high-voltage drift region.
  • the semiconductor device can be used to reduce the leakage current flowing from the high-voltage device region to the power device through the drift region without affecting the withstand voltage of the semiconductor device.
  • Figure 1 is a perspective view of a semiconductor device in an embodiment
  • Figure 2 is a cross-sectional view of a semiconductor device in an embodiment
  • Figure 3 is a flow chart of a manufacturing method of a semiconductor device in an embodiment
  • Figure 4 is a flow chart of a manufacturing method of a semiconductor device in an embodiment
  • FIG. 5 is a flowchart of a method of manufacturing a semiconductor device in another embodiment.
  • 100 substrate; 101, high-voltage device area; 102, low-voltage device area; 200, drift area; 210, high-voltage drift area; 220, power device drift area; 310, second conductivity type well area; 320, isolation well area; 400, high-voltage power supply extraction area; 500, power device source area; 600, power device drain area; 700, isolation structure; 710, dielectric layer; 720, conductive structure; 810, field oxygen layer; 820, gate; 900. Substrate lead-out area.
  • Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown may be anticipated due, for example, to manufacturing techniques and/or tolerances. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region that appears as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by an implant may result in some implantation in the area between the buried region and the surface through which the implant occurs. Therefore, the regions shown in the figures are schematic in nature and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the invention.
  • P+ type simply represents P type with heavy doping concentration
  • P type represents medium doping concentration
  • P-type with doping concentration P-type with light doping concentration
  • N+ type represents N-type with heavy doping concentration
  • N-type N-type with medium doping concentration
  • N-type represents lightly doped concentration.
  • FIG. 1 is a perspective view of a semiconductor device in an embodiment
  • FIG. 2 is a cross-sectional view of the semiconductor device in an embodiment.
  • a semiconductor device provided by one embodiment of the present application includes a high voltage device region 101, a low voltage The device region 102 and the isolation region located between the high-voltage device region 101 and the low-voltage device region 102.
  • the semiconductor device also includes a drift region 200, a second conductivity type well region 310, an isolation well region 320, a power device source region 500, and a power device drain region. Zone 600 and isolation structure 700.
  • the substrate 100 includes a high-voltage device region 101, a low-voltage device region 102, and an isolation region located between the high-voltage device region 101 and the low-voltage device region 102.
  • the drift region 200 is provided in the high-voltage device region 101 , and the second conductivity type well region 310 is provided in the isolation region and extends to the low-voltage device region 102 .
  • the drift region 200 has a first conductivity type, and the first conductivity type is opposite to the second conductivity type.
  • One of the first conductivity type and the second conductivity type is P type, and the other type is N type.
  • the first conductivity type is N type and the second conductivity type is P type; or the first conductivity type is P type and the second conductivity type is N type.
  • the first conductivity type is N type
  • the second conductivity type is P type
  • the conductivity type of the second conductivity type well region 310 is P type
  • the conductivity type of the drift region 200 is N type.
  • the isolation well region 320 is provided in the drift region 200, and the isolation well region 320 separates the drift region 200 into a high voltage drift region 210 and a power device drift region 220.
  • the isolation structure 700 is disposed in the isolation well region 320.
  • the isolation structure 700 includes a dielectric layer 710 and a conductive structure 720.
  • the dielectric layer 710 surrounds the bottom and side surfaces of the conductive structure 720.
  • the power device source region 500 is disposed in the isolation region and is located in the second conductivity type well region 310.
  • the power device source region 500 has the first conductivity type.
  • the power device drain region 600 is disposed in the power device drift region 220.
  • the power device drain region 600 Has a first conductivity type.
  • the isolation well region 320 has a second conductivity type, and the high voltage drift region 210 and the power device drift region 220 have a first conductivity type.
  • a parasitic PN diode is formed between the isolation well region 320 and the high voltage drift region 210 , and a parasitic PN diode is also formed between the isolation well region 320 and the power device drift region 220 .
  • the parasitic PN diode formed between the isolation well region 320 and the power device drift region 220 is reverse biased, and the isolation well
  • the concentration of conductive particles decreases near the interface between the region 320 and the high voltage drift region 210 and between the isolation well region 320 and the power device drift region 220 .
  • This increases the parasitic resistance formed between the isolation well region 320 and the high-voltage drift region 210 and between the isolation well region 320 and the power device drift region 220, and reduces the conductivity, thereby reducing the passage of the high-voltage device region 101 through the drift region. 200Leakage current flowing to power devices.
  • the dielectric layer 710 of the isolation structure 700 plays an electrical isolation role, which can reduce Depend on The leakage current of the high voltage device region 101 flows to the power device through the high voltage drift region 210 .
  • the drift region 200 and the substrate 100 are in the power device drain region 600
  • the electric field peak value increases, but the conductive structure 720, the dielectric layer 710 and the isolation well region 320 form a capacitor effect similar to a conductive material-dielectric material-semiconductor, which can not only assist in depleting the drift region 200, but also cut off the reverse direction of the power device.
  • the equipotential lines at the bottom of the drift region 200 are pressed into the isolation structure 700 , the electric field peak caused by the introduction of the isolation well region 320 is greatly reduced. In this way, the semiconductor device can be used to reduce the leakage current flowing from the high-voltage device region 101 to the power device through the drift region 200 without affecting the withstand voltage of the semiconductor device.
  • the semiconductor device further includes a high-voltage power supply lead-out area 400, which is provided in the high-voltage drift area 210 for external connection to the high-voltage power supply.
  • the power device drift region 220 is completely surrounded by the area surrounded by the isolation well region 320 and the second conductivity type well region 310 .
  • the isolation well region 320 is connected to the second conductivity type well region 310 .
  • the isolation well region 320 and the second conductivity type well region 310 surround the power device drift region 220 on three sides.
  • the parasitic PN diode formed between the isolation well region 320 and the power device drift region 220 is reverse biased, the parasitic resistance formed between the isolation well region 320 and the power device drift region 220 increases. Combined with the isolation well region 320 surrounding the power device drain region 600. In this way, when the high voltage current flows to the power device drain region 600 of the power device through the drift region 200, the isolation well region 320 can be better utilized to reduce the leakage current flowing into the power device drain region 600 of the power device. Improve the reliability of semiconductor devices.
  • the isolation well region 320 is provided with a plurality of trenches arranged at intervals, and the trenches extend from the upper surface of the isolation well region 320 into the isolation well region 320 . Both are equipped with an isolation structure 700.
  • multiple trenches surround the drain region 600 of the power device, and the isolation structures 700 provided in each trench can form a capacitor effect similar to conductive material-dielectric material-semiconductor, which can not only assist in depleting the drift region 200 , it can also make the equipotential lines at the bottom of the drift region 200 press against the multiple isolation structures 700 when the power device is reversely turned off, which greatly reduces the electric field peak caused by the introduction of the isolation well region 320 and can better The leakage current flowing into the power device drain region 600 of the power device is reduced, thereby improving the reliability of the semiconductor device without affecting the withstand voltage of the semiconductor device.
  • the trenches are arranged at equal intervals, so that the capacitance between two adjacent isolation structures 700 can be regarded as equal.
  • the trench also continues to extend to the bottom of the isolation well region 320 .
  • the potential at the top of the conductive structure 720 can be equal to the potential at the bottom of the conductive structure 720, which is conducive to using the conductive structure 720, the dielectric layer 710 and the isolation well region 320 to form a capacitor effect similar to the conductive material-dielectric material-semiconductor.
  • Working hard When the rate device is reversely turned off, the equipotential line at the bottom of the drift region 200 can press against the bottom of the conductive structure 720, which greatly reduces the electric field peak caused by the introduction of the isolation well region 320.
  • the isolation well region 320 is provided with a trench extending from the upper surface of the isolation well region 320 into the isolation well region 320 .
  • the depth of the trench is the same as the depth of the isolation well region 320 .
  • An isolation structure 700 is provided inside.
  • the isolation structure 700 can form a capacitor effect similar to a conductive material-dielectric material-semiconductor, which can not only assist in depleting the drift region 200, but also press the equipotential line at the bottom of the drift region 200 against the isolation structure 700 when the power device is reversely turned off.
  • the electric field peak caused by the introduction of the isolation well region 320 is greatly reduced, and the leakage current flowing into the power device drain region 600 of the power device can be better reduced, thereby improving the reliability of the semiconductor device without sacrificing the Will affect the withstand voltage of semiconductor devices.
  • the material of the dielectric layer 710 includes silicon oxide.
  • Silicon oxide is an insulating material. Therefore, using the insulating material to electrically isolate between the high-voltage drift region 210 and the power device drift region 220 can better reduce the power device flow from the high-voltage device region 101 through the high-voltage drift region 210 to the power device.
  • the silicon oxide is silicon dioxide.
  • the material of the conductive structure 720 includes polysilicon. It is easy to fill the trench with polysilicon material and is relatively stable. Moreover, the polysilicon material can be directly implanted with impurities or doped in-situ to obtain the resistance value we need (the in-situ doping method is easy to adjust the resistance of the conductive structure 720). In other embodiments, the conductive structure 720 may also be made of other conductive materials known in the art.
  • the conductive structure 720 is connected to an external potential for applying a forward voltage when the device in the high-voltage device region 101 is powered on.
  • the isolation structure 700 can form a capacitor effect similar to a conductive material-dielectric material-semiconductor.
  • the power device leakage The region 600 and the high voltage device region 101 are depleted to the power device drift region 220.
  • a forward voltage is applied on the conductive structure 720 to assist in depleting the isolation well region 320, which can avoid the power line drop caused by the introduction of the isolation well region 320.
  • the device drift region 220 reduces leakage while hardly affecting the withstand voltage level.
  • the power device is a laterally diffused metal oxide semiconductor field effect transistor LDMOS.
  • a part of the high-voltage device region 101 and a part of the low-voltage device region 102 are used to fabricate LDMOS.
  • the part of the drift region 200 that is not surrounded by the isolation well region 320 still belongs to the high-voltage device region 101 . That is, this application embeds LDMOS in the area between the high-voltage device region 101 and the low-voltage device region 102 . There is no need to separately configure LDMOS in an additional area, which saves device area and improves chip integration. At the same time, it is also avoided that the LDMOS adopts a "source-pack-drain" racetrack structure, and the problem of the device withstand voltage being affected by the high-voltage current flowing into the drift region 200 will not occur.
  • LDMOS, the devices in the high-voltage device area 101, and the devices in the low-voltage device area 102 belong to the same driving circuit, and the LDMOS is used for level shifting.
  • the power device also includes a field oxide layer 810, a gate electrode 820, and a substrate extraction region 900.
  • the field oxide layer 810 is provided on part of the drift region 220 of the power device, and the gate electrode 820 is provided in the isolation region.
  • the substrate lead-out region 900 is provided in the low-voltage device region 102 and is located in the second conductivity type well region 310, and is located on the side of the power device source region 500 away from the gate 820, and is spaced apart from the power device source region 500.
  • the substrate lead-out region 900 has a Two conductivity types. It should be noted that in FIG. 1 , in order to show the top view structure of the isolation well region 320 and the isolation structure 700 , only one side of the field oxide layer 810 is shown.
  • the power device source region 500 is led out as the source of the power device
  • the power device drain region 600 is led out as the drain of the power device
  • the substrate lead out region 900 is used to lead out the substrate end of the power device.
  • One side of the gate 820 extends to cover a part of the power device source region 500 .
  • the gate 820 can serve as a doping injection barrier layer for injecting doping into the power device source region 500 , so that the power device source region 500 can undergo Self-aligned injection ensures the width of the conductive channel of the power device.
  • the present application accordingly provides a method for manufacturing a semiconductor device, which can be used to manufacture the semiconductor device of any of the foregoing embodiments.
  • Figure 3 is a flow chart of a manufacturing method of a semiconductor device in an embodiment, including the following steps:
  • S120 Form a second conductivity type well region in the isolation region.
  • the second conductivity type well region also extends to the low-voltage device region.
  • Form an isolation well region in the drift region to separate the drift region into a high-voltage drift region and a power device drift region.
  • the first conductivity type is opposite to the second conductivity type.
  • the isolation structure includes a conductive structure and a dielectric layer surrounding the bottom and side surfaces of the conductive structure.
  • S140 Form a power device source region, which is located in the isolation region and in the second conductivity type well region, and form a power device drain region located in the power device drift region.
  • the power device source region and the power device drain region are both Has a first conductivity type.
  • the semiconductor device produced by the manufacturing method of the semiconductor device can reduce the leakage current flowing from the high-voltage device region to the power device through the drift region without affecting the withstand voltage of the semiconductor device.
  • step S110 also includes: providing a substrate 100, which includes a high-voltage device region 101, a low-voltage device region 102, and an isolation region between the high-voltage device region 101 and the low-voltage device region 102.
  • an isolation structure is formed in the isolation well region, including:
  • the material of the dielectric layer is silicon oxide, such as silicon dioxide.
  • the conductive structure is made of polysilicon.
  • a long trench is formed in the isolation well region extending from the upper surface of the isolation well region into the isolation well region, and the depth of the trench is the same as the depth of the isolation well region.
  • An isolation structure is formed in the tank.
  • a silicon oxide layer can be formed as a dielectric layer on the inner wall of the trench through thermal oxidation.
  • the dielectric layer can also be formed on the inner wall of the trench through other processes known in the art.
  • polysilicon is selected as the conductive structure in the trench.
  • Polysilicon with a certain doping concentration can be deposited into the trenches through a deposition process to form conductive structures on the dielectric layer.
  • the doping concentration of polysilicon can be adjusted through doping processes such as in-situ doping, thereby adjusting the resistance value of polysilicon.
  • the top of the trench is flush with the top of the drift area, and the top of the conductive structure filled in the trench is also flush with the top of the drift area. In this way, the impact caused by high voltage can be better reduced. Leakage current flows from the device region to the power device through the drift region.
  • an isolation structure is formed in the isolation well region, including:
  • the isolation well region is etched downward to form a plurality of trenches spaced apart along the extension direction of the isolation well region in the isolation well region.
  • a dielectric layer is formed on the inner wall of each trench.
  • a conductive structure filling the trench is formed.
  • first conductivity type ions are implanted into part of the upper surface layer of the second conductivity type well region through a doping process, and a power device source region is formed on part of the upper surface layer of the second conductivity type well region.
  • first conductive type ions are implanted into part of the upper surface layer of the drift region of the power device through a doping process, and a power device drain region is formed on part of the upper surface layer of the drift region of the power device.
  • FIG. 5 is a flowchart of a method of manufacturing a semiconductor device in another embodiment.
  • a manufacturing method of a semiconductor device includes:
  • S220 Form a second conductivity type well region in the isolation region.
  • the second conductivity type well region also extends to the low-voltage device region.
  • Form an isolation well region in the drift region to separate the drift region into a high-voltage drift region and a power device drift region.
  • the first conductivity type is opposite to the second conductivity type.
  • the isolation structure includes a conductive structure and a dielectric layer surrounding the bottom and side surfaces of the conductive structure.
  • the power device source region is located in the isolation region and is located in the second conductivity type well region and extends under the gate.
  • a power device drain region is formed in the power device drift region, and a power device source region is formed in the power device.
  • a substrate lead-out area is provided on a side of the source area away from the gate. The substrate lead-out area is provided in the low-voltage device area and is located in the second conductivity type well area.
  • the power device source region and the power device drain region both have a first conductivity type, and the substrate lead-out region and the power device source region are spaced apart from each other and have a second conductivity type.
  • S260 Lead out the source lead-out terminal in the source area of the power device, lead out the drain lead-out terminal in the drain area of the power device, and lead out the substrate lead-out terminal in the substrate lead-out area.
  • the power device source region and the power device drain region are N+ doped regions, and the substrate extraction region is a P+ doped region.
  • an oxide layer can be formed on the drift region of the power device as a field oxide layer through a deposition process and patterning.
  • the step of forming the field oxide layer further includes a step of forming a gate electrode.
  • the step of forming the gate may include first forming a gate dielectric layer, and then forming a gate conductive layer on the gate dielectric layer.
  • the gate includes a gate dielectric layer and a gate conductive layer.
  • the gate dielectric layer is made of silicon oxide, such as silicon dioxide; the gate electrode is made of polysilicon.
  • the manufacturing method of the above-mentioned semiconductor device due to the arrangement of the isolation structure in the isolation well region, combined with the isolation structure including a dielectric layer, in the process of high-voltage current flowing to the power device through the high-voltage drift region, the dielectric layer of the isolation structure is electrified
  • the isolation effect can reduce the leakage current flowing from the high-voltage device area to the power device through the high-voltage drift area.
  • the isolation well region is introduced between the isolation well region and the high-voltage drift region and between the isolation well region and the power device drift region, the electric field peak value of the drift region and the substrate in the drain region of the power device is increased, but the conductive The structure, dielectric layer and isolation well region form a capacitor effect similar to conductive material-dielectric material-semiconductor, which can not only assist in depleting the drift region, but also press the equipotential line at the bottom of the drift region when the power device is reversely cut off.
  • the isolation structure the electric field peak caused by the introduction of the isolation well region is greatly reduced. In this way, the semiconductor device can be used to reduce the leakage current flowing from the high-voltage device region to the power device through the drift region without affecting the withstand voltage of the semiconductor device.

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Abstract

本发明涉及一种半导体器件及其制造方法。一种半导体器件，包括高压器件区、低压器件区和位于高压器件区与低压器件区之间的隔离区，还包括漂移区、第二导电类型阱区、隔离阱区、隔离结构、功率器件源区以及功率器件漏区。漂移区设于高压器件区，第二导电类型阱区设于隔离区并延伸至低压器件区，隔离阱区设于漂移区中，隔离阱区将漂移区分隔为高压漂移区和功率器件漂移区。隔离结构设于隔离阱区中。功率器件源区设于隔离区并位于第二导电类型阱区中，功率器件漏区设于功率器件漂移区中。利用该半导体器件，既能减小由高压器件区通过漂移区流向功率器件的漏电流，又不会影响半导体器件的耐压。

Description

半导体器件及其制造方法 技术领域
本发明涉及半导体制造领域，特别是涉及一种半导体器件，还涉及一种半导体器件的制造方法。
背景技术
高压集成电路通常包括高压集成电路、低压集成电路以及高压功率器件，其中，高压功率器件通常采用的是“源包漏”的跑道型结构。然而，这种高压功率器件的源端接低压且其漏端接高压的方式会导致高压跨线经过器件的漂移区，进而影响器件的耐压。此外，还存在高压集成电路与漏端之间的漏电、高压集成电路器件面积过大等缺点。
发明内容
基于此，本申请提供一种半导体器件及其制造方法，以解决上述至少一个技术问题。
一种半导体器件，包括高压器件区、低压器件区和位于高压器件区与低压器件区之间的隔离区，还包括：
漂移区，设于所述高压器件区，且具有第一导电类型；
第二导电类型阱区，设于所述隔离区并延伸至所述低压器件区，所述第一导电类型与所述第二导电类型相反；
隔离阱区，具有所述第二导电类型，设于所述漂移区中，将所述漂移区分隔为高压漂移区和功率器件漂移区；
隔离结构，设于所述隔离阱区中，包括导电结构及包围所述导电结构的底面与侧面的介电层；
功率器件源区，设于所述隔离区并位于所述第二导电类型阱区中，具有所述第一导电类型；以及
功率器件漏区，设于所述功率器件漂移区中，具有所述第一导电类型。
在其中一个实施例中，所述功率器件漂移区完全包围于所述隔离阱区与所述第二导电类型阱区围成的区域中。
在其中一个实施例中，所述隔离阱区中设有间隔设置的多个沟槽，所述沟槽从所述隔离阱区的上表面延伸入所述隔离阱区中，所述沟槽内设有所述隔离结构。
在其中一个实施例中，各所述沟槽等间距设置。
在其中一个实施例中，所述沟槽还继续延伸至所述隔离阱区的底部。
在其中一个实施例中，所述隔离阱区中设有从所述隔离阱区的上表面延伸入所述隔离阱区中的沟槽，所述沟槽的深度与所述隔离阱区的深度相同，所述沟槽内设有所述隔离结构。
在其中一个实施例中，所述介电层的材质包括硅氧化物；和/或，所述导电结构的材质包括多晶硅。
在其中一个实施例中，所述导电结构外接电位。
在其中一个实施例中，功率器件为横向扩散金属氧化物半导体场效应晶体管LDMOS。
在其中一个实施例中，所述功率器件还包括：
场氧层，设于所述功率器件漂移区上；
栅极，设于所述场氧层上，且延伸覆盖至所述功率器件源区的一部分；
衬底引出区，具有第二导电类型，设于所述低压器件区并位于所述第二导电类型阱区中。
一种半导体器件的制造方法，包括：
在高压器件区形成漂移区，所述漂移区具有第一导电类型；
在隔离区形成第二导电类型阱区，所述第二导电类型阱区还延伸至低压器件区，在所述漂移区中形成隔离阱区，以将所述漂移区分隔为高压漂移区和功率器件漂移区，所述第一导电类型与所述第二导电类型相反；
在所述隔离阱区中形成隔离结构，所述隔离结构包括导电结构及包围所述导电结构的底面与侧面的介电层；
形成功率器件源区，所述功率器件源区设于所述隔离区并位于所述第二导电类型阱区中，以及形成位于所述功率器件漂移区中的功率器件漏区，所述功率器件源区和所述功率器件漏区均具有所述第一导电类型。
在其中一个实施例中，所述在所述隔离阱区中形成隔离结构，包括：
向下刻蚀所述隔离阱区，从而在所述隔离阱区中形成至少一沟槽；
在各所述沟槽的内壁形成所述介电层；
形成填充于所述沟槽的导电结构。
上述半导体器件及其制造方法，一方面，因隔离阱区中隔离结构的设置，在高压电流通过高压漂移区流向功率器件的过程中，隔离结构的介电层起电隔离作用，可减小由高压器件区通过高压漂移区流向功率器件的漏电流。另一方面，虽然隔离阱区与高压漂移区之间以及隔离阱区与功率器件漂移区之间引入新的耗尽区，使得漂移区和衬底在功率器件漏区的电场 峰值提高，但是导电结构、介电层和隔离阱区构成类似导电材料-介电材料-半导体的电容器效果。既能辅助耗尽漂移区，还能在功率器件反向截止时使漂移区底部的等势线压在隔离结构中，极大地减小了因隔离阱区的引入而造成的电场峰值。如此，利用该半导体器件，既能减小由高压器件区通过漂移区流向功率器件的漏电流，又不会影响半导体器件的耐压。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中半导体器件的立体图；
图2是一实施例中半导体器件的剖视图；
图3是一实施例中半导体器件的制造方法的流程图；
图4是一实施例中半导体器件的制造方法的流程图；
图5是另一实施例中半导体器件的制造方法的流程图。
其中：100、衬底；101、高压器件区；102、低压器件区；200、漂移区；210、高压漂移区；220、功率器件漂移区；310、第二导电类型阱区；320、隔离阱区；400、高压电源引出区；500、功率器件源区；600、功率器件漏区；700、隔离结构；710、介电层；720、导电结构；810、场氧层；820、栅极；900、衬底引出区。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直 接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中半导体器件的立体图，图2是一实施例中半导体器件的剖视图。
请参阅图1及图2，本申请的一个实施例提供的半导体器件，包括高压器件区101、低压 器件区102和位于高压器件区101与低压器件区102之间的隔离区，半导体器件还包括漂移区200、第二导电类型阱区310、隔离阱区320、功率器件源区500、功率器件漏区600和隔离结构700。
在本申请的一个实施例中，衬底100包括高压器件区101、低压器件区102和位于高压器件区101与低压器件区102之间的隔离区。
漂移区200设于高压器件区101，第二导电类型阱区310设于隔离区并延伸至低压器件区102。其中，漂移区200具有第一导电类型，第一导电类型与第二导电类型相反。第一导电类型和第二导电类型中的其中一种类型为P型，另一种类型为N型。例如，第一导电类型为N型，第二导电类型为P型；或者，第一导电类型为P型，第二导电类型为N型。在本申请的一个实施例中，第一导电类型为N型，第二导电类型为P型，第二导电类型阱区310的导电类型为P型，漂移区200的导电类型为N型。
隔离阱区320设于漂移区200中，隔离阱区320将漂移区200分隔为高压漂移区210和功率器件漂移区220。隔离结构700设于隔离阱区320中，隔离结构700包括介电层710和导电结构720，介电层710包围导电结构720的底面与侧面。在隔离阱区320中设置介电层710，漂移区200内的掺杂离子和隔离结构700之间的电荷就更易平衡，有利于漂移区200和衬底100在功率器件漏区600的电场峰值转移至隔离阱区320中的隔离结构700上，可以有效地避免半导体器件在反向耐压时被提前击穿。
功率器件源区500设于隔离区并位于第二导电类型阱区310中，功率器件源区500具有第一导电类型，功率器件漏区600设于功率器件漂移区220中，功率器件漏区600具有第一导电类型。
隔离阱区320具有第二导电类型，高压漂移区210和功率器件漂移区220具有第一导电类型。隔离阱区320与高压漂移区210之间形成寄生PN二极管，隔离阱区320与功率器件漂移区220之间也形成寄生PN二极管。当高压器件区101的器件上电时，高压电流通过高压漂移区210流向功率器件的过程中，隔离阱区320与功率器件漂移区220之间形成的寄生PN二极管发生反向偏置，隔离阱区320与高压漂移区210之间以及隔离阱区320与功率器件漂移区220之间的交界面附近导电粒子浓度下降。这就增加了隔离阱区320与高压漂移区210之间以及隔离阱区320与功率器件漂移区220之间形成的寄生电阻，并使导电能力下降，从而减小由高压器件区101通过漂移区200流向功率器件的漏电流。
上述半导体器件，一方面，因隔离阱区320中隔离结构700的设置，在高压电流通过高压漂移区210流向功率器件的过程中，隔离结构700的介电层710起电隔离作用，可减小由 高压器件区101通过高压漂移区210流向功率器件的漏电流。另一方面，虽然隔离阱区320与高压漂移区210之间以及隔离阱区320与功率器件漂移区220之间引入新的耗尽区，使得漂移区200和衬底100在功率器件漏区600的电场峰值提高，但是导电结构720、介电层710和隔离阱区320构成类似导电材料-介电材料-半导体的电容器效果，既能辅助耗尽漂移区200，还能在功率器件反向截止时使漂移区200底部的等势线压在隔离结构700中，极大地减小了因隔离阱区320的引入而造成的电场峰值。如此，利用该半导体器件，既能减小由高压器件区101通过漂移区200流向功率器件的漏电流，又不会影响半导体器件的耐压。
在本申请的一个实施例中，半导体器件还包括高压电源引出区400，其设于高压漂移区210中，以便外接高压电源。
在本申请的一个实施例中，请参阅图1，功率器件漂移区220完全包围于隔离阱区320与第二导电类型阱区310围成的区域中。
在本申请的一个实施例中，隔离阱区320与第二导电类型阱区310连接。在图1所示的实施例中，隔离阱区320与第二导电类型阱区310在三个面上将功率器件漂移区220包围。
由于隔离阱区320与功率器件漂移区220之间形成的寄生PN二极管发生反向偏置，使得隔离阱区320与功率器件漂移区220之间形成的寄生电阻增加，结合隔离阱区320包围功率器件漏区600，如此，高压电流通过漂移区200流向功率器件的功率器件漏区600的过程中，能更好地利用隔离阱区320减小流入功率器件的功率器件漏区600的漏电流，提高半导体器件的可靠性。
在本申请的一个实施例中，请参阅图1，隔离阱区320中设有间隔设置的多个沟槽，沟槽从隔离阱区320的上表面延伸入隔离阱区320中，沟槽内均设有隔离结构700。
可以理解的是，多个沟槽围绕于功率器件漏区600，且各沟槽内设置的隔离结构700能构成类似导电材料-介电材料-半导体的电容器效果，既能辅助耗尽漂移区200，还能在功率器件反向截止时使漂移区200底部的等势线压在多个隔离结构700中，极大地减小了因隔离阱区320的引入而造成的电场峰值，能更好地减小流入功率器件的功率器件漏区600的漏电流，提高半导体器件的可靠性的同时，又不会影响半导体器件的耐压。
在本申请的一个实施例中，各沟槽等间距设置，如此，可以使得相邻的两个隔离结构700之间的电容看成是相等的。
在本申请的一个实施例中，请参阅图1及图2，沟槽还继续延伸至隔离阱区320的底部。如此，可使导电结构720的顶部的电势等于导电结构720的底部的电势，有利于利用导电结构720、介电层710和隔离阱区320构成类似导电材料-介电材料-半导体的电容器效果，在功 率器件反向截止时漂移区200底部的等势线能压在导电结构720的底部，极大地减小了因隔离阱区320的引入而造成的电场峰值。
在本申请的一个实施例中，隔离阱区320中设有从隔离阱区320的上表面延伸入隔离阱区320中的沟槽，沟槽的深度与隔离阱区320的深度相同，沟槽内设有隔离结构700。隔离结构700能构成类似导电材料-介电材料-半导体的电容器效果，既能辅助耗尽漂移区200，还能在功率器件反向截止时使漂移区200底部的等势线压在隔离结构700中，极大地减小了因隔离阱区320的引入而造成的电场峰值，能更好地减小流入功率器件的功率器件漏区600的漏电流，提高半导体器件的可靠性的同时，又不会影响半导体器件的耐压。
在本申请的一个实施例中，介电层710的材质包括硅氧化物。硅氧化物属于绝缘材料，如此，利用绝缘材料电隔离于高压漂移区210和功率器件漂移区220之间，可更好地减小由高压器件区101通过高压漂移区210流向功率器件的功率器件漏区600的漏电流。示例性地，硅氧化物为二氧化硅。
在本申请的一个实施例中，导电结构720的材质包括多晶硅。采用多晶硅材料填充易于将沟槽填满，且比较稳定。并且，多晶硅材料可以直接通过杂质注入或者原位掺杂来获得我们需要的电阻值(原位掺杂方式易于调节导电结构720的电阻)。在其他实施例中，导电结构720的材质也可以采用本领域习知的其他导电材料。
在本申请的一个实施例中，导电结构720外接电位，以用于在高压器件区101的器件上电时被施加正向电压。
如前述所述，隔离结构700能构成类似导电材料-介电材料-半导体的电容器效果，当高压器件区101的器件上电从而高压器件区101与功率器件漏区600加高压时，功率器件漏区600与高压器件区101向功率器件漂移区220耗尽，在导电结构720上施加正向电压以辅助耗尽隔离阱区320，可避免因隔离阱区320的引入而产生的电力线降在功率器件漂移区220，减小漏电的同时几乎不会影响耐压水平。
在本申请的一个实施例中，功率器件是横向扩散金属氧化物半导体场效应晶体管LDMOS。
高压器件区101的一部分和低压器件区102的一部分用来制作得到LDMOS，漂移区200中未被隔离阱区320包围的部分仍然属于高压器件区101。即，本申请在高压器件区101和低压器件区102之间的区域中嵌入LDMOS。无需额外的区域单独设置LDMOS，节约了器件面积，提高芯片集成度。同时也避免了LDMOS采用“源包漏”跑道型结构，不会出现因流入漂移区200的高压电流而影响器件耐压的问题。
在本申请的一个实施例中，LDMOS、高压器件区101中的器件、低压器件区102中的器件属于同一个驱动电路，LDMOS用于电平移位。在本申请的一个实施例中，功率器件还包括场氧层810、栅极820及衬底引出区900，场氧层810设于功率器件的部分漂移区220上，栅极820设于隔离区的第二导电类型阱区310上，且栅极820的一侧延伸覆盖至场氧层810上，且栅极820的另一侧延伸覆盖至功率器件源区500的一部分，衬底引出区900设于低压器件区102并位于第二导电类型阱区310中，且位于功率器件源区500背离栅极820的一侧，并与功率器件源区500彼此间隔设置，衬底引出区900具有第二导电类型。需要指出的是，图1中为了示出隔离阱区320和隔离结构700的俯视结构，因此场氧层810只画出了一面。
功率器件源区500引出作为功率器件的源极，功率器件漏区600引出作为功率器件的漏极，衬底引出区900用于引出功率器件的衬底端。
栅极820的一侧延伸覆盖至功率器件源区500的一部分，在功率器件形成的过程中栅极820可以作为功率器件源区500注入掺杂的注入阻挡层，以使功率器件源区500进行自对准注入，保证功率器件的导电沟道的宽度。本申请相应提供一种半导体器件的制造方法，可以用于制造前述任一实施例的半导体器件。图3是一实施例中半导体器件的制造方法的流程图，包括下列步骤：
S110、在高压器件区形成漂移区，漂移区具有第一导电类型。
S120、在隔离区形成第二导电类型阱区，第二导电类型阱区还延伸至低压器件区，在漂移区中形成隔离阱区，以将漂移区分隔为高压漂移区和功率器件漂移区，第一导电类型与第二导电类型相反。
S130、在隔离阱区中形成隔离结构，隔离结构包括导电结构及包围所述导电结构的底面与侧面的介电层。
S140、形成功率器件源区，功率器件源区设于隔离区并位于第二导电类型阱区中，以及形成位于功率器件漂移区中的功率器件漏区，功率器件源区和功率器件漏区均具有第一导电类型。
利用该半导体器件的制造方法制得的半导体器件，既能减小由高压器件区通过漂移区流向功率器件的漏电流，又不会影响半导体器件的耐压。
在本申请的一个实施例中，步骤S110之前还包括：提供衬底100，衬底100包括高压器件区101、低压器件区102和位于高压器件区101与低压器件区102之间的隔离区。
在本申请的一个实施例中，请参阅图4，在隔离阱区中形成隔离结构，包括：
S131、向下刻蚀隔离阱区，从而在隔离阱区中形成至少一沟槽。
S132、在各沟槽的内壁形成介电层。
S133、形成填充于沟槽的导电结构。
在一些实施例中，介电层的材质为硅氧化物，例如二氧化硅。导电结构的材质为多晶硅。
在本申请的一个实施例中，在隔离阱区中形成从隔离阱区的上表面延伸入隔离阱区中的一个长条型沟槽，且沟槽的深度与隔离阱区的深度相同，沟槽内形成隔离结构。
在本申请的一个实施例中，可通过热氧化在沟槽的内壁形成硅氧化层作为介电层。在其他实施例中，也可以通过本领域习知的其他工艺在沟槽的内壁形成介电层。
在本申请的一个实施例中，沟槽中的导电结构选用多晶硅。可以通过淀积工艺向沟槽中淀积一定掺杂浓度的多晶硅，以在介电层上形成导电结构。
在本申请的一个实施例中，可以通过原位掺杂等掺杂工艺调整多晶硅的掺杂浓度，从而调节多晶硅的电阻值。
在本申请的一个实施例中，沟槽的顶部与漂移区的顶部平齐，那么填充于沟槽内的导电结构的顶部也与漂移区的顶部平齐，如此，可更好减小由高压器件区通过漂移区流向功率器件的漏电流。
在本申请的一个实施例中，在隔离阱区中形成隔离结构，包括：
向下刻蚀隔离阱区，以在隔离阱区中形成沿隔离阱区的延伸方向间隔布设的多个沟槽。
在各沟槽的内壁形成介电层。
形成填充于沟槽的导电结构。
在本申请的一个实施例中，通过掺杂工艺向第二导电类型阱区的部分上表层注入第一导电类型离子，在第二导电类型阱区的部分上表层形成功率器件源区。
在本申请的一个实施例中，通过掺杂工艺向功率器件漂移区的部分上表层注入第一导电类型离子，在功率器件漂移区的部分上表层形成功率器件漏区。
图5是另一实施例中半导体器件的制造方法的流程图。
在本申请的一个实施例中，请参阅图5，半导体器件的制造方法包括：
S210、在高压器件区形成漂移区，漂移区具有第一导电类型。
S220、在隔离区形成第二导电类型阱区，第二导电类型阱区还延伸至低压器件区，在漂移区中形成隔离阱区，以将漂移区分隔为高压漂移区和功率器件漂移区，第一导电类型与第二导电类型相反。
S230、在隔离阱区中形成隔离结构，隔离结构包括导电结构及包围所述导电结构的底面与侧面的介电层。
S240、在部分的功率器件漂移区上形成场氧层，在隔离区并在第二导电类型阱区上形成栅极，栅极延伸覆盖至未被场氧层覆盖的功率器件漂移区后，还继续延伸覆盖至场氧层的一部分。
S250、形成功率器件源区，功率器件源区设于隔离区并位于第二导电类型阱区中且延伸至栅极下，形成位于功率器件漂移区中的功率器件漏区，以及形成位于功率器件源区背离栅极的一侧的衬底引出区，衬底引出区设于低压器件区并位于第二导电类型阱区中。功率器件源区和功率器件漏区均具有第一导电类型，衬底引出区与功率器件源区彼此间隔设置，且具有第二导电类型。
S260、在功率器件源区引出源极引出端，在功率器件漏区引出漏极引出端，在衬底引出区引出衬底引出端。
在本申请的一个实施例中，功率器件源区和功率器件漏区为N+掺杂区，衬底引出区为P+掺杂区。
在本申请的一个实施例中，可以通过淀积工艺和图案化在功率器件漂移区上形成一层氧化层作为场氧层。
在本申请的一个实施例中，形成场氧层的步骤之后还包括形成栅极的步骤。形成栅极的步骤可以包括先形成栅介电层，然后在栅介电层上形成栅极导电层，栅极包括栅介电层和栅极导电层。
在本申请的一个实施例中，栅介电层的材质为硅氧化物，例如二氧化硅；栅极的材质为多晶硅。
上述半导体器件的制造方法，一方面，因隔离阱区中隔离结构的设置，结合隔离结构包括介电层，在高压电流通过高压漂移区流向功率器件的过程中，隔离结构的介电层起电隔离作用，可减小由高压器件区通过高压漂移区流向功率器件的漏电流。另一方面，虽然隔离阱区与高压漂移区之间以及隔离阱区与功率器件漂移区之间引入新的耗尽区，使得漂移区和衬底在功率器件漏区的电场峰值提高，但是导电结构、介电层和隔离阱区构成类似导电材料-介电材料-半导体的电容器效果，既能辅助耗尽漂移区，还能在功率器件反向截止时使漂移区底部的等势线压在隔离结构中，极大地减小了因隔离阱区的引入而造成的电场峰值。如此，利用该半导体器件，既能减小由高压器件区通过漂移区流向功率器件的漏电流，又不会影响半导体器件的耐压。
应该理解的是，虽然本申请的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行 并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，本申请的流程图中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体器件，包括高压器件区、低压器件区和位于高压器件区与低压器件区之间的隔离区，其特征在于，还包括：
    漂移区，设于所述高压器件区，且具有第一导电类型；
    第二导电类型阱区，设于所述隔离区并延伸至所述低压器件区，所述第一导电类型与所述第二导电类型相反；
    隔离阱区，具有所述第二导电类型，设于所述漂移区中，将所述漂移区分隔为高压漂移区和功率器件漂移区；
    隔离结构，设于所述隔离阱区中，包括导电结构及包围所述导电结构的底面与侧面的介电层；
    功率器件源区，设于所述隔离区并位于所述第二导电类型阱区中，具有所述第一导电类型；以及
    功率器件漏区，设于所述功率器件漂移区中，具有所述第一导电类型。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述功率器件漂移区完全包围于所述隔离阱区与所述第二导电类型阱区围成的区域中。
  3. 根据权利要求1所述的半导体器件，其特征在于，所述隔离阱区中设有间隔设置的多个沟槽，所述沟槽从所述隔离阱区的上表面延伸入所述隔离阱区中，所述沟槽内设有所述隔离结构。
  4. 根据权利要求3所述的半导体器件，其特征在于，各所述沟槽等间距设置。
  5. 根据权利要求3所述的半导体器件，其特征在于，所述沟槽还继续延伸至所述隔离阱区的底部。
  6. 根据权利要求2所述的半导体器件，其特征在于，所述隔离阱区中设有从所述隔离阱区的上表面延伸入所述隔离阱区中的沟槽，所述沟槽的深度与所述隔离阱区的深度相同，所述沟槽内设有所述隔离结构。
  7. 根据权利要求1所述的半导体器件，其特征在于，所述介电层的材质包括硅氧化物；和/或，所述导电结构的材质包括多晶硅。
  8. 根据权利要求1所述的半导体器件，其特征在于，所述导电结构外接电位。
  9. 根据权利要求1所述的半导体器件，其特征在于，半导体器件还包括高压电源引出区，所述高压电源引出区设于高压漂移区中。
  10. 根据权利要求1-9任一项所述的半导体器件，其特征在于，功率器件为横向扩散金属氧化物半导体场效应晶体管LDMOS。
  11. 根据权利要求10所述的半导体器件，其特征在于，所述功率器件还包括：
    场氧层，设于所述功率器件漂移区上；
    栅极，设于所述场氧层上，且延伸覆盖至所述功率器件源区的一部分；
    衬底引出区，具有第二导电类型，设于所述低压器件区并位于所述第二导电类型阱区中。
  12. 一种半导体器件的制造方法，其特征在于，包括：
    在高压器件区形成漂移区，所述漂移区具有第一导电类型；
    在隔离区形成第二导电类型阱区，所述第二导电类型阱区还延伸至低压器件区，在所述漂移区中形成隔离阱区，以将所述漂移区分隔为高压漂移区和功率器件漂移区，所述第一导电类型与所述第二导电类型相反；
    在所述隔离阱区中形成隔离结构，所述隔离结构包括导电结构及包围所述导电结构的底面与侧面的介电层；
  13. 形成功率器件源区，所述功率器件源区设于所述隔离区并位于所述第二导电类型阱区中，以及形成位于所述功率器件漂移区中的功率器件漏区，所述功率器件源区和所述功率器件漏区均具有所述第一导电类型。根据权利要求12所述的半导体器件的制造方法，其特征在于，所述在高压器件区形成漂移区之前还包括：提供衬底，所述衬底包括所述高压器件区、所述低压器件区和位于所述高压器件区与所述低压器件区之间的所述隔离区。
  14. 根据权利要求12所述的半导体器件的制造方法，其特征在于，所述在所述隔离阱区中形成隔离结构，包括：
    向下刻蚀所述隔离阱区，从而在所述隔离阱区中形成至少一沟槽；
    在各所述沟槽的内壁形成所述介电层；
    形成填充于所述沟槽的导电结构。
  15. 根据权利要求14所述的半导体器件的制造方法，其特征在于，所述沟槽的顶部与漂移区的顶部平齐。
PCT/CN2023/086693 2022-06-30 2023-04-06 半导体器件及其制造方法 WO2024001394A1 (zh)

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