WO2024001098A1

WO2024001098A1 - Display device, source chip on film, and driving method

Info

Publication number: WO2024001098A1
Application number: PCT/CN2022/141124
Authority: WO
Inventors: 张大雷; 林沛炀; 阮永鑫; 刘洪海; 袁海江
Original assignee: 惠科股份有限公司
Priority date: 2022-06-30
Filing date: 2022-12-22
Publication date: 2024-01-04
Also published as: CN114822401B; CN114822401A

Abstract

A display device (500), a source chip on film, and a driving method. The display device (500) comprises a first source chip on film (300) and a second source chip on film (400). The first source chip on film (300) and the second source chip on film (400) are both connected to a printed circuit board (200) and a display panel (100). The first source chip on film (300) comprises a first source driver IC (320) and a first timing control IC (310). The second source chip on film (400) comprises a second source driver IC (420). The first timing control IC (310) receives a signal to be parsed which is outputted by the printed circuit board (200), and parses, generates and outputs a first parsed signal and a second parsed signal. The first source driver IC (320) and the second source driver IC (420) simultaneously drive the display panel (100) according to the first parsed signal and the second parsed signal. The display device (500) can display a high resolution when employing a Tconless framework.

Description

Display device, source chip-on-chip film and driving method

This application claims priority to the Chinese patent application submitted to the China Patent Office on June 30, 2022, with the application number CN2022107545051 and the application name "Display device, source electrode on-chip film and driving method", the entire content of which is incorporated by reference. in this application.

Technical field

The present application relates to the field of display technology, and in particular, to a display device, a source electrode on-chip film and a driving method.

Background technique

At present, for displays, such as NB (Note book) displays, with the development of products, the quality requirements for products are getting higher and higher, and the frame requirements are getting narrower, which leads to an increase in product development costs. In addition, for In the development of narrow borders, one of the electrical components that determines the width of the product frame is TCON IC (timing control chip). TCON IC is usually packaged on a printed circuit board. However, the packaging of TCON IC requires a large space, which limits The size of the printed circuit board, in turn, limits the width of the product frame. In existing narrow-frame screen designs, the TCON IC on the printed circuit board is usually removed, and the functions of the TCON IC are integrated on the source flip-chip film (Tconless for short). ), which can reduce the number of independent TCON ICs and achieve the effect of narrow bezels of the product at the same time;

However, the current Tconless architecture can only be applied to HD (1366*768) resolution display devices, and is difficult to apply to higher resolution display devices; therefore, there is no need to change the front-end design (such as the NB control circuit board). And how to achieve high-resolution display using the Tconless architecture without improving the production process of the Source IC has become an urgent technical problem that needs to be solved by those skilled in the field.

Application content

The purpose of this application is to provide a display device, a source chip-on-chip film and a driving method that can achieve high-resolution display while adopting a Tconless architecture.

This application discloses a display device, which includes a display panel and a printed circuit board. The printed circuit board is connected to the display panel. The display device also includes a first source electrode on-chip film and a second source electrode on-chip film. , the first source electrode chip-on-chip film and the second source electrode chip-on-chip film are connected to the printed circuit board and the display panel; the first source electrode chip-on-chip film includes a first source driver chip and A first timing control chip. The second source electrode on-chip film includes a second source driver chip. The first timing control chip is electrically connected to the first source driver chip and the second source driver chip respectively. The first timing control chip receives the signal to be analyzed output by the printed circuit board, analyzes, generates and outputs the first analysis signal and the second analysis signal; the first source driver chip receives the first analysis signal signal, the second source driver chip receives the second analysis signal, and the first source driver chip and the second source driver chip simultaneously drive the display panel.

This application also discloses a source electrode on-chip film, used to connect a printed circuit board and a display panel, and applied to a display device. The source electrode on-chip film includes a source driver chip and a timing control chip. The timing control chip Integrated in the source driver chip, the timing control chip includes an input port, a first group of output ports and a second group of output ports. The input port receives the signal to be analyzed, analyzes, generates and outputs the first analysis signal. and a second analysis signal, the first group of output ports outputs the first analysis signal to the source driver chip, and the second group of output ports outputs the second analysis signal to the printed circuit board;

The display device includes a display panel and a printed circuit board, and the printed circuit board is connected to the display panel, wherein the source-level chip-on-chip film includes a first source chip-on-chip film and a second source chip-on-chip film, The first source chip-on-chip film and the second source chip-on-chip film are both connected to the printed circuit board and the display panel;

The first source electrode on-chip film includes a first source driver chip and a first timing control chip, the second source electrode on-chip film includes a second source driver chip, and the first timing control chip is respectively connected with the The first source driver chip and the second source driver chip are electrically connected;

Wherein, the first timing control chip receives the signal to be analyzed output by the printed circuit board, analyzes to generate and output the first analysis signal and the second analysis signal; the first source driver chip receives the first analysis signal , the second source driver chip receives the second analysis signal, and the first source driver chip and the second source driver chip drive simultaneously according to the first analysis signal and the second analysis signal. The display panel.

This application also discloses a driving method, applied to a display device, including the steps:

The first timing control chip receives the signal to be analyzed and analyzes it to generate a first analysis signal and a second analysis signal; and

After the first source driver chip receives the first analysis signal, and the second source driver chip receives the second analysis signal, the first source driver chip and the second source driver chip drive simultaneously according to the first analysis signal and the second analysis signal. display panel;

Wherein, the display device includes a display panel and a printed circuit board, the printed circuit board is connected to the display panel, the display device further includes a first source electrode chip-on-chip film and a second source electrode chip-on-chip film, The first source electrode chip-on-chip film and the second source electrode chip-on-chip film are both connected to the printed circuit board and the display panel;

This application disposes the first timing control chip and the first source driver chip on the first source electrode on the chip and the second source driver chip on the second source on the chip. The first timing control chip receives the printed circuit. The signal to be analyzed outputted by the board is then analyzed to generate two analysis signals and transmitted to the first source driver chip and the second source driver chip respectively, and then the first source driver chip and the second source driver chip simultaneously drive the display. The panel can achieve high-resolution output, and the display device under the Tconless architecture can achieve high-resolution output without the need for additional conversion circuits.

Description of drawings

The accompanying drawings are included to provide a further understanding of the embodiments of the application, and constitute a part of the specification for illustrating the embodiments of the application and together with the written description to explain the principles of the application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting any creative effort. In the attached picture:

Figure 1 is a schematic structural diagram of a display device according to the first embodiment of the present application;

Figure 2 is a schematic structural diagram of a display device according to the second embodiment of the present application;

Figure 3 is a schematic structural diagram of a source electrode on-chip film according to the third embodiment of the present application;

Figure 4 is a flow chart of a driving method according to the fourth embodiment of the present application.

Detailed ways

It should be understood that the terminology used and the specific structural and functional details disclosed here are only for describing specific embodiments and are representative. However, the present application can be specifically implemented in many alternative forms and should not be interpreted as merely are limited to the embodiments set forth herein.

In the description of the present application, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating relative importance or implicitly indicating the number of indicated technical features. Therefore, unless otherwise stated, features defined as “first” and “second” may explicitly or implicitly include one or more of the features; “plurality” means two or more. The term "comprises" and any variations thereof, means the non-exclusive inclusion of the possible presence or addition of one or more other features, integers, steps, operations, units, components and/or combinations thereof.

In addition, "center", "horizontal", "top", "bottom", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" The terms indicating the orientation or positional relationship, etc. are described based on the orientation or relative positional relationship shown in the drawings, and are only used to facilitate the simplified description of the present application, and do not indicate that the device or element referred to must have a specific orientation. , is constructed and operated in a specific orientation and therefore cannot be construed as a limitation on this application.

In addition, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection. , or it can be an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or an internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

The present application will be described in detail below with reference to the accompanying drawings and optional embodiments. It should be noted that, on the premise that there is no conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments. .

In current products, removing the TCON IC on the printed circuit board and integrating the functions of the TCON IC on the source chip-on-chip film (Tconless for short) is an important design to achieve narrow bezel design; in display devices using the Tconless architecture, when After TCON IC receives the signal to be analyzed (usually EDP signal), it will analyze and output the analytical signal (usually point to point signal, referred to as P-P signal) to the source driver chip on the source chip-on-chip film. The source driver chip The analysis signal is then output to drive the display panel, thereby realizing the display of the display device.

Taking the NB display device as an example, in order to achieve a narrower frame, a Tconless architecture will be used. In this case, only one source on-chip film is generally used, and the TOCN IC is integrated into the source driver chip on the source on-chip film. This When the TOCN IC receives as many signals to be analyzed, it will output the analysis signals generated by the corresponding analysis to the source driver chip. This means that the number of output channels the source driver chip has can achieve the same resolution display.

However, nowadays, due to the production process of the source driver chip, the number of output channels on the source driver chip is limited. The number of output channels on the source driver chip can only achieve HD (1366*768) resolution. However, it cannot meet higher resolution output, such as FHD (1920*1080), etc. In order to achieve FHD and higher resolution display, the current solutions are mainly:

1. Display devices that do not use the Tconless architecture continue to package the TCON IC on the printed circuit board. The FHD resolution display is achieved through the TCON IC on the printed circuit board and two source chip-on-chip films. However, this will cause TCON The IC is packaged on a printed circuit board. The area of the printed circuit board is relatively large, and there will be a problem of a large frame of the display screen. Even if the FHD resolution display can be achieved, it will conflict with the narrow-framed screen that is currently pursued by the mainstream, and Not a good solution;

2. Display devices using the Tconless architecture, taking the NB display device as an example. The NB display panel includes the NB control circuit board at the front end, and the NB display screen (with printed circuit board and source chip-on-chip film, etc.). When using the Tconless architecture Under the premise, a conversion circuit needs to be added to the NB control circuit board to split the signal to be analyzed (for example: EDP signal) into two signals, and then transmit them to the two source chip-on-chip films through the printed circuit board. Although such a design can achieve high resolution, the conversion circuit itself is more complex, and the stability and consistency of the signal are more difficult to control. Moreover, the conversion circuit involves front-end design, which is more troublesome. Therefore, the applicant considers the above solutions. The problems that arise in this application have been improved through continuous research and experiments, as detailed below:

Figure 1 is a schematic structural diagram of a display device according to the first embodiment of the present application. As shown in Figure 1, as the first embodiment of the present application, a display device 500 is disclosed. The display device 500 includes a display panel 100 and a printed circuit board 200. The printed circuit board 200 is connected to the display panel 100. The display device 500 also includes a first source electrode chip-on-chip film 300 and a second source electrode chip-on-chip film 400. The electrode chip-on-chip film 300 and the second source chip-on-chip film 400 are both connected to the printed circuit board 200 and the display panel 100. The first source chip-on-chip film 300 includes a first source driver chip 320 and The first timing control chip 310, the second source electrode on-chip film 400 includes a second source driver chip 420, the first timing control chip 310 is respectively connected with the first source driver chip 320 and the second source driver chip 420. The source driver chip 420 is electrically connected; the first timing control chip 310 receives the signal to be analyzed output from the printed circuit board 200, analyzes, generates and outputs a first analysis signal and a second analysis signal. The first source The driver chip 320 receives the first analysis signal, the second source driver chip 420 receives the second analysis signal, and the first source driver chip 320 and the second source driver chip 420 operate according to the The first analysis signal and the second analysis signal drive the display panel 100 simultaneously.

Compared with the display device using Tconless architecture, it breaks through the conventional practice that the TCON IC located on the source flip-chip film is only for the source driver chip on the current source flip-chip film to process signals. This application is located on the first source flip-chip The first timing control chip 310 on the film 300 not only processes the signals to be analyzed corresponding to the first source driver chip 320, but also processes the signals to be analyzed corresponding to other source electrode on-chip films. The first timing control chip 310 analyzes the signal to be analyzed, and then transmits the first analysis signal generated by the analysis to the first source driver chip 320, and transmits the second analysis signal to the second source driver chip 420, through the first source driver chip 320 and the second source driver chip 420 output at the same time to drive the display panel 100 for display; this makes the application do not need to make changes to the front end (for example, adding a conversion circuit on the main control board of the front end to split the signal to be analyzed), and also There is no need to use a source driver chip with higher process requirements and a higher number of channels, and on the premise of achieving narrow borders, high-resolution display can still be achieved based on the Tconless architecture.

Wherein, there may be multiple second source driver chips 420, and there may also be multiple second analysis signals, and the number of the second analysis signals is the same as the number of the second source driver chips 420. When designing the display device 500, the designer can select and set the number of the second source driver chips 420 according to the resolution of the display screen, thereby achieving a high-resolution display screen; in addition, in this embodiment, the NB display Taking the device as an example, the printed circuit board 200 is the printed circuit board 200 in the display screen of the display device 500 .

Optional in this embodiment, in this application, after receiving the EDP signal output from the printed circuit board 200, the first timing control chip 310 on the first source over-chip film 300 analyzes and generates the first analysis signal and the second analysis signal. , the first analysis signal is a first point to point signal, the second analysis signal is a second point to point signal, and the first timing control chip 310 includes a first group of output ports 312 and a second group of outputs Port 313. The first timing control chip 310 outputs the first point-to-point signal to the first source driver chip 320 through the first group of output ports 312. The first timing control chip 310 outputs the first point-to-point signal to the first source driver chip 320 through the first group of output ports 312. The two sets of output ports 313 output the second point-to-point signal to the second source driver chip 420. The first source driver chip 320 and the second source driver chip 420 are driven simultaneously according to the first point-to-point signal and the second point-to-point signal. The display panel 100 realizes high-resolution display.

In a display device using a Tconless architecture, the input terminal and output terminal of the timing control chip are matched with the output channel of the source driver chip. Compared with the existing technology, the first timing control chip 310 of the present application is provided with a corresponding In addition to the first set of output ports 312 of the first source driver chip 320, a second set of output ports 313 is additionally provided. The second set of output ports 313 is used to output the second point-to-point signal generated by analysis of the first timing control chip 310. Give the source driver chip of another source overlay film to achieve a higher resolution display.

Among them, regarding the signal to be analyzed and the analysis signal: the signal to be analyzed can be an EDP signal. The EDP signal is a high-speed signal, and the display device 500 uses the EDP signal for transmission. Compared with using the LVDS signal, the EDP signal is transmitted Signal transmission lines require fewer pairs of wires, which is conducive to high-speed signal transmission and narrow borders; however, the existing printed circuit board 200 located at the back end cannot directly separate a group of EDP signals on a group of lines. Divided into two groups of EDP signals; this is also the reason why the two existing solutions cannot perform high-resolution display based on the Tconless architecture without changing the front-end design and achieving narrow borders; and based on the technical solution of this application , based on the Tconless architecture, EDP signals can be used to achieve high-resolution display.

In this embodiment, in order to quickly transmit the second analysis signal (ie, the second point-to-point signal) to the second source driver chip 420 on the second source on-chip film 400 while minimizing signal loss, the following is used Solution: The printed circuit board 200 is provided with a high-speed signal line 210 connecting the first source chip-on-chip film 300 and the second source chip-on-chip film 400. The first timing control chip 310 can pass through the high-speed signal line. Step 210 outputs the second analysis signal generated by analysis to the second source driver chip 420 . Doing so can ensure transmission efficiency and transmission quality, and by doing so, even if the TCON IC is not set on the printed circuit board 200, the driving requirements for multiple source electrode flip-chips can be achieved; of course, if future processes can ensure deposition If the traces on the glass substrate can also transmit high-speed signals, the second analytical signal can also be transmitted using traces deposited in the non-display area of the display panel 100 .

In addition, in order to ensure that there is no obvious difference in the display screen, the specifications of the first analysis signal and the second analysis signal are exactly the same, and the first source electrode flip-chip film 300 and the second source electrode flip-chip film 400 are used to drive the half screen respectively. For example, the first timing control chip 310 splits the analytically generated half signal into a first analytical signal and a second analytical signal. In this case, the first source electrode chip-on-chip film 300 and the second source electrode chip-on-chip film 400 transmit The difference in the signals will be reduced accordingly, thereby reducing the display difference problem; of course, it can also be split into unequal first analytical signals and second analytical signals. In this case, an additional signal compensation module needs to be set up to avoid display Difference issue.

In this embodiment, the first timing control chip 310 is integrated into the first source driver chip 320 as a functional module, and is uniformly packaged on the first source on-chip film 300. It may also be the The first timing control chip 310 and the first source driver chip 320 are separately packaged and respectively disposed on the first source on-chip film 300. Of course, no matter which arrangement method is used, the first timing control chip 310 They are all used to receive the signal to be analyzed and analyze it to generate the first analysis signal and the second analysis signal. The arrangement of the second source electrode on-chip film 400 can also be the same as the arrangement of the first source electrode on-chip film 300 .

The second source chip-on-chip film 400 may or may not be provided with a timing control chip. When the second source chip-on-chip film 400 is not provided with a timing control chip, existing technology may be used. The chip-on-chip film does not require improvements to the chip-on-chip film. This solution can reduce costs.

Based on the fact that the second source on-chip film 400 does not include a timing control chip, the display device 500 further includes a compensation module for connecting the first source driver chip 320 and/or the second source driver chip. 420, used to compensate the first analysis signal and/or the second analysis signal so that the signal strengths of the first analysis signal and the second analysis signal are consistent to prevent the setting of the main timing control chip. When the first timing control chip 310 outputs the second analysis signal to the second source driver chip 420 or the first source driver chip 320, the second analysis signal is affected by problems such as wire impedance or voltage fluctuation during the transmission process, resulting in signal The intensity decrease causes the signal intensity of the second analysis signal output to the display panel 100 to be different from the signal intensity of the first analysis signal output to the display panel 100 , resulting in a display difference problem.

In order to ensure that the first source driver chip 320 and the second source driver chip 420 can drive the display panel 100 at the same time, the display device 500 further includes a synchronization module, which connects the first source driver chip 320 and the second source driver chip 420 . Two source driver chips 420 are used to drive the display panel 100 at the same time. Of course, a bent signal transmission line can also be provided at the first group of output ports 312 of the first source driver chip 320 to allow the first source driver chip 320 to The time at which the signal is output to the display panel 100 is the same as the time at which the second source driver chip 420 outputs the signal to the display panel 100, thereby achieving simultaneous driving of the display panel 100.

As follows, we will focus on the solution of setting the timing control chip for the second flip-chip film 400:

Figure 2 is a structural diagram of a display device according to the second embodiment of the present application. As shown in Figure 2, in order to ensure the consistency of the production process of the first source electrode on-chip film 300 and the second source electrode on-chip film 400, The second source electrode on-chip film 400 also includes a second timing control chip 410. The second timing control chip 410 is used to receive the second analysis signal and output the second analysis signal to the For the second source driver chip 420 , the first source chip-on-chip film 300 and the second source chip-on-chip film 400 have the same specifications.

Wherein, the first source electrode chip-on-chip film 300 and the second source electrode chip-on-chip film 400 have the same production process. Because the process difference of the source chip-on-chip film is too large, it will lead to obvious signal difference problems, thereby improving the display difference problems caused by signal differences;

Furthermore, in order to easily distinguish the functions of the first source chip-on-chip film 300 and the second source chip-on-chip film 400 during use, the display device 500 further includes a control module for controlling the first source chip-on-chip film 300 . The master-slave relationship between the timing control chip 310 and the second timing control chip 410 is set as the master timing when the first timing control chip 310 or the second timing control chip 410 is set as the master timing control chip. The first timing control chip 310 or the second timing control chip 410 of the control chip receives the signal to be analyzed and outputs the first analysis signal and the second analysis signal; when the first timing control chip 310 or the second timing control chip When 410 is set as a slave timing control chip, the first timing control chip 310 or the second timing control chip 410 is set as a slave timing control chip to receive the second analysis signal and output the second analysis signal.

When assembling the display device 500, it is only necessary to produce the same type of source electrode on-chip film, and the master-slave relationship is distinguished through the control module. Therefore, there is no need to distinguish between the first source electrode on-chip film 300 and the second source electrode cover during assembly. The first source electrode chip-on-chip film 400 speeds up the assembly speed and assembly efficiency to a certain extent. At the same time, the first source electrode chip-on-chip film 300 and the second source electrode chip-on-chip film 400 are exactly the same. Moreover, during use, when the first timing control chip 310 or the second timing control chip 410 set as the master timing control chip has an unsolvable problem, the control module can be used to set the slave timing control chip to the first timing control chip 310 or the second timing control chip 410. The first timing control chip 310 or the second timing control chip 410 is set as the main timing control chip to continue to complete the analysis work, which extends the service life of the display device 500 to a certain extent.

Figure 3 is a schematic structural diagram of a source electrode on-chip film according to the third embodiment of the present application. As shown in Figure 3, as the third embodiment of the present application, a source electrode on-chip film is disclosed for connecting The printed circuit board 200 and the display panel 100 are applied to the display device 500 shown in the first embodiment. The source electrode chip-on-chip film includes a source driver chip and a timing control chip. The timing control chip is integrated in the source electrode. In the pole driver chip, the timing control chip includes an input port 311, a first group of output ports 312 and a second group of output ports 313. The input port 311 receives the signal to be analyzed, analyzes, generates and outputs the first analysis signal and Second analysis signal, the first group of output ports 312 outputs the first analysis signal to the source driver chip, and the second group of output ports 313 outputs the second analysis signal to the printed circuit board 200 .

When the source chip-on-chip film of the present application is used in the display device of the present application, it can realize a resolution display based on the Tconless architecture; of course, the chip-on-chip film of the present application can also be used in a low-resolution display device. In this case, The second set of output ports can be floating, so that the chip-on-chip film of the present application has a wider application range.

Figure 4 is a flow chart of a driving method according to the fourth embodiment of the present application. As shown in Figure 4, as the fourth embodiment of the present application, a driving method is disclosed, which is applied as described in the first embodiment. The display device includes steps:

S100: The first timing control chip receives the signal to be analyzed and analyzes it to generate a first analysis signal and a second analysis signal. The first analysis signal is output to the first source driver chip, and the second analysis signal is output to the second source driver chip; as well as

S200: The first source driver chip receives the first analysis signal, and after the second source driver chip receives the second analysis signal, the first source driver chip and the second source driver chip use the first analysis signal and the second analysis signal. The signal simultaneously drives the display panel for display.

It should be noted that the restrictions on each step involved in this plan are not considered to limit the order of the steps as long as they do not affect the implementation of the specific plan. The steps written in front can be executed first. It can also be executed later, or even simultaneously. As long as this solution can be implemented, it should be regarded as belonging to the protection scope of this application.

The technical solution of this application can be widely used in NB display devices, and of course can also be used in various display panels, such as TN (Twisted Nematic, twisted nematic) display panels, IPS (In-Plane Switching, plane switching) display panels, VA (Vertical Alignment, vertical alignment type) display panel, MVA (Multi-Domain Vertical Alignment, multi-quadrant vertical alignment type) display panel, of course, it can also be other types of display panels, such as OLED (Organic Light-Emitting Diode, organic light-emitting Diode) display panel, the above solution can be applied.

It should be noted that the application concept of this application can be formed into many embodiments, but the length of the application document is limited and cannot be listed one by one. Therefore, on the premise that there is no conflict, there are no differences between or among the above-described embodiments. Technical features can be arbitrarily combined to form new embodiments, and the combination of each embodiment or technical feature will enhance the original technical effect.

The above content is a further detailed description of the present application in combination with specific optional implementation modes, and it cannot be concluded that the specific implementation of the present application is limited to these descriptions. For those of ordinary skill in the technical field to which this application belongs, several simple deductions or substitutions can be made without departing from the concept of this application, which should be regarded as falling within the protection scope of this application.

Claims

A display device includes a display panel and a printed circuit board. The printed circuit board is connected to the display panel. The display device further includes a first source electrode chip-on-chip film and a second source electrode chip-on-chip film. The first source chip-on-chip film and the second source chip-on-chip film are both connected to the printed circuit board and the display panel;

The first source electrode on-chip film includes a first source driver chip and a first timing control chip, the second source electrode on-chip film includes a second source driver chip, and the first timing control chip is respectively connected with the The first source driver chip and the second source driver chip are electrically connected;

Wherein, the first timing control chip receives the signal to be analyzed output by the printed circuit board, analyzes to generate and output the first analysis signal and the second analysis signal; the first source driver chip receives the first analysis signal , the second source driver chip receives the second analysis signal, and the first source driver chip and the second source driver chip drive simultaneously according to the first analysis signal and the second analysis signal. The display panel.
The display device according to claim 1, wherein the signal to be analyzed is an EDP signal, the first analysis signal is a first point-to-point signal, and the second analysis signal is a second point-to-point signal;

The first timing control chip includes an input port, a first group of output ports and a second group of output ports. The input port is used to receive the EDP signal. The first timing control chip passes through the first group of output ports. The first point-to-point signal is output to the first source driver chip, and the first timing control chip outputs the second point-to-point signal to the second source driver chip through the second set of output ports.
The display device according to claim 2, wherein a high-speed signal line connecting the first source chip-on-chip film and the second source chip-on-chip film is provided on the printed circuit board, and the first timing sequence The control chip outputs the second analysis signal to the second source driver chip through the high-speed signal line.
The display device according to claim 1, wherein the second source electrode on-chip film further includes a second timing control chip, the second timing control chip is used to receive the second analysis signal and convert the The second analysis signal is output to the second source driver chip, and the first source chip-on-chip film and the second source chip-on-chip film have the same specifications.
The display device according to claim 4, wherein the display device further includes a control module, the control module is used to control the master-slave relationship of the first timing control chip and the second timing control chip;

When the first timing control chip or the second timing control chip is set as the main timing control chip, the signal to be analyzed is received and analyzed to generate a first analysis signal and a second analysis signal; the first timing control chip or When the second timing control chip is set as the slave timing control chip, it receives the second analysis signal and outputs it.
The display device according to claim 1, wherein the display device further includes a synchronization module, the synchronization module connects the first source driver chip and the second source driver chip, so that the first source driver chip The driving chip and the second source driving chip drive the display panel at the same time.
The display device according to claim 1, wherein the display device further includes a compensation module, the compensation module is used to connect the first source driver chip and the second source driver chip, and is used to compensate the third source driver chip. An analysis signal and the second analysis signal, so that the signal strengths of the first analysis signal and the second analysis signal are consistent.
The display device according to claim 1, wherein the display device further includes a compensation module connected to the first source driver chip and used to compensate the first analysis signal so that the The signal strengths of the first analytical signal and the second analytical signal are consistent.
The display device according to claim 1, wherein the display device further includes a compensation module connected to the second source driver chip and used to compensate the second analysis signal so that the The signal strengths of the first analytical signal and the second analytical signal are consistent.
The display device according to claim 1, wherein the first timing control chip is integrated into the first source driver chip as a functional module and is uniformly packaged on the first source chip-on-chip film.
The display device according to claim 1, wherein the first timing control chip and the first source driver chip are respectively packaged and respectively disposed on the first source electrode cover film.
The display device of claim 1, wherein there are multiple second source driver chips and multiple second analysis signals, and the number of the second analysis signals is the same as the number of the second analysis signals. The number of source driver chips is the same.
The display device according to claim 2, wherein the first analysis signal and the second analysis signal have exactly the same specifications.
The display device according to claim 2, wherein a bent signal transmission line is provided at the first group of output ports of the first source driver chip, so that the first source driver chip outputs a signal to the display panel. The time is the same as the time when the second source driver chip outputs a signal to the display panel.
The display device according to claim 1, wherein the second source electrode on-chip film is provided with only a second source driver chip, and the first timing control chip of the first source on-chip film outputs a first analysis signal. and a second analysis signal, the first analysis signal is output to the first source driver chip, and the second analysis signal is output to the second source driver chip.
A source electrode on-chip film is used to connect a printed circuit board and a display panel, and is used in a display device, which includes a source driver chip and a timing control chip, and the timing control chip is integrated in the source driver chip, The timing control chip includes an input port, a first group of output ports and a second group of output ports. The input port receives the signal to be analyzed, analyzes, generates and outputs a first analysis signal and a second analysis signal. The first analysis signal A set of output ports outputs the first analysis signal to the source driver chip, and the second set of output ports outputs the second analysis signal to the printed circuit board;

The display device includes a display panel and a printed circuit board, and the printed circuit board is connected to the display panel, wherein the source-level chip-on-chip film includes a first source chip-on-chip film and a second source chip-on-chip film, The first source chip-on-chip film and the second source chip-on-chip film are both connected to the printed circuit board and the display panel;

The first source electrode on-chip film includes a first source driver chip and a first timing control chip, the second source electrode on-chip film includes a second source driver chip, and the first timing control chip is respectively connected with the The first source driver chip and the second source driver chip are electrically connected;

Wherein, the first timing control chip receives the signal to be analyzed output by the printed circuit board, analyzes to generate and output the first analysis signal and the second analysis signal; the first source driver chip receives the first analysis signal , the second source driver chip receives the second analysis signal, and the first source driver chip and the second source driver chip drive simultaneously according to the first analysis signal and the second analysis signal. The display panel.
A driving method, applied to a display device, including the steps:

The first timing control chip receives the signal to be analyzed and analyzes it to generate a first analysis signal and a second analysis signal; and

After the first source driver chip receives the first analysis signal, and the second source driver chip receives the second analysis signal, the first source driver chip and the second source driver chip drive simultaneously according to the first analysis signal and the second analysis signal. display panel;

Wherein, the display device includes a display panel and a printed circuit board, the printed circuit board is connected to the display panel, the display device further includes a first source electrode chip-on-chip film and a second source electrode chip-on-chip film, The first source electrode chip-on-chip film and the second source electrode chip-on-chip film are both connected to the printed circuit board and the display panel;

The first source electrode on-chip film includes a first source driver chip and a first timing control chip, the second source electrode on-chip film includes a second source driver chip, and the first timing control chip is respectively connected with the The first source driver chip and the second source driver chip are electrically connected;

Wherein, the first timing control chip receives the signal to be analyzed output by the printed circuit board, analyzes to generate and output the first analysis signal and the second analysis signal; the first source driver chip receives the first analysis signal , the second source driver chip receives the second analysis signal, and the first source driver chip and the second source driver chip drive simultaneously according to the first analysis signal and the second analysis signal. The display panel.
The driving method according to claim 17, wherein the signal to be analyzed is an EDP signal, the first analysis signal is a first point-to-point signal, and the second analysis signal is a second point-to-point signal;

The first timing control chip includes an input port, a first group of output ports and a second group of output ports. The input port is used to receive the EDP signal. The first timing control chip passes through the first group of output ports. Output the first point-to-point signal to the first source driver chip, and the first timing control chip outputs the second point-to-point signal to the second source driver chip through the second set of output ports.
The driving method according to claim 18, wherein a high-speed signal line connecting the first source chip-on-chip film and the second source chip-on-chip film is provided on the printed circuit board, and the first timing sequence The control chip outputs the second analysis signal to the second source driver chip through the high-speed signal line.
The driving method according to claim 17, wherein the second source electrode on-chip film further includes a second timing control chip, the second timing control chip is used to receive the second analysis signal and convert the The second analysis signal is output to the second source driver chip, and the first source chip-on-chip film and the second source chip-on-chip film have the same specifications;

Wherein, the display device further includes a control module, the control module is used to control the master-slave relationship between the first timing control chip and the second timing control chip;

When the first timing control chip or the second timing control chip is set as the main timing control chip, the signal to be analyzed is received and analyzed to generate a first analysis signal and a second analysis signal; the first timing control chip or When the second timing control chip is set as the slave timing control chip, it receives the second analysis signal and outputs it.