WO2024000761A1 - 混合型探针卡的制作方法及探针卡 - Google Patents

混合型探针卡的制作方法及探针卡 Download PDF

Info

Publication number
WO2024000761A1
WO2024000761A1 PCT/CN2022/113296 CN2022113296W WO2024000761A1 WO 2024000761 A1 WO2024000761 A1 WO 2024000761A1 CN 2022113296 W CN2022113296 W CN 2022113296W WO 2024000761 A1 WO2024000761 A1 WO 2024000761A1
Authority
WO
WIPO (PCT)
Prior art keywords
probe
signal
power
probe card
hybrid
Prior art date
Application number
PCT/CN2022/113296
Other languages
English (en)
French (fr)
Inventor
梁建
罗雄科
Original Assignee
上海泽丰半导体科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海泽丰半导体科技有限公司 filed Critical 上海泽丰半导体科技有限公司
Publication of WO2024000761A1 publication Critical patent/WO2024000761A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07357—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with flexible bodies, e.g. buckling beams
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor

Definitions

  • the present application relates to the field of semiconductor testing technology, and specifically to a method for making a hybrid probe card and a probe card.
  • Probe cards are used during the testing process.
  • the probe cards complete the electrical connection of the wafer pads or bumps to the testing machine, and then pass the test
  • the machine completes the performance measurement of wafer chips, completes the screening and classification of wafers, and eliminates chips that do not meet the design requirements.
  • the size of the probe used in the probe card is usually only a few tens of microns ( ⁇ m).
  • the current minimum effective diameter is 30 ⁇ m
  • the size of the pads or bumps on the wafer also ranges from tens to hundreds of microns. etc. At present, the minimum equivalent size is basically 45 ⁇ m.
  • the test system requires high stability and high alignment accuracy.
  • Probe cards on the market generally only use one type of probe, which is the default approach in probe card design; however, due to the increasingly complex chip functions, the chip will contain multiple signals and multiple power supplies at the same time. Signal and power supply have different performance requirements for probes. Therefore, it is necessary to develop suitable probes for different signal types and use multiple probes on the same probe card. Although this will introduce some costs in the production of the probe card, But this can indeed ensure that the performance of various signals and power supplies of the chip reaches optimal status.
  • embodiments of this specification provide a method for making a hybrid probe card and a probe card to solve the problem that existing probe cards cannot simultaneously meet the probe requirements of multiple signals and multiple power sources in the chip. technical problem.
  • the embodiment of this specification provides a method for making a hybrid probe card, which includes:
  • Step 1 According to the signal of at least one signal area on the chip, optimize the probe size of the probe card to obtain at least one initial probe, where each signal area corresponds to one initial probe;
  • Step 2 According to the elasticity and life of each initial probe and the preset standards, optimize at least one initial probe to obtain at least one optimized probe;
  • Step 3 Assemble at least one optimized probe in the probe card based on at least one optimized probe and the corresponding signal region.
  • the signal area includes a digital signal area and a power signal area
  • the manufacturing method of the hybrid probe includes:
  • Step 01 According to the digital signal in the digital signal area of the chip and the power signal in the power signal area, optimize the probe size of the probe card to obtain the first signal probe and the first power probe;
  • Step 02 According to the elasticity and life of the first signal probe and the first power probe, and the preset standards, optimize the first signal probe and the first power probe to obtain the second signal probe and the second power probe;
  • Step 03 According to the distribution positions of the digital signals and power signals in the chip, assemble the second signal probe and the second power probe in the probe card.
  • step 01 includes:
  • Step 101 Use simulation software to simulate the digital signal and power signal to obtain the probe simulation results
  • Step 102 Optimize the probe size of the probe card according to the simulation results to obtain the first signal probe and the first power probe.
  • the probe simulation results include: spacing simulation results, electrical simulation results and elastic simulation results.
  • Step 101 includes:
  • Step 1011 Use simulation software to simulate the pad spacing of the digital signal and the pad spacing of the power signal, and obtain the spacing simulation results of the digital signal and the power signal;
  • Step 1012 Perform electrical simulation on the probe in the probe card according to the performance requirements of the digital signal and power signal, and obtain the electrical simulation results of the digital signal and power signal;
  • Step 1013 Perform elastic force simulation on the probe card according to the elastic force requirements of the digital signal and power signal on the probe in the probe card, and obtain the elastic force simulation results of the digital signal and power signal.
  • step 102 includes:
  • Step 1021 Determine the lateral displacement of the probe in the probe card according to the spacing simulation result, and obtain the first size of the probe;
  • Step 1022 According to the electrical simulation results, optimize the first size to obtain the second size
  • Step 1023 According to the elastic force simulation results, optimize the second size to obtain the first signal probe and the first power probe.
  • step 02 includes:
  • Step 201 Test the elasticity and life of the first signal probe and the first power probe, and obtain the first test result of the first signal probe and the second test result of the first power probe;
  • Step 202 Optimize the first signal probe and the first power probe according to the first test result, the second test result and the preset standard to obtain the second signal probe and the second power probe.
  • step 201 includes:
  • Step 2011 Determine whether the first test result and the second test result are consistent with the preset standard
  • Step 2012 If yes, determine the first signal probe and the first power probe, which are the second signal probe and the second power probe respectively;
  • Step 2013 If not, perform optimization processing on the first signal probe and the first power probe to obtain a second signal probe and a second power probe.
  • it also includes:
  • Step 4 According to the chip testing requirements, adjust the structure of the probe head to obtain a hybrid probe card.
  • step 4 includes:
  • Step 401 Set the tip of the probe head to the high-frequency probe tip to obtain a hybrid probe card.
  • Embodiments of this specification also provide a probe card, which is manufactured using the above-mentioned hybrid probe card manufacturing method, including: a printed circuit board, a back support and at least one probe;
  • the back support is disposed on the printed circuit board and at least one probe is disposed on the printed circuit board.
  • the beneficial effects achieved by at least one of the above technical solutions adopted in the embodiments of this specification at least include: meeting the performance requirements for signals in different signal areas such as loss, improving probe card performance, and enhancing testing capabilities; meeting Different power supplies have requirements for current endurance and other performance, improve the performance of probe cards, and enhance testing capabilities; meet the ultra-high frequency requirements of high-frequency transformed radio frequency signals, improve probe card performance, and enhance testing capabilities.
  • Figure 1 is a schematic structural diagram of a wafer testing system in this application.
  • Figure 2 is a schematic diagram of a signal pad arrangement in this application.
  • FIG. 3 is a schematic diagram of a power supply pad arrangement in this application.
  • Figure 4 is a simulation diagram of a pad spacing in this application.
  • Figure 5 is a schematic diagram of the return loss curve of a signal simulation in this application.
  • Figure 6 is a schematic diagram of the insertion loss curve of a signal simulation in this application.
  • Figure 7 is a schematic diagram of the time domain impedance curve of a signal simulation in this application.
  • Figure 8 is a schematic diagram of the mechanical simulation of a probe in this application.
  • Figure 9 is a schematic curve diagram of a mechanical simulation in this application.
  • Figure 10 is a schematic diagram of the elastic force and overload curves of the first signal probe and the first power probe in this application;
  • Figure 11 is a schematic diagram of the elastic force and current curves of the first signal probe and the first power probe in this application;
  • Figure 12 is a schematic diagram of the arrangement of signal probes in this application.
  • FIG. 13 is a schematic diagram of the power probe arrangement in this application.
  • Figure 14 is a schematic structural diagram of the high-frequency test probe in this application.
  • Figure 15 is a schematic structural diagram of the probe card in this application.
  • the wafer testing system includes: a testing machine, a probe card, a probe station, a wafer carrying station, and a wafer.
  • the probe card includes: a printed circuit board, an organic substrate, and a probe.
  • the embodiment of this specification proposes a solution: consider the different performance requirements of different signals and power supplies, develop targeted probes for different signals and different power supplies, and apply multiple types of probes at the same time. On one probe card, it ensures the performance of important signals and power at the same time, so that the performance of the probe card can be optimized.
  • the pad arrangement in the signal and power areas is obviously different. Measurements show that the pad spacing in the signal area is about 130 ⁇ m, while the pad spacing in the power area is about 200 ⁇ m. Due to the large number of digital signals in this project, the speed requirements are also very high, reaching 30 gigabits per second (Gbps). At the same time, due to the large number of signals, the overall power consumption of the chip is also very large, with the total current exceeding 100A.
  • the embodiment of this specification provides a method for making a hybrid probe card, which includes:
  • Step 1 According to the signal of at least one signal area on the chip, optimize the probe size of the probe card to obtain at least one initial probe, where each signal area corresponds to one initial probe.
  • the chip will contain multiple signal areas at the same time. Different signal areas have different requirements for probes. Therefore, in this application, the signals of different signal areas are simulated, and the size of the probe is optimized based on the simulation results. , corresponding to each signal region, the corresponding initial probe is obtained, and at least one initial probe is obtained.
  • Step 2 According to the elasticity and life of each initial probe and the preset standards, optimize at least one initial probe to obtain at least one optimized probe.
  • the elasticity and lifespan of the initial probe may not be suitable for the corresponding signal area, which may result in the need to measure loss and The impedance does not meet the requirements. Therefore, the elasticity and life of the initial probe need to be tested according to preset standards, and at least one initial probe is optimized based on the test results to obtain at least one optimized probe.
  • Step 3 Assemble at least one optimized probe in the probe card based on at least one optimized probe and the corresponding signal region.
  • At least one optimized probe is assembled in a probe card based on at least one optimized probe and the corresponding signal area to obtain a hybrid probe card, which can meet the wafer testing requirements of the chip. .
  • the following takes the signal area including the digital signal area and the power signal area as an example for detailed explanation.
  • Step 01 According to the digital signal in the digital signal area of the chip and the power signal in the power signal area, optimize the probe size of the probe card to obtain the first signal probe and the first power probe.
  • simulation is performed based on the digital signal area and power signal area of the chip, and the probe size is optimized based on the simulation results.
  • the probe for the digital signal area needs to meet the requirements of the digital signal area to obtain the first signal probe.
  • For the power signal The probes in the area need to meet the requirements of the power signal area to obtain the first power probe.
  • step 01 includes: Step 101: Use simulation software to simulate digital signals and power signals to obtain probe simulation results; Step 102: Optimize the probe size of the probe card based on the simulation results to obtain the first signal probe and first power probe.
  • the probe simulation results include: spacing simulation results, electrical simulation results and elastic force simulation results.
  • Step 101 includes: Step 1011: Use simulation software to calculate the pad spacing of the digital signal and the pad spacing of the power signal. Simulate to obtain the spacing simulation results of the digital signal and the power signal;
  • Step 1012 Perform electrical simulation on the probe in the probe card according to the performance requirements of the digital signal and the power signal, and obtain the electrical simulation results of the digital signal and the power signal;
  • Step 1013 Carry out elastic force simulation on the probe card based on the elastic force requirements of the digital signal and power signal on the probe in the probe card, and obtain the elastic force simulation results of the digital signal and power signal.
  • step 102 includes: step 1021: determine the lateral displacement of the probe in the probe card according to the spacing simulation result, and obtain the first size of the probe; step 1022: optimize the first size according to the electrical simulation result Process to obtain the second size; Step 1023: According to the elastic simulation results, optimize the second size to obtain the first signal probe and the first power probe.
  • the main consideration in the design of the first size of the probe is that the maximum probe size supported by different pad spacing (pitch) is different. If the probe size is too large, it will easily cause short circuit problems in adjacent probes. This can be done through simulation. Determine the lateral displacement of the probe to ensure that the probe will not cause short circuit problems. As shown in Figure 4, the probe is simulated. The black solid square in the figure represents the probe guide plate, and the black curve represents the probe. Among them, 2 represents the fixed end of the probe, that is, the end of the probe close to the organic substrate. Point 1 refers to the maximum lateral displacement of the probe obtained by simulation, and A refers to the lateral displacement of the probe obtained from the point. Based on the lateral displacement, the first size of the probe is determined.
  • the electrical simulation of the probe models the probe part based on the pad arrangement on the wafer, distinguishes the signal pin and the ground pin according to the signal type of the wafer, and then uses three-dimensional electromagnetic field simulation software to calculate the probe's High speed performance.
  • the main basis for judging high-speed performance is the return loss and insertion loss of the signal, as well as the time domain impedance. For high speed, it is generally required that the return loss consumption is small, the insertion loss consumption is large, and the impedance fluctuation is as small as possible.
  • the solid line represents the data with a Pitch of 110 ⁇ m
  • the dotted line represents the data with a Pitch of 150 ⁇ m
  • the double short dotted line represents the data with a Pitch of 130 ⁇ m
  • the long dotted line represents the data with a Pitch of 170 ⁇ m.
  • the abscissa in Figure 5 is frequency (freq), unit GHz, ordinate is return loss, unitless, among which, dB(S(55,55)), dB(S(53,53)), dB(S(51,51)) and dB(S(49,49)) respectively represent the return loss data with pitches of 110 ⁇ m, 130 ⁇ m, 150 ⁇ m and 170 ⁇ m.
  • the abscissa in Figure 6 is frequency, unit GHz, and the ordinate is insertion loss, unitless, where, dB(S(56,55)), dB(S(54,53)), dB(S(52,51)), dB(S(50,49)) respectively represent Pitch of 110 ⁇ m, 130 ⁇ m, 150 ⁇ m and 170 ⁇ m Insertion loss data.
  • the abscissa in Figure 7 is time in picoseconds (psec), and the ordinate is time domain impedance in ohms. Sim_OHMS38, Sim_OHMS37, Sim_OHMS36 and Sim_OHMS35 respectively represent Pitch of 110 ⁇ m and 130 ⁇ m. , 150 ⁇ m and 170 ⁇ m impedance data.
  • m16 in Figure 5 represents the frequency and return loss of each curve read here.
  • m14 in Figure 6 represents the frequency and insertion loss of each curve read here.
  • m15 in Figure 7 represents the time and time domain impedance of each curve read here.
  • the solid line represents the data with a pitch of 110 ⁇ m
  • the dotted line represents the data with a pitch of 150 ⁇ m
  • the double short dotted line represents the data with a pitch of 130um
  • the long dotted line represents the data with a pitch of 170um.
  • the power supply part is calculated according to the calculation formula of the flow capacity to evaluate the optimal size of the probe.
  • Table 1 shows the flow capacity in the embodiment of the present application.
  • Table 1 shows the flow capacity of the probe as 1.10A
  • the effective length of the obtained probe is 3.5mil
  • the effective width of the probe is 1.5mil
  • the temperature rise is 80 degrees Celsius.
  • the flow capacity is calculated by formula (1), where I represents the current, K is 0.048, A represents the flow cross-sectional area, and ⁇ T represents the degree of temperature rise.
  • the optimized second size of the probe is used to simulate whether the elasticity of the probe is too large or too small. If the elasticity of the probe is too large or too small, it needs to be based on The probe material parameter table selects the appropriate probe material so that the elasticity of the probe meets the requirements.
  • the elastic force of the probe will affect the damage to the wafer pad.
  • the elastic force of the probe cannot exceed 2.5g. If it exceeds, the wafer solder will be penetrated. disk risk. If it is found that the elasticity of the probe has exceeded the limit value, it is necessary to improve the material of the probe and choose a material with a smaller elastic modulus. The larger the elastic modulus, the greater the elasticity of the probe.
  • Figure 8 shows the mechanical simulation of the elasticity of the probe.
  • the curve represents the probe, the black solid square represents the organic substrate, and the abscissa in Figure 9 is Over Driver (OD), the unit is ⁇ m, the ordinate is force (Force), the unit is gram force (gf), through optimization, the signal probe size is 30x50 ⁇ m, and the power probe size is 30x65 ⁇ m.
  • Step 02 According to the elasticity and life of the first signal probe and the first power probe, and the preset standards, optimize the first signal probe and the first power probe to obtain the second signal probe and the second Power probe.
  • the preset standard may be that the elastic forces of the first signal probe and the first power probe tend to be consistent.
  • step 02 includes: step 201: test the elasticity and life of the first signal probe and the first power probe, and obtain the first test result of the first signal probe and the first test result of the first power probe. Two test results; Step 202: Optimize the first signal probe and the first power probe according to the first test result, the second test result and the preset standard to obtain the second signal probe and the second power probe. .
  • step 201 includes: step 2011: determine whether the first test result and the second test result are consistent with the preset standard; step 2012: if so, determine whether the first signal probe and the first power probe are respectively the first and second test results. Two signal probes and a second power probe; Step 2013: If not, optimize the first signal probe and the first power probe to obtain a second signal probe and a second power probe.
  • the elasticity and life span of the first signal probe and the first power probe meet the requirements. If they do not meet the requirements, they need to be optimized and adjusted to obtain the second signal probe and the second power probe.
  • the test data of the first signal probe and the first power probe As shown in Figure 10, it is the test data of the first signal probe and the first power probe.
  • the probe size of the first signal probe is 30x50 ⁇ m, and the probe size of the first power probe is 30x65 ⁇ m.
  • the point designated by 3 represents the data of the first signal probe, and the point designated by 4 represents the data of the first power probe.
  • the abscissa in Figure 10 is overload, in microns, and the ordinate is elastic force (Force), in grams (g).
  • the elastic force of the first signal probe and the first power probe is almost Consistency ensures that the probe marks on the wafer are consistent and do not cause differences due to the use of different probes.
  • FIG 11 it is the test data of the first signal probe and the first power probe.
  • the abscissa is the current (Current) in milliamperes (mA)
  • the ordinate is the elastic force (Force) in grams ( g)
  • the point designated by 5 in Figure 11 represents the data of the first power probe
  • the point designated by 6 represents the data of the first signal probe.
  • the first signal probe and The flow capacity of the first power supply probe is inconsistent, and the flow capacity of the power supply probe is better.
  • Step 03 According to the distribution positions of the digital signals and power signals in the chip, assemble the second signal probe and the second power probe in the probe card.
  • the method of making a hybrid probe card also includes: step 4: adjusting the structure of the probe head of the probe according to the test requirements of the chip to obtain a hybrid probe card.
  • the structure of the probe head needs to be adjusted and a dedicated high-frequency test probe can be added.
  • the high-frequency test probe can support more than 50 ⁇ m. Pitch, the supported signal frequency can be as high as 300GHz or more, and high-frequency test probes are generally customized from suppliers.
  • Step 4 includes: Step 401: Set the tip of the probe head to a high-frequency probe tip to obtain a hybrid probe card.
  • FIG 14 it is a simplified structural diagram of a high-frequency test probe, including: the high-frequency probe tip and interface, and the interface is generally connected with a cable.
  • the high-frequency test probe tip and interface There can be many high-frequency test probes arranged side by side, and the arrangement can be of various types, such as GSSGSSGSG, etc.
  • G represents the reference ground and S represents the signal.
  • the external interface is generally SMA series, for example, K head, V head, etc., which can be directly connected to the cable, and the cable can be connected to the instrument.
  • the main parameters of a certain 110G high-frequency probe are: insertion loss (Insertion loss) is -2.0 decibels (dB), return loss (Return loss) is -10dB, and frequency range (frequency range) is 75 to 110GHz.
  • the main parameters of a high-frequency probe with adjustable pitch and 40GHz bandwidth are: insertion loss (Insertion loss) is -1.0 decibel (dB), return loss (Return loss) is -15dB, and frequency range (frequency range) is Direct current (DC) to 110GHz.
  • Embodiments of this specification also provide a probe card, which is manufactured using the above-mentioned hybrid probe card manufacturing method, including: a printed circuit board, a back support member and at least one probe, and the back support member is disposed on the printed circuit board. , at least one probe is disposed on the printed circuit board.
  • it also includes: a displacement platform; the displacement platform is arranged on the printed circuit, the probe card is fixed on the displacement platform, and the displacement platform moves at least one probe in the probe card to the working position through displacement movement.
  • the probe card includes: a printed circuit board, a back support member, a signal probe and a power probe; the back support member is arranged on the printed circuit board, and the signal probe and the power probe are arranged on the printed circuit board.
  • it also includes: a displacement platform; the displacement platform is arranged on the printed circuit, the probe card is fixed on the displacement platform, and the displacement platform moves the signal probe and the power probe in the probe card to the working position through displacement movement.
  • Figure 15 it includes: a displacement platform, an instrument, a back support, a printed circuit board, a signal probe and a power probe. It can also include a high-frequency test probe, which is connected to the probe through a cable. Instrument connections. Holes need to be opened on the printed circuit board to place the probe and displacement platform. The probe is fixed on the displacement platform. An adapter board may be needed. The displacement platform supports small displacement movements and supports moving the probe to the appropriate position. The signal probe The number of probes and power probes needs to be determined based on the actual situation. The number of openings will also be different, and the number of displacement platforms will also change accordingly.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measuring Leads Or Probes (AREA)

Abstract

一种混合型探针卡的制作方法及探针卡，应用于半导体测试技术领域，包括：根据芯片上至少一个信号区域的信号，对探针卡的探针尺寸进行优化处理，得到至少一种初始探针，其中，每一个信号区域对应一种初始探针；根据每一种初始探针的弹力和寿命以及预设标准，对至少一种初始探针进行优化处理，得到至少一种优化探针；根据至少一种优化探针以及对应的信号区域，将至少一种优化探针在探针卡中进行组装。与现有技术相比，混合型探针卡的制作方法满足不同信号区域对损耗和耐流等性能的要求，改善探针卡性能，提升测试能力；满足高频变换的射频信号对超高频的要求，改善探针卡性能，提升测试能力。

Description

混合型探针卡的制作方法及探针卡 技术领域
本申请涉及半导体测试技术领域，具体涉及一种混合型探针卡的制作方法及探针卡。
背景技术
在半导体晶圆测试阶段，需要对晶圆上的未封装芯片进行测试，测试过程中会用到探针卡，探针卡完成晶圆焊盘或凸点到测试机的电气连接，然后通过测试机完成晶圆芯片的性能量测，并完成对晶圆的筛选分类，剔除不符合设计要求的芯片。探针卡所用的探针尺寸，即横截面，通常只有几十微米(μm)，例如当前最小有效直径在30μm，晶圆上的焊盘或凸点尺寸也在几十微米至几百微米不等,目前最小等效尺寸基本在45μm，这么小尺寸的探针要完成晶圆和测试的电气连接，就要求测试系统具有很高的稳定性和很高的对位精度。
市面上的探针卡一般只会采用一种探针，这种做法是一种探针卡设计上的默认做法；但由于芯片功能日益复杂，芯片会同时包含多种信号和多种电源，这些信号和电源对于探针的性能要求也千差万别，因此需要对于不同的信号类型研发合适的探针，在同一张探针卡上采用多种探针，这样虽然在针卡制作上会引入一些成本，但这样确实可以保证芯片的各种信号和电源的性能都达到最优状态。
因此，需要一种新的针对有特殊要求的信号和电源设计对应的探针的技术方案。
发明内容
有鉴于此，本说明书实施例提供一种混合型探针卡的制作方法及探针卡，以解决现有的探针卡无法同时满足芯片中多种信号和多种电源对于探针的要 求的技术问题。
本说明书实施例提供以下技术方案：
本说明书实施例提供一种混合型探针卡的制作方法，包括：
步骤1：根据芯片上至少一个信号区域的信号，对探针卡的探针尺寸进行优化处理，得到至少一种初始探针，其中，每一个信号区域对应一种初始探针；
步骤2：根据每一种初始探针的弹力和寿命以及预设标准，对至少一种初始探针进行优化处理，得到至少一种优化探针；
步骤3：根据至少一种优化探针以及对应的信号区域，将至少一种优化探针在探针卡中进行组装。
优选地，信号区域包括数字信号区域和电源信号区域，混合型探针的制作方法包括：
步骤01：根据芯片的数字信号区域中的数字信号和电源信号区域中的电源信号，对探针卡的探针尺寸进行优化处理，得到第一信号探针和第一电源探针；
步骤02：根据第一信号探针和第一电源探针的弹力和寿命，以及预设标准，对第一信号探针和第一电源探针进行优化处理，得到第二信号探针和第二电源探针；
步骤03：根据芯片中的数字信号和电源信号的分布位置，将第二信号探针和第二电源探针在探针卡中进行组装。
优选地，步骤01，包括：
步骤101：利用仿真软件对数字信号和电源信号进行仿真，得到探针仿真结果；
步骤102：根据仿真结果对探针卡的探针尺寸进行优化处理，得到第一信号探针和第一电源探针。
优选地，探针仿真结果包括：间距仿真结果、电仿真结果和弹力仿真结 果，步骤101，包括：
步骤1011：通过仿真软件对数字信号的焊盘间距和电源信号的焊盘间距进行仿真，得到数字信号和电源信号的间距仿真结果；
步骤1012：根据数字信号和电源信号的性能要求对探针卡中的探针进行电仿真，得到数字信号和电源信号的电仿真结果；
步骤1013：根据数字信号和电源信号对探针卡中的探针的弹力要求对探针卡进行弹力仿真，得到数字信号和电源信号的弹力仿真结果。
优选地，步骤102，包括：
步骤1021：根据间距仿真结果，确定探针卡中的探针的横向位移，得到探针的第一尺寸；
步骤1022：根据电仿真结果，对第一尺寸进行优化处理，得到第二尺寸；
步骤1023：根据弹力仿真结果，对第二尺寸进行优化处理，得到第一信号探针和第一电源探针。
优选地，步骤02，包括：
步骤201：对第一信号探针和第一电源探针的弹力和寿命进行测试，得到第一信号探针的第一测试结果，以及第一电源探针的第二测试结果；
步骤202：根据第一测试结果、第二测试结果以及预设标准，对第一信号探针和第一电源探针进行优化处理，得到第二信号探针和第二电源探针。
优选地，步骤201，包括：
步骤2011：判断第一测试结果和第二测试结果与预设标准是否一致；
步骤2012：若是，则确定第一信号探针和第一电源探针，分别为第二信号探针和第二电源探针；
步骤2013：若否，则对第一信号探针和第一电源探针进行优化处理，得到第二信号探针和第二电源探针。
优选地，还包括：
步骤4：根据芯片的测试需求，对探针的探针头的结构进行调整，得到 混合型探针卡。
优选地，步骤4，包括：
步骤401：将探针头的针尖设置为高频探针针尖，得到混合型探针卡。
本说明书实施例还提供一种探针卡，使用上述的混合型探针卡的制作方法制作，包括：印刷电路板、背部支撑件和至少一种探针；
背部支撑件设置在印刷电路板上，至少一种探针设置在印刷电路板上。
与现有技术相比，本说明书实施例采用的上述至少一个技术方案能够达到的有益效果至少包括：满足不同信号区域的信号对损耗等性能的要求，改善探针卡性能，提升测试能力；满足不同电源对耐流等性能的要求，改善探针卡性能，提升测试能力；满足高频变换的射频信号对超高频的要求，改善探针卡性能，提升测试能力。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本申请中的一种晶圆测试系统的结构示意图；
图2是本申请中的一种信号焊盘排布的示意图；
图3是本申请中的一种电源焊盘排布的示意图；
图4是本申请中的一种焊盘间距的仿真示意图；
图5是本申请中的一种信号仿真的回波损耗的曲线示意图；
图6是本申请中的一种信号仿真的插入损耗的曲线示意图；
图7是本申请中的一种信号仿真的时域阻抗的曲线示意图；
图8是本申请中的一种探针的力学仿真的示意图；
图9是本申请中的一种力学仿真的曲线示意图；
图10是本申请中的第一信号探针和第一电源探针的弹力和过载的曲线 示意图；
图11是本申请中的第一信号探针和第一电源探针的弹力和电流的曲线示意图；
图12是本申请中的信号探针排布的示意图；
图13是本申请中的电源探针排布的示意图；
图14是本申请中的高频测试探针的结构示意图；
图15是本申请中的探针卡的结构示意图。
具体实施方式
下面结合附图对本申请实施例进行详细描述。
以下通过特定的具体实例说明本申请的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本申请的其他优点与功效。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。本申请还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本申请的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
要说明的是，下文描述在所附权利要求书的范围内的实施例的各种方面。应显而易见，本文中所描述的方面可体现于广泛多种形式中，且本文中所描述的任何特定结构及/或功能仅为说明性的。基于本申请，所属领域的技术人员应了解，本文中所描述的一个方面可与任何其它方面独立地实施，且可以各种方式组合这些方面中的两者或两者以上。举例来说，可使用本文中所阐述的任何数目和方面来实施设备及/或实践方法。另外，可使用除了本文中所阐述的方面中的一或多者之外的其它结构及/或功能性实施此设备及/或实践此方法。
还需要说明的是，以下实施例中所提供的图示仅以示意方式说明本申请 的基本构想，图式中仅显示与本申请中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
另外，在以下描述中，提供具体细节是为了便于透彻理解实例。然而，所属领域的技术人员将理解，可在没有这些特定细节的情况下实践。
在半导体晶圆测试阶段，需要对晶圆上的未封装芯片进行测试，测试过程中会用到探针卡，探针卡完成晶圆焊盘或凸点到测试机的电气连接，然后通过测试机完成晶圆芯片的性能量测，并完成对晶圆的筛选分类，剔除不符合设计要求的芯片。如图1所示，晶圆测试系统包括：测试机、探针卡、探针台和晶圆承载台以及晶圆，其中，探针卡包括：印刷电路板、有机基板和探针。
现有的用于晶圆测试的探针卡采用一种探针，但是，由于芯片的功能日益复杂，芯片上会同时包括多种信号和多种电源，这些信号和电源对于探针的性能要求不同。因此，需要针对不同的信号类型研发适配的探针，在同一张探针卡上采用多中探针，保证芯片上的各种信号和电源的性能最优。
基于此，本说明书实施例提出了一种处理方案：考虑不同信号和电源对性能的不同要求，针对不同信号和不同电源有针对性的研发探针，并将多种类型的探针应用在同一个的探针卡上，同时保证重要的信号和电源的性能，使探针卡的性能达到最优。
如图2和图3所示，信号和电源区域的焊盘排布明显有差异，测量可知信号区域的焊盘间距在130μm左右，而电源区域的焊盘间距在200μm左右。由于该项目数字信号数量非常多，速率要求也很高，要求达到30千兆比特每秒(Gbps),于此同时由于信号数量众多导致芯片的整体功耗也非常大，总电流在100A以上。
面对上面的要求，既要满足数字信号的高速要求，有要满足电源的大电流的要求，采用一款探针是无法做到的，因此需要针对数字信号和电源信号 进行优化，设计出针对数字信号和电源信号的专用探针。
以下结合附图，说明本申请各实施例提供的技术方案。
本说明书实施例提供一种混合型探针卡的制作方法，包括：
步骤1：根据芯片上至少一个信号区域的信号，对探针卡的探针尺寸进行优化处理，得到至少一种初始探针，其中，每一个信号区域对应一种初始探针。
具体的，芯片上会同时包含多种信号区域，不同的信号区域对于探针的要求不同，因此在本申请中对不同的信号区域的信号进行仿真，根据仿真结果对探针的尺寸进行优化处理，对应于每一种信号区域的得到对应的初始探针，得到至少一种初始探针。
步骤2：根据每一种初始探针的弹力和寿命以及预设标准，对至少一种初始探针进行优化处理，得到至少一种优化探针。
具体的，对于得到的每一种初始探针，其可能并不能很好的用于晶圆测试，初始探针的弹力和寿命可能并不适用于对应的信号区域，可能会造成需要对损耗和阻抗不满足要求的情况发生，因此需要对初始探针的弹力和寿命根据预设标准进行测试，根据测试结果至少一种初始探针进行优化处理，得到至少一种优化探针。
步骤3：根据至少一种优化探针以及对应的信号区域，将至少一种优化探针在探针卡中进行组装。
具体的，优化完成后，根据至少一种优化探针以及对应的信号区域，将至少一种优化探针在探针卡中进行组装，得到混合型探针卡，可以满足芯片的晶圆测试需求。
下面以信号区域包括数字信号区域和电源信号区域为例进行详细说明。
步骤01：根据芯片的数字信号区域中的数字信号和电源信号区域中的电源信号，对探针卡的探针尺寸进行优化处理，得到第一信号探针和第一电源探针。
具体的，根据芯片的数字信号区域和电源信号区域进行仿真，根据仿真结果对探针尺寸优化，对于数字信号区域的探针需要满足数字信号区域的要求，得到第一信号探针，对于电源信号区域的探针需要满足电源信号区域的要求，得到第一电源探针。
优选地，步骤01，包括：步骤101：利用仿真软件对数字信号和电源信号进行仿真，得到探针仿真结果；步骤102：根据仿真结果对探针卡的探针尺寸进行优化处理，得到第一信号探针和第一电源探针。
在本申请实施例中探针仿真结果包括：间距仿真结果、电仿真结果和弹力仿真结果，步骤101，包括：步骤1011：通过仿真软件对数字信号的焊盘间距和电源信号的焊盘间距进行仿真，得到数字信号和电源信号的间距仿真结果；步骤1012：根据数字信号和电源信号的性能要求对探针卡中的探针进行电仿真，得到数字信号和电源信号的电仿真结果；步骤1013：根据数字信号和电源信号对探针卡中的探针的弹力要求对探针卡进行弹力仿真，得到数字信号和电源信号的弹力仿真结果。
进一步地，步骤102，包括：步骤1021：根据间距仿真结果，确定探针卡中的探针的横向位移，得到探针的第一尺寸；步骤1022：根据电仿真结果，对第一尺寸进行优化处理，得到第二尺寸；步骤1023：根据弹力仿真结果，对第二尺寸进行优化处理，得到第一信号探针和第一电源探针。
其中，探针的第一尺寸的设计主要考虑因素是不同焊盘间距(pitch)支持的最大探针尺寸是不一样的，探针尺寸过大容易导致相邻探针出现短路问题，可以通过仿真确定探针的横向位移，保证探针不会出现短路问题。如图4所示，对探针进行仿真，图中的黑的实心方块表示探针导板，黑色曲线表示探针，其中，2处表示探针的固定端，即探针靠近有机基板的一端，1处是指仿真得到的探针的侧向位移最大处，A是指方针得到的探针的横向位移，根据横向位移，确定探针的第一尺寸。
进一步地，探针的电仿真依据晶圆上的焊盘排布，对探针部分进行建模， 根据晶圆的信号类型，区分信号针和地针，然后利用三维电磁场仿真软件计算探针的高速性能。高速性能主要的判断依据是信号的回波损耗和插入损耗，以及时域阻抗。对于高速而言，一般要求回波损耗尽量小，插入损耗尽量大，阻抗波动尽量小。
如图5到图7所示，根据数字信号和电源信号的性能要求对探针卡中的探针进行电仿真，得到数字信号和电源信号的电仿真结果。在图5到图7中实线表示Pitch为110μm的数据，虚线表示Pitch为150μm的数据，双短虚线表示Pitch为130μm的数据，长虚线表示Pitch为170μm的数据，其中图5中的横坐标为频率(freq)，单位GHz，纵坐标为回波损耗，无单位，其中，dB(S(55，55))、dB(S(53，53))、dB(S(51，51))和dB(S(49，49))分别代表Pitch为110μm、130μm、150μm和170μm的回波损耗的数据，图6的横坐标为频率，单位GHz，纵坐标为插入损耗，无单位，其中，dB(S(56，55))，dB(S(54，53))，dB(S(52，51))，dB(S(50，49))分别代表Pitch为110μm、130μm、150μm和170μm的插入损耗的数据，图7的横坐标为时间(time)，单位皮秒(psec)，纵坐标为时域阻抗，单位欧姆，其中，Sim_OHMS38、Sim_OHMS37、Sim_OHMS36和Sim_OHMS35分别代表Pitch为110μm、130μm、150μm和170μm的阻抗数据。图5中的m16表示在此处读出的各个曲线的频率和回波损耗，m16处的频率为：freq＝15.00GHz，回波损耗为：dB(S(49,49))＝-16.404，dB(S(51,51))＝-25.903，dB(S(53,53))＝-16.654，dB(S(55，55))＝-12.510。图6中的m14表示在此处读出的各个曲线的频率和插入损耗，m14处的频率为：freq＝15.00GHz，插入损耗为：dB(S(50，49))＝-0.258，dB(S(52，51))＝-0.142，dB(S(54，53))＝-0.209，dB(S(56，55))＝-0.355。图7中的m15表示在此处读出的各个曲线的时间和时域阻抗，m15处的时间为：time＝66.00psec，时域阻抗为：Sim_OHMS35＝87.003，Sim_OHMS36＝98.406，Sim_OHMS37＝107.248，Sim_OHMS38＝115.379。在图5到图7中实线表示 Pitch为110μm的数据，虚线表示Pitch为150μm的数据，双短虚线表示Pitch为130um的数据，长虚线表示Pitch为170um的数据，由图5到图7所示Pitch为130um为最优方案，该情况下回波损耗小，插入损耗大，阻抗波动小。此外分贝格式下描述，分贝格式下损耗值越大，表示实际损耗越。
另外，对于电源部分依据通流能力的计算公式进行计算，评估探针最优尺寸，表格1示出的为本申请实施例中的通流能力，如表格1给出了探针通流能力为1.10A，得到的探针有效长为3.5mil，探针有效宽为1.5mil，温升为80摄氏度。通流能力通过公式(1)计算得到，其中，I表示电流，K为0.048，A表示通流截面积，△T表示温度升高的度数。
I＝kΔT 0.44A 0.725；(1)
表格1
Figure PCTCN2022113296-appb-000001
更进一步地，基于探针卡对探针弹力的要求，利用优化出的探针第二尺寸，仿真探针的弹力是否过大或过小，如果探针弹力过大或过小，则需要依据探针材料参数表选取合适的探针材料，从而使探针的弹力符合要求。
举例说明，探针的弹力大小会影响对晶圆焊盘的损坏情况，一般当晶圆焊盘厚度在1μm左右时，探针的弹力一般不能超过2.5g，如果超过则有扎穿晶圆焊盘的风险。如果发现探针的弹力已经超过限定值，那就需要改进探针的材质，选用弹性模量更小的材质，弹性模量越大，探针弹力越大。
如图8和图9所示，对探针进行力学仿真，图8为对探针的弹性进行力学仿真的情况，其中，曲线表示探针，黑色实心方块表示有机基板，图9中的横坐标为过载(Over Driver，OD)，单位为μm，纵坐标为力(Force)，单 位为克力(gf)，通过优化，信号的探针尺寸为30x50μm，电源探针尺寸为30x65μm。
步骤02：根据第一信号探针和第一电源探针的弹力和寿命，以及预设标准，对第一信号探针和第一电源探针进行优化处理，得到第二信号探针和第二电源探针。
其中，预设标准可以为第一信号探针和第一电源探针的弹力趋向于一致。
优选地，步骤02，包括：步骤201：对第一信号探针和第一电源探针的弹力和寿命进行测试，得到第一信号探针的第一测试结果，以及第一电源探针的第二测试结果；步骤202：根据第一测试结果、第二测试结果以及预设标准，对第一信号探针和第一电源探针进行优化处理，得到第二信号探针和第二电源探针。
进一步地，步骤201，包括：步骤2011：判断第一测试结果和第二测试结果与预设标准是否一致；步骤2012：若是，则确定第一信号探针和第一电源探针，分别为第二信号探针和第二电源探针；步骤2013：若否，则对第一信号探针和第一电源探针进行优化处理，得到第二信号探针和第二电源探针。
具体地，通过实测确认第一信号探针和第一电源探针的弹力和寿命等指标是否符合要求，如果不符合还需要优化和调整，得到第二信号探针和第二电源探针。
如图10所示，为第一信号探针和第一电源探针的测试数据，其中，第一信号探针的探针尺寸为30x50μm，第一电源探针的探针尺寸为30x65μm，图中3所指代的点表示第一信号探针的数据，4所指代的点表示第一电源探针的数据。图10中的横坐标为过载，单位微米，纵坐标为弹力(Force)，单位为克(g))，从图10中可以看出，第一信号探针和第一电源探针的弹力几乎一致，可以保证探针在晶圆上的扎痕具备一致性，不因采用不同探针而产生差异。
如图11所示，为第一信号探针和第一电源探针的测试数据，横坐标为电 流(Current)，单位为毫安(mA)，纵坐标为弹力(Force)，单位为克(g)，图11中5所指代的点表示第一电源探针的数据，6所指代的点表示第一信号探针的数据，从图11中可以看出，第一信号探针和第一电源探针的通流能力不一致，电源探针的通流能力更好。
步骤03：根据芯片中的数字信号和电源信号的分布位置，将第二信号探针和第二电源探针在探针卡中进行组装。
如图12和图13所示，组装探针卡时需要注意的是由于信号和电源采用的探针尺寸不一样，要保证探针被植入到合适的位置，这样才能保证针卡的设计与成品是一致的。
进一步地，混合型探针卡的制作方法还包括：步骤4：根据芯片的测试需求，对探针的探针头的结构进行调整，得到混合型探针卡。
具体地，如果芯片测试上还有射频(RF)高频信号的测试需求，就需要对探针头的结构进行调整，增加专用的高频测试探针，该高频测试探针可以支持50μm以上的Pitch，支持的信号频率可以高达300GHz以上，高频测试探针一般向供应商定制。
其中，步骤4，包括：步骤401：将探针头的针尖设置为高频探针针尖，得到混合型探针卡。
如图14所示，为高频测试探针的结构简图，包括：高频探针针尖和接口，接口一般接线缆。高频测试探针可以是并排很多根，排布可以是多种类型，例如GSSGSSGSG等，G表示参考地，S表示信号。对外的接口一般是SMA系列，例如，K头V头等，可以直接接线缆，线缆可以连接至仪表。示例性的，某一款110G高频探针的主要参数，插入损耗(Insertion loss)为-2.0分贝(dB)，回波损耗(Return loss)为-10dB，频率范围(frequency range)为75到110GHz。某一款pitch可调的40GHz带宽的高频探针，主要参数，插入损耗(Insertion loss)为-1.0分贝(dB)，回波损耗(Return loss)为-15dB，频率范围(frequency range)为直流(DC)到110GHz。
本说明书实施例还提供一种探针卡，使用上述的混合型探针卡的制作方法制作，包括：印刷电路板、背部支撑件和至少一种探针，背部支撑件设置在印刷电路板上，至少一种探针设置在印刷电路板上。
优选地，还包括：位移平台；位移平台设置在印刷电路上，探针卡固定在位移平台上，位移平台通过位移移动将探针卡中的至少一种探针移动至工作位置。
下面以至少一种探针包括信号探针和电源探针为例进行详细说明。
探针卡包括：印刷电路板、背部支撑件、信号探针和电源探针；背部支撑件设置在印刷电路板上，信号探针和电源探针设置在印刷电路板上。
优选地，还包括：位移平台；位移平台设置在印刷电路上，探针卡固定在位移平台上，位移平台通过位移移动将探针卡中的信号探针和电源探针移动至工作位置。
具体地，如图15所示，包括：位移平台、仪表、背部支撑件、印刷电路板、信号探针和电源探针，还可以包括高频测试探针，高频测试探针通过线缆与仪表连接。印刷电路板上需开孔，用于放置探针和位移平台，探针固定在位移平台上，可能需要转接板，位移平台支持微小位移移动，支持将探针移动至合适位置，信号探针和电源探针的数量需要依据实际情况确定，开孔的数量也会有所不同，位移平台数量也会随之改变。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例侧重说明的都是与其他实施例的不同之处。尤其，对于后面说明的产品实施例而言，由于其与方法是对应的，描述比较简单，相关之处参见系统实施例的部分说明即可。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种混合型探针卡的制作方法，其特征在于，包括：
    步骤1：根据芯片上至少一个信号区域的信号，对所述探针卡的探针尺寸进行优化处理，得到至少一种初始探针，其中，每一个信号区域对应一种初始探针；
    步骤2：根据每一种所述初始探针的弹力和寿命以及预设标准，对所述至少一种初始探针进行优化处理，得到至少一种优化探针；
    步骤3：根据所述至少一种优化探针以及对应的所述信号区域，将至少一种所述优化探针在所述探针卡中进行组装。
  2. 根据权利要求1所述的混合型探针卡的制作方法，其特征在于，所述信号区域包括数字信号区域和电源信号区域，所述方法包括：
    步骤01：根据芯片的数字信号区域中的数字信号和电源信号区域中的电源信号，对所述探针卡的探针尺寸进行优化处理，得到第一信号探针和第一电源探针；
    步骤02：根据所述第一信号探针和所述第一电源探针的弹力和寿命，以及预设标准，对所述第一信号探针和所述第一电源探针进行优化处理，得到第二信号探针和第二电源探针；
    步骤03：根据所述芯片中的所述数字信号和所述电源信号的分布位置，将所述第二信号探针和所述第二电源探针在所述探针卡中进行组装。
  3. 根据权利要求2所述的混合型探针卡的制作方法，其特征在于，所述步骤01，包括：
    步骤101：利用仿真软件对所述数字信号和所述电源信号进行仿真，得到探针仿真结果；
    步骤102：根据所述仿真结果对所述探针卡的所述探针尺寸进行优化处理，得到所述第一信号探针和所述第一电源探针。
  4. 根据权利要求3所述的混合型探针卡的制作方法，其特征在于，所述探针仿真结果包括：间距仿真结果、电仿真结果和弹力仿真结果，所述步骤101，包括：
    步骤1011：通过所述仿真软件对所述数字信号的焊盘间距和所述电源信号的焊盘间距进行仿真，得到所述数字信号和所述电源信号的所述间距仿真结果；
    步骤1012：根据所述数字信号和所述电源信号的性能要求对所述探针卡中的探针进行电仿真，得到所述数字信号和所述电源信号的所述电仿真结果；
    步骤1013：根据所述数字信号和所述电源信号对所述探针卡中的所述探针的弹力要求对所述探针卡进行弹力仿真，得到所述数字信号和所述电源信号的所述弹力仿真结果。
  5. 根据权利要求1-4任一项所述的混合型探针卡的制作方法，其特征在于，所述步骤102，包括：
    步骤1021：根据所述间距仿真结果，确定所述探针卡中的探针的横向位移，得到所述探针的第一尺寸；
    步骤1022：根据所述电仿真结果，对所述第一尺寸进行优化处理，得到第二尺寸；
    步骤1023：根据所述弹力仿真结果，对所述第二尺寸进行优化处理，得到所述第一信号探针和所述第一电源探针。
  6. 根据权利要求2所述的混合型探针卡的制作方法，其特征在于，所述步骤02，包括：
    步骤201：对所述第一信号探针和所述第一电源探针的弹力和寿命进行测试，得到所述第一信号探针的第一测试结果，以及第一电源探针的第二测试结果；
    步骤202：根据所述第一测试结果、所述第二测试结果以及所述预设标准，对所述第一信号探针和所述第一电源探针进行优化处理，得到所述第二 信号探针和所述第二电源探针。
  7. 根据权利要求6所述的混合型探针卡的制作方法，其特征在于，所述步骤201，包括：
    步骤2011：判断所述第一测试结果和所述第二测试结果与所述预设标准是否一致；
    步骤2012：若是，则确定所述第一信号探针和所述第一电源探针，分别为所述第二信号探针和所述第二电源探针；
    步骤2013：若否，则对所述第一信号探针和所述第一电源探针进行优化处理，得到所述第二信号探针和所述第二电源探针。
  8. 根据权利要求2所述的混合型探针卡的制作方法，其特征在于，还包括：
    步骤4：根据所述芯片的测试需求，对所述探针的探针头的结构进行调整，得到所述混合型探针卡。
  9. 根据权利要求7所述的混合型探针卡的制作方法，其特征在于，所述步骤4，包括：
    步骤401：将所述探针头的针尖设置为高频探针针尖，得到所述混合型探针卡。
  10. 一种探针卡，其特征在于，使用权利要求1-9任一项所述的混合型探针卡的制作方法制作，包括：印刷电路板、背部支撑件和至少一种探针；
    所述背部支撑件设置在所述印刷电路板上，所述至少一种探针设置在所述印刷电路板上。
PCT/CN2022/113296 2022-06-30 2022-08-18 混合型探针卡的制作方法及探针卡 WO2024000761A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210778688.0 2022-06-30
CN202210778688.0A CN115112929A (zh) 2022-06-30 2022-06-30 混合型探针卡的制作方法及探针卡

Publications (1)

Publication Number Publication Date
WO2024000761A1 true WO2024000761A1 (zh) 2024-01-04

Family

ID=83329761

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/113296 WO2024000761A1 (zh) 2022-06-30 2022-08-18 混合型探针卡的制作方法及探针卡

Country Status (2)

Country Link
CN (1) CN115112929A (zh)
WO (1) WO2024000761A1 (zh)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05312833A (ja) * 1992-05-13 1993-11-26 Hitachi Ltd プローブカード
US20090289650A1 (en) * 2008-05-22 2009-11-26 Kabushiki Kaisha Toshiba Probe card and method for selecting the same
JP2009300234A (ja) * 2008-06-12 2009-12-24 Japan Electronic Materials Corp プローブカード
CN101680914A (zh) * 2007-04-03 2010-03-24 斯卡尼梅特里科斯有限公司 使用有源探针集成电路的电子电路的测试
CN102466739A (zh) * 2010-11-02 2012-05-23 旺矽科技股份有限公司 探针卡
US8310253B1 (en) * 2009-07-14 2012-11-13 Xilinx, Inc. Hybrid probe card
CN111443321A (zh) * 2020-03-13 2020-07-24 上海泽丰半导体科技有限公司 一种高速探针卡测试方法及测试系统
CN113030700A (zh) * 2021-03-04 2021-06-25 强一半导体（苏州）有限公司 一种晶圆级测试探针卡及晶圆级测试探针卡装配方法
CN215866990U (zh) * 2021-08-24 2022-02-18 北海惠科半导体科技有限公司 探针卡、检测装置及晶圆的检测装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011017564A (ja) * 2009-07-07 2011-01-27 Renesas Electronics Corp プローブカード、試験装置、試験方法およびコンピュータプログラム
US8836363B2 (en) * 2011-10-14 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Probe card partition scheme
CN104991097B (zh) * 2015-06-29 2018-05-29 上海华力微电子有限公司 一种探针卡
KR101845652B1 (ko) * 2017-01-17 2018-04-04 주식회사 텝스 부품 실장된 웨이퍼 테스트를 위한 하이브리드 프로브 카드
CN108535519B (zh) * 2018-04-23 2020-11-24 上海华虹宏力半导体制造有限公司 半导体芯片测试探针卡及测试系统和测试方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05312833A (ja) * 1992-05-13 1993-11-26 Hitachi Ltd プローブカード
CN101680914A (zh) * 2007-04-03 2010-03-24 斯卡尼梅特里科斯有限公司 使用有源探针集成电路的电子电路的测试
US20090289650A1 (en) * 2008-05-22 2009-11-26 Kabushiki Kaisha Toshiba Probe card and method for selecting the same
JP2009300234A (ja) * 2008-06-12 2009-12-24 Japan Electronic Materials Corp プローブカード
US8310253B1 (en) * 2009-07-14 2012-11-13 Xilinx, Inc. Hybrid probe card
CN102466739A (zh) * 2010-11-02 2012-05-23 旺矽科技股份有限公司 探针卡
CN111443321A (zh) * 2020-03-13 2020-07-24 上海泽丰半导体科技有限公司 一种高速探针卡测试方法及测试系统
CN113030700A (zh) * 2021-03-04 2021-06-25 强一半导体（苏州）有限公司 一种晶圆级测试探针卡及晶圆级测试探针卡装配方法
CN215866990U (zh) * 2021-08-24 2022-02-18 北海惠科半导体科技有限公司 探针卡、检测装置及晶圆的检测装置

Also Published As

Publication number Publication date
CN115112929A (zh) 2022-09-27

Similar Documents

Publication Publication Date Title
US20070040565A1 (en) Compliant probes and test methodology for fine pitch wafer level devices and interconnects
JP2018510355A (ja) フィルタリング特性を強化した、電子機器の試験装置のプローブカード
JP2010523945A (ja) アクティブプローブ集積回路を用いた電子回路試験
CN111707850A (zh) 探针装置
Leslie et al. Membrane Probe Card Technology (the Future for High Performance Wafer Test).
JPH06317624A (ja) 電極の接続装置
Yim et al. Microwave model of anisotropic conductive film flip-chip interconnections for high frequency applications
CN108205081B (zh) 一种用于微尺度焊球回波损耗测量的装置
CN110531125B (zh) 空间转换器、探针卡及其制造方法
WO2024000761A1 (zh) 混合型探针卡的制作方法及探针卡
US6992255B2 (en) Via and via landing structures for smoothing transitions in multi-layer substrates
Kam et al. 40-Gb/s package design using wire-bonded plastic ball grid array
CN112462178B (zh) 一种芯片插座s参数的测试结构及其测试方法
Leslie et al. Wafer-level testing with a membrane probe
US8402406B2 (en) Controlling plating stub reflections in a chip package
US8373432B2 (en) Automated test equipment employing test signal transmission channel with embedded series isolation resistors
Park et al. High-Frequency Electrical Characterization of a New Coaxial Silicone Rubber Socket for High-Bandwidth and High-Density Package Test
Carter 'Fuzz Button'interconnects at microwave and mm-wave frequencies
US7772861B2 (en) Probe card
Barber et al. A bare-chip probe for high I/O, high speed testing
CN207662969U (zh) 一种用于微尺度焊球回波损耗测量的装置
Abdullatif et al. Robust hot via interconnect technique with silver epoxy for gaas mmic
Kim et al. Signal integrity design and analysis of a multilayer test interposer for LPDDR4 memory test with silicone rubber-based sheet contact
Chuang et al. Radio frequency characterization of bonding wire interconnections in a molded chip
TWI747750B (zh) 雙面探針量測校正結構與校正方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22948852

Country of ref document: EP

Kind code of ref document: A1