WO2024000504A1 - 阵列基板及其制造方法、显示面板 - Google Patents

阵列基板及其制造方法、显示面板 Download PDF

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Publication number
WO2024000504A1
WO2024000504A1 PCT/CN2022/103104 CN2022103104W WO2024000504A1 WO 2024000504 A1 WO2024000504 A1 WO 2024000504A1 CN 2022103104 W CN2022103104 W CN 2022103104W WO 2024000504 A1 WO2024000504 A1 WO 2024000504A1
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Prior art keywords
substrate
insulating layer
via hole
opening
close
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PCT/CN2022/103104
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English (en)
French (fr)
Inventor
林滨
王洋
王金良
李启明
邹振游
李增荣
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 福州京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/103104 priority Critical patent/WO2024000504A1/zh
Priority to CN202280002106.8A priority patent/CN117642850A/zh
Publication of WO2024000504A1 publication Critical patent/WO2024000504A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present application relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • GOA Gate Driver on Array
  • the gate of at least one TFT needs to be electrically connected to the source or drain of other TFTs.
  • the transfer electrode is easily disconnected in the via hole, causing the GOA circuit on the array substrate to not work properly, resulting in poor display effect of the display panel.
  • Embodiments of the present application provide an array substrate, a manufacturing method thereof, and a display panel.
  • the problem of poor display effect of the display panel in the prior art can be solved.
  • the technical solution is as follows:
  • a method for manufacturing an array substrate including:
  • At least two insulating layers are formed on the first electrode, and a first etching process and a second etching process are sequentially performed on the at least two insulating layers to form at least two insulating layers in the at least two insulating layers. interconnected via holes, the size of the first via hole closest to the substrate among at least two of the via holes is smaller than the size of the other via holes;
  • a transfer electrode is formed on the at least two insulating layers, so that the transfer electrode overlaps the first electrode through at least two via holes.
  • forming at least two insulating layers on the first electrode, and sequentially performing a first etching process and a second etching process on the at least two insulating layers including:
  • the second insulating layer and the third insulating layer are sequentially subjected to a second etching process to form a second via in the second insulating layer connected to the third via hole. hole, and a first via hole connected to the second via hole is formed in the first insulating layer;
  • the orthographic projection of the opening of the second via hole away from the substrate on the substrate is located within the orthographic projection of the opening of the third via hole close to the substrate on the substrate, And the outer boundary of the orthographic projection of the opening of the second via hole away from the substrate on the substrate is the same as the orthographic projection of the opening of the third via hole close to the substrate on the substrate.
  • the outer boundaries do not overlap.
  • forming at least two insulating layers on the first electrode, and sequentially performing a first etching process and a second etching process on the at least two insulating layers including:
  • the orthographic projection of the opening of the first via hole away from the substrate on the substrate is located within the orthographic projection of the opening of the third via hole close to the substrate on the substrate, And the outer boundary of the orthographic projection of the opening of the first via hole close to the substrate on the substrate is the same as the orthographic projection of the opening of the third via hole close to the substrate on the substrate. The outer boundaries do not overlap.
  • forming at least two insulating layers on the first electrode, and sequentially performing a first etching process and a second etching process on the at least two insulating layers including:
  • the fourth insulating layer, the second insulating layer and the first insulating layer are sequentially subjected to a second etching process to form a third via hole in the fourth insulating layer.
  • a connected fourth via hole, a second via hole connected to the fourth via hole is formed in the second insulating layer, and a third via hole connected to the second via hole is formed in the first insulating layer.
  • the orthographic projection of the opening of the fourth via hole away from the substrate on the substrate is located within the orthographic projection of the opening of the third via hole close to the substrate on the substrate, And the outer boundary of the orthographic projection of the opening of the fourth via hole away from the substrate on the substrate is the same as the orthographic projection of the opening of the third via hole close to the substrate on the substrate.
  • the outer boundaries do not coincide; the second via hole is away from the orthogonal projection of the opening of the substrate on the substrate, and the fourth via hole is located close to the orthogonal projection of the opening of the substrate on the substrate.
  • the material of the first insulating layer and the third insulating layer includes silicon element and nitrogen element
  • the material of the second insulating layer includes silicon element and oxygen element
  • the materials of the first insulating layer and the third insulating layer include silicon element and nitrogen element.
  • the materials of the first insulating layer and the third insulating layer both contain silicon element and nitrogen element
  • the materials of the second insulating layer and the fourth insulating layer both contain silicon element and oxygen element.
  • the lateral etching ability of the first etching gas on the third insulating layer is stronger than the lateral etching ability of the second etching gas on the first insulating layer.
  • the first etching gas is a mixed gas of at least one of sulfur hexafluoride, sulfur tetrafluoride, carbon tetrafluoride and nitrogen fluoride and the oxygen.
  • the second etching gas is a mixed gas of nitrogen trifluoride gas and oxygen.
  • an array substrate which is characterized by including:
  • a first electrode, a transfer electrode and at least two insulating layers are provided on the substrate.
  • the first electrode is located on a side of the at least two insulating layers close to the first electrode.
  • the transfer electrode is located on the side of the at least two insulating layers. The side of the at least two insulating layers facing away from the substrate;
  • the at least two insulating layers have at least two interconnected via holes, the size of the first via hole closest to the substrate among the at least two via holes is smaller than the size of the other via holes, and the turning hole is The connecting electrode overlaps with the first electrode through at least two via holes.
  • the at least two insulating layers include: a first insulating layer, a second insulating layer and a third insulating layer sequentially arranged in a direction perpendicular to and away from the substrate, and the first insulating layer has a first insulating layer.
  • via hole the second insulating layer has a second via hole connected to the first via hole
  • the third insulating layer has a third via hole connected to the second via hole;
  • the orthographic projection of the opening of the second via hole away from the substrate on the substrate is located within the orthographic projection of the opening of the third via hole close to the substrate on the substrate, And the outer boundary of the orthographic projection of the opening of the second via hole away from the substrate on the substrate is the same as the orthographic projection of the opening of the third via hole close to the substrate on the substrate.
  • the outer boundaries do not overlap.
  • the first via hole is away from the outer boundary of the orthographic projection of the opening of the substrate on the substrate, and the second via hole is close to the opening of the substrate on the substrate.
  • the outer boundaries of the orthographic projections coincide with each other.
  • the angle between the sidewall of the third via hole and the side of the third insulating layer close to the substrate is less than 60°.
  • the angle between the sidewall of the third via hole and the side of the third insulating layer close to the substrate is less than or equal to 45°.
  • the second via hole is away from the outer boundary of the orthographic projection of the opening of the substrate on the substrate, and the third via hole is close to the opening of the substrate on the substrate.
  • the distance between the outer boundaries of the orthographic projection ranges from: 0.2 ⁇ m to 0.5 ⁇ m.
  • the thickness of the second insulating layer ranges from 500 angstroms to 1000 angstroms, and the angle between the sidewall of the second via hole and the side of the second insulating layer close to the substrate is greater than or equal to 30°, and less than or equal to 50°.
  • the thickness of the second insulating layer ranges from 200 angstroms to 500 angstroms, and the angle between the sidewall of the second via hole and the side of the second insulating layer close to the substrate is less than or equal to 30°.
  • the angle between the sidewall of the first via hole and the side of the first insulation layer close to the substrate is greater than or equal to 80° and less than 90°.
  • the at least two insulating layers include: a first insulating layer and a third insulating layer sequentially arranged in a direction vertical and away from the substrate, the first insulating layer has a first via hole, and the The third insulating layer has a third via hole connected to the first via hole;
  • the orthographic projection of the opening of the first via hole away from the substrate on the substrate is located within the orthographic projection of the opening of the third via hole close to the substrate on the substrate, And the outer boundary of the orthographic projection of the opening of the first via hole close to the substrate on the substrate is the same as the orthographic projection of the opening of the third via hole close to the substrate on the substrate.
  • the outer boundaries do not overlap.
  • a portion of the side wall of the first via hole close to the third insulating layer is an arc-shaped side wall.
  • the angle between the arc-shaped sidewall and the side of the first insulating layer close to the substrate is less than or equal to 30°.
  • the sidewall of the first via hole also has a planar sidewall located on the side of the arcuate sidewall close to the substrate, and the planar sidewall is in contact with the first insulating layer close to the liner.
  • the angle between the bottom surfaces is greater than or equal to 80° and less than 90°.
  • the at least two insulating layers include: a first insulating layer, a second insulating layer, a fourth insulating layer and a third insulating layer sequentially arranged in a direction perpendicular to and away from the substrate, the first insulating layer
  • the insulating layer has a first via hole
  • the second insulating layer has a second via hole connected to the first via hole
  • the fourth insulating layer has a fourth via hole connected to the second via hole
  • the third insulating layer has a third via hole connected to the fourth via hole;
  • the orthographic projection of the opening of the fourth via hole away from the substrate on the substrate is located within the orthographic projection of the opening of the third via hole close to the substrate on the substrate, And the outer boundary of the orthographic projection of the opening of the fourth via hole away from the substrate on the substrate is the same as the orthographic projection of the opening of the third via hole close to the substrate on the substrate.
  • the outer boundaries do not coincide; the second via hole is away from the orthogonal projection of the opening of the substrate on the substrate, and is located close to the orthogonal projection of the opening of the substrate on the substrate.
  • the materials of the second insulating layer and the fourth insulating layer both contain silicon element and oxygen element, and the distribution density of silicon element and oxygen element in the material of the fourth insulating layer is smaller than that of the third insulating layer.
  • the distribution density of silicon element and oxygen element in the material of the second insulating layer is smaller than that of the third insulating layer.
  • the second via hole is away from the outer boundary of the orthographic projection of the opening of the substrate on the substrate, and the third via hole is close to the opening of the substrate on the substrate.
  • the distance between the outer boundaries of the orthographic projection ranges from: 0.4 ⁇ m to 0.6 ⁇ m.
  • the array substrate further includes: a second electrode located between two adjacent insulating layers among the at least two insulating layers, and the at least two insulating layers further have a first overlapping via hole. , the transfer electrode is overlapped with the second electrode through the first overlap via hole.
  • At least two interconnected via holes in the at least two insulation layers are used to form a second overlapping via hole, and the side walls of the second overlapping via hole have a plurality of columnar compounds, so The average height of the columnar compound is smaller than the thickness of the transfer electrode.
  • the angle between the tangent line of the top of the columnar compound protrusion and the horizontal direction is smaller than the slope angle of the transfer electrode.
  • the elements composing the columnar compound include: carbon element, oxygen element, fluorine element and copper element.
  • a display panel including: an array substrate and a color filter substrate arranged oppositely.
  • the array substrate is the array substrate described in the second aspect.
  • An array substrate includes: a substrate, a first electrode, a transfer electrode and at least two insulating layers located on the substrate. Since the size of the first via hole closest to the substrate among the at least two via holes is smaller than the size of the other via holes, a step structure may be formed in the second overlapping via hole. In this way, it can be ensured that part of the transfer electrode can be located on this step structure. In this way, the contact area between the transfer electrode located in the second overlapping via hole and each film layer is increased, and the problem of disconnection is less likely to occur, so that the overlap effect between the transfer electrode and the first electrode is better.
  • the electrical connection effect between different TFTs in the GOA circuit is better, thereby making the display device equipped with the array substrate provided by the embodiment of the present application have a better display effect.
  • the slope angle and structure of each film layer can be controlled, as well as the size of the columnar compound, thereby improving the yield and current resistance of the display panel.
  • Figure 1 is a schematic plan view of an array substrate
  • Figure 2 is a schematic diagram of the film layer structure of the array substrate shown in Figure 1 at A-A';
  • Figure 3 is a cross-sectional scanning electron microscope image of the inside of the via hole after long-term etching
  • Figure 4 is a schematic diagram of the film structure of an insulating layer with a first via hole
  • Figure 5 is a schematic plan view of an array substrate provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of the film structure of the array substrate at A-A' shown in Figure 5;
  • Figure 7 is a schematic diagram of the film structure of an array substrate provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of an array substrate with a photoresist film provided by an embodiment of the present application.
  • Figure 9 is a schematic diagram of an array substrate forming a third via hole provided by an embodiment of the present application.
  • Figure 10 is a schematic diagram of an array substrate forming a second via hole according to an embodiment of the present application.
  • Figure 13 is a cross-sectional scanning electron microscope view of a second overlapping via hole formed in another array substrate provided by an embodiment of the present application;
  • Figure 14 is a schematic diagram of the film structure of another array substrate provided by an embodiment of the present application.
  • Figure 15 is a schematic diagram of another array substrate with a photoresist film provided by an embodiment of the present application.
  • Figure 17 is a schematic diagram of another array substrate for forming first via holes provided by an embodiment of the present application.
  • Figure 18 is a cross-sectional scanning electron microscope view of a second overlapping via hole formed in yet another array substrate provided by an embodiment of the present application;
  • Figure 19 is a schematic diagram of the film structure of yet another array substrate provided by an embodiment of the present application.
  • Figure 20 is a schematic diagram of yet another array substrate with a photoresist film provided by an embodiment of the present application.
  • Figure 21 is a schematic diagram of yet another array substrate for forming a third via hole provided by an embodiment of the present application.
  • Figure 22 is a schematic diagram of an array substrate forming a fourth via hole and a second via hole according to an embodiment of the present application
  • Figure 23 is a schematic diagram of yet another array substrate with first via holes provided by an embodiment of the present application.
  • Figure 24 is a cross-sectional scanning electron microscope view of a second overlapping via hole formed in yet another array substrate provided by an embodiment of the present application.
  • FIG. 25 is a diagram showing the overlapping effect of a transfer electrode provided in the second overlapping via hole according to the embodiment of the present application.
  • FIG. 1 is a schematic plan view of an array substrate.
  • the array substrate 00 has a display area 0a and a non-display area 0b located at the periphery of the display area 0a. Among them, a plurality of sub-pixels (not marked in the figure) are provided in the display area 0a, and a GOA circuit 0b1 is provided in the non-display area 0b.
  • the array substrate 00 can control multiple sub-pixels provided in the display area 0a through the GOA circuit 0b1, so that the display device can display images.
  • Figure 2 is a schematic diagram of the film structure of the array substrate at A-A' shown in Figure 1.
  • the array substrate may include: a substrate 01, and a TFT 02, a first passivation layer 03, an organic insulating layer 04, a pixel electrode 05, a second passivation layer 06 and a common electrode 07 that are stacked on the substrate 01.
  • TFT 02 may include: gate electrode 021, active layer 024, source electrode 023 and drain electrode 022.
  • the source electrode 023 and the drain electrode 022 are both overlapped with the active layer 024 , and the active layer 024 and the gate electrode 021 are insulated by a gate insulating layer 025 .
  • the pixel electrode 05 may be electrically connected to one of the source electrode 024 and the drain electrode 025 in the TFT 02 through the connection via hole V00.
  • the gate insulation layer 025 has a first gate insulation layer 0251 and a second gate insulation layer 0252, and the first gate insulation layer 0251 is closer to the active layer pattern 024 than the second gate insulation layer 0252.
  • the gate insulating layer 025 Both a gate insulation layer 0251 and the first passivation layer 03 can be made of silicon oxide material with better insulation effect.
  • both the second gate insulating layer 0252 and the second passivation layer 06 may be made of silicon nitride material.
  • the GOA circuit 0b1 in the non-display area 0b of the array substrate 00 usually also includes multiple TFTs, and these TFTs can be arranged on the same layer as the TFT 02 in the display area 0a. Because in the GOA circuit 0b1, there is at least one gate 08 of TFT that needs to be electrically connected to the source or drain 09 of other TFTs. Therefore, it is usually necessary to drill multiple insulating layers in the array substrate 00, and use a transfer electrode 010 arranged on the same layer as the common electrode 07 to connect the gate electrode 08 of one TFT and the source or drain of another TFT. 09 Carry out overlapping.
  • the GOA circuit 0b1 can control multiple sub-pixels provided in the display area 0a, so that the display device can normally display images after the array substrate 00 is integrated into the display device.
  • a patterning process is usually used to punch multiple insulating layers in the GOA circuit 0b1 to form the first via hole V01 and the second via hole V02 in the array substrate 00.
  • the transfer electrode 010 can pass through the first via hole V01.
  • the overlapping via V01 overlaps the gate electrode 08 of one TFT, and can overlap the source or drain electrode 09 of another TFT through the second via V02.
  • the first passivation layer 03 and the organic insulating layer 04 located in the non-display area 0b are usually also removed.
  • the first gate insulating layer 0251, the second gate insulating layer 0252 and the second passivation layer 06 need to be etched simultaneously;
  • the second passivation layer 06 needs to be etched.
  • the first gate insulating layer 0251 is made of silicon oxide material, when the silicon oxide material is drilled, the etching rate of the silicon dioxide by the etching gas is slow. Therefore, in the process of forming the first via hole V01, the etching time of the first gate insulating layer 0251 made of silicon oxide material is longer, resulting in lower manufacturing efficiency of the array substrate 00.
  • Figure 3 is a cross-sectional scanning electron microscope image of the inside of the via hole after long-term etching. It can be seen from the microscopic morphology that during the long-term etching process, carbon-containing by-products (such as CH 2 , CF 2 , COF, etc.) may be produced. These carbon-containing by-products may interact with the Cu particles on the metal surface. Combined, a columnar compound 011 will be formed on the inner wall of the first via hole V01. In this way, when the transfer electrode 010 is used to overlap the gate electrode 08 of the TFT through the first via hole V01, the columnar compound 011 on the inner wall of the first via hole V01 will give way to the transfer electrode 011 in the first via hole V01.
  • the transfer electrode 010 is used to overlap the gate electrode 08 of the TFT through the first via hole V01
  • the columnar compound 011 on the inner wall of the first via hole V01 will give way to the transfer electrode 011 in the first via hole V01.
  • the connecting electrode 010 has poor overlapping, which leads to poor overlapping effect between the connecting electrode 010 and the gate electrode 08 of the TFT.
  • the columnar compound 011 on the inner wall of the via hole may cause the GOA circuit 0b1 to fail to work, thereby resulting in poor display effect of the display device.
  • Figure 4 is a schematic diagram of a film structure of an insulating layer with a first via hole.
  • the etching gas has a strong longitudinal etching ability on the second passivation layer 06 and a weak lateral etching ability on the second passivation layer 06. Therefore, the slope angle ⁇ of the second passivation layer 06 is relatively large.
  • the slope angle ⁇ of the second passivation layer 06 is generally greater than 60°. In this way, the problem of disconnection easily occurs between the portion of the transfer electrode 010 located outside the first via hole V01 and the portion located within the first via hole V01 .
  • the etching rate of the second gate insulating layer 0252 made of silicon nitride material is greater than that of the second gate insulating layer 0252 made of silicon nitride material. Due to the etching rate of the first gate insulating layer 0251 made of silicon oxide material, bumps are easily generated at the position Q of the second gate insulating layer 0252 close to the first gate insulating layer 0251 in the first via hole V01. In this way, when the transfer electrode 010 located in the first via hole V01 is prone to disconnection at the position Q, the overlapping effect between the common electrode 07 and the gate electrode 08 of the TFT is poor. After the disconnection problem occurs in the transfer electrode 010, it may also cause the GOA circuit 0b1 to fail to work.
  • Figure 5 is a top view of an array substrate provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of the film structure of the array substrate at A-A’ shown in Figure 5.
  • the array substrate 000 has a display area 00a and a non-display area 00b located at the periphery of the display area 00a.
  • a plurality of sub-pixels 001 arranged in an array are distributed in the display area 00a, and GOA circuits 002 are distributed in the non-display area 00b.
  • the GOA circuit 002 can be electrically connected to the gate electrode of the driving TFT in each sub-pixel 001, so that the GOA circuit 002 can drive the driving TFT in each sub-pixel 001 to operate.
  • the GOA circuit 002 may include multiple TFTs arranged in the same layer as the driving TFTs in each sub-pixel 001.
  • the multiple TFTs in the GOA circuit 002 there is a gate of one TFT (that is, the first gate electrode in the following).
  • the electrode 500) needs to be electrically connected to one of the source electrode and the drain electrode of another TFT (ie, the second electrode 700 below). Since the array substrate 000 usually contains multiple insulating layers, when the first electrode 500 and the second electrode 700 need to be overlapped, the first overlapping vias V10 and V10 need to be formed in the insulating layer located in the non-display area 00b.
  • the second lap via hole V20 is arranged in the same layer as the driving TFTs in each sub-pixel 001.
  • the first overlapping via hole V10 and the second overlapping via hole V20 in the array substrate 000 are usually formed based on one patterning process. For example, first, a photoresist film can be coated on the array substrate 000 with an insulating layer formed thereon; then, a photoresist pattern can be obtained by performing one exposure and development on the photoresist film coated on the array substrate 000; Then, dry etching is used to etch the portion of the array substrate 000 that does not have the photoresist pattern attached; finally, the photoresist on the array substrate 000 is peeled off, so that the non-display area 00b in the array substrate 000 can be A first overlapping via hole V10 and a second overlapping via hole V20 are formed therein.
  • the first electrode 500 needs to be located in the second overlapping via hole V20, and at least part of the second electrode 700 needs to be located in the first overlapping via hole V10, and the transfer electrode 600 needs to be located in the second overlapping via hole V10.
  • the overlapping via hole V20 overlaps with the first electrode 500, and the first overlapping via hole V10 overlaps with the second electrode 700. In this way, the first electrode 500 and the second electrode 700 can be overlapped through the transfer electrode 600 .
  • the first electrode 500 belongs to the gate metal layer in the array substrate 000
  • the second electrode 700 belongs to the source and drain metal layer in the array substrate 000
  • the gate metal layer is smaller than the source and drain metal layer.
  • the conductive layer where the transfer electrode 600 is located is generally located at the outermost side of the array substrate 000. Therefore, the thickness of the insulating layer between the transfer electrode 600 and the first electrode 500 is greater than the thickness of the insulating layer between the transfer electrode 600 and the second electrode 700 , that is, the second bridge formed in the array substrate 000
  • the depth of the connecting via hole V20 is greater than the depth of the first overlapping via hole V10.
  • the greater the depth of the overlapping via hole the more likely it is that defects will occur during the formation process.
  • the second overlapping via hole V20 in the array substrate 000 provided by the embodiment of the present application has a lower probability of developing defects. Therefore, the following embodiments will focus on illustrating the structural principle and formation process of the second overlapping via hole V20 with a larger depth.
  • Embodiments of the present application provide an array substrate.
  • the array substrate may include: a substrate; a first electrode, a transfer electrode and at least two insulating layers provided on the substrate.
  • the first electrode is located close to the at least two insulating layers.
  • the transfer electrode is located on a side of at least two insulating layers facing away from the substrate.
  • At least two insulating layers have at least two interconnected via holes, the size of the first via hole closest to the substrate among the at least two via holes is smaller than the size of other via holes, and the transfer electrode passes through the at least two via holes. Overlapping with the first electrode.
  • At least two interconnected via holes in at least two insulation layers are used to form a second overlapping via hole. Because the size of the first via hole closest to the substrate among the at least two via holes is smaller than the size of the other via holes.
  • two etching gas distributions may be used to etch at least two insulating layers, thereby forming via holes with different sizes in at least two insulating layers. Therefore, a step structure can be formed in the second overlapping via hole. In this way, it can be ensured that part of the transfer electrode can be located on this step structure.
  • FIG. 7 is a schematic diagram of the film structure of an array substrate provided by an embodiment of the present application.
  • the array substrate 000 may include: a substrate 100, a first insulating layer 200, a second insulating layer 300, a third insulating layer 400, a first electrode 500 and a transfer electrode 600.
  • the first insulating layer 200 , the second insulating layer 300 and the third insulating layer 400 are sequentially stacked in a direction vertical and away from the substrate 100 .
  • the first insulating layer 200 has a first via hole V1
  • the second insulating layer 300 has a second via hole V2 connected to the first via hole V1
  • the third insulating layer 400 has a third via hole connected to the second via hole V2. V3.
  • the first via hole V1, the second via hole V2, and the third via hole V3 can form the second overlapping via hole V20 in the above embodiment.
  • the orthographic projection of the opening of the second via hole V2 away from the substrate 100 on the substrate 100 is located within the orthographic projection of the opening of the third via hole V3 close to the substrate 100 on the substrate 100, and the second via hole V2
  • the outer boundary of the orthographic projection of the opening on the substrate 100 away from the substrate 100 does not coincide with the outer boundary of the orthographic projection of the opening of the third via V3 close to the substrate 100 on the substrate 100 .
  • the second overlapping via hole V20 composed of the first via hole V1
  • the second via hole V2 and the third via hole V3 the second insulating layer 300 will protrude from the third insulating layer 400.
  • the outer boundary of the orthographic projection of a certain opening on the substrate 100 refers to the outline frame of the orthographic projection of this opening on the substrate 100 .
  • the first electrode 500 is located on a side of the first insulating layer 200 close to the substrate 100 , and the orthographic projection of the first electrode 500 on the substrate 100 at least partially coincides with the orthographic projection of the first via V1 on the substrate 100 . In this way, at least part of the first electrode 500 is within the first via hole V1 in the first insulation layer 200 .
  • the first electrode 500 is the gate electrode of a certain TFT in the GOA circuit 001 in the above embodiment.
  • the transfer electrode 600 is located on a side of the third insulating layer 400 facing away from the substrate 100 . At least part of the transfer electrode 600 is located in the first via hole V1 , the second via hole V2 and the third via hole V3 , and is connected with the first via hole V1 , the second via hole V2 and the third via hole V3 .
  • the electrodes 500 overlap.
  • the second insulating layer 300 will protrude beyond the third insulating layer. 400, and the part of the second insulating layer 300 protruding from the third insulating layer 400 is a step structure. Therefore, after at least part of the transfer electrode 600 is located in the second overlapping via hole V20, part of the transfer electrode 600 can be located on this step structure. In this way, the contact area between the transfer electrode 600 located in the second overlapping via hole V20 and each film layer is increased, and the problem of disconnection is less likely to occur, so that the overlap effect between the transfer electrode 600 and the first electrode 500 is better. In this way, it can be ensured that the electrical connection effect between different TFTs of the GOA circuit 002 is better, thereby making the display device equipped with the array substrate provided by the embodiment of the present application have a better display effect.
  • the first via V1 in the first insulation layer 200 is away from the outer boundary of the orthographic projection of the opening of the substrate 100 on the substrate 100 , and the second via V2 in the second insulation layer 300 is close to the substrate.
  • the opening of the bottom 100 coincides with the outer boundary of the orthographic projection on the substrate 100 .
  • redundant protrusions are easily generated at the position Q in the via hole in the array substrate.
  • the first insulating layer 200 is in the first via hole V1 and the second via hole V2 that are connected to each other.
  • the angle ⁇ 1 between the sidewall of the third via hole V3 and the side of the third insulating layer 400 close to the substrate 100 is less than 60°.
  • the angle ⁇ 1 between the sidewall of the third via hole V3 and the side of the third insulating layer 400 close to the substrate 100 is less than or equal to 45°.
  • the thickness of the third insulating layer 400 is 1000 angstroms to 4000 angstroms.
  • the slope angle ⁇ of the second passivation layer 06 in the array substrate is relatively large.
  • the angle ⁇ 1 between the side wall of the third via hole V3 and the side close to the substrate 100 is relatively large.
  • the portion of the transfer electrode 600 inside the first via hole V1 and outside the first via hole V1 is less likely to be disconnected.
  • the angle ⁇ 1 between the side wall of the third via hole V3 and the side of the third insulating layer 400 close to the substrate 100 is small, so that the transfer electrode 600 overlaps the third via hole V3.
  • the overlapping effect between the electrode 600 and the third via hole V3 is better, so that the display device equipped with the array substrate provided by the embodiment of the present application has a better display effect.
  • the second via hole V2 in the second insulating layer 300 is away from the outer boundary of the orthographic projection of the opening of the substrate 100 on the substrate 100, and the third via hole V3 in the third insulating layer 400 is close to the substrate.
  • the distance h between the outer boundary of the orthographic projection of the opening of the bottom 100 on the substrate 100 ranges from 0.2 microns to 0.5 microns.
  • the second via hole V2 in the second insulating layer 300 is away from the outer boundary of the orthographic projection of the opening of the substrate 100 on the substrate 100
  • the third via hole V3 in the third insulating layer 400 is close to the substrate 100
  • the distance h between the outer boundaries of the orthographic projection of the opening on the substrate 100 is the width of the step structure of the second insulating layer 300 protruding from the third insulating layer 400 .
  • the width of the step structure ranges from 0.2 microns to 0.5 microns, at least part of the transfer electrode 600 can be located in the second overlapping via hole V20 and fall on the step structure at the same time, and the position on the second overlapping via hole V20 can be further reduced. There is a probability that the transfer electrode 600 in the via hole V20 may be disconnected.
  • the included angle ⁇ 2 is greater than or equal to 30° and less than or equal to 50°; in some other embodiments, the included angle ⁇ 2 is less than or equal to 30°.
  • the angle ⁇ 2 between the sidewall of the second via hole V2 and the side of the second insulating layer 300 close to the substrate 100 is less than or equal to 50°; or, when the thickness of the second insulating layer 300 ranges from 200 angstroms to 500 angstroms, the angle ⁇ 2 between the sidewall of the second via hole V2 and the side of the second insulating layer 300 close to the substrate 100 is less than or equal to 30°.
  • the angle ⁇ 2 between the sidewall of the second via hole V2 and the side of the second insulating layer 300 close to the substrate 100 has a certain correlation with the second insulating layer 300 , but by controlling the second insulating layer The thickness of the layer 300 can ensure that the angle ⁇ 2 between the sidewall of the second via hole V2 and the side of the second insulating layer 300 close to the substrate 100 is small. In this way, when the transfer electrode 600 overlaps the second via hole V2, the overlap effect between the transfer electrode 600 and the side wall of the second via hole V2 in the second insulating layer 300 is better, that is, the connection between the transfer electrode 600 and the second via hole V2 is better. The transfer electrode 600 in the second overlapping via hole V20 is less likely to be disconnected.
  • the side walls of the second via hole V2 in the insulating layer 300 are overlapped, so that the transfer electrode 600 located in the second overlapping via hole V20 is less likely to be disconnected.
  • the angle ⁇ 3 between the sidewall of the first via V1 in the first insulating layer 200 and the side of the first insulating layer 200 close to the substrate 100 is greater than or equal to 80° and less than 90°.
  • the angle ⁇ 3 between the sidewall of the first via hole V1 in the first insulating layer 200 and the side of the first insulating layer 200 close to the substrate 100 is relatively large.
  • the angle ⁇ 2 between the sidewall of the second via hole V2 in the second insulating layer 300 and the side of the second insulating layer 300 close to the substrate 100 is small, and the sidewall of the third via hole V3 is close to The angle ⁇ 1 between one side of the substrate 100 is also small.
  • the transfer electrode 600 After at least part of the transfer electrode 600 is overlapped with the side wall of the first via hole V1 in the first insulating layer 200 , it can also be ensured that at least part of the transfer electrode 600 is connected to the first insulating layer 200 .
  • the overlapping effect of the side walls of the first via V1 is better. In this way, the display effect of the display device equipped with the array substrate provided by the embodiment of the present application is better.
  • the first insulating layer 200 and the third insulating layer 400 are both made of SiNx (x>0) material
  • the second insulating layer 300 is made of SiOy (y>0) material.
  • SiNx refers to a substance that contains the nitrogen element in composition and contains 10 atomic % to 50 atomic % silicon and 5 atomic % to 25 atomic % hydrogen in a concentration range such that the total becomes 100 Each element is included in atomic % and at any concentration.
  • SiOy refers to a substance that contains oxygen in its composition and contains silicon in the concentration range of 10 atomic % to 50 atomic % and 1 atomic % to 25 atomic %.
  • the first insulating layer 200 and the third insulating layer 400 include silicon nitride material
  • the second insulating layer Layer 300 includes silicon oxide material.
  • FIG. 8 is a schematic diagram of an array substrate with a photoresist film provided by an embodiment of the present application.
  • the photoresist pattern 111 may be baked. After the baking process, the edge of the photoresist pattern 111 close to the opening V11 will collapse, so that the portion of the photoresist pattern 111 close to the opening V11 forms a certain slope angle.
  • the baking process is controlled so that the angle formed between the side of the photoresist pattern 111 close to the substrate 100 and the side of the opening V11 is less than or equal to 50°.
  • the baked photoresist pattern 111 has higher strength and is less likely to deform after being bombarded by the etching gas.
  • FIG. 6 schematically illustrates the photoresist film 111 having an opening portion as an example.
  • the etching gas can enter from the opening V11 and sequentially etch the third insulating layer 400, The second insulating layer 300 and the first insulating layer 200 are etched.
  • the angle formed between the side of the baked photoresist pattern 111 close to the substrate 100 and the side of the opening is less than or equal to 50°, therefore, the angle of the photoresist pattern 111 close to the opening V11
  • the lateral thickness of the part is small, so that the part of the photoresist pattern 111 close to the opening V11 is more likely to shrink under the action of the etching gas, thereby avoiding the subsequent shrinkage of the part of the photoresist pattern 111 close to the opening V11.
  • the problem of holes appearing on the side walls of the first via hole V1, the second via hole V2 and the third via hole V3 that is, the second overlapping via hole V20
  • the transfer electrode 600 formed in the two overlapping via holes V20 may have a disconnection problem.
  • FIG. 9 is a schematic diagram of an array substrate for forming a third via hole according to an embodiment of the present application.
  • a photoresist pattern 111 is formed on the array substrate 000, and after the photoresist pattern 111 is baked, at least one of sulfur hexafluoride, sulfur tetrafluoride, carbon tetrafluoride and nitrogen fluoride can be used.
  • a mixed gas of the first gas and the oxygen is used as the first etching gas to etch the third insulating layer 400 on the array substrate 000 so that openings with the photoresist pattern 111 can be formed in the third insulating layer 400 V11 is connected to the third via V3.
  • the third insulating layer 400 is made of silicon nitride material, and the etching rate of the silicon nitride material by the first etching gas is relatively fast, usually the longitudinal etching rate of the silicon nitride material by the first etching gas is will be greater than 10,000 Angstroms per minute. Therefore, the time for etching the third via hole V3 formed by the third insulating layer 400 can be shortened, thereby improving the manufacturing efficiency of the array substrate 00 .
  • the second insulating layer 300 is made of silicon oxide material, the etching speed of the silicon oxide material by the first etching gas is slow. Therefore, when the first etching gas is used to longitudinally etch the third insulating layer 400, although the first etching gas will etch the second insulating layer 300, it will not cause much damage to the second insulating layer 300. Influence. Moreover, the first etching gas also has strong lateral etching ability. Therefore, during the etching process of the third insulating layer 400 by the first etching gas, the third insulating layer 400 will shrink inward relative to the photoresist pattern 111, so that a larger opening is formed in the third insulating layer 400. Three vias V3.
  • the orthographic projection of the opening V11 of the photoresist pattern 111 on the substrate 100 will be located within the orthographic projection of the third via hole V3 on the substrate 100 .
  • the lateral etching ability of the first etching gas on the third insulating layer 400 is strong, it can also be ensured that the side wall of the third via V3 in the third insulating layer 400 is close to the lining in the third insulating layer 400 .
  • the angle ⁇ 1 between the two sides of the bottom 100 is less than or equal to 45°.
  • the opening in the third insulating layer 400 facing away from the substrate 100 may be 9.7 microns, and the opening in the third insulating layer 400 close to the substrate 100 may be 8.8 microns.
  • the length of the side wall of the third via V3 is greater than 0.4 micron.
  • FIG. 10 is a schematic diagram of an array substrate for forming a second via hole according to an embodiment of the present application.
  • a mixed gas of nitrogen trifluoride gas and oxygen can be used as the second etching gas to etch the second insulating layer 300 in the array substrate 000.
  • the second via hole V2 connected to the third via hole V3 can be formed in the second insulating layer 300 .
  • the second insulating layer 300 is made of silicon oxide material, and the etching rate of the second etching gas on the silicon oxide material is relatively fast, usually the longitudinal etching rate of the second etching gas on the silicon oxide material is about 4000 Angstroms per minute. Therefore, the time for etching the second via hole V2 formed by the second insulating layer 300 can be greatly shortened, further improving the manufacturing efficiency of the array substrate 000 .
  • the second insulating layer 300 will not shrink relative to the photoresist pattern 111. That is, the second insulating layer 300 will not shrink in the lateral direction. It is not easily etched by the second etching gas, so that after the second via hole V2 is formed in the second insulating layer 300, the second insulating layer 300 will protrude from the third insulating layer 400, and the second insulating layer 300 will protrude from the third insulating layer 400.
  • the part emerging from the third insulating layer 400 is a step structure.
  • the width of this step structure is the outer boundary of the orthographic projection of the second via hole V2 in the second insulating layer 300 away from the opening of the substrate 100 on the substrate 100, and the width of the third via hole V3 in the third insulating layer 400.
  • FIG. 11 is a schematic diagram of an array substrate for forming a first via hole according to an embodiment of the present application.
  • the mixed gas of nitrogen trifluoride gas and oxygen can be used as the second etching gas to etch the first insulating layer 200 in the array substrate 000. So that the first via hole V1 connected with the second via hole V2 can be formed in the first insulation layer 200 .
  • the first insulating layer 200 is made of silicon nitride material, and the etching rate of the silicon nitride material of the second etching gas is greater than the etching rate of the silicon oxide material, usually the second etching gas has a negative impact on the silicon oxide material.
  • the longitudinal etch rate is approximately 11,000 angstroms per minute. Therefore, the time for etching the second via hole V1 formed by the first insulating layer 200 can be greatly shortened, further improving the manufacturing efficiency of the array substrate 00 . Furthermore, it can be ensured that the angle ⁇ 3 between the sidewall of the first via V1 in the first insulating layer 300 and the side of the first insulating layer 200 close to the substrate 100 is greater than or equal to 80° and less than 90°.
  • the first insulating layer 200 will not shrink relative to the photoresist pattern 111 , that is, the first insulating layer 200 will not shrink in the lateral direction. It is not easily etched away by the second etching gas. In this way, it can be ensured that the first via V1 in the first insulating layer 200 is away from the outer boundary of the orthographic projection of the opening of the substrate 100 on the substrate 100 and the second via V2 in the second insulating layer 300 is close to the substrate. The opening of the bottom 100 coincides with the outer boundary of the orthographic projection on the substrate 100 .
  • the thickness of the second insulating layer 300 in the embodiment of the present application can be adjusted, and after the thickness of the second insulating layer 300 is adjusted, the second overlapping via V20 is formed on the array substrate 000 by etching.
  • the etching time of the insulating layer is basically unchanged.
  • the shrinkage amount of the photoresist pattern 20 under the action of the etching gas that is, the first etching gas and the second etching gas
  • the width of the step structure in the second overlapping via hole V20 is also basically unchanged.
  • the size of the angle ⁇ 2 between the sidewall of the second via hole V2 in the second insulating layer 300 and the side of the second insulating layer 300 close to the substrate 100 is in a certain positive relationship with the thickness of the second insulating layer 300 . relationship.
  • the embodiments of this application take the following two situations as examples for description:
  • Figure 12 is an actual schematic diagram of a second overlapping via formed in an array substrate provided by an embodiment of the present application.
  • the angle ⁇ 2 between the sidewall of the second via hole V2 and the side of the second insulating layer 300 close to the substrate 100 is less than or equal to 50°.
  • Figure 13 is an actual schematic diagram of the second overlapping via hole formed in another array substrate according to the embodiment of the present application.
  • the angle ⁇ 2 between the sidewall of the second via hole V2 and the side of the second insulating layer 300 close to the substrate 100 is less than or equal to 30°.
  • the present application uses two etching gases with different etching properties (the first etching gas and the second etching gas) to form the first etching gas in the array substrate 000.
  • the etching rate of the second lap via V20 is faster. Therefore, compared with the first via hole formed after a long period of etching in the above description, in the embodiment of the present application, after a patterning process, the second overlapping via hole V20 formed in the GOA circuit 002 in the array substrate 000 No columnar compounds will appear.
  • the transfer electrode 600 located in the second overlapping via hole V20 is not prone to poor overlap, so that the transfer electrode 600 has a better overlapping effect with the first electrode 500, thereby ensuring that the GOA circuit 002 has different TFTs. The electrical connection between them is better.
  • the array substrate 000 may include: a substrate 100, a first insulating layer 200, a third insulating layer 400, a first electrode 500 and a transfer electrode 600.
  • the first insulating layer 200 and the third insulating layer 400 are sequentially stacked in a direction vertical and away from the substrate 100 .
  • the first insulation layer 200 has a first via hole V1
  • the third insulation layer 400 has a third via hole V3 connected with the first via hole V1.
  • the first via hole V1 and the third via hole V3 can constitute the second overlapping via hole V20 in the above embodiment.
  • the orthographic projection of the opening of the first via V1 away from the substrate 100 on the substrate 100 is located within the orthographic projection of the opening of the third via V3 close to the substrate 100 on the substrate 100 , and the first via V1
  • the outer boundary of the orthographic projection of the opening on the substrate 100 away from the substrate 100 does not coincide with the outer boundary of the orthographic projection of the opening of the third via V3 close to the substrate 100 on the substrate 100 .
  • the first insulating layer 200 will protrude from the third insulating layer 400.
  • the first electrode 500 is located on a side of the first insulating layer 200 close to the substrate 100 , and the orthographic projection of the first electrode 500 on the substrate 100 at least partially coincides with the orthographic projection of the first via V1 on the substrate 100 . In this way, at least part of the first electrode 500 is within the first via hole V1 in the first insulation layer 200 .
  • the first electrode 500 is the gate electrode of a certain TFT in the GOA circuit 001 in the above embodiment.
  • the transfer electrode 600 is located on a side of the third insulating layer 400 facing away from the substrate 100 . At least part of the transfer electrode 600 is located in the first via hole V1 and the third via hole V3 and overlaps with the first electrode 500 .
  • the first insulating layer 200 will protrude from the third insulating layer 400, and the first insulating layer 200 will protrude from the third insulating layer 400.
  • the portion of the layer 200 protruding from the third insulating layer 400 is a step structure. Therefore, after at least part of the transfer electrode 600 is located in the second overlapping via hole V20, part of the transfer electrode 600 can be located on this step structure. In this way, the transfer electrode 600 located in the second overlapping via hole V20 is less likely to be disconnected, thereby ensuring a better overlapping effect between the transfer electrode 600 and the first electrode 500 . In this way, it can be ensured that the electrical connection effect between different TFTs in the GOA circuit 002 is better, thereby making the display device equipped with the array substrate provided by the embodiment of the present application have a better display effect.
  • the first via V1 in the first insulating layer 200 is close to the outer boundary of the orthographic projection of the opening of the substrate 100 on the substrate 100
  • the third via V3 in the third insulating layer 400 is close to the substrate.
  • the distance h between the outer boundaries of the orthographic projection of the opening of the bottom 100 on the substrate 100 is the width of the step structure of the portion of the first insulating layer 200 protruding from the third insulating layer 400 .
  • the angle ⁇ between the sidewall of the third via hole V3 and the side of the third insulating layer 400 close to the substrate 100 is less than or equal to 45°.
  • the thickness of the third insulating layer 400 is 1000 angstroms to 4000 angstroms.
  • the angle ⁇ 1 between the side wall of the third via hole V3 and the side close to the substrate 100 Smaller, so that the portion of the transfer electrode 600 inside the first via hole V1 and outside the first via hole V1 is less likely to be disconnected.
  • the part of the side wall of the first via hole V1 in the first insulating layer 200 that is close to the third insulating layer 400 is an arc-shaped side wall 201.
  • the side wall of the first via V1 in the first insulating layer 200 is close to the partial arc shape of the third insulating layer 400
  • the sidewall 201, that is, the portion of the step structure close to the third insulating layer 400 is an arc-shaped sidewall 201.
  • the overlapping effect between the transfer electrode 600 and the first insulating layer 200 and the third insulating layer 400 in the second overlapping via hole V20 is better, thereby ensuring that the overlapping effect between the transfer electrode 600 and the first electrode 500 is better. good. In this way, the probability of disconnection of the transfer electrode 600 located in the second overlapping via hole V20 is further reduced.
  • the sidewall of the first via V1 in the first insulating layer 200 is sandwiched between the arc-shaped sidewall 201 of the third insulating layer 400 and the side of the first insulating layer 200 that is close to the substrate 100 .
  • the angle is less than or equal to 30°.
  • the angle between the arc-shaped sidewall 201 and the side of the first insulating layer 200 close to the substrate 100 is small. Therefore, at least part of the transfer electrode 600 easily overlaps with the arc-shaped sidewall 201 of the first via hole V1 in the first insulation layer 200 .
  • the transfer electrode 600 After at least part of the transfer electrode 600 is located in the second overlapping via hole V20, it is also possible to ensure that at least part of the transfer electrode 600 is in an arc shape with the first via hole V1 in the first insulation layer 200.
  • the side wall 201 has a good overlapping effect, which can ensure a good overlapping effect between the transfer electrode 600 and the first electrode 500 .
  • the sidewall of the first via V1 in the first insulating layer 200 also has a planar sidewall 202 located on the side of the arcuate sidewall 201 close to the substrate 100 , and the planar sidewall 202 is in contact with the first insulating layer 200
  • the angle ⁇ 3 between the surfaces close to the substrate 100 is greater than or equal to 80° and less than 90°.
  • the angle ⁇ 3 between the planar sidewall 202 of the first via hole V1 in the first insulating layer 200 and the side of the first insulating layer 200 close to the substrate 100 is relatively large.
  • the angle between the arc-shaped sidewall 201 of the first via hole V1 in the first insulating layer 200 and the side of the first insulating layer 200 close to the substrate 100 is small. Therefore, after at least part of the transfer electrode 600 is located in the second overlapping via hole V20, it can also be ensured that at least part of the transfer electrode 600 is connected to the plane side of the first via hole V1 in the first insulation layer 200.
  • the overlapping effect of the wall 202 is better, which can ensure a better overlapping effect between the transfer electrode 600 and the first electrode 500 .
  • both the first insulating layer 200 and the third insulating layer 400 are made of silicon nitride material.
  • FIG. 15 is a schematic diagram of another array substrate with a photoresist film provided by an embodiment of the present application.
  • the photoresist pattern 111 may be baked. After the baking process, the edge of the photoresist pattern 111 close to the opening V11 will collapse, so that the portion of the photoresist pattern 111 close to the opening V11 forms a certain slope angle.
  • the angle formed between the side of the baked photoresist pattern 111 close to the substrate 100 and the side of the opening V11 is less than or equal to 50°.
  • the baked photoresist pattern 111 has higher strength and is less likely to deform after being bombarded by the etching gas.
  • FIG. 15 schematically illustrates the photoresist film 111 having an opening portion as an example.
  • the etching gas can enter from the opening V11 and sequentially etch the third insulating layer 400 and the first insulating layer 200 . etching.
  • the angle formed between the side of the baked photoresist pattern 111 close to the substrate 100 and the side of the opening is less than or equal to 50°, therefore, the angle of the photoresist pattern 111 close to the opening V11
  • the lateral thickness of the part is small, so that the part of the photoresist pattern 111 close to the opening V11 is more likely to shrink under the action of the etching gas, thereby avoiding the subsequent shrinkage of the part of the photoresist pattern 111 close to the opening V11.
  • the problem of holes appearing on the side walls of the first via V1 and the third via V3 that is, the second overlapping via V20
  • the transfer electrode 600 formed in the circuit breaker may have a disconnection problem.
  • FIG. 16 is a schematic diagram of another array substrate for forming a third via hole according to an embodiment of the present application.
  • a mixed gas of sulfur hexafluoride gas and oxygen can be used as the first etching gas to etch the photoresist pattern 111 on the array substrate 000.
  • the third insulating layer 400 is etched so that a third via hole V3 connected to the opening V11 of the photoresist pattern 111 can be formed in the third insulating layer 400 .
  • FIG. 17 is a schematic diagram of another array substrate for forming first via holes according to an embodiment of the present application.
  • the mixed gas of nitrogen trifluoride gas and oxygen can be used as the second etching gas to etch the first insulating layer 200 in the array substrate 000. Therefore, the first via hole V1 connected to the third via hole V3 can be formed in the first insulating layer 200 .
  • the first insulating layer 200 is made of silicon nitride material, and the etching rate of the silicon nitride material of the second etching gas is relatively high, usually the longitudinal etching rate of the silicon oxide material by the second etching gas is about 11,000 Angstroms per minute. Therefore, the time for etching the second via hole V1 formed by the first insulating layer 200 can be greatly shortened, further improving the manufacturing efficiency of the array substrate 00 .
  • the first etching gas also has strong lateral etching ability, and the lateral etching ability of the second etching gas is weaker than the lateral etching ability of the first etching gas. Therefore, during the etching process of the third insulating layer 400 by the first etching gas, the third insulating layer 400 will shrink inward relative to the photoresist pattern 111, so that the opening formed in the third insulating layer 400 will be larger.
  • the portion of the first insulating layer 200 protruding from the third insulating layer 400 is a step structure.
  • the width of this step structure is the outer boundary of the orthographic projection of the first via hole V1 in the first insulating layer 200 close to the opening of the substrate 100 on the substrate 100, and the width of the third via hole V3 in the third insulating layer 400. The distance h between the outer boundaries of the orthographic projection on the substrate 100 of an opening close to the substrate 100 .
  • the portion of the first insulating layer 200 close to the third insulating layer 400 is not blocked by the photoresist pattern 111.
  • the second etching gas also has a strong bombardment effect. Therefore, the portion of the first insulating layer 200 close to the third insulating layer 400 that is not blocked by the photoresist pattern 111 will be strongly bombarded, causing the side of the first via V1 in the first insulating layer 200 to The portion of the wall close to the third insulating layer 400 is an arc-shaped side wall 201.
  • the sidewalls of the first via V1 in the first insulating layer 200 are close to the arc-shaped sidewalls 201 of the third insulating layer 400 and the first insulating layer 200 .
  • the included angle between the sides of the layer 200 close to the substrate 100 is less than or equal to 30°.
  • the portion of the first insulating layer 200 close to the third insulating layer 400 is bombarded by the second etching gas, the portion of the first insulating layer 200 close to the substrate 100 is protected. In this way, among the sidewalls of the first via hole V1 in the first insulating layer 200 , the portion close to the substrate 100 is the planar sidewall 202 . Moreover, due to the relatively large longitudinal etching rate of the silicon oxide material by the second etching gas, the angle between the planar sidewall 202 in the first insulating layer 200 and the side of the first insulating layer 200 close to the substrate 100 is relatively large. big.
  • the sidewall of the first via V1 in the first insulating layer 200 also has a planar sidewall 202 located on the side of the arcuate sidewall 201 close to the substrate 100 , and the planar sidewall 202 is close to the substrate in the first insulating layer 200
  • the angle ⁇ 3 between one side of 100 is greater than or equal to 80° and less than 90°.
  • FIG. 18 is an actual schematic diagram of a second overlapping via hole formed in yet another array substrate provided by an embodiment of the present application. Since this application uses two etching gases with different etching properties (the first etching gas and the second etching gas) to form the etching rate of the second overlapping via V20 in the array substrate 000 as shown in Figure 14 Faster. Therefore, compared with the first via hole formed after a long time of etching in the above description, in the embodiment of the present application, after a patterning process, the second overlapping via hole V20 formed in the GOA circuit 002 in the array substrate 000 No columnar compounds will appear.
  • the transfer electrode 600 located in the second overlapping via hole V20 is not prone to poor overlap, so that the transfer electrode 600 and the first electrode 500 have a better overlapping effect, thereby ensuring that the GOA circuit 002 has different TFTs.
  • the electrical connection between them is better.
  • Figure 19 is a schematic diagram of the film structure of yet another array substrate provided by an embodiment of the present application.
  • the array substrate 000 may include: a substrate 100, a first insulating layer 200, a second insulating layer 300, a third insulating layer 400, a fourth insulating layer 1000, a first electrode 500 and a transfer electrode 600.
  • the first insulating layer 200 , the second insulating layer 300 , the fourth insulating layer 1000 and the third insulating layer 400 are sequentially stacked in a direction vertical and away from the substrate 100 .
  • the first insulating layer 200 has a first via hole V1
  • the second insulating layer 300 has a second via hole V2 connected to the first via hole V1
  • the fourth insulating layer 1000 has a fourth via hole connected to the second via hole V2.
  • V4 the third insulating layer 400 has a third via hole V3 connected to the fourth via hole V4.
  • the first via hole V1, the second via hole V2, the fourth via hole V4, and the third via hole V3 can form the second overlapping via hole V20 in the above embodiment.
  • the fourth via hole V4 is away from the orthographic projection of the opening of the substrate 100 on the substrate 100, and is located within the orthographic projection of the third via hole V3 close to the opening of the substrate 100 on the substrate 100, and the fourth via hole V4
  • the outer boundary of the orthographic projection of the opening on the substrate 100 away from the substrate 100 does not coincide with the outer boundary of the orthographic projection of the opening of the third via V3 close to the substrate 100 on the substrate 100 .
  • the fourth insulating layer 1000 will protrude from the third insulating layer 400.
  • the second via V2 faces away from the orthographic projection of the opening of the substrate 100 on the substrate 100 and is located within the orthographic projection of the fourth via V4 close to the opening of the substrate 100 on the substrate 100 , and the second via V2 faces away from the substrate.
  • the outer boundary of the orthographic projection of the opening of the bottom 100 on the substrate 100 does not coincide with the outer boundary of the orthographic projection of the opening of the fourth via V4 close to the substrate 100 on the substrate 100 . In this way, in the through hole formed in the fourth via hole V4 and the second via hole V2, the second insulating layer 300 will protrude from the fourth insulating layer 1000.
  • the first electrode 500 is located on a side of the first insulating layer 200 close to the substrate 100 , and the orthographic projection of the first electrode 500 on the substrate 100 at least partially coincides with the orthographic projection of the first via V1 on the substrate 100 . In this way, at least part of the first electrode 500 is within the first via hole V1 in the first insulation layer 200 .
  • the first electrode 500 is the gate electrode of a certain TFT in the GOA circuit 001 in the above embodiment.
  • the transfer electrode 600 is located on a side of the third insulating layer 400 facing away from the substrate 100 , and at least part of the transfer electrode 600 is located on the first via hole V1 , the second via hole V2 , the fourth via hole V4 and the third via hole V3 inside and overlapped with the first electrode 500 .
  • the second insulating layer 300 will protrude. out of the fourth insulating layer 1000, and the fourth insulating layer 1000 will also protrude from the third insulating layer 400.
  • the part of the second insulating layer 300 protruding from the fourth insulating layer 1000 is the first step
  • the part of the fourth insulating layer 1000 protruding from the third insulating layer 400 is the second step.
  • the first step and the second step Steps can form a stepped structure.
  • part of the transfer electrode 600 can be located on this step structure.
  • the transfer electrode 600 located in the second overlapping via hole V20 is less likely to be disconnected, so that the overlap effect between the transfer electrode 600 and the first electrode 500 is better.
  • the first via V1 in the first insulation layer 200 is away from the outer boundary of the orthographic projection of the opening of the substrate 100 on the substrate 100 , and the second via V2 in the second insulation layer 300 is close to the substrate.
  • the opening of the bottom 100 coincides with the outer boundary of the orthographic projection on the substrate 100 .
  • redundant protrusions are easily generated at the position Q in the via hole in the array substrate.
  • the first insulating layer 200 is in the first via hole V1 and the second via hole V2 that are connected to each other.
  • the angle ⁇ 3 between the sidewall of the third via hole V3 and the side of the third insulating layer 400 close to the substrate 100 is less than or equal to 45°.
  • the thickness of the third insulating layer 400 is 1000 angstroms to 4000 angstroms.
  • the angle ⁇ 1 between the side wall of the third via hole V3 and the side close to the substrate 100 Smaller the transfer electrode 600 is less likely to be disconnected in the portions inside the first via hole V1 and outside the first via hole V1 .
  • both the fourth insulating layer 1000 and the second insulating layer 300 are made of SiOy material, and the film density of the fourth insulating layer 1000 is smaller than that of the second insulating layer 300 .
  • the material of the second insulating layer 300 and the fourth insulating layer 1000 is silicon oxide material.
  • the thickness of the second insulating layer 300 ranges from 500 angstroms to 700 angstroms.
  • the thickness of the second insulating layer 300 is greater than the thickness of the fourth insulating layer 1000 .
  • the film quality of the silicon oxide of the second insulating layer 300 is relatively dense.
  • the fourth insulating layer 1000 is usually located on the side of the TFT active layer in the GOA circuit 002 away from the substrate 100, and the TFT active layer in the GOA circuit 002 is not resistant to high temperatures, the temperature at which the fourth insulating layer 1000 is formed It is lower, so that the silicon oxide film quality of the fourth insulating layer 1000 is relatively loose. In this case, since the film quality of the fourth insulating layer 1000 is relatively loose compared to the film quality of the second insulating layer 300, the second insulating layer 300 and the third insulating layer in the second overlapping via hole V20 are formed. A step structure can be formed between the electrodes 400 to ensure a better overlapping effect between the transfer electrode 600 and the first electrode 500 .
  • the outer boundary of the orthographic projection of the opening of the second via V2 on the substrate 100 away from the substrate 100 is the same as the orthographic projection of the opening of the third via V3 on the substrate 100 close to the substrate 100 .
  • the distance h between the outer boundaries ranges from: 0.4 ⁇ m to 0.6 ⁇ m.
  • the second via hole V2 in the second insulating layer 300 is away from the outer boundary of the orthographic projection of the opening of the substrate 100 on the substrate 100
  • the third via hole V3 in the third insulating layer 400 is close to the substrate 100
  • the distance h between the outer boundaries of the orthographic projection of the opening on the substrate 100 is a step structure that can be composed of a first step and a second step.
  • the width of this step structure is the outer boundary of the orthographic projection of the second via hole V2 away from the opening of the substrate 100 on the substrate 100, and the width of the orthogonal projection of the third via hole V3 close to the opening of the substrate 100 on the substrate 100.
  • the angle ⁇ 2 between the sidewall of the second via hole V2 and the side of the second insulating layer 300 close to the substrate 100 is less than or equal to 50°.
  • the smaller the angle ⁇ 2 between the sidewall of the second via hole V2 in the second insulating layer 300 and the side of the second insulating layer 300 close to the substrate 100 the easier it is for the transfer electrode 600 to connect with the second insulating layer 300
  • the side walls of the second via hole V2 are overlapped, so that the transfer electrode 600 located in the second overlapping via hole V20 is less likely to be disconnected.
  • the angle ⁇ 3 between the sidewall of the first via V1 in the first insulating layer 200 and the side of the first insulating layer 200 close to the substrate 100 is greater than or equal to 80° and less than 90°. .
  • the angle ⁇ 3 between the sidewall of the first via hole V1 in the first insulating layer 200 and the side of the first insulating layer 200 close to the substrate 100 is relatively large.
  • the angle ⁇ 2 between the sidewall of the second via hole V2 in the second insulating layer 300 and the side of the second insulating layer 300 close to the substrate 100 is small.
  • the transfer electrode 600 After at least part of the transfer electrode 600 is overlapped with the side wall of the first via hole V1 in the first insulating layer 200 , it can also be ensured that at least part of the transfer electrode 600 is connected to the first insulating layer 200 .
  • the overlapping effect of the side walls of the first via V1 is better. In this way, the display effect of the display device equipped with the array substrate provided by the embodiment of the present application is better.
  • the first insulating layer 200 and the third insulating layer 400 are both made of silicon nitride material
  • the second insulating layer 300 and the fourth insulating layer 1000 are both made of silicon oxide material.
  • the silicon oxide density of the fourth insulating layer 1000 is smaller than the silicon oxide density of the second insulating layer 300 .
  • FIG. 20 is a schematic diagram of yet another array substrate with a photoresist film provided by an embodiment of the present application. It should be noted that for the process of forming the second overlapping via hole V20 shown in FIG. 19 in this application, for the detailed method of forming the photoresist pattern on the array substrate 000, please refer to the above embodiment for forming the photoresist pattern on the array substrate 000. The method of photoresist pattern will not be described in detail in this application.
  • FIG. 21 is a schematic diagram of yet another array substrate for forming a third via hole according to an embodiment of the present application.
  • a mixed gas of sulfur hexafluoride gas and oxygen can be used as the first etching gas to etch the photoresist pattern 111 on the array substrate 000.
  • the third insulating layer 400 is etched so that a third via hole V3 connected to the opening V11 of the photoresist pattern 111 can be formed in the third insulating layer 400 .
  • FIG. 22 is a schematic diagram of an array substrate for forming a fourth via hole and a second via hole according to an embodiment of the present application.
  • a mixed gas of nitrogen trifluoride gas and oxygen can be used as the second etching gas to etch the fourth insulating layer 1000 in the array substrate 000.
  • a fourth via hole V4 connected to the third via hole V3 can be formed in the fourth insulating layer 1000 .
  • the second etching gas has a faster etching rate on the fourth insulating layer 1000 made of silicon oxide material, and the fourth insulating layer 1000 is made of silicon oxide material with a relatively loose film quality. Therefore, the time for etching the fourth via V4 formed by the fourth insulating layer 1000 can be greatly shortened, further improving the manufacturing efficiency of the array substrate 000 .
  • the fourth insulating layer 1000 will not shrink relative to the photoresist pattern 111. That is, the fourth insulating layer 1000 will not shrink in the lateral direction. It is not easily etched by the second etching gas, so that after the fourth via hole V4 is formed in the fourth insulating layer 1000, the fourth insulating layer 1000 will protrude from the third insulating layer 400, and the second insulating layer 300 will protrude from the third insulating layer 400.
  • the part emerging from the third insulating layer 400 is the first step T1.
  • the width of this first step T1 is the outer boundary of the orthographic projection of the fourth via hole V4 in the fourth insulating layer 1000 away from the opening of the substrate 100 on the substrate 100, and the width of the third via hole V4 in the third insulating layer 400.
  • the hole V3 is close to the distance between the outer boundaries of the orthographic projection of the opening on the substrate 100 on the substrate 100 .
  • the mixed gas of nitrogen trifluoride gas and oxygen is still used as the second etching gas to etch the second insulating layer in the array substrate 000.
  • 300 is etched so that a second via hole V2 connected to the fourth via hole V4 can be formed in the second insulating layer 300 . Since the etching rate of the second insulating layer 300 made of silicon oxide material by the second etching gas is relatively fast, the time for etching the fourth via hole V4 formed by the fourth insulating layer 1000 can be greatly shortened. Further, The manufacturing efficiency of the array substrate 000 is improved.
  • the second insulating layer 300 will not shrink relative to the photoresist pattern 111. That is, the second insulating layer 300 will not shrink in the lateral direction. It is not easily etched by the second etching gas, so that after the second via hole V2 is formed in the second insulating layer 300, the fourth insulating layer 1000 will protrude from the second insulating layer 300, and the fourth insulating layer 1000 will protrude from the second insulating layer 300.
  • the part emerging from the second insulating layer 300 is the second step T2.
  • the width of this second step T2 is the outer boundary of the orthographic projection of the second via hole V2 away from the opening of the substrate 100 on the substrate 100, and is the same as the width of the fourth via hole V4 close to the opening of the substrate 100 on the substrate 100. The distance between the outer boundaries of orthographic projections.
  • the silicon oxide density of the fourth insulating layer 10000 is smaller than the silicon oxide density of the second insulating layer 300 . Therefore, during the etching process of the fourth insulating layer 1000 and the second insulating layer 300 by the second etching gas, the speed at which the fourth insulating layer 1000 shrinks inwards relative to the photoresist pattern 111 is faster than that of the second insulating layer 1000 . Layer 300 shrinks inward relative to photoresist pattern 111 relatively quickly. In this way, the fourth insulating layer 1000 will guide the portion of the second insulating layer 300 close to one side thereof, so that the width of the step structure composed of the first step T1 and the second step T2 is further increased.
  • the width of this step is the outer boundary of the orthographic projection of the opening of the second via hole V2 away from the substrate 100 on the substrate 100, and is the same as the orthographic projection of the opening of the third via hole V3 close to the substrate 100 on the substrate 100.
  • the distance between outer boundaries ranges h.
  • FIG. 23 is a schematic diagram of yet another array substrate for forming first via holes according to an embodiment of the present application.
  • the mixed gas of nitrogen trifluoride gas and oxygen can be used as the second etching gas to etch the first insulating layer 200 in the array substrate 000. Therefore, the first via hole V1 connected to the third via hole V3 can be formed in the first insulating layer 200 . It should be noted that for the process of forming the second overlapping via V20 shown in FIG.
  • the detailed method of forming the first via V1 in the first insulating layer 200 can be referred to the first via in the above embodiment.
  • the method of forming the first via hole V1 in the insulating layer 200 will not be described again in this application.
  • FIG. 24 is an actual schematic diagram of the second overlapping via hole formed in yet another array substrate according to the embodiment of the present application. Since this application uses two etching gases with different etching properties (the first etching gas and the second etching gas) to form the etching rate of the second overlapping via V20 in the array substrate 000 as shown in Figure 19 Faster. Therefore, compared with the first via hole formed after a long period of etching in the above description, in the embodiment of the present application, after a patterning process, the second overlapping via hole V20 formed in the GOA circuit 002 in the array substrate 000 No columnar compounds will appear.
  • the transfer electrode 600 located in the second overlapping via hole V20 is not prone to poor overlap, so that the transfer electrode 600 has a better overlapping effect with the first electrode 500, thereby ensuring that the GOA circuit 002 has different TFTs. The electrical connection between them is better.
  • FIG. 25 is an effect diagram of a transfer electrode overlapping in the second overlapping via hole according to an embodiment of the present application.
  • At least two interconnected via holes in at least two insulation layers in the array substrate 000 are used to form the second overlapping via hole V20.
  • the average height of the columnar compound on the side wall of the via hole V20 is smaller than the thickness of the transfer electrode.
  • the angle ⁇ 1 between the tangent line of the top of the columnar compound protrusion and the horizontal direction is smaller than the slope angle ⁇ 2 of the transfer electrode 600 .
  • the elements that make up the columnar compound include: carbon element, oxygen element, fluorine element, copper element, etc.
  • each sub-pixel 001 and the GOA circuit in the array substrate 000 are composed of a stacked film structure.
  • the array substrate 000 may include: a substrate 100, and a gate metal layer located on the substrate 100, a first insulating layer 200, a second insulating layer 300, an active layer pattern, a source and drain metal layer, a fourth Insulating layer 1000, organic insulating layer 1100, pixel electrode layer, third insulating layer 400 and common electrode layer.
  • the gate metal layer may include: the gate electrode 801 of the driving TFT in the sub-pixel 001, the gate electrode of the TFT in the GOA circuit 002, etc.
  • the first electrode 400 in the above embodiment belongs to the part within this gate metal layer.
  • the active layer pattern may include: the active layer 802 of the driving TFT in the sub-pixel 001, the active layer of the TFT in the GOA circuit 002, and the like.
  • the active layer is made of oxide semiconductor material.
  • the source and drain metal layers may include: the source electrode 803 and the drain electrode 804 of the driving TFT in the sub-pixel 001, and the source electrode and drain electrode of the TFT in the GOA circuit 002, etc.
  • the pixel electrode layer may include: a pixel electrode 900 electrically connected to the driving TFT in the sub-pixel 001.
  • the common electrode layer may include: the common electrode 1200 in the sub-pixel 001, the transfer electrode 600 in the GOA circuit 002, and so on. That is, the transfer electrode 600 in the non-display area and the common electrode 1200 in the sub-pixel 001 are formed through one patterning process.
  • the active layer pattern is made of an oxide semiconductor material, and the oxide semiconductor material is easily affected by ions (for example, hydrogen ions) in the surrounding film layer. Therefore, the second insulating layer 300 located on the side of the active layer pattern close to the substrate 100 and the fourth insulating layer 1000 located on the side of the active layer pattern away from the substrate 100 need to be made of silicon oxide materials with better insulation effects. become.
  • Other insulating layers (for example, the first insulating layer 200 and the third insulating layer 400) are made of silicon nitride material.
  • the array substrate 000 needs to be drilled before forming the pixel electrode to form a connection in the display area.
  • the pixel electrode 900 may be electrically connected to one of the source electrode and the drain electrode in the driving TFT through the connection via hole V30.
  • the second insulating layer 300, the fourth insulating layer 1000 and the second insulating layer 300 located near the first overlapping via V10 and the second overlapping via V20 in the non-display area 00b can be At least one of the organic insulating layers 1100 undergoes removal processing. For example, in FIG.
  • the fourth insulating layer 1000 and the fourth insulating layer 1000 near the first and second overlapping vias V10 and V20 in the non-display area 00b are The organic insulating layer 1100 undergoes removal processing.
  • the second insulating layer 300 and the fourth insulating layer 300 located near the first overlapping via V10 and the second overlapping via V20 in the non-display area 00b are The layer 1000 and the organic insulating layer 1100 are removed.
  • the organic insulating layer 1100 located near the first overlapping via hole V10 and the second overlapping via hole V20 in the non-display area 00 b is removed.
  • Embodiments of the present application also provide a method for manufacturing an array substrate.
  • the method for manufacturing an array substrate includes:
  • Step S1 Form a first electrode on the substrate.
  • Step S2 Form at least two insulating layers on the first electrode, and sequentially perform a first etching process and a second etching process on the at least two insulating layers to form at least two interconnected layers in the at least two insulating layers.
  • via holes the size of at least the first via hole closest to the substrate among the two via holes is smaller than the size of the other via holes;
  • Step S3 Form a transfer electrode on at least two insulating layers, so that the transfer electrode overlaps the first electrode through at least two via holes.
  • forming at least two insulating layers on the first electrode and sequentially performing a first etching process and a second etching process on the at least two insulating layers, including: sequentially forming a first insulating layer on the first electrode.
  • the connected first via hole wherein, the orthographic projection of the opening of the second via hole away from the substrate on the substrate is located within the orthographic projection of the opening of the third via hole close to the substrate on the substrate, and the second via hole
  • the outer boundary of the orthographic projection of the opening facing away from the substrate on the substrate does not coincide with the outer boundary of the orthographic projection of the third via hole close to the substrate on the substrate.
  • forming at least two insulating layers on the first electrode and sequentially performing a first etching process and a second etching process on the at least two insulating layers, including: sequentially forming a first insulating layer on the first electrode.
  • forming at least two insulating layers on the first electrode and sequentially performing a first etching process and a second etching process on the at least two insulating layers, including: sequentially forming a first insulating layer on the first electrode.
  • a first etching gas to perform a first etching process on the third insulating layer to form a third via hole in the third insulating layer
  • using a first etching gas sequentially performs a second etching process on the fourth insulating layer, the second insulating layer and the first insulating layer to form a fourth via hole connected to the third via hole in the fourth insulating layer.
  • a second via hole connected to the fourth via hole is formed in the insulating layer, and a first via hole connected to the second via hole is formed in the first insulating layer;
  • the orthographic projection of the opening of the fourth via hole facing away from the substrate on the substrate is located within the orthographic projection of the opening of the third via hole close to the substrate on the substrate, and the opening of the fourth via hole facing away from the substrate is within the orthogonal projection of the opening of the fourth via hole facing away from the substrate.
  • the outer boundary of the orthographic projection on the substrate does not coincide with the outer boundary of the orthographic projection on the substrate of the opening of the third via hole close to the substrate; the orthographic projection of the opening of the second via hole away from the substrate on the substrate is located at the third The opening of the four via holes close to the substrate is within the orthographic projection on the substrate, and the outer boundary of the orthogonal projection of the opening of the second via hole away from the substrate on the substrate is the same as the opening of the fourth via hole close to the substrate within the orthogonal projection of the substrate.
  • the outer boundaries of the orthographic projection on do not coincide.
  • the materials of the first insulating layer and the third insulating layer both contain silicon element and nitrogen element, and the material of the second insulating layer contains silicon element and oxygen element.
  • the materials of the first insulating layer and the third insulating layer include silicon element and nitrogen element.
  • the materials of the first insulating layer and the third insulating layer both contain silicon element and nitrogen element
  • the materials of the second insulating layer and the fourth insulating layer both contain silicon element and oxygen element.
  • the lateral etching ability of the first etching gas is stronger than the lateral etching ability of the second etching gas.
  • the first etching gas is: a mixed gas of at least one of sulfur hexafluoride, sulfur tetrafluoride, carbon tetrafluoride and nitrogen fluoride and oxygen.
  • the second etching gas is: a mixed gas of nitrogen trifluoride gas and oxygen.
  • An embodiment of the present application also provides a display panel.
  • the display panel may include: an array substrate and a color filter substrate arranged oppositely, and a liquid crystal layer located between them.
  • the array substrate may be the array substrate in the above embodiment. For example, it may be the array substrate shown in FIG. 6 . After the color filter substrate and the array substrate are connected to each other, the display panel can apply electrical signals to the array substrate so that the display panel can display images.
  • An embodiment of the present application also provides a display device.
  • the display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the display device may include: a driver chip and a display panel.
  • the display panel may be the display panel in the above embodiment.
  • it may include: the array substrate shown in FIG. 6, FIG. 14, or FIG. 19, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the two.
  • the driver chip is connected to the display panel and used to provide electrical signals to the display panel so that the display panel can display images.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
  • plurality refers to two or more than two, unless expressly limited otherwise.

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Abstract

本申请公开了一种阵列基板及其制造方法、显示面板，属于显示技术领域。阵列基板，包括：衬底，以及位于衬底上的第一电极、转接电极和至少两层绝缘层。由于至少两个过孔中最靠近衬底的第一过孔的尺寸小于其他过孔的尺寸，因此，在第二搭接过孔内可以形成台阶结构。如此，可以保证转接电极中的部分能够位于这个台阶结构上。这样，位于第二搭接过孔内的转接电极与各膜层的接触面积增大，不易出现断线的问题，使得转接电极和第一电极的搭接效果较好。

Description

阵列基板及其制造方法、显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板及其制造方法、显示面板。
背景技术
随着显示技术的不断发展，各种具有显示功能的产品出现在日常生活中，例如手机、平板电脑、电视机、笔记本电脑、数码相框和导航仪等，这些产品都无一例外的需要装配显示面板。
目前，大部分显示面板可以包括阵列基板、彩膜基板以及位于阵列基板与彩膜基板之间的液晶层。阵列基板具有显示区，以及位于显示区外围的非显示区。其中，显示区内设置有多个子像素，非显示区内设置有栅极驱动电路(英文：Gate Driver on Array，简称：GOA)。在显示面板需要进行画面显示时，需要通过GOA电路对显示区内设置的多个子像素进行控制。其中，GOA电路通常包括多个薄膜晶体管(英文：Thin Film Transistor；简称：TFT)，在这些TFT中，存在至少一个TFT的栅极需要与其他TFT的源极或漏极电连接。在TFT的栅极与其他TFT的源极或漏极之间进行电连接时，需要对阵列基板中的绝缘层进行打孔处理，并采用转接电极实现二者的电连接。
然而，转接电极在过孔内极易出现断线的问题，导致阵列基板上的GOA电路可能无法正常工作，进而导致显示面板的显示效果较差。
发明内容
本申请实施例提供了一种阵列基板及其制造方法、显示面板。可以解决现有技术的显示面板的显示效果较差的问题，所述技术方案如下：
第一方面，提供了一种阵列基板的制造方法，所述方法包括：
在衬底上形成第一电极；
在所述第一电极上形成至少两层绝缘层，并对所述至少两层绝缘层依次执 行第一刻蚀处理和第二刻蚀处理，以在所述至少两层绝缘层中形成至少两个相互连通的过孔，至少两个所述过孔中最靠近所述衬底的第一过孔的尺寸小于其他过孔的尺寸；
在所述至少两层绝缘层上形成转接电极，以使所述转接电极通过至少两个过孔与所述第一电极搭接。
可选的，在所述第一电极上形成至少两层绝缘层，并对所述至少两层绝缘层依次执行第一刻蚀处理和第二刻蚀处理，包括：
在所述第一电极上依次形成的第一绝缘层、第二绝缘层和第三绝缘层；
采用第一刻蚀气体对所述第三绝缘层进行第一刻蚀处理，以在所述第三绝缘层中形成第三过孔；
采用第二刻蚀气体依次对所述第二绝缘层和所述第三绝缘层进行第二刻蚀处理，以在所述第二绝缘层中形成与所述第三过孔连通的第二过孔，且在所述第一绝缘层中形成与所述第二过孔连通的第一过孔；
其中，所述第二过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。
可选的，在所述第一电极上形成至少两层绝缘层，并对所述至少两层绝缘层依次执行第一刻蚀处理和第二刻蚀处理，包括：
在所述第一电极上依次形成的第一绝缘层和第三绝缘层；
采用第一刻蚀气体对所述第三绝缘层进行第一刻蚀处理，以在所述第三绝缘层中形成第三过孔；
采用第二刻蚀气体对所述第一绝缘层进行第二刻蚀处理，以在所述第一绝缘层中形成与所述第三过孔连通的第一过孔；
其中，所述第一过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第一过孔靠近所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。
可选的，在所述第一电极上形成至少两层绝缘层，并对所述至少两层绝缘层依次执行第一刻蚀处理和第二刻蚀处理，包括：
在所述第一电极上依次形成的第一绝缘层、第二绝缘层、第四绝缘层和第三绝缘层；
采用第一刻蚀气体对所述第三绝缘层进行第一刻蚀处理，以在所述第三绝缘层中形成第三过孔；
采用第二刻蚀气体依次对所述第四绝缘层、所述第二绝缘层和所述第一绝缘层进行第二刻蚀处理，以在所述第四绝缘层中形成与第三过孔连通的第四过孔，在所述第二绝缘层中形成与所述第四过孔连通的第二过孔，且在所述第一绝缘层中形成与所述第二过孔连通的第一过孔；
其中，所述第四过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第四过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合；所述第二过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第四过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第四过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。
可选的，所述第一绝缘层和所述第三绝缘层的材料均包含硅元素和氮元素，所述第二绝缘层的材料包含硅元素和氧元素。
可选的，所述第一绝缘层和所述第三绝缘层的材料包含硅元素和氮元素。
可选的，所述第一绝缘层和所述第三绝缘层的材料均包含硅元素和氮元素，所述第二绝缘层和所述第四绝缘层的材料均包含硅元素和氧元素
可选的，所述第一刻蚀气体对所述第三绝缘层的横向刻蚀能力强于所述第二刻蚀气体对所述第一绝缘层的横向刻蚀能力。
可选的，所述第一刻蚀气体为：六氟化硫、四氟化硫，四氟化碳和氟化氮中的至少一种气体与所述氧气的混合气体。
可选的，所述第二刻蚀气体为：三氟化氮气体和氧气的混合气体。
第二方面，提供了一种阵列基板，其特征在于，包括：
衬底；
在衬底上设置的第一电极、转接电极和至少两层绝缘层，所述第一电极位于所述至少两层绝缘层靠近所述第一电极的一侧，所述转接电极位于所述至少 两层绝缘层背离所述衬底的一侧；
其中，所述至少两层绝缘层具有至少两个相互连通的过孔，至少两个所述过孔中最靠近所述衬底的第一过孔的尺寸小于其他过孔的尺寸，所述转接电极通过至少两个过孔与所述第一电极搭接。
可选的，所述至少两层绝缘层包括：沿垂直且远离所述衬底的方向依次设置的第一绝缘层、第二绝缘层和第三绝缘层，所述第一绝缘层具有第一过孔，所述第二绝缘层具有与所述第一过孔连通的第二过孔，所述第三绝缘层具有与所述第二过孔连通的第三过孔；
其中，所述第二过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。
可选的，所述第一过孔背离所述衬底的开口在所述衬底上的正投影的外边界，与所述第二过孔靠近所述衬底的开口在所述衬底上的正投影的外边界重合。
可选的，所述第三过孔的侧壁与所述第三绝缘层中靠近所述衬底一面之间的夹角小于60°。
可选的，所述第三过孔的侧壁与所述第三绝缘层中靠近所述衬底一面之间的夹角小于或等于45°。
可选的，所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界，与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界之间的距离范围为：0.2微米至0.5微米。
可选的，所述第二绝缘层的厚度的范围为500埃至1000埃，所述第二过孔的侧壁与所述第二绝缘层中靠近所述衬底一面之间的夹角大于或等于30°，且小于或等于50°。
可选的，所述第二绝缘层的厚度的范围为200埃至500埃，所述第二过孔的侧壁与所述第二绝缘层中靠近所述衬底一面之间的夹角小于或等于30°。
可选的，所述第一过孔的侧壁与所述第一绝缘层中靠近所述衬底一面之间的夹角大于或等于80°，且小于90°。
可选的，所述至少两层绝缘层包括：沿垂直且远离所述衬底的方向依次设置的第一绝缘层和第三绝缘层，所述第一绝缘层具有第一过孔，所述第三绝缘 层具有与所述第一过孔连通的第三过孔；
其中，所述第一过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第一过孔靠近所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。可选的，所述第一过孔的侧壁靠近所述第三绝缘层的部分为弧形侧壁。可选的，所述弧形侧壁与所述第一绝缘层中靠近所述衬底一面之间的夹角小于或等于30°。
可选的，所述第一过孔的侧壁还具有位于所述弧形侧壁靠近所述衬底一侧平面侧壁，所述平面侧壁与所述第一绝缘层中靠近所述衬底一面之间的夹角大于或等于80°，且小于90°。
可选的，所述至少两层绝缘层包括：沿垂直且远离所述衬底的方向依次设置的第一绝缘层、第二绝缘层、第四绝缘层和第三绝缘层，所述第一绝缘层具有第一过孔，所述第二绝缘层具有与所述第一过孔连通的第二过孔，所述第四绝缘层具有与所述第二过孔连通的第四过孔，所述第三绝缘层具有与所述第四过孔连通的第三过孔；
其中，所述第四过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第四过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合；所述第二过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第四过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第四过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。
可选的，所述第二绝缘层和所述第四绝缘层的材料均包含硅元素和氧元素，且所述第四绝缘层的材料中的硅元素和氧元素的分布密度小于所述第二绝缘层的材料中的硅元素和氧元素的分布密度。
可选的，所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界，与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界之间的距离范围为：0.4微米至0.6微米。
可选的，所述阵列基板还包括：位于所述至少两层绝缘层中的两层相邻的 绝缘层之间的第二电极，所述至少两层绝缘层还具有第一搭接过孔，所述转接电极通过所述第一搭接过孔与所述第二电极搭接。
可选的，所述至少两层绝缘层中的至少两个相互连通的过孔用于组成第二搭接过孔，所述第二搭接过孔的侧壁上具有多个柱状化合物，所述柱状化合物的平均高度小于所述转接电极的厚度。可选的，所述柱状化合物凸起顶端切线与水平方向的夹角小于所述转接电极的坡度角。可选的，组成所述柱状化合物的元素包括：碳元素、氧元素、氟元素和铜元素。
第三方面，提供了一种显示面板，包括：相对设置的阵列基板和彩膜基板，所述阵列基板上述第二方面所述的阵列基板。
本申请实施例提供的技术方案带来的有益效果至少包括：
一种阵列基板，包括：衬底，以及位于衬底上的第一电极、转接电极和至少两层绝缘层。由于至少两个过孔中最靠近衬底的第一过孔的尺寸小于其他过孔的尺寸，因此，在第二搭接过孔内可以形成台阶结构。如此，可以保证转接电极中的部分能够位于这个台阶结构上。这样，位于第二搭接过孔内的转接电极与各膜层的接触面积增大，不易出现断线的问题，使得转接电极和第一电极的搭接效果较好。这样，可以保证GOA电路不同TFT之间的电连接效果较好，进而使得装配有本申请实施例提供的阵列基板的显示装置的显示效果较好。此外，通过分步刻蚀的工艺，可控制各膜层的坡度角和结构，以及控制柱状化合物的尺寸，从而提高显示面板的良率和耐电流性。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种阵列基板的平面示意图；
图2是图1示出的阵列基板在A-A’处的膜层结构示意图；
图3是一种长时间刻蚀后过孔内部的截面扫描电镜图；
图4是一种带有第一过孔的绝缘层的膜层结构示意图；
图5是本申请实施例提供的一种阵列基板的平面示意图；
图6是图5示出的阵列基板在A-A’处的膜层结构示意图；
图7是本申请实施例提供的一种阵列基板的膜层结构示意图；
图8是本申请实施例提供的一种具有光刻胶薄膜的阵列基板的示意图；
图9是本申请实施例提供的一种形成第三过孔的阵列基板的示意图；
图10是本申请实施例提供的一种形成第二过孔的阵列基板的示意图；
图11是本申请实施例提供的一种形成第一过孔的阵列基板的示意图；
图12是本申请实施例提供的一种阵列基板内形成的第二搭接过孔的截面扫描电镜图；
图13是本申请实施例提供的另一种阵列基板内形成的第二搭接过孔的截面扫描电镜图；
图14是本申请实施例提供的另一种阵列基板的膜层结构示意图；
图15是本申请实施例提供的另一种具有光刻胶薄膜的阵列基板的示意图；
图16是本申请实施例提供的另一种形成第三过孔的阵列基板的示意图；
图17是本申请实施例提供的另一种形成第一过孔的阵列基板的示意图；
图18是本申请实施例提供的又一种阵列基板内形成的第二搭接过孔的截面扫描电镜图；
图19是本申请实施例提供的又一种阵列基板的膜层结构示意图；
图20是本申请实施例提供的又一种具有光刻胶薄膜的阵列基板的示意图；
图21是本申请实施例提供的又一种形成第三过孔的阵列基板的示意图；
图22是本申请实施例提供的一种形成第四过孔和第二过孔的阵列基板的示意图；
图23是本申请实施例提供的又一种形成第一过孔的阵列基板的示意图；
图24是本申请实施例提供的再一种阵列基板内形成的第二搭接过孔的截面扫描电镜图；
图25是本申请实施例提供的一种转接电极在第二搭接过孔内搭接的效果图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
请参考图1，图1是一种阵列基板的平面示意图。阵列基板00具有显示区0a，以及位于显示区0a外围的非显示区0b。其中，显示区0a内设置有多个子像素(图中未标注)，非显示区0b内设置有GOA电路0b1。这里，阵列基板00在装配到显示装置内后，阵列基板00可以通过GOA电路0b1，对显示区0a内设置的多个子像素进行控制，以使显示装置能够显示画面。
为了更清楚看到该阵列基板00的膜层结构，请参考图2，图2是图1示出的阵列基板在A-A’处的膜层结构示意图。阵列基板可以包括：衬底01，以及位于衬底01上层叠设置的TFT 02、第一钝化层03、有机绝缘层04、像素电极05、第二钝化层06和公共电极07。
其中，TFT 02可以包括：栅极021、有源层024、源极023和漏极022。该源极023与漏极022均与有源层024搭接，且有源层024和栅极021之间通过栅极绝缘层025绝缘。像素电极05可以通过连接过孔V00与TFT 02中的源极024和漏极025中的一个电连接。栅极绝缘层025具有第一栅极绝缘层0251和第二栅极绝缘层0252，且第一栅极绝缘层0251相比于第二栅极绝缘层0252更靠近有源层图案024。由于有源层图案024通常是由多晶硅或氧化物半导体制成的，且有源层图案024容易受周围膜层中的离子(例如，氢离子)的影响，因此，栅极绝缘层025中第一栅极绝缘层0251与第一钝化层03均可以由绝缘效果更好的氧化硅材料制成。这里，第二栅极绝缘层0252与第二钝化层06均可以由氮化硅材料制成。
阵列基板00的非显示区0b内的GOA电路0b1通常也包括多个TFT，且这些TFT可以与显示区0a内的TFT 02同层设置。由于在GOA电路0b1中，存在至少一个TFT的栅极08需要与其他TFT的源极或漏极09电连接。因此，通常需要对阵列基板00中的多个绝缘层进行打孔处理，并且采用与公共电极07同层设置的转接电极010让一个TFT的栅极08和另一个TFT的源极或漏极09进行搭接。这样，GOA电路0b1能够对显示区0a内设置的多个子像素进行控制，使得阵列基板00在集成在显示装置内后显示装置能够正常显示画面。这里，通常采用一次构图工艺，对GOA电路0b1中的多个绝缘层进行打孔处理，以在阵列基板00内形成第一过孔V01和第二过孔V02，转接电极010可以通过第一搭接过孔V01与一个TFT的栅极08搭接，且可以通过第二过孔V02与另一个TFT的源极或漏极09进行搭接。需要说明的是，在形成显示区0a内的连接过孔V00 的过程中，通常也会将位于非显示区0b内的第一钝化层03和有机绝缘层04去除。为此，在形成第一过孔V01的过程中，需要同时对第一栅极绝缘层0251、第二栅极绝缘层0252和第二钝化层06进行刻蚀处理；在形成第二过孔V02的过程中，仅需要对第二钝化层06进行刻蚀处理。而需要刻蚀的绝缘层的厚度越大，在这个绝缘层内形成的过孔越容易出现不良问题。因此，下文将以在形成第一过孔V01的过程中可能存在的问题为例说明。
由于第一栅极绝缘层0251由氧化硅材料制成，而对氧化硅材料进行打孔处理时，刻蚀气体对二氧化硅的刻蚀速率较慢。因此，在形成第一过孔V01的过程中，由氧化硅材料制成的第一栅极绝缘层0251的刻蚀的时间较长，导致阵列基板00的制造效率较低。
并且，请参考图3，图3是一种长时间刻蚀后过孔内部的截面扫描电镜图。从微观形貌可看到，在经过长时间刻蚀过程中，可能会产生含碳副产物(例如，CH 2、CF 2、COF等)，这些含碳副产物可能会与金属表面的Cu粒子结合，进而会在第一过孔V01的内壁上会形成柱状化合物011。这样，在采用转接电极010通过该第一过孔V01与TFT的栅极08进行搭接时，第一过孔V01的内壁上的柱状化合物011会让位于第一过孔V01内的转接电极010出现搭接不良的情况，进而导致转接电极010与TFT的栅极08搭接效果较差。如此，过孔内壁的柱状化合物011会导致GOA电路0b1可能无法工作，进而导致显示装置的显示效果较差。
此外，请参考图2和4，图4是一种带有第一过孔的绝缘层的膜层结构示意图。在形成第一过孔V01的过程中，由于刻蚀气体对第二钝化层06的纵向刻蚀能力较强，且对第二钝化层06的横向刻蚀能力较弱。因此，第二钝化层06的坡度角α较大，例如，第二钝化层06的坡度角α通常大于60°。这样，转接电极010中位于第一过孔V01外的部分与位于第一过孔V01内的部分之间极易出现断线的问题。同时，在采用同一种刻蚀气体对多个绝缘层进行刻蚀以形成第一过孔V01的过程中，由氮化硅材料制成的第二栅极绝缘层0252的刻蚀速率，大于由氧化硅材料制成的第一栅极绝缘层0251的刻蚀速率，因此，第一过孔V01内第二栅极绝缘层0252靠近第一栅极绝缘层0251的位置Q处容易产生凸起。这样，当位于第一过孔V01内的转接电极010在位置Q处也容易出现断线的问题，进而导致公共电极07与TFT的栅极08搭接效果较差。在转接电极010 出现断线问题后，也可能会导致GOA电路0b1无法工作。
在对本申请实施例提供的阵列基板的结构原理进行说明之前，先对本申请实施例提供的阵列基板所涉及到的使用场景进行说明。请参考图5和图6，图5是本申请实施例提供的一种阵列基板的俯视图，图6是图5示出的阵列基板在A-A’处的膜层结构示意图。阵列基板000具有显示区00a，以及位于显示区00a外围的非显示区00b。显示区00a内分布有多个阵列排布的子像素001，非显示区00b内分布有GOA电路002。其中，GOA电路002可以与各个子像素001中的驱动TFT的栅极电连接，使得GOA电路002能够驱动各个子像素001内的驱动TFT工作。
其中，GOA电路002可以包含有与各个子像素001内的驱动TFT同层设置的多个TFT，在GOA电路002中的多个TFT中，存在一个TFT的栅极(也即后文中的第一电极500)需要与另一个TFT的源极和漏极中的一个(也即后文中的第二电极700)电连接的情况。由于阵列基板000中通常包含多个绝缘层，因此，在需要第一电极500与第二电极700搭接时，需要在位于非显示区00b内的绝缘层中形成第一搭接过孔V10和第二搭接过孔V20。示例的，阵列基板000内的第一搭接过孔V10与第二搭接过孔V20通常均是基于一次构图工艺形成的。示例的，首先，可以在形成有绝缘层的阵列基板000上涂覆光刻胶薄膜；之后，对阵列基板000上涂覆的光刻胶薄膜执行一次曝光和显影即可得到光刻胶图案；然后，采用干法刻蚀对阵列基板000中没有附着光刻胶图案的部分进行刻蚀；最后，将阵列基板000上的光刻胶进行剥离，即可在阵列基板000中的非显示区00b内形成第一搭接过孔V10和第二搭接过孔V20。
其中，第一电极500中的至少部分需要位于第二搭接过孔V20内，而第二电极700中的至少部分需要位于第一搭接过孔V10内，并让转接电极600在第二搭接过孔V20内与第一电极500搭接，且在第一搭接过孔V10内与第二电极700搭接。这样，通过转接电极600可以实现第一电极500与第二电极700的搭接。
需要说明的是，由于第一电极500属于阵列基板000内的栅极金属层，第二电极700属于阵列基板000内的源漏极金属层，且栅极金属层相对于源漏极金属层更靠近阵列基板000中的衬底100，转接电极600所在的导电层通常位于 阵列基板000的最外侧。因此，转接电极600与第一电极500之间的绝缘层的厚度，大于转接电极600与第二电极700之间的绝缘层的厚度，也即，在阵列基板000内形成的第二搭接过孔V20的深度大于第一搭接过孔V10的深度。又由于深度越大的搭接过孔，在形成过程中越容易出现不良问题，而本申请实施例提供的阵列基板000内的第二搭接过孔V20出现不良问题的概率较低。因此，以下实施例将着重对深度较大的第二搭接过孔V20的结构原理和形成过程进行说明。
本申请实施例提供了一种阵列基板，该阵列基板可以包括：衬底；在衬底上设置的第一电极、转接电极和至少两层绝缘层，第一电极位于至少两层绝缘层靠近第一电极的一侧，转接电极位于至少两层绝缘层背离衬底的一侧。
其中，至少两层绝缘层具有至少两个相互连通的过孔，至少两个过孔中最靠近衬底的第一过孔的尺寸小于其他过孔的尺寸，转接电极通过至少两个过孔与第一电极搭接。
其中，至少两层绝缘层内的至少两个相互连通的过孔用于组成第二搭接过孔。由于至少两个过孔中最靠近衬底的第一过孔的尺寸小于其他过孔的尺寸。示例的，可以采用两种刻蚀气体分布对至少两层绝缘层进行刻蚀处理，进而可以在至少两层绝缘层中形成尺寸和不同的过孔。因此，在第二搭接过孔内可以形成台阶结构。如此，可以保证转接电极中的部分能够位于这个台阶结构上。这样，位于第二搭接过孔内的转接电极与各膜层的接触面积增大，不易出现断线的问题，使得转接电极和第一电极的搭接效果较好。这样，可以保证GOA电路不同TFT之间的电连接效果较好，进而使得装配有本申请实施例提供的阵列基板的显示装置的显示效果较好。
在本申请中，由于阵列基板中的至少两层绝缘层的配合方式有多种，因此，本申请实施例将以下述三种可选的实现方式为例进行说明：
第一种可选的实现方式，请参考图7，图7是本申请实施例提供的一种阵列基板的膜层结构示意图。该阵列基板000可以包括：衬底100、第一绝缘层200、第二绝缘层300、第三绝缘层400、第一电极500和转接电极600。
第一绝缘层200、第二绝缘层300和第三绝缘层400沿垂直且远离衬底100 的方向依次层叠设置。第一绝缘层200具有第一过孔V1，第二绝缘层300具有与第一过孔V1连通的第二过孔V2，第三绝缘层400具有与第二过孔V2连通的第三过孔V3。这里，第一过孔V1、第二过孔V2与第三过孔V3即可组成上述实施例中的第二搭接过孔V20。
其中，第二过孔V2背离衬底100的开口在衬底100上的正投影，位于第三过孔V3靠近衬底100的开口在衬底100上的正投影内，且第二过孔V2背离衬底100的开口在衬底100上的正投影的外边界与第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界不重合。这样，在第一过孔V1、第二过孔V2与第三过孔V3组成的第二搭接过孔V20内，第二绝缘层300会凸出于第三绝缘层400。需要说明的是，本申请实施例中的某个开口在衬底100上的正投影的外边界是指：这个开口在衬底100上的正投影的轮廓边框。
第一电极500位于第一绝缘层200靠近衬底100的一侧，第一电极500在衬底100上的正投影与第一过孔V1在衬底100上的正投影至少部分重合。这样，第一电极500中的至少部分在第一绝缘层200中的第一过孔V1内。这里，第一电极500即为上述实施例中的GOA电路001内的某个TFT的栅极。
转接电极600位于第三绝缘层400背离衬底100的一侧，转接电极600中的至少部分位于第一过孔V1、第二过孔V2和第三过孔V3内，且与第一电极500搭接。
在本申请实施例中，由于在第一过孔V1、第二过孔V2与第三过孔V3组成的第二搭接过孔V20内，第二绝缘层300会凸出于第三绝缘层400，且第二绝缘层300凸出于第三绝缘层400的部分即为台阶结构。因此，在将转接电极600中的至少部分位于第二搭接过孔V20内后，转接电极600中的部分能够位于这个台阶结构上。这样，位于第二搭接过孔V20内的转接电极600与各膜层的接触面积增大，不易出现断线的问题，使得转接电极600和第一电极500的搭接效果较好。如此，可以保证GOA电路002不同TFT之间的电连接效果较好，进而使得装配有本申请实施例提供的阵列基板的显示装置的显示效果较好。
在本申请中，第一绝缘层200中的第一过孔V1背离衬底100的开口在衬底100上的正投影的外边界，与第二绝缘层300中的第二过孔V2靠近衬底100的开口在衬底100上的正投影的外边界重合。这里，相比于上述描述中阵列基板中的过孔内位置Q处容易产生多余凸起，本申请实施例，在相互连通的第一过 孔V1和第二过孔V2中第一绝缘层200和第二绝缘层300接触的位置不存在多余凸起，使得转接电极600与第一绝缘层200和第二绝缘层300的搭接效果较好。如此，进一步的降低了位于第二搭接过孔V20内的转接电极600出现断线的问题的概率。
在本申请实施例中，第三过孔V3的侧壁与第三绝缘层400中靠近衬底100一面之间的夹角γ1小于60°。优选的，第三过孔V3的侧壁与第三绝缘层400中靠近衬底100一面之间的夹角γ1小于或等于45°。这里，第三绝缘层400的厚度为1000埃至4000埃。相比于上述描述中阵列基板中的第二钝化层06的坡度角α较大，本申请实施例中，第三过孔V3的侧壁与靠近衬底100一面之间的夹角γ1较小，使得转接电极600在第一过孔V1内和第一过孔V1外的部分不容易出现断线的问题。如此，当转接电极600与第三过孔V3进行搭接时，第三过孔V3的侧壁与第三绝缘层400中靠近衬底100一面之间的夹角γ1较小，使得转接电极600与第三过孔V3的搭接效果较好，进而使得装配有本申请实施例提供的阵列基板的显示装置的显示效果较好。
在本申请中，第二绝缘层300中的第二过孔V2背离衬底100的开口在衬底100上的正投影的外边界，与第三绝缘层400中的第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界之间的距离范围h为：0.2微米至0.5微米。这里，第二绝缘层300中的第二过孔V2背离衬底100的开口在衬底100上的正投影的外边界，与第三绝缘层400中的第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界之间的距离h，即为第二绝缘层300凸出于第三绝缘层400的台阶结构的宽度。当台阶结构的宽度的范围为0.2微米至0.5微米时，可使转接电极600中的至少部分位于第二搭接过孔V20内且同时落在台阶结构上，可以进一步的降低位于第二搭接过孔V20内的转接电极600出现断线的问题的概率。
在本申请实施例中，第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2和第二绝缘层300的厚度存在一定的相关关系。在本申请一些实施例中，夹角γ2的角度大于或等于30°，且小于或等于50°；在其他一些实施例中，夹角γ2的角度小于或等于30°。示例的，当第二绝缘层300的厚度的范围为500埃至1000埃时，第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2小于或等于50°；或者，当第二绝缘层300的 厚度的范围为200埃至500埃时，第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2小于或等于30°。在这种情况下，第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2和第二绝缘层300存在一定的相关关系，但通过控制第二绝缘层300的厚度可以保证第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2较小。如此，当转接电极600与第二过孔V2进行搭接时，转接电极600与第二绝缘层300中的第二过孔V2的侧壁的搭接效果较好，也即是位于第二搭接过孔V20内的转接电极600不易出现断线的问题。需要说明的是，第二绝缘层300中的第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2越小，转接电极600越容易与第二绝缘层300中的第二过孔V2的侧壁进行搭接，使得位于第二搭接过孔V20内的转接电极600越不易出现断线的问题。
在本申请中，第一绝缘层200中的第一过孔V1的侧壁与第一绝缘层200中靠近衬底100一面之间的夹角γ3大于或等于80°，且小于90°。这里，尽管第一绝缘层200中的第一过孔V1的侧壁与第一绝缘层200中靠近衬底100一面之间的夹角γ3较大。但是，由于第二绝缘层300中的第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2较小，且第三过孔V3的侧壁与靠近衬底100一面之间的夹角γ1也较小。因此，在将转接电极600中的至少部分与第一绝缘层200中的第一过孔V1的侧壁进行搭接后，也能够保证转接电极600中的至少部分与第一绝缘层200中的第一过孔V1的侧壁的搭接效果较好。如此，进而使得装配有本申请实施例提供的阵列基板的显示装置的显示效果较好。
在本申请实施例中，第一绝缘层200和第三绝缘层400均由SiNx(x>0材料制成，第二绝缘层300由SiOy(y>0)材料制成。需要说明的是，SiNx指的是如下物质：在组成方面包含氮元素，且在浓度范围上，在包含10原子％至50原子％的硅、5原子％至25原子％的氢的范围中，以使总和成为100原子％的方式且以任意浓度包含各元素。SiOy指的是如下物质：在组成方面包含氧元素，且在浓度范围上，在包含10原子％至50原子％的硅、1原子％至25原子％的氢的范围中，以使总和成为100原子％的方式且以任意浓度包含各元素。在一些实施例中，第一绝缘层200和第三绝缘层400包含氮化硅材料，第二绝缘层300包含氧化硅材料。
以下实施例将对形成图7示出的第二搭接过孔V20的过程进行详细说明：
对于阵列基板000上形成光刻胶图案的方式。请参考图8，图8是本申请实施例提供的一种具有光刻胶薄膜的阵列基板的示意图。在形成有第一绝缘层200、第二绝缘层300和第三绝缘层400的阵列基板000上形成光刻胶图案111后，可以对光刻胶图案111进行烘烤处理。经过烘烤处理后光刻胶图案111中靠近开孔V11的边缘会塌陷，使得光刻胶图案111中靠近开孔V11的部分形成一定的坡度角。示例的，通过控制烘烤工艺处理，使得光刻胶图案111中靠近衬底100的一面与开孔V11的侧面之间形成的角度小于或等于50°。需要说明的是，经过烘烤处理的光刻胶图案111的强度较高，其在受到刻蚀气体的轰击作用后不易产生变形。这里，图6是以光刻胶薄膜111具有一个开孔部分为例进行示意性说明的。在这种情况下，后续在对第三绝缘层400、第二绝缘层300和第一绝缘层层200进行刻蚀时，刻蚀气体可以从开孔V11进入并依次对第三绝缘层400、第二绝缘层300和第一绝缘层200进行刻蚀。并且，由于经过烘烤处理后的光刻胶图案111中靠近衬底100的一面与开孔部分的侧面之间形成的角度小于或等于50°，因此，光刻胶图案111中靠近开孔V11部分的横向厚度较小，使得光刻胶图案111中靠近开孔V11部分更容易在刻蚀气体的作用下内缩，进而可以避免后续因光刻胶图案111中靠近开孔V11部分内缩较慢，而在第一过孔V1、第二过孔V2和第三过孔V3(也即第二搭接过孔V20)的侧壁上出现孔洞的不良问题，从而可以进一步的降低后续在第二搭接过孔V20内形成的转接电极600出现断线问题的概率。
对于在第三绝缘层400内形成第三过孔V3的方式。请参考图9，图9是本申请实施例提供的一种形成第三过孔的阵列基板的示意图。在阵列基板000上形成光刻胶图案111，且对这个光刻胶图案111进行烘烤处理后，可以采用六氟化硫、四氟化硫，四氟化碳和氟化氮中的至少一种气体与所述氧气的混合气体作为第一刻蚀气体，对阵列基板000上的第三绝缘层400进行刻蚀，以使第三绝缘层400内能够形成与光刻胶图案111的开孔V11连通的第三过孔V3。由于第三绝缘层400是由氮化硅材料制成的，且第一刻蚀气体对氮化硅材料的刻蚀速率较快，通常第一刻蚀气体对氮化硅材料的纵向刻蚀速率会大于10000埃每分钟。因此，可以缩短刻蚀第三绝缘层400形成的第三过孔V3时间，进而可以提高阵列基板00的制造效率。
又由于第二绝缘层300是由氧化硅材料制成的，而第一刻蚀气体对氧化硅材料的刻蚀速度较慢。因此，当采用第一刻蚀气体将第三绝缘层400纵向刻蚀完成后，尽管第一刻蚀气体会刻蚀到第二绝缘层300，也不会对第二绝缘层300造成很大的影响。并且，由于第一刻蚀气体还具有较强的横向刻蚀能力。因此，通过第一刻蚀气体对第三绝缘层400刻蚀过程中，第三绝缘层400会相对于光刻胶图案111向内缩，使得第三绝缘层400内形成的开口较大的第三过孔V3。也即是，光刻胶图案111的开孔V11在衬底100上的正投影会位于第三过孔V3在衬底100上的正投影内。并且，当第一刻蚀气体对第三绝缘层400的横向刻蚀能力较强时，还可以保证第三绝缘层400中的第三过孔V3的侧壁与第三绝缘层400中靠近衬底100一面之间的夹角γ1小于或等于45°。示例的，当第三绝缘层400的厚度为0.4微米时，第三绝缘层400中背离衬底100的开口可以为9.7微米，第三绝缘层400中靠近衬底100的开口可以为8.8微米，第三过孔V3的侧壁长度大于0.4微米。
对于在第二绝缘层300内形成第二过孔V2的方式。请参考图10，图10是本申请实施例提供的一种形成第二过孔的阵列基板的示意图。在第三绝缘层400中形成第三过孔V3后，可以采用三氟化氮气体和氧气的混合气体作为第二刻蚀气体，对阵列基板000中的第二绝缘层300进行刻蚀，以使第二绝缘层300内能够形成与第三过孔V3连通的第二过孔V2。由于第二绝缘层300是由氧化硅材料制成的，且第二刻蚀气体对氧化硅材料的刻蚀速率较快，通常第二刻蚀气体对氧化硅材料的纵向刻蚀速率约为4000埃每分钟。因此，可以极大的缩短刻蚀第二绝缘层300形成的第二过孔V2时间，进一步的提高了阵列基板000的制造效率。
又由于第二刻蚀气体的横向刻蚀能力较弱。因此，通过第二刻蚀气体对第二绝缘层300的刻蚀过程中，第二绝缘层300不会相对于光刻胶图案111内缩，也即是，第二绝缘层300在横向方向上不容易被第二刻蚀气体刻蚀掉，使得在第二绝缘层300内形成第二过孔V2后，第二绝缘层300会凸出于第三绝缘层400，且第二绝缘层300凸出于第三绝缘层400的部分即为台阶结构。这个台阶结构的宽度即为第二绝缘层300中的第二过孔V2背离衬底100的开口在衬底100上的正投影的外边界，与第三绝缘层400中的第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界之间的距离h。
对于在第一绝缘层200内形成第一过孔V1的方式。请参考图11，图11是本申请实施例提供的一种形成第一过孔的阵列基板的示意图。在第二绝缘层300中形成第二过孔V2后，可以继续采用三氟化氮气体和氧气的混合气体作为第二刻蚀气体，对阵列基板000内的第一绝缘层200进行刻蚀，以使第一绝缘层200内能够形成与第二过孔V2连通的第一过孔V1。由于第一绝缘层200是由氮化硅材料制成，且第二刻蚀气体氮化硅材料的刻蚀速率大于对氧化硅材料的刻蚀速率，通常第二刻蚀气体对氧化硅材料的纵向刻蚀速率约为11000埃每分钟。因此，可以极大的缩短刻蚀第一绝缘层200形成的第二过孔V1时间，进一步的提高了阵列基板00的制造效率。并且，可以保证第一绝缘层300中的第一过孔V1的侧壁与第一绝缘层200中靠近衬底100一面之间的夹角γ3大于或等于80°，且小于90°。
又由于第二刻蚀气体的横向刻蚀能力较弱。因此，通过第二刻蚀气体对第一绝缘层200的刻蚀过程中，第一绝缘层200不会相对于光刻胶图案111内缩，也即是，第一绝缘层200在横向方向上不容易被第二刻蚀气体刻蚀掉。这样，即可保证第一绝缘层200中的第一过孔V1背离衬底100的开口在衬底100上的正投影的外边界，与第二绝缘层300中的第二过孔V2靠近衬底100的开口在衬底100上的正投影的外边界重合。
需要说明的是，本申请实施例中的第二绝缘层300的厚度是可以调整的，且在第二绝缘层300的厚度调整后，在阵列基板000通过刻蚀形成第二搭接过孔V20时对绝缘层的刻蚀时间是基本不变的。为此，在形成第二搭接过孔V20的过程中，光刻胶图案20在刻蚀气体(也即第一刻蚀气体和第二刻蚀气体)的作用下内缩量是基本不变的，且第二搭接过孔V20内的台阶结构的宽度也是基本不变的。这样，第二绝缘层300中的第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2的大小，与第二绝缘层300的厚度呈一定的正相关关系。示例的，本申请实施例以以下两种情况为例进行说明：
第一种情况，如图12所示，图12是本申请实施例提供的一种阵列基板内形成的第二搭接过孔的实际示意图。当第二绝缘层300的厚度的范围为500埃至1000埃时，第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2小于或等于50°。
第二种情况，请参考图13，图13是本申请实施例通过的另一种阵列基板内 形成的第二搭接过孔的实际示意图。当第二绝缘层300的厚度的范围为200埃至500埃时，第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2小于或等于30°。
在本申请实施例中，如图12和图13所示，由于本申请采用两种刻蚀性质不同的刻蚀气体(第一刻蚀气体和第二刻蚀气体)在阵列基板000中形成第二搭接过孔V20的刻蚀速率较快。因此，相比于上述描述中经过长时间刻蚀后形成的第一过孔，本申请实施例在经过一次构图工艺后，阵列基板000中GOA电路002内形成的第二搭接过孔V20内不会出现柱状化合物。这样，位于第二搭接过孔V20内的转接电极600不容易出现搭接不良的情况，使得转接电极600第一电极500的搭接效果较好，进而可以保证GOA电路002不同TFT之间的电连接效果较好。
第二种可选的实现方式，请参考图14，图14是本申请实施例提供的另一种阵列基板的膜层结构示意图。该阵列基板000可以包括：衬底100、第一绝缘层200、第三绝缘层400、第一电极500和转接电极600。
第一绝缘层200和第三绝缘层400沿垂直且远离衬底100的方向依次层叠设置。第一绝缘层200具有第一过孔V1，第三绝缘层400具有与第一过孔V1连通的第三过孔V3。这里，第一过孔V1和第三过孔V3即可组成上述实施例中的第二搭接过孔V20。
其中，第一过孔V1背离衬底100的开口在衬底100上的正投影，位于第三过孔V3靠近衬底100的开口在衬底100上的正投影内，且第一过孔V1背离衬底100的开口在衬底100上的正投影的外边界与第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界不重合。这样，在第一过孔V1和第三过孔V3组成的第二搭接过孔V20内，第一绝缘层200会凸出于第三绝缘层400。
第一电极500位于第一绝缘层200靠近衬底100的一侧，第一电极500在衬底100上的正投影与第一过孔V1在衬底100上的正投影至少部分重合。这样，第一电极500中的至少部分在第一绝缘层200中的第一过孔V1内。这里，第一电极500即为上述实施例中的GOA电路001内的某个TFT的栅极。
转接电极600位于第三绝缘层400背离衬底100的一侧，转接电极600中的至少部分位于第一过孔V1和第三过孔V3内，且与第一电极500搭接。
在本申请实施例中，由于在第一过孔V1和第三过孔V3组成的第二搭接过孔V20内，第一绝缘层200会凸出于第三绝缘层400，且第一绝缘层200凸出于第三绝缘层400的部分即为台阶结构。因此，在将转接电极600中的至少部分位于第二搭接过孔V20内后，转接电极600中的部分能够位于这个台阶结构上。这样，位于第二搭接过孔V20内的转接电极600不易出现断线的问题，进而可以保证转接电极600和第一电极500的搭接效果较好。如此，可以保证GOA电路002不同TFT之间的电连接效果较好，进而使得装配有本申请实施例提供的阵列基板的显示装置的显示效果较好。
在本申请中，第一绝缘层200中的第一过孔V1靠近衬底100的开口在衬底100上的正投影的外边界，与第三绝缘层400中的第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界之间的距离h，即为第一绝缘层200凸出于第三绝缘层400的部分的台阶结构的宽度。当台阶结构的宽度的范围为0.2微米至0.5微米时，在转接电极600中的至少部分位于第二搭接过孔V20内后，可以进一步的降低位于第二搭接过孔V20内的转接电极600出现断线的问题的概率。
在本申请实施例中，第三过孔V3的侧壁与第三绝缘层400中靠近衬底100一面之间的夹角γ小于或等于45°。这里，第三绝缘层400的厚度1000埃至4000埃。这里，相比与上述描述中阵列基板中的第二钝化层06的坡度角α较大，本申请实施例，第三过孔V3的侧壁与靠近衬底100一面之间的夹角γ1较小，使得转接电极600在第一过孔V1内和第一过孔V1外的部分不容易出现的断线的问题。
在本申请中，第一绝缘层200中的第一过孔V1的侧壁靠近第三绝缘层400的部分为弧形侧壁201。这里，在第一过孔V1和第三过孔V3组成的第二搭接过孔V20内，第一绝缘层200中的第一过孔V1的侧壁靠近第三绝缘层400的部分弧形侧壁201，也即是台阶结构中靠近第三绝缘层400的部分为弧形侧壁201。这样，在将转接电极600中的至少部分位于第二搭接过孔V20内后，转接电极600中的部分能够与该弧形侧壁201搭接。这样，转接电极600与第二搭接过孔V20内的第一绝缘层200和第三绝缘层400搭接效果较好，进而可以保证转接电极600和第一电极500的搭接效果较好。如此，进一步的降低了位于第二搭接过孔V20内的转接电极600出现断线的问题的概率。
在本申请实施例中，第一绝缘层200中的第一过孔V1的侧壁靠近第三绝缘层400的弧形侧壁201与第一绝缘层200中靠近衬底100一面之间的夹角小于或等于30°。这里，由于该弧形侧壁201与第一绝缘层200中靠近衬底100一面之间的夹角较小。因此，转接电极600中的至少部分与第一绝缘层200中的第一过孔V1的弧形侧壁201容易搭接。这样，在将转接电极600中的至少部分位于第二搭接过孔V20内后，也能够保证转接电极600中的至少部分与第一绝缘层200中的第一过孔V1的弧形侧壁201的搭接效果较好，进而可以保证转接电极600和第一电极500的搭接效果较好。
在本申请中，第一绝缘层200中的第一过孔V1的侧壁还具有位于弧形侧壁201靠近衬底100一侧平面侧壁202，平面侧壁202与第一绝缘层200中靠近衬底100一面之间的夹角γ3大于或等于80°，且小于90°。这里，尽管第一绝缘层200中的第一过孔V1的平面侧壁202与第一绝缘层200中靠近衬底100一面之间的夹角γ3较大。但是，由于第一绝缘层200中的第一过孔V1的弧形侧壁201与第一绝缘层200中靠近衬底100一面之间的夹角较小。因此，在将转接电极600中的至少部分位于第二搭接过孔V20内后，也能够保证转接电极600中的至少部分与第一绝缘层200中的第一过孔V1的平面侧壁202的搭接效果较好，进而可以保证转接电极600和第一电极500的搭接效果较好。
在本申请实施例中，第一绝缘层200和第三绝缘层400均由氮化硅材料制成的。
以下实施例将对形成图14示出的第二搭接过孔V20的过程进行详细说明：
对于阵列基000上形成光刻胶图案的方式。请参考图15，图15是本申请实施例提供的另一种具有光刻胶薄膜的阵列基板的示意图。在形成有第一绝缘层200和第三绝缘层400的阵列基板000上形成光刻胶图案111后，可以对光刻胶图案111进行烘烤处理。经过烘烤处理后光刻胶图案111中靠近开孔V11的边缘会塌陷，使得光刻胶图案111中靠近开孔V11的部分形成一定的坡度角。示例的，经过烘烤处理后的光刻胶图案111中靠近衬底100的一面与开孔V11的侧面之间形成的角度小于或等于50°。需要说明的是，经过烘烤处理的光刻胶图案111的强度较高，其在受到刻蚀气体的轰击作用后不易产生变形。这里，图15是以光刻胶薄膜111具有一个开孔部分为例进行示意性说明的。在这种情况下，后续在对第三绝缘层400和第一绝缘层200进行刻蚀时，刻蚀气体可以 从开孔V11进入并依次对第三绝缘层400和第一绝缘层层200进行刻蚀。并且，由于经过烘烤处理后的光刻胶图案111中靠近衬底100的一面与开孔部分的侧面之间形成的角度小于或等于50°，因此，光刻胶图案111中靠近开孔V11部分的横向厚度较小，使得光刻胶图案111中靠近开孔V11部分更容易在刻蚀气体的作用下内缩，进而可以避免后续因光刻胶图案111中靠近开孔V11部分内缩较慢，而在第一过孔V1和第三过孔V3(也即第二搭接过孔V20)的侧壁上出现孔洞的不良问题，从而可以进一步的降低后续在第二搭接过孔V20内形成的转接电极600出现断线问题的概率。
对于在第三绝缘层400内形成第三过孔V3的方式。请参考图16，图16是本申请实施例提供的另一种形成第三过孔的阵列基板的示意图。在阵列基板000上形成光刻胶图案111，且对这个光刻胶图案111进行烘烤处理后，可以采用六氟化硫气体和氧气的混合气体作为第一刻蚀气体，对阵列基板000上的第三绝缘层400进行刻蚀，以使第三绝缘层400内能够形成与光刻胶图案111的开孔V11连通的第三过孔V3。需要说明的是，对于本申请形成图14所示的第二搭接过孔V20的过程，在第三绝缘层400内形成第三过孔V3的详细方式，可以参考上述实施例中在第三绝缘层400内形成第三过孔V3的方式，本申请对此不再赘述。
对于在第一绝缘层200内形成第一过孔V1的方式。请参考图17，图17是本申请实施例提供的另一种形成第一过孔的阵列基板的示意图。在第三绝缘层400内形成第三过孔V3后，可以继续采用三氟化氮气体和氧气的混合气体作为第二刻蚀气体，对阵列基板000内的第一绝缘层200进行刻蚀，以使第一绝缘层200内能够形成与第三过孔V3连通的第一过孔V1。由于第一绝缘层200是由氮化硅材料制成，且第二刻蚀气体氮化硅材料的刻蚀速率较大，通常第二刻蚀气体对氧化硅材料的纵向刻蚀速率约为11000埃每分钟。因此，可以极大的缩短刻蚀第一绝缘层200形成的第二过孔V1时间，进一步的提高了阵列基板00的制造效率。
又由于第一刻蚀气体还具有较强的横向刻蚀能力，且第二刻蚀气体的横向刻蚀能力相比于第一刻蚀气体的横向刻蚀能力较弱。因此，通过第一刻蚀气体对第三绝缘层400刻蚀过程中，第三绝缘层400会相对于光刻胶图案111向内缩，使得第三绝缘层层400内形成的开口较大的第三过孔V3。而由于第二刻蚀 气体的横向刻蚀能力较弱，因此，通过第二刻蚀气体对第一绝缘层200的刻蚀过程中，第一绝缘层200不会相对于光刻胶图案111内缩，也即是，第一绝缘层200在横向方向上不容易被第二刻蚀气体刻蚀掉，使得在第一绝缘层200内形成第一过孔V1后，第一绝缘层200会凸出于第三绝缘层400，且第一绝缘层200凸出于第三绝缘层400的部分即为台阶结构。这个台阶结构的宽度即为第一绝缘层200中的第一过孔V1靠近衬底100的开口在衬底100上的正投影的外边界，与第三绝缘层400中的第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界之间的距离h。
又由于第一绝缘层200不会相对于光刻胶图案111内缩，因此，第一绝缘层200中靠近第三绝缘层400一面的部分，不会有光刻胶图案111对其进行遮挡。并且，还由于第二刻蚀气体还具有较强的轰击作用。因此，第一绝缘层200中靠近第三绝缘层400一面的没有被光刻胶图案111进行遮挡的部分，会受到强烈的轰击作用，使得第一绝缘层200中的第一过孔V1的侧壁靠近第三绝缘层400的部分为弧形侧壁201。并且，由于第二刻蚀气体的轰击效果强，第一绝缘层200中第一绝缘层200中的第一过孔V1的侧壁靠近第三绝缘层400的弧形侧壁201与第一绝缘层200中靠近衬底100一面之间的夹角小于或等于30°。
之后，由于第一绝缘层200中靠近第三绝缘层400一面的部分被第二刻蚀气体轰击，保护了第一绝缘层200中靠近衬底100一面的部分。这样，第一绝缘层200中的第一过孔V1的侧壁中，靠近衬底100一面的部分为平面侧壁202。并且，由于第二刻蚀气体对氧化硅材料的纵向刻蚀速率较大，使得第一绝缘层200中的平面侧壁202与第一绝缘层200中靠近衬底100一面之间的夹角较大。如此，第一绝缘层200中的第一过孔V1的侧壁还具有位于弧形侧壁201靠近衬底100一侧平面侧壁202，平面侧壁202与第一绝缘层200中靠近衬底100一面之间的夹角γ3大于或等于80°，且小于90°。
在本申请实施例中，请参考图18，图18是本申请实施例提供的又一种阵列基板内形成的第二搭接过孔的实际示意图。由于本申请采用两种刻蚀性质不同的刻蚀气体(第一刻蚀气体和第二刻蚀气体)在阵列基板000中形成如图14所示的第二搭接过孔V20的刻蚀速率较快。因此，相比于上述描述中经过长时间刻蚀后形成的第一过孔，本申请实施例在经过一次构图工艺后，阵列基板000中GOA电路002内形成的第二搭接过孔V20内不会出现柱状化合物。这样，位 于第二搭接过孔V20内的转接电极600不容易出现搭接不良的情况，使得转接电极600第一电极500的搭接效果较好，进而可以保证GOA电路002不同TFT之间的电连接效果较好。
第三种可选的实现方式，请参考图19，图19是本申请实施例提供的又一种阵列基板的膜层结构示意图。该阵列基板000可以包括：衬底100、第一绝缘层200、第二绝缘层300、第三绝缘层400、第四绝缘层1000、第一电极500和转接电极600。
第一绝缘层200、第二绝缘层300、第四绝缘层1000和第三绝缘层400沿垂直且远离衬底100的方向依次层叠设置。第一绝缘层200具有第一过孔V1，第二绝缘层300具有与第一过孔V1连通的第二过孔V2，第四绝缘层1000具有与第二过孔V2连通的第四过孔V4，第三绝缘层400具有与第四过孔V4连通的第三过孔V3。这里，第一过孔V1、第二过孔V2、第四过孔V4与第三过孔V3即可组成上述实施例中的第二搭接过孔V20。
其中，第四过孔V4背离衬底100的开口在衬底100上的正投影，位于第三过孔V3靠近衬底100的开口在衬底100上的正投影内，且第四过孔V4背离衬底100的开口在衬底100上的正投影的外边界与第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界不重合。这样，在第四过孔V4和第三过孔V3内组成的通孔内，第四绝缘层1000会凸出于第三绝缘层400。第二过孔V2背离衬底100的开口在衬底100上的正投影，位于第四过孔V4靠近衬底100的开口在衬底100上的正投影内，且第二过孔V2背离衬底100的开口在衬底100上的正投影的外边界与第四过孔V4靠近衬底100的开口在衬底100上的正投影的外边界不重合。这样，在第四过孔V4和第二过孔V2内组成的通孔内，第二绝缘层300会凸出于第四绝缘层1000。
第一电极500位于第一绝缘层200靠近衬底100的一侧，第一电极500在衬底100上的正投影与第一过孔V1在衬底100上的正投影至少部分重合。这样，第一电极500中的至少部分在第一绝缘层200中的第一过孔V1内。这里，第一电极500即为上述实施例中的GOA电路001内的某个TFT的栅极。
转接电极600位于第三绝缘层400背离衬底100的一侧，转接电极600中的至少部分位于第一过孔V1、第二过孔V2、第四过孔V4和第三过孔V3内， 且与第一电极500搭接。
在本申请实施例中，由于在第一过孔V1、第二过孔V2、第四过孔V4与第三过孔V3组成的第二搭接过孔V20内，第二绝缘层300会凸出于第四绝缘层1000，且该会第四绝缘层1000还会凸出于第三绝缘层400。这样，第二绝缘层300凸出于第四绝缘层1000的部分即为第一台阶，第四绝缘层1000凸出于第三绝缘层400的部分即为第二台阶，第一台阶和第二台阶可以组成一个台阶结构。因此，在将转接电极600中的至少部分位于第二搭接过孔V20内后，转接电极600中的部分能够位于这个台阶结构上。这样，位于第二搭接过孔V20内的转接电极600不易出现断线的问题，使得转接电极600和第一电极500的搭接效果较好。如此，可以保证GOA电路002不同TFT之间的电连接效果较好，进而使得装配有本申请实施例提供的阵列基板的显示装置的显示效果较好。
在本申请中，第一绝缘层200中的第一过孔V1背离衬底100的开口在衬底100上的正投影的外边界，与第二绝缘层300中的第二过孔V2靠近衬底100的开口在衬底100上的正投影的外边界重合。这里，相比于上述描述中阵列基板中的过孔内位置Q处容易产生多余凸起，本申请实施例，在相互连通的第一过孔V1和第二过孔V2中第一绝缘层200和第二绝缘层300接触的位置不存在多余凸起，使得转接电极600与第一绝缘层200和第二绝缘层300的搭接效果较好。如此，进一步的降低了位于第二搭接过孔V20内的转接电极600出现断线的问题的概率。
在本申请实施例中，第三过孔V3的侧壁与第三绝缘层400中靠近衬底100一面之间的夹角γ3小于或等于45°。这里，第三绝缘层400的厚度1000埃至4000埃。这里，相比与上述描述中阵列基板中的第二钝化层06的坡度角α较大，本申请实施例，第三过孔V3的侧壁与靠近衬底100一面之间的夹角γ1较小，使得转接电极600在第一过孔V1内和第一过孔V1外的部分不容易出现的断线的问题。
在本申请中，第四绝缘层1000和第二绝缘层300均由SiOy材料制成，且第四绝缘层1000的膜层致密度小于第二绝缘层300的膜层致密度。在本申请的一些实施例中，第二绝缘层300和第四绝缘层1000的材料为氧化硅材料。第二绝缘层300的厚度的范围为500埃至700埃。第二绝缘层300的厚度大于第四绝缘层1000的厚度。这里，由于形成第二绝缘层300的温度较高，因此第二绝缘 层300的氧化硅的膜质较为紧密。而由于第四绝缘层1000通常位于GOA电路002中的TFT有源层背离衬底100的一侧，并且GOA电路002中的TFT有源层不耐高温，因此，形成第四绝缘层1000的温度较低，使得第四绝缘层1000的氧化硅的膜质较为疏松。在这种情况下，由于第四绝缘层1000的膜质相比于第二绝缘层300的膜质较为疏松，使得形成第二搭接过孔V20内的第二绝缘层300和第三绝缘层400之间能够形成台阶结构，进而保证转接电极600和第一电极500的搭接效果较好。
在本申请实施例中，第二过孔V2背离衬底100的开口在衬底100上的正投影的外边界，与第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界之间的距离范围h为：0.4微米至0.6微米。这里，第二绝缘层300中的第二过孔V2背离衬底100的开口在衬底100上的正投影的外边界，与第三绝缘层400中的第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界之间的距离h，即为由第一台阶和第二台阶可以组成的台阶结构。这个台阶结构的宽度为第二过孔V2背离衬底100的开口在衬底100上的正投影的外边界，与第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界之间的距离h。当台阶结构的宽度的范围为0.4微米至0.6微米时，在转接电极600中的至少部分位于第二搭接过孔V20内后，可以进一步的降低位于第二搭接过孔V20内的转接电极600出现断线的问题的概率。
在本申请中，当第二绝缘层300的厚度的范围为500埃至700埃时，第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2小于或等于50°。这里，第二绝缘层300中的第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2越小，转接电极600越容易与第二绝缘层300中的第二过孔V2的侧壁进行搭接，使得位于第二搭接过孔V20内的转接电极600越不易出现断线的问题。
在本申请实施例中，第一绝缘层200中的第一过孔V1的侧壁与第一绝缘层200中靠近衬底100一面之间的夹角γ3大于或等于80°，且小于90°。这里，尽管第一绝缘层200中的第一过孔V1的侧壁与第一绝缘层200中靠近衬底100一面之间的夹角γ3较大。但是，由于第二绝缘层300中的第二过孔V2的侧壁与第二绝缘层300中靠近衬底100一面之间的夹角γ2较小。因此，在将转接电极600中的至少部分与第一绝缘层200中的第一过孔V1的侧壁进行搭接后，也 能够保证转接电极600中的至少部分与第一绝缘层200中的第一过孔V1的侧壁的搭接效果较好。如此，进而使得装配有本申请实施例提供的阵列基板的显示装置的显示效果较好。
在本申请中，第一绝缘层200和第三绝缘层400均由氮化硅材料制成，第二绝缘层300和第四绝缘层1000均由氧化硅材料制成。并且第四绝缘层1000的氧化硅密度小于第二绝缘层300的氧化硅密度。
以下实施例将对形成图19示出的第二搭接过孔V20的过程进行详细说明：
对于阵列基板000上形成光刻胶图案的方式。请参考图20，图20是本申请实施例提供的又一种具有光刻胶薄膜的阵列基板的示意图。需要说明的是，对于本申请形成图19所示的第二搭接过孔V20的过程，在阵列基板000上形成光刻胶图案的详细方式，可以参考上述实施例中对于阵列基000上形成光刻胶图案的方式，本申请对此不再赘述。
对于在第三绝缘层400内形成第三过孔V3的方式。请参考图21，图21是本申请实施例提供的又一种形成第三过孔的阵列基板的示意图。在阵列基板000上形成光刻胶图案111，且对这个光刻胶图案111进行烘烤处理后，可以采用六氟化硫气体和氧气的混合气体作为第一刻蚀气体，对阵列基板000上的第三绝缘层400进行刻蚀，以使第三绝缘层400内能够形成与光刻胶图案111的开孔V11连通的第三过孔V3。需要说明的是，对于本申请形成图19所示的第二搭接过孔V20的过程，在第三绝缘层400内形成第三过孔V3的详细方式，可以参考上述实施例中在第三绝缘层400内形成第三过孔V3的方式，本申请对此不再赘述。
对于在第四绝缘层1000内形成第四过孔V4的方式。请参考图22，图22是本申请实施例提供的一种形成第四过孔和第二过孔的阵列基板的示意图。在第三绝缘层400中形成第三过孔V3后，可以采用三氟化氮气体和氧气的混合气体作为第二刻蚀气体，对阵列基板000中的第四绝缘层1000进行刻蚀，以使第四绝缘层1000内能够形成与第三过孔V3连通的第四过孔V4。由于第二刻蚀气体对由氧化硅材料制成的第四绝缘层1000的刻蚀速率较快，并且，第四绝缘层1000是由膜质较为疏松的氧化硅材料制成的。因此，可以极大的缩短刻蚀第四绝缘层1000形成的第四过孔V4时间，进一步的提高了阵列基板000的制造效率。
又由于第二刻蚀气体的横向刻蚀能力较弱。因此，通过第二刻蚀气体对第四绝缘层1000的刻蚀过程中，第四绝缘层1000不会相对于光刻胶图案111内缩，也即是，第四绝缘层1000在横向方向上不容易被第二刻蚀气体刻蚀掉，使得在第四绝缘层1000内形成第四过孔V4后，第四绝缘层1000会凸出于第三绝缘层400，且第二绝缘层300凸出于第三绝缘层400的部分即为第一台阶T1。这个第一台阶T1的宽度即为第四绝缘层1000中的第四过孔V4背离衬底100的开口在衬底100上的正投影的外边界，与第三绝缘层400中的第三过孔V3靠近衬底100的开口在衬底100上的正投影的外边界之间的距离。
对于在第二绝缘层300内形成第二过孔V2的方式。如图22所示，在第四绝缘层1000中形成第四过孔V4后，依旧采用三氟化氮气体和氧气的混合气体作为第二刻蚀气体，对阵列基板000中的第二绝缘层300进行刻蚀，以使第二绝缘层300内能够形成与第四过孔V4连通的第二过孔V2。由于第二刻蚀气体对由氧化硅材料制成的第二绝缘层300的刻蚀速率较快，因此，可以极大的缩短刻蚀第四绝缘层1000形成的第四过孔V4时间，进一步的提高了阵列基板000的制造效率。
又由于第二刻蚀气体的横向刻蚀能力较弱。因此，通过第二刻蚀气体对第二绝缘层300的刻蚀过程中，第二绝缘层300不会相对于光刻胶图案111内缩，也即是，第二绝缘层300在横向方向上不容易被第二刻蚀气体刻蚀掉，使得在第二绝缘层300内形成第二过孔V2后，第四绝缘层1000会凸出于第二绝缘层300，且第四绝缘层1000凸出于第二绝缘层300的部分即为第二台阶T2。这个第二台阶T2的宽度即为第二过孔V2背离衬底100的开口在衬底100上的正投影的外边界，与第四过孔V4靠近衬底100的开口在衬底100上的正投影的外边界之间的距离。
又由于第四绝缘层10000的氧化硅密度小于第二绝缘层300的氧化硅密度。因此，通过第二刻蚀气体对第四绝缘层1000和第二绝缘层300的刻蚀过程中，第四绝缘层1000相对于光刻胶图案111向内缩的速度，相比于第二绝缘层300相对于光刻胶图案111向内缩的速度较快。这样，第四绝缘层1000会对第二绝缘层300靠近其一面的部分产生引导作用，使得由第一台阶T1和第二台阶T2可以组成的台阶结构的宽度进一步增大。这个台阶的宽度即为第二过孔V2背离衬底100的开口在衬底100上的正投影的外边界，与第三过孔V3靠近衬底100 的开口在衬底100上的正投影的外边界之间的距离范围h。
对于在第一绝缘层200内形成第一过孔V1的方式。请参考图23，图23是本申请实施例提供的又一种形成第一过孔的阵列基板的示意图。在第三绝缘层400内形成第三过孔V3后，可以继续采用三氟化氮气体和氧气的混合气体作为第二刻蚀气体，对阵列基板000内的第一绝缘层200进行刻蚀，以使第一绝缘层200内能够形成与第三过孔V3连通的第一过孔V1。需要说明的是，对于本申请形成图19所示的第二搭接过孔V20的过程，在第一绝缘层200内形成第一过孔V1的详细方式，可以参考上述实施例中在第一绝缘层200内形成第一过孔V1的方式，本申请对此不再赘述。
在本申请实施例中，请参考图24，图24是本申请实施例通过的再一种阵列基板内形成的第二搭接过孔的实际示意图。由于本申请采用两种刻蚀性质不同的刻蚀气体(第一刻蚀气体和第二刻蚀气体)在阵列基板000中形成如图19所示的第二搭接过孔V20的刻蚀速率较快。因此，相比于上述描述中经过长时间刻蚀后形成的第一过孔，本申请实施例在经过一次构图工艺后，阵列基板000中GOA电路002内形成的第二搭接过孔V20内不会出现柱状化合物。这样，位于第二搭接过孔V20内的转接电极600不容易出现搭接不良的情况，使得转接电极600第一电极500的搭接效果较好，进而可以保证GOA电路002不同TFT之间的电连接效果较好。
需要说明的是，请参考图25，图25是本申请实施例提供的一种转接电极在第二搭接过孔内搭接的效果图。阵列基板000中的至少两层绝缘层中的至少两个相互连通的过孔用于组成第二搭接过孔V20。这个第二搭接过孔V20的侧壁上具有上仍然会具有多个柱状化合物，但是柱状化合物的分布密度会远小于相关技术中的柱状化合物的分布密度，且本申请中的第二搭接过孔V20的侧壁上的柱状化合物平均高度小于转接电极的厚度。并且，柱状化合物凸起顶端切线与水平方向的夹角β 1小于转接电极600的坡度角β 2。
如此，即使第二搭接过孔V20的侧壁上上分布了多个柱状化合物，这些柱状化合物也不会影响转接电极与第一电极的搭接效果。这里，组成柱状化合物的元素包括：碳元素、氧元素、氟元素和铜元素等。
在本申请实施例中，如图6所示，阵列基板000中的各个子像素001与GOA 电路均是层叠设置的膜层结构组成的。示例的，阵列基板000可以包括：衬底100，以及位于衬底100上的栅极金属层、第一绝缘层200、第二绝缘层300、有源层图案、源漏极金属层、第四绝缘层1000、有机绝缘层1100、像素电极层、第三绝缘层400和公共电极层。
其中，栅极金属层可以包括：子像素001内的驱动TFT的栅极801，以及GOA电路002内的TFT的栅极等。示例的，上述实施例中的第一电极400属于这个栅极金属层内的部分。
有源层图案可以包括：子像素001内的驱动TFT的有源层802，以及GOA电路002内的TFT的有源层等。这里，有源层是由氧化物半导体材料制成的。
源漏极金属层可以包括：子像素001内的驱动TFT的源极803和漏极804，以及GOA电路002内的TFT的源极和漏极等。
像素电极层可以包括：子像素001内与驱动TFT电连接的像素电极900。
公共电极层可以包括：子像素001内的公共电极1200，以及GOA电路002内的转接电极600等。也即是，非显示区内的转接电极600和子像素001内的公共电极1200是通过一次构图工艺形成的。
在本申请中，由于有源层图案由氧化物半导体材料制成，且氧化物半导体材料容易受周围膜层中的离子(例如，氢离子)的影响。因此，位于有源层图案靠近衬底100一侧的第二绝缘层300，与位于有源层图案背离衬底100一侧的第四绝缘层1000均需要采用绝缘效果更好的氧化硅材料制成。而其他的绝缘层(例如，第一绝缘层200和第三绝缘层400)均由氮化硅材料制成。
需要说明的是，为了能够让像素电极与驱动TFT中的源极和漏极中的一个电连接，需要在形成像素电极之前，对阵列基板000进行打孔处理，以在显示区内形成连接过孔V30，像素电极900可以通过连接过孔V30与驱动TFT中的源极和漏极中的一个电连接。而在形成连接过孔V30的过程中，可以对位于非显示区00b内的第一搭接过孔V10和第二搭接过孔V20附近处的第二绝缘层300、第四绝缘层1000和有机绝缘层1100中的至少一个进行去除处理。示例的，在图6中，在形成连接过孔V30的过程中，对位于非显示区00b内的第一搭接过孔V10和第二搭接过孔V20附近处的第四绝缘层1000和有机绝缘层1100进行去除处理。在图14中，在形成连接过孔V30的过程中，对位于非显示区00b内的第一搭接过孔V10和第二搭接过孔V20附近处的第二绝缘层300、第四绝 缘层1000和有机绝缘层1100进行去除处理。在图19中，在形成连接过孔V30的过程中，对位于非显示区00b内的第一搭接过孔V10和第二搭接过孔V20附近处的有机绝缘层1100进行去除处理。
本申请实施例还提供了一种阵列基板的制造方法，该阵列基板的制造方法包括：
步骤S1、在衬底上形成第一电极。
步骤S2、在第一电极上形成至少两层绝缘层，并对至少两层绝缘层依次执行第一刻蚀处理和第二刻蚀处理，以在至少两层绝缘层中形成至少两个相互连通的过孔，至少两个过孔中最靠近衬底的第一过孔的尺寸小于其他过孔的尺寸；
步骤S3、在至少两层绝缘层上形成转接电极，以使转接电极通过至少两个过孔与第一电极搭接。
可选的，在第一电极上形成至少两层绝缘层，并对至少两层绝缘层依次执行第一刻蚀处理和第二刻蚀处理，包括：在第一电极上依次形成的第一绝缘层、第二绝缘层和第三绝缘层；采用第一刻蚀气体对第三绝缘层进行第一刻蚀处理，以在第三绝缘层中形成第三过孔；采用第二刻蚀气体依次对第二绝缘层和第三绝缘层进行第二刻蚀处理，以在第二绝缘层中形成与第三过孔连通的第二过孔，且在第一绝缘层中形成与第二过孔连通的第一过孔；其中，第二过孔背离衬底的开口在衬底上的正投影，位于第三过孔靠近衬底的开口在衬底上的正投影内，且第二过孔背离衬底的开口在衬底上的正投影的外边界与第三过孔靠近衬底的开口在衬底上的正投影的外边界不重合。
可选的，在第一电极上形成至少两层绝缘层，并对至少两层绝缘层依次执行第一刻蚀处理和第二刻蚀处理，包括：在第一电极上依次形成的第一绝缘层和第三绝缘层；采用第一刻蚀气体对第三绝缘层进行第一刻蚀处理，以在第三绝缘层中形成第三过孔；采用第二刻蚀气体对第一绝缘层进行第二刻蚀处理，以在第一绝缘层中形成与第三过孔连通的第一过孔；其中，第一过孔背离衬底的开口在衬底上的正投影，位于第三过孔靠近衬底的开口在衬底上的正投影内，且第一过孔靠近衬底的开口在衬底上的正投影的外边界与第三过孔靠近衬底的开口在衬底上的正投影的外边界不重合。
可选的，在第一电极上形成至少两层绝缘层，并对至少两层绝缘层依次执 行第一刻蚀处理和第二刻蚀处理，包括：在第一电极上依次形成的第一绝缘层、第二绝缘层、第四绝缘层和第三绝缘层；采用第一刻蚀气体对第三绝缘层进行第一刻蚀处理，以在第三绝缘层中形成第三过孔；采用第二刻蚀气体依次对第四绝缘层、第二绝缘层和第一绝缘层进行第二刻蚀处理，以在第四绝缘层中形成与第三过孔连通的第四过孔，在第二绝缘层中形成与第四过孔连通的第二过孔，且在第一绝缘层中形成与第二过孔连通的第一过孔；
其中，第四过孔背离衬底的开口在衬底上的正投影，位于第三过孔靠近衬底的开口在衬底上的正投影内，且第四过孔背离衬底的开口在衬底上的正投影的外边界与第三过孔靠近衬底的开口在衬底上的正投影的外边界不重合；第二过孔背离衬底的开口在衬底上的正投影，位于第四过孔靠近衬底的开口在衬底上的正投影内，且第二过孔背离衬底的开口在衬底上的正投影的外边界与第四过孔靠近衬底的开口在衬底上的正投影的外边界不重合。
可选的，第一绝缘层和第三绝缘层的材料均包含硅元素和氮元素，第二绝缘层的材料包含硅元素和氧元素。
可选的，第一绝缘层和第三绝缘层的材料包含硅元素和氮元素。
可选的，第一绝缘层和第三绝缘层的材料均包含硅元素和氮元素，第二绝缘层和第四绝缘层的材料均包含硅元素和氧元素
可选的，第一刻蚀气体的横向刻蚀能力强于第二刻蚀气体的横向刻蚀能力。
可选的，第一刻蚀气体为：六氟化硫、四氟化硫，四氟化碳和氟化氮中的至少一种气体与氧气的混合气体。
可选的，第二刻蚀气体为：三氟化氮气体和氧气的混合气体。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的阵列基板具体原理，可以参考前述阵列基板结构的实施例中的对应内容，在此不再赘述。
本申请实施例还提供了一种显示面板。该显示面板可以包括：相对设置的阵列基板和彩膜基板，以及位于二者之间的液晶层。阵列基板可以为上述实施例中的阵列基板。例如，其可以为图6示出的阵列基板。在彩膜基板与阵列基板对盒连接后，显示面板可以向阵列基板施加电信号，以使显示面板能够显示图像。
本申请实施例还提供了一种显示装置。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置可以包括：驱动芯片和显示面板。
在本申请实施例中，显示面板可以为上述实施例中的显示面板。例如，其可以包括：图6、图14、或图19示出的阵列基板，与阵列基板相对设置的彩膜基板，以及位于二者之间的液晶层。该驱动芯片与显示面板连接，用于为显示面板提供电信号，以使显示面板能够显示图像。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本申请中，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
以上所述仅为本申请的可选的实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (31)

  1. 一种阵列基板的制造方法，其特征在于，所述方法包括：
    在衬底上形成第一电极；
    在所述第一电极上形成至少两层绝缘层，并对所述至少两层绝缘层依次执行第一刻蚀处理和第二刻蚀处理，以在所述至少两层绝缘层中形成至少两个相互连通的过孔，至少两个所述过孔中最靠近所述衬底的第一过孔的尺寸小于其他过孔的尺寸；
    在所述至少两层绝缘层上形成转接电极，以使所述转接电极通过至少两个过孔与所述第一电极搭接。
  2. 根据权利要求1所述的方法，其特征在于，在所述第一电极上形成至少两层绝缘层，并对所述至少两层绝缘层依次执行第一刻蚀处理和第二刻蚀处理，包括：
    在所述第一电极上依次形成的第一绝缘层、第二绝缘层和第三绝缘层；
    采用第一刻蚀气体对所述第三绝缘层进行第一刻蚀处理，以在所述第三绝缘层中形成第三过孔；
    采用第二刻蚀气体依次对所述第二绝缘层和所述第三绝缘层进行第二刻蚀处理，以在所述第二绝缘层中形成与所述第三过孔连通的第二过孔，且在所述第一绝缘层中形成与所述第二过孔连通的第一过孔；
    其中，所述第二过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。
  3. 根据权利要求1所述的方法，其特征在于，在所述第一电极上形成至少两层绝缘层，并对所述至少两层绝缘层依次执行第一刻蚀处理和第二刻蚀处理，包括：
    在所述第一电极上依次形成的第一绝缘层和第三绝缘层；
    采用第一刻蚀气体对所述第三绝缘层进行第一刻蚀处理，以在所述第三绝 缘层中形成第三过孔；
    采用第二刻蚀气体对所述第一绝缘层进行第二刻蚀处理，以在所述第一绝缘层中形成与所述第三过孔连通的第一过孔；
    其中，所述第一过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第一过孔靠近所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。
  4. 根据权利要求1所述的方法，其特征在于，在所述第一电极上形成至少两层绝缘层，并对所述至少两层绝缘层依次执行第一刻蚀处理和第二刻蚀处理，包括：
    在所述第一电极上依次形成的第一绝缘层、第二绝缘层、第四绝缘层和第三绝缘层；
    采用第一刻蚀气体对所述第三绝缘层进行第一刻蚀处理，以在所述第三绝缘层中形成第三过孔；
    采用第二刻蚀气体依次对所述第四绝缘层、所述第二绝缘层和所述第一绝缘层进行第二刻蚀处理，以在所述第四绝缘层中形成与第三过孔连通的第四过孔，在所述第二绝缘层中形成与所述第四过孔连通的第二过孔，且在所述第一绝缘层中形成与所述第二过孔连通的第一过孔；
    其中，所述第四过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第四过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合；所述第二过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第四过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第四过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。
  5. 根据权利要求2所述的方法，其特征在于，所述第一绝缘层和所述第三绝缘层的材料均包含硅元素和氮元素，所述第二绝缘层的材料包含硅元素和氧元 素。
  6. 根据权利要求3所述的方法，其特征在于，所述第一绝缘层和所述第三绝缘层的材料包含硅元素和氮元素。
  7. 根据权利要求4所述的方法，其特征在于，所述第一绝缘层和所述第三绝缘层的材料均包含硅元素和氮元素，所述第二绝缘层和所述第四绝缘层的材料均包含硅元素和氧元素。
  8. 根据权利要求5至7任一所述的方法，其特征在于，所述第一刻蚀气体对所述第三绝缘层的横向刻蚀能力强于所述第二刻蚀气体对所述第一绝缘层的横向刻蚀能力。
  9. 根据权利要求8所述的方法，其特征在于，所述第一刻蚀气体为：六氟化硫、四氟化硫，四氟化碳和氟化氮中的至少一种气体与氧气的混合气体。
  10. 根据权利要求8所述的方法，其特征在于，所述第二刻蚀气体为：三氟化氮气体和氧气的混合气体。
  11. 一种阵列基板，其特征在于，包括：
    衬底；
    在衬底上设置的第一电极、转接电极和至少两层绝缘层，所述第一电极位于所述至少两层绝缘层靠近所述第一电极的一侧，所述转接电极位于所述至少两层绝缘层背离所述衬底的一侧；
    其中，所述至少两层绝缘层具有至少两个相互连通的过孔，至少两个所述过孔中最靠近所述衬底的第一过孔的尺寸小于其他过孔的尺寸，所述转接电极通过至少两个过孔与所述第一电极搭接。
  12. 根据权利要求11所述的阵列基板，其特征在于，所述至少两层绝缘层包括：沿垂直且远离所述衬底的方向依次设置的第一绝缘层、第二绝缘层和第三 绝缘层，所述第一绝缘层具有第一过孔，所述第二绝缘层具有与所述第一过孔连通的第二过孔，所述第三绝缘层具有与所述第二过孔连通的第三过孔；
    其中，所述第二过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。
  13. 根据权利要求12所述的阵列基板，其特征在于，所述第一过孔背离所述衬底的开口在所述衬底上的正投影的外边界，与所述第二过孔靠近所述衬底的开口在所述衬底上的正投影的外边界重合。
  14. 根据权利要求12所述的阵列基板，其特征在于，所述第三过孔的侧壁与所述第三绝缘层中靠近所述衬底一面之间的夹角小于60°。
  15. 根据权利要求14所述的阵列基板，其特征在于，所述第三过孔的侧壁与所述第三绝缘层中靠近所述衬底一面之间的夹角小于或等于45°。
  16. 根据权利要求15所述的阵列基板，其特征在于，所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界，与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界之间的距离范围为：0.2微米至0.5微米。
  17. 根据权利要求16所述的阵列基板，其特征在于，所述第二绝缘层的厚度的范围为500埃至1000埃，所述第二过孔的侧壁与所述第二绝缘层中靠近所述衬底一面之间的夹角大于或等于30°，且小于或等于50°。
  18. 根据权利要求16所述的阵列基板，其特征在于，所述第二绝缘层的厚度的范围为200埃至500埃，所述第二过孔的侧壁与所述第二绝缘层中靠近所述衬底一面之间的夹角小于或等于30°。
  19. 根据权利要求17或18所述的阵列基板，其特征在于，所述第一过孔的 侧壁与所述第一绝缘层中靠近所述衬底一面之间的夹角大于或等于80°，且小于90°。
  20. 根据权利要求11所述的阵列基板，其特征在于，所述至少两层绝缘层包括：沿垂直且远离所述衬底的方向依次设置的第一绝缘层和第三绝缘层，所述第一绝缘层具有第一过孔，所述第三绝缘层具有与所述第一过孔连通的第三过孔；
    其中，所述第一过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第一过孔靠近所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。
  21. 根据权利要求20所述的阵列基板，其特征在于，所述第一过孔的侧壁靠近所述第三绝缘层的部分为弧形侧壁。
  22. 根据权利要求21所述的阵列基板，其特征在于，所述弧形侧壁与所述第一绝缘层中靠近所述衬底一面之间的夹角小于或等于30°。
  23. 根据权利要求21所述的阵列基板，其特征在于，所述第一过孔的侧壁还具有位于所述弧形侧壁靠近所述衬底一侧平面侧壁，所述平面侧壁与所述第一绝缘层中靠近所述衬底一面之间的夹角大于或等于80°，且小于90°。
  24. 根据权利要求11所述的阵列基板，其特征在于，所述至少两层绝缘层包括：沿垂直且远离所述衬底的方向依次设置的第一绝缘层、第二绝缘层、第四绝缘层和第三绝缘层，所述第一绝缘层具有第一过孔，所述第二绝缘层具有与所述第一过孔连通的第二过孔，所述第四绝缘层具有与所述第二过孔连通的第四过孔，所述第三绝缘层具有与所述第四过孔连通的第三过孔；
    其中，所述第四过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第三过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第四过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第三过孔靠近所述衬 底的开口在所述衬底上的正投影的外边界不重合；所述第二过孔背离所述衬底的开口在所述衬底上的正投影，位于所述第四过孔靠近所述衬底的开口在所述衬底上的正投影内，且所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界与所述第四过孔靠近所述衬底的开口在所述衬底上的正投影的外边界不重合。
  25. 根据权利要求24所述的阵列基板，其特征在于，所述第二绝缘层和所述第四绝缘层的材料均包含硅元素和氧元素，且所述第四绝缘层的材料中的硅元素和氧元素的分布密度小于所述第二绝缘层的材料中的硅元素和氧元素的分布密度。
  26. 根据权利要求25所述的阵列基板，其特征在于，所述第二过孔背离所述衬底的开口在所述衬底上的正投影的外边界，与所述第三过孔靠近所述衬底的开口在所述衬底上的正投影的外边界之间的距离范围为：0.4微米至0.6微米。
  27. 根据权利要求11至26任一所述的阵列基板，其特征在于，所述阵列基板还包括：位于所述至少两层绝缘层中的两层相邻的绝缘层之间的第二电极，所述至少两层绝缘层还具有第一搭接过孔，所述转接电极通过所述第一搭接过孔与所述第二电极搭接。
  28. 根据权利要求11至26任一所述的阵列基板，其特征在于，所述至少两层绝缘层中的至少两个相互连通的过孔用于组成第二搭接过孔，所述第二搭接过孔的侧壁上具有多个柱状化合物，所述柱状化合物的平均高度小于所述转接电极的厚度。
  29. 根据权利要求28所述的阵列基板，其特征在于，所述柱状化合物凸起顶端切线与水平方向的夹角小于所述转接电极的坡度角。
  30. 根据权利要求28所述的阵列基板，其特征在于，组成所述柱状化合物的元素包括：碳元素、氧元素、氟元素和铜元素。
  31. 一种显示面板，其特征在于，包括：相对设置的阵列基板和彩膜基板，所述阵列基板为权利要求11至30任一所述的阵列基板。
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