WO2024000492A9 - 阵列基板和液晶显示面板 - Google Patents

阵列基板和液晶显示面板 Download PDF

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Publication number
WO2024000492A9
WO2024000492A9 PCT/CN2022/103074 CN2022103074W WO2024000492A9 WO 2024000492 A9 WO2024000492 A9 WO 2024000492A9 CN 2022103074 W CN2022103074 W CN 2022103074W WO 2024000492 A9 WO2024000492 A9 WO 2024000492A9
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WIPO (PCT)
Prior art keywords
slit
array substrate
electrode
segment
section
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PCT/CN2022/103074
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English (en)
French (fr)
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WO2024000492A1 (zh
Inventor
干泉
张然
王永灿
张明飞
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002043.6A priority Critical patent/CN117642692A/zh
Priority to PCT/CN2022/103074 priority patent/WO2024000492A1/zh
Publication of WO2024000492A1 publication Critical patent/WO2024000492A1/zh
Publication of WO2024000492A9 publication Critical patent/WO2024000492A9/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes

Definitions

  • the present disclosure relates to the field of display technology, and specifically to an array substrate and a liquid crystal display panel.
  • the contrast ratio of current LCD panels at large viewing angles is difficult to meet some high-demand application scenarios. Therefore, it is necessary to develop display products with high contrast at large viewing angles.
  • the purpose of this disclosure is to overcome the above-mentioned shortcomings of the prior art, provide an array substrate and a liquid crystal display panel, and improve the contrast of the liquid crystal display panel at a large viewing angle.
  • an array substrate including a substrate substrate, a first electrode layer, an insulating layer and a second electrode layer that are stacked in sequence; wherein the first electrode layer and the second electrode layer are One of the electrode layers is provided with a slit electrode; the array substrate further includes a plurality of data traces, portions of the data traces adjacent to the slit electrode extend straight along the column direction;
  • the slit electrode is provided with a plurality of slits, and the slits include a first slit section; the angle between the extension direction of the first slit section and the row direction is in the range of 69° to 85°.
  • an angle between the extension direction of the first slit section and the row direction is between 79° and 85°.
  • the angle between the extending direction of the first slit section and the row direction is 79° or 83°.
  • At least part of the slits further includes at least one of a second slit segment and a third slit segment; One end is connected, and the third slit section is connected to the other end of the first slit section; along the column direction, the second slit section and the third slit section are respectively located on the first Both sides of the slit segment;
  • the line between the end of the second slit segment away from the first slit segment and the end of the first slit segment away from the second slit segment and the row direction The acute angle is smaller than the acute angle between the extension direction of the first slit segment and the row direction;
  • the line between the end of the third slit segment away from the first slit segment and the end of the first slit segment away from the third slit segment and the row direction The acute angle is smaller than the acute angle between the extending direction of the first slit section and the row direction.
  • At least part of the slits includes a second slit section, a first slit section and a third slit section connected in sequence.
  • the angle between the extension direction of the second slit section and the row direction is between 50° and 60°; and/or,
  • the angle between the extension direction of the third slit section and the row direction is between 50° and 60°.
  • the second slit section has the same width as the first slit section and has a length smaller than the first slit section;
  • the third slit section has the same width as the first slit section and has a length smaller than the first slit section.
  • the slit electrode includes a plurality of slit groups, and the slit group includes two of the slits having a common end;
  • the two slits of the slit group are located on the same side of the common end;
  • the two slits of the slit group are respectively located on both sides of the common end.
  • the extending directions of the first slit sections of the two slits of the slit group are mirror-symmetrical with respect to the row direction.
  • any one of the slits in the slit group further includes a second slit section close to the common end; the first slit section of the slit is located on the The side of the second slit section away from the common end;
  • the line between the end of the second slit segment away from the first slit segment and the end of the first slit segment away from the second slit segment and the row direction The acute angle is smaller than the acute angle between the first slit section and the row direction.
  • the extension directions of the second slit sections of the two slits of the slit group are mirror-symmetrical with respect to the row direction.
  • the extending directions of the first slit sections of the two slit electrodes are mirror symmetrical with respect to the column direction.
  • the extending directions of the first slit sections of the two slit electrodes are mirror-symmetrical with respect to the row direction.
  • the extending directions of the first slit sections of the two slit electrodes are mirror symmetrical with respect to the column direction; in Among the two slit electrodes adjacent along the column direction, the extending directions of the first slit sections of the two slit electrodes are mirror symmetrical with respect to the row direction.
  • the width of the first slit section is between 3.4 microns and 5.6 microns.
  • the slit electrode includes electrode comb teeth located between two adjacent first slit segments, and the width of the electrode comb teeth is between 2.0 microns and 3.4 microns.
  • the ratio of the width of the first slit segment to the width of the electrode comb teeth is between 1 and 2.4.
  • the width of the first slit section is between 4.1 and 4.5 microns; the width of the electrode comb teeth is between 2.3 and 2.7 microns.
  • the width of the first slit section is between 4.4 and 4.6 microns; the width of the electrode comb teeth is between 2.7 and 2.9 microns.
  • the slit electrode is located on the second electrode layer.
  • a liquid crystal display panel including an array substrate and a color filter substrate arranged in pairs, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate.
  • FIG. 1 is a schematic structural diagram of a display device in an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a liquid crystal display panel in an embodiment of the present disclosure.
  • FIG. 3 is a partial structural diagram of an array substrate in an embodiment of the present disclosure.
  • FIG. 4 is a partial structural diagram of an array substrate in an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a slit electrode in an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of the principle of reducing light leakage through an array substrate in an embodiment of the present disclosure.
  • FIG. 7 is a partial schematic diagram of a gate layer of an array substrate in an embodiment of the present disclosure.
  • FIG. 8 is a partial schematic diagram of the semiconductor layer of the array substrate in an embodiment of the present disclosure.
  • FIG. 9 is a partial schematic diagram of the source and drain metal layers of the array substrate in an embodiment of the present disclosure.
  • FIG. 10 is a partial schematic diagram of the first electrode layer of the array substrate in an embodiment of the present disclosure.
  • FIG. 11 is a partial schematic diagram of the second electrode layer of the array substrate in an embodiment of the present disclosure.
  • FIG. 12 is a partial structural diagram of an array substrate in an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the arrangement of slit electrodes in an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of the arrangement of slit electrodes in an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of the arrangement of slit electrodes in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • a transistor is a component that includes at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source .
  • the channel region refers to the area through which current mainly flows.
  • the structural layer A is located on the side of the structural layer B facing away from the base substrate. It can be understood that the structural layer A is formed on the side of the structural layer B facing away from the base substrate.
  • part of the structure of structural layer A may also be located at the same physical height of structural layer B or lower than the physical height of structural layer B, where the base substrate is the height reference.
  • the liquid crystal display device includes a liquid crystal display panel PNL, a control component CTR, and a backlight module BLU.
  • the control component CTR simultaneously drives the liquid crystal display panel PNL and the backlight module BLU.
  • the liquid crystal display panel may include an array substrate ARR and a color filter substrate CF arranged in a box, with a liquid crystal layer LC sandwiched between the array substrate and the color filter substrate.
  • the array substrate, the color filter substrate, and the sealant disposed therebetween define a closed box-shaped area, which is filled with liquid crystal to form a liquid crystal layer LC.
  • the liquid crystal display panel further includes a lower polarizer located on a side of the array substrate away from the color filter substrate and an upper polarizer located on a side of the color filter substrate away from the array substrate.
  • the array substrate is provided with pixel electrodes and a pixel driving circuit for loading data voltages to the pixel electrodes.
  • a common electrode is provided on the array substrate or color filter substrate.
  • FIG. 3 shows a schematic structural diagram of a liquid crystal display panel PNL in an embodiment of the present disclosure.
  • the liquid crystal display panel PNL may include a display area AA and a peripheral area BB surrounding the display area AA.
  • the array substrate is provided with scanning lines GL extending in the row direction and data lines DataL extending in the column direction.
  • the scanning lines GL and the data lines DataL define multiple pixel areas (for example, in Figure 4 Pixel area PIXA), the pixel electrode and the pixel driving circuit may be located in the pixel area.
  • the pixel driving circuit may be a thin film transistor serving as a switching transistor.
  • the peripheral area BB of the array substrate has a first peripheral area B1 in which the source driving circuit SIC is bound, and a second peripheral area B2 in which the gate driving circuit GOA is arranged. Among them, the first peripheral area B1 extends along the column direction, and the second peripheral area B2 extends along the row direction.
  • the gate driving circuit GOA is electrically connected to each scan line GL, and is used to load the scan signal to the scan line GL to turn on the switching transistor.
  • the source driver circuit SIC is electrically connected to the data line DataL, and is used to generate a data voltage according to the picture synchronization data and load it to the data line DataL.
  • the number of source driving circuits SIC of the liquid crystal display panel PNL is multiple, and each source driving circuit SIC can drive multiple data lines DataL respectively.
  • the source driving circuit SIC is a chip; the array substrate is provided with an FPC (flexible circuit board) binding area and a source driving circuit binding area in the first peripheral area B1.
  • the source drive circuit binding area can be bound with the source drive circuit SIC, and the source drive circuit binding area is electrically connected to the data trace DataL and the FPC binding area through wiring.
  • the FPC binding area can be bound and connected to the control component CTR through FPC. In this way, the signals and voltages of the control component CTR can be transmitted to the source drive circuit SIC through the FPC.
  • the signal between the source driver circuit SIC and the control component CTR can be an LVDS (low voltage differential signal) signal or a mini LVDS signal to reduce signal crosstalk.
  • the liquid crystal display panel PNL may also have other structures.
  • the gate drive circuit GOA may not be provided on the array substrate but an additional gate drive circuit board may be bound thereto; for another example, the array substrate may have Gate drive circuits GOA are set up on both sides of the row direction to reduce the scanning signal voltage drop or increase the scanning frequency; for another example, source drive circuits SIC are set up at both ends of the array substrate in the column direction to drive the liquid crystal display panel PNL on both sides, reducing the The voltage drop on the data trace DataL in the large-size liquid crystal display panel PNL, especially the voltage drop on the data trace DataL in the splicing screen.
  • the source driving circuit SIC may not be provided on the liquid crystal display panel PNL, but may be provided on a COF (Chip On Film).
  • COF Chip On Film
  • This disclosure does not limit the relative positional relationship and arrangement form between the source driving circuit SIC and the liquid crystal display panel PNL, as long as the source driving circuit SIC can directly drive each pixel in the display area of the liquid crystal display panel PNL.
  • the backlight module BLU in the example of the embodiment of the present disclosure may be an edge-type backlight source or a direct-type backlight source.
  • the backlight module BLU may include a light panel.
  • a control unit can be provided on the lamp board.
  • Each control unit includes a microchip and at least one lamp area controlled by the microchip.
  • Each lamp area is distributed in an array so that the backlight module BLU can present good luminous uniformity and facilitate Debugging of backlight module BLU.
  • Each light area has one or more light-emitting elements (such as Mini LED or Micro LED).
  • each light-emitting element can be connected in series, in parallel, or in a series-parallel mixture, so that Each light-emitting element can be driven, for example, so that each light-emitting element is in an electrical path with the same current amplitude.
  • Multiple light-emitting elements in the electrical path constitute a light-emitting circuit.
  • the microchip controls the overall brightness of the lamp area by driving the brightness of each light-emitting element in the lamp area.
  • the microchip controls the brightness of each light-emitting element in the lamp area under the control of the control component CTR, and then controls the brightness of the lamp area, so that the brightness of the backlight module BLU and the picture of the liquid crystal display panel PNL cooperate with each other to improve the display. effects, such as increasing contrast.
  • the above example of the backlight module BLU is an actively driven backlight module that can achieve local dimming of each lamp area through a microchip.
  • the backlight module BLU may not need to implement local dimming, or may adopt a passive driving method to implement local dimming, or may adopt other active driving methods to implement local dimming.
  • the array substrate ARR may include a first electrode layer EDLA, an insulating layer PVX and a second electrode layer EDLB that are sequentially stacked on one side of the base substrate, wherein in any one pixel area PIXA , one of the first electrode layer EDLA and the second electrode layer EDLB may be provided with a slit electrode SLD, and the other may be provided with a plate electrode. An edge electric field is generated between the slit electrode SLD and the plate electrode, which is used to drive the liquid crystal in the liquid crystal layer to collapse or flip, thereby controlling the light emission of the liquid crystal display panel in the pixel area PIXA.
  • the data trace DataL of the liquid crystal display panel PNL can be arranged at an angle, and the slit SL of the slit electrode SLD matches (ie is parallel to) the inclination direction of the data trace DataL.
  • the data trace DataL of the liquid crystal display panel PNL can be arranged in a straight line and extend along the column direction DV, and the slit SL of the slit electrode SLD is inclined at a small angle to the row direction DH.
  • the contrast of liquid crystal display panels PNL needs to be further improved; in particular, the contrast of display panels in related technologies at large viewing angles is difficult to meet some high-demand application scenarios. For example, in the field of vehicle-mounted displays, the contrast of the above-mentioned related technology products at a large viewing angle is difficult to meet relevant requirements.
  • the present disclosure provides a liquid crystal display panel PNL.
  • the liquid crystal display panel PNL includes a base substrate BP, a first electrode layer EDLA, an insulating layer PVX and a second electrode layer EDLB that are stacked in sequence; wherein, the One of the first electrode layer EDLA and the second electrode layer EDLB is provided with a slit electrode SLD; the liquid crystal display panel PNL also includes a plurality of data traces DataL, and the data traces DataL are adjacent to the slits.
  • the portion of the electrode SLD extends linearly along the column direction DV.
  • the slit electrode SLD is provided with a plurality of slits SL, and the slits SL include a first slit section SLA; the angle between the extension direction of the first slit section SLA and the row direction DH is Within the range of 69° ⁇ 85°.
  • the data lines DataL are linearly arranged along the row direction DH, and the extending direction of the first slit section SLA of the slit electrode SLD is close to the column direction DV and is consistent with the column direction DV.
  • this liquid crystal display panel PNL can also be used in consumer-grade products that have high requirements for display quality.
  • the linearly polarized light Exy passing through the lower polarizer can have two components (S wave Es and P wave Ep), that is, the S wave Es along the S component axis (parallel to the extension direction of the SD metal line) and the P wave along the P wave Ep of the component axis (perpendicular to the extension direction of the SD metal line and parallel to the plane of the display panel).
  • the P wave Ep changes to the vertical direction (perpendicular to the display panel plane, that is, the Z direction), resulting in only S wave Es in the display panel plane; S wave Es It can also decompose the component Exy' in the direction of the transmission axis of the upper polarizer, and Exy' is the polarization amount.
  • Exy’ can produce light leakage through the upper polarizer. According to the formula, when ⁇ is 45°, the larger Exy’ is, the most serious light leakage is; when ⁇ is 0°, Exy’ is the smallest, and the light leakage is the slightest.
  • the data trace DataL is arranged straight along the column direction DV, so that ⁇ is 0°, thereby making the light leakage of the liquid crystal display panel PNL small, which can significantly improve the performance of the liquid crystal display panel.
  • PNL contrast including but not limited to contrast at large viewing angles.
  • the liquid crystal display panel PNL according to the embodiment of the present disclosure exhibits better light efficiency in the test, which correspondingly makes the liquid crystal display panel PNL of the present disclosure have a greater contrast ratio; specifically, the liquid crystal display panel PNL according to the present disclosure has a greater contrast ratio.
  • the liquid crystal display panel of the disclosed embodiment has a smaller dark pattern area than the second related technology.
  • the light transmittance of the liquid crystal display panel PNL of the present disclosure is higher than that of the second related technology.
  • the rate is 8.7% higher; the driving voltage of the liquid crystal display panel of the present disclosure when reaching the maximum brightness is lower than that of the second related technology.
  • the array substrate includes a first electrode layer EDLA and a second electrode layer EDLB.
  • a bottom electrode is provided on the first electrode layer EDLA
  • a top electrode corresponding to the bottom electrode is provided on the second electrode layer EDLB.
  • the orthographic projection of the bottom electrode on the base substrate BP and the orthographic projection of the top electrode on the base substrate BP at least partially coincide.
  • one of the bottom electrode and the top electrode may be a slit electrode SLD, and the other may be a plate electrode.
  • one of the first electrode layer EDLA and the second electrode layer EDLB may be provided with the slit electrode SLD, and the other may be provided with a plate-shaped electrode corresponding to the slit electrode SLD.
  • the orthographic projection of the slit electrode SLD on the base substrate BP at least partially coincides with the orthographic projection of the plate electrode on the base substrate BP.
  • one of the bottom electrode and the top electrode may be a common electrode, and the other may be a pixel electrode.
  • one of the first electrode layer EDLA and the second electrode layer EDLB may be a common electrode layer that is provided with a common electrode, and the other may be a pixel electrode layer that is provided with a pixel electrode.
  • the bottom electrode provided in the first electrode layer EDLA may be a plate electrode and may serve as the pixel electrode PIXP.
  • the top electrode provided in the second electrode layer EDLB can be a slit electrode SLD, which can serve as a common electrode.
  • the material of the first electrode layer EDLA and the second electrode layer EDLB may be a transparent conductive material, such as a transparent metal oxide.
  • the material of the slit electrode SLD is ITO (indium zinc oxide).
  • the array substrate of the present disclosure is provided with a plurality of scanning lines GL, a plurality of data lines DataL and a switching transistor connected to the pixel electrode; wherein one end of the switching transistor is connected to the data line DataL, and the other end of the switching transistor is connected to the data line DataL. Connect the pixel electrode, and the gate electrode is connected to the scanning line GL. Under the control of the scan voltage loaded on the scan line GL, the switching transistor can be turned on, so that the data voltage on the data line DataL is loaded to the pixel electrode.
  • the portion of the data trace DataL adjacent to the slit electrode SLD extends straight along the column direction DV; for example, the data trace DataL extends straight along the column direction DV as a whole, or the data trace DataL is in a portion adjacent to the switching transistor.
  • the portion that can be bent and is close to the slit electrode SLD extends straight along the column direction DV.
  • the data trace DataL is a straight line and extends along the column direction; along the row direction, data traces are provided on both sides of the slit electrode SLD DataL.
  • the scan trace GL may extend along the row direction.
  • the bottom electrode and the top electrode may be disposed between two adjacent scan lines GL.
  • the gate layer is provided with a scanning line GL and a gate TWG of a switching transistor electrically connected to the scanning line GL.
  • the semiconductor layer may include a source contact area TWSA of the switching transistor, a channel area TWAct of the switching transistor, and a drain contact area TWDA of the switching transistor connected in sequence.
  • the source-drain metal layer SD is provided with the source TWS of the switching transistor electrically connected to the data line DataL and is provided with the drain electrode TWD of the switching transistor.
  • the source TWS of the switching transistor and the source contact area TWSA of the switching transistor are electrically connected through a via hole, or the source TWS of the switching transistor is directly connected to the source contact area TWSA of the switching transistor; the drain of the switching transistor
  • the electrode TWD and the drain contact area TWDA of the switching transistor are electrically connected through a via hole, or the drain TWD of the switching transistor is directly connected to the drain contact area TWDA of the switching transistor;
  • the drain TWD of the switching transistor is connected to the pixel electrode PIXP
  • the pixel electrode PIXP is electrically connected through a via hole, or the pixel electrode PIXP and the drain electrode TWD of the switching transistor are partially stacked.
  • the gate electrode TWG of the switching transistor overlaps with the channel region TWAct of the switching transistor, and a gate insulating layer GI is spaced between them.
  • the active layer of the switching transistor is provided on the semiconductor layer, and its material may be an amorphous silicon semiconductor material, a polycrystalline silicon semiconductor material, a metal oxide semiconductor material, or an organic semiconductor material.
  • the material of the active layer of the switching transistor may be a low-temperature polysilicon semiconductor material or amorphous silicon; wherein the source contact region and the drain contact region may be ion doped. With high conductivity, the channel region can maintain semiconductor characteristics and turn on or off corresponding to the scanning signal loaded on the gate.
  • the second electrode layer EDLB is a common electrode layer, and the second electrode layer EDLB is also provided with a common electrode line COML, and the top electrode is electrically connected to the common electrode line COML.
  • the color filter substrate CF is provided with a black matrix BM, and the black matrix BM covers the common electrode line COML.
  • the common electrode line COML covers the data trace DataL.
  • uneven brightness in the edge area of the pixel area PIXA can be avoided and the size and area of the pixel area PIXA can be limited.
  • each data line DataL drives two rows of pixels, and each row of pixels is driven by two scan lines GL. In this way, through the time-sharing driving of the two scanning lines GL of the pixels in the same row, the data on the data line DataL can be written into the pixel electrodes of the two pixels in the same row.
  • the second electrode layer EDLB is used as the common electrode layer and the slit electrode SLD is disposed on the second electrode layer EDLB.
  • the gate layer used to form the scanning line GL, the gate electrode TWG of the switching transistor, etc.
  • the gate insulating layer GI, the semiconductor layer, and the first layer can be sequentially prepared on one side of the base substrate BP.
  • the array substrate may further include an alignment layer covering the second electrode layer EDLB.
  • the liquid crystal display panel PNL can also be in other ways.
  • the second electrode layer EDLB can be a pixel electrode layer and the first electrode layer EDLA can be a common electrode layer; for another example, the bottom electrode can be a slit electrode. SLD and the top electrode is a plate electrode.
  • the first electrode layer EDLA is a common electrode layer, and the bottom electrode provided therein can be used as a common electrode overlapping with the pixel electrode PIXP; the first electrode layer EDLA is also provided with a common electrode connected to the bottom electrode. line COML to load the bottom electrode with a common voltage.
  • the second electrode layer EDLB is a pixel electrode layer, and its top electrode is a slit electrode SLD, and the slit electrode SLD and the bottom electrode are overlapped.
  • an organic insulating layer ORG may be provided between the first electrode layer EDLA and the source-drain metal layer SD.
  • the slit electrode SLD is provided with a plurality of slits SL, and the slits SL include a first slit section SLA; the angle between the extension direction of the first slit section SLA and the row direction DH is Within the range of 69° ⁇ 85°. Furthermore, the angle between the extension direction of the first slit section SLA and the row direction DH is between 79° and 85°. In particular, the extension direction of the first slit section SLA and the row direction DH are between 79° and 85°. The angle between the row direction DH is 79° or 83°.
  • liquid crystal display panel PNL of the present disclosure by limiting the inclination angle of the first slit section SLA, a balance can be achieved between the light efficiency (transmittance Tr) of the liquid crystal display panel PNL and the liquid crystal recovery time, so that the liquid crystal display The panel PNL has high light efficiency while maintaining a fast recovery speed, avoiding the impact on the refresh rate of the liquid crystal display panel PNL by simply increasing the light efficiency and contrast.
  • the inclination angle of the first slit section SLA can be increased by increasing the inclination angle of the first slit section SLA (increasing the inclination angle of the first slit section SLA).
  • the refresh rate of the liquid crystal display panel PNL can be increased by reducing the inclination angle of the first slit section SLA.
  • At least part of the slit SL further includes at least one of a second slit section SLB and a third slit section SLC.
  • the second slit section SLB is connected to one end of the first slit section SLA, and the third slit section SLC is connected to the other end of the first slit section SLA; along the column direction DV,
  • the second slit section SLB and the third slit section SLC are respectively located on both sides of the first slit section SLA.
  • the acute angle between the directions DH is smaller than the acute angle between the first slit section SLA and the row direction DH.
  • connection line between the end of the third slit section SLC away from the first slit section SLA and the end of the first slit section SLA away from the third slit section SLC and the row The acute angle between the directions DH is smaller than the acute angle between the first slit section SLA and the row direction DH.
  • each slit SL of the liquid crystal display panel PNL may be additionally provided with a second slit segment SLB or a third slit segment SLC in addition to the first slit segment SLA according to requirements.
  • the electric field at the edge of the pixel area PIXA can be balanced and the brightness uniformity of the PIX can be improved.
  • the second slit section SLB and the third slit section SLC are not necessary; the slit SL may only be provided with the first slit section SLA and the second slit section SLB , or only the first slit section SLA and the third slit section SLC can be provided, or only the first slit section SLA can be provided.
  • the second slit section SLB and the first slit section connected in sequence can also be provided at the same time. Slit section SLA and third slit section SLC.
  • the slits SL includes a second slit segment SLB, a first slit segment SLA and a third slit segment SLC connected in sequence, such as those not adjacent to the edge of the pixel area PIXA.
  • Each slit SL includes a second slit section SLB, a first slit section SLA and a third slit section SLC connected in sequence. In this way, the uniformity of brightness in the pixel area PIXA can be improved.
  • the angle between the second slit section SLB and the row direction DH is between 50° and 60°.
  • the angle between the third slit section SLC and the row direction DH is between 50° and 60°.
  • the second slit section SLB when the slit SL is provided with a second slit section SLB, the second slit section SLB has the same width as the first slit section SLA and a length smaller than the first slit section SLA. A slit segment SLA. In this way, on the one hand, the brightness uniformity of the pixel area PIXA can be improved, and on the other hand, the second slit section SLB can be prevented from being too large and affecting the light efficiency.
  • the third slit section SLC when the slit SL is provided with a third slit section SLC, the third slit section SLC has the same width as the first slit section SLA and a length smaller than the third slit section SLA.
  • a slit segment SLA In this way, on the one hand, the brightness uniformity of the pixel area PIXA can be improved, and on the other hand, the third slit section SLC can be prevented from being too large and affecting the light efficiency.
  • the slit electrode SLD includes a plurality of slit groups SLS, and the slit group SLS includes two slits SL having a common end.
  • the two slits SL of the slit group SLS are located on the same side of the common end; along the column direction DV, the two slits SL of the slit group SLS are located on the same side of the common end.
  • the slits SL are respectively located on both sides of the common end. In this way, 1P (one pixel) and 2D (two domain areas) can be realized in the pixel area PIXA, thereby improving the viewing angle of the liquid crystal display panel PNL.
  • the liquid crystal display panel PNL of the present disclosure can achieve a large viewing angle and high contrast, especially high contrast at a large viewing angle. Furthermore, in this embodiment, the resolution of the liquid crystal display panel PNL may not be too high, for example, the PPI may not be greater than 280, so as to improve the manufacturability of the liquid crystal display panel PNL.
  • the extension direction of the first slit section SLA of the two slits SL of the slit group SLS is mirror-symmetrical with respect to the row direction DH. In this way, the uniformity of different domain areas can be improved, thereby improving the uniformity of images under viewing angles in different directions.
  • any one of the slits SL in the slit group SLS further includes a second slit section SLB close to the common end; the first slit of the slit SL
  • the slit segment SLA is located on the side of the second slit segment SLB away from the common end; the end of the second slit segment SLB away from the first slit segment SLA is in contact with the first slit segment
  • the acute angle between the line connecting the end of SLA away from the second slit section SLB and the row direction DH is smaller than the acute angle between the first slit section SLA and the row direction DH. angle.
  • the light extraction rate at the connection of the two slits SL can be basically consistent with that of other areas, improve the uniformity of brightness in the pixel area PIXA, and avoid sudden changes in light efficiency caused by sudden changes in the angle of the slits SL.
  • the extending directions of the second slit sections SLB of the two slits SL of the slit group SLS are mirror-symmetrical with respect to the row direction DH.
  • the liquid crystal display panel PNL can also adopt a 2P2D (2 pixels, 2 domain areas) or 4P4D (4 pixels, 4 domain areas) architecture to improve the viewing angle, for example, in a higher resolution display In panels (such as display panels with a PPI greater than 280) or in products that do not have high requirements for picture quality.
  • a 2P2D (2 pixels, 2 domain areas) or 4P4D (4 pixels, 4 domain areas) architecture to improve the viewing angle, for example, in a higher resolution display In panels (such as display panels with a PPI greater than 280) or in products that do not have high requirements for picture quality.
  • the extension direction of the first slit section SLA of the two slit electrodes SLD is with respect to the column.
  • the extension direction of the first slit section SLA of the two slit electrodes SLD is with respect to the row direction.
  • DH mirror symmetry In this way, the 2P2D effect can be achieved.
  • the extending direction of the first slit section SLA of the two slit electrodes SLD is about the The column direction DV is mirror symmetrical; among the two slit electrodes SLD adjacent along the column direction DV, the extending directions of the first slit sections SLA of the two slit electrodes SLD are mirror symmetrical with respect to the row direction DH. In this way, the effect of 4P4D can be achieved.
  • the width of the first slit section SLA is between 3.4 microns and 5.6 microns.
  • the slit electrode SLD includes an electrode comb tooth DA located between two adjacent first slit segments SLA, and the width of the electrode comb tooth DA is between 2.0 microns and Between 3.4 microns.
  • the ratio of the width of the first slit section SLA to the width of the electrode comb teeth DA is between 1 and 2.4.
  • the width of the first slit segment SLA, the width of the electrode comb teeth DA/the width of the first slit segment SLA and The ratio of the widths of the electrode comb teeth DA can be adjusted as needed to balance the quality of the liquid crystal display panel PNL.
  • the width of the first slit section SLA is between 4.1 and 4.5 microns; the width of the electrode comb teeth DA is between 2.3 and 2.7 microns. In this way, the liquid crystal display panel PNL can have higher light efficiency and better recovery time.
  • the slit electrodes are common electrodes, and a common electrode line COML is provided between adjacent slit electrodes along the row direction.
  • the width of the first slit section SLA is 3.8 microns, the width of the electrode comb teeth DA is 2.7 microns; the width of the common electrode line COML is 9.6 microns, and covers the data line DataL.
  • the width of the data line DataL is 3.5 microns, which makes the common electrode line COML exceed the data line DataL by 3.05 microns on one side.
  • the pixel electrode is a plate-shaped electrode and is located on the first electrode layer. The distance between the edge of the pixel electrode and the data line DataL is 4.35 microns.
  • a black matrix is provided on the color filter substrate; along the row direction, the width of the black matrix BM between two pixels is 7.0 microns, and one side exceeds the data line DataL by 1.75 microns.
  • the width of the first slit section SLA is between 4.4 and 4.6 microns; the width of the electrode comb teeth DA is between 2.7 and 2.9 microns. In this way, the liquid crystal display panel PNL can also have higher light efficiency and better recovery time.
  • the effects of different sizes of the first slit section SLA and the electrode comb teeth DA on the light efficiency of the liquid crystal display panel PNL were also tested.
  • test cases 1 to 6 were tested in sequence. Please see Table 1 for specific data:
  • W, S, Pitch, Gap, and Overall Width are in microns.
  • Vop is the driving voltage when the pixel reaches its maximum brightness, in V.
  • Tr is the light efficiency (light transmittance); Tr (%) refers to the normalized data of the light efficiency of each test example based on the light efficiency of Test Example 6 (100%).
  • each slit electrode was provided with 8 slits.
  • 2ITO-2ITO represents the spacing between two slit electrodes. It can be seen from Table 2 that when W is 2 microns and S is 4.2 microns, the liquid crystal display panel PNL can have higher brightness, and in other tests it was found that this setting method can also reduce brightness fluctuations, that is, Achieving a balance between brightness fluctuation and high light efficiency.

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Abstract

本公开提供一种阵列基板和显示面板，属于显示技术领域。该阵列基板(ARR)，包括依次层叠设置的衬底基板(BP)、第一电极层(EDLA)、绝缘层(PVX)和第二电极层(EDLB)；其中，所述第一电极层(EDLA)和所述第二电极层(EDLB)中的一个设置有狭缝电极(SLD)；所述阵列基板(ARR)还包括多个数据走线(DataL)，所述数据走线(DataL)临近所述狭缝电极(SLD)的部分沿所述列方向(DV)直线延伸；所述狭缝电极(SLD)设置有多个狭缝(SL)，所述狭缝(SL)包括第一狭缝段(SLA)；所述第一狭缝段(SLA)的延伸方向与行方向(DH)的夹角在69°～85°的范围内。

Description

阵列基板和液晶显示面板 技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板和液晶显示面板。
背景技术
当前液晶显示面板在大视角下的对比度，难以满足一些高要求的应用场景。因此，有必要开发在大视角下具有高对比度的显示产品。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种阵列基板和液晶显示面板，提高液晶显示面板在大视角下的对比度。
根据本公开的第一个方面，提供一种阵列基板，包括依次层叠设置的衬底基板、第一电极层、绝缘层和第二电极层；其中，所述第一电极层和所述第二电极层中的一个设置有狭缝电极；所述阵列基板还包括多个数据走线，所述数据走线临近所述狭缝电极的部分沿所述列方向直线延伸；
所述狭缝电极设置有多个狭缝，所述狭缝包括第一狭缝段；所述第一狭缝段的延伸方向与行方向的夹角在69°～85°的范围内。
根据本公开的一种实施方式，所述第一狭缝段的延伸方向与所述行方向的夹角在79°～85°之间。
根据本公开的一种实施方式，所述第一狭缝段的延伸方向与所述行方向的夹角为79°或者83°。
根据本公开的一种实施方式，至少部分所述狭缝还包括第二狭缝段和第三狭缝段中的至少一者；所述第二狭缝段与所述第一狭缝段的一端连接，所述第三狭缝段与所述第一狭缝段的另一端连接；沿所述列方向，所述第二狭缝段和所述第三狭缝段分别位于所述第一狭缝段的两侧；
所述第二狭缝段远离所述第一狭缝段的端部与所述第一狭缝段远离所述第二狭缝段的端部之间的连线与所述行方向之间的锐角夹角，小于所述第一狭缝段的延伸方向与所述行方向之间的锐角夹角；
所述第三狭缝段远离所述第一狭缝段的端部与所述第一狭缝段远离所述第三狭缝段的端部之间的连线与所述行方向之间的锐角夹角，小于所述第一狭缝段的延伸方向与所述行方向之间的锐角夹角。
根据本公开的一种实施方式，至少部分所述狭缝包括依次连接的第二狭缝段、第一狭缝段和第三狭缝段。
根据本公开的一种实施方式，所述第二狭缝段的延伸方向与所述行方向的夹角在50°～60°之间；和/或，
所述第三狭缝段的延伸方向与所述行方向的夹角在50°～60°之间。
根据本公开的一种实施方式，所述第二狭缝段与所述第一狭缝段宽度相同，且长度小于所述第一狭缝段；和/或，
所述第三狭缝段与所述第一狭缝段宽度相同，且长度小于所述第一狭缝段。
根据本公开的一种实施方式，所述狭缝电极包括多个狭缝组，所述狭缝组包括具有共同端部的两个所述狭缝；
沿所述行方向，所述狭缝组的两个所述狭缝均位于所述共同端部的同一侧；
沿所述列方向，所述狭缝组的两个所述狭缝分别位于所述共同端部的两侧。
根据本公开的一种实施方式，所述狭缝组的两个所述狭缝的第一狭缝段的延伸方向关于所述行方向镜像对称。
根据本公开的一种实施方式，所述狭缝组中的任意一个所述狭缝还包括靠近所述共同端部的第二狭缝段；所述狭缝的第一狭缝段位于所述第二狭缝段远离所述共同端部的一侧；
所述第二狭缝段远离所述第一狭缝段的端部与所述第一狭缝段远离所述第二狭缝段的端部之间的连线与所述行方向之间的锐角夹角，小于所述第一狭缝段与所述行方向之间的锐角夹角。
根据本公开的一种实施方式，所述狭缝组的两个所述狭缝的第二狭缝 段的延伸方向关于所述行方向镜像对称。
根据本公开的一种实施方式，在沿行方向相邻的两个所述狭缝电极中，两个所述狭缝电极的第一狭缝段的延伸方向关于所述列方向镜像对称。
根据本公开的一种实施方式，在沿列方向相邻的两个狭缝电极中，两个所述狭缝电极的第一狭缝段的延伸方向关于所述行方向镜像对称。
根据本公开的一种实施方式，在沿行方向相邻的两个所述狭缝电极中，两个所述狭缝电极的第一狭缝段的延伸方向关于所述列方向镜像对称；在沿列方向相邻的两个狭缝电极中，两个所述狭缝电极的第一狭缝段的延伸方向关于所述行方向镜像对称。
根据本公开的一种实施方式，所述第一狭缝段的宽度在3.4微米～5.6微米之间。
根据本公开的一种实施方式，所述狭缝电极包括位于相邻两个所述第一狭缝段之间的电极梳齿，所述电极梳齿的宽度在2.0微米～3.4微米之间。
根据本公开的一种实施方式，所述第一狭缝段的宽度与所述电极梳齿的宽度的比值在1～2.4之间。
根据本公开的一种实施方式，所述第一狭缝段的宽度在4.1～4.5微米之间；所述电极梳齿的宽度在2.3～2.7微米之间。
根据本公开的一种实施方式，所述第一狭缝段的宽度在4.4～4.6微米之间；所述电极梳齿的宽度在2.7～2.9微米之间。
根据本公开的一种实施方式，所述狭缝电极位于所述第二电极层。
根据本公开的第二个方面，提供一种液晶显示面板，包括对盒设置的阵列基板和彩膜基板，以及包括夹设于阵列基板和彩膜基板中的液晶层。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他 的附图。
图1为本公开一种实施方式中，显示装置的结构示意图。
图2为本公开一种实施方式中，液晶显示面板的结构示意图。
图3为本公开一种实施方式中，阵列基板的局部结构示意图。
图4为本公开一种实施方式中，阵列基板的局部结构示意图。
图5为本公开一种实施方式中，狭缝电极的结构示意图。
图6为本公开一种实施方式中，阵列基板降低漏光的原理示意图。
图7为本公开一种实施方式中，阵列基板的栅极层的局部示意图。
图8为本公开一种实施方式中，阵列基板的半导体层的局部示意图。
图9为本公开一种实施方式中，阵列基板的源漏金属层的局部示意图。
图10为本公开一种实施方式中，阵列基板的第一电极层的局部示意图。
图11为本公开一种实施方式中，阵列基板的第二电极层的局部示意图。
图12为本公开一种实施方式中，阵列基板的局部结构示意图。
图13为本公开一种实施方式中，狭缝电极的排列方式示意图。
图14为本公开一种实施方式中，狭缝电极的排列方式示意图。
图15为本公开一种实施方式中，狭缝电极的排列方式示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于 方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区，并且电流可以流过漏极、沟道区以及源极。沟道区是指电流主要流过的区域。
结构层A位于结构层B背离衬底基板的一侧，可以理解为，结构层A在结构层B背离衬底基板的一侧形成。当结构层B为图案化结构时，结构层A的部分结构也可以位于结构层B的同一物理高度或低于结构层B的物理高度，其中，衬底基板为高度基准。
本公开实施方式提供一种液晶显示装置，参见图1，该液晶显示装置包括液晶显示面板PNL、控制组件CTR和背光模组BLU。控制组件CTR同时驱动液晶显示面板PNL和背光模组BLU。
从层叠结构看，参见图2，液晶显示面板可以包括对盒设置的阵列基板ARR和彩膜基板CF，在阵列基板、彩膜基板之间夹设有液晶层LC。例如，阵列基板、彩膜基板以及设置在其之间的封框胶限定出封闭的盒状区域，该区域内填充有液晶以形成液晶层LC。其中，液晶显示面板还包括位于阵列基板远离彩膜基板一侧的下偏光片和位于彩膜基板远离阵列基板一侧的上偏光片。阵列基板上设置有像素电极和用于向像素电极加载数据电压的像素驱动电路。阵列基板或者彩膜基板上设置有公共电极。通过控制像素电极与公共电极之间的电场强度，可以调整像素电极对应范围内的液晶的扭转程度或者倒伏程度，进而调整通过液晶的偏振光的偏振方 向，最终调整液晶显示面板在像素电极对应范围内的出光率。
图3示出了本公开实施方式中一种液晶显示面板PNL的结构示意图。从平面的角度，液晶显示面板PNL可以包括显示区AA和围绕显示区AA的外围区BB。在显示区AA，阵列基板设置有沿行方向延伸的扫描走线GL和沿列方向延伸的数据走线DataL，扫描走线GL和数据走线DataL限定出多个像素区域(例如图4中的像素区域PIXA)，像素电极和像素驱动电路可以位于该像素区域中。在示例中，像素驱动电路可以为一个作为开关晶体管的薄膜晶体管，开关晶体管的一端与数据走线DataL电连接，开关晶体管的另一端与像素电极连接，开关晶体管的栅极与扫描走线GL连接。阵列基板的外围区BB具有绑定有源极驱动电路SIC的第一外围区B1，以及具有设置栅极驱动电路GOA的第二外围区B2。其中，第一外围区B1沿列方向延伸，第二外围区B2沿行方向延伸。其中，栅极驱动电路GOA与各个扫描走线GL电连接，用于向扫描走线GL加载使得开关晶体管导通的扫描信号。源极驱动电路SIC与数据走线DataL电连接，用于根据画面同步数据生成数据电压并加载至数据走线DataL。
参见图3，在该示例中，液晶显示面板PNL的源极驱动电路SIC的数量为多个，每个源极驱动电路SIC可以分别驱动多个数据走线DataL。进一步的，源极驱动电路SIC为芯片；阵列基板在第一外围区B1设置有FPC(柔性电路板)绑定区和源极驱动电路绑定区。源极驱动电路绑定区内可以绑定源极驱动电路SIC，且源极驱动电路绑定区通过走线分别与数据走线DataL电连接、FPC绑定区电连接。FPC绑定区能够通过FPC与控制组件CTR绑定连接。这样，控制组件CTR的信号和电压可以通过FPC传输至源极驱动电路SIC。进一步的，源极驱动电路SIC和控制组件CTR之间的信号，可以为LVDS(低电压差分信号)信号或者mini LVDS信号，以减小信号串扰。
当然的，在本公开的其他实施方式中，液晶显示面板PNL也可以呈其他结构，例如阵列基板上可以不设置栅极驱动电路GOA而是额外绑定栅极驱动电路板；再例如阵列基板在行方向两侧均设置栅极驱动电路GOA以降低扫描信号压降或者提高扫描频率；再例如在阵列基板列方向的两端均设置源极驱动电路SIC以便对液晶显示面板PNL双侧驱动，降 低大尺寸液晶显示面板PNL中数据走线DataL上的压降，尤其是降低拼接屏中数据走线DataL上的压降。再例如，源极驱动电路SIC可以不设置在液晶显示面板PNL上，而是设置在COF(覆晶薄膜)上。本公开对源极驱动电路SIC与液晶显示面板PNL之间的相对位置关系和设置形式不做限定，以源极驱动电路SIC能够直接驱动液晶显示面板PNL的显示区的各个像素为准。
本公开实施方式示例的背光模组BLU可以为侧入式背光源，也可以为直下式背光源。在一种示例中，背光模组BLU可以包括灯板。灯板上可以设置有控制单元，每个控制单元包括微芯片和微芯片控制的至少一个灯区；其中，各个灯区阵列分布，以使得背光模组BLU能够呈现良好的发光均一性，并利于背光模组BLU的调试。其中，每个灯区中均具有一个或者多个发光元件(例如Mini LED或者Micro LED)，当同一灯区中具有多个发光元件时，这些发光元件可以串联、并联或者串并联混合，以使得各个发光元件可以被驱动为准，例如使得各个发光元件处于相同的电流幅值的电气通路为准，处于电气通路中的多个发光元件即构成发光电路。在本公开中，微芯片通过驱动灯区中各个发光元件的亮度，进而实现对灯区整体亮度的控制。可选的，微芯片在控制组件CTR的控制下，控制灯区中各个发光元件的亮度，进而控制灯区的亮度，使得背光模组BLU的亮度与液晶显示面板PNL的画面相互配合，提高显示效果，例如提高对比度。
当然的，上述对背光模组BLU的示例为一种有源驱动式的背光模组，能够通过微芯片实现对各个灯区的局域调光。在本公开的其他实施方式中，背光模组BLU可以不用实现局域调光，或者可以采用无源驱动的方式实现局域调光，再或者采用其他有源驱动的方式实现局域调光。
在本公开实施方式中，参见图2，阵列基板ARR可以包括依次层叠设置于衬底基板一侧的第一电极层EDLA、绝缘层PVX和第二电极层EDLB，其中，在任意一个像素区域PIXA，第一电极层EDLA和第二电极层EDLB中的一个可以设置狭缝电极SLD，另一个可以设置板状电极。狭缝电极SLD和板状电极之间产生边缘电场，用于驱动液晶层中的液晶倒伏或者翻转，进而控制液晶显示面板在该像素区域PIXA的出光。
在第一种相关技术中，液晶显示面板PNL的数据走线DataL可以倾斜设置，且狭缝电极SLD的狭缝SL与数据走线DataL的倾斜方向匹配(即平行)。在第二种相关技术中，液晶显示面板PNL的数据走线DataL可以直线设置且沿列方向DV延伸，且狭缝电极SLD的狭缝SL与行方向DH呈小角度的倾斜设置。这两种相关技术中，液晶显示面板PNL的对比度均有待进一步提升；尤其是，相关技术中的显示面板在大视角下的对比度，难以满足一些高要求的应用场景。示例性的，在车载显示器领域，上述相关技术的产品在大视角下的对比难以满足相关要求。
本公开提供一种液晶显示面板PNL，参见图2～4，液晶显示面板PNL包括依次层叠设置的衬底基板BP、第一电极层EDLA、绝缘层PVX和第二电极层EDLB；其中，所述第一电极层EDLA和所述第二电极层EDLB中的一个设置有狭缝电极SLD；所述液晶显示面板PNL还包括多个沿数据走线DataL，所述数据走线DataL临近所述狭缝电极SLD的部分沿所述列方向DV直线延伸。参见图5，所述狭缝电极SLD设置有多个狭缝SL，所述狭缝SL包括第一狭缝段SLA；所述第一狭缝段SLA的延伸方向与行方向DH的夹角在69°～85°的范围内。这样，本公开的液晶显示面板PNL中，使得数据走线DataL沿行方向DH直线排列，且使得狭缝电极SLD的第一狭缝段SLA的延伸方向接近列方向DV且与列方向DV呈一定的夹角；通过数据走线DataL和第一狭缝段SLA在布设方向上的配合，可以在保证液晶显示面板PNL的出光率等指标的前提下，提高液晶显示面板PNL的对比度，尤其是能够显著的提高液晶显示面板PNL在大视角下的对比度，使得该液晶显示面板PNL满足车载等高要求领域的应用，例如能够满足German 5.1等高端车载规格的要求。当然，该液晶显示面板PNL也可以在对显示品质具有高要求的消费级产品中应用。
在图6中，对本公开实施方式能够提高液晶显示面板PNL的对比度的原理进行了简要说明。参见图6，经过下偏光片的的线偏光Exy可以具有两个分量(S波Es和P波Ep)，即沿S分量轴(平行于SD金属线的延伸方向)的S波Es和沿P分量轴(垂直于SD金属线的延伸方向且平行于显示面板的平面)的P波Ep。该线偏光Exy遇到SD金属线(即数据走线DataL)时P波Ep变为竖直方向(垂直于显示面板平面，即Z向)， 导致显示面板平面内只有S波Es；S波Es又可分解出在上偏光片透过轴方向上的分量Exy’，Exy’即解偏振量。Exy’可透过上偏光片产生漏光。根据公式，当α为45°时，Exy’越大，漏光最严重；当α为0°时，Exy’最小，漏光最轻微。
相较于第一种相关技术，本公开实施方式中数据走线DataL沿列方向DV直线设置，使得α为0°，进而使得该液晶显示面板PNL的漏光小，这可以显著的提升液晶显示面板PNL的对比度，包括但不限于在大视角下的对比度。
相较于第二种相关技术，本公开实施方式的液晶显示面板PNL在测试中呈现更佳的光效，这也相应的使得本公开的液晶显示面板PNL具有更大的对比度；具体的，本公开实施方式的液晶显示面板在显示时，相较于第二种相关技术，其暗纹区域更小。在测试中发现，在具有相同的设计尺寸的情况下(例如狭缝宽度相同、电极梳齿宽度相同等)，本公开的液晶显示面板PNL的透光率要比第二种相关技术的透光率高8.7％；本公开的液晶显示面板在达到最大亮度时的驱动电压要低于第二种相关技术。
如下，结合附图，对本公开实施方式中的液晶显示面板PNL的结构、原理和效果做进一步的解释和说明。
参见图2和图4，阵列基板包括第一电极层EDLA和第二电极层EDLB。其中，第一电极层EDLA上设置有底电极，第二电极层EDLB上设置有与底电极对应的顶电极。在对应设置的底电极和顶电极中，底电极在衬底基板BP上的正投影与顶电极在衬底基板BP上的正投影至少部分重合。在电极的形状层面上，底电极和顶电极中的一个为狭缝电极SLD，另一个可以为板状电极。即，第一电极层EDLA和第二电极层EDLB中的一个可以设置有狭缝电极SLD，另一个可以设置有与狭缝电极SLD对应设置的板状电极。其中，在对应设置的狭缝电极SLD和板状电极中，狭缝电极SLD在衬底基板BP上的正投影与板状电极在衬底基板BP上的正投影至少部分重合。在电极的功能层面上，底电极和顶电极中的一个可以为公共电极，另一个可以为像素电极。换言之，第一电极层EDLA和第二电极层EDLB中的一个可以为设置公共电极的公共电极层，另一个可以为设置像素电极的像素电极层。
示例性地，在本公开的一种实施方式中，参见图2和图10，第一电极层EDLA设置的底电极可以为板状电极，且可以作为像素电极PIXP。参见图2和图11，第二电极层EDLB设置的顶电极，可以为狭缝电极SLD，其可以作为公共电极。
可选地，本公开的阵列基板中，第一电极层EDLA和第二电极层EDLB的材料可以为透明导电材料，例如可以为透明金属氧化物。示例性地，狭缝电极SLD的材料为ITO(氧化铟锌)。
参见图3和图4，本公开的阵列基板设置有多条扫描走线GL、多条数据走线DataL和与像素电极连接的开关晶体管；其中，开关晶体管的一端连接数据走线DataL，另一端连接像素电极，栅极连接扫描走线GL。在扫描走线GL上加载的扫描电压的控制下，开关晶体管可以导通，以使得数据走线DataL上的数据电压加载至像素电极。
参见图4，数据走线DataL与狭缝电极SLD相邻的部分沿列方向DV直线延伸；例如，数据走线DataL整体上沿列方向DV直线延伸，或者数据走线DataL在临近开关晶体管的部分可以弯折且靠近狭缝电极SLD的部分沿列方向DV直线延伸。
示例性地，在本公开的一种实施方式中，参见图4和图9，数据走线DataL为直线且沿列方向延伸；沿行方向，狭缝电极SLD的两侧均设置有数据走线DataL。
可选地，参见图4和图7，扫描走线GL可以沿行方向延伸。底电极和顶电极可以设置于相邻两个扫描走线GL之间。
在一种示例中，参见图7，栅极层设置有扫描走线GL和与扫描走线GL电连接的开关晶体管的栅极TWG。参见图8，半导体层可以包括依次连接的开关晶体管的源极接触区TWSA、开关晶体管的沟道区TWAct和开关晶体管的漏极接触区TWDA。参见图9，源漏金属层SD设置有与数据走线DataL电连接的开关晶体管的源极TWS和设置有开关晶体管的漏极TWD。其中，开关晶体管的源极TWS与开关晶体管的源极接触区TWSA之间通过过孔电连接，或者开关晶体管的源极TWS直接搭接在开关晶体管的源极接触区TWSA上；开关晶体管的漏极TWD与开关晶体管的漏极接触区TWDA之间通过过孔电连接，或者开关晶体管的漏极TWD直接搭 接在开关晶体管的漏极接触区TWDA上；开关晶体管的漏极TWD与像素电极PIXP通过过孔电连接，或者像素电极PIXP与开关晶体管的漏极TWD部分层叠设置。开关晶体管的栅极TWG与开关晶体管的沟道区TWAct交叠设置，且两者之间间隔有栅极绝缘层GI。
在本公开实施方式中，开关晶体管的有源层设于半导体层，其材料可以为非晶硅半导体材料、多晶硅半导体材料、金属氧化物半导体材料或者有机半导体材料。示例性地，在本公开的一种实施方式中，开关晶体管的有源层的材料可以为低温多晶硅半导体材料或者非晶硅；其中，源极接触区和漏极接触区可以经过离子掺杂而具有高导电性，沟道区可以保持半导体特性以相应栅极上加载的扫描信号而导通或者截止。
在一种示例中，第二电极层EDLB为公共电极层，则第二电极层EDLB还设置有公共电极线COML，顶电极与公共电极线COML电连接。进一步的，彩膜基板CF设置有黑矩阵BM，黑矩阵BM覆盖公共电极线COML。
可选的，参见图2，公共电极线COML覆盖数据走线DataL。这样，通过黑矩阵BM对公共电极线COML和数据走线DataL的覆盖，可以避免像素区域PIXA在边缘区域的亮度不均一，并限定像素区域PIXA的大小和区域。
在本公开的一种实施方式中，参见图4，每个数据走线DataL驱动两行像素，且每行像素通过两个扫描走线GL来驱动。这样，通过同一行像素的两个扫描走线GL的分时驱动，将可以将数据走线DataL上是数据分别写入同行的两个像素的像素电极中。
在图4的示例中，是以第二电极层EDLB为公共电极层且狭缝电极SLD设置于第二电极层EDLB为例进行示例的。在制备该阵列基板时，可以在衬底基板BP的一侧依次制备栅极层(用于形成扫描走线GL、开关晶体管的栅极TWG等)、栅极绝缘层GI、半导体层、第一电极层EDLA、源漏金属层SD、绝缘层PVX和第二电极层EDLB等膜层。在一些示例中，阵列基板还可以包括覆盖第二电极层EDLB的取向层。
在本公开的其他实施方式中，该液晶显示面板PNL还可以为其他方式，例如第二电极层EDLB可以为像素电极层且第一电极层EDLA为公共电极层；再例如底电极为狭缝电极SLD且顶电极为板状电极。示例性的， 参见图12，第一电极层EDLA为公共电极层，其设置的底电极可以作为与像素电极PIXP交叠的公共电极；第一电极层EDLA还设置有与底电极连接的公共电极线COML，以便向底电极加载公共电压。第二电极层EDLB为像素电极层，其设置的顶电极为狭缝电极SLD，狭缝电极SLD与底电极交叠设置。其中，在第一电极层EDLA和源漏金属层SD之间，可以设置有有机绝缘层ORG。
参见图5，所述狭缝电极SLD设置有多个狭缝SL，所述狭缝SL包括第一狭缝段SLA；所述第一狭缝段SLA的延伸方向与行方向DH的夹角在69°～85°的范围内。更进一步的，所述第一狭缝段SLA的延伸方向与所述行方向DH的夹角在79°～85°之间，尤其是，所述第一狭缝段SLA的延伸方向与所述行方向DH的夹角为79°或者83°。本公开的液晶显示面板PNL中，通过对第一狭缝段SLA的倾斜角度的限定，可以在液晶显示面板PNL的光效(透光率Tr)和液晶恢复时间之间达到平衡，使得液晶显示面板PNL具有高光效的同时保持较快的恢复速度，避免单纯提高光效和对比度而对液晶显示面板PNL的刷新率产生影响。
可选的，在本公开的液晶显示面板PNL中，在第一狭缝段SLA的倾斜角度可行的范围内，可以通过增大第一狭缝段SLA的倾斜角(增大第一狭缝段SLA与行方向DH之间的锐角夹角)来提高液晶显示面板PNL的光效；即第一狭缝段SLA越竖直(越靠近列方向DV方向)，则液晶显示面板PNL的出光率越高。相应的，可以通过减小第一狭缝段SLA的倾斜角来提高液晶显示面板PNL的刷新率。
在本公开的一种实施方式中，参见图5，至少部分所述狭缝SL还包括第二狭缝段SLB和第三狭缝段SLC中的至少一者。
所述第二狭缝段SLB与所述第一狭缝段SLA的一端连接，所述第三狭缝段SLC与所述第一狭缝段SLA的另一端连接；沿所述列方向DV，所述第二狭缝段SLB和所述第三狭缝段SLC分别位于所述第一狭缝段SLA的两侧。所述第二狭缝段SLB远离所述第一狭缝段SLA的端部与所述第一狭缝段SLA远离所述第二狭缝段SLB的端部之间的连线与所述行方向DH之间的锐角夹角，小于所述第一狭缝段SLA与所述行方向DH之间的锐角夹角。所述第三狭缝段SLC远离所述第一狭缝段SLA的端部 与所述第一狭缝段SLA远离所述第三狭缝段SLC的端部之间的连线与所述行方向DH之间的锐角夹角，小于所述第一狭缝段SLA与所述行方向DH之间的锐角夹角。
换言之，液晶显示面板PNL的各个狭缝SL可以根据需求，在第一狭缝段SLA之外可以额外设置第二狭缝段SLB或者第三狭缝段SLC。这样，可以均衡像素区域PIXA边缘处的电场，提高PIX的亮度均一性。可以理解的是，在本公开的实施方式中，第二狭缝段SLB和第三狭缝段SLC并不是必需的；狭缝SL可以仅设置第一狭缝段SLA和第二狭缝段SLB，也可以仅设置第一狭缝段SLA和第三狭缝段SLC，还可以仅设置第一狭缝段SLA，当然的，也可以同时设置依次连接的第二狭缝段SLB、第一狭缝段SLA和第三狭缝段SLC。
在本公开的一种实施方式中，至少部分所述狭缝SL包括依次连接的第二狭缝段SLB、第一狭缝段SLA和第三狭缝段SLC，例如不临近像素区域PIXA边缘的各个狭缝SL均包括依次连接的第二狭缝段SLB、第一狭缝段SLA和第三狭缝段SLC。这样，可以提高像素区域PIXA亮度的均一性。
在本公开的一种实施方式中，所述第二狭缝段SLB与所述行方向DH的夹角在50°～60°之间。相应的，所述第三狭缝段SLC与所述行方向DH的夹角在50°～60°之间。
在本公开的一种实施方式中，当狭缝SL设置有第二狭缝段SLB时，所述第二狭缝段SLB与所述第一狭缝段SLA宽度相同，且长度小于所述第一狭缝段SLA。这样，一方面可以提高像素区域PIXA的亮度均一性，又避免第二狭缝段SLB太大而影响光效。
在本公开的一种实施方式中，当狭缝SL设置有第三狭缝段SLC时，所述第三狭缝段SLC与所述第一狭缝段SLA宽度相同，且长度小于所述第一狭缝段SLA。这样，一方面可以提高像素区域PIXA的亮度均一性，又避免第三狭缝段SLC太大而影响光效。
在本公开的一种实施方式中，参见图5，所述狭缝电极SLD包括多个狭缝组SLS，所述狭缝组SLS包括具有共同端部的两个所述狭缝SL。沿所述行方向DH，所述狭缝组SLS的两个所述狭缝SL均位于所述共同端 部的同一侧；沿所述列方向DV，所述狭缝组SLS的两个所述狭缝SL分别位于所述共同端部的两侧。这样，该像素区域PIXA内可以实现1P(一个像素)2D(两个畴区)，提高液晶显示面板PNL的可视角。这样，本公开的液晶显示面板PNL可以实现大可视角且高对比度，尤其是能够在大视角下就有高对比度。进一步的，该实施方式中，液晶显示面板PNL的分辨率可以不太高，例如PPI可以不大于280，以提高液晶显示面板PNL可制备性。
在一种示例中，参见图5，所述狭缝组SLS的两个所述狭缝SL的第一狭缝段SLA的延伸方向关于所述行方向DH镜像对称。这样，可以提高不同畴区的均一性，进而提高不同方向的视角下的画面均一性。
在一种示例中，参见图5，所述狭缝组SLS中的任意一个所述狭缝SL还包括靠近所述共同端部的第二狭缝段SLB；所述狭缝SL的第一狭缝段SLA位于所述第二狭缝段SLB远离所述共同端部的一侧；所述第二狭缝段SLB远离所述第一狭缝段SLA的端部与所述第一狭缝段SLA远离所述第二狭缝段SLB的端部之间的连线与所述行方向DH之间的锐角夹角，小于所述第一狭缝段SLA与所述行方向DH之间的锐角夹角。这样，可以使得两个狭缝SL连接处的出光率与其他区域基本一致，提高像素区域PIXA内亮度的均一性，避免因狭缝SL角度突变而引起的光效突变。
在一种示例中，所述狭缝组SLS的两个所述狭缝SL的第二狭缝段SLB的延伸方向关于所述行方向DH镜像对称。
在本公开的另一种实施方式中，液晶显示面板PNL还可以采用2P2D(2像素2畴区)或者4P4D(4像素4畴区)的架构来提高可视角，例如在较高分辨率的显示面板中(例如PPI大于280的显示面板)或者在对画面质量要求不太高的产品中。
在一种示例中，参见图13，在沿行方向DH相邻的两个所述狭缝电极SLD中，两个所述狭缝电极SLD的第一狭缝段SLA的延伸方向关于所述列方向DV镜像对称。这样，可以实现2P2D效果。
在另一种示例中，参见图14，在沿列方向DV相邻的两个狭缝电极SLD中，两个所述狭缝电极SLD的第一狭缝段SLA的延伸方向关于所述行方向DH镜像对称。这样，可以实现2P2D效果。
在另一种示例中，参见图15，在沿行方向DH相邻的两个所述狭缝电极SLD中，两个所述狭缝电极SLD的第一狭缝段SLA的延伸方向关于所述列方向DV镜像对称；在沿列方向DV相邻的两个狭缝电极SLD中，两个所述狭缝电极SLD的第一狭缝段SLA的延伸方向关于所述行方向DH镜像对称。这样，可以实现4P4D的效果。
在本公开的一种实施方式中，所述第一狭缝段SLA的宽度在3.4微米～5.6微米之间。
在本公开的一种实施方式中，所述狭缝电极SLD包括位于相邻两个所述第一狭缝段SLA之间的电极梳齿DA，所述电极梳齿DA的宽度在2.0微米～3.4微米之间。
在本公开的一种实施方式中，所述第一狭缝段SLA的宽度与所述电极梳齿DA的宽度的比值在1～2.4之间。
当然的，对于不同的液晶显示面板PNL，例如具有不同PPI或者不同像素尺寸的液晶显示面板PNL，第一狭缝段SLA的宽度、电极梳齿DA的宽度/第一狭缝段SLA的宽度与所述电极梳齿DA的宽度的比值等，可以根据需要进行调整，以使得液晶显示面板PNL的品质均衡。
在一种示例中，所述第一狭缝段SLA的宽度在4.1～4.5微米之间；所述电极梳齿DA的宽度在2.3～2.7微米之间。这样，可以使得该液晶显示面板PNL具有较高的光效和较好的恢复时间。
在另一种示例中，狭缝电极为公共电极，沿行方向，相邻狭缝电极之间设置有公共电极线COML。第一狭缝段SLA的宽度为3.8微米，电极梳齿DA的宽度为2.7微米；公共电极线COML的宽度为9.6微米，且覆盖数据线DataL。数据线DataL的宽度为3.5微米，这使得公共电极线COML单边超过数据线DataL3.05微米。像素电极为板状电极且位于第一电极层，像素电极的边缘与数据线DataL之间的间距为4.35微米。彩膜基板上设置有黑矩阵；沿行方向，两个像素之间的黑矩阵BM的宽度为7.0微米，且单边超出数据线DataL 1.75微米。
在本公开的另一种实施方式中，所述第一狭缝段SLA的宽度在4.4～4.6微米之间；所述电极梳齿DA的宽度在2.7～2.9微米之间。这样，也可以使得该液晶显示面板PNL具有较高的光效和较好的恢复时间。
本公开实施方式中，还测试了不同的第一狭缝段SLA、电极梳齿DA的尺寸对液晶显示面板PNL的光效的影响。
举例而言，在第一组测试中，依次对测试例1～测试例6进行了测试，具体数据请参见表1：
表1
Figure PCTCN2022103074-appb-000001
其中，W为电极梳齿DA的宽度；S为第一狭缝段SLA的宽度；Pitch为设置间距，即为W+S；两个间隙(Space)分别为沿行方向最外侧的两个狭缝SL与对应的底电极的边缘之间的距离；总宽为狭缝电极沿行方向的尺寸。W、S、Pitch、间隙和总宽的单位均为微米。Vop为像素达到最大亮度时的驱动电压，单位为V。Tr为光效(透光率)；Tr(％)是指以测试例6的光效为基准(100％)，各个测试例的光效的归一化数据。
根据表1的数据可知，通过对电极梳齿DA的宽度、第一狭缝段SLA的宽度的优化，例如在测试例1和测试例5中的优化，可以在提高液晶显示面板PNL的出光率。
再举例而言，在第二组测试中，测试了多个不同的测试例。具体数据请参见表2，每一行表示一个测试例中狭缝电极的参数和相关测试结果。在该第二组测试中，每个狭缝电极设置有8条狭缝。
表2
Pitch(um) W(μm) S(um) 2ITO-2ITO W/S Vop(V) 亮度归一化
6.8 2 4.8 13.43 41.67％ 6.0V 99.3％
6.8 2.1 4.7 13.33 44.68％ 5.9V 99.7％
6.8 2.2 4.6 13.23 47.83％ 5.9V 99.8％
6.8 2.3 4.5 13.13 51.11％ 5.9V 100.0％
6.8 2.4 4.4 13.03 54.55％ 5.9V 100.2％
6.8 2.5 4.3 12.93 58.14％ 5.9V 100.1％
6.8 2.6 4.2 12.83 61.90％ 5.9V 100.0％
6.8 2.7 4.1 12.73 65.85％ 5.9V 99.8％
6.8 2.8 4 12.63 70.00％ 5.9V 99.6％
6.8 2.9 3.9 12.53 74.36％ 5.9V 99.2％
6.8 3 3.8 12.43 78.95％ 5.9V 98.6％
6.8 3.1 3.7 12.33 83.78％ 6.0V 98.0％
6.8 3.2 3.6 12.23 88.89％ 6.1V 97.3％
6.8 3.3 3.5 12.13 94.29％ 6.1V 96.4％
6.8 3.4 3.4 12.03 100.00％ 6.2V 95.2％
7 2.4 4.6 11.63 52.17％ 5.8V 98.7％
7 2.5 4.5 11.53 55.56％ 5.8V 98.7％
7 2.6 4.4 11.43 59.09％ 5.8V 98.5％
7 2.7 4.3 11.33 62.79％ 5.8V 98.3％
在表2中，2ITO-2ITO表示两个狭缝电极之间的间距。通过表2可以看出，当W为2微米、S为4.2微米时，该液晶显示面板PNL可以具有较高的亮度，且在其他测试中发现，这种设置方式还可以减小亮度波动，即实现了亮度波动和高光效的平衡。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (21)

  1. 一种阵列基板，包括依次层叠设置的衬底基板、第一电极层、绝缘层和第二电极层；其中，所述第一电极层和所述第二电极层中的一个设置有狭缝电极；所述阵列基板还包括多个数据走线，所述数据走线临近所述狭缝电极的部分沿所述列方向直线延伸；
    所述狭缝电极设置有多个狭缝，所述狭缝包括第一狭缝段；所述第一狭缝段的延伸方向与行方向的夹角在69°～85°的范围内。
  2. 根据权利要求1所述的阵列基板，其中，所述第一狭缝段的延伸方向与所述行方向的夹角在79°～85°之间。
  3. 根据权利要求1所述的阵列基板，其中，所述第一狭缝段的延伸方向与所述行方向的夹角为79°或者83°。
  4. 根据权利要求1所述的阵列基板，其中，至少部分所述狭缝还包括第二狭缝段和第三狭缝段中的至少一者；所述第二狭缝段与所述第一狭缝段的一端连接，所述第三狭缝段与所述第一狭缝段的另一端连接；沿所述列方向，所述第二狭缝段和所述第三狭缝段分别位于所述第一狭缝段的两侧；
    所述第二狭缝段远离所述第一狭缝段的端部与所述第一狭缝段远离所述第二狭缝段的端部之间的连线与所述行方向之间的锐角夹角，小于所述第一狭缝段的延伸方向与所述行方向之间的锐角夹角；
    所述第三狭缝段远离所述第一狭缝段的端部与所述第一狭缝段远离所述第三狭缝段的端部之间的连线与所述行方向之间的锐角夹角，小于所述第一狭缝段的延伸方向与所述行方向之间的锐角夹角。
  5. 根据权利要求4所述的阵列基板，其中，至少部分所述狭缝包括依次连接的第二狭缝段、第一狭缝段和第三狭缝段。
  6. 根据权利要求4所述的阵列基板，其中，所述第二狭缝段的延伸方向与所述行方向的夹角在50°～60°之间；和/或，
    所述第三狭缝段的延伸方向与所述行方向的夹角在50°～60°之间。
  7. 根据权利要求4所述的阵列基板，其中，所述第二狭缝段与所述第一狭缝段宽度相同，且长度小于所述第一狭缝段；和/或，
    所述第三狭缝段与所述第一狭缝段宽度相同，且长度小于所述第一狭 缝段。
  8. 根据权利要求1所述的阵列基板，其中，所述狭缝电极包括多个狭缝组，所述狭缝组包括具有共同端部的两个所述狭缝；
    沿所述行方向，所述狭缝组的两个所述狭缝均位于所述共同端部的同一侧；
    沿所述列方向，所述狭缝组的两个所述狭缝分别位于所述共同端部的两侧。
  9. 根据权利要求8所述的阵列基板，其中，所述狭缝组的两个所述狭缝的第一狭缝段的延伸方向关于所述行方向镜像对称。
  10. 根据权利要求8所述的阵列基板，其中，所述狭缝组中的任意一个所述狭缝还包括靠近所述共同端部的第二狭缝段；所述狭缝的第一狭缝段位于所述第二狭缝段远离所述共同端部的一侧；
    所述第二狭缝段远离所述第一狭缝段的端部与所述第一狭缝段远离所述第二狭缝段的端部之间的连线与所述行方向之间的锐角夹角，小于所述第一狭缝段与所述行方向之间的锐角夹角。
  11. 根据权利要求10所述的阵列基板，其中，所述狭缝组的两个所述狭缝的第二狭缝段的延伸方向关于所述行方向镜像对称。
  12. 根据权利要求1所述的阵列基板，其中，在沿行方向相邻的两个所述狭缝电极中，两个所述狭缝电极的第一狭缝段的延伸方向关于所述列方向镜像对称。
  13. 根据权利要求1所述的阵列基板，其中，在沿列方向相邻的两个狭缝电极中，两个所述狭缝电极的第一狭缝段的延伸方向关于所述行方向镜像对称。
  14. 根据权利要求1所述的阵列基板，其中，在沿行方向相邻的两个所述狭缝电极中，两个所述狭缝电极的第一狭缝段的延伸方向关于所述列方向镜像对称；在沿列方向相邻的两个狭缝电极中，两个所述狭缝电极的第一狭缝段的延伸方向关于所述行方向镜像对称。
  15. 根据权利要求1～14任意一项所述的阵列基板，其中，所述第一狭缝段的宽度在3.4微米～5.6微米之间。
  16. 根据权利要求1～14任意一项所述的阵列基板，其中，所述狭缝 电极包括位于相邻两个所述第一狭缝段之间的电极梳齿，所述电极梳齿的宽度在2.0微米～3.4微米之间。
  17. 根据权利要求1～14任意一项所述的阵列基板，其中，所述第一狭缝段的宽度与所述电极梳齿的宽度的比值在1～2.4之间。
  18. 根据权利要求1～14任意一项所述的阵列基板，其中，所述第一狭缝段的宽度在4.1～4.5微米之间；所述电极梳齿的宽度在2.3～2.7微米之间。
  19. 根据权利要求1～14任意一项所述的阵列基板，其中，所述第一狭缝段的宽度在4.4～4.6微米之间；所述电极梳齿的宽度在2.7～2.9微米之间。
  20. 根据权利要求1～14任意一项所述的阵列基板，其中，所述狭缝电极位于所述第二电极层。
  21. 一种液晶显示面板，包括对盒设置的阵列基板和彩膜基板，以及包括夹设于阵列基板和彩膜基板中的液晶层；所述阵列基板为权利要求1～20任意一项所述的阵列基板。
PCT/CN2022/103074 2022-06-30 2022-06-30 阵列基板和液晶显示面板 WO2024000492A1 (zh)

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