WO2023279241A1 - Led芯片、led阵列及电子设备 - Google Patents

Led芯片、led阵列及电子设备 Download PDF

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Publication number
WO2023279241A1
WO2023279241A1 PCT/CN2021/104545 CN2021104545W WO2023279241A1 WO 2023279241 A1 WO2023279241 A1 WO 2023279241A1 CN 2021104545 W CN2021104545 W CN 2021104545W WO 2023279241 A1 WO2023279241 A1 WO 2023279241A1
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Prior art keywords
layer
led chip
type semiconductor
led
carbon nanotube
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PCT/CN2021/104545
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English (en)
French (fr)
Inventor
蔡明达
张杨
陈靖中
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重庆康佳光电技术研究院有限公司
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Priority to PCT/CN2021/104545 priority Critical patent/WO2023279241A1/zh
Publication of WO2023279241A1 publication Critical patent/WO2023279241A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

  • the present application relates to the technical field of LEDs, in particular to an LED chip, an LED array and electronic equipment.
  • the N-type semiconductor layer and the P-type semiconductor layer respectively inject electrons and holes into the active layer, allowing the electrons and holes to recombine in the active layer to convert electrical energy into light energy and excite light; at the same time , the energy that is not converted into light energy will be radiated as heat energy. It is understandable that the radiated heat will increase the temperature of the LED chip, and the high temperature will not only affect the reliability of the LED chip, but also cause some carriers (electrons and holes) to overflow, resulting in "light saturation” phenomenon (ie The light output no longer increases with the increase of the current), which in turn affects the luminous efficiency of the LED chip.
  • the purpose of this application is to provide an LED chip, LED array and electronic equipment, aiming at solving the problem that carrier overflow affects the light extraction efficiency of the LED chip.
  • the application provides an LED chip, including an epitaxial layer and an electrode; the epitaxial layer includes:
  • the electrodes include an N electrode electrically connected to the N-type semiconductor layer, and a P electrode electrically connected to the P-type semiconductor layer; the active layer and the electron blocking layer are both located between the N-type semiconductor layer and the P-type semiconductor layer, and the electron blocking layer The active layer is closer to the N-type semiconductor layer than the active layer.
  • the active layer and the electron blocking layer are located between the N-type semiconductor layer and the P-type semiconductor layer, and the electron blocking layer is closer to the N-type semiconductor layer than the active layer.
  • the electron blocking layer can be used to limit the number of electrons injected into the active layer by the N-type semiconductor layer, suppress carrier overflow, and avoid light saturation, thereby improving the light emission of the LED chip. output efficiency.
  • the present application also provides an LED array, which includes at least two LED chips according to any one of the foregoing items, and the semiconductor layers of each LED chip are electrically connected to each other.
  • an electron blocking layer is set between the active layer and the N-type semiconductor layer in the LED chip, which can The electron blocking layer can limit the number of electrons injected into the active layer by the N-type semiconductor layer, suppress carrier overflow, avoid light saturation, and further improve the light output efficiency of the LED array.
  • the present application also provides an electronic device, which includes a driving circuit and the LED chip in any one of the foregoing items; electrodes of the LED chip are electrically connected to the driving circuit.
  • an electron blocking layer is set between the active layer and the N-type semiconductor layer, so that the electron blocking layer can be used to limit the number of electrons injected into the active layer by the N-type semiconductor layer, and suppress Carrier overflow avoids light saturation, further improves the light output efficiency of LED chips, and enhances the quality of electronic equipment .
  • the active layer and the electron blocking layer are located between the N-type semiconductor layer and the P-type semiconductor layer, and the electron blocking layer is closer to the N-type semiconductor layer than the active layer.
  • the electron blocking layer can be used to limit the number of electrons injected into the active layer by the N-type semiconductor layer, suppress carrier overflow, and avoid light saturation, thereby improving the light emission of the LED chip. output efficiency.
  • an electron blocking layer is set between the active layer and the N-type semiconductor layer in the LED chip, which can The electron blocking layer can limit the number of electrons injected into the active layer by the N-type semiconductor layer, suppress carrier overflow, avoid light saturation, and further improve the light output efficiency of the LED array.
  • an electron blocking layer is set between the active layer and the N-type semiconductor layer, so that the electron blocking layer can be used to limit the number of electrons injected into the active layer by the N-type semiconductor layer, and suppress Carrier overflow avoids light saturation, further improves the light output efficiency of LED chips, and enhances the quality of electronic equipment.
  • FIG. 1 is a schematic structural diagram of a first LED chip provided in an optional embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a second LED chip provided in an optional embodiment of the present application.
  • Fig. 3 is a schematic structural diagram of a third LED chip provided in an optional embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a heat dissipation substrate provided in an alternative embodiment of the present application.
  • Fig. 5 is a schematic structural diagram of a fourth LED chip provided in an optional embodiment of the present application.
  • Fig. 6 is a schematic structural diagram of a fifth LED chip provided in an alternative embodiment of the present application.
  • Fig. 7 is a schematic structural diagram of the first LED array provided in an alternative embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of a second LED array provided in an alternative embodiment of the present application.
  • FIG. 9 is a schematic structural view of a composite wire layer provided in an optional embodiment of the present application.
  • Fig. 10a is a schematic diagram of wiring of a composite wiring layer in an LED array in an optional embodiment of the present application
  • Figure 10b is a schematic diagram of the equivalent circuit connection of the LED array in Figure 10a;
  • Fig. 11a is another schematic diagram of wiring of a composite wire layer in an LED array in an optional embodiment of the present invention.
  • Figure 11b is a schematic diagram of the equivalent circuit connection of the LED array in Figure 11a;
  • Fig. 12 is a schematic structural diagram of an ultraviolet LED chip provided in another optional embodiment of the present application.
  • Fig. 13 is a schematic structural diagram of an ultraviolet LED array provided in another alternative embodiment of the present application.
  • 10-LED chip 11-epitaxy layer; 111-N type semiconductor layer; 112-electron blocking layer; 113-active layer; 114-P type semiconductor layer; 12-electrode; 121-N electrode; 122-P electrode; 13-growth substrate; 14-heat dissipation substrate; 141-CVD-diamond layer; 142-carbon nanotube array layer; 143-silicon substrate layer; 15-bonding layer; 20-LED chip; 30-LED chip; 50- LED chip; 60-LED chip; 7-LED array; 70-LED chip; 8-LED array; 80-LED chip; 813-upper isolation layer; 100-LED array; 110-LED array; 120-ultraviolet LED chip; 1211-N type semiconductor layer; 1212-electron blocking layer; 1213-active layer; 1214-P type semiconductor layer 1214; -N electrode; 1222-P electrode; 123-growth substrate; 1241-silicon substrate layer; 1242-carbon nanotube array layer; 1243-CVD-diamond
  • This embodiment provides an LED chip, please refer to the schematic structural diagram of the LED chip shown in Figure 1:
  • the LED chip 10 includes an epitaxial layer 11 and an electrode 12, wherein the epitaxial layer 11 includes an N-type semiconductor layer 111, an active layer 113, and a P-type semiconductor layer 114, and the active layer 113 is located between the N-type semiconductor layer 111 and the P-type semiconductor layer 114. between.
  • the N-type semiconductor layer 111 is an N-type doped semiconductor layer
  • the P-type semiconductor layer 114 is a P-type doped semiconductor layer
  • the N-type doped doping sources include but are not limited to silicon sources, boron sources, and germanium sources. Any one of them; taking the silicon source as an example, SiH 4 (monosilane), Si 2 H 6 (disilane), etc. can be selected as the doping source.
  • the doping source of P-type doping includes but not limited to at least one of magnesium source and zinc source. For example, when magnesium source is used as the doping source, Cp2Mg (dimagnesium) can be selected.
  • the electrodes 12 include an N electrode (not shown in FIG. 1 ) electrically connected to the N-type semiconductor layer 111 , and a P electrode 122 electrically connected to the P-type semiconductor layer 114 .
  • the P electrode 122 is directly arranged on the P-type semiconductor layer 114 in FIG. 1 , those skilled in the art should understand that the electrical connection between the electrode and the corresponding semiconductor layer is not necessarily a direct connection, and may also be indirectly through a conductor. connect.
  • the epitaxial layer 11 further includes an electron blocking layer 112, and the electron blocking layer 112 is also located between the N-type semiconductor layer 111 and the P-type semiconductor layer 114, but the electron blocking layer 112 is closer to the N-type semiconductor layer than the active layer 113.
  • the semiconductor layer 111 that is, the distance between the electron blocking layer 112 and the N-type semiconductor layer 111 is smaller than the distance between the active layer 112 and the N-type semiconductor layer 111.
  • the electron blocking layer 112 is arranged between the active layer 113 and the N-type semiconductor layer. Between the semiconductor layers 111.
  • the electron blocking layer 112 is used to limit the number of electrons injected into the active layer 113 by the N-type semiconductor layer 111, so as to prevent excessive electrons in the active layer 113 from recombining with holes and overflowing into the P-type semiconductor layer 114, The conversion of electronic energy to thermal energy is reduced, the heating problem of the LED chip 10 is alleviated, and the effective conversion rate of electric energy is improved. At the same time, because the light saturation limitation in the LED chip 10 is suppressed, the light extraction efficiency of the LED chip 10 is improved. .
  • the electron blocking layer 112 in order to limit electrons injected from the N-type semiconductor layer 111 to the active layer 113, the electron blocking layer 112 should have a larger energy gap.
  • the band gap of the electron blocking layer 112 The gap is between 5.6eV ⁇ 8.7eV.
  • the bandgap of the electron blocking layer 112 is 5.6eV (SiN, silicon nitride), and in another example, the bandgap of the electron blocking layer is 7.8eV ( MgO, magnesium oxide), and in another example, the band gap of the electron blocking layer 112 is 6.2eV (AlN, aluminum nitride), and in another example, the band gap of the electron blocking layer 112 is 8.7eV (Al 2 O 3 , Al2O3).
  • the electron blocking layer 112 may be a superlattice structure layer, such as a ZnMgO/AlGaN (zinc magnesium oxide/aluminum gallium nitride) superlattice structure layer, AlN/AlGaN (aluminum nitride/aluminum gallium nitride) Nitrogen) superlattice structure layer, AlGaN/InGaN (aluminum gallium nitride/indium gallium nitride) superlattice structure layer; in some examples, the electron blocking layer 112 can also be formed of a single material, for example, in an example, electron The barrier layer 112 is an AlGaN layer.
  • the electron blocking layer 112 may include h-BN (hexagonal boron nitride), and the energy gap of the h-BN material is 6.4 eV.
  • the electron blocking layer 112 is an h-BN layer.
  • h-BN also known as white graphite
  • h-BN is similar to the hexagonal carbon network in graphite.
  • Nitrogen and boron in hexagonal boron nitride also form hexagonal network layers, which overlap each other to form crystals.
  • the crystal is similar to graphite, with diamagnetism and high anisotropy, and the crystal parameters are quite similar.
  • the epitaxial layer 11 is not limited to the four layers of the N-type semiconductor layer 111, the electron blocking layer 112, the active layer 113, and the P-type semiconductor layer 114. In some other examples, the epitaxial layer 11 may also include a buffer layer, intrinsic layer, ohmic contact layer and other layer structures.
  • the LED chip further includes a growth substrate.
  • the growth substrate 13 is located under the epitaxial layer 11 , and the growth substrate 13 may be a nitride growth substrate, for example, in one example, the growth substrate 13 may be a GaN (gallium nitride) growth substrate.
  • the lattice constant of the electron blocking layer 112 is generally smaller than that of the growth substrate 13.
  • its lattice constant is 5.2 angstroms
  • the lattice constant of the h-BN material constant is 2.5 angstroms
  • the lattice constant of the electron blocking layer 112 is smaller than the lattice constant of the growth substrate 13, which will result in Lattice mismatch strain in the stretching direction occurs inside the barrier layer 112 , affecting the crystal quality of the epitaxial layer 11 .
  • this embodiment also provides an LED chip, as shown in Figure 3:
  • a heat dissipation substrate 14 is also provided, wherein the heat dissipation substrate 14 is arranged on the side of the growth substrate 13 away from the epitaxial layer 11, and its thermal expansion coefficient It is smaller than the thermal expansion coefficient of each layer structure above it, but its thermal conductivity is greater than the thermal conductivity of each layer structure above it.
  • the thermal expansion coefficient of the heat dissipation substrate 14 is smaller than that of the growth substrate 13 and the epitaxial layer 11.
  • the thermal conductivity of is greater than the thermal conductivity of the growth substrate 13 and the epitaxial layer 11.
  • the heat-dissipating base material 14 can also help the layers above it to dissipate heat, improve the heat-dissipating performance of the LED chip 30 , and alleviate the problem of carrier overflow.
  • the heat dissipation substrate 14 includes CVD (Chemical Vapor Deposition)-diamond, because CVD-diamond is a material with a very high thermal conductivity (1500 W/mK) and a small thermal expansion coefficient (2.2).
  • the heat dissipation substrate 14 includes a CVD-diamond layer. By using the CVD-diamond layer, compressive strain can be generated in each layer structure of the LED chip, thereby relieving the tension in the electron blocking layer 112. strain.
  • the heat dissipation substrate 14 is a composite layer structure.
  • the tube array layer 142 is located on the side of the CVD-diamond layer 141 away from the growth substrate 13 .
  • Carbon Nanotube (CNT) also known as bucky tube, is mainly composed of carbon atoms arranged in a hexagonal shape to form a coaxial circular tube with several to dozens of layers. It is a special structure (the radial dimension is A one-dimensional quantum material with a nanometer level, an axial dimension of the micron level, and both ends of the tube are basically sealed).
  • carbon nanotubes are light in weight, perfectly connected in a hexagonal structure, and have many unusual mechanical, electrical, and chemical properties. Moreover, carbon nanotubes have excellent thermal conductivity, and their thermal conductivity can reach 3500W/mK at room temperature, and can reach 6000W/mK under extreme conditions. Therefore, the use of carbon nanotube material to form the carbon nanotube array layer 142 in this embodiment can greatly help the LED chip to dissipate heat, enhance the heat dissipation performance of the LED chip, prevent it from being in a high temperature environment for a long time, and improve the quality of the LED chip.
  • Carbon nanotube materials can be prepared by any one of several methods such as arc discharge method, laser ablation method, solid phase pyrolysis method, ion or laser sputtering method, polymerization reaction synthesis, catalytic cracking method, etc.
  • the carbon nanotube material can be single-walled carbon nanotubes, double-walled carbon nanotubes or multi-walled carbon nanotubes, and even in some examples, the carbon nanotube array layer 142 can be made of two or more types Carbon nanotube materials are co-formed.
  • the heat dissipation base material 14 also includes a silicon substrate layer.
  • a silicon substrate layer Please refer to the schematic structural diagram of an LED chip shown in FIG. The bottom layer 143 , the carbon nanotube array layer 142 and the CVD-diamond layer 141 , wherein the silicon substrate layer 143 is farthest from the growth substrate 13 .
  • the silicon substrate layer 143 is provided in the heat dissipation base material 14, so that the silicon substrate layer 143 can be directly doped when the driving circuit for the LED chip 50 is provided subsequently, thereby simplifying the design of the driving circuit for the LED chip 50.
  • the setting process improves the market competitiveness of the LED chip 50 .
  • the silicon substrate layer 143 can be combined with the carbon nanotube array layer 142 to form a composite substrate, and then the composite substrate can be combined with the CVD-diamond layer 141 .
  • a silicon substrate layer 143 when preparing the composite substrate, can be provided first, and then spray pyrolysis method, thermal chemical vapor deposition method, spin coating method, etc. on the silicon substrate layer 143. Any one of the carbon nanotube array layers 142 is formed.
  • the prepared metallic carbon nanotube material can be dispersed in the dispersion liquid, and then the dispersion liquid is spin-coated on the silicon substrate layer 143, and then the dispersion liquid is removed to obtain the carbon nanotube array A composite substrate of layer 142 and silicon substrate layer 143 .
  • the heat dissipation substrate 14 may not include the carbon nanotube array layer 142 , and only the CVD-diamond layer 141 and the silicon substrate layer 143 are provided. In some other examples, the heat dissipation substrate 14 may also be formed by other materials, or be formed by combining at least one of CVD, carbon nanotube material, and silicon material with other materials.
  • a bonding layer is also provided in the LED chip, please refer to FIG. 6 : the LED chip 60 is provided with a Bonding layer 15, it can be understood that the heat dissipation substrate 14 can be bonded to the growth substrate 13 in various ways, for example, in an example of this embodiment, the heat dissipation substrate 14 and the growth substrate 13 are bonded by metal In this example, the bonding layer 15 is a metal bonding layer.
  • the LED chip 60 has a vertical structure, therefore, its P electrode 122 and N electrode 121 are respectively arranged on opposite sides of the epitaxial layer 11, for example, in FIG.
  • the N electrode 121 is a metal electrode layer, as long as a metal bonding layer is also provided on the side of the heat dissipation substrate 14 facing the growth substrate 13, the metal bonding layer can be metal bonded to the N electrode 121, thereby The heat dissipation substrate 14 is combined with the growth substrate 13 .
  • the LED chip itself is not a vertical structure, for example, the LED chip is a flip-chip LED chip, and its N electrode is arranged on the side of the N-type semiconductor layer facing the active layer, it can also be directly grown
  • Another metal bonding layer is provided on the side of the substrate 13 facing the heat dissipation substrate 14 , so that the growth substrate 13 and the heat dissipation substrate 14 are bonded through the two metal bonding layers.
  • the growth substrate 13 and the heat dissipation substrate 14 can be eutectically bonded, in this case, the bonding layer 15 is a eutectic bonding layer, and the eutectic bonding layer includes two A eutectic bonding sublayer of the same material, such as a eutectic bonding sublayer formed by AuSn (gold-tin eutectic/gold-tin alloy) solder (it can be understood that the material of the eutectic bonding sublayer includes but is not limited to AuSn) .
  • AuSn gold-tin eutectic/gold-tin alloy
  • two eutectic bonding sublayers are respectively arranged on the growth substrate 13 and the heat dissipation substrate 14, and the two are opposite.
  • the two eutectic bonding sub-layers can be bonded together so that they overlap each other to form a eutectic bonding layer, so as to realize the bonding of the growth substrate 13 and the heat dissipation substrate 14 .
  • This embodiment also provides an LED array, the LED array includes at least two LED chips, and the LED chips can be any one of the LED chips in the foregoing examples.
  • the semiconductor layers (N-type semiconductor layer 111 and P-type semiconductor layer 114 ) of each LED chip are electrically connected to each other, that is, the semiconductor layer of one LED chip is electrically connected to the semiconductor layer of another LED chip.
  • the N-type semiconductor layer of one LED chip is electrically connected to the N-type semiconductor layer of another LED chip; or, the P-type semiconductor layer of one LED chip is electrically connected to the P-type semiconductor layer of another LED chip; Alternatively, the N-type semiconductor layer of one LED chip is electrically connected to the P-type semiconductor layer of another LED chip; The N-type semiconductor layer of the chip is electrically connected, and its P-type semiconductor layer can also be electrically connected with the N-type semiconductor layer of the other LED chip.
  • the electrical connection of the semiconductor layers of different LED chips can be a direct electrical connection of the semiconductor layers or an indirect electrical connection.
  • the N-type semiconductor layer 111 is equivalent to the direct electrical connection of the N-type semiconductor layer 111 of each LED chip 70; in some examples, the electrodes of each LED chip are electrically connected through interconnection wires, which is equivalent to the semiconductor layer of each LED chip indirect electrical connection.
  • the LED array 8 shown in FIG. P electrodes 122 are arranged on the semiconductor layer 114 , and the P electrodes of the LED chips 80 in the LED array 8 are electrically connected through the composite wire layer. Therefore, in the LED array 8 shown in FIG. 8 , the LED chips 80 are connected in parallel with each other.
  • the composite wire layer 81 includes a carbon nanotube interconnection layer 812 and a lower isolation layer 811.
  • the carbon nanotube interconnection layer 812 is a conductor containing carbon nanotube materials and has electrical conductivity. , used to electrically connect the P electrodes in the LED array 8.
  • the carbon nanotube material has good electrical and thermal conductivity. Connect the P electrodes 122 to realize current expansion in the LED array 8, and also help the LED array 8 to dissipate heat, enhance the heat dissipation performance of the LED array 8, prevent the LED array 8 from being in a high temperature environment for a long time, and improve the performance of the LED array 8. quality.
  • the carbon nanotube material can be single-walled carbon nanotubes, double-walled carbon nanotubes or multi-walled carbon nanotubes, and even in some examples, the carbon nanotube interconnection wire layer 812 can be made of two or more types The carbon nanotube materials are jointly formed.
  • the lower isolation layer 811 is used as an insulating layer to electrically isolate the carbon nanotube interconnection wire layer 811 from the epitaxial layer 11 .
  • the lower isolation layer 811 is attached to the surface of the epitaxial layer 11, while the carbon nanotube interconnection wire layer 812 is attached to the lower isolation layer 811, and the isolation of the lower isolation layer 811 can ensure the carbon nanotube interconnection wire
  • the LED chip is an ultraviolet LED chip
  • the LED array is an ultraviolet LED array capable of emitting ultraviolet light.
  • the wavelength of ultraviolet light can be between 320nm-400nm (long-wave ultraviolet, UVA), or between 280nm-320nm (medium-wave ultraviolet, UVB), or between 200nm-280nm (short-wave ultraviolet, ie deep ultraviolet, UVC).
  • UVA long-wave ultraviolet
  • UVB medium-wave ultraviolet
  • UVC short-wave ultraviolet
  • UVC short-wave ultraviolet
  • the LED array 8 is UVB or UVC.
  • the energy radiated to the carbon nanotube material will easily cause the carbon nanotube material to become brittle, thereby affecting the reliability of the carbon nanotube interconnection wire layer 812 and the LED array 8 .
  • the lower isolation layer 811 has the function of reflecting ultraviolet light, and it reflects the ultraviolet light excited by the epitaxial layer 11, thereby preventing the ultraviolet light from irradiating the carbon nanotube interconnection wire layer 812 superior. Therefore, the lower isolation layer 811 in these examples not only has insulating properties, but also blocks ultraviolet light.
  • the material of the lower isolation layer 811 includes but not limited to AlN, PVC (Polyvinyl chloride, polyvinyl chloride) at least one.
  • the "carbon nanotube interconnection wire layer” is actually a wire in the shape of a long and thin line, and the function of the lower isolation layer 811 is mainly to isolate and shield the carbon nanotube interconnection wire layer 812, Therefore, in order to prevent the lower isolation layer 811 from affecting the light output of the LED array 8 , the lower isolation layer 811 is usually in the shape of a thin and long line. Usually, however, the line width of the lower isolation layer 811 is greater than that of the carbon nanotube interconnection wire layer 812 , so that the lower isolation layer 811 can better shield the carbon nanotube interconnection wire layer 812 .
  • the composite wire layer of the LED array also includes an upper isolation layer, please refer to a composite wire layer shown in FIG.
  • the upper isolation layer 813 is arranged on the side of the carbon nanotube interconnection wire layer 812 away from the lower isolation layer 811, that is, the upper isolation layer 813 and the lower isolation layer 811 are respectively arranged on the carbon nanotube interconnection wire
  • the upper isolation layer 813 also has the ability to reflect ultraviolet light, and it and the lower isolation layer 811 can respectively block ultraviolet light from two different directions.
  • the upper isolation layer 813 is also made of insulating material. In some examples of this embodiment, the upper isolation layer 813 is made of the same material as the lower isolation layer 811 .
  • the lower isolation layer 811, the carbon nanotube interconnection wire layer 812 and the upper isolation layer 813 can be used such as PVD (Physical Vapor Deposition, physical vapor deposition), CVD, EV (evaporation), spin In some examples of this embodiment, they are all temporarily formed on the epitaxial layer 11, and in some examples, corresponding structures can be formed at other positions first, and then transferred to the epitaxial layer 11.
  • the routing of the composite wire layer 81 in the LED array can be in various ways, for example, please refer to the schematic diagrams of the routing of the two composite wire layers 81 shown in Figure 10a and Figure 11a, and Figure 10b and Figure 11b The schematic diagrams of equivalent circuit connections corresponding to the two routing methods are shown respectively.
  • the composite wire layer 81 connects the P electrodes 122 of the LED chips in each row together, and connects the P electrodes 122 of the LED chips in the first row together, forming a "comb shape" as a whole.
  • the composite wire layer 81 is respectively connected to the P electrodes 122 of LED chips in each row, it can also be connected to the P electrodes 122 of other columns of LED chips, for example, the rightmost column of LED chips The electrode or the P electrode 122 of the middle row of LED chips. Or, in some other examples, the composite wire layer 81 can be respectively connected to the P electrodes 122 of LED chips in each column, and then selectively connected to the P electrodes 122 of at least one row of LED chips. In the LED array 110 of FIG. 11 a , the composite wire layer 81 includes a plurality of continuous "S"-shaped turns, from left to right, and from the top to connect at least the P electrodes 122 of each LED chip one by one.
  • This embodiment also provides an electronic device, which includes a driving circuit and the LED chip provided in any one of the above examples, the electrodes of the LED chip are electrically connected to the driving circuit, and can work under the driving of the driving circuit.
  • the LED chip is an ultraviolet LED chip or a deep ultraviolet LED chip
  • the electronic equipment can be applied to electronic equipment in the fields of sterilization, polymer curing, biochemical detection, non-line-of-sight communication and special lighting, such as ultraviolet disinfection equipment, UV curing equipment, etc.
  • the LED chip, LED array and electronic equipment provided by this embodiment limit the number of electrons in the N-type semiconductor layer such as the active layer by setting an electron blocking layer between the active layer of the LED chip and the N-type semiconductor layer, thereby Suppresses the carrier overflow phenomenon and improves the light extraction efficiency of the LED chip.
  • the heat dissipation substrate with a thermal expansion coefficient smaller than that of the growth substrate and the epitaxial layer and a thermal conductivity greater than that of the growth substrate and the epitaxial layer on the side of the growth substrate away from the epitaxial layer, compression can be generated in the LED chip.
  • the carbon nanotube interconnection wire layer formed by carbon nanotube material replaces the oxide to interconnect the P electrodes of each LED chip in the LED array, which not only realizes current expansion, but also utilizes carbon
  • the excellent thermal conductivity of the nanotube material dissipates heat from the LED array, thereby avoiding the problem that the LED array is always in a high temperature environment and affecting its performance, improving the reliability of the LED array and electronic equipment, and enhancing the quality of the array and equipment.
  • UV LED Light-Emitting Diode
  • AlGaN material is the core material for making UV LEDs.
  • Al x Ga 1-x N material is a wide bandgap direct bandgap semiconductor material.
  • the energy gap of AlGaN can be continuously changed between 3.4eV and 6.2eV, so that the wavelength Ultraviolet light ranging from 210nm to 365nm.
  • the luminous efficiency of ultraviolet LEDs, especially deep ultraviolet LEDs is generally relatively low, which limits the wide application of ultraviolet LEDs.
  • the main reason for the low luminous efficiency of UV LEDs is its relatively low light extraction efficiency, because P-type GaN has a strong absorption effect on ultraviolet light, causing a large amount of light emitted by the front of the UV LED to be absorbed.
  • a light-emitting element based on nitride or the like radiates light by injecting electrons and holes (electron-hole pairs) into an active layer (active layer) composed of quantum wells or the like so that electrons and holes recombine. At this time, the energy not converted into light is converted into Joule heat, which raises the temperature of the element.
  • this embodiment first provides an ultraviolet LED chip. Please refer to the schematic structural diagram of an ultraviolet LED chip 120 shown in FIG. Layer 125.
  • the epitaxial layer includes an N-type semiconductor layer 1211 , an electron blocking layer 1212 , an active layer 1213 , and a P-type semiconductor layer 1214 sequentially from bottom to top.
  • the electron blocking layer 1212 is made of h-BN with an energy gap of 6.4eV.
  • the growth substrate 123 is disposed on the side of the N-type semiconductor layer 1211 away from the active layer, which may be a GaN growth substrate.
  • the electrodes include an N electrode 1221 and a P electrode 1222.
  • the ultraviolet LED chip 120 is a LED chip with a vertical structure, so the N electrode 1211 is arranged on the side of the growth substrate 123 away from the N-type semiconductor layer 1211, and the P electrode 1222 is arranged On the side of the P-type semiconductor layer 1214 away from the active layer 1213 .
  • the heat dissipation substrate includes a silicon substrate layer 1241 , a carbon nanotube array layer 1242 and a CVD-diamond layer 1243 , and the distances between the three and the growth substrate 123 become smaller in turn.
  • the heat dissipation base material and the growth substrate 123 are metal-bonded with the N electrode 1221 through the metal bonding layer 125 to form a whole.
  • the ultraviolet LED chip 120 provided in this embodiment, by setting an electron blocking layer 1212 made of h-BN material with a band gap of 6.4eV between the N-type semiconductor layer 1211 and the active layer 1213, the self-N The number of electrons injected into the active layer 1213 by the P-type semiconductor layer 1211 can avoid electrons from overflowing into the P-type semiconductor layer 1214, resulting in a decrease in the luminous efficiency of the ultraviolet LED chip.
  • this ultraviolet LED chip 120 by setting the heat dissipation base material comprising CVD-diamond under the growth substrate 123, because the thermal expansion coefficient of the heat dissipation base material is smaller than the thermal expansion coefficient of each layer above it, but the thermal conductivity is greater than that of each layer above it.
  • Thermal conductivity (the thermal conductivity of CVD diamond is 1500W/mK; the thermal conductivity of carbon nanotube material is 3500W/mK, and can reach 6000W/mK in extreme cases), so that compressive strain can be generated in the ultraviolet LED chip 120, so as to alleviate the Since the electron blocking layer 1211 has a lattice constant (2.5 angstroms) smaller than that of the nitride growth substrate 123 (5.2 angstroms), a lattice mismatch strain in the stretching direction is generated inside, thereby suppressing a decrease in effective barrier height.
  • the heat dissipation substrate includes a carbon nanotube array layer 1242 , which has excellent thermal conductivity, can improve the heat dissipation capability of the heat dissipation substrate, and enhance the heat dissipation performance of the ultraviolet LED chip.
  • the setting of the silicon substrate layer 1241 can facilitate subsequent doping of the silicon substrate layer 1241 directly when setting and driving the ultraviolet LED chip, which is beneficial to improving the convenience of setting the driving circuit.
  • AlN ceramics, DC60, SiC (silicon carbide) ceramics, SiC ceramics with high thermal conductivity and other materials with better heat dissipation performance can also be used to replace the carbon nanotube array layer 1242 and/or silicon lining in the heat dissipation substrate Ground floor 1241.
  • This embodiment also provides an ultraviolet LED array, please refer to Figure 13:
  • the ultraviolet LED array 130 includes a plurality of ultraviolet LED chips 120, and these ultraviolet LED chips 120 share an N-type semiconductor layer 1211, a growth substrate 123, an N electrode 1221, and a heat dissipation substrate, but different from the electron blocking layer 1212 of the ultraviolet LED chip 120, there are
  • the source layer 1213, the P-type semiconductor layer 1214, and the P-electrode 1222 are independent from each other.
  • each ultraviolet LED chip 120 is connected in parallel with each other, so the ultraviolet LED array 130 also includes a composite wire layer, and the composite wire layer includes a lower isolation layer 1311, a carbon nanotube interconnection wire layer 1312 and an upper isolation layer 1313 , wherein the lower isolation layer 1311 and the upper isolation layer 1313 are respectively arranged on opposite sides of the carbon nanotube interconnection wire layer 1312, both of which are insulating layers, wherein the lower isolation layer 1311 is used to electrically isolate the carbon nanotube interconnection wire layer 1312 and the epitaxial layer, and the upper isolation layer 1313 can electrically isolate the carbon nanotube interconnection wire layer 1312 from the outside world. At the same time, both of them have the ability to reflect ultraviolet light.
  • the lower isolation layer 1311 and the upper isolation layer 1313 wrap the carbon nanotube interconnection wire layer 1312 in the middle, it can reduce the ultraviolet light emitted by the active layer 1213 from irradiating the carbon nanotubes. tube interconnection wire layer 1312, thereby protecting the carbon nanotube interconnection wire layer 1312, delaying or even avoiding the occurrence of the carbon nanotube interconnection wire layer 1312 being brittle due to the irradiation of ultraviolet light, and improving the ultraviolet light The reliability of the LED chip array 130.
  • both the upper isolation layer 1313 and the lower isolation layer 1311 are made of AlN, in other examples, PVC can be used instead of AlN, and in some examples, the upper isolation layer 1313 and the lower isolation layer
  • the materials of 1311 can be different, for example, one of them is made of AlN, and the other is made of PVC.
  • This embodiment also provides an electronic device, which includes at least one of an ultraviolet LED chip 120 and an ultraviolet LED array 130 , electrodes of the ultraviolet LED chip 120 and the ultraviolet LED array 130 are electrically connected to corresponding driving circuits.
  • the ultraviolet LED product provided in this embodiment suppresses the carrier overflow phenomenon and improves the light output efficiency. At the same time, compression is generated in the ultraviolet LED chip through the selection of the heat dissipation base material so as to cope with the tensile strain in the electron blocking layer, and the reduction of the effective barrier height is suppressed.
  • each P electrode in the ultraviolet LED array is interconnected through the carbon nanotube interconnection wire layer formed by the carbon nanotube material, which not only realizes the current expansion, but also uses the excellent thermal conductivity of the carbon nanotube material to dissipate heat from the LED array, thereby Avoiding the problem that the ultraviolet LED array is always in a high temperature environment, which affects its performance, improves the reliability of the ultraviolet LED array and electronic equipment, and enhances the quality of the array and equipment.

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Abstract

本申请涉及一种LED芯片、LED阵列及电子设备，LED芯片（10）中包括外延层（11）与电极（12）；外延层（11）包括N型半导体层（111）、P型半导体层（114）以及设置在二者之间的有源层（113）；电极（12）包括同N型半导体层（111）电连接的N电极（121）、同P型半导体层（114）电连接的P电极（122）；另外，LED芯片（10）中还包括设置在有源层（112）与N型半导体层（111）之间的电子阻挡层（112）。

Description

LED芯片、LED阵列及电子设备 技术领域
本申请涉及LED技术领域，尤其涉及一种LED芯片、LED阵列及电子设备。
 背景技术
在LED芯片中是由N型半导体层与P型半导体层分别向有源层中注入电子与空穴，让电子与空穴在有源层中复合从而将电能转换成光能，激发出光；同时，未被转换成光能的能量将以热能辐射出来。可以理解的是，辐射出的热能将使得LED芯片温度上升，而高温不仅会影响LED芯片的可靠性，而且会导致一部分载流子（电子与空穴）溢出，产生“光饱和”现象（即光输出不再随着电流量的增加而增大），进而影响LED芯片的发光效率。
因此，如何解决载流子溢出，提升LED芯片的发光效率是目前亟需解决的问题。
 技术问题
鉴于上述相关技术的不足，本申请的目的在于提供一种LED芯片、LED阵列及电子设备，旨在解决载流子溢出影响LED芯片光提取效率的问题。
 技术解决方案
本申请提供一种LED芯片，包括外延层与电极；外延层包括：
N型半导体层；
有源层；
P型半导体层；以及
电子阻挡层；
其中，电极包括同N型半导体层电连接的N电极、同P型半导体层电连接的P电极；有源层与电子阻挡层均位于N型半导体层与P型半导体层之间，且电子阻挡层比有源层距离N型半导体层更近。
上述LED芯片中，有源层与电子阻挡层均位于N型半导体层与P型半导体层之间，且电子阻挡层比有源层距离N型半导体层更近，因此，电子阻挡层设置在有源层与N型半导体层之间，这样可以利用电子阻挡层可以对N型半导体层注入有源层的电子的数量进行限制，抑制载流子溢出，避免光饱和现象，从而提升LED芯片的光输出效率。
基于同样的发明构思，本申请还提供一种LED阵列，LED阵列中包括至少两颗前述任一项中的LED芯片，且各LED芯片的半导体层相互电连接。
上述LED阵列中通过至少两颗LED芯片组合形成LED阵列，提升了LED阵列的发光效率，更重要的是，LED芯片中在有源层与N型半导体层之间设置了电子阻挡层，这样可以利用电子阻挡层可以对N型半导体层注入有源层的电子的数量进行限制，抑制载流子溢出，避免光饱和现象，进一步提升LED阵列的光输出效率。
基于同样的发明构思，本申请还提供一种电子设备，该电子设备中包括驱动电路以及前述任一项中的LED芯片；LED芯片的电极与驱动电路电连接。
上述电子设备内的LED芯片中，在有源层与N型半导体层之间设置了电子阻挡层，这样可以利用电子阻挡层可以对N型半导体层注入有源层的电子的数量进行限制，抑制载流子溢出，避免光饱和现象，进一步提升LED芯片的光输出效率，增强电子设备的品质 。
有益效果
上述LED芯片中，有源层与电子阻挡层均位于N型半导体层与P型半导体层之间，且电子阻挡层比有源层距离N型半导体层更近，因此，电子阻挡层设置在有源层与N型半导体层之间，这样可以利用电子阻挡层可以对N型半导体层注入有源层的电子的数量进行限制，抑制载流子溢出，避免光饱和现象，从而提升LED芯片的光输出效率。
上述LED阵列中通过至少两颗LED芯片组合形成LED阵列，提升了LED阵列的发光效率，更重要的是，LED芯片中在有源层与N型半导体层之间设置了电子阻挡层，这样可以利用电子阻挡层可以对N型半导体层注入有源层的电子的数量进行限制，抑制载流子溢出，避免光饱和现象，进一步提升LED阵列的光输出效率。
上述电子设备内的LED芯片中，在有源层与N型半导体层之间设置了电子阻挡层，这样可以利用电子阻挡层可以对N型半导体层注入有源层的电子的数量进行限制，抑制载流子溢出，避免光饱和现象，进一步提升LED芯片的光输出效率，增强电子设备的品质。
 附图说明
图1为本申请一可选实施例中提供的第一种LED芯片的结构示意图；
图2为本申请一可选实施例中提供的第二种LED芯片的结构示意图；
图3为本申请一可选实施例中提供的第三种LED芯片的结构示意图；
图4为本申请一可选实施例中提供的散热基材的结构示意图；
图5为本申请一可选实施例中提供的第四种LED芯片的结构示意图；
图6为本申请一可选实施例中提供的第五种LED芯片的结构示意图；
图7为本申请一可选实施例中提供的第一种LED阵列的结构示意图；
图8为本申请一可选实施例中提供的第二种LED阵列的结构示意图；
图9为本申请一可选实施例中提供的复合导线层的结构示意图；
图10a为本申请一可选实施例中LED阵列中复合导线层的一种走线示意图；
图10b为图10a中LED阵列的等效电路连接示意图；
图11a为本发明一可选实施例中LED阵列中复合导线层的另一种走线示意图；
图11b为图11a中LED阵列的等效电路连接示意图；
图12为本申请另一可选实施例中提供的一种紫外LED芯片的结构示意图；
图13为本申请另一可选实施例中提供的一种紫外LED阵列的结构示意图。
附图标记说明：
10-LED芯片；11-外延层；111-N型半导体层；112-电子阻挡层；113-有源层；114-P型半导体层；12-电极；121-N电极；122-P电极；13-生长基板；14-散热基材；141-CVD-金刚石层；142-碳纳米管阵列层；143-硅衬底层；15-键合层；20-LED芯片；30-LED芯片；50-LED芯片；60-LED芯片；7-LED阵列；70-LED芯片；8-LED阵列；80-LED芯片；81-复合导线层；811-下隔离层；812-碳纳米管互连导线层；813-上隔离层；100-LED阵列；110-LED阵列；120-紫外LED芯片；1211-N型半导体层；1212-电子阻挡层；1213-有源层；1214-P型半导体层1214；1221-N电极；1222-P电极；123-生长基板；1241-硅衬底层；1242-碳纳米管阵列层；1243-CVD-金刚石层；125-金属键合层；130-紫外LED阵列；1311-下隔离层；1312-碳纳米管互连导线层；1313-上隔离层。
 本发明的实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本申请。
载流子溢出会导致LED芯片产生“光饱和”现象，进而影响LED芯片的发光效率，基于此，本申请希望提供一种能够解决上述技术问题的方案，其详细内容将在后续实施例中得以阐述。
本申请一可选实施例：
本实施例提供一种LED芯片，请参见图1示出的该LED芯片的结构示意图：
LED芯片10包括外延层11与电极12，其中，外延层11包括N型半导体层111、有源层113以及P型半导体层114，有源层113位于N型半导体层111与P型半导体层114之间。N型半导体层111为N型掺杂的半导体层，P型半导体层114为P型掺杂的半导体层，其中，N型掺杂的掺杂源包括但不限于硅源、硼源与锗源中的任意一种；以硅源为例，可以选用SiH 4（甲硅烷）、Si 2H 6（乙硅烷）等作为掺杂源。P型掺杂的掺杂源包括但不限于镁源、锌源中的至少一种，例如以镁源作为掺杂源时，可以选用Cp2Mg（二茂镁）。
电极12包括与N型半导体层111电连接的N电极（图1中并未示出），与P型半导体层114电连接的P电极122。虽然在图1中P电极122直接设置在P型半导体层114上，但本领域技术人员应当明白的是，电极与对应半导体层的电连接并不一定是直接的连接，也可能是通过导体间接连接。
在本实施例中，外延层11还包括电子阻挡层112，电子阻挡层112也位于N型半导体层111与P型半导体层114之间，不过电子阻挡层112比有源层113更靠近N型半导体层111，也即电子阻挡层112距离N型半导体层111的距离，比有源层112距离N型半导体层111的距离更小，换言之，电子阻挡层112设置在有源层113与N型半导体层111之间。
电子阻挡层112用于对N型半导体层111注入有源层113中的电子的数量进行限制，避免有源层113中过多的电子无法与空穴复合从而溢出到P型半导体层114中，减少了电子能量向热能的转换，缓解了LED芯片10的发热问题，有利于提升电能的有效转换率，同时，因为抑制了LED芯片10中的光饱和限向，提高了LED芯片10的出光效率。
可以理解的是，为了对N型半导体层111向有源层113注入的电子进行限制，电子阻挡层112应当具有较大的能隙，在本实施例的一些示例中，电子阻挡层112的带隙介于5.6eV~8.7eV之间，例如，一种示例中电子阻挡层112的带隙为5.6eV（SiN，氮化硅），另一种示例中电子阻挡层的带隙为7.8eV（MgO，氧化镁），还有一种示例中，电子阻挡层112的带隙为6.2eV（AlN，氮化铝），再有一种示例中，电子阻挡层112的带隙为8.7eV（Al 2O 3，三氧化二铝）。
在本实施例的一些示例中，电子阻挡层112可以为超晶格结构层，例如ZnMgO/AlGaN（氧化锌镁/铝镓氮）超晶格结构层、AlN/AlGaN（氮化铝/铝镓氮）超晶格结构层、AlGaN/InGaN（铝镓氮/铟镓氮）超晶格结构层；还有一些示例中，电子阻挡层112也可以由单种材质形成，例如一种示例中电子阻挡层112为AlGaN层。在本实施例中，电子阻挡层112可以包含h-BN（六方氮化硼），h-BN材料的能隙为6.4eV，一种示例中，电子阻挡层112为h-BN层。
h-BN，又称白石墨（white graphite），其与石墨中的六角碳网相似，六方氮化硼中氮和硼也组成六角网状层面，互相重叠，构成晶体。晶体与石墨相似，具有反磁性及很高的异向性，晶体参数两者也颇为相近。
应当明白的是，外延层11并不仅限于N型半导体层111、电子阻挡层112、有源层113以及P型半导体层114这四层，在其他一些示例中，外延层11中还可以包括缓冲层、本征层、欧姆接触层等层结构中的至少一种。
在本实施例的一些示例中，LED芯片还包括生长基板，如图2所示，LED芯片20中包括设置在N型半导体层111远离电子阻挡层112的一侧的生长基板13，例如，在图2当中，生长基板13位于外延层11的下方，该生长基板13可以为氮化物生长基板，例如在一种示例中该生长基板13可以为GaN（氮化镓）生长基板。
在本实施例中，电子阻挡层112的晶格常数通常小于生长基板13的晶格常数，例如，以GaN的C面为例，其晶格常数为5.2埃，而h-BN材料的晶格常数为2.5埃，所以，当电子阻挡层112为h-BN层，生长基板13为GaN生长基板时，电子阻挡层112的晶格常数小于生长基板13的晶格常数，这就会导致在电子阻挡层112内部产生拉伸方向的晶格失配应变，影响外延层11的晶体质量。对此，本实施例中还提供一种LED芯片，如图3所示：
在LED芯片30中，除了外延层11、电极12以及生长基板13之外，还设置有散热基材14，其中，散热基材14设置在生长基板13远离外延层11的一侧，其热膨胀系数小于其上各层结构的热膨胀系数，但其热传导率大于其上各层结构的热传导率，换言之，散热基材14的热膨胀系数小于生长基板13及外延层11的热膨胀系数，且散热基材14的热传导率大于生长基板13及外延层11的热传导率。这种热膨胀系数即热传导率的关系使得LED芯片30中会产生压缩应变，从而通过该压缩应变缓解电子阻挡层112中的拉伸应变，抑制有效的势垒高度的降低。
另外，散热基材14也能帮助其上各层结构进行散热，提升LED芯片30的散热性能，从而缓解载流子溢出的问题。
在本实施例的一些示例中，散热基材14中包括CVD（Chemical Vapor Deposition）-金刚石，因为CVD-金刚石是热传导率（1500W/mK）非常高且热膨胀系数（2.2）小的材料。在本实施例的一种示例中，散热基材14中包括CVD-金刚石层，通过采用CVD-金刚石层可以让LED芯片的各层结构中产生压缩应变，进而缓解电子阻挡层112中的拉伸应变。
在本实施例的一些示例中，散热基材14为复合层结构，例如图4示出的散热基材14中，除了包括CVD-金刚石层141以外，还包括碳纳米管阵列层142，碳纳米管阵列层142位于CVD-金刚石层141远离生长基板13的一侧。碳纳米管（Carbon Nanotube，CNT）又名巴基管，其主要由呈六边形排列的碳原子构成数层到数十层的同轴圆管，是一种具有特殊结构（径向尺寸为纳米量级，轴向尺寸为微米量级，管子两端基本上都封口）的一维量子材料。碳纳米管作为一维纳米材料，重量轻，六边形结构连接完美，具有许多异常的力学、电学和化学性能。而且，碳纳米管具有优良的导热性能，其在常温下的热传导率可达3500W/mK，极限情况下可达6000W/mK。因此在本实施例中采用碳纳米管材料形成碳纳米管阵列层142可以极大地帮助LED芯片进行散热，增强LED芯片的散热性能，避免其长时间处于高温环境中，提升了LED芯片的品质。
碳纳米管材料可以通过诸如电弧放电法、激光烧蚀法、固相热解法、离子或激光溅射法、聚合反应合成、催化裂解法等几种中的任意一种制得。在本实施例中，形成碳纳米管阵列层142的碳纳米管材料的手性指数（n，m），其中，n与m满足n-m=3k(k为整数)的关系。另外，该碳纳米管材料可以为单壁碳纳米管、双壁碳纳米管或者是多壁碳纳米管，甚至还有一些示例中，碳纳米管阵列层142可以由两种或多种类型的碳纳米管材料共同形成。
在本实施例的一些示例中，散热基材14还包括硅衬底层，请参见图5示出的一种LED芯片的结构示意图：LED芯片50中散热基材14中从下至上依次包括硅衬底层143、碳纳米管阵列层142以及CVD-金刚石层141，其中，硅衬底层143距离生长基板13的距离最远。在本实施例中在散热基材14中设置硅衬底层143，可以使得后续在为LED芯片50设置驱动电路的时候直接针对该硅衬底层143进行掺杂，从而简化了LED芯片50驱动电路的设置流程，提升了LED芯片50的市场竞争力。
形成散热基材14的时候，可以先将硅衬底层143与碳纳米管阵列层142结合，形成复合衬底，然后再将复合衬底与CVD-金刚石层141结合。在本实施例的一些示例中在制备复合衬底的时候，可以先提供一硅衬底层143然后再硅衬底层143上通过喷雾热解法、热化学气相沉积法、旋涂法等几种中的任意一种形成碳纳米管阵列层142。以旋涂法为例，可先将制备好的金属性碳纳米管材料分散在分散液中，然后将分散液旋涂至硅衬底层143上，随后将分散液去除即可得到碳纳米管阵列层142与硅衬底层143的复合衬底。
另外，可以理解的是，在本实施例的其他一些示例当中，散热基材14中也可以不包括碳纳米管阵列层142，只设置CVD-金刚石层141与硅衬底层143。还有一些示例中，散热基材14也可以通过其他材质形成，或者是通过CVD、碳纳米管材料、硅材中的至少一种与其他材质进行组合形成。
一些示例中，为了实现散热基材14与生长基板13的键合，LED芯片中还设置有键合层，请参见图6所示：LED芯片60中在散热基材14与生长基板13设置有键合层15，可以理解的是，散热基材14可以采用多种方式与生长基板13键合，例如，在本实施例的一种示例中，散热基材14与生长基板13通过金属键合的方式结合，在这种示例中，键合层15就是金属键合层。一些示例中，LED芯片60为垂直结构，因此，其P电极122与N电极121分别设置在外延层11相对的两侧，例如，在图6中，P电极122设置在P型半导体层114远离有源层113的一侧，而N电极121则设置在生长基板13远离外延层11的一面上，在这种情况下，N电极121与N型半导体层111通过生长基板13间接连接。因为N电极121为金属电极层，因此，只要在散热基材14朝向生长基板13的一侧也设置一金属键合层，就能使得该金属键合层与N电极121进行金属键合，从而将散热基材14与生长基板13结合在一起。当然，本领域技术人员可以理解的是，如果LED芯片本身不是垂直结构，例如LED芯片为倒装LED芯片，其N电极设置在N型半导体层朝向有源层的一面上，也可以直接在生长基板13朝向散热基材14的一侧上设置另一金属键合层，从而通过两个金属键合层实现生长基板13与散热基材14的结合。
在本实施例的另外一些示例中，生长基板13与散热基材14可以共晶键合，在这种情况下，键合层15为共晶键合层，该共晶键合层中包括两个材质相同的共晶键合子层，例如AuSn（金锡共晶/金锡合金）焊料所形成的共晶键合子层（可以理解的是，共晶键合子层的材质包括但不限于AuSn）。在未将生长基本13与散热基材14结合之前，两个共晶键合子层分别设置在生长基板13上、散热基材14上，且二者相对，当需要键合生长基板13与散热基材14时，可以将两个共晶键合子层键合在一起，让二者相互重叠，结合形成共晶键合层，从而实现生长基板13与散热基材14的键合。
本实施例还提供一种LED阵列，该LED阵列中包括至少两颗LED芯片，LED芯片可以为前述示例中的任意一种LED芯片。在该LED阵列中，各LED芯片的半导体层（N型半导体层111、P型半导体层114）相互电连接，即一颗LED芯片的半导体层与另一颗LED芯片的半导体层电连接。例如，一颗LED芯片的N型半导体层与另一颗LED芯片的N型半导体层电连接；或者，一颗LED芯片的P型半导体层与另一颗LED芯片的P型半导体层电连接；又或者，一颗LED芯片的N型半导体层与另一颗LED芯片的P型半导体层电连接；又一些示例提供的LED阵列中，一颗LED芯片的N型半导体层可以与另一颗LED芯片的N型半导体层电连接，同时其P型半导体层也可与该另一颗LED芯片的N型半导体层电连接。通过将LED芯片组合成LED阵列，提升了发光效率。
应当明白的是，不同LED芯片的半导体层电连接，可以是半导体层的直接电连接，也可以是间接地电连接，例如，在图7所示出的LED阵列7当中，各LED芯片70共N型半导体层111，这样就相当于是各LED芯片70的N型半导体层111直接电连接；一些示例中，各LED芯片的电极通过互连导线电连接，这就相当于是各LED芯片的半导体层间接电连接。还有一些示例中，请参见图8示出的LED阵列8，各LED芯片80共N型半导体层111，但电子阻挡层112、有源层113与P型半导体层114相互独立，在P型半导体层114上设置有P电极122，LED阵列8中各LED芯片80的P电极通过复合导线层实现电连接。所以，在图8示出的LED阵列8中，各LED芯片80相互并联。当然，本领域技术人员可以理解的是，在其他一些示例示出的LED阵列中，LED芯片间可以为其他电连接关系。
继续以图8为例进行说明：复合导线层81包括碳纳米管互连导线层812以及下隔离层811，顾名思义，碳纳米管互连导线层812是包含碳纳米管材料的导体，具有导电性能，用于电连接LED阵列8中各P电极，根据前面的介绍可知，碳纳米管材料导电、导热性能良好，因此，采用包含碳纳米管互连导线层812的复合导线层不仅可以可靠地电连接各P电极122，在LED阵列8中实现电流扩展，而且还能帮助LED阵列8进行散热，增强LED阵列8的散热性能，避免LED阵列8长时间处于高温环境中，提升了LED阵列8的品质。
在本实施例中，碳纳米管互连导线层812中碳纳米管材料的手性指数为（n，m），其中，n与m满足n-m=3k(k为整数)的关系。另外，碳纳米管材料可以为单壁碳纳米管、双壁碳纳米管或者是多壁碳纳米管，甚至还有一些示例中，碳纳米管互连导线层812可以由两种或多种类型的碳纳米管材料共同形成。
下隔离层811则作为绝缘层电气隔离碳纳米管互连导线层811与外延层11。在图8中，下隔离层811附着在外延层11的表面，而碳纳米管互连导线层812则附着在下隔离层811上，通过下隔离层811的隔离，可以保障碳纳米管互连导线层812与外延层11的电气性能。
在本实施例的一些示例中，LED芯片为紫外LED芯片，LED阵列为紫外LED阵列，其能够发出紫外光。紫外光的波长可以介于320nm-400nm之间（长波紫外，UVA），也可以介于280nm-320nm之间（中波紫外，UVB），还可以介于200nm-280nm之间（短波紫外，即深紫外，UVC）。一些示例中，当该LED阵列8所辐射之紫外光为UVB或UVC时。其所具有的能量辐射至碳纳米管材料上后容易导致碳纳米管材料变脆，进而影响碳纳米管互连导线层812与LED阵列8的可靠性。所以，在本实施例的一些示例中，下隔离层811具有反射紫外光的功能，其通过对外延层11激发出的紫外光进行反射，从而避免紫外光照射到碳纳米管互连导线层812上。因此，这些示例中的下隔离层811不仅具有绝缘性质，而且还能阻挡紫外光。在一些示例中下隔离层811的材质包括但不限于AlN、PVC（Polyvinyl chloride，聚氯乙烯）中的至少一种。
可以理解的是，“碳纳米管互连导线层”实际上是一种导线，其形状是细长的线条状，而下隔离层811的作用主要是隔离遮挡碳纳米管互连导线层812，因此，为了避免下隔离层811影响LED阵列8的出光，下隔离层811也通常是细长的线条状。不过通常情况下，下隔离层811的线宽大于碳纳米管互连导线层812的线宽，这样可以让下隔离层811更好地遮挡碳纳米管互连导线层812。
由于下隔离层811并不会对外延层进行全包覆，所以，未被下隔离层811覆盖的外延层11的其他区域还是会有紫外光射出，这些区域的紫外光也能照射到碳纳米管互连导线层812上，为了进一步保护碳纳米管互连导线层812，在本实施例的一些示例，LED阵列的复合导线层还包括上隔离层，请参见图9示出的一种复合导线层81的剖面示意图：上隔离层813设置在碳纳米管互连导线层812远离下隔离层811的一面上，也即上隔离层813与下隔离层811分别设置在碳纳米管互连导线层812相对的两面上，上隔离层813也具有反射紫外光的能力，其与下隔离层811可以分别从两个不同方向阻挡紫外光。通常情况下，上隔离层813也是绝缘材料制成的，在本实施例的一些示例中，上隔离层813与下隔离层811的材质相同。
可以理解的是，下隔离层811、碳纳米管互连导线层812以及上隔离层813中的至少一个可以采用诸如PVD（Physical Vapour Deposition，物理气相沉积）、CVD、EV（蒸镀）、旋涂等方式中的任意一种设置形成，在本实施例的一些示例中，均是临时在外延层11上形成的，还有一些示例中，可以先在其他位置形成对应的更结构，然后转移到外延层11上。
可以理解的是，复合导线层81在LED阵列中的走线可以由多种，例如，请参见图10a与图11a中示出的两种复合导线层81的走线示意图，图10b与图11b则分别示出了这两种走线方式对应的等效电路连接示意图。在图10a示出的LED阵列100当中，复合导线层81将各行LED芯片的P电极122连接在一起，并将第一列的LED芯片的P电极122连接在一起，整体呈“梳子状”。可以理解的是，在其他一些走线方式中，复合导线层81在分别连接各行LED芯片的P电极122的同时，也可以选择连通其他列LED芯片的P电极122，例如最右侧一列LED芯片的电极或者是中间一列LED芯片的P电极122。或者，在其他一些示例中，复合导线层81可以分别连通各列LED芯片的P电极122，然后再选择将至少一行LED芯片的P电极122连通。在图11a的LED阵列110当中，复合导线层81包含多个连续的“S”形拐弯，从左至右，从上至少逐个连通各LED芯片的P电极122。
本实施例还提供一种电子设备，该电子设备中包括驱动电路以及上述任意一种示例中提供的LED芯片，LED芯片的电极与驱动电路电连接，可在驱动电路的驱动下进行工作。例如，当LED芯片为紫外LED芯片或者深紫外LED芯片时，该电子设备可以应用于杀菌消毒、聚合物固化、生化探测、非视距通讯及特种照明等领域的电子设备，例如紫外消毒设备、紫外固化设备等。
本实施例提供的LED芯片、LED阵列以及电子设备，一方面通过在LED芯片的有源层与N型半导体层之间设置电子阻挡层，限制N型半导体层诸如有源层的电子数量，从而抑制载流子溢出现象，提升LED芯片的出光效率。另一方面，通过在生长基板远离外延层的一侧设置热膨胀系数小于生长基板及外延层的热膨胀系数，热传导率大于生长基板及外延层的热膨胀率的散热基材，可以在LED芯片中产生压缩应变，从而缓和因电子阻挡层与生长基板晶格常数相差大而在电子阻挡层中产生的拉伸应变，抑制有效的势垒高度的降低。除此以外，在LED阵列中还通过碳纳米管材料形成的碳纳米管互连导线层代替氧化物来互连LED阵列中各LED芯片的P电极，不仅实现了电流扩展，而且还能利用碳纳米管材料优良的导热性能对LED阵列进行散热，从而避免LED阵列总是处于高温环境下，影响其性能的问题，提高了LED阵列与电子设备的可靠性，增强了阵列与设备的品质。
本申请另一可选实施例：
基于三族氮化物（III-nitride）宽禁带半导体材料的紫外发光二极管（Ultraviolet Light-Emitting Diode，UV LED）在杀菌消毒、聚合物固化、生化探测、非视距通讯及特种照明等领域有着广阔的应用前景。相比于传统紫外光源汞灯，紫外LED有着无汞环保、小巧便携、低功耗、低电压等许多优势，近年来受到越来越多的关注和重视。
AlGaN材料是制备紫外LED的核心材料。Al xGa 1-xN材料是宽禁带直接带隙半导体材料，通过调节三元化合物AlGaN中的Al组分，可以使得AlGaN的能隙在3.4eV～6.2eV之间连续变化，从而获得波长范围从210nm~365nm的紫外光。然而，目前紫外LED，尤其是深紫外LED的发光效率普遍比较低，限制了紫外LED的广泛应用。
造成紫外LED发光效率偏低的主要原因为其光提取效率比较低，因为P型GaN对紫外光具有强吸收作用，造成紫外LED的正面发出的光被大量吸收。同时，基于氮化物等的发光元件通过向由量子阱等构成的活性层（有源层）注入电子和空穴(电子空穴对)，使得电子与空穴复合来辐射光。此时，未被变换成光的能量将转换成为焦耳热，使元件的温度上升。为了使氮化物半导体发光元件高输出化，需要增大所注入的电流，但电流的增加会使氮化物半导体发光元件的发热也同步增大。并且，元件温度上升会产生电子或空穴的一部分未注入活性层而溢出的现象，即载流子溢出现象。这种情况下，即使继续增加电流光输出也不会再增大，最终产生光输出饱和的现象。因此，为了得到高的光输出，需要抑制元件温度的上升并抑制载流子的溢出。
对此，本实施例首先提供一种紫外LED芯片，请参见图12示出的紫外LED芯片120的结构示意图：紫外LED芯片120包括外延层、电极、生长基板123、散热基材、金属键合层125。
其中，外延层从下至上依次包括N型半导体层1211、电子阻挡层1212、有源层1213、P型半导体层1214。其中电子阻挡层1212的材质为能隙6.4eV的h-BN。
生长基板123设置在N型半导体层1211远离有源层的一侧，其可以为GaN生长基板。
电极包括N电极1221、P电极1222，在本实施例中，紫外LED芯片120为垂直结构的LED芯片，因此N电极1211设置在生长基板123远离N型半导体层1211的一面上，P电极1222设置在P型半导体层1214远离有源层1213的一面上。
散热基材包括硅衬底层1241、碳纳米管阵列层1242以及CVD-金刚石层1243，且三者距离生长基板123的距离依次变小。散热基材与生长基板123通过金属键合层125与N电极1221金属键合为一个整体。
在本实施例中提供的紫外LED芯片120，通过在N型半导体层1211与有源层1213之间设置带隙在6.4eV的由h-BN材料制成的电子阻挡层1212，可控制自N型半导体层1211注入有源层1213的电子数量，从而可避免电子溢出至P型半导体层1214中，造成紫外LED芯片发光效率降低的问题。
同时，该紫外LED芯片120中，通过在生长基板123下设置包括CVD-金刚石的散热基材，因为散热基材的热膨胀系数小于其上各层的热膨胀系数，但热传导率大于其上各层的热传导率（CVD金刚石的热传导率为1500W/mK；碳纳米管材料的热传导率3500W/mK，极限情况下可达6000W/mK），这样可以在紫外LED芯片120中产生压缩应变，以此缓解因电子阻挡层1211因晶格常数（2.5埃）小于氮化物生长基板123的晶格常数（5.2埃）而在内部产生拉伸方向的晶格失配应变，抑制有效的势垒高度的降低。
另外，在散热基材中包括有碳纳米管阵列层1242，其导热性能优良，可以提升散热基材的散热能力，增强紫外LED芯片的散热性能。硅衬底层1241的设置可以方便后续在对紫外LED芯片设置驱动的时候直接对硅衬底层1241进行掺杂，有利于提升驱动电路设置的便捷性。一些示例中，也可以采用AlN陶瓷、DC60、SiC（碳化硅）陶瓷、高热传导SiC陶瓷等几种具有较好散热性能的材料代替散热基材中的碳纳米管阵列层1242和/或硅衬底层1241。
本实施例还提供一种紫外LED阵列，请参见图13：
紫外LED阵列130包括多颗紫外LED芯片120，且这些紫外LED芯片120共N型半导体层1211、生长基板123、N电极1221以及散热基材，但不同紫外LED芯片120的电子阻挡层1212、有源层1213以及P型半导体层1214、P电极1222相互独立。
在紫外LED阵列130中，各紫外LED芯片120相互并联，因此紫外LED阵列130中还包括复合导线层，该复合导线层包括下隔离层1311、碳纳米管互连导线层1312以及上隔离层1313，其中，下隔离层1311与上隔离层1313分别设置在碳纳米管互连导线层1312相对的两侧，二者均为绝缘层，其中下隔离层1311用于电气隔离碳纳米管互连导线层1312与外延层，而上隔离层1313能够电气隔离碳纳米管互连导线层1312与外界。同时二者均具有反射紫外光的能力，由于下隔离层1311与上隔离层1313将碳纳米管互连导线层1312包覆在中间，可以减少有源层1213所射出的紫外光照射到碳纳米管互连导线层1312上的概率，从而对碳纳米管互连导线层1312进行保护，延缓甚至是避免碳纳米管互连导线层1312因紫外光的照射而变脆的情况的发生，提升紫外LED芯片阵列130的可靠性。在本实施例的一种示例中，上隔离层1313与下隔离层1311均为AlN材质，在另一些示例中，可以采用PVC代替AlN，还有一些示例中，上隔离层1313与下隔离层1311的材质可以不相同，例如其中一个为AlN材质，另一个PVC材质。
本实施例还提供一种电子设备，该电子设备中包括紫外LED芯片120与紫外LED阵列130中的至少一种，紫外LED芯片120、紫外LED阵列130的电极与对应的驱动电路电连接。
本实施例提供的紫外LED产品，抑制了载流子溢出现象，提升了光输出效率。同时，通过散热基材的选取在紫外LED芯片中产生压缩以便以应对电子阻挡层中的拉伸应变，抑制有效的势垒高度的降低。同时通过碳纳米管材料形成的碳纳米管互连导线层互连紫外LED阵列中各P电极，不仅实现了电流扩展，而且还能利用碳纳米管材料优良的导热性能对LED阵列进行散热，从而避免紫外LED阵列总是处于高温环境下，影响其性能的问题，提高了紫外LED阵列与电子设备的可靠性，增强了阵列与设备的品质。
应当理解的是，本申请的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本申请所附权利要求的保护范围。

Claims (18)

  1. 一种LED芯片，包括外延层与电极；所述外延层包括：
    N型半导体层；
    有源层；
    P型半导体层；以及
    电子阻挡层；
    其中，所述电极包括同所述N型半导体层电连接的N电极、同所述P型半导体层电连接的P电极；所述有源层与所述电子阻挡层均位于所述N型半导体层与所述P型半导体层之间，且所述电子阻挡层比所述有源层距离所述N型半导体层更近。
  2. 如权利要求1所述的LED芯片，其中，所述电子阻挡层的带隙介于5.6eV~8.7eV之间。
  3. 如权利要求2所述的LED芯片，其中，所述电子阻挡层包括六方氮化硼。
  4. 如权利要求1-3任一项所述的LED芯片，其中，所述LED芯片还包括生长基板，所述生长基板位于所述N型半导体层远离所述电子阻挡层的一侧。
  5. 如权利要求4所述的LED芯片，其中，所述LED芯片还包括散热基材，所述散热基材位于所述生长基板远离所述外延层的一侧；所述生长基板的晶格常数大于所述电子阻挡层的晶格常数，所述散热基材的热膨胀系数小于所述生长基板及所述外延层的热膨胀系数，且所述散热基材的热传导率大于所述生长基板及所述外延层的热传导率。
  6. 如权利要求5所述的LED芯片，其中，所述散热基材包括CVD-金刚石层。
  7. 如权利要求6所述的LED芯片，其中，所述散热基材还包括碳纳米管阵列层，所述碳纳米管阵列层位于所述CVD-金刚石层远离所述生长基板的一侧。
  8. 如权利要求7所述的LED芯片，其中，所述散热基材还包括硅衬底层，所述硅衬底层位于所述碳纳米管阵列层远离所述生长基板的一侧。
  9. 如权利要求5所述的LED芯片，其中，所述N电极为设置在所述生长基板远离所述外延层的一面上的金属层；所述散热基材包括金属键合层，所述散热基材通过所述金属键合层与所述N电极键合。
  10. 如权利要求5所述的LED芯片，其中，所述LED芯片还包括共晶键合层，所述共晶键合层包括两个材质相同且重叠设置的共晶键合子层，所述共晶键合层介于所述生长基板与所述散热基材之间。
  11. 一种LED阵列，所述LED阵列中包括至少两颗如权利要求1-10任一项所述的LED芯片，且各所述LED芯片的半导体层相互电连接。
  12. 如权利要求11所述的紫外LED阵列，其特征在于，所述LED阵列中各所述LED芯片共N型半导体层。
  13. 如权利要求11或12所述的LED阵列，其中，所述LED阵列还包括复合导线层，所述复合导线层被配置为电连接各所述LED芯片的P电极。
  14. 如权利要求13所述的LED阵列，其中，所述复合导线层包括下隔离层与碳纳米管互连导线层，所述碳纳米管互连导线层被配置为电连接各所述LED芯片的P电极；所述下隔离层被配置为电气隔离所述碳纳米管互连导线层与所述外延层。
  15. 如权利要求14所述的LED阵列，其中，所述LED芯片为紫外LED芯片，所述下隔离层还被配置为反射所述外延层发出的紫外光，以阻挡所述紫外光照射到所述碳纳米管互连导线层上。
  16. 如权利要求15所述的LED阵列，其中，所述下隔离层包括氮化铝、聚氯乙烯中的至少一种。
  17. 如权利要求14所述的LED阵列，其中，所述复合导线层还包括上隔离层，所述上隔离层设置在所述碳纳米管互连导线层远离所述下隔离层的一侧，所述上隔离层被配置为反射所述外延层发出的紫外光，以阻挡所述紫外光照射到所述碳纳米管互连导线层上。
  18. 一种电子设备，所述电子设备中包括驱动电路以及如权利要求1-10任一项所述的LED芯片；所述LED芯片的电极与所述驱动电路电连接。
     
PCT/CN2021/104545 2021-07-05 2021-07-05 Led芯片、led阵列及电子设备 WO2023279241A1 (zh)

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